4 * Copyright (C) Cavium networks Ltd. 2016.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
10 * * Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * * Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in
14 * the documentation and/or other materials provided with the
16 * * Neither the name of Cavium networks nor the names of its
17 * contributors may be used to endorse or promote products derived
18 * from this software without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
21 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
22 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
23 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
24 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
25 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
26 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
30 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
42 #include <netinet/in.h>
43 #include <sys/queue.h>
44 #include <sys/timerfd.h>
46 #include <rte_alarm.h>
47 #include <rte_atomic.h>
48 #include <rte_branch_prediction.h>
49 #include <rte_byteorder.h>
50 #include <rte_common.h>
51 #include <rte_cycles.h>
52 #include <rte_debug.h>
55 #include <rte_ether.h>
56 #include <rte_ethdev.h>
57 #include <rte_interrupts.h>
59 #include <rte_memory.h>
60 #include <rte_memzone.h>
61 #include <rte_malloc.h>
62 #include <rte_random.h>
64 #include <rte_tailq.h>
66 #include "base/nicvf_plat.h"
68 #include "nicvf_ethdev.h"
70 #include "nicvf_logs.h"
73 nicvf_atomic_write_link_status(struct rte_eth_dev *dev,
74 struct rte_eth_link *link)
76 struct rte_eth_link *dst = &dev->data->dev_link;
77 struct rte_eth_link *src = link;
79 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
80 *(uint64_t *)src) == 0)
87 nicvf_set_eth_link_status(struct nicvf *nic, struct rte_eth_link *link)
89 link->link_status = nic->link_up;
90 link->link_duplex = ETH_LINK_AUTONEG;
91 if (nic->duplex == NICVF_HALF_DUPLEX)
92 link->link_duplex = ETH_LINK_HALF_DUPLEX;
93 else if (nic->duplex == NICVF_FULL_DUPLEX)
94 link->link_duplex = ETH_LINK_FULL_DUPLEX;
95 link->link_speed = nic->speed;
96 link->link_autoneg = ETH_LINK_SPEED_AUTONEG;
100 nicvf_interrupt(void *arg)
102 struct nicvf *nic = arg;
104 if (nicvf_reg_poll_interrupts(nic) == NIC_MBOX_MSG_BGX_LINK_CHANGE) {
105 if (nic->eth_dev->data->dev_conf.intr_conf.lsc)
106 nicvf_set_eth_link_status(nic,
107 &nic->eth_dev->data->dev_link);
108 _rte_eth_dev_callback_process(nic->eth_dev,
109 RTE_ETH_EVENT_INTR_LSC);
112 rte_eal_alarm_set(NICVF_INTR_POLL_INTERVAL_MS * 1000,
113 nicvf_interrupt, nic);
117 nicvf_periodic_alarm_start(struct nicvf *nic)
119 return rte_eal_alarm_set(NICVF_INTR_POLL_INTERVAL_MS * 1000,
120 nicvf_interrupt, nic);
124 nicvf_periodic_alarm_stop(struct nicvf *nic)
126 return rte_eal_alarm_cancel(nicvf_interrupt, nic);
130 * Return 0 means link status changed, -1 means not changed
133 nicvf_dev_link_update(struct rte_eth_dev *dev,
134 int wait_to_complete __rte_unused)
136 struct rte_eth_link link;
137 struct nicvf *nic = nicvf_pmd_priv(dev);
139 PMD_INIT_FUNC_TRACE();
141 memset(&link, 0, sizeof(link));
142 nicvf_set_eth_link_status(nic, &link);
143 return nicvf_atomic_write_link_status(dev, &link);
147 nicvf_dev_get_reg_length(struct rte_eth_dev *dev __rte_unused)
149 return nicvf_reg_get_count();
153 nicvf_dev_get_regs(struct rte_eth_dev *dev, struct rte_dev_reg_info *regs)
155 uint64_t *data = regs->data;
156 struct nicvf *nic = nicvf_pmd_priv(dev);
161 /* Support only full register dump */
162 if ((regs->length == 0) ||
163 (regs->length == (uint32_t)nicvf_reg_get_count())) {
164 regs->version = nic->vendor_id << 16 | nic->device_id;
165 nicvf_reg_dump(nic, data);
172 nicvf_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
174 struct nicvf *nic = nicvf_pmd_priv(dev);
176 PMD_INIT_FUNC_TRACE();
178 dev_info->min_rx_bufsize = ETHER_MIN_MTU;
179 dev_info->max_rx_pktlen = NIC_HW_MAX_FRS;
180 dev_info->max_rx_queues = (uint16_t)MAX_RCV_QUEUES_PER_QS;
181 dev_info->max_tx_queues = (uint16_t)MAX_SND_QUEUES_PER_QS;
182 dev_info->max_mac_addrs = 1;
183 dev_info->max_vfs = dev->pci_dev->max_vfs;
185 dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP;
186 dev_info->tx_offload_capa =
187 DEV_TX_OFFLOAD_IPV4_CKSUM |
188 DEV_TX_OFFLOAD_UDP_CKSUM |
189 DEV_TX_OFFLOAD_TCP_CKSUM |
190 DEV_TX_OFFLOAD_TCP_TSO |
191 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM;
193 dev_info->reta_size = nic->rss_info.rss_size;
194 dev_info->hash_key_size = RSS_HASH_KEY_BYTE_SIZE;
195 dev_info->flow_type_rss_offloads = NICVF_RSS_OFFLOAD_PASS1;
196 if (nicvf_hw_cap(nic) & NICVF_CAP_TUNNEL_PARSING)
197 dev_info->flow_type_rss_offloads |= NICVF_RSS_OFFLOAD_TUNNEL;
199 dev_info->default_rxconf = (struct rte_eth_rxconf) {
200 .rx_free_thresh = NICVF_DEFAULT_RX_FREE_THRESH,
204 dev_info->default_txconf = (struct rte_eth_txconf) {
205 .tx_free_thresh = NICVF_DEFAULT_TX_FREE_THRESH,
207 ETH_TXQ_FLAGS_NOMULTSEGS |
208 ETH_TXQ_FLAGS_NOREFCOUNT |
209 ETH_TXQ_FLAGS_NOMULTMEMP |
210 ETH_TXQ_FLAGS_NOVLANOFFL |
211 ETH_TXQ_FLAGS_NOXSUMSCTP,
216 nicvf_dev_configure(struct rte_eth_dev *dev)
218 struct rte_eth_conf *conf = &dev->data->dev_conf;
219 struct rte_eth_rxmode *rxmode = &conf->rxmode;
220 struct rte_eth_txmode *txmode = &conf->txmode;
221 struct nicvf *nic = nicvf_pmd_priv(dev);
223 PMD_INIT_FUNC_TRACE();
225 if (!rte_eal_has_hugepages()) {
226 PMD_INIT_LOG(INFO, "Huge page is not configured");
230 if (txmode->mq_mode) {
231 PMD_INIT_LOG(INFO, "Tx mq_mode DCB or VMDq not supported");
235 if (rxmode->mq_mode != ETH_MQ_RX_NONE &&
236 rxmode->mq_mode != ETH_MQ_RX_RSS) {
237 PMD_INIT_LOG(INFO, "Unsupported rx qmode %d", rxmode->mq_mode);
241 if (!rxmode->hw_strip_crc) {
242 PMD_INIT_LOG(NOTICE, "Can't disable hw crc strip");
243 rxmode->hw_strip_crc = 1;
246 if (rxmode->hw_ip_checksum) {
247 PMD_INIT_LOG(NOTICE, "Rxcksum not supported");
248 rxmode->hw_ip_checksum = 0;
251 if (rxmode->split_hdr_size) {
252 PMD_INIT_LOG(INFO, "Rxmode does not support split header");
256 if (rxmode->hw_vlan_filter) {
257 PMD_INIT_LOG(INFO, "VLAN filter not supported");
261 if (rxmode->hw_vlan_extend) {
262 PMD_INIT_LOG(INFO, "VLAN extended not supported");
266 if (rxmode->enable_lro) {
267 PMD_INIT_LOG(INFO, "LRO not supported");
271 if (conf->link_speeds & ETH_LINK_SPEED_FIXED) {
272 PMD_INIT_LOG(INFO, "Setting link speed/duplex not supported");
276 if (conf->dcb_capability_en) {
277 PMD_INIT_LOG(INFO, "DCB enable not supported");
281 if (conf->fdir_conf.mode != RTE_FDIR_MODE_NONE) {
282 PMD_INIT_LOG(INFO, "Flow director not supported");
286 PMD_INIT_LOG(DEBUG, "Configured ethdev port%d hwcap=0x%" PRIx64,
287 dev->data->port_id, nicvf_hw_cap(nic));
292 /* Initialize and register driver with DPDK Application */
293 static const struct eth_dev_ops nicvf_eth_dev_ops = {
294 .dev_configure = nicvf_dev_configure,
295 .link_update = nicvf_dev_link_update,
296 .dev_infos_get = nicvf_dev_info_get,
297 .get_reg_length = nicvf_dev_get_reg_length,
298 .get_reg = nicvf_dev_get_regs,
302 nicvf_eth_dev_init(struct rte_eth_dev *eth_dev)
305 struct rte_pci_device *pci_dev;
306 struct nicvf *nic = nicvf_pmd_priv(eth_dev);
308 PMD_INIT_FUNC_TRACE();
310 eth_dev->dev_ops = &nicvf_eth_dev_ops;
312 pci_dev = eth_dev->pci_dev;
313 rte_eth_copy_pci_info(eth_dev, pci_dev);
315 nic->device_id = pci_dev->id.device_id;
316 nic->vendor_id = pci_dev->id.vendor_id;
317 nic->subsystem_device_id = pci_dev->id.subsystem_device_id;
318 nic->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
319 nic->eth_dev = eth_dev;
321 PMD_INIT_LOG(DEBUG, "nicvf: device (%x:%x) %u:%u:%u:%u",
322 pci_dev->id.vendor_id, pci_dev->id.device_id,
323 pci_dev->addr.domain, pci_dev->addr.bus,
324 pci_dev->addr.devid, pci_dev->addr.function);
326 nic->reg_base = (uintptr_t)pci_dev->mem_resource[0].addr;
327 if (!nic->reg_base) {
328 PMD_INIT_LOG(ERR, "Failed to map BAR0");
333 nicvf_disable_all_interrupts(nic);
335 ret = nicvf_periodic_alarm_start(nic);
337 PMD_INIT_LOG(ERR, "Failed to start period alarm");
341 ret = nicvf_mbox_check_pf_ready(nic);
343 PMD_INIT_LOG(ERR, "Failed to get ready message from PF");
347 "node=%d vf=%d mode=%s sqs=%s loopback_supported=%s",
348 nic->node, nic->vf_id,
349 nic->tns_mode == NIC_TNS_MODE ? "tns" : "tns-bypass",
350 nic->sqs_mode ? "true" : "false",
351 nic->loopback_supported ? "true" : "false"
356 PMD_INIT_LOG(INFO, "Unsupported SQS VF detected, Detaching...");
357 /* Detach port by returning Positive error number */
362 eth_dev->data->mac_addrs = rte_zmalloc("mac_addr", ETHER_ADDR_LEN, 0);
363 if (eth_dev->data->mac_addrs == NULL) {
364 PMD_INIT_LOG(ERR, "Failed to allocate memory for mac addr");
368 if (is_zero_ether_addr((struct ether_addr *)nic->mac_addr))
369 eth_random_addr(&nic->mac_addr[0]);
371 ether_addr_copy((struct ether_addr *)nic->mac_addr,
372 ð_dev->data->mac_addrs[0]);
374 ret = nicvf_mbox_set_mac_addr(nic, nic->mac_addr);
376 PMD_INIT_LOG(ERR, "Failed to set mac addr");
380 ret = nicvf_base_init(nic);
382 PMD_INIT_LOG(ERR, "Failed to execute nicvf_base_init");
386 ret = nicvf_mbox_get_rss_size(nic);
388 PMD_INIT_LOG(ERR, "Failed to get rss table size");
392 PMD_INIT_LOG(INFO, "Port %d (%x:%x) mac=%02x:%02x:%02x:%02x:%02x:%02x",
393 eth_dev->data->port_id, nic->vendor_id, nic->device_id,
394 nic->mac_addr[0], nic->mac_addr[1], nic->mac_addr[2],
395 nic->mac_addr[3], nic->mac_addr[4], nic->mac_addr[5]);
400 rte_free(eth_dev->data->mac_addrs);
402 nicvf_periodic_alarm_stop(nic);
407 static const struct rte_pci_id pci_id_nicvf_map[] = {
409 .class_id = RTE_CLASS_ANY_ID,
410 .vendor_id = PCI_VENDOR_ID_CAVIUM,
411 .device_id = PCI_DEVICE_ID_THUNDERX_PASS1_NICVF,
412 .subsystem_vendor_id = PCI_VENDOR_ID_CAVIUM,
413 .subsystem_device_id = PCI_SUB_DEVICE_ID_THUNDERX_PASS1_NICVF,
416 .class_id = RTE_CLASS_ANY_ID,
417 .vendor_id = PCI_VENDOR_ID_CAVIUM,
418 .device_id = PCI_DEVICE_ID_THUNDERX_PASS2_NICVF,
419 .subsystem_vendor_id = PCI_VENDOR_ID_CAVIUM,
420 .subsystem_device_id = PCI_SUB_DEVICE_ID_THUNDERX_PASS2_NICVF,
427 static struct eth_driver rte_nicvf_pmd = {
429 .name = "rte_nicvf_pmd",
430 .id_table = pci_id_nicvf_map,
431 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
433 .eth_dev_init = nicvf_eth_dev_init,
434 .dev_private_size = sizeof(struct nicvf),
438 rte_nicvf_pmd_init(const char *name __rte_unused, const char *para __rte_unused)
440 PMD_INIT_FUNC_TRACE();
441 PMD_INIT_LOG(INFO, "librte_pmd_thunderx nicvf version %s",
442 THUNDERX_NICVF_PMD_VERSION);
444 rte_eth_driver_register(&rte_nicvf_pmd);
448 static struct rte_driver rte_nicvf_driver = {
449 .name = "nicvf_driver",
451 .init = rte_nicvf_pmd_init,
454 PMD_REGISTER_DRIVER(rte_nicvf_driver);