1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2015-2020 Beijing WangXun Technology Co., Ltd.
3 * Copyright(c) 2010-2017 Intel Corporation
6 #include "txgbe_type.h"
9 #include "txgbe_dcb_hw.h"
12 * txgbe_pfc_enable - Enable flow control
13 * @hw: pointer to hardware structure
14 * @tc_num: traffic class number
15 * Enable flow control according to the current settings.
18 txgbe_dcb_pfc_enable(struct txgbe_hw *hw, uint8_t tc_num)
21 uint32_t mflcn_reg, fccfg_reg;
23 uint32_t fcrtl, fcrth;
27 /* Validate the water mark configuration */
28 if (!hw->fc.pause_time) {
29 ret_val = TXGBE_ERR_INVALID_LINK_SETTINGS;
33 /* Low water mark of zero causes XOFF floods */
34 if (hw->fc.current_mode & txgbe_fc_tx_pause) {
35 /* High/Low water can not be 0 */
36 if (!hw->fc.high_water[tc_num] ||
37 !hw->fc.low_water[tc_num]) {
38 PMD_INIT_LOG(ERR, "Invalid water mark configuration");
39 ret_val = TXGBE_ERR_INVALID_LINK_SETTINGS;
43 if (hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
44 PMD_INIT_LOG(ERR, "Invalid water mark configuration");
45 ret_val = TXGBE_ERR_INVALID_LINK_SETTINGS;
49 /* Negotiate the fc mode to use */
52 /* Disable any previous flow control settings */
53 mflcn_reg = rd32(hw, TXGBE_RXFCCFG);
54 mflcn_reg &= ~(TXGBE_RXFCCFG_FC | TXGBE_RXFCCFG_PFC);
56 fccfg_reg = rd32(hw, TXGBE_TXFCCFG);
57 fccfg_reg &= ~(TXGBE_TXFCCFG_FC | TXGBE_TXFCCFG_PFC);
59 switch (hw->fc.current_mode) {
62 * If the count of enabled RX Priority Flow control > 1,
63 * and the TX pause can not be disabled
66 for (i = 0; i < TXGBE_DCB_TC_MAX; i++) {
67 uint32_t reg = rd32(hw, TXGBE_FCWTRHI(i));
68 if (reg & TXGBE_FCWTRHI_XOFF)
72 fccfg_reg |= TXGBE_TXFCCFG_PFC;
74 case txgbe_fc_rx_pause:
76 * Rx Flow control is enabled and Tx Flow control is
77 * disabled by software override. Since there really
78 * isn't a way to advertise that we are capable of RX
79 * Pause ONLY, we will advertise that we support both
80 * symmetric and asymmetric Rx PAUSE. Later, we will
81 * disable the adapter's ability to send PAUSE frames.
83 mflcn_reg |= TXGBE_RXFCCFG_PFC;
85 * If the count of enabled RX Priority Flow control > 1,
86 * and the TX pause can not be disabled
89 for (i = 0; i < TXGBE_DCB_TC_MAX; i++) {
90 uint32_t reg = rd32(hw, TXGBE_FCWTRHI(i));
91 if (reg & TXGBE_FCWTRHI_XOFF)
95 fccfg_reg |= TXGBE_TXFCCFG_PFC;
97 case txgbe_fc_tx_pause:
99 * Tx Flow control is enabled, and Rx Flow control is
100 * disabled by software override.
102 fccfg_reg |= TXGBE_TXFCCFG_PFC;
105 /* Flow control (both Rx and Tx) is enabled by SW override. */
106 mflcn_reg |= TXGBE_RXFCCFG_PFC;
107 fccfg_reg |= TXGBE_TXFCCFG_PFC;
110 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
111 ret_val = TXGBE_ERR_CONFIG;
115 /* Set 802.3x based flow control settings. */
116 wr32(hw, TXGBE_RXFCCFG, mflcn_reg);
117 wr32(hw, TXGBE_TXFCCFG, fccfg_reg);
119 /* Set up and enable Rx high/low water mark thresholds, enable XON. */
120 if ((hw->fc.current_mode & txgbe_fc_tx_pause) &&
121 hw->fc.high_water[tc_num]) {
122 fcrtl = TXGBE_FCWTRLO_TH(hw->fc.low_water[tc_num]) |
124 fcrth = TXGBE_FCWTRHI_TH(hw->fc.high_water[tc_num]) |
128 * In order to prevent Tx hangs when the internal Tx
129 * switch is enabled we must set the high water mark
130 * to the maximum FCRTH value. This allows the Tx
131 * switch to function even under heavy Rx workloads.
134 fcrth = rd32(hw, TXGBE_PBRXSIZE(tc_num)) - 32;
136 wr32(hw, TXGBE_FCWTRLO(tc_num), fcrtl);
137 wr32(hw, TXGBE_FCWTRHI(tc_num), fcrth);
139 /* Configure pause time (2 TCs per register) */
140 pause_time = TXGBE_RXFCFSH_TIME(hw->fc.pause_time);
141 for (i = 0; i < (TXGBE_DCB_TC_MAX / 2); i++)
142 wr32(hw, TXGBE_FCXOFFTM(i), pause_time * 0x00010001);
144 /* Configure flow control refresh threshold value */
145 wr32(hw, TXGBE_RXFCRFSH, pause_time / 2);
152 * txgbe_dcb_calculate_tc_credits_cee - Calculates traffic class credits
153 * @hw: pointer to hardware structure
154 * @dcb_config: Struct containing DCB settings
155 * @max_frame_size: Maximum frame size
156 * @direction: Configuring either Tx or Rx
158 * This function calculates the credits allocated to each traffic class.
159 * It should be called only after the rules are checked by
160 * txgbe_dcb_check_config_cee().
162 s32 txgbe_dcb_calculate_tc_credits_cee(struct txgbe_hw *hw,
163 struct txgbe_dcb_config *dcb_config,
164 u32 max_frame_size, u8 direction)
166 struct txgbe_dcb_tc_path *p;
167 u32 min_multiplier = 0;
168 u16 min_percent = 100;
170 /* Initialization values default for Tx settings */
172 u32 credit_refill = 0;
174 u16 link_percentage = 0;
178 UNREFERENCED_PARAMETER(hw);
180 if (dcb_config == NULL) {
181 ret_val = TXGBE_ERR_CONFIG;
185 min_credit = ((max_frame_size / 2) + TXGBE_DCB_CREDIT_QUANTUM - 1) /
186 TXGBE_DCB_CREDIT_QUANTUM;
188 /* Find smallest link percentage */
189 for (i = 0; i < TXGBE_DCB_TC_MAX; i++) {
190 p = &dcb_config->tc_config[i].path[direction];
191 bw_percent = dcb_config->bw_percentage[p->bwg_id][direction];
192 link_percentage = p->bwg_percent;
194 link_percentage = (link_percentage * bw_percent) / 100;
196 if (link_percentage && link_percentage < min_percent)
197 min_percent = link_percentage;
201 * The ratio between traffic classes will control the bandwidth
202 * percentages seen on the wire. To calculate this ratio we use
203 * a multiplier. It is required that the refill credits must be
204 * larger than the max frame size so here we find the smallest
205 * multiplier that will allow all bandwidth percentages to be
206 * greater than the max frame size.
208 min_multiplier = (min_credit / min_percent) + 1;
210 /* Find out the link percentage for each TC first */
211 for (i = 0; i < TXGBE_DCB_TC_MAX; i++) {
212 p = &dcb_config->tc_config[i].path[direction];
213 bw_percent = dcb_config->bw_percentage[p->bwg_id][direction];
215 link_percentage = p->bwg_percent;
216 /* Must be careful of integer division for very small nums */
217 link_percentage = (link_percentage * bw_percent) / 100;
218 if (p->bwg_percent > 0 && link_percentage == 0)
221 /* Save link_percentage for reference */
222 p->link_percent = (u8)link_percentage;
224 /* Calculate credit refill ratio using multiplier */
225 credit_refill = min(link_percentage * min_multiplier,
226 (u32)TXGBE_DCB_MAX_CREDIT_REFILL);
228 /* Refill at least minimum credit */
229 if (credit_refill < min_credit)
230 credit_refill = min_credit;
232 p->data_credits_refill = (u16)credit_refill;
234 /* Calculate maximum credit for the TC */
235 credit_max = (link_percentage * TXGBE_DCB_MAX_CREDIT) / 100;
238 * Adjustment based on rule checking, if the percentage
239 * of a TC is too small, the maximum credit may not be
240 * enough to send out a jumbo frame in data plane arbitration.
242 if (credit_max < min_credit)
243 credit_max = min_credit;
245 if (direction == TXGBE_DCB_TX_CONFIG) {
246 dcb_config->tc_config[i].desc_credits_max =
250 p->data_credits_max = (u16)credit_max;
258 * txgbe_dcb_unpack_pfc_cee - Unpack dcb_config PFC info
259 * @cfg: dcb configuration to unpack into hardware consumable fields
260 * @map: user priority to traffic class map
261 * @pfc_up: u8 to store user priority PFC bitmask
263 * This unpacks the dcb configuration PFC info which is stored per
264 * traffic class into a 8bit user priority bitmask that can be
265 * consumed by hardware routines. The priority to tc map must be
266 * updated before calling this routine to use current up-to maps.
268 void txgbe_dcb_unpack_pfc_cee(struct txgbe_dcb_config *cfg, u8 *map, u8 *pfc_up)
270 struct txgbe_dcb_tc_config *tc_config = &cfg->tc_config[0];
274 * If the TC for this user priority has PFC enabled then set the
275 * matching bit in 'pfc_up' to reflect that PFC is enabled.
277 for (*pfc_up = 0, up = 0; up < TXGBE_DCB_UP_MAX; up++) {
278 if (tc_config[map[up]].pfc != txgbe_dcb_pfc_disabled)
283 void txgbe_dcb_unpack_refill_cee(struct txgbe_dcb_config *cfg, int direction,
286 struct txgbe_dcb_tc_config *tc_config = &cfg->tc_config[0];
289 for (tc = 0; tc < TXGBE_DCB_TC_MAX; tc++)
290 refill[tc] = tc_config[tc].path[direction].data_credits_refill;
293 void txgbe_dcb_unpack_max_cee(struct txgbe_dcb_config *cfg, u16 *max)
295 struct txgbe_dcb_tc_config *tc_config = &cfg->tc_config[0];
298 for (tc = 0; tc < TXGBE_DCB_TC_MAX; tc++)
299 max[tc] = tc_config[tc].desc_credits_max;
302 void txgbe_dcb_unpack_bwgid_cee(struct txgbe_dcb_config *cfg, int direction,
305 struct txgbe_dcb_tc_config *tc_config = &cfg->tc_config[0];
308 for (tc = 0; tc < TXGBE_DCB_TC_MAX; tc++)
309 bwgid[tc] = tc_config[tc].path[direction].bwg_id;
312 void txgbe_dcb_unpack_tsa_cee(struct txgbe_dcb_config *cfg, int direction,
315 struct txgbe_dcb_tc_config *tc_config = &cfg->tc_config[0];
318 for (tc = 0; tc < TXGBE_DCB_TC_MAX; tc++)
319 tsa[tc] = tc_config[tc].path[direction].tsa;
322 u8 txgbe_dcb_get_tc_from_up(struct txgbe_dcb_config *cfg, int direction, u8 up)
324 struct txgbe_dcb_tc_config *tc_config = &cfg->tc_config[0];
325 u8 prio_mask = 1 << up;
326 u8 tc = cfg->num_tcs.pg_tcs;
328 /* If tc is 0 then DCB is likely not enabled or supported */
333 * Test from maximum TC to 1 and report the first match we find. If
334 * we find no match we can assume that the TC is 0 since the TC must
335 * be set for all user priorities
337 for (tc--; tc; tc--) {
338 if (prio_mask & tc_config[tc].path[direction].up_to_tc_bitmap)
345 void txgbe_dcb_unpack_map_cee(struct txgbe_dcb_config *cfg, int direction,
350 for (up = 0; up < TXGBE_DCB_UP_MAX; up++)
351 map[up] = txgbe_dcb_get_tc_from_up(cfg, direction, up);
354 /* Helper routines to abstract HW specifics from DCB netlink ops */
355 s32 txgbe_dcb_config_pfc(struct txgbe_hw *hw, u8 pfc_en, u8 *map)
357 int ret = TXGBE_ERR_PARAM;
358 ret = txgbe_dcb_config_pfc_raptor(hw, pfc_en, map);