1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2015-2020
5 #include "txgbe_type.h"
10 * txgbe_dcb_config_rx_arbiter_raptor - Config Rx Data arbiter
11 * @hw: pointer to hardware structure
12 * @refill: refill credits index by traffic class
13 * @max: max credits index by traffic class
14 * @bwg_id: bandwidth grouping indexed by traffic class
15 * @tsa: transmission selection algorithm indexed by traffic class
16 * @map: priority to tc assignments indexed by priority
18 * Configure Rx Packet Arbiter and credits for each traffic class.
20 s32 txgbe_dcb_config_rx_arbiter_raptor(struct txgbe_hw *hw, u16 *refill,
21 u16 *max, u8 *bwg_id, u8 *tsa,
25 u32 credit_refill = 0;
30 * Disable the arbiter before changing parameters
31 * (always enable recycle mode; WSP)
33 reg = TXGBE_ARBRXCTL_RRM | TXGBE_ARBRXCTL_WSP |
35 wr32(hw, TXGBE_ARBRXCTL, reg);
38 * map all UPs to TCs. up_to_tc_bitmap for each TC has corresponding
39 * bits sets for the UPs that needs to be mappped to that TC.
40 * e.g if priorities 6 and 7 are to be mapped to a TC then the
41 * up_to_tc_bitmap value for that TC will be 11000000 in binary.
44 for (i = 0; i < TXGBE_DCB_UP_MAX; i++)
45 reg |= (map[i] << (i * TXGBE_RPUP2TC_UP_SHIFT));
47 wr32(hw, TXGBE_RPUP2TC, reg);
49 /* Configure traffic class credits and priority */
50 for (i = 0; i < TXGBE_DCB_TC_MAX; i++) {
51 credit_refill = refill[i];
53 reg = TXGBE_QARBRXCFG_CRQ(credit_refill) |
54 TXGBE_QARBRXCFG_MCL(credit_max) |
55 TXGBE_QARBRXCFG_BWG(bwg_id[i]);
57 if (tsa[i] == txgbe_dcb_tsa_strict)
58 reg |= TXGBE_QARBRXCFG_LSP;
60 wr32(hw, TXGBE_QARBRXCFG(i), reg);
64 * Configure Rx packet plane (recycle mode; WSP) and
67 reg = TXGBE_ARBRXCTL_RRM | TXGBE_ARBRXCTL_WSP;
68 wr32(hw, TXGBE_ARBRXCTL, reg);
74 * txgbe_dcb_config_tx_desc_arbiter_raptor - Config Tx Desc. arbiter
75 * @hw: pointer to hardware structure
76 * @refill: refill credits index by traffic class
77 * @max: max credits index by traffic class
78 * @bwg_id: bandwidth grouping indexed by traffic class
79 * @tsa: transmission selection algorithm indexed by traffic class
81 * Configure Tx Descriptor Arbiter and credits for each traffic class.
83 s32 txgbe_dcb_config_tx_desc_arbiter_raptor(struct txgbe_hw *hw, u16 *refill,
84 u16 *max, u8 *bwg_id, u8 *tsa)
89 /* Clear the per-Tx queue credits; we use per-TC instead */
90 for (i = 0; i < 128; i++)
91 wr32(hw, TXGBE_QARBTXCRED(i), 0);
93 /* Configure traffic class credits and priority */
94 for (i = 0; i < TXGBE_DCB_TC_MAX; i++) {
96 reg = TXGBE_QARBTXCFG_MCL(max_credits) |
97 TXGBE_QARBTXCFG_CRQ(refill[i]) |
98 TXGBE_QARBTXCFG_BWG(bwg_id[i]);
100 if (tsa[i] == txgbe_dcb_tsa_group_strict_cee)
101 reg |= TXGBE_QARBTXCFG_GSP;
103 if (tsa[i] == txgbe_dcb_tsa_strict)
104 reg |= TXGBE_QARBTXCFG_LSP;
106 wr32(hw, TXGBE_QARBTXCFG(i), reg);
110 * Configure Tx descriptor plane (recycle mode; WSP) and
113 reg = TXGBE_ARBTXCTL_WSP | TXGBE_ARBTXCTL_RRM;
114 wr32(hw, TXGBE_ARBTXCTL, reg);
120 * txgbe_dcb_config_tx_data_arbiter_raptor - Config Tx Data arbiter
121 * @hw: pointer to hardware structure
122 * @refill: refill credits index by traffic class
123 * @max: max credits index by traffic class
124 * @bwg_id: bandwidth grouping indexed by traffic class
125 * @tsa: transmission selection algorithm indexed by traffic class
126 * @map: priority to tc assignments indexed by priority
128 * Configure Tx Packet Arbiter and credits for each traffic class.
130 s32 txgbe_dcb_config_tx_data_arbiter_raptor(struct txgbe_hw *hw, u16 *refill,
131 u16 *max, u8 *bwg_id, u8 *tsa,
138 * Disable the arbiter before changing parameters
139 * (always enable recycle mode; SP; arb delay)
141 reg = TXGBE_PARBTXCTL_SP |
142 TXGBE_PARBTXCTL_RECYC |
144 wr32(hw, TXGBE_PARBTXCTL, reg);
147 * map all UPs to TCs. up_to_tc_bitmap for each TC has corresponding
148 * bits sets for the UPs that needs to be mappped to that TC.
149 * e.g if priorities 6 and 7 are to be mapped to a TC then the
150 * up_to_tc_bitmap value for that TC will be 11000000 in binary.
153 for (i = 0; i < TXGBE_DCB_UP_MAX; i++)
154 reg |= TXGBE_DCBUP2TC_MAP(i, map[i]);
156 wr32(hw, TXGBE_PBRXUP2TC, reg);
158 /* Configure traffic class credits and priority */
159 for (i = 0; i < TXGBE_DCB_TC_MAX; i++) {
160 reg = TXGBE_PARBTXCFG_CRQ(refill[i]) |
161 TXGBE_PARBTXCFG_MCL(max[i]) |
162 TXGBE_PARBTXCFG_BWG(bwg_id[i]);
164 if (tsa[i] == txgbe_dcb_tsa_group_strict_cee)
165 reg |= TXGBE_PARBTXCFG_GSP;
167 if (tsa[i] == txgbe_dcb_tsa_strict)
168 reg |= TXGBE_PARBTXCFG_LSP;
170 wr32(hw, TXGBE_PARBTXCFG(i), reg);
174 * Configure Tx packet plane (recycle mode; SP; arb delay) and
177 reg = TXGBE_PARBTXCTL_SP | TXGBE_PARBTXCTL_RECYC;
178 wr32(hw, TXGBE_PARBTXCTL, reg);
184 * txgbe_dcb_config_pfc_raptor - Configure priority flow control
185 * @hw: pointer to hardware structure
186 * @pfc_en: enabled pfc bitmask
187 * @map: priority to tc assignments indexed by priority
189 * Configure Priority Flow Control (PFC) for each traffic class.
191 s32 txgbe_dcb_config_pfc_raptor(struct txgbe_hw *hw, u8 pfc_en, u8 *map)
193 u32 i, j, fcrtl, reg;
196 /* Enable Transmit Priority Flow Control */
197 wr32(hw, TXGBE_TXFCCFG, TXGBE_TXFCCFG_PFC);
199 /* Enable Receive Priority Flow Control */
200 wr32m(hw, TXGBE_RXFCCFG, TXGBE_RXFCCFG_PFC,
201 pfc_en ? TXGBE_RXFCCFG_PFC : 0);
203 for (i = 0; i < TXGBE_DCB_UP_MAX; i++) {
208 /* Configure PFC Tx thresholds per TC */
209 for (i = 0; i <= max_tc; i++) {
212 for (j = 0; j < TXGBE_DCB_UP_MAX; j++) {
213 if (map[j] == i && (pfc_en & (1 << j))) {
220 reg = TXGBE_FCWTRHI_TH(hw->fc.high_water[i]) |
222 fcrtl = TXGBE_FCWTRLO_TH(hw->fc.low_water[i]) |
224 wr32(hw, TXGBE_FCWTRLO(i), fcrtl);
227 * In order to prevent Tx hangs when the internal Tx
228 * switch is enabled we must set the high water mark
229 * to the Rx packet buffer size - 24KB. This allows
230 * the Tx switch to function even under heavy Rx
233 reg = rd32(hw, TXGBE_PBRXSIZE(i)) - 24576;
234 wr32(hw, TXGBE_FCWTRLO(i), 0);
237 wr32(hw, TXGBE_FCWTRHI(i), reg);
240 for (; i < TXGBE_DCB_TC_MAX; i++) {
241 wr32(hw, TXGBE_FCWTRLO(i), 0);
242 wr32(hw, TXGBE_FCWTRHI(i), 0);
245 /* Configure pause time (2 TCs per register) */
246 reg = hw->fc.pause_time | (hw->fc.pause_time << 16);
247 for (i = 0; i < (TXGBE_DCB_TC_MAX / 2); i++)
248 wr32(hw, TXGBE_FCXOFFTM(i), reg);
250 /* Configure flow control refresh threshold value */
251 wr32(hw, TXGBE_RXFCRFSH, hw->fc.pause_time / 2);
257 * txgbe_dcb_config_tc_stats_raptor - Config traffic class statistics
258 * @hw: pointer to hardware structure
259 * @dcb_config: pointer to txgbe_dcb_config structure
261 * Configure queue statistics registers, all queues belonging to same traffic
262 * class uses a single set of queue statistics counters.
264 s32 txgbe_dcb_config_tc_stats_raptor(struct txgbe_hw *hw,
265 struct txgbe_dcb_config *dcb_config)
268 bool vt_mode = false;
270 UNREFERENCED_PARAMETER(hw);
272 if (dcb_config != NULL) {
273 tc_count = dcb_config->num_tcs.pg_tcs;
274 vt_mode = dcb_config->vt_mode;
277 if (!((tc_count == 8 && !vt_mode) || tc_count == 4))
278 return TXGBE_ERR_PARAM;