1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2015-2020 Beijing WangXun Technology Co., Ltd.
3 * Copyright(c) 2010-2017 Intel Corporation
6 #ifndef _TXGBE_EEPROM_H_
7 #define _TXGBE_EEPROM_H_
9 /* Checksum and EEPROM pointers */
10 #define TXGBE_PBANUM_PTR_GUARD 0xFAFA
11 #define TXGBE_EEPROM_SUM 0xBABA
13 #define TXGBE_FW_VER_LEN 32
14 #define TXGBE_FW_N_TXEQ 0x0002000A
16 #define TXGBE_FW_PTR 0x0F
17 #define TXGBE_PBANUM0_PTR 0x05
18 #define TXGBE_PBANUM1_PTR 0x06
19 #define TXGBE_SW_REGION_PTR 0x1C
21 #define TXGBE_EE_CSUM_MAX 0x800
22 #define TXGBE_EEPROM_CHECKSUM 0x2F
24 #define TXGBE_SAN_MAC_ADDR_PTR 0x18
25 #define TXGBE_DEVICE_CAPS 0x1C
26 #define TXGBE_EEPROM_VERSION_L 0x1D
27 #define TXGBE_EEPROM_VERSION_H 0x1E
28 #define TXGBE_ISCSI_BOOT_CONFIG 0x07
30 #define TXGBE_SAN_MAC_ADDR_PORT0_OFFSET 0x0
31 #define TXGBE_SAN_MAC_ADDR_PORT1_OFFSET 0x3
32 #define TXGBE_DEVICE_CAPS_ALLOW_ANY_SFP 0x1
33 #define TXGBE_DEVICE_CAPS_NO_CROSSTALK_WR (1 << 7)
34 #define TXGBE_FW_LESM_PARAMETERS_PTR 0x2
35 #define TXGBE_FW_LESM_STATE_1 0x1
36 #define TXGBE_FW_LESM_STATE_ENABLED 0x8000 /* LESM Enable bit */
37 #define TXGBE_ALT_SAN_MAC_ADDR_BLK_PTR 0x27 /* Alt. SAN MAC block */
38 #define TXGBE_ALT_SAN_MAC_ADDR_CAPS_OFFSET 0x0 /* Alt SAN MAC capability */
39 #define TXGBE_ALT_SAN_MAC_ADDR_PORT0_OFFSET 0x1 /* Alt SAN MAC 0 offset */
40 #define TXGBE_ALT_SAN_MAC_ADDR_PORT1_OFFSET 0x4 /* Alt SAN MAC 1 offset */
41 #define TXGBE_ALT_SAN_MAC_ADDR_WWNN_OFFSET 0x7 /* Alt WWNN prefix offset */
42 #define TXGBE_ALT_SAN_MAC_ADDR_WWPN_OFFSET 0x8 /* Alt WWPN prefix offset */
43 #define TXGBE_ALT_SAN_MAC_ADDR_CAPS_SANMAC 0x0 /* Alt SAN MAC exists */
44 #define TXGBE_ALT_SAN_MAC_ADDR_CAPS_ALTWWN 0x1 /* Alt WWN base exists */
46 s32 txgbe_init_eeprom_params(struct txgbe_hw *hw);
47 s32 txgbe_calc_eeprom_checksum(struct txgbe_hw *hw);
48 s32 txgbe_validate_eeprom_checksum(struct txgbe_hw *hw, u16 *checksum_val);
49 s32 txgbe_update_eeprom_checksum(struct txgbe_hw *hw);
50 s32 txgbe_get_eeprom_semaphore(struct txgbe_hw *hw);
51 void txgbe_release_eeprom_semaphore(struct txgbe_hw *hw);
53 s32 txgbe_ee_read16(struct txgbe_hw *hw, u32 offset, u16 *data);
54 s32 txgbe_ee_readw_sw(struct txgbe_hw *hw, u32 offset, u16 *data);
55 s32 txgbe_ee_readw_buffer(struct txgbe_hw *hw, u32 offset, u32 words,
57 s32 txgbe_ee_read32(struct txgbe_hw *hw, u32 addr, u32 *data);
59 s32 txgbe_ee_write16(struct txgbe_hw *hw, u32 offset, u16 data);
60 s32 txgbe_ee_writew_sw(struct txgbe_hw *hw, u32 offset, u16 data);
61 s32 txgbe_ee_writew_buffer(struct txgbe_hw *hw, u32 offset, u32 words,
63 s32 txgbe_ee_write32(struct txgbe_hw *hw, u32 addr, u32 data);
66 #endif /* _TXGBE_EEPROM_H_ */