1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2015-2020 Beijing WangXun Technology Co., Ltd.
3 * Copyright(c) 2010-2017 Intel Corporation
6 #include "txgbe_type.h"
11 #include "txgbe_eeprom.h"
12 #include "txgbe_mng.h"
15 #define TXGBE_RAPTOR_MAX_TX_QUEUES 128
16 #define TXGBE_RAPTOR_MAX_RX_QUEUES 128
17 #define TXGBE_RAPTOR_RAR_ENTRIES 128
18 #define TXGBE_RAPTOR_MC_TBL_SIZE 128
19 #define TXGBE_RAPTOR_VFT_TBL_SIZE 128
20 #define TXGBE_RAPTOR_RX_PB_SIZE 512 /*KB*/
22 static s32 txgbe_setup_copper_link_raptor(struct txgbe_hw *hw,
24 bool autoneg_wait_to_complete);
26 static s32 txgbe_mta_vector(struct txgbe_hw *hw, u8 *mc_addr);
27 static s32 txgbe_get_san_mac_addr_offset(struct txgbe_hw *hw,
31 * txgbe_device_supports_autoneg_fc - Check if device supports autonegotiation
33 * @hw: pointer to hardware structure
35 * This function returns true if the device supports flow control
36 * autonegotiation, and false if it does not.
39 bool txgbe_device_supports_autoneg_fc(struct txgbe_hw *hw)
41 bool supported = false;
45 DEBUGFUNC("txgbe_device_supports_autoneg_fc");
47 switch (hw->phy.media_type) {
48 case txgbe_media_type_fiber_qsfp:
49 case txgbe_media_type_fiber:
50 hw->mac.check_link(hw, &speed, &link_up, false);
51 /* if link is down, assume supported */
53 supported = speed == TXGBE_LINK_SPEED_1GB_FULL ?
59 case txgbe_media_type_backplane:
62 case txgbe_media_type_copper:
63 /* only some copper devices support flow control autoneg */
64 switch (hw->subsystem_device_id & 0xFF) {
65 case TXGBE_DEV_ID_XAUI:
66 case TXGBE_DEV_ID_SGMII:
77 DEBUGOUT("Device %x does not support flow control autoneg",
83 * txgbe_setup_fc - Set up flow control
84 * @hw: pointer to hardware structure
86 * Called at init time to set up flow control.
88 s32 txgbe_setup_fc(struct txgbe_hw *hw)
96 DEBUGFUNC("txgbe_setup_fc");
98 /* Validate the requested mode */
99 if (hw->fc.strict_ieee && hw->fc.requested_mode == txgbe_fc_rx_pause) {
100 DEBUGOUT("txgbe_fc_rx_pause not valid in strict IEEE mode\n");
101 err = TXGBE_ERR_INVALID_LINK_SETTINGS;
106 * 10gig parts do not have a word in the EEPROM to determine the
107 * default flow control setting, so we explicitly set it to full.
109 if (hw->fc.requested_mode == txgbe_fc_default)
110 hw->fc.requested_mode = txgbe_fc_full;
113 * The possible values of fc.requested_mode are:
114 * 0: Flow control is completely disabled
115 * 1: Rx flow control is enabled (we can receive pause frames,
116 * but not send pause frames).
117 * 2: Tx flow control is enabled (we can send pause frames but
118 * we do not support receiving pause frames).
119 * 3: Both Rx and Tx flow control (symmetric) are enabled.
122 switch (hw->fc.requested_mode) {
124 /* Flow control completely disabled by software override. */
126 case txgbe_fc_tx_pause:
128 * Tx Flow control is enabled, and Rx Flow control is
129 * disabled by software override.
131 reg |= SR_MII_MMD_AN_ADV_PAUSE_ASM;
132 reg_bp |= SR_AN_MMD_ADV_REG1_PAUSE_ASM;
134 case txgbe_fc_rx_pause:
136 * Rx Flow control is enabled and Tx Flow control is
137 * disabled by software override. Since there really
138 * isn't a way to advertise that we are capable of RX
139 * Pause ONLY, we will advertise that we support both
140 * symmetric and asymmetric Rx PAUSE, as such we fall
141 * through to the fc_full statement. Later, we will
142 * disable the adapter's ability to send PAUSE frames.
145 /* Flow control (both Rx and Tx) is enabled by SW override. */
146 reg |= SR_MII_MMD_AN_ADV_PAUSE_SYM |
147 SR_MII_MMD_AN_ADV_PAUSE_ASM;
148 reg_bp |= SR_AN_MMD_ADV_REG1_PAUSE_SYM |
149 SR_AN_MMD_ADV_REG1_PAUSE_ASM;
152 DEBUGOUT("Flow control param set incorrectly\n");
153 err = TXGBE_ERR_CONFIG;
158 * Enable auto-negotiation between the MAC & PHY;
159 * the MAC will advertise clause 37 flow control.
161 value = rd32_epcs(hw, SR_MII_MMD_AN_ADV);
162 value = (value & ~(SR_MII_MMD_AN_ADV_PAUSE_ASM |
163 SR_MII_MMD_AN_ADV_PAUSE_SYM)) | reg;
164 wr32_epcs(hw, SR_MII_MMD_AN_ADV, value);
167 * AUTOC restart handles negotiation of 1G and 10G on backplane
168 * and copper. There is no need to set the PCS1GCTL register.
171 if (hw->phy.media_type == txgbe_media_type_backplane) {
172 value = rd32_epcs(hw, SR_AN_MMD_ADV_REG1);
173 value = (value & ~(SR_AN_MMD_ADV_REG1_PAUSE_ASM |
174 SR_AN_MMD_ADV_REG1_PAUSE_SYM)) |
176 wr32_epcs(hw, SR_AN_MMD_ADV_REG1, value);
177 } else if ((hw->phy.media_type == txgbe_media_type_copper) &&
178 (txgbe_device_supports_autoneg_fc(hw))) {
179 hw->phy.write_reg(hw, TXGBE_MD_AUTO_NEG_ADVT,
180 TXGBE_MD_DEV_AUTO_NEG, reg_cu);
183 DEBUGOUT("Set up FC; reg = 0x%08X\n", reg);
189 * txgbe_start_hw - Prepare hardware for Tx/Rx
190 * @hw: pointer to hardware structure
192 * Starts the hardware by filling the bus info structure and media type, clears
193 * all on chip counters, initializes receive address registers, multicast
194 * table, VLAN filter table, calls routine to set up link and flow control
195 * settings, and leaves transmit and receive units disabled and uninitialized
197 s32 txgbe_start_hw(struct txgbe_hw *hw)
202 DEBUGFUNC("txgbe_start_hw");
204 /* Set the media type */
205 hw->phy.media_type = hw->phy.get_media_type(hw);
207 /* Clear the VLAN filter table */
208 hw->mac.clear_vfta(hw);
210 /* Clear statistics registers */
211 hw->mac.clear_hw_cntrs(hw);
213 /* Setup flow control */
214 err = txgbe_setup_fc(hw);
215 if (err != 0 && err != TXGBE_NOT_IMPLEMENTED) {
216 DEBUGOUT("Flow control setup failed, returning %d\n", err);
220 /* Cache bit indicating need for crosstalk fix */
221 switch (hw->mac.type) {
222 case txgbe_mac_raptor:
223 hw->mac.get_device_caps(hw, &device_caps);
224 if (device_caps & TXGBE_DEVICE_CAPS_NO_CROSSTALK_WR)
225 hw->need_crosstalk_fix = false;
227 hw->need_crosstalk_fix = true;
230 hw->need_crosstalk_fix = false;
234 /* Clear adapter stopped flag */
235 hw->adapter_stopped = false;
241 * txgbe_start_hw_gen2 - Init sequence for common device family
242 * @hw: pointer to hw structure
244 * Performs the init sequence common to the second generation
247 s32 txgbe_start_hw_gen2(struct txgbe_hw *hw)
251 /* Clear the rate limiters */
252 for (i = 0; i < hw->mac.max_tx_queues; i++) {
253 wr32(hw, TXGBE_ARBPOOLIDX, i);
254 wr32(hw, TXGBE_ARBTXRATE, 0);
258 /* We need to run link autotry after the driver loads */
259 hw->mac.autotry_restart = true;
265 * txgbe_init_hw - Generic hardware initialization
266 * @hw: pointer to hardware structure
268 * Initialize the hardware by resetting the hardware, filling the bus info
269 * structure and media type, clears all on chip counters, initializes receive
270 * address registers, multicast table, VLAN filter table, calls routine to set
271 * up link and flow control settings, and leaves transmit and receive units
272 * disabled and uninitialized
274 s32 txgbe_init_hw(struct txgbe_hw *hw)
278 DEBUGFUNC("txgbe_init_hw");
280 /* Get firmware version */
281 hw->phy.get_fw_version(hw, &hw->fw_version);
283 /* Reset the hardware */
284 status = hw->mac.reset_hw(hw);
285 if (status == 0 || status == TXGBE_ERR_SFP_NOT_PRESENT) {
287 status = hw->mac.start_hw(hw);
291 DEBUGOUT("Failed to initialize HW, STATUS = %d\n", status);
297 * txgbe_clear_hw_cntrs - Generic clear hardware counters
298 * @hw: pointer to hardware structure
300 * Clears all hardware statistics counters by reading them from the hardware
301 * Statistics counters are clear on read.
303 s32 txgbe_clear_hw_cntrs(struct txgbe_hw *hw)
307 DEBUGFUNC("txgbe_clear_hw_cntrs");
310 /* don't write clear queue stats */
311 for (i = 0; i < TXGBE_MAX_QP; i++) {
312 hw->qp_last[i].rx_qp_packets = 0;
313 hw->qp_last[i].tx_qp_packets = 0;
314 hw->qp_last[i].rx_qp_bytes = 0;
315 hw->qp_last[i].tx_qp_bytes = 0;
316 hw->qp_last[i].rx_qp_mc_packets = 0;
320 for (i = 0; i < TXGBE_MAX_UP; i++) {
321 rd32(hw, TXGBE_PBRXUPXON(i));
322 rd32(hw, TXGBE_PBRXUPXOFF(i));
323 rd32(hw, TXGBE_PBTXUPXON(i));
324 rd32(hw, TXGBE_PBTXUPXOFF(i));
325 rd32(hw, TXGBE_PBTXUPOFF(i));
327 rd32(hw, TXGBE_PBRXMISS(i));
329 rd32(hw, TXGBE_PBRXLNKXON);
330 rd32(hw, TXGBE_PBRXLNKXOFF);
331 rd32(hw, TXGBE_PBTXLNKXON);
332 rd32(hw, TXGBE_PBTXLNKXOFF);
335 rd32(hw, TXGBE_DMARXPKT);
336 rd32(hw, TXGBE_DMATXPKT);
338 rd64(hw, TXGBE_DMARXOCTL);
339 rd64(hw, TXGBE_DMATXOCTL);
342 rd64(hw, TXGBE_MACRXERRCRCL);
343 rd64(hw, TXGBE_MACRXMPKTL);
344 rd64(hw, TXGBE_MACTXMPKTL);
346 rd64(hw, TXGBE_MACRXPKTL);
347 rd64(hw, TXGBE_MACTXPKTL);
348 rd64(hw, TXGBE_MACRXGBOCTL);
350 rd64(hw, TXGBE_MACRXOCTL);
351 rd32(hw, TXGBE_MACTXOCTL);
353 rd64(hw, TXGBE_MACRX1TO64L);
354 rd64(hw, TXGBE_MACRX65TO127L);
355 rd64(hw, TXGBE_MACRX128TO255L);
356 rd64(hw, TXGBE_MACRX256TO511L);
357 rd64(hw, TXGBE_MACRX512TO1023L);
358 rd64(hw, TXGBE_MACRX1024TOMAXL);
359 rd64(hw, TXGBE_MACTX1TO64L);
360 rd64(hw, TXGBE_MACTX65TO127L);
361 rd64(hw, TXGBE_MACTX128TO255L);
362 rd64(hw, TXGBE_MACTX256TO511L);
363 rd64(hw, TXGBE_MACTX512TO1023L);
364 rd64(hw, TXGBE_MACTX1024TOMAXL);
366 rd64(hw, TXGBE_MACRXERRLENL);
367 rd32(hw, TXGBE_MACRXOVERSIZE);
368 rd32(hw, TXGBE_MACRXJABBER);
371 rd32(hw, TXGBE_FCOECRC);
372 rd32(hw, TXGBE_FCOELAST);
373 rd32(hw, TXGBE_FCOERPDC);
374 rd32(hw, TXGBE_FCOEPRC);
375 rd32(hw, TXGBE_FCOEPTC);
376 rd32(hw, TXGBE_FCOEDWRC);
377 rd32(hw, TXGBE_FCOEDWTC);
379 /* Flow Director Stats */
380 rd32(hw, TXGBE_FDIRMATCH);
381 rd32(hw, TXGBE_FDIRMISS);
382 rd32(hw, TXGBE_FDIRUSED);
383 rd32(hw, TXGBE_FDIRUSED);
384 rd32(hw, TXGBE_FDIRFAIL);
385 rd32(hw, TXGBE_FDIRFAIL);
388 rd32(hw, TXGBE_LSECTX_UTPKT);
389 rd32(hw, TXGBE_LSECTX_ENCPKT);
390 rd32(hw, TXGBE_LSECTX_PROTPKT);
391 rd32(hw, TXGBE_LSECTX_ENCOCT);
392 rd32(hw, TXGBE_LSECTX_PROTOCT);
393 rd32(hw, TXGBE_LSECRX_UTPKT);
394 rd32(hw, TXGBE_LSECRX_BTPKT);
395 rd32(hw, TXGBE_LSECRX_NOSCIPKT);
396 rd32(hw, TXGBE_LSECRX_UNSCIPKT);
397 rd32(hw, TXGBE_LSECRX_DECOCT);
398 rd32(hw, TXGBE_LSECRX_VLDOCT);
399 rd32(hw, TXGBE_LSECRX_UNCHKPKT);
400 rd32(hw, TXGBE_LSECRX_DLYPKT);
401 rd32(hw, TXGBE_LSECRX_LATEPKT);
402 for (i = 0; i < 2; i++) {
403 rd32(hw, TXGBE_LSECRX_OKPKT(i));
404 rd32(hw, TXGBE_LSECRX_INVPKT(i));
405 rd32(hw, TXGBE_LSECRX_BADPKT(i));
407 rd32(hw, TXGBE_LSECRX_INVSAPKT);
408 rd32(hw, TXGBE_LSECRX_BADSAPKT);
414 * txgbe_get_mac_addr - Generic get MAC address
415 * @hw: pointer to hardware structure
416 * @mac_addr: Adapter MAC address
418 * Reads the adapter's MAC address from first Receive Address Register (RAR0)
419 * A reset of the adapter must be performed prior to calling this function
420 * in order for the MAC address to have been loaded from the EEPROM into RAR0
422 s32 txgbe_get_mac_addr(struct txgbe_hw *hw, u8 *mac_addr)
428 DEBUGFUNC("txgbe_get_mac_addr");
430 wr32(hw, TXGBE_ETHADDRIDX, 0);
431 rar_high = rd32(hw, TXGBE_ETHADDRH);
432 rar_low = rd32(hw, TXGBE_ETHADDRL);
434 for (i = 0; i < 2; i++)
435 mac_addr[i] = (u8)(rar_high >> (1 - i) * 8);
437 for (i = 0; i < 4; i++)
438 mac_addr[i + 2] = (u8)(rar_low >> (3 - i) * 8);
444 * txgbe_set_lan_id_multi_port - Set LAN id for PCIe multiple port devices
445 * @hw: pointer to the HW structure
447 * Determines the LAN function id by reading memory-mapped registers and swaps
448 * the port value if requested, and set MAC instance for devices.
450 void txgbe_set_lan_id_multi_port(struct txgbe_hw *hw)
452 struct txgbe_bus_info *bus = &hw->bus;
455 DEBUGFUNC("txgbe_set_lan_id_multi_port_pcie");
457 reg = rd32(hw, TXGBE_PORTSTAT);
458 bus->lan_id = TXGBE_PORTSTAT_ID(reg);
460 /* check for single port */
461 reg = rd32(hw, TXGBE_PWR);
462 if (TXGBE_PWR_LANID(reg) == TXGBE_PWR_LANID_SWAP)
465 bus->func = bus->lan_id;
469 * txgbe_stop_hw - Generic stop Tx/Rx units
470 * @hw: pointer to hardware structure
472 * Sets the adapter_stopped flag within txgbe_hw struct. Clears interrupts,
473 * disables transmit and receive units. The adapter_stopped flag is used by
474 * the shared code and drivers to determine if the adapter is in a stopped
475 * state and should not touch the hardware.
477 s32 txgbe_stop_hw(struct txgbe_hw *hw)
482 DEBUGFUNC("txgbe_stop_hw");
485 * Set the adapter_stopped flag so other driver functions stop touching
488 hw->adapter_stopped = true;
490 /* Disable the receive unit */
491 txgbe_disable_rx(hw);
493 /* Clear interrupt mask to stop interrupts from being generated */
494 wr32(hw, TXGBE_IENMISC, 0);
495 wr32(hw, TXGBE_IMS(0), TXGBE_IMS_MASK);
496 wr32(hw, TXGBE_IMS(1), TXGBE_IMS_MASK);
498 /* Clear any pending interrupts, flush previous writes */
499 wr32(hw, TXGBE_ICRMISC, TXGBE_ICRMISC_MASK);
500 wr32(hw, TXGBE_ICR(0), TXGBE_ICR_MASK);
501 wr32(hw, TXGBE_ICR(1), TXGBE_ICR_MASK);
503 /* Disable the transmit unit. Each queue must be disabled. */
504 for (i = 0; i < hw->mac.max_tx_queues; i++)
505 wr32(hw, TXGBE_TXCFG(i), TXGBE_TXCFG_FLUSH);
507 /* Disable the receive unit by stopping each queue */
508 for (i = 0; i < hw->mac.max_rx_queues; i++) {
509 reg_val = rd32(hw, TXGBE_RXCFG(i));
510 reg_val &= ~TXGBE_RXCFG_ENA;
511 wr32(hw, TXGBE_RXCFG(i), reg_val);
514 /* flush all queues disables */
522 * txgbe_led_on - Turns on the software controllable LEDs.
523 * @hw: pointer to hardware structure
524 * @index: led number to turn on
526 s32 txgbe_led_on(struct txgbe_hw *hw, u32 index)
528 u32 led_reg = rd32(hw, TXGBE_LEDCTL);
530 DEBUGFUNC("txgbe_led_on");
533 return TXGBE_ERR_PARAM;
535 /* To turn on the LED, set mode to ON. */
536 led_reg |= TXGBE_LEDCTL_SEL(index);
537 led_reg |= TXGBE_LEDCTL_ORD(index);
538 wr32(hw, TXGBE_LEDCTL, led_reg);
545 * txgbe_led_off - Turns off the software controllable LEDs.
546 * @hw: pointer to hardware structure
547 * @index: led number to turn off
549 s32 txgbe_led_off(struct txgbe_hw *hw, u32 index)
551 u32 led_reg = rd32(hw, TXGBE_LEDCTL);
553 DEBUGFUNC("txgbe_led_off");
556 return TXGBE_ERR_PARAM;
558 /* To turn off the LED, set mode to OFF. */
559 led_reg &= ~(TXGBE_LEDCTL_SEL(index));
560 led_reg &= ~(TXGBE_LEDCTL_ORD(index));
561 wr32(hw, TXGBE_LEDCTL, led_reg);
568 * txgbe_validate_mac_addr - Validate MAC address
569 * @mac_addr: pointer to MAC address.
571 * Tests a MAC address to ensure it is a valid Individual Address.
573 s32 txgbe_validate_mac_addr(u8 *mac_addr)
577 DEBUGFUNC("txgbe_validate_mac_addr");
579 /* Make sure it is not a multicast address */
580 if (TXGBE_IS_MULTICAST(mac_addr)) {
581 status = TXGBE_ERR_INVALID_MAC_ADDR;
582 /* Not a broadcast address */
583 } else if (TXGBE_IS_BROADCAST(mac_addr)) {
584 status = TXGBE_ERR_INVALID_MAC_ADDR;
585 /* Reject the zero address */
586 } else if (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 &&
587 mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0) {
588 status = TXGBE_ERR_INVALID_MAC_ADDR;
594 * txgbe_set_rar - Set Rx address register
595 * @hw: pointer to hardware structure
596 * @index: Receive address register to write
597 * @addr: Address to put into receive address register
598 * @vmdq: VMDq "set" or "pool" index
599 * @enable_addr: set flag that address is active
601 * Puts an ethernet address into a receive address register.
603 s32 txgbe_set_rar(struct txgbe_hw *hw, u32 index, u8 *addr, u32 vmdq,
606 u32 rar_low, rar_high;
607 u32 rar_entries = hw->mac.num_rar_entries;
609 DEBUGFUNC("txgbe_set_rar");
611 /* Make sure we are using a valid rar index range */
612 if (index >= rar_entries) {
613 DEBUGOUT("RAR index %d is out of range.\n", index);
614 return TXGBE_ERR_INVALID_ARGUMENT;
617 /* setup VMDq pool selection before this RAR gets enabled */
618 hw->mac.set_vmdq(hw, index, vmdq);
621 * HW expects these in little endian so we reverse the byte
622 * order from network order (big endian) to little endian
624 rar_low = TXGBE_ETHADDRL_AD0(addr[5]) |
625 TXGBE_ETHADDRL_AD1(addr[4]) |
626 TXGBE_ETHADDRL_AD2(addr[3]) |
627 TXGBE_ETHADDRL_AD3(addr[2]);
629 * Some parts put the VMDq setting in the extra RAH bits,
630 * so save everything except the lower 16 bits that hold part
631 * of the address and the address valid bit.
633 rar_high = rd32(hw, TXGBE_ETHADDRH);
634 rar_high &= ~TXGBE_ETHADDRH_AD_MASK;
635 rar_high |= (TXGBE_ETHADDRH_AD4(addr[1]) |
636 TXGBE_ETHADDRH_AD5(addr[0]));
638 rar_high &= ~TXGBE_ETHADDRH_VLD;
639 if (enable_addr != 0)
640 rar_high |= TXGBE_ETHADDRH_VLD;
642 wr32(hw, TXGBE_ETHADDRIDX, index);
643 wr32(hw, TXGBE_ETHADDRL, rar_low);
644 wr32(hw, TXGBE_ETHADDRH, rar_high);
650 * txgbe_clear_rar - Remove Rx address register
651 * @hw: pointer to hardware structure
652 * @index: Receive address register to write
654 * Clears an ethernet address from a receive address register.
656 s32 txgbe_clear_rar(struct txgbe_hw *hw, u32 index)
659 u32 rar_entries = hw->mac.num_rar_entries;
661 DEBUGFUNC("txgbe_clear_rar");
663 /* Make sure we are using a valid rar index range */
664 if (index >= rar_entries) {
665 DEBUGOUT("RAR index %d is out of range.\n", index);
666 return TXGBE_ERR_INVALID_ARGUMENT;
670 * Some parts put the VMDq setting in the extra RAH bits,
671 * so save everything except the lower 16 bits that hold part
672 * of the address and the address valid bit.
674 wr32(hw, TXGBE_ETHADDRIDX, index);
675 rar_high = rd32(hw, TXGBE_ETHADDRH);
676 rar_high &= ~(TXGBE_ETHADDRH_AD_MASK | TXGBE_ETHADDRH_VLD);
678 wr32(hw, TXGBE_ETHADDRL, 0);
679 wr32(hw, TXGBE_ETHADDRH, rar_high);
681 /* clear VMDq pool/queue selection for this RAR */
682 hw->mac.clear_vmdq(hw, index, BIT_MASK32);
688 * txgbe_init_rx_addrs - Initializes receive address filters.
689 * @hw: pointer to hardware structure
691 * Places the MAC address in receive address register 0 and clears the rest
692 * of the receive address registers. Clears the multicast table. Assumes
693 * the receiver is in reset when the routine is called.
695 s32 txgbe_init_rx_addrs(struct txgbe_hw *hw)
699 u32 rar_entries = hw->mac.num_rar_entries;
701 DEBUGFUNC("txgbe_init_rx_addrs");
704 * If the current mac address is valid, assume it is a software override
705 * to the permanent address.
706 * Otherwise, use the permanent address from the eeprom.
708 if (txgbe_validate_mac_addr(hw->mac.addr) ==
709 TXGBE_ERR_INVALID_MAC_ADDR) {
710 /* Get the MAC address from the RAR0 for later reference */
711 hw->mac.get_mac_addr(hw, hw->mac.addr);
713 DEBUGOUT(" Keeping Current RAR0 Addr =%.2X %.2X %.2X ",
714 hw->mac.addr[0], hw->mac.addr[1],
716 DEBUGOUT("%.2X %.2X %.2X\n", hw->mac.addr[3],
717 hw->mac.addr[4], hw->mac.addr[5]);
719 /* Setup the receive address. */
720 DEBUGOUT("Overriding MAC Address in RAR[0]\n");
721 DEBUGOUT(" New MAC Addr =%.2X %.2X %.2X ",
722 hw->mac.addr[0], hw->mac.addr[1],
724 DEBUGOUT("%.2X %.2X %.2X\n", hw->mac.addr[3],
725 hw->mac.addr[4], hw->mac.addr[5]);
727 hw->mac.set_rar(hw, 0, hw->mac.addr, 0, true);
730 /* clear VMDq pool/queue selection for RAR 0 */
731 hw->mac.clear_vmdq(hw, 0, BIT_MASK32);
733 hw->addr_ctrl.overflow_promisc = 0;
735 hw->addr_ctrl.rar_used_count = 1;
737 /* Zero out the other receive addresses. */
738 DEBUGOUT("Clearing RAR[1-%d]\n", rar_entries - 1);
739 for (i = 1; i < rar_entries; i++) {
740 wr32(hw, TXGBE_ETHADDRIDX, i);
741 wr32(hw, TXGBE_ETHADDRL, 0);
742 wr32(hw, TXGBE_ETHADDRH, 0);
746 hw->addr_ctrl.mta_in_use = 0;
747 psrctl = rd32(hw, TXGBE_PSRCTL);
748 psrctl &= ~(TXGBE_PSRCTL_ADHF12_MASK | TXGBE_PSRCTL_MCHFENA);
749 psrctl |= TXGBE_PSRCTL_ADHF12(hw->mac.mc_filter_type);
750 wr32(hw, TXGBE_PSRCTL, psrctl);
752 DEBUGOUT(" Clearing MTA\n");
753 for (i = 0; i < hw->mac.mcft_size; i++)
754 wr32(hw, TXGBE_MCADDRTBL(i), 0);
756 txgbe_init_uta_tables(hw);
762 * txgbe_mta_vector - Determines bit-vector in multicast table to set
763 * @hw: pointer to hardware structure
764 * @mc_addr: the multicast address
766 * Extracts the 12 bits, from a multicast address, to determine which
767 * bit-vector to set in the multicast table. The hardware uses 12 bits, from
768 * incoming rx multicast addresses, to determine the bit-vector to check in
769 * the MTA. Which of the 4 combination, of 12-bits, the hardware uses is set
770 * by the MO field of the PSRCTRL. The MO field is set during initialization
773 static s32 txgbe_mta_vector(struct txgbe_hw *hw, u8 *mc_addr)
777 DEBUGFUNC("txgbe_mta_vector");
779 switch (hw->mac.mc_filter_type) {
780 case 0: /* use bits [47:36] of the address */
781 vector = ((mc_addr[4] >> 4) | (((u16)mc_addr[5]) << 4));
783 case 1: /* use bits [46:35] of the address */
784 vector = ((mc_addr[4] >> 3) | (((u16)mc_addr[5]) << 5));
786 case 2: /* use bits [45:34] of the address */
787 vector = ((mc_addr[4] >> 2) | (((u16)mc_addr[5]) << 6));
789 case 3: /* use bits [43:32] of the address */
790 vector = ((mc_addr[4]) | (((u16)mc_addr[5]) << 8));
792 default: /* Invalid mc_filter_type */
793 DEBUGOUT("MC filter type param set incorrectly\n");
798 /* vector can only be 12-bits or boundary will be exceeded */
804 * txgbe_set_mta - Set bit-vector in multicast table
805 * @hw: pointer to hardware structure
806 * @mc_addr: Multicast address
808 * Sets the bit-vector in the multicast table.
810 void txgbe_set_mta(struct txgbe_hw *hw, u8 *mc_addr)
816 DEBUGFUNC("txgbe_set_mta");
818 hw->addr_ctrl.mta_in_use++;
820 vector = txgbe_mta_vector(hw, mc_addr);
821 DEBUGOUT(" bit-vector = 0x%03X\n", vector);
824 * The MTA is a register array of 128 32-bit registers. It is treated
825 * like an array of 4096 bits. We want to set bit
826 * BitArray[vector_value]. So we figure out what register the bit is
827 * in, read it, OR in the new bit, then write back the new value. The
828 * register is determined by the upper 7 bits of the vector value and
829 * the bit within that register are determined by the lower 5 bits of
832 vector_reg = (vector >> 5) & 0x7F;
833 vector_bit = vector & 0x1F;
834 hw->mac.mta_shadow[vector_reg] |= (1 << vector_bit);
838 * txgbe_update_mc_addr_list - Updates MAC list of multicast addresses
839 * @hw: pointer to hardware structure
840 * @mc_addr_list: the list of new multicast addresses
841 * @mc_addr_count: number of addresses
842 * @next: iterator function to walk the multicast address list
843 * @clear: flag, when set clears the table beforehand
845 * When the clear flag is set, the given list replaces any existing list.
846 * Hashes the given addresses into the multicast table.
848 s32 txgbe_update_mc_addr_list(struct txgbe_hw *hw, u8 *mc_addr_list,
849 u32 mc_addr_count, txgbe_mc_addr_itr next,
855 DEBUGFUNC("txgbe_update_mc_addr_list");
858 * Set the new number of MC addresses that we are being requested to
861 hw->addr_ctrl.num_mc_addrs = mc_addr_count;
862 hw->addr_ctrl.mta_in_use = 0;
864 /* Clear mta_shadow */
866 DEBUGOUT(" Clearing MTA\n");
867 memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow));
870 /* Update mta_shadow */
871 for (i = 0; i < mc_addr_count; i++) {
872 DEBUGOUT(" Adding the multicast addresses:\n");
873 txgbe_set_mta(hw, next(hw, &mc_addr_list, &vmdq));
877 for (i = 0; i < hw->mac.mcft_size; i++)
878 wr32a(hw, TXGBE_MCADDRTBL(0), i,
879 hw->mac.mta_shadow[i]);
881 if (hw->addr_ctrl.mta_in_use > 0) {
882 u32 psrctl = rd32(hw, TXGBE_PSRCTL);
883 psrctl &= ~(TXGBE_PSRCTL_ADHF12_MASK | TXGBE_PSRCTL_MCHFENA);
884 psrctl |= TXGBE_PSRCTL_MCHFENA |
885 TXGBE_PSRCTL_ADHF12(hw->mac.mc_filter_type);
886 wr32(hw, TXGBE_PSRCTL, psrctl);
889 DEBUGOUT("txgbe update mc addr list complete\n");
894 * txgbe_fc_enable - Enable flow control
895 * @hw: pointer to hardware structure
897 * Enable flow control according to the current settings.
899 s32 txgbe_fc_enable(struct txgbe_hw *hw)
902 u32 mflcn_reg, fccfg_reg;
907 DEBUGFUNC("txgbe_fc_enable");
909 /* Validate the water mark configuration */
910 if (!hw->fc.pause_time) {
911 err = TXGBE_ERR_INVALID_LINK_SETTINGS;
915 /* Low water mark of zero causes XOFF floods */
916 for (i = 0; i < TXGBE_DCB_TC_MAX; i++) {
917 if ((hw->fc.current_mode & txgbe_fc_tx_pause) &&
918 hw->fc.high_water[i]) {
919 if (!hw->fc.low_water[i] ||
920 hw->fc.low_water[i] >= hw->fc.high_water[i]) {
921 DEBUGOUT("Invalid water mark configuration\n");
922 err = TXGBE_ERR_INVALID_LINK_SETTINGS;
928 /* Negotiate the fc mode to use */
929 hw->mac.fc_autoneg(hw);
931 /* Disable any previous flow control settings */
932 mflcn_reg = rd32(hw, TXGBE_RXFCCFG);
933 mflcn_reg &= ~(TXGBE_RXFCCFG_FC | TXGBE_RXFCCFG_PFC);
935 fccfg_reg = rd32(hw, TXGBE_TXFCCFG);
936 fccfg_reg &= ~(TXGBE_TXFCCFG_FC | TXGBE_TXFCCFG_PFC);
939 * The possible values of fc.current_mode are:
940 * 0: Flow control is completely disabled
941 * 1: Rx flow control is enabled (we can receive pause frames,
942 * but not send pause frames).
943 * 2: Tx flow control is enabled (we can send pause frames but
944 * we do not support receiving pause frames).
945 * 3: Both Rx and Tx flow control (symmetric) are enabled.
948 switch (hw->fc.current_mode) {
951 * Flow control is disabled by software override or autoneg.
952 * The code below will actually disable it in the HW.
955 case txgbe_fc_rx_pause:
957 * Rx Flow control is enabled and Tx Flow control is
958 * disabled by software override. Since there really
959 * isn't a way to advertise that we are capable of RX
960 * Pause ONLY, we will advertise that we support both
961 * symmetric and asymmetric Rx PAUSE. Later, we will
962 * disable the adapter's ability to send PAUSE frames.
964 mflcn_reg |= TXGBE_RXFCCFG_FC;
966 case txgbe_fc_tx_pause:
968 * Tx Flow control is enabled, and Rx Flow control is
969 * disabled by software override.
971 fccfg_reg |= TXGBE_TXFCCFG_FC;
974 /* Flow control (both Rx and Tx) is enabled by SW override. */
975 mflcn_reg |= TXGBE_RXFCCFG_FC;
976 fccfg_reg |= TXGBE_TXFCCFG_FC;
979 DEBUGOUT("Flow control param set incorrectly\n");
980 err = TXGBE_ERR_CONFIG;
984 /* Set 802.3x based flow control settings. */
985 wr32(hw, TXGBE_RXFCCFG, mflcn_reg);
986 wr32(hw, TXGBE_TXFCCFG, fccfg_reg);
988 /* Set up and enable Rx high/low water mark thresholds, enable XON. */
989 for (i = 0; i < TXGBE_DCB_TC_MAX; i++) {
990 if ((hw->fc.current_mode & txgbe_fc_tx_pause) &&
991 hw->fc.high_water[i]) {
992 fcrtl = TXGBE_FCWTRLO_TH(hw->fc.low_water[i]) |
994 fcrth = TXGBE_FCWTRHI_TH(hw->fc.high_water[i]) |
998 * In order to prevent Tx hangs when the internal Tx
999 * switch is enabled we must set the high water mark
1000 * to the Rx packet buffer size - 24KB. This allows
1001 * the Tx switch to function even under heavy Rx
1005 fcrth = rd32(hw, TXGBE_PBRXSIZE(i)) - 24576;
1007 wr32(hw, TXGBE_FCWTRLO(i), fcrtl);
1008 wr32(hw, TXGBE_FCWTRHI(i), fcrth);
1011 /* Configure pause time (2 TCs per register) */
1012 pause_time = TXGBE_RXFCFSH_TIME(hw->fc.pause_time);
1013 for (i = 0; i < (TXGBE_DCB_TC_MAX / 2); i++)
1014 wr32(hw, TXGBE_FCXOFFTM(i), pause_time * 0x00010001);
1016 /* Configure flow control refresh threshold value */
1017 wr32(hw, TXGBE_RXFCRFSH, hw->fc.pause_time / 2);
1024 * txgbe_negotiate_fc - Negotiate flow control
1025 * @hw: pointer to hardware structure
1026 * @adv_reg: flow control advertised settings
1027 * @lp_reg: link partner's flow control settings
1028 * @adv_sym: symmetric pause bit in advertisement
1029 * @adv_asm: asymmetric pause bit in advertisement
1030 * @lp_sym: symmetric pause bit in link partner advertisement
1031 * @lp_asm: asymmetric pause bit in link partner advertisement
1033 * Find the intersection between advertised settings and link partner's
1034 * advertised settings
1036 s32 txgbe_negotiate_fc(struct txgbe_hw *hw, u32 adv_reg, u32 lp_reg,
1037 u32 adv_sym, u32 adv_asm, u32 lp_sym, u32 lp_asm)
1039 if ((!(adv_reg)) || (!(lp_reg))) {
1040 DEBUGOUT("Local or link partner's advertised flow control "
1041 "settings are NULL. Local: %x, link partner: %x\n",
1043 return TXGBE_ERR_FC_NOT_NEGOTIATED;
1046 if ((adv_reg & adv_sym) && (lp_reg & lp_sym)) {
1048 * Now we need to check if the user selected Rx ONLY
1049 * of pause frames. In this case, we had to advertise
1050 * FULL flow control because we could not advertise RX
1051 * ONLY. Hence, we must now check to see if we need to
1052 * turn OFF the TRANSMISSION of PAUSE frames.
1054 if (hw->fc.requested_mode == txgbe_fc_full) {
1055 hw->fc.current_mode = txgbe_fc_full;
1056 DEBUGOUT("Flow Control = FULL.\n");
1058 hw->fc.current_mode = txgbe_fc_rx_pause;
1059 DEBUGOUT("Flow Control=RX PAUSE frames only\n");
1061 } else if (!(adv_reg & adv_sym) && (adv_reg & adv_asm) &&
1062 (lp_reg & lp_sym) && (lp_reg & lp_asm)) {
1063 hw->fc.current_mode = txgbe_fc_tx_pause;
1064 DEBUGOUT("Flow Control = TX PAUSE frames only.\n");
1065 } else if ((adv_reg & adv_sym) && (adv_reg & adv_asm) &&
1066 !(lp_reg & lp_sym) && (lp_reg & lp_asm)) {
1067 hw->fc.current_mode = txgbe_fc_rx_pause;
1068 DEBUGOUT("Flow Control = RX PAUSE frames only.\n");
1070 hw->fc.current_mode = txgbe_fc_none;
1071 DEBUGOUT("Flow Control = NONE.\n");
1077 * txgbe_fc_autoneg_fiber - Enable flow control on 1 gig fiber
1078 * @hw: pointer to hardware structure
1080 * Enable flow control according on 1 gig fiber.
1082 STATIC s32 txgbe_fc_autoneg_fiber(struct txgbe_hw *hw)
1084 u32 pcs_anadv_reg, pcs_lpab_reg;
1085 s32 err = TXGBE_ERR_FC_NOT_NEGOTIATED;
1088 * On multispeed fiber at 1g, bail out if
1089 * - link is up but AN did not complete, or if
1090 * - link is up and AN completed but timed out
1093 pcs_anadv_reg = rd32_epcs(hw, SR_MII_MMD_AN_ADV);
1094 pcs_lpab_reg = rd32_epcs(hw, SR_MII_MMD_LP_BABL);
1096 err = txgbe_negotiate_fc(hw, pcs_anadv_reg,
1098 SR_MII_MMD_AN_ADV_PAUSE_SYM,
1099 SR_MII_MMD_AN_ADV_PAUSE_ASM,
1100 SR_MII_MMD_AN_ADV_PAUSE_SYM,
1101 SR_MII_MMD_AN_ADV_PAUSE_ASM);
1107 * txgbe_fc_autoneg_backplane - Enable flow control IEEE clause 37
1108 * @hw: pointer to hardware structure
1110 * Enable flow control according to IEEE clause 37.
1112 STATIC s32 txgbe_fc_autoneg_backplane(struct txgbe_hw *hw)
1114 u32 anlp1_reg, autoc_reg;
1115 s32 err = TXGBE_ERR_FC_NOT_NEGOTIATED;
1118 * Read the 10g AN autoc and LP ability registers and resolve
1119 * local flow control settings accordingly
1121 autoc_reg = rd32_epcs(hw, SR_AN_MMD_ADV_REG1);
1122 anlp1_reg = rd32_epcs(hw, SR_AN_MMD_LP_ABL1);
1124 err = txgbe_negotiate_fc(hw, autoc_reg,
1126 SR_AN_MMD_ADV_REG1_PAUSE_SYM,
1127 SR_AN_MMD_ADV_REG1_PAUSE_ASM,
1128 SR_AN_MMD_ADV_REG1_PAUSE_SYM,
1129 SR_AN_MMD_ADV_REG1_PAUSE_ASM);
1135 * txgbe_fc_autoneg_copper - Enable flow control IEEE clause 37
1136 * @hw: pointer to hardware structure
1138 * Enable flow control according to IEEE clause 37.
1140 STATIC s32 txgbe_fc_autoneg_copper(struct txgbe_hw *hw)
1142 u16 technology_ability_reg = 0;
1143 u16 lp_technology_ability_reg = 0;
1145 hw->phy.read_reg(hw, TXGBE_MD_AUTO_NEG_ADVT,
1146 TXGBE_MD_DEV_AUTO_NEG,
1147 &technology_ability_reg);
1148 hw->phy.read_reg(hw, TXGBE_MD_AUTO_NEG_LP,
1149 TXGBE_MD_DEV_AUTO_NEG,
1150 &lp_technology_ability_reg);
1152 return txgbe_negotiate_fc(hw, (u32)technology_ability_reg,
1153 (u32)lp_technology_ability_reg,
1154 TXGBE_TAF_SYM_PAUSE, TXGBE_TAF_ASM_PAUSE,
1155 TXGBE_TAF_SYM_PAUSE, TXGBE_TAF_ASM_PAUSE);
1159 * txgbe_fc_autoneg - Configure flow control
1160 * @hw: pointer to hardware structure
1162 * Compares our advertised flow control capabilities to those advertised by
1163 * our link partner, and determines the proper flow control mode to use.
1165 void txgbe_fc_autoneg(struct txgbe_hw *hw)
1167 s32 err = TXGBE_ERR_FC_NOT_NEGOTIATED;
1171 DEBUGFUNC("txgbe_fc_autoneg");
1174 * AN should have completed when the cable was plugged in.
1175 * Look for reasons to bail out. Bail out if:
1176 * - FC autoneg is disabled, or if
1179 if (hw->fc.disable_fc_autoneg) {
1180 DEBUGOUT("Flow control autoneg is disabled");
1184 hw->mac.check_link(hw, &speed, &link_up, false);
1186 DEBUGOUT("The link is down");
1190 switch (hw->phy.media_type) {
1191 /* Autoneg flow control on fiber adapters */
1192 case txgbe_media_type_fiber_qsfp:
1193 case txgbe_media_type_fiber:
1194 if (speed == TXGBE_LINK_SPEED_1GB_FULL)
1195 err = txgbe_fc_autoneg_fiber(hw);
1198 /* Autoneg flow control on backplane adapters */
1199 case txgbe_media_type_backplane:
1200 err = txgbe_fc_autoneg_backplane(hw);
1203 /* Autoneg flow control on copper adapters */
1204 case txgbe_media_type_copper:
1205 if (txgbe_device_supports_autoneg_fc(hw))
1206 err = txgbe_fc_autoneg_copper(hw);
1215 hw->fc.fc_was_autonegged = true;
1217 hw->fc.fc_was_autonegged = false;
1218 hw->fc.current_mode = hw->fc.requested_mode;
1223 * txgbe_acquire_swfw_sync - Acquire SWFW semaphore
1224 * @hw: pointer to hardware structure
1225 * @mask: Mask to specify which semaphore to acquire
1227 * Acquires the SWFW semaphore through the MNGSEM register for the specified
1228 * function (CSR, PHY0, PHY1, EEPROM, Flash)
1230 s32 txgbe_acquire_swfw_sync(struct txgbe_hw *hw, u32 mask)
1233 u32 swmask = TXGBE_MNGSEM_SW(mask);
1234 u32 fwmask = TXGBE_MNGSEM_FW(mask);
1238 DEBUGFUNC("txgbe_acquire_swfw_sync");
1240 for (i = 0; i < timeout; i++) {
1242 * SW NVM semaphore bit is used for access to all
1243 * SW_FW_SYNC bits (not just NVM)
1245 if (txgbe_get_eeprom_semaphore(hw))
1246 return TXGBE_ERR_SWFW_SYNC;
1248 mngsem = rd32(hw, TXGBE_MNGSEM);
1249 if (mngsem & (fwmask | swmask)) {
1250 /* Resource is currently in use by FW or SW */
1251 txgbe_release_eeprom_semaphore(hw);
1255 wr32(hw, TXGBE_MNGSEM, mngsem);
1256 txgbe_release_eeprom_semaphore(hw);
1261 /* If time expired clear the bits holding the lock and retry */
1262 if (mngsem & (fwmask | swmask))
1263 txgbe_release_swfw_sync(hw, mngsem & (fwmask | swmask));
1266 return TXGBE_ERR_SWFW_SYNC;
1270 * txgbe_release_swfw_sync - Release SWFW semaphore
1271 * @hw: pointer to hardware structure
1272 * @mask: Mask to specify which semaphore to release
1274 * Releases the SWFW semaphore through the MNGSEM register for the specified
1275 * function (CSR, PHY0, PHY1, EEPROM, Flash)
1277 void txgbe_release_swfw_sync(struct txgbe_hw *hw, u32 mask)
1282 DEBUGFUNC("txgbe_release_swfw_sync");
1284 txgbe_get_eeprom_semaphore(hw);
1286 mngsem = rd32(hw, TXGBE_MNGSEM);
1288 wr32(hw, TXGBE_MNGSEM, mngsem);
1290 txgbe_release_eeprom_semaphore(hw);
1294 * txgbe_disable_sec_rx_path - Stops the receive data path
1295 * @hw: pointer to hardware structure
1297 * Stops the receive data path and waits for the HW to internally empty
1298 * the Rx security block
1300 s32 txgbe_disable_sec_rx_path(struct txgbe_hw *hw)
1302 #define TXGBE_MAX_SECRX_POLL 4000
1307 DEBUGFUNC("txgbe_disable_sec_rx_path");
1309 secrxreg = rd32(hw, TXGBE_SECRXCTL);
1310 secrxreg |= TXGBE_SECRXCTL_XDSA;
1311 wr32(hw, TXGBE_SECRXCTL, secrxreg);
1312 for (i = 0; i < TXGBE_MAX_SECRX_POLL; i++) {
1313 secrxreg = rd32(hw, TXGBE_SECRXSTAT);
1314 if (!(secrxreg & TXGBE_SECRXSTAT_RDY))
1315 /* Use interrupt-safe sleep just in case */
1321 /* For informational purposes only */
1322 if (i >= TXGBE_MAX_SECRX_POLL)
1323 DEBUGOUT("Rx unit being enabled before security "
1324 "path fully disabled. Continuing with init.\n");
1330 * txgbe_enable_sec_rx_path - Enables the receive data path
1331 * @hw: pointer to hardware structure
1333 * Enables the receive data path.
1335 s32 txgbe_enable_sec_rx_path(struct txgbe_hw *hw)
1339 DEBUGFUNC("txgbe_enable_sec_rx_path");
1341 secrxreg = rd32(hw, TXGBE_SECRXCTL);
1342 secrxreg &= ~TXGBE_SECRXCTL_XDSA;
1343 wr32(hw, TXGBE_SECRXCTL, secrxreg);
1350 * txgbe_disable_sec_tx_path - Stops the transmit data path
1351 * @hw: pointer to hardware structure
1353 * Stops the transmit data path and waits for the HW to internally empty
1354 * the Tx security block
1356 int txgbe_disable_sec_tx_path(struct txgbe_hw *hw)
1358 #define TXGBE_MAX_SECTX_POLL 40
1363 sectxreg = rd32(hw, TXGBE_SECTXCTL);
1364 sectxreg |= TXGBE_SECTXCTL_XDSA;
1365 wr32(hw, TXGBE_SECTXCTL, sectxreg);
1366 for (i = 0; i < TXGBE_MAX_SECTX_POLL; i++) {
1367 sectxreg = rd32(hw, TXGBE_SECTXSTAT);
1368 if (sectxreg & TXGBE_SECTXSTAT_RDY)
1370 /* Use interrupt-safe sleep just in case */
1374 /* For informational purposes only */
1375 if (i >= TXGBE_MAX_SECTX_POLL)
1376 PMD_DRV_LOG(DEBUG, "Tx unit being enabled before security "
1377 "path fully disabled. Continuing with init.");
1383 * txgbe_enable_sec_tx_path - Enables the transmit data path
1384 * @hw: pointer to hardware structure
1386 * Enables the transmit data path.
1388 int txgbe_enable_sec_tx_path(struct txgbe_hw *hw)
1392 sectxreg = rd32(hw, TXGBE_SECTXCTL);
1393 sectxreg &= ~TXGBE_SECTXCTL_XDSA;
1394 wr32(hw, TXGBE_SECTXCTL, sectxreg);
1401 * txgbe_get_san_mac_addr_offset - Get SAN MAC address offset from the EEPROM
1402 * @hw: pointer to hardware structure
1403 * @san_mac_offset: SAN MAC address offset
1405 * This function will read the EEPROM location for the SAN MAC address
1406 * pointer, and returns the value at that location. This is used in both
1407 * get and set mac_addr routines.
1409 static s32 txgbe_get_san_mac_addr_offset(struct txgbe_hw *hw,
1410 u16 *san_mac_offset)
1414 DEBUGFUNC("txgbe_get_san_mac_addr_offset");
1417 * First read the EEPROM pointer to see if the MAC addresses are
1420 err = hw->rom.readw_sw(hw, TXGBE_SAN_MAC_ADDR_PTR,
1423 DEBUGOUT("eeprom at offset %d failed",
1424 TXGBE_SAN_MAC_ADDR_PTR);
1431 * txgbe_get_san_mac_addr - SAN MAC address retrieval from the EEPROM
1432 * @hw: pointer to hardware structure
1433 * @san_mac_addr: SAN MAC address
1435 * Reads the SAN MAC address from the EEPROM, if it's available. This is
1436 * per-port, so set_lan_id() must be called before reading the addresses.
1437 * set_lan_id() is called by identify_sfp(), but this cannot be relied
1438 * upon for non-SFP connections, so we must call it here.
1440 s32 txgbe_get_san_mac_addr(struct txgbe_hw *hw, u8 *san_mac_addr)
1442 u16 san_mac_data, san_mac_offset;
1446 DEBUGFUNC("txgbe_get_san_mac_addr");
1449 * First read the EEPROM pointer to see if the MAC addresses are
1450 * available. If they're not, no point in calling set_lan_id() here.
1452 err = txgbe_get_san_mac_addr_offset(hw, &san_mac_offset);
1453 if (err || san_mac_offset == 0 || san_mac_offset == 0xFFFF)
1454 goto san_mac_addr_out;
1456 /* apply the port offset to the address offset */
1457 (hw->bus.func) ? (san_mac_offset += TXGBE_SAN_MAC_ADDR_PORT1_OFFSET) :
1458 (san_mac_offset += TXGBE_SAN_MAC_ADDR_PORT0_OFFSET);
1459 for (i = 0; i < 3; i++) {
1460 err = hw->rom.read16(hw, san_mac_offset,
1463 DEBUGOUT("eeprom read at offset %d failed",
1465 goto san_mac_addr_out;
1467 san_mac_addr[i * 2] = (u8)(san_mac_data);
1468 san_mac_addr[i * 2 + 1] = (u8)(san_mac_data >> 8);
1475 * No addresses available in this EEPROM. It's not an
1476 * error though, so just wipe the local address and return.
1478 for (i = 0; i < 6; i++)
1479 san_mac_addr[i] = 0xFF;
1484 * txgbe_set_san_mac_addr - Write the SAN MAC address to the EEPROM
1485 * @hw: pointer to hardware structure
1486 * @san_mac_addr: SAN MAC address
1488 * Write a SAN MAC address to the EEPROM.
1490 s32 txgbe_set_san_mac_addr(struct txgbe_hw *hw, u8 *san_mac_addr)
1493 u16 san_mac_data, san_mac_offset;
1496 DEBUGFUNC("txgbe_set_san_mac_addr");
1498 /* Look for SAN mac address pointer. If not defined, return */
1499 err = txgbe_get_san_mac_addr_offset(hw, &san_mac_offset);
1500 if (err || san_mac_offset == 0 || san_mac_offset == 0xFFFF)
1501 return TXGBE_ERR_NO_SAN_ADDR_PTR;
1503 /* Apply the port offset to the address offset */
1504 (hw->bus.func) ? (san_mac_offset += TXGBE_SAN_MAC_ADDR_PORT1_OFFSET) :
1505 (san_mac_offset += TXGBE_SAN_MAC_ADDR_PORT0_OFFSET);
1507 for (i = 0; i < 3; i++) {
1508 san_mac_data = (u16)((u16)(san_mac_addr[i * 2 + 1]) << 8);
1509 san_mac_data |= (u16)(san_mac_addr[i * 2]);
1510 hw->rom.write16(hw, san_mac_offset, san_mac_data);
1518 * txgbe_clear_vmdq - Disassociate a VMDq pool index from a rx address
1519 * @hw: pointer to hardware struct
1520 * @rar: receive address register index to disassociate
1521 * @vmdq: VMDq pool index to remove from the rar
1523 s32 txgbe_clear_vmdq(struct txgbe_hw *hw, u32 rar, u32 vmdq)
1525 u32 mpsar_lo, mpsar_hi;
1526 u32 rar_entries = hw->mac.num_rar_entries;
1528 DEBUGFUNC("txgbe_clear_vmdq");
1530 /* Make sure we are using a valid rar index range */
1531 if (rar >= rar_entries) {
1532 DEBUGOUT("RAR index %d is out of range.\n", rar);
1533 return TXGBE_ERR_INVALID_ARGUMENT;
1536 wr32(hw, TXGBE_ETHADDRIDX, rar);
1537 mpsar_lo = rd32(hw, TXGBE_ETHADDRASSL);
1538 mpsar_hi = rd32(hw, TXGBE_ETHADDRASSH);
1540 if (TXGBE_REMOVED(hw->hw_addr))
1543 if (!mpsar_lo && !mpsar_hi)
1546 if (vmdq == BIT_MASK32) {
1548 wr32(hw, TXGBE_ETHADDRASSL, 0);
1552 wr32(hw, TXGBE_ETHADDRASSH, 0);
1555 } else if (vmdq < 32) {
1556 mpsar_lo &= ~(1 << vmdq);
1557 wr32(hw, TXGBE_ETHADDRASSL, mpsar_lo);
1559 mpsar_hi &= ~(1 << (vmdq - 32));
1560 wr32(hw, TXGBE_ETHADDRASSH, mpsar_hi);
1563 /* was that the last pool using this rar? */
1564 if (mpsar_lo == 0 && mpsar_hi == 0 &&
1565 rar != 0 && rar != hw->mac.san_mac_rar_index)
1566 hw->mac.clear_rar(hw, rar);
1572 * txgbe_set_vmdq - Associate a VMDq pool index with a rx address
1573 * @hw: pointer to hardware struct
1574 * @rar: receive address register index to associate with a VMDq index
1575 * @vmdq: VMDq pool index
1577 s32 txgbe_set_vmdq(struct txgbe_hw *hw, u32 rar, u32 vmdq)
1580 u32 rar_entries = hw->mac.num_rar_entries;
1582 DEBUGFUNC("txgbe_set_vmdq");
1584 /* Make sure we are using a valid rar index range */
1585 if (rar >= rar_entries) {
1586 DEBUGOUT("RAR index %d is out of range.\n", rar);
1587 return TXGBE_ERR_INVALID_ARGUMENT;
1590 wr32(hw, TXGBE_ETHADDRIDX, rar);
1592 mpsar = rd32(hw, TXGBE_ETHADDRASSL);
1594 wr32(hw, TXGBE_ETHADDRASSL, mpsar);
1596 mpsar = rd32(hw, TXGBE_ETHADDRASSH);
1597 mpsar |= 1 << (vmdq - 32);
1598 wr32(hw, TXGBE_ETHADDRASSH, mpsar);
1604 * txgbe_init_uta_tables - Initialize the Unicast Table Array
1605 * @hw: pointer to hardware structure
1607 s32 txgbe_init_uta_tables(struct txgbe_hw *hw)
1611 DEBUGFUNC("txgbe_init_uta_tables");
1612 DEBUGOUT(" Clearing UTA\n");
1614 for (i = 0; i < 128; i++)
1615 wr32(hw, TXGBE_UCADDRTBL(i), 0);
1621 * txgbe_find_vlvf_slot - find the vlanid or the first empty slot
1622 * @hw: pointer to hardware structure
1623 * @vlan: VLAN id to write to VLAN filter
1624 * @vlvf_bypass: true to find vlanid only, false returns first empty slot if
1628 * return the VLVF index where this VLAN id should be placed
1631 s32 txgbe_find_vlvf_slot(struct txgbe_hw *hw, u32 vlan, bool vlvf_bypass)
1633 s32 regindex, first_empty_slot;
1636 /* short cut the special case */
1640 /* if vlvf_bypass is set we don't want to use an empty slot, we
1641 * will simply bypass the VLVF if there are no entries present in the
1642 * VLVF that contain our VLAN
1644 first_empty_slot = vlvf_bypass ? TXGBE_ERR_NO_SPACE : 0;
1646 /* add VLAN enable bit for comparison */
1647 vlan |= TXGBE_PSRVLAN_EA;
1649 /* Search for the vlan id in the VLVF entries. Save off the first empty
1650 * slot found along the way.
1652 * pre-decrement loop covering (TXGBE_NUM_POOL - 1) .. 1
1654 for (regindex = TXGBE_NUM_POOL; --regindex;) {
1655 wr32(hw, TXGBE_PSRVLANIDX, regindex);
1656 bits = rd32(hw, TXGBE_PSRVLAN);
1659 if (!first_empty_slot && !bits)
1660 first_empty_slot = regindex;
1663 /* If we are here then we didn't find the VLAN. Return first empty
1664 * slot we found during our search, else error.
1666 if (!first_empty_slot)
1667 DEBUGOUT("No space in VLVF.\n");
1669 return first_empty_slot ? first_empty_slot : TXGBE_ERR_NO_SPACE;
1673 * txgbe_set_vfta - Set VLAN filter table
1674 * @hw: pointer to hardware structure
1675 * @vlan: VLAN id to write to VLAN filter
1676 * @vind: VMDq output index that maps queue to VLAN id in VLVFB
1677 * @vlan_on: boolean flag to turn on/off VLAN
1678 * @vlvf_bypass: boolean flag indicating updating default pool is okay
1680 * Turn on/off specified VLAN in the VLAN filter table.
1682 s32 txgbe_set_vfta(struct txgbe_hw *hw, u32 vlan, u32 vind,
1683 bool vlan_on, bool vlvf_bypass)
1685 u32 regidx, vfta_delta, vfta;
1688 DEBUGFUNC("txgbe_set_vfta");
1690 if (vlan > 4095 || vind > 63)
1691 return TXGBE_ERR_PARAM;
1694 * this is a 2 part operation - first the VFTA, then the
1695 * VLVF and VLVFB if VT Mode is set
1696 * We don't write the VFTA until we know the VLVF part succeeded.
1700 * The VFTA is a bitstring made up of 128 32-bit registers
1701 * that enable the particular VLAN id, much like the MTA:
1702 * bits[11-5]: which register
1703 * bits[4-0]: which bit in the register
1706 vfta_delta = 1 << (vlan % 32);
1707 vfta = rd32(hw, TXGBE_VLANTBL(regidx));
1710 * vfta_delta represents the difference between the current value
1711 * of vfta and the value we want in the register. Since the diff
1712 * is an XOR mask we can just update the vfta using an XOR
1714 vfta_delta &= vlan_on ? ~vfta : vfta;
1718 * Call txgbe_set_vlvf to set VLVFB and VLVF
1720 err = txgbe_set_vlvf(hw, vlan, vind, vlan_on, &vfta_delta,
1729 /* Update VFTA now that we are ready for traffic */
1731 wr32(hw, TXGBE_VLANTBL(regidx), vfta);
1737 * txgbe_set_vlvf - Set VLAN Pool Filter
1738 * @hw: pointer to hardware structure
1739 * @vlan: VLAN id to write to VLAN filter
1740 * @vind: VMDq output index that maps queue to VLAN id in PSRVLANPLM
1741 * @vlan_on: boolean flag to turn on/off VLAN in PSRVLAN
1742 * @vfta_delta: pointer to the difference between the current value
1743 * of PSRVLANPLM and the desired value
1744 * @vfta: the desired value of the VFTA
1745 * @vlvf_bypass: boolean flag indicating updating default pool is okay
1747 * Turn on/off specified bit in VLVF table.
1749 s32 txgbe_set_vlvf(struct txgbe_hw *hw, u32 vlan, u32 vind,
1750 bool vlan_on, u32 *vfta_delta, u32 vfta,
1757 DEBUGFUNC("txgbe_set_vlvf");
1759 if (vlan > 4095 || vind > 63)
1760 return TXGBE_ERR_PARAM;
1762 /* If VT Mode is set
1764 * make sure the vlan is in PSRVLAN
1765 * set the vind bit in the matching PSRVLANPLM
1767 * clear the pool bit and possibly the vind
1769 portctl = rd32(hw, TXGBE_PORTCTL);
1770 if (!(portctl & TXGBE_PORTCTL_NUMVT_MASK))
1773 vlvf_index = txgbe_find_vlvf_slot(hw, vlan, vlvf_bypass);
1777 wr32(hw, TXGBE_PSRVLANIDX, vlvf_index);
1778 bits = rd32(hw, TXGBE_PSRVLANPLM(vind / 32));
1780 /* set the pool bit */
1781 bits |= 1 << (vind % 32);
1785 /* clear the pool bit */
1786 bits ^= 1 << (vind % 32);
1789 !rd32(hw, TXGBE_PSRVLANPLM(vind / 32))) {
1790 /* Clear PSRVLANPLM first, then disable PSRVLAN. Otherwise
1791 * we run the risk of stray packets leaking into
1792 * the PF via the default pool
1795 wr32(hw, TXGBE_PSRVLANPLM(vlan / 32), vfta);
1797 /* disable VLVF and clear remaining bit from pool */
1798 wr32(hw, TXGBE_PSRVLAN, 0);
1799 wr32(hw, TXGBE_PSRVLANPLM(vind / 32), 0);
1804 /* If there are still bits set in the PSRVLANPLM registers
1805 * for the VLAN ID indicated we need to see if the
1806 * caller is requesting that we clear the PSRVLANPLM entry bit.
1807 * If the caller has requested that we clear the PSRVLANPLM
1808 * entry bit but there are still pools/VFs using this VLAN
1809 * ID entry then ignore the request. We're not worried
1810 * about the case where we're turning the PSRVLANPLM VLAN ID
1811 * entry bit on, only when requested to turn it off as
1812 * there may be multiple pools and/or VFs using the
1813 * VLAN ID entry. In that case we cannot clear the
1814 * PSRVLANPLM bit until all pools/VFs using that VLAN ID have also
1815 * been cleared. This will be indicated by "bits" being
1821 /* record pool change and enable VLAN ID if not already enabled */
1822 wr32(hw, TXGBE_PSRVLANPLM(vind / 32), bits);
1823 wr32(hw, TXGBE_PSRVLAN, TXGBE_PSRVLAN_EA | vlan);
1829 * txgbe_clear_vfta - Clear VLAN filter table
1830 * @hw: pointer to hardware structure
1832 * Clears the VLAN filer table, and the VMDq index associated with the filter
1834 s32 txgbe_clear_vfta(struct txgbe_hw *hw)
1838 DEBUGFUNC("txgbe_clear_vfta");
1840 for (offset = 0; offset < hw->mac.vft_size; offset++)
1841 wr32(hw, TXGBE_VLANTBL(offset), 0);
1843 for (offset = 0; offset < TXGBE_NUM_POOL; offset++) {
1844 wr32(hw, TXGBE_PSRVLANIDX, offset);
1845 wr32(hw, TXGBE_PSRVLAN, 0);
1846 wr32(hw, TXGBE_PSRVLANPLM(0), 0);
1847 wr32(hw, TXGBE_PSRVLANPLM(1), 0);
1854 * txgbe_need_crosstalk_fix - Determine if we need to do cross talk fix
1855 * @hw: pointer to hardware structure
1857 * Contains the logic to identify if we need to verify link for the
1860 static bool txgbe_need_crosstalk_fix(struct txgbe_hw *hw)
1862 /* Does FW say we need the fix */
1863 if (!hw->need_crosstalk_fix)
1866 /* Only consider SFP+ PHYs i.e. media type fiber */
1867 switch (hw->phy.media_type) {
1868 case txgbe_media_type_fiber:
1869 case txgbe_media_type_fiber_qsfp:
1879 * txgbe_check_mac_link - Determine link and speed status
1880 * @hw: pointer to hardware structure
1881 * @speed: pointer to link speed
1882 * @link_up: true when link is up
1883 * @link_up_wait_to_complete: bool used to wait for link up or not
1885 * Reads the links register to determine if link is up and the current speed
1887 s32 txgbe_check_mac_link(struct txgbe_hw *hw, u32 *speed,
1888 bool *link_up, bool link_up_wait_to_complete)
1890 u32 links_reg, links_orig;
1893 DEBUGFUNC("txgbe_check_mac_link");
1895 /* If Crosstalk fix enabled do the sanity check of making sure
1896 * the SFP+ cage is full.
1898 if (txgbe_need_crosstalk_fix(hw)) {
1901 switch (hw->mac.type) {
1902 case txgbe_mac_raptor:
1903 sfp_cage_full = !rd32m(hw, TXGBE_GPIODATA,
1907 /* sanity check - No SFP+ devices here */
1908 sfp_cage_full = false;
1912 if (!sfp_cage_full) {
1914 *speed = TXGBE_LINK_SPEED_UNKNOWN;
1919 /* clear the old state */
1920 links_orig = rd32(hw, TXGBE_PORTSTAT);
1922 links_reg = rd32(hw, TXGBE_PORTSTAT);
1924 if (links_orig != links_reg) {
1925 DEBUGOUT("LINKS changed from %08X to %08X\n",
1926 links_orig, links_reg);
1929 if (link_up_wait_to_complete) {
1930 for (i = 0; i < hw->mac.max_link_up_time; i++) {
1931 if (!(links_reg & TXGBE_PORTSTAT_UP)) {
1938 links_reg = rd32(hw, TXGBE_PORTSTAT);
1941 if (links_reg & TXGBE_PORTSTAT_UP)
1947 switch (links_reg & TXGBE_PORTSTAT_BW_MASK) {
1948 case TXGBE_PORTSTAT_BW_10G:
1949 *speed = TXGBE_LINK_SPEED_10GB_FULL;
1951 case TXGBE_PORTSTAT_BW_1G:
1952 *speed = TXGBE_LINK_SPEED_1GB_FULL;
1954 case TXGBE_PORTSTAT_BW_100M:
1955 *speed = TXGBE_LINK_SPEED_100M_FULL;
1958 *speed = TXGBE_LINK_SPEED_UNKNOWN;
1965 * txgbe_get_wwn_prefix - Get alternative WWNN/WWPN prefix from
1967 * @hw: pointer to hardware structure
1968 * @wwnn_prefix: the alternative WWNN prefix
1969 * @wwpn_prefix: the alternative WWPN prefix
1971 * This function will read the EEPROM from the alternative SAN MAC address
1972 * block to check the support for the alternative WWNN/WWPN prefix support.
1974 s32 txgbe_get_wwn_prefix(struct txgbe_hw *hw, u16 *wwnn_prefix,
1978 u16 alt_san_mac_blk_offset;
1980 DEBUGFUNC("txgbe_get_wwn_prefix");
1982 /* clear output first */
1983 *wwnn_prefix = 0xFFFF;
1984 *wwpn_prefix = 0xFFFF;
1986 /* check if alternative SAN MAC is supported */
1987 offset = TXGBE_ALT_SAN_MAC_ADDR_BLK_PTR;
1988 if (hw->rom.readw_sw(hw, offset, &alt_san_mac_blk_offset))
1989 goto wwn_prefix_err;
1991 if (alt_san_mac_blk_offset == 0 || alt_san_mac_blk_offset == 0xFFFF)
1992 goto wwn_prefix_out;
1994 /* check capability in alternative san mac address block */
1995 offset = alt_san_mac_blk_offset + TXGBE_ALT_SAN_MAC_ADDR_CAPS_OFFSET;
1996 if (hw->rom.read16(hw, offset, &caps))
1997 goto wwn_prefix_err;
1998 if (!(caps & TXGBE_ALT_SAN_MAC_ADDR_CAPS_ALTWWN))
1999 goto wwn_prefix_out;
2001 /* get the corresponding prefix for WWNN/WWPN */
2002 offset = alt_san_mac_blk_offset + TXGBE_ALT_SAN_MAC_ADDR_WWNN_OFFSET;
2003 if (hw->rom.read16(hw, offset, wwnn_prefix))
2004 DEBUGOUT("eeprom read at offset %d failed", offset);
2006 offset = alt_san_mac_blk_offset + TXGBE_ALT_SAN_MAC_ADDR_WWPN_OFFSET;
2007 if (hw->rom.read16(hw, offset, wwpn_prefix))
2008 goto wwn_prefix_err;
2014 DEBUGOUT("eeprom read at offset %d failed", offset);
2019 * txgbe_set_mac_anti_spoofing - Enable/Disable MAC anti-spoofing
2020 * @hw: pointer to hardware structure
2021 * @enable: enable or disable switch for MAC anti-spoofing
2022 * @vf: Virtual Function pool - VF Pool to set for MAC anti-spoofing
2025 void txgbe_set_mac_anti_spoofing(struct txgbe_hw *hw, bool enable, int vf)
2027 int vf_target_reg = vf >> 3;
2028 int vf_target_shift = vf % 8;
2031 pfvfspoof = rd32(hw, TXGBE_POOLTXASMAC(vf_target_reg));
2033 pfvfspoof |= (1 << vf_target_shift);
2035 pfvfspoof &= ~(1 << vf_target_shift);
2036 wr32(hw, TXGBE_POOLTXASMAC(vf_target_reg), pfvfspoof);
2040 * txgbe_set_ethertype_anti_spoofing - Configure Ethertype anti-spoofing
2041 * @hw: pointer to hardware structure
2042 * @enable: enable or disable switch for Ethertype anti-spoofing
2043 * @vf: Virtual Function pool - VF Pool to set for Ethertype anti-spoofing
2046 void txgbe_set_ethertype_anti_spoofing(struct txgbe_hw *hw,
2047 bool enable, int vf)
2049 int vf_target_reg = vf >> 3;
2050 int vf_target_shift = vf % 8;
2053 pfvfspoof = rd32(hw, TXGBE_POOLTXASET(vf_target_reg));
2055 pfvfspoof |= (1 << vf_target_shift);
2057 pfvfspoof &= ~(1 << vf_target_shift);
2058 wr32(hw, TXGBE_POOLTXASET(vf_target_reg), pfvfspoof);
2062 * txgbe_get_device_caps - Get additional device capabilities
2063 * @hw: pointer to hardware structure
2064 * @device_caps: the EEPROM word with the extra device capabilities
2066 * This function will read the EEPROM location for the device capabilities,
2067 * and return the word through device_caps.
2069 s32 txgbe_get_device_caps(struct txgbe_hw *hw, u16 *device_caps)
2071 DEBUGFUNC("txgbe_get_device_caps");
2073 hw->rom.readw_sw(hw, TXGBE_DEVICE_CAPS, device_caps);
2079 * txgbe_set_pba - Initialize Rx packet buffer
2080 * @hw: pointer to hardware structure
2081 * @num_pb: number of packet buffers to allocate
2082 * @headroom: reserve n KB of headroom
2083 * @strategy: packet buffer allocation strategy
2085 void txgbe_set_pba(struct txgbe_hw *hw, int num_pb, u32 headroom,
2088 u32 pbsize = hw->mac.rx_pb_size;
2090 u32 rxpktsize, txpktsize, txpbthresh;
2092 UNREFERENCED_PARAMETER(hw);
2094 /* Reserve headroom */
2100 /* Divide remaining packet buffer space amongst the number of packet
2101 * buffers requested using supplied strategy.
2104 case PBA_STRATEGY_WEIGHTED:
2105 /* txgbe_dcb_pba_80_48 strategy weight first half of packet
2106 * buffer with 5/8 of the packet buffer space.
2108 rxpktsize = (pbsize * 5) / (num_pb * 4);
2109 pbsize -= rxpktsize * (num_pb / 2);
2111 for (; i < (num_pb / 2); i++)
2112 wr32(hw, TXGBE_PBRXSIZE(i), rxpktsize);
2113 /* fall through - configure remaining packet buffers */
2114 case PBA_STRATEGY_EQUAL:
2115 rxpktsize = (pbsize / (num_pb - i));
2117 for (; i < num_pb; i++)
2118 wr32(hw, TXGBE_PBRXSIZE(i), rxpktsize);
2124 /* Only support an equally distributed Tx packet buffer strategy. */
2125 txpktsize = TXGBE_PBTXSIZE_MAX / num_pb;
2126 txpbthresh = (txpktsize / 1024) - TXGBE_TXPKT_SIZE_MAX;
2127 for (i = 0; i < num_pb; i++) {
2128 wr32(hw, TXGBE_PBTXSIZE(i), txpktsize);
2129 wr32(hw, TXGBE_PBTXDMATH(i), txpbthresh);
2132 /* Clear unused TCs, if any, to zero buffer size*/
2133 for (; i < TXGBE_MAX_UP; i++) {
2134 wr32(hw, TXGBE_PBRXSIZE(i), 0);
2135 wr32(hw, TXGBE_PBTXSIZE(i), 0);
2136 wr32(hw, TXGBE_PBTXDMATH(i), 0);
2141 * txgbe_clear_tx_pending - Clear pending TX work from the PCIe fifo
2142 * @hw: pointer to the hardware structure
2144 * The MACs can experience issues if TX work is still pending
2145 * when a reset occurs. This function prevents this by flushing the PCIe
2146 * buffers on the system.
2148 void txgbe_clear_tx_pending(struct txgbe_hw *hw)
2150 u32 hlreg0, i, poll;
2153 * If double reset is not requested then all transactions should
2154 * already be clear and as such there is no work to do
2156 if (!(hw->mac.flags & TXGBE_FLAGS_DOUBLE_RESET_REQUIRED))
2159 hlreg0 = rd32(hw, TXGBE_PSRCTL);
2160 wr32(hw, TXGBE_PSRCTL, hlreg0 | TXGBE_PSRCTL_LBENA);
2162 /* Wait for a last completion before clearing buffers */
2167 * Before proceeding, make sure that the PCIe block does not have
2168 * transactions pending.
2170 poll = (800 * 11) / 10;
2171 for (i = 0; i < poll; i++)
2174 /* Flush all writes and allow 20usec for all transactions to clear */
2178 /* restore previous register values */
2179 wr32(hw, TXGBE_PSRCTL, hlreg0);
2183 * txgbe_get_thermal_sensor_data - Gathers thermal sensor data
2184 * @hw: pointer to hardware structure
2186 * Returns the thermal sensor data structure
2188 s32 txgbe_get_thermal_sensor_data(struct txgbe_hw *hw)
2190 struct txgbe_thermal_sensor_data *data = &hw->mac.thermal_sensor_data;
2194 DEBUGFUNC("txgbe_get_thermal_sensor_data");
2196 /* Only support thermal sensors attached to physical port 0 */
2197 if (hw->bus.lan_id != 0)
2198 return TXGBE_NOT_IMPLEMENTED;
2200 ts_stat = rd32(hw, TXGBE_TSSTAT);
2201 tsv = (s64)TXGBE_TSSTAT_DATA(ts_stat);
2202 tsv = tsv > 1200 ? tsv : 1200;
2203 tsv = -(48380 << 8) / 1000
2204 + tsv * (31020 << 8) / 100000
2205 - tsv * tsv * (18201 << 8) / 100000000
2206 + tsv * tsv * tsv * (81542 << 8) / 1000000000000
2207 - tsv * tsv * tsv * tsv * (16743 << 8) / 1000000000000000;
2210 data->sensor[0].temp = (s16)tsv;
2216 * txgbe_init_thermal_sensor_thresh - Inits thermal sensor thresholds
2217 * @hw: pointer to hardware structure
2219 * Inits the thermal sensor thresholds according to the NVM map
2220 * and save off the threshold and location values into mac.thermal_sensor_data
2222 s32 txgbe_init_thermal_sensor_thresh(struct txgbe_hw *hw)
2224 struct txgbe_thermal_sensor_data *data = &hw->mac.thermal_sensor_data;
2226 DEBUGFUNC("txgbe_init_thermal_sensor_thresh");
2228 memset(data, 0, sizeof(struct txgbe_thermal_sensor_data));
2230 if (hw->bus.lan_id != 0)
2231 return TXGBE_NOT_IMPLEMENTED;
2233 wr32(hw, TXGBE_TSCTRL, TXGBE_TSCTRL_EVALMD);
2234 wr32(hw, TXGBE_TSINTR,
2235 TXGBE_TSINTR_AEN | TXGBE_TSINTR_DEN);
2236 wr32(hw, TXGBE_TSEN, TXGBE_TSEN_ENA);
2239 data->sensor[0].alarm_thresh = 100;
2240 wr32(hw, TXGBE_TSATHRE, 677);
2241 data->sensor[0].dalarm_thresh = 90;
2242 wr32(hw, TXGBE_TSDTHRE, 614);
2247 void txgbe_disable_rx(struct txgbe_hw *hw)
2251 pfdtxgswc = rd32(hw, TXGBE_PSRCTL);
2252 if (pfdtxgswc & TXGBE_PSRCTL_LBENA) {
2253 pfdtxgswc &= ~TXGBE_PSRCTL_LBENA;
2254 wr32(hw, TXGBE_PSRCTL, pfdtxgswc);
2255 hw->mac.set_lben = true;
2257 hw->mac.set_lben = false;
2260 wr32m(hw, TXGBE_PBRXCTL, TXGBE_PBRXCTL_ENA, 0);
2261 wr32m(hw, TXGBE_MACRXCFG, TXGBE_MACRXCFG_ENA, 0);
2264 void txgbe_enable_rx(struct txgbe_hw *hw)
2268 wr32m(hw, TXGBE_MACRXCFG, TXGBE_MACRXCFG_ENA, TXGBE_MACRXCFG_ENA);
2269 wr32m(hw, TXGBE_PBRXCTL, TXGBE_PBRXCTL_ENA, TXGBE_PBRXCTL_ENA);
2271 if (hw->mac.set_lben) {
2272 pfdtxgswc = rd32(hw, TXGBE_PSRCTL);
2273 pfdtxgswc |= TXGBE_PSRCTL_LBENA;
2274 wr32(hw, TXGBE_PSRCTL, pfdtxgswc);
2275 hw->mac.set_lben = false;
2280 * txgbe_setup_mac_link_multispeed_fiber - Set MAC link speed
2281 * @hw: pointer to hardware structure
2282 * @speed: new link speed
2283 * @autoneg_wait_to_complete: true when waiting for completion is needed
2285 * Set the link speed in the MAC and/or PHY register and restarts link.
2287 s32 txgbe_setup_mac_link_multispeed_fiber(struct txgbe_hw *hw,
2289 bool autoneg_wait_to_complete)
2291 u32 link_speed = TXGBE_LINK_SPEED_UNKNOWN;
2292 u32 highest_link_speed = TXGBE_LINK_SPEED_UNKNOWN;
2296 bool autoneg, link_up = false;
2298 DEBUGFUNC("txgbe_setup_mac_link_multispeed_fiber");
2300 /* Mask off requested but non-supported speeds */
2301 status = hw->mac.get_link_capabilities(hw, &link_speed, &autoneg);
2305 speed &= link_speed;
2307 /* Try each speed one by one, highest priority first. We do this in
2308 * software because 10Gb fiber doesn't support speed autonegotiation.
2310 if (speed & TXGBE_LINK_SPEED_10GB_FULL) {
2312 highest_link_speed = TXGBE_LINK_SPEED_10GB_FULL;
2314 /* Set the module link speed */
2315 switch (hw->phy.media_type) {
2316 case txgbe_media_type_fiber:
2317 hw->mac.set_rate_select_speed(hw,
2318 TXGBE_LINK_SPEED_10GB_FULL);
2320 case txgbe_media_type_fiber_qsfp:
2321 /* QSFP module automatically detects MAC link speed */
2324 DEBUGOUT("Unexpected media type.\n");
2328 /* Allow module to change analog characteristics (1G->10G) */
2331 status = hw->mac.setup_mac_link(hw,
2332 TXGBE_LINK_SPEED_10GB_FULL,
2333 autoneg_wait_to_complete);
2337 /* Flap the Tx laser if it has not already been done */
2338 hw->mac.flap_tx_laser(hw);
2340 /* Wait for the controller to acquire link. Per IEEE 802.3ap,
2341 * Section 73.10.2, we may have to wait up to 500ms if KR is
2342 * attempted. uses the same timing for 10g SFI.
2344 for (i = 0; i < 5; i++) {
2345 /* Wait for the link partner to also set speed */
2348 /* If we have link, just jump out */
2349 status = hw->mac.check_link(hw, &link_speed,
2359 if (speed & TXGBE_LINK_SPEED_1GB_FULL) {
2361 if (highest_link_speed == TXGBE_LINK_SPEED_UNKNOWN)
2362 highest_link_speed = TXGBE_LINK_SPEED_1GB_FULL;
2364 /* Set the module link speed */
2365 switch (hw->phy.media_type) {
2366 case txgbe_media_type_fiber:
2367 hw->mac.set_rate_select_speed(hw,
2368 TXGBE_LINK_SPEED_1GB_FULL);
2370 case txgbe_media_type_fiber_qsfp:
2371 /* QSFP module automatically detects link speed */
2374 DEBUGOUT("Unexpected media type.\n");
2378 /* Allow module to change analog characteristics (10G->1G) */
2381 status = hw->mac.setup_mac_link(hw,
2382 TXGBE_LINK_SPEED_1GB_FULL,
2383 autoneg_wait_to_complete);
2387 /* Flap the Tx laser if it has not already been done */
2388 hw->mac.flap_tx_laser(hw);
2390 /* Wait for the link partner to also set speed */
2393 /* If we have link, just jump out */
2394 status = hw->mac.check_link(hw, &link_speed, &link_up, false);
2402 /* We didn't get link. Configure back to the highest speed we tried,
2403 * (if there was more than one). We call ourselves back with just the
2404 * single highest speed that the user requested.
2407 status = txgbe_setup_mac_link_multispeed_fiber(hw,
2409 autoneg_wait_to_complete);
2412 /* Set autoneg_advertised value based on input link speed */
2413 hw->phy.autoneg_advertised = 0;
2415 if (speed & TXGBE_LINK_SPEED_10GB_FULL)
2416 hw->phy.autoneg_advertised |= TXGBE_LINK_SPEED_10GB_FULL;
2418 if (speed & TXGBE_LINK_SPEED_1GB_FULL)
2419 hw->phy.autoneg_advertised |= TXGBE_LINK_SPEED_1GB_FULL;
2425 * txgbe_init_shared_code - Initialize the shared code
2426 * @hw: pointer to hardware structure
2428 * This will assign function pointers and assign the MAC type and PHY code.
2429 * Does not touch the hardware. This function must be called prior to any
2430 * other function in the shared code. The txgbe_hw structure should be
2431 * memset to 0 prior to calling this function. The following fields in
2432 * hw structure should be filled in prior to calling this function:
2433 * hw_addr, back, device_id, vendor_id, subsystem_device_id,
2434 * subsystem_vendor_id, and revision_id
2436 s32 txgbe_init_shared_code(struct txgbe_hw *hw)
2440 DEBUGFUNC("txgbe_init_shared_code");
2445 txgbe_set_mac_type(hw);
2447 txgbe_init_ops_dummy(hw);
2448 switch (hw->mac.type) {
2449 case txgbe_mac_raptor:
2450 status = txgbe_init_ops_pf(hw);
2452 case txgbe_mac_raptor_vf:
2453 status = txgbe_init_ops_vf(hw);
2456 status = TXGBE_ERR_DEVICE_NOT_SUPPORTED;
2459 hw->mac.max_link_up_time = TXGBE_LINK_UP_TIME;
2461 hw->bus.set_lan_id(hw);
2467 * txgbe_set_mac_type - Sets MAC type
2468 * @hw: pointer to the HW structure
2470 * This function sets the mac type of the adapter based on the
2471 * vendor ID and device ID stored in the hw structure.
2473 s32 txgbe_set_mac_type(struct txgbe_hw *hw)
2477 DEBUGFUNC("txgbe_set_mac_type");
2479 if (hw->vendor_id != PCI_VENDOR_ID_WANGXUN) {
2480 DEBUGOUT("Unsupported vendor id: %x", hw->vendor_id);
2481 return TXGBE_ERR_DEVICE_NOT_SUPPORTED;
2484 switch (hw->device_id) {
2485 case TXGBE_DEV_ID_SP1000:
2486 case TXGBE_DEV_ID_WX1820:
2487 hw->mac.type = txgbe_mac_raptor;
2489 case TXGBE_DEV_ID_SP1000_VF:
2490 case TXGBE_DEV_ID_WX1820_VF:
2491 hw->phy.media_type = txgbe_media_type_virtual;
2492 hw->mac.type = txgbe_mac_raptor_vf;
2495 err = TXGBE_ERR_DEVICE_NOT_SUPPORTED;
2496 DEBUGOUT("Unsupported device id: %x", hw->device_id);
2500 DEBUGOUT("found mac: %d, returns: %d\n",
2505 void txgbe_init_mac_link_ops(struct txgbe_hw *hw)
2507 struct txgbe_mac_info *mac = &hw->mac;
2509 DEBUGFUNC("txgbe_init_mac_link_ops");
2512 * enable the laser control functions for SFP+ fiber
2513 * and MNG not enabled
2515 if (hw->phy.media_type == txgbe_media_type_fiber &&
2516 !txgbe_mng_enabled(hw)) {
2517 mac->disable_tx_laser =
2518 txgbe_disable_tx_laser_multispeed_fiber;
2519 mac->enable_tx_laser =
2520 txgbe_enable_tx_laser_multispeed_fiber;
2521 mac->flap_tx_laser =
2522 txgbe_flap_tx_laser_multispeed_fiber;
2525 if ((hw->phy.media_type == txgbe_media_type_fiber ||
2526 hw->phy.media_type == txgbe_media_type_fiber_qsfp) &&
2527 hw->phy.multispeed_fiber) {
2528 /* Set up dual speed SFP+ support */
2529 mac->setup_link = txgbe_setup_mac_link_multispeed_fiber;
2530 mac->setup_mac_link = txgbe_setup_mac_link;
2531 mac->set_rate_select_speed = txgbe_set_hard_rate_select_speed;
2533 mac->setup_link = txgbe_setup_mac_link;
2534 mac->set_rate_select_speed = txgbe_set_hard_rate_select_speed;
2539 * txgbe_init_phy_raptor - PHY/SFP specific init
2540 * @hw: pointer to hardware structure
2542 * Initialize any function pointers that were not able to be
2543 * set during init_shared_code because the PHY/SFP type was
2544 * not known. Perform the SFP init if necessary.
2547 s32 txgbe_init_phy_raptor(struct txgbe_hw *hw)
2549 struct txgbe_mac_info *mac = &hw->mac;
2550 struct txgbe_phy_info *phy = &hw->phy;
2553 DEBUGFUNC("txgbe_init_phy_raptor");
2555 if ((hw->device_id & 0xFF) == TXGBE_DEV_ID_QSFP) {
2556 /* Store flag indicating I2C bus access control unit. */
2557 hw->phy.qsfp_shared_i2c_bus = TRUE;
2559 /* Initialize access to QSFP+ I2C bus */
2563 /* Identify the PHY or SFP module */
2564 err = phy->identify(hw);
2565 if (err == TXGBE_ERR_SFP_NOT_SUPPORTED)
2566 goto init_phy_ops_out;
2568 /* Setup function pointers based on detected SFP module and speeds */
2569 txgbe_init_mac_link_ops(hw);
2571 /* If copper media, overwrite with copper function pointers */
2572 if (phy->media_type == txgbe_media_type_copper) {
2573 mac->setup_link = txgbe_setup_copper_link_raptor;
2574 mac->get_link_capabilities =
2575 txgbe_get_copper_link_capabilities;
2578 if (phy->media_type == txgbe_media_type_backplane) {
2579 mac->kr_handle = txgbe_kr_handle;
2580 mac->bp_down_event = txgbe_bp_down_event;
2583 /* Set necessary function pointers based on PHY type */
2584 switch (hw->phy.type) {
2586 phy->setup_link = txgbe_setup_phy_link_tnx;
2587 phy->check_link = txgbe_check_phy_link_tnx;
2597 s32 txgbe_setup_sfp_modules(struct txgbe_hw *hw)
2601 DEBUGFUNC("txgbe_setup_sfp_modules");
2603 if (hw->phy.sfp_type == txgbe_sfp_type_unknown)
2606 txgbe_init_mac_link_ops(hw);
2608 /* PHY config will finish before releasing the semaphore */
2609 err = hw->mac.acquire_swfw_sync(hw, TXGBE_MNGSEM_SWPHY);
2611 return TXGBE_ERR_SWFW_SYNC;
2613 /* Release the semaphore */
2614 hw->mac.release_swfw_sync(hw, TXGBE_MNGSEM_SWPHY);
2616 /* Delay obtaining semaphore again to allow FW access
2617 * prot_autoc_write uses the semaphore too.
2619 msec_delay(hw->rom.semaphore_delay);
2622 DEBUGOUT("sfp module setup not complete\n");
2623 return TXGBE_ERR_SFP_SETUP_NOT_COMPLETE;
2630 * txgbe_prot_autoc_read_raptor - Hides MAC differences needed for AUTOC read
2631 * @hw: pointer to hardware structure
2632 * @locked: Return the if we locked for this read.
2633 * @value: Value we read from AUTOC
2635 * For this part we need to wrap read-modify-writes with a possible
2636 * FW/SW lock. It is assumed this lock will be freed with the next
2637 * prot_autoc_write_raptor().
2639 s32 txgbe_prot_autoc_read_raptor(struct txgbe_hw *hw, bool *locked, u64 *value)
2642 bool lock_state = false;
2644 /* If LESM is on then we need to hold the SW/FW semaphore. */
2645 if (txgbe_verify_lesm_fw_enabled_raptor(hw)) {
2646 err = hw->mac.acquire_swfw_sync(hw,
2647 TXGBE_MNGSEM_SWPHY);
2649 return TXGBE_ERR_SWFW_SYNC;
2655 *locked = lock_state;
2657 *value = txgbe_autoc_read(hw);
2662 * txgbe_prot_autoc_write_raptor - Hides MAC differences needed for AUTOC write
2663 * @hw: pointer to hardware structure
2664 * @autoc: value to write to AUTOC
2665 * @locked: bool to indicate whether the SW/FW lock was already taken by
2666 * previous prot_autoc_read_raptor.
2668 * This part may need to hold the SW/FW lock around all writes to
2669 * AUTOC. Likewise after a write we need to do a pipeline reset.
2671 s32 txgbe_prot_autoc_write_raptor(struct txgbe_hw *hw, bool locked, u64 autoc)
2675 /* Blocked by MNG FW so bail */
2676 if (txgbe_check_reset_blocked(hw))
2679 /* We only need to get the lock if:
2680 * - We didn't do it already (in the read part of a read-modify-write)
2681 * - LESM is enabled.
2683 if (!locked && txgbe_verify_lesm_fw_enabled_raptor(hw)) {
2684 err = hw->mac.acquire_swfw_sync(hw,
2685 TXGBE_MNGSEM_SWPHY);
2687 return TXGBE_ERR_SWFW_SYNC;
2692 txgbe_autoc_write(hw, autoc);
2693 err = txgbe_reset_pipeline_raptor(hw);
2696 /* Free the SW/FW semaphore as we either grabbed it here or
2697 * already had it when this function was called.
2700 hw->mac.release_swfw_sync(hw, TXGBE_MNGSEM_SWPHY);
2706 * txgbe_init_ops_pf - Inits func ptrs and MAC type
2707 * @hw: pointer to hardware structure
2709 * Initialize the function pointers and assign the MAC type.
2710 * Does not touch the hardware.
2712 s32 txgbe_init_ops_pf(struct txgbe_hw *hw)
2714 struct txgbe_bus_info *bus = &hw->bus;
2715 struct txgbe_mac_info *mac = &hw->mac;
2716 struct txgbe_phy_info *phy = &hw->phy;
2717 struct txgbe_rom_info *rom = &hw->rom;
2718 struct txgbe_mbx_info *mbx = &hw->mbx;
2720 DEBUGFUNC("txgbe_init_ops_pf");
2723 bus->set_lan_id = txgbe_set_lan_id_multi_port;
2726 phy->get_media_type = txgbe_get_media_type_raptor;
2727 phy->identify = txgbe_identify_phy;
2728 phy->init = txgbe_init_phy_raptor;
2729 phy->read_reg = txgbe_read_phy_reg;
2730 phy->write_reg = txgbe_write_phy_reg;
2731 phy->read_reg_mdi = txgbe_read_phy_reg_mdi;
2732 phy->write_reg_mdi = txgbe_write_phy_reg_mdi;
2733 phy->setup_link = txgbe_setup_phy_link;
2734 phy->setup_link_speed = txgbe_setup_phy_link_speed;
2735 phy->get_fw_version = txgbe_get_phy_fw_version;
2736 phy->read_i2c_byte = txgbe_read_i2c_byte;
2737 phy->write_i2c_byte = txgbe_write_i2c_byte;
2738 phy->read_i2c_sff8472 = txgbe_read_i2c_sff8472;
2739 phy->read_i2c_eeprom = txgbe_read_i2c_eeprom;
2740 phy->write_i2c_eeprom = txgbe_write_i2c_eeprom;
2741 phy->identify_sfp = txgbe_identify_module;
2742 phy->read_i2c_byte_unlocked = txgbe_read_i2c_byte_unlocked;
2743 phy->write_i2c_byte_unlocked = txgbe_write_i2c_byte_unlocked;
2744 phy->reset = txgbe_reset_phy;
2747 mac->init_hw = txgbe_init_hw;
2748 mac->start_hw = txgbe_start_hw_raptor;
2749 mac->clear_hw_cntrs = txgbe_clear_hw_cntrs;
2750 mac->enable_rx_dma = txgbe_enable_rx_dma_raptor;
2751 mac->get_mac_addr = txgbe_get_mac_addr;
2752 mac->stop_hw = txgbe_stop_hw;
2753 mac->acquire_swfw_sync = txgbe_acquire_swfw_sync;
2754 mac->release_swfw_sync = txgbe_release_swfw_sync;
2755 mac->reset_hw = txgbe_reset_hw;
2756 mac->update_mc_addr_list = txgbe_update_mc_addr_list;
2758 mac->disable_sec_rx_path = txgbe_disable_sec_rx_path;
2759 mac->enable_sec_rx_path = txgbe_enable_sec_rx_path;
2760 mac->disable_sec_tx_path = txgbe_disable_sec_tx_path;
2761 mac->enable_sec_tx_path = txgbe_enable_sec_tx_path;
2762 mac->get_san_mac_addr = txgbe_get_san_mac_addr;
2763 mac->set_san_mac_addr = txgbe_set_san_mac_addr;
2764 mac->get_device_caps = txgbe_get_device_caps;
2765 mac->get_wwn_prefix = txgbe_get_wwn_prefix;
2766 mac->autoc_read = txgbe_autoc_read;
2767 mac->autoc_write = txgbe_autoc_write;
2768 mac->prot_autoc_read = txgbe_prot_autoc_read_raptor;
2769 mac->prot_autoc_write = txgbe_prot_autoc_write_raptor;
2771 /* RAR, Multicast, VLAN */
2772 mac->set_rar = txgbe_set_rar;
2773 mac->clear_rar = txgbe_clear_rar;
2774 mac->init_rx_addrs = txgbe_init_rx_addrs;
2775 mac->enable_rx = txgbe_enable_rx;
2776 mac->disable_rx = txgbe_disable_rx;
2777 mac->set_vmdq = txgbe_set_vmdq;
2778 mac->clear_vmdq = txgbe_clear_vmdq;
2779 mac->set_vfta = txgbe_set_vfta;
2780 mac->set_vlvf = txgbe_set_vlvf;
2781 mac->clear_vfta = txgbe_clear_vfta;
2782 mac->init_uta_tables = txgbe_init_uta_tables;
2783 mac->setup_sfp = txgbe_setup_sfp_modules;
2784 mac->set_mac_anti_spoofing = txgbe_set_mac_anti_spoofing;
2785 mac->set_ethertype_anti_spoofing = txgbe_set_ethertype_anti_spoofing;
2788 mac->fc_enable = txgbe_fc_enable;
2789 mac->setup_fc = txgbe_setup_fc;
2790 mac->fc_autoneg = txgbe_fc_autoneg;
2793 mac->get_link_capabilities = txgbe_get_link_capabilities_raptor;
2794 mac->check_link = txgbe_check_mac_link;
2795 mac->setup_pba = txgbe_set_pba;
2797 /* Manageability interface */
2798 mac->set_fw_drv_ver = txgbe_hic_set_drv_ver;
2799 mac->get_thermal_sensor_data = txgbe_get_thermal_sensor_data;
2800 mac->init_thermal_sensor_thresh = txgbe_init_thermal_sensor_thresh;
2802 mbx->init_params = txgbe_init_mbx_params_pf;
2803 mbx->read = txgbe_read_mbx_pf;
2804 mbx->write = txgbe_write_mbx_pf;
2805 mbx->check_for_msg = txgbe_check_for_msg_pf;
2806 mbx->check_for_ack = txgbe_check_for_ack_pf;
2807 mbx->check_for_rst = txgbe_check_for_rst_pf;
2810 rom->init_params = txgbe_init_eeprom_params;
2811 rom->read16 = txgbe_ee_read16;
2812 rom->readw_buffer = txgbe_ee_readw_buffer;
2813 rom->readw_sw = txgbe_ee_readw_sw;
2814 rom->read32 = txgbe_ee_read32;
2815 rom->write16 = txgbe_ee_write16;
2816 rom->writew_buffer = txgbe_ee_writew_buffer;
2817 rom->writew_sw = txgbe_ee_writew_sw;
2818 rom->write32 = txgbe_ee_write32;
2819 rom->validate_checksum = txgbe_validate_eeprom_checksum;
2820 rom->update_checksum = txgbe_update_eeprom_checksum;
2821 rom->calc_checksum = txgbe_calc_eeprom_checksum;
2823 mac->mcft_size = TXGBE_RAPTOR_MC_TBL_SIZE;
2824 mac->vft_size = TXGBE_RAPTOR_VFT_TBL_SIZE;
2825 mac->num_rar_entries = TXGBE_RAPTOR_RAR_ENTRIES;
2826 mac->rx_pb_size = TXGBE_RAPTOR_RX_PB_SIZE;
2827 mac->max_rx_queues = TXGBE_RAPTOR_MAX_RX_QUEUES;
2828 mac->max_tx_queues = TXGBE_RAPTOR_MAX_TX_QUEUES;
2834 * txgbe_get_link_capabilities_raptor - Determines link capabilities
2835 * @hw: pointer to hardware structure
2836 * @speed: pointer to link speed
2837 * @autoneg: true when autoneg or autotry is enabled
2839 * Determines the link capabilities by reading the AUTOC register.
2841 s32 txgbe_get_link_capabilities_raptor(struct txgbe_hw *hw,
2848 DEBUGFUNC("txgbe_get_link_capabilities_raptor");
2850 /* Check if 1G SFP module. */
2851 if (hw->phy.sfp_type == txgbe_sfp_type_1g_cu_core0 ||
2852 hw->phy.sfp_type == txgbe_sfp_type_1g_cu_core1 ||
2853 hw->phy.sfp_type == txgbe_sfp_type_1g_lx_core0 ||
2854 hw->phy.sfp_type == txgbe_sfp_type_1g_lx_core1 ||
2855 hw->phy.sfp_type == txgbe_sfp_type_1g_sx_core0 ||
2856 hw->phy.sfp_type == txgbe_sfp_type_1g_sx_core1) {
2857 *speed = TXGBE_LINK_SPEED_1GB_FULL;
2863 * Determine link capabilities based on the stored value of AUTOC,
2864 * which represents EEPROM defaults. If AUTOC value has not
2865 * been stored, use the current register values.
2867 if (hw->mac.orig_link_settings_stored)
2868 autoc = hw->mac.orig_autoc;
2870 autoc = hw->mac.autoc_read(hw);
2872 switch (autoc & TXGBE_AUTOC_LMS_MASK) {
2873 case TXGBE_AUTOC_LMS_1G_LINK_NO_AN:
2874 *speed = TXGBE_LINK_SPEED_1GB_FULL;
2878 case TXGBE_AUTOC_LMS_10G_LINK_NO_AN:
2879 *speed = TXGBE_LINK_SPEED_10GB_FULL;
2883 case TXGBE_AUTOC_LMS_1G_AN:
2884 *speed = TXGBE_LINK_SPEED_1GB_FULL;
2888 case TXGBE_AUTOC_LMS_10G:
2889 *speed = TXGBE_LINK_SPEED_10GB_FULL;
2893 case TXGBE_AUTOC_LMS_KX4_KX_KR:
2894 case TXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN:
2895 *speed = TXGBE_LINK_SPEED_UNKNOWN;
2896 if (autoc & TXGBE_AUTOC_KR_SUPP)
2897 *speed |= TXGBE_LINK_SPEED_10GB_FULL;
2898 if (autoc & TXGBE_AUTOC_KX4_SUPP)
2899 *speed |= TXGBE_LINK_SPEED_10GB_FULL;
2900 if (autoc & TXGBE_AUTOC_KX_SUPP)
2901 *speed |= TXGBE_LINK_SPEED_1GB_FULL;
2905 case TXGBE_AUTOC_LMS_KX4_KX_KR_SGMII:
2906 *speed = TXGBE_LINK_SPEED_100M_FULL;
2907 if (autoc & TXGBE_AUTOC_KR_SUPP)
2908 *speed |= TXGBE_LINK_SPEED_10GB_FULL;
2909 if (autoc & TXGBE_AUTOC_KX4_SUPP)
2910 *speed |= TXGBE_LINK_SPEED_10GB_FULL;
2911 if (autoc & TXGBE_AUTOC_KX_SUPP)
2912 *speed |= TXGBE_LINK_SPEED_1GB_FULL;
2916 case TXGBE_AUTOC_LMS_SGMII_1G_100M:
2917 *speed = TXGBE_LINK_SPEED_1GB_FULL |
2918 TXGBE_LINK_SPEED_100M_FULL |
2919 TXGBE_LINK_SPEED_10M_FULL;
2924 return TXGBE_ERR_LINK_SETUP;
2927 if (hw->phy.multispeed_fiber) {
2928 *speed |= TXGBE_LINK_SPEED_10GB_FULL |
2929 TXGBE_LINK_SPEED_1GB_FULL;
2931 /* QSFP must not enable full auto-negotiation
2932 * Limited autoneg is enabled at 1G
2934 if (hw->phy.media_type == txgbe_media_type_fiber_qsfp)
2944 * txgbe_get_media_type_raptor - Get media type
2945 * @hw: pointer to hardware structure
2947 * Returns the media type (fiber, copper, backplane)
2949 u32 txgbe_get_media_type_raptor(struct txgbe_hw *hw)
2953 DEBUGFUNC("txgbe_get_media_type_raptor");
2955 if (hw->phy.ffe_set)
2956 txgbe_bp_mode_set(hw);
2958 /* Detect if there is a copper PHY attached. */
2959 switch (hw->phy.type) {
2960 case txgbe_phy_cu_unknown:
2962 media_type = txgbe_media_type_copper;
2968 switch (hw->subsystem_device_id & 0xFF) {
2969 case TXGBE_DEV_ID_KR_KX_KX4:
2970 case TXGBE_DEV_ID_MAC_SGMII:
2971 case TXGBE_DEV_ID_MAC_XAUI:
2972 /* Default device ID is mezzanine card KX/KX4 */
2973 media_type = txgbe_media_type_backplane;
2975 case TXGBE_DEV_ID_SFP:
2976 media_type = txgbe_media_type_fiber;
2978 case TXGBE_DEV_ID_QSFP:
2979 media_type = txgbe_media_type_fiber_qsfp;
2981 case TXGBE_DEV_ID_XAUI:
2982 case TXGBE_DEV_ID_SGMII:
2983 media_type = txgbe_media_type_copper;
2985 case TXGBE_DEV_ID_SFI_XAUI:
2986 if (hw->bus.lan_id == 0)
2987 media_type = txgbe_media_type_fiber;
2989 media_type = txgbe_media_type_copper;
2992 media_type = txgbe_media_type_unknown;
3000 * txgbe_start_mac_link_raptor - Setup MAC link settings
3001 * @hw: pointer to hardware structure
3002 * @autoneg_wait_to_complete: true when waiting for completion is needed
3004 * Configures link settings based on values in the txgbe_hw struct.
3005 * Restarts the link. Performs autonegotiation if needed.
3007 s32 txgbe_start_mac_link_raptor(struct txgbe_hw *hw,
3008 bool autoneg_wait_to_complete)
3011 bool got_lock = false;
3013 DEBUGFUNC("txgbe_start_mac_link_raptor");
3015 UNREFERENCED_PARAMETER(autoneg_wait_to_complete);
3017 /* reset_pipeline requires us to hold this lock as it writes to
3020 if (txgbe_verify_lesm_fw_enabled_raptor(hw)) {
3021 status = hw->mac.acquire_swfw_sync(hw, TXGBE_MNGSEM_SWPHY);
3029 txgbe_reset_pipeline_raptor(hw);
3032 hw->mac.release_swfw_sync(hw, TXGBE_MNGSEM_SWPHY);
3034 /* Add delay to filter out noises during initial link setup */
3042 * txgbe_disable_tx_laser_multispeed_fiber - Disable Tx laser
3043 * @hw: pointer to hardware structure
3045 * The base drivers may require better control over SFP+ module
3046 * PHY states. This includes selectively shutting down the Tx
3047 * laser on the PHY, effectively halting physical link.
3049 void txgbe_disable_tx_laser_multispeed_fiber(struct txgbe_hw *hw)
3051 u32 esdp_reg = rd32(hw, TXGBE_GPIODATA);
3053 /* Blocked by MNG FW so bail */
3054 if (txgbe_check_reset_blocked(hw))
3057 /* Disable Tx laser; allow 100us to go dark per spec */
3058 esdp_reg |= (TXGBE_GPIOBIT_0 | TXGBE_GPIOBIT_1);
3059 wr32(hw, TXGBE_GPIODATA, esdp_reg);
3065 * txgbe_enable_tx_laser_multispeed_fiber - Enable Tx laser
3066 * @hw: pointer to hardware structure
3068 * The base drivers may require better control over SFP+ module
3069 * PHY states. This includes selectively turning on the Tx
3070 * laser on the PHY, effectively starting physical link.
3072 void txgbe_enable_tx_laser_multispeed_fiber(struct txgbe_hw *hw)
3074 u32 esdp_reg = rd32(hw, TXGBE_GPIODATA);
3076 /* Enable Tx laser; allow 100ms to light up */
3077 esdp_reg &= ~(TXGBE_GPIOBIT_0 | TXGBE_GPIOBIT_1);
3078 wr32(hw, TXGBE_GPIODATA, esdp_reg);
3084 * txgbe_flap_tx_laser_multispeed_fiber - Flap Tx laser
3085 * @hw: pointer to hardware structure
3087 * When the driver changes the link speeds that it can support,
3088 * it sets autotry_restart to true to indicate that we need to
3089 * initiate a new autotry session with the link partner. To do
3090 * so, we set the speed then disable and re-enable the Tx laser, to
3091 * alert the link partner that it also needs to restart autotry on its
3092 * end. This is consistent with true clause 37 autoneg, which also
3093 * involves a loss of signal.
3095 void txgbe_flap_tx_laser_multispeed_fiber(struct txgbe_hw *hw)
3097 DEBUGFUNC("txgbe_flap_tx_laser_multispeed_fiber");
3099 /* Blocked by MNG FW so bail */
3100 if (txgbe_check_reset_blocked(hw))
3103 if (hw->mac.autotry_restart) {
3104 txgbe_disable_tx_laser_multispeed_fiber(hw);
3105 txgbe_enable_tx_laser_multispeed_fiber(hw);
3106 hw->mac.autotry_restart = false;
3111 * txgbe_set_hard_rate_select_speed - Set module link speed
3112 * @hw: pointer to hardware structure
3113 * @speed: link speed to set
3115 * Set module link speed via RS0/RS1 rate select pins.
3117 void txgbe_set_hard_rate_select_speed(struct txgbe_hw *hw,
3120 u32 esdp_reg = rd32(hw, TXGBE_GPIODATA);
3123 case TXGBE_LINK_SPEED_10GB_FULL:
3124 esdp_reg |= (TXGBE_GPIOBIT_4 | TXGBE_GPIOBIT_5);
3126 case TXGBE_LINK_SPEED_1GB_FULL:
3127 esdp_reg &= ~(TXGBE_GPIOBIT_4 | TXGBE_GPIOBIT_5);
3130 DEBUGOUT("Invalid fixed module speed\n");
3134 wr32(hw, TXGBE_GPIODATA, esdp_reg);
3139 * txgbe_setup_mac_link_smartspeed - Set MAC link speed using SmartSpeed
3140 * @hw: pointer to hardware structure
3141 * @speed: new link speed
3142 * @autoneg_wait_to_complete: true when waiting for completion is needed
3144 * Implements the Intel SmartSpeed algorithm.
3146 s32 txgbe_setup_mac_link_smartspeed(struct txgbe_hw *hw,
3148 bool autoneg_wait_to_complete)
3151 u32 link_speed = TXGBE_LINK_SPEED_UNKNOWN;
3153 bool link_up = false;
3154 u32 autoc_reg = rd32_epcs(hw, SR_AN_MMD_ADV_REG1);
3156 DEBUGFUNC("txgbe_setup_mac_link_smartspeed");
3158 /* Set autoneg_advertised value based on input link speed */
3159 hw->phy.autoneg_advertised = 0;
3161 if (speed & TXGBE_LINK_SPEED_10GB_FULL)
3162 hw->phy.autoneg_advertised |= TXGBE_LINK_SPEED_10GB_FULL;
3164 if (speed & TXGBE_LINK_SPEED_1GB_FULL)
3165 hw->phy.autoneg_advertised |= TXGBE_LINK_SPEED_1GB_FULL;
3167 if (speed & TXGBE_LINK_SPEED_100M_FULL)
3168 hw->phy.autoneg_advertised |= TXGBE_LINK_SPEED_100M_FULL;
3171 * Implement Intel SmartSpeed algorithm. SmartSpeed will reduce the
3172 * autoneg advertisement if link is unable to be established at the
3173 * highest negotiated rate. This can sometimes happen due to integrity
3174 * issues with the physical media connection.
3177 /* First, try to get link with full advertisement */
3178 hw->phy.smart_speed_active = false;
3179 for (j = 0; j < TXGBE_SMARTSPEED_MAX_RETRIES; j++) {
3180 status = txgbe_setup_mac_link(hw, speed,
3181 autoneg_wait_to_complete);
3186 * Wait for the controller to acquire link. Per IEEE 802.3ap,
3187 * Section 73.10.2, we may have to wait up to 500ms if KR is
3188 * attempted, or 200ms if KX/KX4/BX/BX4 is attempted, per
3189 * Table 9 in the AN MAS.
3191 for (i = 0; i < 5; i++) {
3194 /* If we have link, just jump out */
3195 status = hw->mac.check_link(hw, &link_speed, &link_up,
3206 * We didn't get link. If we advertised KR plus one of KX4/KX
3207 * (or BX4/BX), then disable KR and try again.
3209 if (((autoc_reg & TXGBE_AUTOC_KR_SUPP) == 0) ||
3210 ((autoc_reg & TXGBE_AUTOC_KX_SUPP) == 0 &&
3211 (autoc_reg & TXGBE_AUTOC_KX4_SUPP) == 0))
3214 /* Turn SmartSpeed on to disable KR support */
3215 hw->phy.smart_speed_active = true;
3216 status = txgbe_setup_mac_link(hw, speed,
3217 autoneg_wait_to_complete);
3222 * Wait for the controller to acquire link. 600ms will allow for
3223 * the AN link_fail_inhibit_timer as well for multiple cycles of
3224 * parallel detect, both 10g and 1g. This allows for the maximum
3225 * connect attempts as defined in the AN MAS table 73-7.
3227 for (i = 0; i < 6; i++) {
3230 /* If we have link, just jump out */
3231 status = hw->mac.check_link(hw, &link_speed, &link_up, false);
3239 /* We didn't get link. Turn SmartSpeed back off. */
3240 hw->phy.smart_speed_active = false;
3241 status = txgbe_setup_mac_link(hw, speed,
3242 autoneg_wait_to_complete);
3245 if (link_up && link_speed == TXGBE_LINK_SPEED_1GB_FULL)
3246 DEBUGOUT("Smartspeed has downgraded the link speed "
3247 "from the maximum advertised\n");
3252 * txgbe_setup_mac_link - Set MAC link speed
3253 * @hw: pointer to hardware structure
3254 * @speed: new link speed
3255 * @autoneg_wait_to_complete: true when waiting for completion is needed
3257 * Set the link speed in the AUTOC register and restarts link.
3259 s32 txgbe_setup_mac_link(struct txgbe_hw *hw,
3261 bool autoneg_wait_to_complete)
3263 bool autoneg = false;
3266 u64 autoc = hw->mac.autoc_read(hw);
3267 u64 pma_pmd_10gs = autoc & TXGBE_AUTOC_10GS_PMA_PMD_MASK;
3268 u64 pma_pmd_1g = autoc & TXGBE_AUTOC_1G_PMA_PMD_MASK;
3269 u64 link_mode = autoc & TXGBE_AUTOC_LMS_MASK;
3271 u32 link_capabilities = TXGBE_LINK_SPEED_UNKNOWN;
3273 DEBUGFUNC("txgbe_setup_mac_link");
3274 UNREFERENCED_PARAMETER(autoneg_wait_to_complete);
3276 /* Check to see if speed passed in is supported. */
3277 status = hw->mac.get_link_capabilities(hw,
3278 &link_capabilities, &autoneg);
3282 speed &= link_capabilities;
3283 if (speed == TXGBE_LINK_SPEED_UNKNOWN)
3284 return TXGBE_ERR_LINK_SETUP;
3286 /* Use stored value (EEPROM defaults) of AUTOC to find KR/KX4 support*/
3287 if (hw->mac.orig_link_settings_stored)
3288 orig_autoc = hw->mac.orig_autoc;
3292 link_mode = autoc & TXGBE_AUTOC_LMS_MASK;
3293 pma_pmd_1g = autoc & TXGBE_AUTOC_1G_PMA_PMD_MASK;
3295 if (link_mode == TXGBE_AUTOC_LMS_KX4_KX_KR ||
3296 link_mode == TXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
3297 link_mode == TXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
3298 /* Set KX4/KX/KR support according to speed requested */
3299 autoc &= ~(TXGBE_AUTOC_KX_SUPP |
3300 TXGBE_AUTOC_KX4_SUPP |
3301 TXGBE_AUTOC_KR_SUPP);
3302 if (speed & TXGBE_LINK_SPEED_10GB_FULL) {
3303 if (orig_autoc & TXGBE_AUTOC_KX4_SUPP)
3304 autoc |= TXGBE_AUTOC_KX4_SUPP;
3305 if (orig_autoc & TXGBE_AUTOC_KR_SUPP)
3306 autoc |= TXGBE_AUTOC_KR_SUPP;
3308 if (speed & TXGBE_LINK_SPEED_1GB_FULL)
3309 autoc |= TXGBE_AUTOC_KX_SUPP;
3310 } else if ((pma_pmd_1g == TXGBE_AUTOC_1G_SFI) &&
3311 (link_mode == TXGBE_AUTOC_LMS_1G_LINK_NO_AN ||
3312 link_mode == TXGBE_AUTOC_LMS_1G_AN)) {
3313 /* Switch from 1G SFI to 10G SFI if requested */
3314 if (speed == TXGBE_LINK_SPEED_10GB_FULL &&
3315 pma_pmd_10gs == TXGBE_AUTOC_10GS_SFI) {
3316 autoc &= ~TXGBE_AUTOC_LMS_MASK;
3317 autoc |= TXGBE_AUTOC_LMS_10G;
3319 } else if ((pma_pmd_10gs == TXGBE_AUTOC_10GS_SFI) &&
3320 (link_mode == TXGBE_AUTOC_LMS_10G)) {
3321 /* Switch from 10G SFI to 1G SFI if requested */
3322 if (speed == TXGBE_LINK_SPEED_1GB_FULL &&
3323 pma_pmd_1g == TXGBE_AUTOC_1G_SFI) {
3324 autoc &= ~TXGBE_AUTOC_LMS_MASK;
3325 if (autoneg || hw->phy.type == txgbe_phy_qsfp_intel)
3326 autoc |= TXGBE_AUTOC_LMS_1G_AN;
3328 autoc |= TXGBE_AUTOC_LMS_1G_LINK_NO_AN;
3332 autoc &= ~TXGBE_AUTOC_SPEED_MASK;
3333 autoc |= TXGBE_AUTOC_SPEED(speed);
3334 autoc &= ~TXGBE_AUTOC_AUTONEG;
3335 autoc |= (autoneg ? TXGBE_AUTOC_AUTONEG : 0);
3338 hw->mac.autoc_write(hw, autoc);
3340 /* Add delay to filter out noises during initial link setup */
3347 * txgbe_setup_copper_link_raptor - Set the PHY autoneg advertised field
3348 * @hw: pointer to hardware structure
3349 * @speed: new link speed
3350 * @autoneg_wait_to_complete: true if waiting is needed to complete
3352 * Restarts link on PHY and MAC based on settings passed in.
3354 static s32 txgbe_setup_copper_link_raptor(struct txgbe_hw *hw,
3356 bool autoneg_wait_to_complete)
3360 DEBUGFUNC("txgbe_setup_copper_link_raptor");
3362 /* Setup the PHY according to input speed */
3363 status = hw->phy.setup_link_speed(hw, speed,
3364 autoneg_wait_to_complete);
3366 txgbe_start_mac_link_raptor(hw, autoneg_wait_to_complete);
3372 txgbe_check_flash_load(struct txgbe_hw *hw, u32 check_bit)
3377 /* if there's flash existing */
3378 if (!(rd32(hw, TXGBE_SPISTAT) & TXGBE_SPISTAT_BPFLASH)) {
3379 /* wait hw load flash done */
3380 for (i = 0; i < 10; i++) {
3381 reg = rd32(hw, TXGBE_ILDRSTAT);
3382 if (!(reg & check_bit)) {
3389 err = TXGBE_ERR_FLASH_LOADING_FAILED;
3395 txgbe_reset_misc(struct txgbe_hw *hw)
3400 wr32(hw, TXGBE_ISBADDRL, hw->isb_dma & 0x00000000FFFFFFFF);
3401 wr32(hw, TXGBE_ISBADDRH, hw->isb_dma >> 32);
3403 value = rd32_epcs(hw, SR_XS_PCS_CTRL2);
3404 if ((value & 0x3) != SR_PCS_CTRL2_TYPE_SEL_X)
3405 hw->link_status = TXGBE_LINK_STATUS_NONE;
3407 /* receive packets that size > 2048 */
3408 wr32m(hw, TXGBE_MACRXCFG,
3409 TXGBE_MACRXCFG_JUMBO, TXGBE_MACRXCFG_JUMBO);
3411 wr32m(hw, TXGBE_FRMSZ, TXGBE_FRMSZ_MAX_MASK,
3412 TXGBE_FRMSZ_MAX(TXGBE_FRAME_SIZE_DFT));
3414 /* clear counters on read */
3415 wr32m(hw, TXGBE_MACCNTCTL,
3416 TXGBE_MACCNTCTL_RC, TXGBE_MACCNTCTL_RC);
3418 wr32m(hw, TXGBE_RXFCCFG,
3419 TXGBE_RXFCCFG_FC, TXGBE_RXFCCFG_FC);
3420 wr32m(hw, TXGBE_TXFCCFG,
3421 TXGBE_TXFCCFG_FC, TXGBE_TXFCCFG_FC);
3423 wr32m(hw, TXGBE_MACRXFLT,
3424 TXGBE_MACRXFLT_PROMISC, TXGBE_MACRXFLT_PROMISC);
3426 wr32m(hw, TXGBE_RSTSTAT,
3427 TXGBE_RSTSTAT_TMRINIT_MASK, TXGBE_RSTSTAT_TMRINIT(30));
3429 /* errata 4: initialize mng flex tbl and wakeup flex tbl*/
3430 wr32(hw, TXGBE_MNGFLEXSEL, 0);
3431 for (i = 0; i < 16; i++) {
3432 wr32(hw, TXGBE_MNGFLEXDWL(i), 0);
3433 wr32(hw, TXGBE_MNGFLEXDWH(i), 0);
3434 wr32(hw, TXGBE_MNGFLEXMSK(i), 0);
3436 wr32(hw, TXGBE_LANFLEXSEL, 0);
3437 for (i = 0; i < 16; i++) {
3438 wr32(hw, TXGBE_LANFLEXDWL(i), 0);
3439 wr32(hw, TXGBE_LANFLEXDWH(i), 0);
3440 wr32(hw, TXGBE_LANFLEXMSK(i), 0);
3443 /* set pause frame dst mac addr */
3444 wr32(hw, TXGBE_RXPBPFCDMACL, 0xC2000001);
3445 wr32(hw, TXGBE_RXPBPFCDMACH, 0x0180);
3447 hw->mac.init_thermal_sensor_thresh(hw);
3449 /* enable mac transmitter */
3450 wr32m(hw, TXGBE_MACTXCFG, TXGBE_MACTXCFG_TXE, TXGBE_MACTXCFG_TXE);
3452 hw->mac.autoc = hw->mac.orig_autoc;
3453 for (i = 0; i < 4; i++)
3454 wr32m(hw, TXGBE_IVAR(i), 0x80808080, 0);
3458 * txgbe_reset_hw - Perform hardware reset
3459 * @hw: pointer to hardware structure
3461 * Resets the hardware by resetting the transmit and receive units, masks
3462 * and clears all interrupts, perform a PHY reset, and perform a link (MAC)
3465 s32 txgbe_reset_hw(struct txgbe_hw *hw)
3470 DEBUGFUNC("txgbe_reset_hw");
3472 /* Call adapter stop to disable tx/rx and clear interrupts */
3473 status = hw->mac.stop_hw(hw);
3477 /* flush pending Tx transactions */
3478 txgbe_clear_tx_pending(hw);
3480 /* Identify PHY and related function pointers */
3481 status = hw->phy.init(hw);
3482 if (status == TXGBE_ERR_SFP_NOT_SUPPORTED)
3485 /* Setup SFP module if there is one present. */
3486 if (hw->phy.sfp_setup_needed) {
3487 status = hw->mac.setup_sfp(hw);
3488 hw->phy.sfp_setup_needed = false;
3490 if (status == TXGBE_ERR_SFP_NOT_SUPPORTED)
3494 if (!hw->phy.reset_disable)
3497 /* remember AUTOC from before we reset */
3498 autoc = hw->mac.autoc_read(hw);
3502 * Issue global reset to the MAC. Needs to be SW reset if link is up.
3503 * If link reset is used when link is up, it might reset the PHY when
3504 * mng is using it. If link is down or the flag to force full link
3505 * reset is set, then perform link reset.
3507 if (txgbe_mng_present(hw)) {
3508 txgbe_hic_reset(hw);
3510 wr32(hw, TXGBE_RST, TXGBE_RST_LAN(hw->bus.lan_id));
3515 txgbe_reset_misc(hw);
3517 if (hw->bus.lan_id == 0) {
3518 status = txgbe_check_flash_load(hw,
3519 TXGBE_ILDRSTAT_SWRST_LAN0);
3521 status = txgbe_check_flash_load(hw,
3522 TXGBE_ILDRSTAT_SWRST_LAN1);
3530 * Double resets are required for recovery from certain error
3531 * conditions. Between resets, it is necessary to stall to
3532 * allow time for any pending HW events to complete.
3534 if (hw->mac.flags & TXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
3535 hw->mac.flags &= ~TXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
3540 * Store the original AUTOC/AUTOC2 values if they have not been
3541 * stored off yet. Otherwise restore the stored original
3542 * values since the reset operation sets back to defaults.
3544 if (!hw->mac.orig_link_settings_stored) {
3545 hw->mac.orig_autoc = hw->mac.autoc_read(hw);
3546 hw->mac.orig_link_settings_stored = true;
3548 hw->mac.orig_autoc = autoc;
3551 if (hw->phy.ffe_set) {
3552 /* Make sure phy power is up */
3555 /* A temporary solution to set phy */
3556 txgbe_set_phy_temp(hw);
3559 /* Store the permanent mac address */
3560 hw->mac.get_mac_addr(hw, hw->mac.perm_addr);
3563 * Store MAC address from RAR0, clear receive address registers, and
3564 * clear the multicast table. Also reset num_rar_entries to 128,
3565 * since we modify this value when programming the SAN MAC address.
3567 hw->mac.num_rar_entries = 128;
3568 hw->mac.init_rx_addrs(hw);
3570 /* Store the permanent SAN mac address */
3571 hw->mac.get_san_mac_addr(hw, hw->mac.san_addr);
3573 /* Add the SAN MAC address to the RAR only if it's a valid address */
3574 if (txgbe_validate_mac_addr(hw->mac.san_addr) == 0) {
3575 /* Save the SAN MAC RAR index */
3576 hw->mac.san_mac_rar_index = hw->mac.num_rar_entries - 1;
3578 hw->mac.set_rar(hw, hw->mac.san_mac_rar_index,
3579 hw->mac.san_addr, 0, true);
3581 /* clear VMDq pool/queue selection for this RAR */
3582 hw->mac.clear_vmdq(hw, hw->mac.san_mac_rar_index,
3585 /* Reserve the last RAR for the SAN MAC address */
3586 hw->mac.num_rar_entries--;
3589 /* Store the alternative WWNN/WWPN prefix */
3590 hw->mac.get_wwn_prefix(hw, &hw->mac.wwnn_prefix,
3591 &hw->mac.wwpn_prefix);
3597 * txgbe_fdir_check_cmd_complete - poll to check whether FDIRPICMD is complete
3598 * @hw: pointer to hardware structure
3599 * @fdircmd: current value of FDIRCMD register
3601 static s32 txgbe_fdir_check_cmd_complete(struct txgbe_hw *hw, u32 *fdircmd)
3605 for (i = 0; i < TXGBE_FDIRCMD_CMD_POLL; i++) {
3606 *fdircmd = rd32(hw, TXGBE_FDIRPICMD);
3607 if (!(*fdircmd & TXGBE_FDIRPICMD_OP_MASK))
3612 return TXGBE_ERR_FDIR_CMD_INCOMPLETE;
3616 * txgbe_reinit_fdir_tables - Reinitialize Flow Director tables.
3617 * @hw: pointer to hardware structure
3619 s32 txgbe_reinit_fdir_tables(struct txgbe_hw *hw)
3623 u32 fdirctrl = rd32(hw, TXGBE_FDIRCTL);
3625 fdirctrl &= ~TXGBE_FDIRCTL_INITDONE;
3627 DEBUGFUNC("txgbe_reinit_fdir_tables");
3630 * Before starting reinitialization process,
3631 * FDIRPICMD.OP must be zero.
3633 err = txgbe_fdir_check_cmd_complete(hw, &fdircmd);
3635 DEBUGOUT("Flow Director previous command did not complete, aborting table re-initialization.\n");
3639 wr32(hw, TXGBE_FDIRFREE, 0);
3642 * adapters flow director init flow cannot be restarted,
3643 * Workaround silicon errata by performing the following steps
3644 * before re-writing the FDIRCTL control register with the same value.
3645 * - write 1 to bit 8 of FDIRPICMD register &
3646 * - write 0 to bit 8 of FDIRPICMD register
3648 wr32m(hw, TXGBE_FDIRPICMD, TXGBE_FDIRPICMD_CLR, TXGBE_FDIRPICMD_CLR);
3650 wr32m(hw, TXGBE_FDIRPICMD, TXGBE_FDIRPICMD_CLR, 0);
3653 * Clear FDIR Hash register to clear any leftover hashes
3654 * waiting to be programmed.
3656 wr32(hw, TXGBE_FDIRPIHASH, 0x00);
3659 wr32(hw, TXGBE_FDIRCTL, fdirctrl);
3662 /* Poll init-done after we write FDIRCTL register */
3663 for (i = 0; i < TXGBE_FDIR_INIT_DONE_POLL; i++) {
3664 if (rd32m(hw, TXGBE_FDIRCTL, TXGBE_FDIRCTL_INITDONE))
3668 if (i >= TXGBE_FDIR_INIT_DONE_POLL) {
3669 DEBUGOUT("Flow Director Signature poll time exceeded!\n");
3670 return TXGBE_ERR_FDIR_REINIT_FAILED;
3673 /* Clear FDIR statistics registers (read to clear) */
3674 rd32(hw, TXGBE_FDIRUSED);
3675 rd32(hw, TXGBE_FDIRFAIL);
3676 rd32(hw, TXGBE_FDIRMATCH);
3677 rd32(hw, TXGBE_FDIRMISS);
3678 rd32(hw, TXGBE_FDIRLEN);
3684 * txgbe_start_hw_raptor - Prepare hardware for Tx/Rx
3685 * @hw: pointer to hardware structure
3687 * Starts the hardware using the generic start_hw function
3688 * and the generation start_hw function.
3689 * Then performs revision-specific operations, if any.
3691 s32 txgbe_start_hw_raptor(struct txgbe_hw *hw)
3695 DEBUGFUNC("txgbe_start_hw_raptor");
3697 err = txgbe_start_hw(hw);
3701 err = txgbe_start_hw_gen2(hw);
3705 /* We need to run link autotry after the driver loads */
3706 hw->mac.autotry_restart = true;
3713 * txgbe_enable_rx_dma_raptor - Enable the Rx DMA unit
3714 * @hw: pointer to hardware structure
3715 * @regval: register value to write to RXCTRL
3717 * Enables the Rx DMA unit
3719 s32 txgbe_enable_rx_dma_raptor(struct txgbe_hw *hw, u32 regval)
3721 DEBUGFUNC("txgbe_enable_rx_dma_raptor");
3724 * Workaround silicon errata when enabling the Rx datapath.
3725 * If traffic is incoming before we enable the Rx unit, it could hang
3726 * the Rx DMA unit. Therefore, make sure the security engine is
3727 * completely disabled prior to enabling the Rx unit.
3730 hw->mac.disable_sec_rx_path(hw);
3732 if (regval & TXGBE_PBRXCTL_ENA)
3733 txgbe_enable_rx(hw);
3735 txgbe_disable_rx(hw);
3737 hw->mac.enable_sec_rx_path(hw);
3743 * txgbe_verify_lesm_fw_enabled_raptor - Checks LESM FW module state.
3744 * @hw: pointer to hardware structure
3746 * Returns true if the LESM FW module is present and enabled. Otherwise
3747 * returns false. Smart Speed must be disabled if LESM FW module is enabled.
3749 bool txgbe_verify_lesm_fw_enabled_raptor(struct txgbe_hw *hw)
3751 bool lesm_enabled = false;
3752 u16 fw_offset, fw_lesm_param_offset, fw_lesm_state;
3755 DEBUGFUNC("txgbe_verify_lesm_fw_enabled_raptor");
3757 /* get the offset to the Firmware Module block */
3758 status = hw->rom.read16(hw, TXGBE_FW_PTR, &fw_offset);
3760 if (status != 0 || fw_offset == 0 || fw_offset == 0xFFFF)
3763 /* get the offset to the LESM Parameters block */
3764 status = hw->rom.read16(hw, (fw_offset +
3765 TXGBE_FW_LESM_PARAMETERS_PTR),
3766 &fw_lesm_param_offset);
3769 fw_lesm_param_offset == 0 || fw_lesm_param_offset == 0xFFFF)
3772 /* get the LESM state word */
3773 status = hw->rom.read16(hw, (fw_lesm_param_offset +
3774 TXGBE_FW_LESM_STATE_1),
3777 if (status == 0 && (fw_lesm_state & TXGBE_FW_LESM_STATE_ENABLED))
3778 lesm_enabled = true;
3781 lesm_enabled = false;
3782 return lesm_enabled;
3786 * txgbe_reset_pipeline_raptor - perform pipeline reset
3788 * @hw: pointer to hardware structure
3790 * Reset pipeline by asserting Restart_AN together with LMS change to ensure
3791 * full pipeline reset. This function assumes the SW/FW lock is held.
3793 s32 txgbe_reset_pipeline_raptor(struct txgbe_hw *hw)
3798 autoc = hw->mac.autoc_read(hw);
3800 /* Enable link if disabled in NVM */
3801 if (autoc & TXGBE_AUTOC_LINK_DIA_MASK)
3802 autoc &= ~TXGBE_AUTOC_LINK_DIA_MASK;
3804 autoc |= TXGBE_AUTOC_AN_RESTART;
3805 /* Write AUTOC register with toggled LMS[2] bit and Restart_AN */
3806 hw->mac.autoc_write(hw, autoc ^ TXGBE_AUTOC_LMS_AN);
3808 /* Write AUTOC register with original LMS field and Restart_AN */
3809 hw->mac.autoc_write(hw, autoc);