1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2015-2020
5 #include "txgbe_type.h"
7 #include "txgbe_eeprom.h"
11 #define TXGBE_RAPTOR_MAX_TX_QUEUES 128
12 #define TXGBE_RAPTOR_MAX_RX_QUEUES 128
13 #define TXGBE_RAPTOR_RAR_ENTRIES 128
14 #define TXGBE_RAPTOR_MC_TBL_SIZE 128
15 #define TXGBE_RAPTOR_VFT_TBL_SIZE 128
17 static s32 txgbe_setup_copper_link_raptor(struct txgbe_hw *hw,
19 bool autoneg_wait_to_complete);
21 static s32 txgbe_mta_vector(struct txgbe_hw *hw, u8 *mc_addr);
22 static s32 txgbe_get_san_mac_addr_offset(struct txgbe_hw *hw,
26 * txgbe_start_hw - Prepare hardware for Tx/Rx
27 * @hw: pointer to hardware structure
29 * Starts the hardware by filling the bus info structure and media type, clears
30 * all on chip counters, initializes receive address registers, multicast
31 * table, VLAN filter table, calls routine to set up link and flow control
32 * settings, and leaves transmit and receive units disabled and uninitialized
34 s32 txgbe_start_hw(struct txgbe_hw *hw)
38 DEBUGFUNC("txgbe_start_hw");
40 /* Set the media type */
41 hw->phy.media_type = hw->phy.get_media_type(hw);
43 /* Clear the VLAN filter table */
44 hw->mac.clear_vfta(hw);
46 /* Clear statistics registers */
47 hw->mac.clear_hw_cntrs(hw);
49 /* Cache bit indicating need for crosstalk fix */
50 switch (hw->mac.type) {
51 case txgbe_mac_raptor:
52 hw->mac.get_device_caps(hw, &device_caps);
53 if (device_caps & TXGBE_DEVICE_CAPS_NO_CROSSTALK_WR)
54 hw->need_crosstalk_fix = false;
56 hw->need_crosstalk_fix = true;
59 hw->need_crosstalk_fix = false;
63 /* Clear adapter stopped flag */
64 hw->adapter_stopped = false;
70 * txgbe_start_hw_gen2 - Init sequence for common device family
71 * @hw: pointer to hw structure
73 * Performs the init sequence common to the second generation
76 s32 txgbe_start_hw_gen2(struct txgbe_hw *hw)
80 /* Clear the rate limiters */
81 for (i = 0; i < hw->mac.max_tx_queues; i++) {
82 wr32(hw, TXGBE_ARBPOOLIDX, i);
83 wr32(hw, TXGBE_ARBTXRATE, 0);
87 /* We need to run link autotry after the driver loads */
88 hw->mac.autotry_restart = true;
94 * txgbe_init_hw - Generic hardware initialization
95 * @hw: pointer to hardware structure
97 * Initialize the hardware by resetting the hardware, filling the bus info
98 * structure and media type, clears all on chip counters, initializes receive
99 * address registers, multicast table, VLAN filter table, calls routine to set
100 * up link and flow control settings, and leaves transmit and receive units
101 * disabled and uninitialized
103 s32 txgbe_init_hw(struct txgbe_hw *hw)
107 DEBUGFUNC("txgbe_init_hw");
109 /* Reset the hardware */
110 status = hw->mac.reset_hw(hw);
111 if (status == 0 || status == TXGBE_ERR_SFP_NOT_PRESENT) {
113 status = hw->mac.start_hw(hw);
117 DEBUGOUT("Failed to initialize HW, STATUS = %d\n", status);
123 * txgbe_clear_hw_cntrs - Generic clear hardware counters
124 * @hw: pointer to hardware structure
126 * Clears all hardware statistics counters by reading them from the hardware
127 * Statistics counters are clear on read.
129 s32 txgbe_clear_hw_cntrs(struct txgbe_hw *hw)
133 DEBUGFUNC("txgbe_clear_hw_cntrs");
136 /* don't write clear queue stats */
137 for (i = 0; i < TXGBE_MAX_QP; i++) {
138 hw->qp_last[i].rx_qp_packets = 0;
139 hw->qp_last[i].tx_qp_packets = 0;
140 hw->qp_last[i].rx_qp_bytes = 0;
141 hw->qp_last[i].tx_qp_bytes = 0;
142 hw->qp_last[i].rx_qp_mc_packets = 0;
146 for (i = 0; i < TXGBE_MAX_UP; i++) {
147 rd32(hw, TXGBE_PBRXUPXON(i));
148 rd32(hw, TXGBE_PBRXUPXOFF(i));
149 rd32(hw, TXGBE_PBTXUPXON(i));
150 rd32(hw, TXGBE_PBTXUPXOFF(i));
151 rd32(hw, TXGBE_PBTXUPOFF(i));
153 rd32(hw, TXGBE_PBRXMISS(i));
155 rd32(hw, TXGBE_PBRXLNKXON);
156 rd32(hw, TXGBE_PBRXLNKXOFF);
157 rd32(hw, TXGBE_PBTXLNKXON);
158 rd32(hw, TXGBE_PBTXLNKXOFF);
161 rd32(hw, TXGBE_DMARXPKT);
162 rd32(hw, TXGBE_DMATXPKT);
164 rd64(hw, TXGBE_DMARXOCTL);
165 rd64(hw, TXGBE_DMATXOCTL);
168 rd64(hw, TXGBE_MACRXERRCRCL);
169 rd64(hw, TXGBE_MACRXMPKTL);
170 rd64(hw, TXGBE_MACTXMPKTL);
172 rd64(hw, TXGBE_MACRXPKTL);
173 rd64(hw, TXGBE_MACTXPKTL);
174 rd64(hw, TXGBE_MACRXGBOCTL);
176 rd64(hw, TXGBE_MACRXOCTL);
177 rd32(hw, TXGBE_MACTXOCTL);
179 rd64(hw, TXGBE_MACRX1TO64L);
180 rd64(hw, TXGBE_MACRX65TO127L);
181 rd64(hw, TXGBE_MACRX128TO255L);
182 rd64(hw, TXGBE_MACRX256TO511L);
183 rd64(hw, TXGBE_MACRX512TO1023L);
184 rd64(hw, TXGBE_MACRX1024TOMAXL);
185 rd64(hw, TXGBE_MACTX1TO64L);
186 rd64(hw, TXGBE_MACTX65TO127L);
187 rd64(hw, TXGBE_MACTX128TO255L);
188 rd64(hw, TXGBE_MACTX256TO511L);
189 rd64(hw, TXGBE_MACTX512TO1023L);
190 rd64(hw, TXGBE_MACTX1024TOMAXL);
192 rd64(hw, TXGBE_MACRXERRLENL);
193 rd32(hw, TXGBE_MACRXOVERSIZE);
194 rd32(hw, TXGBE_MACRXJABBER);
197 rd32(hw, TXGBE_FCOECRC);
198 rd32(hw, TXGBE_FCOELAST);
199 rd32(hw, TXGBE_FCOERPDC);
200 rd32(hw, TXGBE_FCOEPRC);
201 rd32(hw, TXGBE_FCOEPTC);
202 rd32(hw, TXGBE_FCOEDWRC);
203 rd32(hw, TXGBE_FCOEDWTC);
205 /* Flow Director Stats */
206 rd32(hw, TXGBE_FDIRMATCH);
207 rd32(hw, TXGBE_FDIRMISS);
208 rd32(hw, TXGBE_FDIRUSED);
209 rd32(hw, TXGBE_FDIRUSED);
210 rd32(hw, TXGBE_FDIRFAIL);
211 rd32(hw, TXGBE_FDIRFAIL);
214 rd32(hw, TXGBE_LSECTX_UTPKT);
215 rd32(hw, TXGBE_LSECTX_ENCPKT);
216 rd32(hw, TXGBE_LSECTX_PROTPKT);
217 rd32(hw, TXGBE_LSECTX_ENCOCT);
218 rd32(hw, TXGBE_LSECTX_PROTOCT);
219 rd32(hw, TXGBE_LSECRX_UTPKT);
220 rd32(hw, TXGBE_LSECRX_BTPKT);
221 rd32(hw, TXGBE_LSECRX_NOSCIPKT);
222 rd32(hw, TXGBE_LSECRX_UNSCIPKT);
223 rd32(hw, TXGBE_LSECRX_DECOCT);
224 rd32(hw, TXGBE_LSECRX_VLDOCT);
225 rd32(hw, TXGBE_LSECRX_UNCHKPKT);
226 rd32(hw, TXGBE_LSECRX_DLYPKT);
227 rd32(hw, TXGBE_LSECRX_LATEPKT);
228 for (i = 0; i < 2; i++) {
229 rd32(hw, TXGBE_LSECRX_OKPKT(i));
230 rd32(hw, TXGBE_LSECRX_INVPKT(i));
231 rd32(hw, TXGBE_LSECRX_BADPKT(i));
233 rd32(hw, TXGBE_LSECRX_INVSAPKT);
234 rd32(hw, TXGBE_LSECRX_BADSAPKT);
240 * txgbe_get_mac_addr - Generic get MAC address
241 * @hw: pointer to hardware structure
242 * @mac_addr: Adapter MAC address
244 * Reads the adapter's MAC address from first Receive Address Register (RAR0)
245 * A reset of the adapter must be performed prior to calling this function
246 * in order for the MAC address to have been loaded from the EEPROM into RAR0
248 s32 txgbe_get_mac_addr(struct txgbe_hw *hw, u8 *mac_addr)
254 DEBUGFUNC("txgbe_get_mac_addr");
256 wr32(hw, TXGBE_ETHADDRIDX, 0);
257 rar_high = rd32(hw, TXGBE_ETHADDRH);
258 rar_low = rd32(hw, TXGBE_ETHADDRL);
260 for (i = 0; i < 2; i++)
261 mac_addr[i] = (u8)(rar_high >> (1 - i) * 8);
263 for (i = 0; i < 4; i++)
264 mac_addr[i + 2] = (u8)(rar_low >> (3 - i) * 8);
270 * txgbe_set_lan_id_multi_port - Set LAN id for PCIe multiple port devices
271 * @hw: pointer to the HW structure
273 * Determines the LAN function id by reading memory-mapped registers and swaps
274 * the port value if requested, and set MAC instance for devices.
276 void txgbe_set_lan_id_multi_port(struct txgbe_hw *hw)
278 struct txgbe_bus_info *bus = &hw->bus;
281 DEBUGFUNC("txgbe_set_lan_id_multi_port_pcie");
283 reg = rd32(hw, TXGBE_PORTSTAT);
284 bus->lan_id = TXGBE_PORTSTAT_ID(reg);
286 /* check for single port */
287 reg = rd32(hw, TXGBE_PWR);
288 if (TXGBE_PWR_LANID(reg) == TXGBE_PWR_LANID_SWAP)
291 bus->func = bus->lan_id;
295 * txgbe_stop_hw - Generic stop Tx/Rx units
296 * @hw: pointer to hardware structure
298 * Sets the adapter_stopped flag within txgbe_hw struct. Clears interrupts,
299 * disables transmit and receive units. The adapter_stopped flag is used by
300 * the shared code and drivers to determine if the adapter is in a stopped
301 * state and should not touch the hardware.
303 s32 txgbe_stop_hw(struct txgbe_hw *hw)
308 DEBUGFUNC("txgbe_stop_hw");
311 * Set the adapter_stopped flag so other driver functions stop touching
314 hw->adapter_stopped = true;
316 /* Disable the receive unit */
317 txgbe_disable_rx(hw);
319 /* Clear interrupt mask to stop interrupts from being generated */
320 wr32(hw, TXGBE_IENMISC, 0);
321 wr32(hw, TXGBE_IMS(0), TXGBE_IMS_MASK);
322 wr32(hw, TXGBE_IMS(1), TXGBE_IMS_MASK);
324 /* Clear any pending interrupts, flush previous writes */
325 wr32(hw, TXGBE_ICRMISC, TXGBE_ICRMISC_MASK);
326 wr32(hw, TXGBE_ICR(0), TXGBE_ICR_MASK);
327 wr32(hw, TXGBE_ICR(1), TXGBE_ICR_MASK);
329 /* Disable the transmit unit. Each queue must be disabled. */
330 for (i = 0; i < hw->mac.max_tx_queues; i++)
331 wr32(hw, TXGBE_TXCFG(i), TXGBE_TXCFG_FLUSH);
333 /* Disable the receive unit by stopping each queue */
334 for (i = 0; i < hw->mac.max_rx_queues; i++) {
335 reg_val = rd32(hw, TXGBE_RXCFG(i));
336 reg_val &= ~TXGBE_RXCFG_ENA;
337 wr32(hw, TXGBE_RXCFG(i), reg_val);
340 /* flush all queues disables */
348 * txgbe_validate_mac_addr - Validate MAC address
349 * @mac_addr: pointer to MAC address.
351 * Tests a MAC address to ensure it is a valid Individual Address.
353 s32 txgbe_validate_mac_addr(u8 *mac_addr)
357 DEBUGFUNC("txgbe_validate_mac_addr");
359 /* Make sure it is not a multicast address */
360 if (TXGBE_IS_MULTICAST(mac_addr)) {
361 status = TXGBE_ERR_INVALID_MAC_ADDR;
362 /* Not a broadcast address */
363 } else if (TXGBE_IS_BROADCAST(mac_addr)) {
364 status = TXGBE_ERR_INVALID_MAC_ADDR;
365 /* Reject the zero address */
366 } else if (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 &&
367 mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0) {
368 status = TXGBE_ERR_INVALID_MAC_ADDR;
374 * txgbe_set_rar - Set Rx address register
375 * @hw: pointer to hardware structure
376 * @index: Receive address register to write
377 * @addr: Address to put into receive address register
378 * @vmdq: VMDq "set" or "pool" index
379 * @enable_addr: set flag that address is active
381 * Puts an ethernet address into a receive address register.
383 s32 txgbe_set_rar(struct txgbe_hw *hw, u32 index, u8 *addr, u32 vmdq,
386 u32 rar_low, rar_high;
387 u32 rar_entries = hw->mac.num_rar_entries;
389 DEBUGFUNC("txgbe_set_rar");
391 /* Make sure we are using a valid rar index range */
392 if (index >= rar_entries) {
393 DEBUGOUT("RAR index %d is out of range.\n", index);
394 return TXGBE_ERR_INVALID_ARGUMENT;
397 /* setup VMDq pool selection before this RAR gets enabled */
398 hw->mac.set_vmdq(hw, index, vmdq);
401 * HW expects these in little endian so we reverse the byte
402 * order from network order (big endian) to little endian
404 rar_low = TXGBE_ETHADDRL_AD0(addr[5]) |
405 TXGBE_ETHADDRL_AD1(addr[4]) |
406 TXGBE_ETHADDRL_AD2(addr[3]) |
407 TXGBE_ETHADDRL_AD3(addr[2]);
409 * Some parts put the VMDq setting in the extra RAH bits,
410 * so save everything except the lower 16 bits that hold part
411 * of the address and the address valid bit.
413 rar_high = rd32(hw, TXGBE_ETHADDRH);
414 rar_high &= ~TXGBE_ETHADDRH_AD_MASK;
415 rar_high |= (TXGBE_ETHADDRH_AD4(addr[1]) |
416 TXGBE_ETHADDRH_AD5(addr[0]));
418 rar_high &= ~TXGBE_ETHADDRH_VLD;
419 if (enable_addr != 0)
420 rar_high |= TXGBE_ETHADDRH_VLD;
422 wr32(hw, TXGBE_ETHADDRIDX, index);
423 wr32(hw, TXGBE_ETHADDRL, rar_low);
424 wr32(hw, TXGBE_ETHADDRH, rar_high);
430 * txgbe_clear_rar - Remove Rx address register
431 * @hw: pointer to hardware structure
432 * @index: Receive address register to write
434 * Clears an ethernet address from a receive address register.
436 s32 txgbe_clear_rar(struct txgbe_hw *hw, u32 index)
439 u32 rar_entries = hw->mac.num_rar_entries;
441 DEBUGFUNC("txgbe_clear_rar");
443 /* Make sure we are using a valid rar index range */
444 if (index >= rar_entries) {
445 DEBUGOUT("RAR index %d is out of range.\n", index);
446 return TXGBE_ERR_INVALID_ARGUMENT;
450 * Some parts put the VMDq setting in the extra RAH bits,
451 * so save everything except the lower 16 bits that hold part
452 * of the address and the address valid bit.
454 wr32(hw, TXGBE_ETHADDRIDX, index);
455 rar_high = rd32(hw, TXGBE_ETHADDRH);
456 rar_high &= ~(TXGBE_ETHADDRH_AD_MASK | TXGBE_ETHADDRH_VLD);
458 wr32(hw, TXGBE_ETHADDRL, 0);
459 wr32(hw, TXGBE_ETHADDRH, rar_high);
461 /* clear VMDq pool/queue selection for this RAR */
462 hw->mac.clear_vmdq(hw, index, BIT_MASK32);
468 * txgbe_init_rx_addrs - Initializes receive address filters.
469 * @hw: pointer to hardware structure
471 * Places the MAC address in receive address register 0 and clears the rest
472 * of the receive address registers. Clears the multicast table. Assumes
473 * the receiver is in reset when the routine is called.
475 s32 txgbe_init_rx_addrs(struct txgbe_hw *hw)
479 u32 rar_entries = hw->mac.num_rar_entries;
481 DEBUGFUNC("txgbe_init_rx_addrs");
484 * If the current mac address is valid, assume it is a software override
485 * to the permanent address.
486 * Otherwise, use the permanent address from the eeprom.
488 if (txgbe_validate_mac_addr(hw->mac.addr) ==
489 TXGBE_ERR_INVALID_MAC_ADDR) {
490 /* Get the MAC address from the RAR0 for later reference */
491 hw->mac.get_mac_addr(hw, hw->mac.addr);
493 DEBUGOUT(" Keeping Current RAR0 Addr =%.2X %.2X %.2X ",
494 hw->mac.addr[0], hw->mac.addr[1],
496 DEBUGOUT("%.2X %.2X %.2X\n", hw->mac.addr[3],
497 hw->mac.addr[4], hw->mac.addr[5]);
499 /* Setup the receive address. */
500 DEBUGOUT("Overriding MAC Address in RAR[0]\n");
501 DEBUGOUT(" New MAC Addr =%.2X %.2X %.2X ",
502 hw->mac.addr[0], hw->mac.addr[1],
504 DEBUGOUT("%.2X %.2X %.2X\n", hw->mac.addr[3],
505 hw->mac.addr[4], hw->mac.addr[5]);
507 hw->mac.set_rar(hw, 0, hw->mac.addr, 0, true);
510 /* clear VMDq pool/queue selection for RAR 0 */
511 hw->mac.clear_vmdq(hw, 0, BIT_MASK32);
513 hw->addr_ctrl.overflow_promisc = 0;
515 hw->addr_ctrl.rar_used_count = 1;
517 /* Zero out the other receive addresses. */
518 DEBUGOUT("Clearing RAR[1-%d]\n", rar_entries - 1);
519 for (i = 1; i < rar_entries; i++) {
520 wr32(hw, TXGBE_ETHADDRIDX, i);
521 wr32(hw, TXGBE_ETHADDRL, 0);
522 wr32(hw, TXGBE_ETHADDRH, 0);
526 hw->addr_ctrl.mta_in_use = 0;
527 psrctl = rd32(hw, TXGBE_PSRCTL);
528 psrctl &= ~(TXGBE_PSRCTL_ADHF12_MASK | TXGBE_PSRCTL_MCHFENA);
529 psrctl |= TXGBE_PSRCTL_ADHF12(hw->mac.mc_filter_type);
530 wr32(hw, TXGBE_PSRCTL, psrctl);
532 DEBUGOUT(" Clearing MTA\n");
533 for (i = 0; i < hw->mac.mcft_size; i++)
534 wr32(hw, TXGBE_MCADDRTBL(i), 0);
536 txgbe_init_uta_tables(hw);
542 * txgbe_mta_vector - Determines bit-vector in multicast table to set
543 * @hw: pointer to hardware structure
544 * @mc_addr: the multicast address
546 * Extracts the 12 bits, from a multicast address, to determine which
547 * bit-vector to set in the multicast table. The hardware uses 12 bits, from
548 * incoming rx multicast addresses, to determine the bit-vector to check in
549 * the MTA. Which of the 4 combination, of 12-bits, the hardware uses is set
550 * by the MO field of the PSRCTRL. The MO field is set during initialization
553 static s32 txgbe_mta_vector(struct txgbe_hw *hw, u8 *mc_addr)
557 DEBUGFUNC("txgbe_mta_vector");
559 switch (hw->mac.mc_filter_type) {
560 case 0: /* use bits [47:36] of the address */
561 vector = ((mc_addr[4] >> 4) | (((u16)mc_addr[5]) << 4));
563 case 1: /* use bits [46:35] of the address */
564 vector = ((mc_addr[4] >> 3) | (((u16)mc_addr[5]) << 5));
566 case 2: /* use bits [45:34] of the address */
567 vector = ((mc_addr[4] >> 2) | (((u16)mc_addr[5]) << 6));
569 case 3: /* use bits [43:32] of the address */
570 vector = ((mc_addr[4]) | (((u16)mc_addr[5]) << 8));
572 default: /* Invalid mc_filter_type */
573 DEBUGOUT("MC filter type param set incorrectly\n");
578 /* vector can only be 12-bits or boundary will be exceeded */
584 * txgbe_set_mta - Set bit-vector in multicast table
585 * @hw: pointer to hardware structure
586 * @mc_addr: Multicast address
588 * Sets the bit-vector in the multicast table.
590 void txgbe_set_mta(struct txgbe_hw *hw, u8 *mc_addr)
596 DEBUGFUNC("txgbe_set_mta");
598 hw->addr_ctrl.mta_in_use++;
600 vector = txgbe_mta_vector(hw, mc_addr);
601 DEBUGOUT(" bit-vector = 0x%03X\n", vector);
604 * The MTA is a register array of 128 32-bit registers. It is treated
605 * like an array of 4096 bits. We want to set bit
606 * BitArray[vector_value]. So we figure out what register the bit is
607 * in, read it, OR in the new bit, then write back the new value. The
608 * register is determined by the upper 7 bits of the vector value and
609 * the bit within that register are determined by the lower 5 bits of
612 vector_reg = (vector >> 5) & 0x7F;
613 vector_bit = vector & 0x1F;
614 hw->mac.mta_shadow[vector_reg] |= (1 << vector_bit);
618 * txgbe_update_mc_addr_list - Updates MAC list of multicast addresses
619 * @hw: pointer to hardware structure
620 * @mc_addr_list: the list of new multicast addresses
621 * @mc_addr_count: number of addresses
622 * @next: iterator function to walk the multicast address list
623 * @clear: flag, when set clears the table beforehand
625 * When the clear flag is set, the given list replaces any existing list.
626 * Hashes the given addresses into the multicast table.
628 s32 txgbe_update_mc_addr_list(struct txgbe_hw *hw, u8 *mc_addr_list,
629 u32 mc_addr_count, txgbe_mc_addr_itr next,
635 DEBUGFUNC("txgbe_update_mc_addr_list");
638 * Set the new number of MC addresses that we are being requested to
641 hw->addr_ctrl.num_mc_addrs = mc_addr_count;
642 hw->addr_ctrl.mta_in_use = 0;
644 /* Clear mta_shadow */
646 DEBUGOUT(" Clearing MTA\n");
647 memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow));
650 /* Update mta_shadow */
651 for (i = 0; i < mc_addr_count; i++) {
652 DEBUGOUT(" Adding the multicast addresses:\n");
653 txgbe_set_mta(hw, next(hw, &mc_addr_list, &vmdq));
657 for (i = 0; i < hw->mac.mcft_size; i++)
658 wr32a(hw, TXGBE_MCADDRTBL(0), i,
659 hw->mac.mta_shadow[i]);
661 if (hw->addr_ctrl.mta_in_use > 0) {
662 u32 psrctl = rd32(hw, TXGBE_PSRCTL);
663 psrctl &= ~(TXGBE_PSRCTL_ADHF12_MASK | TXGBE_PSRCTL_MCHFENA);
664 psrctl |= TXGBE_PSRCTL_MCHFENA |
665 TXGBE_PSRCTL_ADHF12(hw->mac.mc_filter_type);
666 wr32(hw, TXGBE_PSRCTL, psrctl);
669 DEBUGOUT("txgbe update mc addr list complete\n");
674 * txgbe_acquire_swfw_sync - Acquire SWFW semaphore
675 * @hw: pointer to hardware structure
676 * @mask: Mask to specify which semaphore to acquire
678 * Acquires the SWFW semaphore through the MNGSEM register for the specified
679 * function (CSR, PHY0, PHY1, EEPROM, Flash)
681 s32 txgbe_acquire_swfw_sync(struct txgbe_hw *hw, u32 mask)
684 u32 swmask = TXGBE_MNGSEM_SW(mask);
685 u32 fwmask = TXGBE_MNGSEM_FW(mask);
689 DEBUGFUNC("txgbe_acquire_swfw_sync");
691 for (i = 0; i < timeout; i++) {
693 * SW NVM semaphore bit is used for access to all
694 * SW_FW_SYNC bits (not just NVM)
696 if (txgbe_get_eeprom_semaphore(hw))
697 return TXGBE_ERR_SWFW_SYNC;
699 mngsem = rd32(hw, TXGBE_MNGSEM);
700 if (mngsem & (fwmask | swmask)) {
701 /* Resource is currently in use by FW or SW */
702 txgbe_release_eeprom_semaphore(hw);
706 wr32(hw, TXGBE_MNGSEM, mngsem);
707 txgbe_release_eeprom_semaphore(hw);
712 /* If time expired clear the bits holding the lock and retry */
713 if (mngsem & (fwmask | swmask))
714 txgbe_release_swfw_sync(hw, mngsem & (fwmask | swmask));
717 return TXGBE_ERR_SWFW_SYNC;
721 * txgbe_release_swfw_sync - Release SWFW semaphore
722 * @hw: pointer to hardware structure
723 * @mask: Mask to specify which semaphore to release
725 * Releases the SWFW semaphore through the MNGSEM register for the specified
726 * function (CSR, PHY0, PHY1, EEPROM, Flash)
728 void txgbe_release_swfw_sync(struct txgbe_hw *hw, u32 mask)
733 DEBUGFUNC("txgbe_release_swfw_sync");
735 txgbe_get_eeprom_semaphore(hw);
737 mngsem = rd32(hw, TXGBE_MNGSEM);
739 wr32(hw, TXGBE_MNGSEM, mngsem);
741 txgbe_release_eeprom_semaphore(hw);
745 * txgbe_disable_sec_rx_path - Stops the receive data path
746 * @hw: pointer to hardware structure
748 * Stops the receive data path and waits for the HW to internally empty
749 * the Rx security block
751 s32 txgbe_disable_sec_rx_path(struct txgbe_hw *hw)
753 #define TXGBE_MAX_SECRX_POLL 4000
758 DEBUGFUNC("txgbe_disable_sec_rx_path");
760 secrxreg = rd32(hw, TXGBE_SECRXCTL);
761 secrxreg |= TXGBE_SECRXCTL_XDSA;
762 wr32(hw, TXGBE_SECRXCTL, secrxreg);
763 for (i = 0; i < TXGBE_MAX_SECRX_POLL; i++) {
764 secrxreg = rd32(hw, TXGBE_SECRXSTAT);
765 if (!(secrxreg & TXGBE_SECRXSTAT_RDY))
766 /* Use interrupt-safe sleep just in case */
772 /* For informational purposes only */
773 if (i >= TXGBE_MAX_SECRX_POLL)
774 DEBUGOUT("Rx unit being enabled before security "
775 "path fully disabled. Continuing with init.\n");
781 * txgbe_enable_sec_rx_path - Enables the receive data path
782 * @hw: pointer to hardware structure
784 * Enables the receive data path.
786 s32 txgbe_enable_sec_rx_path(struct txgbe_hw *hw)
790 DEBUGFUNC("txgbe_enable_sec_rx_path");
792 secrxreg = rd32(hw, TXGBE_SECRXCTL);
793 secrxreg &= ~TXGBE_SECRXCTL_XDSA;
794 wr32(hw, TXGBE_SECRXCTL, secrxreg);
801 * txgbe_disable_sec_tx_path - Stops the transmit data path
802 * @hw: pointer to hardware structure
804 * Stops the transmit data path and waits for the HW to internally empty
805 * the Tx security block
807 int txgbe_disable_sec_tx_path(struct txgbe_hw *hw)
809 #define TXGBE_MAX_SECTX_POLL 40
814 sectxreg = rd32(hw, TXGBE_SECTXCTL);
815 sectxreg |= TXGBE_SECTXCTL_XDSA;
816 wr32(hw, TXGBE_SECTXCTL, sectxreg);
817 for (i = 0; i < TXGBE_MAX_SECTX_POLL; i++) {
818 sectxreg = rd32(hw, TXGBE_SECTXSTAT);
819 if (sectxreg & TXGBE_SECTXSTAT_RDY)
821 /* Use interrupt-safe sleep just in case */
825 /* For informational purposes only */
826 if (i >= TXGBE_MAX_SECTX_POLL)
827 PMD_DRV_LOG(DEBUG, "Tx unit being enabled before security "
828 "path fully disabled. Continuing with init.");
834 * txgbe_enable_sec_tx_path - Enables the transmit data path
835 * @hw: pointer to hardware structure
837 * Enables the transmit data path.
839 int txgbe_enable_sec_tx_path(struct txgbe_hw *hw)
843 sectxreg = rd32(hw, TXGBE_SECTXCTL);
844 sectxreg &= ~TXGBE_SECTXCTL_XDSA;
845 wr32(hw, TXGBE_SECTXCTL, sectxreg);
852 * txgbe_get_san_mac_addr_offset - Get SAN MAC address offset from the EEPROM
853 * @hw: pointer to hardware structure
854 * @san_mac_offset: SAN MAC address offset
856 * This function will read the EEPROM location for the SAN MAC address
857 * pointer, and returns the value at that location. This is used in both
858 * get and set mac_addr routines.
860 static s32 txgbe_get_san_mac_addr_offset(struct txgbe_hw *hw,
865 DEBUGFUNC("txgbe_get_san_mac_addr_offset");
868 * First read the EEPROM pointer to see if the MAC addresses are
871 err = hw->rom.readw_sw(hw, TXGBE_SAN_MAC_ADDR_PTR,
874 DEBUGOUT("eeprom at offset %d failed",
875 TXGBE_SAN_MAC_ADDR_PTR);
882 * txgbe_get_san_mac_addr - SAN MAC address retrieval from the EEPROM
883 * @hw: pointer to hardware structure
884 * @san_mac_addr: SAN MAC address
886 * Reads the SAN MAC address from the EEPROM, if it's available. This is
887 * per-port, so set_lan_id() must be called before reading the addresses.
888 * set_lan_id() is called by identify_sfp(), but this cannot be relied
889 * upon for non-SFP connections, so we must call it here.
891 s32 txgbe_get_san_mac_addr(struct txgbe_hw *hw, u8 *san_mac_addr)
893 u16 san_mac_data, san_mac_offset;
897 DEBUGFUNC("txgbe_get_san_mac_addr");
900 * First read the EEPROM pointer to see if the MAC addresses are
901 * available. If they're not, no point in calling set_lan_id() here.
903 err = txgbe_get_san_mac_addr_offset(hw, &san_mac_offset);
904 if (err || san_mac_offset == 0 || san_mac_offset == 0xFFFF)
905 goto san_mac_addr_out;
907 /* apply the port offset to the address offset */
908 (hw->bus.func) ? (san_mac_offset += TXGBE_SAN_MAC_ADDR_PORT1_OFFSET) :
909 (san_mac_offset += TXGBE_SAN_MAC_ADDR_PORT0_OFFSET);
910 for (i = 0; i < 3; i++) {
911 err = hw->rom.read16(hw, san_mac_offset,
914 DEBUGOUT("eeprom read at offset %d failed",
916 goto san_mac_addr_out;
918 san_mac_addr[i * 2] = (u8)(san_mac_data);
919 san_mac_addr[i * 2 + 1] = (u8)(san_mac_data >> 8);
926 * No addresses available in this EEPROM. It's not an
927 * error though, so just wipe the local address and return.
929 for (i = 0; i < 6; i++)
930 san_mac_addr[i] = 0xFF;
935 * txgbe_set_san_mac_addr - Write the SAN MAC address to the EEPROM
936 * @hw: pointer to hardware structure
937 * @san_mac_addr: SAN MAC address
939 * Write a SAN MAC address to the EEPROM.
941 s32 txgbe_set_san_mac_addr(struct txgbe_hw *hw, u8 *san_mac_addr)
944 u16 san_mac_data, san_mac_offset;
947 DEBUGFUNC("txgbe_set_san_mac_addr");
949 /* Look for SAN mac address pointer. If not defined, return */
950 err = txgbe_get_san_mac_addr_offset(hw, &san_mac_offset);
951 if (err || san_mac_offset == 0 || san_mac_offset == 0xFFFF)
952 return TXGBE_ERR_NO_SAN_ADDR_PTR;
954 /* Apply the port offset to the address offset */
955 (hw->bus.func) ? (san_mac_offset += TXGBE_SAN_MAC_ADDR_PORT1_OFFSET) :
956 (san_mac_offset += TXGBE_SAN_MAC_ADDR_PORT0_OFFSET);
958 for (i = 0; i < 3; i++) {
959 san_mac_data = (u16)((u16)(san_mac_addr[i * 2 + 1]) << 8);
960 san_mac_data |= (u16)(san_mac_addr[i * 2]);
961 hw->rom.write16(hw, san_mac_offset, san_mac_data);
969 * txgbe_init_uta_tables - Initialize the Unicast Table Array
970 * @hw: pointer to hardware structure
972 s32 txgbe_init_uta_tables(struct txgbe_hw *hw)
976 DEBUGFUNC("txgbe_init_uta_tables");
977 DEBUGOUT(" Clearing UTA\n");
979 for (i = 0; i < 128; i++)
980 wr32(hw, TXGBE_UCADDRTBL(i), 0);
986 * txgbe_clear_vfta - Clear VLAN filter table
987 * @hw: pointer to hardware structure
989 * Clears the VLAN filer table, and the VMDq index associated with the filter
991 s32 txgbe_clear_vfta(struct txgbe_hw *hw)
995 DEBUGFUNC("txgbe_clear_vfta");
997 for (offset = 0; offset < hw->mac.vft_size; offset++)
998 wr32(hw, TXGBE_VLANTBL(offset), 0);
1000 for (offset = 0; offset < TXGBE_NUM_POOL; offset++) {
1001 wr32(hw, TXGBE_PSRVLANIDX, offset);
1002 wr32(hw, TXGBE_PSRVLAN, 0);
1003 wr32(hw, TXGBE_PSRVLANPLM(0), 0);
1004 wr32(hw, TXGBE_PSRVLANPLM(1), 0);
1011 * txgbe_need_crosstalk_fix - Determine if we need to do cross talk fix
1012 * @hw: pointer to hardware structure
1014 * Contains the logic to identify if we need to verify link for the
1017 static bool txgbe_need_crosstalk_fix(struct txgbe_hw *hw)
1019 /* Does FW say we need the fix */
1020 if (!hw->need_crosstalk_fix)
1023 /* Only consider SFP+ PHYs i.e. media type fiber */
1024 switch (hw->phy.media_type) {
1025 case txgbe_media_type_fiber:
1026 case txgbe_media_type_fiber_qsfp:
1036 * txgbe_check_mac_link - Determine link and speed status
1037 * @hw: pointer to hardware structure
1038 * @speed: pointer to link speed
1039 * @link_up: true when link is up
1040 * @link_up_wait_to_complete: bool used to wait for link up or not
1042 * Reads the links register to determine if link is up and the current speed
1044 s32 txgbe_check_mac_link(struct txgbe_hw *hw, u32 *speed,
1045 bool *link_up, bool link_up_wait_to_complete)
1047 u32 links_reg, links_orig;
1050 DEBUGFUNC("txgbe_check_mac_link");
1052 /* If Crosstalk fix enabled do the sanity check of making sure
1053 * the SFP+ cage is full.
1055 if (txgbe_need_crosstalk_fix(hw)) {
1058 switch (hw->mac.type) {
1059 case txgbe_mac_raptor:
1060 sfp_cage_full = !rd32m(hw, TXGBE_GPIODATA,
1064 /* sanity check - No SFP+ devices here */
1065 sfp_cage_full = false;
1069 if (!sfp_cage_full) {
1071 *speed = TXGBE_LINK_SPEED_UNKNOWN;
1076 /* clear the old state */
1077 links_orig = rd32(hw, TXGBE_PORTSTAT);
1079 links_reg = rd32(hw, TXGBE_PORTSTAT);
1081 if (links_orig != links_reg) {
1082 DEBUGOUT("LINKS changed from %08X to %08X\n",
1083 links_orig, links_reg);
1086 if (link_up_wait_to_complete) {
1087 for (i = 0; i < hw->mac.max_link_up_time; i++) {
1088 if (!(links_reg & TXGBE_PORTSTAT_UP)) {
1095 links_reg = rd32(hw, TXGBE_PORTSTAT);
1098 if (links_reg & TXGBE_PORTSTAT_UP)
1104 switch (links_reg & TXGBE_PORTSTAT_BW_MASK) {
1105 case TXGBE_PORTSTAT_BW_10G:
1106 *speed = TXGBE_LINK_SPEED_10GB_FULL;
1108 case TXGBE_PORTSTAT_BW_1G:
1109 *speed = TXGBE_LINK_SPEED_1GB_FULL;
1111 case TXGBE_PORTSTAT_BW_100M:
1112 *speed = TXGBE_LINK_SPEED_100M_FULL;
1115 *speed = TXGBE_LINK_SPEED_UNKNOWN;
1122 * txgbe_get_wwn_prefix - Get alternative WWNN/WWPN prefix from
1124 * @hw: pointer to hardware structure
1125 * @wwnn_prefix: the alternative WWNN prefix
1126 * @wwpn_prefix: the alternative WWPN prefix
1128 * This function will read the EEPROM from the alternative SAN MAC address
1129 * block to check the support for the alternative WWNN/WWPN prefix support.
1131 s32 txgbe_get_wwn_prefix(struct txgbe_hw *hw, u16 *wwnn_prefix,
1135 u16 alt_san_mac_blk_offset;
1137 DEBUGFUNC("txgbe_get_wwn_prefix");
1139 /* clear output first */
1140 *wwnn_prefix = 0xFFFF;
1141 *wwpn_prefix = 0xFFFF;
1143 /* check if alternative SAN MAC is supported */
1144 offset = TXGBE_ALT_SAN_MAC_ADDR_BLK_PTR;
1145 if (hw->rom.readw_sw(hw, offset, &alt_san_mac_blk_offset))
1146 goto wwn_prefix_err;
1148 if (alt_san_mac_blk_offset == 0 || alt_san_mac_blk_offset == 0xFFFF)
1149 goto wwn_prefix_out;
1151 /* check capability in alternative san mac address block */
1152 offset = alt_san_mac_blk_offset + TXGBE_ALT_SAN_MAC_ADDR_CAPS_OFFSET;
1153 if (hw->rom.read16(hw, offset, &caps))
1154 goto wwn_prefix_err;
1155 if (!(caps & TXGBE_ALT_SAN_MAC_ADDR_CAPS_ALTWWN))
1156 goto wwn_prefix_out;
1158 /* get the corresponding prefix for WWNN/WWPN */
1159 offset = alt_san_mac_blk_offset + TXGBE_ALT_SAN_MAC_ADDR_WWNN_OFFSET;
1160 if (hw->rom.read16(hw, offset, wwnn_prefix))
1161 DEBUGOUT("eeprom read at offset %d failed", offset);
1163 offset = alt_san_mac_blk_offset + TXGBE_ALT_SAN_MAC_ADDR_WWPN_OFFSET;
1164 if (hw->rom.read16(hw, offset, wwpn_prefix))
1165 goto wwn_prefix_err;
1171 DEBUGOUT("eeprom read at offset %d failed", offset);
1176 * txgbe_get_device_caps - Get additional device capabilities
1177 * @hw: pointer to hardware structure
1178 * @device_caps: the EEPROM word with the extra device capabilities
1180 * This function will read the EEPROM location for the device capabilities,
1181 * and return the word through device_caps.
1183 s32 txgbe_get_device_caps(struct txgbe_hw *hw, u16 *device_caps)
1185 DEBUGFUNC("txgbe_get_device_caps");
1187 hw->rom.readw_sw(hw, TXGBE_DEVICE_CAPS, device_caps);
1193 * txgbe_clear_tx_pending - Clear pending TX work from the PCIe fifo
1194 * @hw: pointer to the hardware structure
1196 * The MACs can experience issues if TX work is still pending
1197 * when a reset occurs. This function prevents this by flushing the PCIe
1198 * buffers on the system.
1200 void txgbe_clear_tx_pending(struct txgbe_hw *hw)
1202 u32 hlreg0, i, poll;
1205 * If double reset is not requested then all transactions should
1206 * already be clear and as such there is no work to do
1208 if (!(hw->mac.flags & TXGBE_FLAGS_DOUBLE_RESET_REQUIRED))
1211 hlreg0 = rd32(hw, TXGBE_PSRCTL);
1212 wr32(hw, TXGBE_PSRCTL, hlreg0 | TXGBE_PSRCTL_LBENA);
1214 /* Wait for a last completion before clearing buffers */
1219 * Before proceeding, make sure that the PCIe block does not have
1220 * transactions pending.
1222 poll = (800 * 11) / 10;
1223 for (i = 0; i < poll; i++)
1226 /* Flush all writes and allow 20usec for all transactions to clear */
1230 /* restore previous register values */
1231 wr32(hw, TXGBE_PSRCTL, hlreg0);
1235 * txgbe_get_thermal_sensor_data - Gathers thermal sensor data
1236 * @hw: pointer to hardware structure
1238 * Returns the thermal sensor data structure
1240 s32 txgbe_get_thermal_sensor_data(struct txgbe_hw *hw)
1242 struct txgbe_thermal_sensor_data *data = &hw->mac.thermal_sensor_data;
1246 DEBUGFUNC("txgbe_get_thermal_sensor_data");
1248 /* Only support thermal sensors attached to physical port 0 */
1249 if (hw->bus.lan_id != 0)
1250 return TXGBE_NOT_IMPLEMENTED;
1252 ts_stat = rd32(hw, TXGBE_TSSTAT);
1253 tsv = (s64)TXGBE_TSSTAT_DATA(ts_stat);
1254 tsv = tsv > 1200 ? tsv : 1200;
1255 tsv = -(48380 << 8) / 1000
1256 + tsv * (31020 << 8) / 100000
1257 - tsv * tsv * (18201 << 8) / 100000000
1258 + tsv * tsv * tsv * (81542 << 8) / 1000000000000
1259 - tsv * tsv * tsv * tsv * (16743 << 8) / 1000000000000000;
1262 data->sensor[0].temp = (s16)tsv;
1268 * txgbe_init_thermal_sensor_thresh - Inits thermal sensor thresholds
1269 * @hw: pointer to hardware structure
1271 * Inits the thermal sensor thresholds according to the NVM map
1272 * and save off the threshold and location values into mac.thermal_sensor_data
1274 s32 txgbe_init_thermal_sensor_thresh(struct txgbe_hw *hw)
1276 struct txgbe_thermal_sensor_data *data = &hw->mac.thermal_sensor_data;
1278 DEBUGFUNC("txgbe_init_thermal_sensor_thresh");
1280 memset(data, 0, sizeof(struct txgbe_thermal_sensor_data));
1282 if (hw->bus.lan_id != 0)
1283 return TXGBE_NOT_IMPLEMENTED;
1285 wr32(hw, TXGBE_TSCTRL, TXGBE_TSCTRL_EVALMD);
1286 wr32(hw, TXGBE_TSINTR,
1287 TXGBE_TSINTR_AEN | TXGBE_TSINTR_DEN);
1288 wr32(hw, TXGBE_TSEN, TXGBE_TSEN_ENA);
1291 data->sensor[0].alarm_thresh = 100;
1292 wr32(hw, TXGBE_TSATHRE, 677);
1293 data->sensor[0].dalarm_thresh = 90;
1294 wr32(hw, TXGBE_TSDTHRE, 614);
1299 void txgbe_disable_rx(struct txgbe_hw *hw)
1303 pfdtxgswc = rd32(hw, TXGBE_PSRCTL);
1304 if (pfdtxgswc & TXGBE_PSRCTL_LBENA) {
1305 pfdtxgswc &= ~TXGBE_PSRCTL_LBENA;
1306 wr32(hw, TXGBE_PSRCTL, pfdtxgswc);
1307 hw->mac.set_lben = true;
1309 hw->mac.set_lben = false;
1312 wr32m(hw, TXGBE_PBRXCTL, TXGBE_PBRXCTL_ENA, 0);
1313 wr32m(hw, TXGBE_MACRXCFG, TXGBE_MACRXCFG_ENA, 0);
1316 void txgbe_enable_rx(struct txgbe_hw *hw)
1320 wr32m(hw, TXGBE_MACRXCFG, TXGBE_MACRXCFG_ENA, TXGBE_MACRXCFG_ENA);
1321 wr32m(hw, TXGBE_PBRXCTL, TXGBE_PBRXCTL_ENA, TXGBE_PBRXCTL_ENA);
1323 if (hw->mac.set_lben) {
1324 pfdtxgswc = rd32(hw, TXGBE_PSRCTL);
1325 pfdtxgswc |= TXGBE_PSRCTL_LBENA;
1326 wr32(hw, TXGBE_PSRCTL, pfdtxgswc);
1327 hw->mac.set_lben = false;
1332 * txgbe_setup_mac_link_multispeed_fiber - Set MAC link speed
1333 * @hw: pointer to hardware structure
1334 * @speed: new link speed
1335 * @autoneg_wait_to_complete: true when waiting for completion is needed
1337 * Set the link speed in the MAC and/or PHY register and restarts link.
1339 s32 txgbe_setup_mac_link_multispeed_fiber(struct txgbe_hw *hw,
1341 bool autoneg_wait_to_complete)
1343 u32 link_speed = TXGBE_LINK_SPEED_UNKNOWN;
1344 u32 highest_link_speed = TXGBE_LINK_SPEED_UNKNOWN;
1348 bool autoneg, link_up = false;
1350 DEBUGFUNC("txgbe_setup_mac_link_multispeed_fiber");
1352 /* Mask off requested but non-supported speeds */
1353 status = hw->mac.get_link_capabilities(hw, &link_speed, &autoneg);
1357 speed &= link_speed;
1359 /* Try each speed one by one, highest priority first. We do this in
1360 * software because 10Gb fiber doesn't support speed autonegotiation.
1362 if (speed & TXGBE_LINK_SPEED_10GB_FULL) {
1364 highest_link_speed = TXGBE_LINK_SPEED_10GB_FULL;
1366 /* Set the module link speed */
1367 switch (hw->phy.media_type) {
1368 case txgbe_media_type_fiber:
1369 hw->mac.set_rate_select_speed(hw,
1370 TXGBE_LINK_SPEED_10GB_FULL);
1372 case txgbe_media_type_fiber_qsfp:
1373 /* QSFP module automatically detects MAC link speed */
1376 DEBUGOUT("Unexpected media type.\n");
1380 /* Allow module to change analog characteristics (1G->10G) */
1383 status = hw->mac.setup_mac_link(hw,
1384 TXGBE_LINK_SPEED_10GB_FULL,
1385 autoneg_wait_to_complete);
1389 /* Flap the Tx laser if it has not already been done */
1390 hw->mac.flap_tx_laser(hw);
1392 /* Wait for the controller to acquire link. Per IEEE 802.3ap,
1393 * Section 73.10.2, we may have to wait up to 500ms if KR is
1394 * attempted. uses the same timing for 10g SFI.
1396 for (i = 0; i < 5; i++) {
1397 /* Wait for the link partner to also set speed */
1400 /* If we have link, just jump out */
1401 status = hw->mac.check_link(hw, &link_speed,
1411 if (speed & TXGBE_LINK_SPEED_1GB_FULL) {
1413 if (highest_link_speed == TXGBE_LINK_SPEED_UNKNOWN)
1414 highest_link_speed = TXGBE_LINK_SPEED_1GB_FULL;
1416 /* Set the module link speed */
1417 switch (hw->phy.media_type) {
1418 case txgbe_media_type_fiber:
1419 hw->mac.set_rate_select_speed(hw,
1420 TXGBE_LINK_SPEED_1GB_FULL);
1422 case txgbe_media_type_fiber_qsfp:
1423 /* QSFP module automatically detects link speed */
1426 DEBUGOUT("Unexpected media type.\n");
1430 /* Allow module to change analog characteristics (10G->1G) */
1433 status = hw->mac.setup_mac_link(hw,
1434 TXGBE_LINK_SPEED_1GB_FULL,
1435 autoneg_wait_to_complete);
1439 /* Flap the Tx laser if it has not already been done */
1440 hw->mac.flap_tx_laser(hw);
1442 /* Wait for the link partner to also set speed */
1445 /* If we have link, just jump out */
1446 status = hw->mac.check_link(hw, &link_speed, &link_up, false);
1454 /* We didn't get link. Configure back to the highest speed we tried,
1455 * (if there was more than one). We call ourselves back with just the
1456 * single highest speed that the user requested.
1459 status = txgbe_setup_mac_link_multispeed_fiber(hw,
1461 autoneg_wait_to_complete);
1464 /* Set autoneg_advertised value based on input link speed */
1465 hw->phy.autoneg_advertised = 0;
1467 if (speed & TXGBE_LINK_SPEED_10GB_FULL)
1468 hw->phy.autoneg_advertised |= TXGBE_LINK_SPEED_10GB_FULL;
1470 if (speed & TXGBE_LINK_SPEED_1GB_FULL)
1471 hw->phy.autoneg_advertised |= TXGBE_LINK_SPEED_1GB_FULL;
1477 * txgbe_init_shared_code - Initialize the shared code
1478 * @hw: pointer to hardware structure
1480 * This will assign function pointers and assign the MAC type and PHY code.
1481 * Does not touch the hardware. This function must be called prior to any
1482 * other function in the shared code. The txgbe_hw structure should be
1483 * memset to 0 prior to calling this function. The following fields in
1484 * hw structure should be filled in prior to calling this function:
1485 * hw_addr, back, device_id, vendor_id, subsystem_device_id,
1486 * subsystem_vendor_id, and revision_id
1488 s32 txgbe_init_shared_code(struct txgbe_hw *hw)
1492 DEBUGFUNC("txgbe_init_shared_code");
1497 txgbe_set_mac_type(hw);
1499 txgbe_init_ops_dummy(hw);
1500 switch (hw->mac.type) {
1501 case txgbe_mac_raptor:
1502 status = txgbe_init_ops_pf(hw);
1505 status = TXGBE_ERR_DEVICE_NOT_SUPPORTED;
1508 hw->mac.max_link_up_time = TXGBE_LINK_UP_TIME;
1510 hw->bus.set_lan_id(hw);
1516 * txgbe_set_mac_type - Sets MAC type
1517 * @hw: pointer to the HW structure
1519 * This function sets the mac type of the adapter based on the
1520 * vendor ID and device ID stored in the hw structure.
1522 s32 txgbe_set_mac_type(struct txgbe_hw *hw)
1526 DEBUGFUNC("txgbe_set_mac_type");
1528 if (hw->vendor_id != PCI_VENDOR_ID_WANGXUN) {
1529 DEBUGOUT("Unsupported vendor id: %x", hw->vendor_id);
1530 return TXGBE_ERR_DEVICE_NOT_SUPPORTED;
1533 switch (hw->device_id) {
1534 case TXGBE_DEV_ID_RAPTOR_KR_KX_KX4:
1535 hw->phy.media_type = txgbe_media_type_backplane;
1536 hw->mac.type = txgbe_mac_raptor;
1538 case TXGBE_DEV_ID_RAPTOR_XAUI:
1539 case TXGBE_DEV_ID_RAPTOR_SGMII:
1540 hw->phy.media_type = txgbe_media_type_copper;
1541 hw->mac.type = txgbe_mac_raptor;
1543 case TXGBE_DEV_ID_RAPTOR_SFP:
1544 case TXGBE_DEV_ID_WX1820_SFP:
1545 hw->phy.media_type = txgbe_media_type_fiber;
1546 hw->mac.type = txgbe_mac_raptor;
1548 case TXGBE_DEV_ID_RAPTOR_QSFP:
1549 hw->phy.media_type = txgbe_media_type_fiber_qsfp;
1550 hw->mac.type = txgbe_mac_raptor;
1552 case TXGBE_DEV_ID_RAPTOR_VF:
1553 case TXGBE_DEV_ID_RAPTOR_VF_HV:
1554 hw->phy.media_type = txgbe_media_type_virtual;
1555 hw->mac.type = txgbe_mac_raptor_vf;
1558 err = TXGBE_ERR_DEVICE_NOT_SUPPORTED;
1559 DEBUGOUT("Unsupported device id: %x", hw->device_id);
1563 DEBUGOUT("found mac: %d media: %d, returns: %d\n",
1564 hw->mac.type, hw->phy.media_type, err);
1568 void txgbe_init_mac_link_ops(struct txgbe_hw *hw)
1570 struct txgbe_mac_info *mac = &hw->mac;
1572 DEBUGFUNC("txgbe_init_mac_link_ops");
1575 * enable the laser control functions for SFP+ fiber
1576 * and MNG not enabled
1578 if (hw->phy.media_type == txgbe_media_type_fiber &&
1579 !txgbe_mng_enabled(hw)) {
1580 mac->disable_tx_laser =
1581 txgbe_disable_tx_laser_multispeed_fiber;
1582 mac->enable_tx_laser =
1583 txgbe_enable_tx_laser_multispeed_fiber;
1584 mac->flap_tx_laser =
1585 txgbe_flap_tx_laser_multispeed_fiber;
1588 if ((hw->phy.media_type == txgbe_media_type_fiber ||
1589 hw->phy.media_type == txgbe_media_type_fiber_qsfp) &&
1590 hw->phy.multispeed_fiber) {
1591 /* Set up dual speed SFP+ support */
1592 mac->setup_link = txgbe_setup_mac_link_multispeed_fiber;
1593 mac->setup_mac_link = txgbe_setup_mac_link;
1594 mac->set_rate_select_speed = txgbe_set_hard_rate_select_speed;
1595 } else if ((hw->phy.media_type == txgbe_media_type_backplane) &&
1596 (hw->phy.smart_speed == txgbe_smart_speed_auto ||
1597 hw->phy.smart_speed == txgbe_smart_speed_on) &&
1598 !txgbe_verify_lesm_fw_enabled_raptor(hw)) {
1599 mac->setup_link = txgbe_setup_mac_link_smartspeed;
1601 mac->setup_link = txgbe_setup_mac_link;
1606 * txgbe_init_phy_raptor - PHY/SFP specific init
1607 * @hw: pointer to hardware structure
1609 * Initialize any function pointers that were not able to be
1610 * set during init_shared_code because the PHY/SFP type was
1611 * not known. Perform the SFP init if necessary.
1614 s32 txgbe_init_phy_raptor(struct txgbe_hw *hw)
1616 struct txgbe_mac_info *mac = &hw->mac;
1617 struct txgbe_phy_info *phy = &hw->phy;
1620 DEBUGFUNC("txgbe_init_phy_raptor");
1622 if (hw->device_id == TXGBE_DEV_ID_RAPTOR_QSFP) {
1623 /* Store flag indicating I2C bus access control unit. */
1624 hw->phy.qsfp_shared_i2c_bus = TRUE;
1626 /* Initialize access to QSFP+ I2C bus */
1630 /* Identify the PHY or SFP module */
1631 err = phy->identify(hw);
1632 if (err == TXGBE_ERR_SFP_NOT_SUPPORTED)
1633 goto init_phy_ops_out;
1635 /* Setup function pointers based on detected SFP module and speeds */
1636 txgbe_init_mac_link_ops(hw);
1638 /* If copper media, overwrite with copper function pointers */
1639 if (phy->media_type == txgbe_media_type_copper) {
1640 mac->setup_link = txgbe_setup_copper_link_raptor;
1641 mac->get_link_capabilities =
1642 txgbe_get_copper_link_capabilities;
1645 /* Set necessary function pointers based on PHY type */
1646 switch (hw->phy.type) {
1648 phy->setup_link = txgbe_setup_phy_link_tnx;
1649 phy->check_link = txgbe_check_phy_link_tnx;
1659 s32 txgbe_setup_sfp_modules(struct txgbe_hw *hw)
1663 DEBUGFUNC("txgbe_setup_sfp_modules");
1665 if (hw->phy.sfp_type == txgbe_sfp_type_unknown)
1668 txgbe_init_mac_link_ops(hw);
1670 /* PHY config will finish before releasing the semaphore */
1671 err = hw->mac.acquire_swfw_sync(hw, TXGBE_MNGSEM_SWPHY);
1673 return TXGBE_ERR_SWFW_SYNC;
1675 /* Release the semaphore */
1676 hw->mac.release_swfw_sync(hw, TXGBE_MNGSEM_SWPHY);
1678 /* Delay obtaining semaphore again to allow FW access
1679 * prot_autoc_write uses the semaphore too.
1681 msec_delay(hw->rom.semaphore_delay);
1684 DEBUGOUT("sfp module setup not complete\n");
1685 return TXGBE_ERR_SFP_SETUP_NOT_COMPLETE;
1692 * txgbe_init_ops_pf - Inits func ptrs and MAC type
1693 * @hw: pointer to hardware structure
1695 * Initialize the function pointers and assign the MAC type.
1696 * Does not touch the hardware.
1698 s32 txgbe_init_ops_pf(struct txgbe_hw *hw)
1700 struct txgbe_bus_info *bus = &hw->bus;
1701 struct txgbe_mac_info *mac = &hw->mac;
1702 struct txgbe_phy_info *phy = &hw->phy;
1703 struct txgbe_rom_info *rom = &hw->rom;
1705 DEBUGFUNC("txgbe_init_ops_pf");
1708 bus->set_lan_id = txgbe_set_lan_id_multi_port;
1711 phy->get_media_type = txgbe_get_media_type_raptor;
1712 phy->identify = txgbe_identify_phy;
1713 phy->init = txgbe_init_phy_raptor;
1714 phy->read_reg = txgbe_read_phy_reg;
1715 phy->write_reg = txgbe_write_phy_reg;
1716 phy->read_reg_mdi = txgbe_read_phy_reg_mdi;
1717 phy->write_reg_mdi = txgbe_write_phy_reg_mdi;
1718 phy->setup_link = txgbe_setup_phy_link;
1719 phy->setup_link_speed = txgbe_setup_phy_link_speed;
1720 phy->read_i2c_byte = txgbe_read_i2c_byte;
1721 phy->write_i2c_byte = txgbe_write_i2c_byte;
1722 phy->read_i2c_eeprom = txgbe_read_i2c_eeprom;
1723 phy->write_i2c_eeprom = txgbe_write_i2c_eeprom;
1724 phy->reset = txgbe_reset_phy;
1727 mac->init_hw = txgbe_init_hw;
1728 mac->start_hw = txgbe_start_hw_raptor;
1729 mac->clear_hw_cntrs = txgbe_clear_hw_cntrs;
1730 mac->enable_rx_dma = txgbe_enable_rx_dma_raptor;
1731 mac->get_mac_addr = txgbe_get_mac_addr;
1732 mac->stop_hw = txgbe_stop_hw;
1733 mac->acquire_swfw_sync = txgbe_acquire_swfw_sync;
1734 mac->release_swfw_sync = txgbe_release_swfw_sync;
1735 mac->reset_hw = txgbe_reset_hw;
1737 mac->disable_sec_rx_path = txgbe_disable_sec_rx_path;
1738 mac->enable_sec_rx_path = txgbe_enable_sec_rx_path;
1739 mac->disable_sec_tx_path = txgbe_disable_sec_tx_path;
1740 mac->enable_sec_tx_path = txgbe_enable_sec_tx_path;
1741 mac->get_san_mac_addr = txgbe_get_san_mac_addr;
1742 mac->set_san_mac_addr = txgbe_set_san_mac_addr;
1743 mac->get_device_caps = txgbe_get_device_caps;
1744 mac->get_wwn_prefix = txgbe_get_wwn_prefix;
1745 mac->autoc_read = txgbe_autoc_read;
1746 mac->autoc_write = txgbe_autoc_write;
1748 mac->set_rar = txgbe_set_rar;
1749 mac->clear_rar = txgbe_clear_rar;
1750 mac->init_rx_addrs = txgbe_init_rx_addrs;
1751 mac->enable_rx = txgbe_enable_rx;
1752 mac->disable_rx = txgbe_disable_rx;
1753 mac->clear_vfta = txgbe_clear_vfta;
1754 mac->init_uta_tables = txgbe_init_uta_tables;
1755 mac->setup_sfp = txgbe_setup_sfp_modules;
1757 mac->get_link_capabilities = txgbe_get_link_capabilities_raptor;
1758 mac->check_link = txgbe_check_mac_link;
1760 /* Manageability interface */
1761 mac->set_fw_drv_ver = txgbe_hic_set_drv_ver;
1762 mac->get_thermal_sensor_data = txgbe_get_thermal_sensor_data;
1763 mac->init_thermal_sensor_thresh = txgbe_init_thermal_sensor_thresh;
1766 rom->init_params = txgbe_init_eeprom_params;
1767 rom->read16 = txgbe_ee_read16;
1768 rom->readw_buffer = txgbe_ee_readw_buffer;
1769 rom->readw_sw = txgbe_ee_readw_sw;
1770 rom->read32 = txgbe_ee_read32;
1771 rom->write16 = txgbe_ee_write16;
1772 rom->writew_buffer = txgbe_ee_writew_buffer;
1773 rom->writew_sw = txgbe_ee_writew_sw;
1774 rom->write32 = txgbe_ee_write32;
1775 rom->validate_checksum = txgbe_validate_eeprom_checksum;
1776 rom->update_checksum = txgbe_update_eeprom_checksum;
1777 rom->calc_checksum = txgbe_calc_eeprom_checksum;
1779 mac->mcft_size = TXGBE_RAPTOR_MC_TBL_SIZE;
1780 mac->vft_size = TXGBE_RAPTOR_VFT_TBL_SIZE;
1781 mac->num_rar_entries = TXGBE_RAPTOR_RAR_ENTRIES;
1782 mac->max_rx_queues = TXGBE_RAPTOR_MAX_RX_QUEUES;
1783 mac->max_tx_queues = TXGBE_RAPTOR_MAX_TX_QUEUES;
1789 * txgbe_get_link_capabilities_raptor - Determines link capabilities
1790 * @hw: pointer to hardware structure
1791 * @speed: pointer to link speed
1792 * @autoneg: true when autoneg or autotry is enabled
1794 * Determines the link capabilities by reading the AUTOC register.
1796 s32 txgbe_get_link_capabilities_raptor(struct txgbe_hw *hw,
1803 DEBUGFUNC("txgbe_get_link_capabilities_raptor");
1805 /* Check if 1G SFP module. */
1806 if (hw->phy.sfp_type == txgbe_sfp_type_1g_cu_core0 ||
1807 hw->phy.sfp_type == txgbe_sfp_type_1g_cu_core1 ||
1808 hw->phy.sfp_type == txgbe_sfp_type_1g_lx_core0 ||
1809 hw->phy.sfp_type == txgbe_sfp_type_1g_lx_core1 ||
1810 hw->phy.sfp_type == txgbe_sfp_type_1g_sx_core0 ||
1811 hw->phy.sfp_type == txgbe_sfp_type_1g_sx_core1) {
1812 *speed = TXGBE_LINK_SPEED_1GB_FULL;
1818 * Determine link capabilities based on the stored value of AUTOC,
1819 * which represents EEPROM defaults. If AUTOC value has not
1820 * been stored, use the current register values.
1822 if (hw->mac.orig_link_settings_stored)
1823 autoc = hw->mac.orig_autoc;
1825 autoc = hw->mac.autoc_read(hw);
1827 switch (autoc & TXGBE_AUTOC_LMS_MASK) {
1828 case TXGBE_AUTOC_LMS_1G_LINK_NO_AN:
1829 *speed = TXGBE_LINK_SPEED_1GB_FULL;
1833 case TXGBE_AUTOC_LMS_10G_LINK_NO_AN:
1834 *speed = TXGBE_LINK_SPEED_10GB_FULL;
1838 case TXGBE_AUTOC_LMS_1G_AN:
1839 *speed = TXGBE_LINK_SPEED_1GB_FULL;
1843 case TXGBE_AUTOC_LMS_10G:
1844 *speed = TXGBE_LINK_SPEED_10GB_FULL;
1848 case TXGBE_AUTOC_LMS_KX4_KX_KR:
1849 case TXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN:
1850 *speed = TXGBE_LINK_SPEED_UNKNOWN;
1851 if (autoc & TXGBE_AUTOC_KR_SUPP)
1852 *speed |= TXGBE_LINK_SPEED_10GB_FULL;
1853 if (autoc & TXGBE_AUTOC_KX4_SUPP)
1854 *speed |= TXGBE_LINK_SPEED_10GB_FULL;
1855 if (autoc & TXGBE_AUTOC_KX_SUPP)
1856 *speed |= TXGBE_LINK_SPEED_1GB_FULL;
1860 case TXGBE_AUTOC_LMS_KX4_KX_KR_SGMII:
1861 *speed = TXGBE_LINK_SPEED_100M_FULL;
1862 if (autoc & TXGBE_AUTOC_KR_SUPP)
1863 *speed |= TXGBE_LINK_SPEED_10GB_FULL;
1864 if (autoc & TXGBE_AUTOC_KX4_SUPP)
1865 *speed |= TXGBE_LINK_SPEED_10GB_FULL;
1866 if (autoc & TXGBE_AUTOC_KX_SUPP)
1867 *speed |= TXGBE_LINK_SPEED_1GB_FULL;
1871 case TXGBE_AUTOC_LMS_SGMII_1G_100M:
1872 *speed = TXGBE_LINK_SPEED_1GB_FULL |
1873 TXGBE_LINK_SPEED_100M_FULL |
1874 TXGBE_LINK_SPEED_10M_FULL;
1879 return TXGBE_ERR_LINK_SETUP;
1882 if (hw->phy.multispeed_fiber) {
1883 *speed |= TXGBE_LINK_SPEED_10GB_FULL |
1884 TXGBE_LINK_SPEED_1GB_FULL;
1886 /* QSFP must not enable full auto-negotiation
1887 * Limited autoneg is enabled at 1G
1889 if (hw->phy.media_type == txgbe_media_type_fiber_qsfp)
1899 * txgbe_get_media_type_raptor - Get media type
1900 * @hw: pointer to hardware structure
1902 * Returns the media type (fiber, copper, backplane)
1904 u32 txgbe_get_media_type_raptor(struct txgbe_hw *hw)
1908 DEBUGFUNC("txgbe_get_media_type_raptor");
1910 /* Detect if there is a copper PHY attached. */
1911 switch (hw->phy.type) {
1912 case txgbe_phy_cu_unknown:
1914 media_type = txgbe_media_type_copper;
1920 switch (hw->device_id) {
1921 case TXGBE_DEV_ID_RAPTOR_KR_KX_KX4:
1922 /* Default device ID is mezzanine card KX/KX4 */
1923 media_type = txgbe_media_type_backplane;
1925 case TXGBE_DEV_ID_RAPTOR_SFP:
1926 case TXGBE_DEV_ID_WX1820_SFP:
1927 media_type = txgbe_media_type_fiber;
1929 case TXGBE_DEV_ID_RAPTOR_QSFP:
1930 media_type = txgbe_media_type_fiber_qsfp;
1932 case TXGBE_DEV_ID_RAPTOR_XAUI:
1933 case TXGBE_DEV_ID_RAPTOR_SGMII:
1934 media_type = txgbe_media_type_copper;
1937 media_type = txgbe_media_type_unknown;
1945 * txgbe_start_mac_link_raptor - Setup MAC link settings
1946 * @hw: pointer to hardware structure
1947 * @autoneg_wait_to_complete: true when waiting for completion is needed
1949 * Configures link settings based on values in the txgbe_hw struct.
1950 * Restarts the link. Performs autonegotiation if needed.
1952 s32 txgbe_start_mac_link_raptor(struct txgbe_hw *hw,
1953 bool autoneg_wait_to_complete)
1956 bool got_lock = false;
1958 DEBUGFUNC("txgbe_start_mac_link_raptor");
1960 UNREFERENCED_PARAMETER(autoneg_wait_to_complete);
1962 /* reset_pipeline requires us to hold this lock as it writes to
1965 if (txgbe_verify_lesm_fw_enabled_raptor(hw)) {
1966 status = hw->mac.acquire_swfw_sync(hw, TXGBE_MNGSEM_SWPHY);
1974 txgbe_reset_pipeline_raptor(hw);
1977 hw->mac.release_swfw_sync(hw, TXGBE_MNGSEM_SWPHY);
1979 /* Add delay to filter out noises during initial link setup */
1987 * txgbe_disable_tx_laser_multispeed_fiber - Disable Tx laser
1988 * @hw: pointer to hardware structure
1990 * The base drivers may require better control over SFP+ module
1991 * PHY states. This includes selectively shutting down the Tx
1992 * laser on the PHY, effectively halting physical link.
1994 void txgbe_disable_tx_laser_multispeed_fiber(struct txgbe_hw *hw)
1996 u32 esdp_reg = rd32(hw, TXGBE_GPIODATA);
1998 /* Blocked by MNG FW so bail */
1999 if (txgbe_check_reset_blocked(hw))
2002 /* Disable Tx laser; allow 100us to go dark per spec */
2003 esdp_reg |= (TXGBE_GPIOBIT_0 | TXGBE_GPIOBIT_1);
2004 wr32(hw, TXGBE_GPIODATA, esdp_reg);
2010 * txgbe_enable_tx_laser_multispeed_fiber - Enable Tx laser
2011 * @hw: pointer to hardware structure
2013 * The base drivers may require better control over SFP+ module
2014 * PHY states. This includes selectively turning on the Tx
2015 * laser on the PHY, effectively starting physical link.
2017 void txgbe_enable_tx_laser_multispeed_fiber(struct txgbe_hw *hw)
2019 u32 esdp_reg = rd32(hw, TXGBE_GPIODATA);
2021 /* Enable Tx laser; allow 100ms to light up */
2022 esdp_reg &= ~(TXGBE_GPIOBIT_0 | TXGBE_GPIOBIT_1);
2023 wr32(hw, TXGBE_GPIODATA, esdp_reg);
2029 * txgbe_flap_tx_laser_multispeed_fiber - Flap Tx laser
2030 * @hw: pointer to hardware structure
2032 * When the driver changes the link speeds that it can support,
2033 * it sets autotry_restart to true to indicate that we need to
2034 * initiate a new autotry session with the link partner. To do
2035 * so, we set the speed then disable and re-enable the Tx laser, to
2036 * alert the link partner that it also needs to restart autotry on its
2037 * end. This is consistent with true clause 37 autoneg, which also
2038 * involves a loss of signal.
2040 void txgbe_flap_tx_laser_multispeed_fiber(struct txgbe_hw *hw)
2042 DEBUGFUNC("txgbe_flap_tx_laser_multispeed_fiber");
2044 /* Blocked by MNG FW so bail */
2045 if (txgbe_check_reset_blocked(hw))
2048 if (hw->mac.autotry_restart) {
2049 txgbe_disable_tx_laser_multispeed_fiber(hw);
2050 txgbe_enable_tx_laser_multispeed_fiber(hw);
2051 hw->mac.autotry_restart = false;
2056 * txgbe_set_hard_rate_select_speed - Set module link speed
2057 * @hw: pointer to hardware structure
2058 * @speed: link speed to set
2060 * Set module link speed via RS0/RS1 rate select pins.
2062 void txgbe_set_hard_rate_select_speed(struct txgbe_hw *hw,
2065 u32 esdp_reg = rd32(hw, TXGBE_GPIODATA);
2068 case TXGBE_LINK_SPEED_10GB_FULL:
2069 esdp_reg |= (TXGBE_GPIOBIT_4 | TXGBE_GPIOBIT_5);
2071 case TXGBE_LINK_SPEED_1GB_FULL:
2072 esdp_reg &= ~(TXGBE_GPIOBIT_4 | TXGBE_GPIOBIT_5);
2075 DEBUGOUT("Invalid fixed module speed\n");
2079 wr32(hw, TXGBE_GPIODATA, esdp_reg);
2084 * txgbe_setup_mac_link_smartspeed - Set MAC link speed using SmartSpeed
2085 * @hw: pointer to hardware structure
2086 * @speed: new link speed
2087 * @autoneg_wait_to_complete: true when waiting for completion is needed
2089 * Implements the Intel SmartSpeed algorithm.
2091 s32 txgbe_setup_mac_link_smartspeed(struct txgbe_hw *hw,
2093 bool autoneg_wait_to_complete)
2096 u32 link_speed = TXGBE_LINK_SPEED_UNKNOWN;
2098 bool link_up = false;
2099 u32 autoc_reg = rd32_epcs(hw, SR_AN_MMD_ADV_REG1);
2101 DEBUGFUNC("txgbe_setup_mac_link_smartspeed");
2103 /* Set autoneg_advertised value based on input link speed */
2104 hw->phy.autoneg_advertised = 0;
2106 if (speed & TXGBE_LINK_SPEED_10GB_FULL)
2107 hw->phy.autoneg_advertised |= TXGBE_LINK_SPEED_10GB_FULL;
2109 if (speed & TXGBE_LINK_SPEED_1GB_FULL)
2110 hw->phy.autoneg_advertised |= TXGBE_LINK_SPEED_1GB_FULL;
2112 if (speed & TXGBE_LINK_SPEED_100M_FULL)
2113 hw->phy.autoneg_advertised |= TXGBE_LINK_SPEED_100M_FULL;
2116 * Implement Intel SmartSpeed algorithm. SmartSpeed will reduce the
2117 * autoneg advertisement if link is unable to be established at the
2118 * highest negotiated rate. This can sometimes happen due to integrity
2119 * issues with the physical media connection.
2122 /* First, try to get link with full advertisement */
2123 hw->phy.smart_speed_active = false;
2124 for (j = 0; j < TXGBE_SMARTSPEED_MAX_RETRIES; j++) {
2125 status = txgbe_setup_mac_link(hw, speed,
2126 autoneg_wait_to_complete);
2131 * Wait for the controller to acquire link. Per IEEE 802.3ap,
2132 * Section 73.10.2, we may have to wait up to 500ms if KR is
2133 * attempted, or 200ms if KX/KX4/BX/BX4 is attempted, per
2134 * Table 9 in the AN MAS.
2136 for (i = 0; i < 5; i++) {
2139 /* If we have link, just jump out */
2140 status = hw->mac.check_link(hw, &link_speed, &link_up,
2151 * We didn't get link. If we advertised KR plus one of KX4/KX
2152 * (or BX4/BX), then disable KR and try again.
2154 if (((autoc_reg & TXGBE_AUTOC_KR_SUPP) == 0) ||
2155 ((autoc_reg & TXGBE_AUTOC_KX_SUPP) == 0 &&
2156 (autoc_reg & TXGBE_AUTOC_KX4_SUPP) == 0))
2159 /* Turn SmartSpeed on to disable KR support */
2160 hw->phy.smart_speed_active = true;
2161 status = txgbe_setup_mac_link(hw, speed,
2162 autoneg_wait_to_complete);
2167 * Wait for the controller to acquire link. 600ms will allow for
2168 * the AN link_fail_inhibit_timer as well for multiple cycles of
2169 * parallel detect, both 10g and 1g. This allows for the maximum
2170 * connect attempts as defined in the AN MAS table 73-7.
2172 for (i = 0; i < 6; i++) {
2175 /* If we have link, just jump out */
2176 status = hw->mac.check_link(hw, &link_speed, &link_up, false);
2184 /* We didn't get link. Turn SmartSpeed back off. */
2185 hw->phy.smart_speed_active = false;
2186 status = txgbe_setup_mac_link(hw, speed,
2187 autoneg_wait_to_complete);
2190 if (link_up && link_speed == TXGBE_LINK_SPEED_1GB_FULL)
2191 DEBUGOUT("Smartspeed has downgraded the link speed "
2192 "from the maximum advertised\n");
2197 * txgbe_setup_mac_link - Set MAC link speed
2198 * @hw: pointer to hardware structure
2199 * @speed: new link speed
2200 * @autoneg_wait_to_complete: true when waiting for completion is needed
2202 * Set the link speed in the AUTOC register and restarts link.
2204 s32 txgbe_setup_mac_link(struct txgbe_hw *hw,
2206 bool autoneg_wait_to_complete)
2208 bool autoneg = false;
2211 u64 autoc = hw->mac.autoc_read(hw);
2212 u64 pma_pmd_10gs = autoc & TXGBE_AUTOC_10GS_PMA_PMD_MASK;
2213 u64 pma_pmd_1g = autoc & TXGBE_AUTOC_1G_PMA_PMD_MASK;
2214 u64 link_mode = autoc & TXGBE_AUTOC_LMS_MASK;
2215 u64 current_autoc = autoc;
2219 u32 link_capabilities = TXGBE_LINK_SPEED_UNKNOWN;
2221 DEBUGFUNC("txgbe_setup_mac_link");
2223 /* Check to see if speed passed in is supported. */
2224 status = hw->mac.get_link_capabilities(hw,
2225 &link_capabilities, &autoneg);
2229 speed &= link_capabilities;
2230 if (speed == TXGBE_LINK_SPEED_UNKNOWN)
2231 return TXGBE_ERR_LINK_SETUP;
2233 /* Use stored value (EEPROM defaults) of AUTOC to find KR/KX4 support*/
2234 if (hw->mac.orig_link_settings_stored)
2235 orig_autoc = hw->mac.orig_autoc;
2239 link_mode = autoc & TXGBE_AUTOC_LMS_MASK;
2240 pma_pmd_1g = autoc & TXGBE_AUTOC_1G_PMA_PMD_MASK;
2242 if (link_mode == TXGBE_AUTOC_LMS_KX4_KX_KR ||
2243 link_mode == TXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
2244 link_mode == TXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
2245 /* Set KX4/KX/KR support according to speed requested */
2246 autoc &= ~(TXGBE_AUTOC_KX_SUPP |
2247 TXGBE_AUTOC_KX4_SUPP |
2248 TXGBE_AUTOC_KR_SUPP);
2249 if (speed & TXGBE_LINK_SPEED_10GB_FULL) {
2250 if (orig_autoc & TXGBE_AUTOC_KX4_SUPP)
2251 autoc |= TXGBE_AUTOC_KX4_SUPP;
2252 if ((orig_autoc & TXGBE_AUTOC_KR_SUPP) &&
2253 !hw->phy.smart_speed_active)
2254 autoc |= TXGBE_AUTOC_KR_SUPP;
2256 if (speed & TXGBE_LINK_SPEED_1GB_FULL)
2257 autoc |= TXGBE_AUTOC_KX_SUPP;
2258 } else if ((pma_pmd_1g == TXGBE_AUTOC_1G_SFI) &&
2259 (link_mode == TXGBE_AUTOC_LMS_1G_LINK_NO_AN ||
2260 link_mode == TXGBE_AUTOC_LMS_1G_AN)) {
2261 /* Switch from 1G SFI to 10G SFI if requested */
2262 if (speed == TXGBE_LINK_SPEED_10GB_FULL &&
2263 pma_pmd_10gs == TXGBE_AUTOC_10GS_SFI) {
2264 autoc &= ~TXGBE_AUTOC_LMS_MASK;
2265 autoc |= TXGBE_AUTOC_LMS_10G;
2267 } else if ((pma_pmd_10gs == TXGBE_AUTOC_10GS_SFI) &&
2268 (link_mode == TXGBE_AUTOC_LMS_10G)) {
2269 /* Switch from 10G SFI to 1G SFI if requested */
2270 if (speed == TXGBE_LINK_SPEED_1GB_FULL &&
2271 pma_pmd_1g == TXGBE_AUTOC_1G_SFI) {
2272 autoc &= ~TXGBE_AUTOC_LMS_MASK;
2273 if (autoneg || hw->phy.type == txgbe_phy_qsfp_intel)
2274 autoc |= TXGBE_AUTOC_LMS_1G_AN;
2276 autoc |= TXGBE_AUTOC_LMS_1G_LINK_NO_AN;
2280 if (autoc == current_autoc)
2283 autoc &= ~TXGBE_AUTOC_SPEED_MASK;
2284 autoc |= TXGBE_AUTOC_SPEED(speed);
2285 autoc |= (autoneg ? TXGBE_AUTOC_AUTONEG : 0);
2288 hw->mac.autoc_write(hw, autoc);
2290 /* Only poll for autoneg to complete if specified to do so */
2291 if (autoneg_wait_to_complete) {
2292 if (link_mode == TXGBE_AUTOC_LMS_KX4_KX_KR ||
2293 link_mode == TXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
2294 link_mode == TXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
2295 links_reg = 0; /*Just in case Autoneg time=0*/
2296 for (i = 0; i < TXGBE_AUTO_NEG_TIME; i++) {
2297 links_reg = rd32(hw, TXGBE_PORTSTAT);
2298 if (links_reg & TXGBE_PORTSTAT_UP)
2302 if (!(links_reg & TXGBE_PORTSTAT_UP)) {
2303 status = TXGBE_ERR_AUTONEG_NOT_COMPLETE;
2304 DEBUGOUT("Autoneg did not complete.\n");
2309 /* Add delay to filter out noises during initial link setup */
2316 * txgbe_setup_copper_link_raptor - Set the PHY autoneg advertised field
2317 * @hw: pointer to hardware structure
2318 * @speed: new link speed
2319 * @autoneg_wait_to_complete: true if waiting is needed to complete
2321 * Restarts link on PHY and MAC based on settings passed in.
2323 static s32 txgbe_setup_copper_link_raptor(struct txgbe_hw *hw,
2325 bool autoneg_wait_to_complete)
2329 DEBUGFUNC("txgbe_setup_copper_link_raptor");
2331 /* Setup the PHY according to input speed */
2332 status = hw->phy.setup_link_speed(hw, speed,
2333 autoneg_wait_to_complete);
2335 txgbe_start_mac_link_raptor(hw, autoneg_wait_to_complete);
2341 txgbe_check_flash_load(struct txgbe_hw *hw, u32 check_bit)
2346 /* if there's flash existing */
2347 if (!(rd32(hw, TXGBE_SPISTAT) & TXGBE_SPISTAT_BPFLASH)) {
2348 /* wait hw load flash done */
2349 for (i = 0; i < 10; i++) {
2350 reg = rd32(hw, TXGBE_ILDRSTAT);
2351 if (!(reg & check_bit)) {
2358 err = TXGBE_ERR_FLASH_LOADING_FAILED;
2364 txgbe_reset_misc(struct txgbe_hw *hw)
2369 wr32(hw, TXGBE_ISBADDRL, hw->isb_dma & 0x00000000FFFFFFFF);
2370 wr32(hw, TXGBE_ISBADDRH, hw->isb_dma >> 32);
2372 value = rd32_epcs(hw, SR_XS_PCS_CTRL2);
2373 if ((value & 0x3) != SR_PCS_CTRL2_TYPE_SEL_X)
2374 hw->link_status = TXGBE_LINK_STATUS_NONE;
2376 /* receive packets that size > 2048 */
2377 wr32m(hw, TXGBE_MACRXCFG,
2378 TXGBE_MACRXCFG_JUMBO, TXGBE_MACRXCFG_JUMBO);
2380 wr32m(hw, TXGBE_FRMSZ, TXGBE_FRMSZ_MAX_MASK,
2381 TXGBE_FRMSZ_MAX(TXGBE_FRAME_SIZE_DFT));
2383 /* clear counters on read */
2384 wr32m(hw, TXGBE_MACCNTCTL,
2385 TXGBE_MACCNTCTL_RC, TXGBE_MACCNTCTL_RC);
2387 wr32m(hw, TXGBE_RXFCCFG,
2388 TXGBE_RXFCCFG_FC, TXGBE_RXFCCFG_FC);
2389 wr32m(hw, TXGBE_TXFCCFG,
2390 TXGBE_TXFCCFG_FC, TXGBE_TXFCCFG_FC);
2392 wr32m(hw, TXGBE_MACRXFLT,
2393 TXGBE_MACRXFLT_PROMISC, TXGBE_MACRXFLT_PROMISC);
2395 wr32m(hw, TXGBE_RSTSTAT,
2396 TXGBE_RSTSTAT_TMRINIT_MASK, TXGBE_RSTSTAT_TMRINIT(30));
2398 /* errata 4: initialize mng flex tbl and wakeup flex tbl*/
2399 wr32(hw, TXGBE_MNGFLEXSEL, 0);
2400 for (i = 0; i < 16; i++) {
2401 wr32(hw, TXGBE_MNGFLEXDWL(i), 0);
2402 wr32(hw, TXGBE_MNGFLEXDWH(i), 0);
2403 wr32(hw, TXGBE_MNGFLEXMSK(i), 0);
2405 wr32(hw, TXGBE_LANFLEXSEL, 0);
2406 for (i = 0; i < 16; i++) {
2407 wr32(hw, TXGBE_LANFLEXDWL(i), 0);
2408 wr32(hw, TXGBE_LANFLEXDWH(i), 0);
2409 wr32(hw, TXGBE_LANFLEXMSK(i), 0);
2412 /* set pause frame dst mac addr */
2413 wr32(hw, TXGBE_RXPBPFCDMACL, 0xC2000001);
2414 wr32(hw, TXGBE_RXPBPFCDMACH, 0x0180);
2416 hw->mac.init_thermal_sensor_thresh(hw);
2418 /* enable mac transmitter */
2419 wr32m(hw, TXGBE_MACTXCFG, TXGBE_MACTXCFG_TXE, TXGBE_MACTXCFG_TXE);
2421 for (i = 0; i < 4; i++)
2422 wr32m(hw, TXGBE_IVAR(i), 0x80808080, 0);
2426 * txgbe_reset_hw - Perform hardware reset
2427 * @hw: pointer to hardware structure
2429 * Resets the hardware by resetting the transmit and receive units, masks
2430 * and clears all interrupts, perform a PHY reset, and perform a link (MAC)
2433 s32 txgbe_reset_hw(struct txgbe_hw *hw)
2438 DEBUGFUNC("txgbe_reset_hw");
2440 /* Call adapter stop to disable tx/rx and clear interrupts */
2441 status = hw->mac.stop_hw(hw);
2445 /* flush pending Tx transactions */
2446 txgbe_clear_tx_pending(hw);
2448 /* Identify PHY and related function pointers */
2449 status = hw->phy.init(hw);
2450 if (status == TXGBE_ERR_SFP_NOT_SUPPORTED)
2453 /* Setup SFP module if there is one present. */
2454 if (hw->phy.sfp_setup_needed) {
2455 status = hw->mac.setup_sfp(hw);
2456 hw->phy.sfp_setup_needed = false;
2458 if (status == TXGBE_ERR_SFP_NOT_SUPPORTED)
2462 if (!hw->phy.reset_disable)
2465 /* remember AUTOC from before we reset */
2466 autoc = hw->mac.autoc_read(hw);
2470 * Issue global reset to the MAC. Needs to be SW reset if link is up.
2471 * If link reset is used when link is up, it might reset the PHY when
2472 * mng is using it. If link is down or the flag to force full link
2473 * reset is set, then perform link reset.
2475 if (txgbe_mng_present(hw)) {
2476 txgbe_hic_reset(hw);
2478 wr32(hw, TXGBE_RST, TXGBE_RST_LAN(hw->bus.lan_id));
2483 txgbe_reset_misc(hw);
2485 if (hw->bus.lan_id == 0) {
2486 status = txgbe_check_flash_load(hw,
2487 TXGBE_ILDRSTAT_SWRST_LAN0);
2489 status = txgbe_check_flash_load(hw,
2490 TXGBE_ILDRSTAT_SWRST_LAN1);
2498 * Double resets are required for recovery from certain error
2499 * conditions. Between resets, it is necessary to stall to
2500 * allow time for any pending HW events to complete.
2502 if (hw->mac.flags & TXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
2503 hw->mac.flags &= ~TXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
2508 * Store the original AUTOC/AUTOC2 values if they have not been
2509 * stored off yet. Otherwise restore the stored original
2510 * values since the reset operation sets back to defaults.
2512 if (!hw->mac.orig_link_settings_stored) {
2513 hw->mac.orig_autoc = hw->mac.autoc_read(hw);
2514 hw->mac.autoc_write(hw, hw->mac.orig_autoc);
2515 hw->mac.orig_link_settings_stored = true;
2517 hw->mac.orig_autoc = autoc;
2520 /* Store the permanent mac address */
2521 hw->mac.get_mac_addr(hw, hw->mac.perm_addr);
2524 * Store MAC address from RAR0, clear receive address registers, and
2525 * clear the multicast table. Also reset num_rar_entries to 128,
2526 * since we modify this value when programming the SAN MAC address.
2528 hw->mac.num_rar_entries = 128;
2529 hw->mac.init_rx_addrs(hw);
2531 /* Store the permanent SAN mac address */
2532 hw->mac.get_san_mac_addr(hw, hw->mac.san_addr);
2534 /* Add the SAN MAC address to the RAR only if it's a valid address */
2535 if (txgbe_validate_mac_addr(hw->mac.san_addr) == 0) {
2536 /* Save the SAN MAC RAR index */
2537 hw->mac.san_mac_rar_index = hw->mac.num_rar_entries - 1;
2539 hw->mac.set_rar(hw, hw->mac.san_mac_rar_index,
2540 hw->mac.san_addr, 0, true);
2542 /* clear VMDq pool/queue selection for this RAR */
2543 hw->mac.clear_vmdq(hw, hw->mac.san_mac_rar_index,
2546 /* Reserve the last RAR for the SAN MAC address */
2547 hw->mac.num_rar_entries--;
2550 /* Store the alternative WWNN/WWPN prefix */
2551 hw->mac.get_wwn_prefix(hw, &hw->mac.wwnn_prefix,
2552 &hw->mac.wwpn_prefix);
2558 * txgbe_start_hw_raptor - Prepare hardware for Tx/Rx
2559 * @hw: pointer to hardware structure
2561 * Starts the hardware using the generic start_hw function
2562 * and the generation start_hw function.
2563 * Then performs revision-specific operations, if any.
2565 s32 txgbe_start_hw_raptor(struct txgbe_hw *hw)
2569 DEBUGFUNC("txgbe_start_hw_raptor");
2571 err = txgbe_start_hw(hw);
2575 err = txgbe_start_hw_gen2(hw);
2579 /* We need to run link autotry after the driver loads */
2580 hw->mac.autotry_restart = true;
2587 * txgbe_enable_rx_dma_raptor - Enable the Rx DMA unit
2588 * @hw: pointer to hardware structure
2589 * @regval: register value to write to RXCTRL
2591 * Enables the Rx DMA unit
2593 s32 txgbe_enable_rx_dma_raptor(struct txgbe_hw *hw, u32 regval)
2595 DEBUGFUNC("txgbe_enable_rx_dma_raptor");
2598 * Workaround silicon errata when enabling the Rx datapath.
2599 * If traffic is incoming before we enable the Rx unit, it could hang
2600 * the Rx DMA unit. Therefore, make sure the security engine is
2601 * completely disabled prior to enabling the Rx unit.
2604 hw->mac.disable_sec_rx_path(hw);
2606 if (regval & TXGBE_PBRXCTL_ENA)
2607 txgbe_enable_rx(hw);
2609 txgbe_disable_rx(hw);
2611 hw->mac.enable_sec_rx_path(hw);
2617 * txgbe_verify_lesm_fw_enabled_raptor - Checks LESM FW module state.
2618 * @hw: pointer to hardware structure
2620 * Returns true if the LESM FW module is present and enabled. Otherwise
2621 * returns false. Smart Speed must be disabled if LESM FW module is enabled.
2623 bool txgbe_verify_lesm_fw_enabled_raptor(struct txgbe_hw *hw)
2625 bool lesm_enabled = false;
2626 u16 fw_offset, fw_lesm_param_offset, fw_lesm_state;
2629 DEBUGFUNC("txgbe_verify_lesm_fw_enabled_raptor");
2631 /* get the offset to the Firmware Module block */
2632 status = hw->rom.read16(hw, TXGBE_FW_PTR, &fw_offset);
2634 if (status != 0 || fw_offset == 0 || fw_offset == 0xFFFF)
2637 /* get the offset to the LESM Parameters block */
2638 status = hw->rom.read16(hw, (fw_offset +
2639 TXGBE_FW_LESM_PARAMETERS_PTR),
2640 &fw_lesm_param_offset);
2643 fw_lesm_param_offset == 0 || fw_lesm_param_offset == 0xFFFF)
2646 /* get the LESM state word */
2647 status = hw->rom.read16(hw, (fw_lesm_param_offset +
2648 TXGBE_FW_LESM_STATE_1),
2651 if (status == 0 && (fw_lesm_state & TXGBE_FW_LESM_STATE_ENABLED))
2652 lesm_enabled = true;
2655 lesm_enabled = false;
2656 return lesm_enabled;
2660 * txgbe_reset_pipeline_raptor - perform pipeline reset
2662 * @hw: pointer to hardware structure
2664 * Reset pipeline by asserting Restart_AN together with LMS change to ensure
2665 * full pipeline reset. This function assumes the SW/FW lock is held.
2667 s32 txgbe_reset_pipeline_raptor(struct txgbe_hw *hw)
2672 autoc = hw->mac.autoc_read(hw);
2674 /* Enable link if disabled in NVM */
2675 if (autoc & TXGBE_AUTOC_LINK_DIA_MASK)
2676 autoc &= ~TXGBE_AUTOC_LINK_DIA_MASK;
2678 autoc |= TXGBE_AUTOC_AN_RESTART;
2679 /* Write AUTOC register with toggled LMS[2] bit and Restart_AN */
2680 hw->mac.autoc_write(hw, autoc ^ TXGBE_AUTOC_LMS_AN);
2682 /* Write AUTOC register with original LMS field and Restart_AN */
2683 hw->mac.autoc_write(hw, autoc);