1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2015-2020
5 #include "txgbe_type.h"
10 #include "txgbe_eeprom.h"
11 #include "txgbe_mng.h"
14 #define TXGBE_RAPTOR_MAX_TX_QUEUES 128
15 #define TXGBE_RAPTOR_MAX_RX_QUEUES 128
16 #define TXGBE_RAPTOR_RAR_ENTRIES 128
17 #define TXGBE_RAPTOR_MC_TBL_SIZE 128
18 #define TXGBE_RAPTOR_VFT_TBL_SIZE 128
19 #define TXGBE_RAPTOR_RX_PB_SIZE 512 /*KB*/
21 static s32 txgbe_setup_copper_link_raptor(struct txgbe_hw *hw,
23 bool autoneg_wait_to_complete);
25 static s32 txgbe_mta_vector(struct txgbe_hw *hw, u8 *mc_addr);
26 static s32 txgbe_get_san_mac_addr_offset(struct txgbe_hw *hw,
30 * txgbe_device_supports_autoneg_fc - Check if device supports autonegotiation
32 * @hw: pointer to hardware structure
34 * This function returns true if the device supports flow control
35 * autonegotiation, and false if it does not.
38 bool txgbe_device_supports_autoneg_fc(struct txgbe_hw *hw)
40 bool supported = false;
44 DEBUGFUNC("txgbe_device_supports_autoneg_fc");
46 switch (hw->phy.media_type) {
47 case txgbe_media_type_fiber_qsfp:
48 case txgbe_media_type_fiber:
49 hw->mac.check_link(hw, &speed, &link_up, false);
50 /* if link is down, assume supported */
52 supported = speed == TXGBE_LINK_SPEED_1GB_FULL ?
58 case txgbe_media_type_backplane:
61 case txgbe_media_type_copper:
62 /* only some copper devices support flow control autoneg */
63 switch (hw->subsystem_device_id & 0xFF) {
64 case TXGBE_DEV_ID_XAUI:
65 case TXGBE_DEV_ID_SGMII:
76 DEBUGOUT("Device %x does not support flow control autoneg",
82 * txgbe_setup_fc - Set up flow control
83 * @hw: pointer to hardware structure
85 * Called at init time to set up flow control.
87 s32 txgbe_setup_fc(struct txgbe_hw *hw)
96 DEBUGFUNC("txgbe_setup_fc");
98 /* Validate the requested mode */
99 if (hw->fc.strict_ieee && hw->fc.requested_mode == txgbe_fc_rx_pause) {
100 DEBUGOUT("txgbe_fc_rx_pause not valid in strict IEEE mode\n");
101 err = TXGBE_ERR_INVALID_LINK_SETTINGS;
106 * 10gig parts do not have a word in the EEPROM to determine the
107 * default flow control setting, so we explicitly set it to full.
109 if (hw->fc.requested_mode == txgbe_fc_default)
110 hw->fc.requested_mode = txgbe_fc_full;
113 * Set up the 1G and 10G flow control advertisement registers so the
114 * HW will be able to do fc autoneg once the cable is plugged in. If
115 * we link at 10G, the 1G advertisement is harmless and vice versa.
117 switch (hw->phy.media_type) {
118 case txgbe_media_type_backplane:
119 /* some MAC's need RMW protection on AUTOC */
120 err = hw->mac.prot_autoc_read(hw, &locked, ®_bp);
124 /* fall through - only backplane uses autoc */
125 case txgbe_media_type_fiber_qsfp:
126 case txgbe_media_type_fiber:
127 case txgbe_media_type_copper:
128 hw->phy.read_reg(hw, TXGBE_MD_AUTO_NEG_ADVT,
129 TXGBE_MD_DEV_AUTO_NEG, ®_cu);
136 * The possible values of fc.requested_mode are:
137 * 0: Flow control is completely disabled
138 * 1: Rx flow control is enabled (we can receive pause frames,
139 * but not send pause frames).
140 * 2: Tx flow control is enabled (we can send pause frames but
141 * we do not support receiving pause frames).
142 * 3: Both Rx and Tx flow control (symmetric) are enabled.
145 switch (hw->fc.requested_mode) {
147 /* Flow control completely disabled by software override. */
148 reg &= ~(SR_MII_MMD_AN_ADV_PAUSE_SYM |
149 SR_MII_MMD_AN_ADV_PAUSE_ASM);
150 if (hw->phy.media_type == txgbe_media_type_backplane)
151 reg_bp &= ~(TXGBE_AUTOC_SYM_PAUSE |
152 TXGBE_AUTOC_ASM_PAUSE);
153 else if (hw->phy.media_type == txgbe_media_type_copper)
154 reg_cu &= ~(TXGBE_TAF_SYM_PAUSE | TXGBE_TAF_ASM_PAUSE);
156 case txgbe_fc_tx_pause:
158 * Tx Flow control is enabled, and Rx Flow control is
159 * disabled by software override.
161 reg |= SR_MII_MMD_AN_ADV_PAUSE_ASM;
162 reg &= ~SR_MII_MMD_AN_ADV_PAUSE_SYM;
163 if (hw->phy.media_type == txgbe_media_type_backplane) {
164 reg_bp |= TXGBE_AUTOC_ASM_PAUSE;
165 reg_bp &= ~TXGBE_AUTOC_SYM_PAUSE;
166 } else if (hw->phy.media_type == txgbe_media_type_copper) {
167 reg_cu |= TXGBE_TAF_ASM_PAUSE;
168 reg_cu &= ~TXGBE_TAF_SYM_PAUSE;
170 reg |= SR_MII_MMD_AN_ADV_PAUSE_ASM;
171 reg_bp |= SR_AN_MMD_ADV_REG1_PAUSE_ASM;
173 case txgbe_fc_rx_pause:
175 * Rx Flow control is enabled and Tx Flow control is
176 * disabled by software override. Since there really
177 * isn't a way to advertise that we are capable of RX
178 * Pause ONLY, we will advertise that we support both
179 * symmetric and asymmetric Rx PAUSE, as such we fall
180 * through to the fc_full statement. Later, we will
181 * disable the adapter's ability to send PAUSE frames.
184 /* Flow control (both Rx and Tx) is enabled by SW override. */
185 reg |= SR_MII_MMD_AN_ADV_PAUSE_SYM |
186 SR_MII_MMD_AN_ADV_PAUSE_ASM;
187 if (hw->phy.media_type == txgbe_media_type_backplane)
188 reg_bp |= TXGBE_AUTOC_SYM_PAUSE |
189 TXGBE_AUTOC_ASM_PAUSE;
190 else if (hw->phy.media_type == txgbe_media_type_copper)
191 reg_cu |= TXGBE_TAF_SYM_PAUSE | TXGBE_TAF_ASM_PAUSE;
192 reg |= SR_MII_MMD_AN_ADV_PAUSE_SYM |
193 SR_MII_MMD_AN_ADV_PAUSE_ASM;
194 reg_bp |= SR_AN_MMD_ADV_REG1_PAUSE_SYM |
195 SR_AN_MMD_ADV_REG1_PAUSE_ASM;
198 DEBUGOUT("Flow control param set incorrectly\n");
199 err = TXGBE_ERR_CONFIG;
204 * Enable auto-negotiation between the MAC & PHY;
205 * the MAC will advertise clause 37 flow control.
207 value = rd32_epcs(hw, SR_MII_MMD_AN_ADV);
208 value = (value & ~(SR_MII_MMD_AN_ADV_PAUSE_ASM |
209 SR_MII_MMD_AN_ADV_PAUSE_SYM)) | reg;
210 wr32_epcs(hw, SR_MII_MMD_AN_ADV, value);
213 * AUTOC restart handles negotiation of 1G and 10G on backplane
214 * and copper. There is no need to set the PCS1GCTL register.
217 if (hw->phy.media_type == txgbe_media_type_backplane) {
218 value = rd32_epcs(hw, SR_AN_MMD_ADV_REG1);
219 value = (value & ~(SR_AN_MMD_ADV_REG1_PAUSE_ASM |
220 SR_AN_MMD_ADV_REG1_PAUSE_SYM)) |
222 wr32_epcs(hw, SR_AN_MMD_ADV_REG1, value);
223 } else if ((hw->phy.media_type == txgbe_media_type_copper) &&
224 (txgbe_device_supports_autoneg_fc(hw))) {
225 hw->phy.write_reg(hw, TXGBE_MD_AUTO_NEG_ADVT,
226 TXGBE_MD_DEV_AUTO_NEG, reg_cu);
229 DEBUGOUT("Set up FC; reg = 0x%08X\n", reg);
235 * txgbe_start_hw - Prepare hardware for Tx/Rx
236 * @hw: pointer to hardware structure
238 * Starts the hardware by filling the bus info structure and media type, clears
239 * all on chip counters, initializes receive address registers, multicast
240 * table, VLAN filter table, calls routine to set up link and flow control
241 * settings, and leaves transmit and receive units disabled and uninitialized
243 s32 txgbe_start_hw(struct txgbe_hw *hw)
248 DEBUGFUNC("txgbe_start_hw");
250 /* Set the media type */
251 hw->phy.media_type = hw->phy.get_media_type(hw);
253 /* Clear the VLAN filter table */
254 hw->mac.clear_vfta(hw);
256 /* Clear statistics registers */
257 hw->mac.clear_hw_cntrs(hw);
259 /* Setup flow control */
260 err = txgbe_setup_fc(hw);
261 if (err != 0 && err != TXGBE_NOT_IMPLEMENTED) {
262 DEBUGOUT("Flow control setup failed, returning %d\n", err);
266 /* Cache bit indicating need for crosstalk fix */
267 switch (hw->mac.type) {
268 case txgbe_mac_raptor:
269 hw->mac.get_device_caps(hw, &device_caps);
270 if (device_caps & TXGBE_DEVICE_CAPS_NO_CROSSTALK_WR)
271 hw->need_crosstalk_fix = false;
273 hw->need_crosstalk_fix = true;
276 hw->need_crosstalk_fix = false;
280 /* Clear adapter stopped flag */
281 hw->adapter_stopped = false;
287 * txgbe_start_hw_gen2 - Init sequence for common device family
288 * @hw: pointer to hw structure
290 * Performs the init sequence common to the second generation
293 s32 txgbe_start_hw_gen2(struct txgbe_hw *hw)
297 /* Clear the rate limiters */
298 for (i = 0; i < hw->mac.max_tx_queues; i++) {
299 wr32(hw, TXGBE_ARBPOOLIDX, i);
300 wr32(hw, TXGBE_ARBTXRATE, 0);
304 /* We need to run link autotry after the driver loads */
305 hw->mac.autotry_restart = true;
311 * txgbe_init_hw - Generic hardware initialization
312 * @hw: pointer to hardware structure
314 * Initialize the hardware by resetting the hardware, filling the bus info
315 * structure and media type, clears all on chip counters, initializes receive
316 * address registers, multicast table, VLAN filter table, calls routine to set
317 * up link and flow control settings, and leaves transmit and receive units
318 * disabled and uninitialized
320 s32 txgbe_init_hw(struct txgbe_hw *hw)
324 DEBUGFUNC("txgbe_init_hw");
326 /* Get firmware version */
327 hw->phy.get_fw_version(hw, &hw->fw_version);
329 /* Reset the hardware */
330 status = hw->mac.reset_hw(hw);
331 if (status == 0 || status == TXGBE_ERR_SFP_NOT_PRESENT) {
333 status = hw->mac.start_hw(hw);
337 DEBUGOUT("Failed to initialize HW, STATUS = %d\n", status);
343 * txgbe_clear_hw_cntrs - Generic clear hardware counters
344 * @hw: pointer to hardware structure
346 * Clears all hardware statistics counters by reading them from the hardware
347 * Statistics counters are clear on read.
349 s32 txgbe_clear_hw_cntrs(struct txgbe_hw *hw)
353 DEBUGFUNC("txgbe_clear_hw_cntrs");
356 /* don't write clear queue stats */
357 for (i = 0; i < TXGBE_MAX_QP; i++) {
358 hw->qp_last[i].rx_qp_packets = 0;
359 hw->qp_last[i].tx_qp_packets = 0;
360 hw->qp_last[i].rx_qp_bytes = 0;
361 hw->qp_last[i].tx_qp_bytes = 0;
362 hw->qp_last[i].rx_qp_mc_packets = 0;
366 for (i = 0; i < TXGBE_MAX_UP; i++) {
367 rd32(hw, TXGBE_PBRXUPXON(i));
368 rd32(hw, TXGBE_PBRXUPXOFF(i));
369 rd32(hw, TXGBE_PBTXUPXON(i));
370 rd32(hw, TXGBE_PBTXUPXOFF(i));
371 rd32(hw, TXGBE_PBTXUPOFF(i));
373 rd32(hw, TXGBE_PBRXMISS(i));
375 rd32(hw, TXGBE_PBRXLNKXON);
376 rd32(hw, TXGBE_PBRXLNKXOFF);
377 rd32(hw, TXGBE_PBTXLNKXON);
378 rd32(hw, TXGBE_PBTXLNKXOFF);
381 rd32(hw, TXGBE_DMARXPKT);
382 rd32(hw, TXGBE_DMATXPKT);
384 rd64(hw, TXGBE_DMARXOCTL);
385 rd64(hw, TXGBE_DMATXOCTL);
388 rd64(hw, TXGBE_MACRXERRCRCL);
389 rd64(hw, TXGBE_MACRXMPKTL);
390 rd64(hw, TXGBE_MACTXMPKTL);
392 rd64(hw, TXGBE_MACRXPKTL);
393 rd64(hw, TXGBE_MACTXPKTL);
394 rd64(hw, TXGBE_MACRXGBOCTL);
396 rd64(hw, TXGBE_MACRXOCTL);
397 rd32(hw, TXGBE_MACTXOCTL);
399 rd64(hw, TXGBE_MACRX1TO64L);
400 rd64(hw, TXGBE_MACRX65TO127L);
401 rd64(hw, TXGBE_MACRX128TO255L);
402 rd64(hw, TXGBE_MACRX256TO511L);
403 rd64(hw, TXGBE_MACRX512TO1023L);
404 rd64(hw, TXGBE_MACRX1024TOMAXL);
405 rd64(hw, TXGBE_MACTX1TO64L);
406 rd64(hw, TXGBE_MACTX65TO127L);
407 rd64(hw, TXGBE_MACTX128TO255L);
408 rd64(hw, TXGBE_MACTX256TO511L);
409 rd64(hw, TXGBE_MACTX512TO1023L);
410 rd64(hw, TXGBE_MACTX1024TOMAXL);
412 rd64(hw, TXGBE_MACRXERRLENL);
413 rd32(hw, TXGBE_MACRXOVERSIZE);
414 rd32(hw, TXGBE_MACRXJABBER);
417 rd32(hw, TXGBE_FCOECRC);
418 rd32(hw, TXGBE_FCOELAST);
419 rd32(hw, TXGBE_FCOERPDC);
420 rd32(hw, TXGBE_FCOEPRC);
421 rd32(hw, TXGBE_FCOEPTC);
422 rd32(hw, TXGBE_FCOEDWRC);
423 rd32(hw, TXGBE_FCOEDWTC);
425 /* Flow Director Stats */
426 rd32(hw, TXGBE_FDIRMATCH);
427 rd32(hw, TXGBE_FDIRMISS);
428 rd32(hw, TXGBE_FDIRUSED);
429 rd32(hw, TXGBE_FDIRUSED);
430 rd32(hw, TXGBE_FDIRFAIL);
431 rd32(hw, TXGBE_FDIRFAIL);
434 rd32(hw, TXGBE_LSECTX_UTPKT);
435 rd32(hw, TXGBE_LSECTX_ENCPKT);
436 rd32(hw, TXGBE_LSECTX_PROTPKT);
437 rd32(hw, TXGBE_LSECTX_ENCOCT);
438 rd32(hw, TXGBE_LSECTX_PROTOCT);
439 rd32(hw, TXGBE_LSECRX_UTPKT);
440 rd32(hw, TXGBE_LSECRX_BTPKT);
441 rd32(hw, TXGBE_LSECRX_NOSCIPKT);
442 rd32(hw, TXGBE_LSECRX_UNSCIPKT);
443 rd32(hw, TXGBE_LSECRX_DECOCT);
444 rd32(hw, TXGBE_LSECRX_VLDOCT);
445 rd32(hw, TXGBE_LSECRX_UNCHKPKT);
446 rd32(hw, TXGBE_LSECRX_DLYPKT);
447 rd32(hw, TXGBE_LSECRX_LATEPKT);
448 for (i = 0; i < 2; i++) {
449 rd32(hw, TXGBE_LSECRX_OKPKT(i));
450 rd32(hw, TXGBE_LSECRX_INVPKT(i));
451 rd32(hw, TXGBE_LSECRX_BADPKT(i));
453 rd32(hw, TXGBE_LSECRX_INVSAPKT);
454 rd32(hw, TXGBE_LSECRX_BADSAPKT);
460 * txgbe_get_mac_addr - Generic get MAC address
461 * @hw: pointer to hardware structure
462 * @mac_addr: Adapter MAC address
464 * Reads the adapter's MAC address from first Receive Address Register (RAR0)
465 * A reset of the adapter must be performed prior to calling this function
466 * in order for the MAC address to have been loaded from the EEPROM into RAR0
468 s32 txgbe_get_mac_addr(struct txgbe_hw *hw, u8 *mac_addr)
474 DEBUGFUNC("txgbe_get_mac_addr");
476 wr32(hw, TXGBE_ETHADDRIDX, 0);
477 rar_high = rd32(hw, TXGBE_ETHADDRH);
478 rar_low = rd32(hw, TXGBE_ETHADDRL);
480 for (i = 0; i < 2; i++)
481 mac_addr[i] = (u8)(rar_high >> (1 - i) * 8);
483 for (i = 0; i < 4; i++)
484 mac_addr[i + 2] = (u8)(rar_low >> (3 - i) * 8);
490 * txgbe_set_lan_id_multi_port - Set LAN id for PCIe multiple port devices
491 * @hw: pointer to the HW structure
493 * Determines the LAN function id by reading memory-mapped registers and swaps
494 * the port value if requested, and set MAC instance for devices.
496 void txgbe_set_lan_id_multi_port(struct txgbe_hw *hw)
498 struct txgbe_bus_info *bus = &hw->bus;
501 DEBUGFUNC("txgbe_set_lan_id_multi_port_pcie");
503 reg = rd32(hw, TXGBE_PORTSTAT);
504 bus->lan_id = TXGBE_PORTSTAT_ID(reg);
506 /* check for single port */
507 reg = rd32(hw, TXGBE_PWR);
508 if (TXGBE_PWR_LANID(reg) == TXGBE_PWR_LANID_SWAP)
511 bus->func = bus->lan_id;
515 * txgbe_stop_hw - Generic stop Tx/Rx units
516 * @hw: pointer to hardware structure
518 * Sets the adapter_stopped flag within txgbe_hw struct. Clears interrupts,
519 * disables transmit and receive units. The adapter_stopped flag is used by
520 * the shared code and drivers to determine if the adapter is in a stopped
521 * state and should not touch the hardware.
523 s32 txgbe_stop_hw(struct txgbe_hw *hw)
528 DEBUGFUNC("txgbe_stop_hw");
531 * Set the adapter_stopped flag so other driver functions stop touching
534 hw->adapter_stopped = true;
536 /* Disable the receive unit */
537 txgbe_disable_rx(hw);
539 /* Clear interrupt mask to stop interrupts from being generated */
540 wr32(hw, TXGBE_IENMISC, 0);
541 wr32(hw, TXGBE_IMS(0), TXGBE_IMS_MASK);
542 wr32(hw, TXGBE_IMS(1), TXGBE_IMS_MASK);
544 /* Clear any pending interrupts, flush previous writes */
545 wr32(hw, TXGBE_ICRMISC, TXGBE_ICRMISC_MASK);
546 wr32(hw, TXGBE_ICR(0), TXGBE_ICR_MASK);
547 wr32(hw, TXGBE_ICR(1), TXGBE_ICR_MASK);
549 /* Disable the transmit unit. Each queue must be disabled. */
550 for (i = 0; i < hw->mac.max_tx_queues; i++)
551 wr32(hw, TXGBE_TXCFG(i), TXGBE_TXCFG_FLUSH);
553 /* Disable the receive unit by stopping each queue */
554 for (i = 0; i < hw->mac.max_rx_queues; i++) {
555 reg_val = rd32(hw, TXGBE_RXCFG(i));
556 reg_val &= ~TXGBE_RXCFG_ENA;
557 wr32(hw, TXGBE_RXCFG(i), reg_val);
560 /* flush all queues disables */
568 * txgbe_led_on - Turns on the software controllable LEDs.
569 * @hw: pointer to hardware structure
570 * @index: led number to turn on
572 s32 txgbe_led_on(struct txgbe_hw *hw, u32 index)
574 u32 led_reg = rd32(hw, TXGBE_LEDCTL);
576 DEBUGFUNC("txgbe_led_on");
579 return TXGBE_ERR_PARAM;
581 /* To turn on the LED, set mode to ON. */
582 led_reg |= TXGBE_LEDCTL_SEL(index);
583 led_reg |= TXGBE_LEDCTL_ORD(index);
584 wr32(hw, TXGBE_LEDCTL, led_reg);
591 * txgbe_led_off - Turns off the software controllable LEDs.
592 * @hw: pointer to hardware structure
593 * @index: led number to turn off
595 s32 txgbe_led_off(struct txgbe_hw *hw, u32 index)
597 u32 led_reg = rd32(hw, TXGBE_LEDCTL);
599 DEBUGFUNC("txgbe_led_off");
602 return TXGBE_ERR_PARAM;
604 /* To turn off the LED, set mode to OFF. */
605 led_reg &= ~(TXGBE_LEDCTL_SEL(index));
606 led_reg &= ~(TXGBE_LEDCTL_ORD(index));
607 wr32(hw, TXGBE_LEDCTL, led_reg);
614 * txgbe_validate_mac_addr - Validate MAC address
615 * @mac_addr: pointer to MAC address.
617 * Tests a MAC address to ensure it is a valid Individual Address.
619 s32 txgbe_validate_mac_addr(u8 *mac_addr)
623 DEBUGFUNC("txgbe_validate_mac_addr");
625 /* Make sure it is not a multicast address */
626 if (TXGBE_IS_MULTICAST(mac_addr)) {
627 status = TXGBE_ERR_INVALID_MAC_ADDR;
628 /* Not a broadcast address */
629 } else if (TXGBE_IS_BROADCAST(mac_addr)) {
630 status = TXGBE_ERR_INVALID_MAC_ADDR;
631 /* Reject the zero address */
632 } else if (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 &&
633 mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0) {
634 status = TXGBE_ERR_INVALID_MAC_ADDR;
640 * txgbe_set_rar - Set Rx address register
641 * @hw: pointer to hardware structure
642 * @index: Receive address register to write
643 * @addr: Address to put into receive address register
644 * @vmdq: VMDq "set" or "pool" index
645 * @enable_addr: set flag that address is active
647 * Puts an ethernet address into a receive address register.
649 s32 txgbe_set_rar(struct txgbe_hw *hw, u32 index, u8 *addr, u32 vmdq,
652 u32 rar_low, rar_high;
653 u32 rar_entries = hw->mac.num_rar_entries;
655 DEBUGFUNC("txgbe_set_rar");
657 /* Make sure we are using a valid rar index range */
658 if (index >= rar_entries) {
659 DEBUGOUT("RAR index %d is out of range.\n", index);
660 return TXGBE_ERR_INVALID_ARGUMENT;
663 /* setup VMDq pool selection before this RAR gets enabled */
664 hw->mac.set_vmdq(hw, index, vmdq);
667 * HW expects these in little endian so we reverse the byte
668 * order from network order (big endian) to little endian
670 rar_low = TXGBE_ETHADDRL_AD0(addr[5]) |
671 TXGBE_ETHADDRL_AD1(addr[4]) |
672 TXGBE_ETHADDRL_AD2(addr[3]) |
673 TXGBE_ETHADDRL_AD3(addr[2]);
675 * Some parts put the VMDq setting in the extra RAH bits,
676 * so save everything except the lower 16 bits that hold part
677 * of the address and the address valid bit.
679 rar_high = rd32(hw, TXGBE_ETHADDRH);
680 rar_high &= ~TXGBE_ETHADDRH_AD_MASK;
681 rar_high |= (TXGBE_ETHADDRH_AD4(addr[1]) |
682 TXGBE_ETHADDRH_AD5(addr[0]));
684 rar_high &= ~TXGBE_ETHADDRH_VLD;
685 if (enable_addr != 0)
686 rar_high |= TXGBE_ETHADDRH_VLD;
688 wr32(hw, TXGBE_ETHADDRIDX, index);
689 wr32(hw, TXGBE_ETHADDRL, rar_low);
690 wr32(hw, TXGBE_ETHADDRH, rar_high);
696 * txgbe_clear_rar - Remove Rx address register
697 * @hw: pointer to hardware structure
698 * @index: Receive address register to write
700 * Clears an ethernet address from a receive address register.
702 s32 txgbe_clear_rar(struct txgbe_hw *hw, u32 index)
705 u32 rar_entries = hw->mac.num_rar_entries;
707 DEBUGFUNC("txgbe_clear_rar");
709 /* Make sure we are using a valid rar index range */
710 if (index >= rar_entries) {
711 DEBUGOUT("RAR index %d is out of range.\n", index);
712 return TXGBE_ERR_INVALID_ARGUMENT;
716 * Some parts put the VMDq setting in the extra RAH bits,
717 * so save everything except the lower 16 bits that hold part
718 * of the address and the address valid bit.
720 wr32(hw, TXGBE_ETHADDRIDX, index);
721 rar_high = rd32(hw, TXGBE_ETHADDRH);
722 rar_high &= ~(TXGBE_ETHADDRH_AD_MASK | TXGBE_ETHADDRH_VLD);
724 wr32(hw, TXGBE_ETHADDRL, 0);
725 wr32(hw, TXGBE_ETHADDRH, rar_high);
727 /* clear VMDq pool/queue selection for this RAR */
728 hw->mac.clear_vmdq(hw, index, BIT_MASK32);
734 * txgbe_init_rx_addrs - Initializes receive address filters.
735 * @hw: pointer to hardware structure
737 * Places the MAC address in receive address register 0 and clears the rest
738 * of the receive address registers. Clears the multicast table. Assumes
739 * the receiver is in reset when the routine is called.
741 s32 txgbe_init_rx_addrs(struct txgbe_hw *hw)
745 u32 rar_entries = hw->mac.num_rar_entries;
747 DEBUGFUNC("txgbe_init_rx_addrs");
750 * If the current mac address is valid, assume it is a software override
751 * to the permanent address.
752 * Otherwise, use the permanent address from the eeprom.
754 if (txgbe_validate_mac_addr(hw->mac.addr) ==
755 TXGBE_ERR_INVALID_MAC_ADDR) {
756 /* Get the MAC address from the RAR0 for later reference */
757 hw->mac.get_mac_addr(hw, hw->mac.addr);
759 DEBUGOUT(" Keeping Current RAR0 Addr =%.2X %.2X %.2X ",
760 hw->mac.addr[0], hw->mac.addr[1],
762 DEBUGOUT("%.2X %.2X %.2X\n", hw->mac.addr[3],
763 hw->mac.addr[4], hw->mac.addr[5]);
765 /* Setup the receive address. */
766 DEBUGOUT("Overriding MAC Address in RAR[0]\n");
767 DEBUGOUT(" New MAC Addr =%.2X %.2X %.2X ",
768 hw->mac.addr[0], hw->mac.addr[1],
770 DEBUGOUT("%.2X %.2X %.2X\n", hw->mac.addr[3],
771 hw->mac.addr[4], hw->mac.addr[5]);
773 hw->mac.set_rar(hw, 0, hw->mac.addr, 0, true);
776 /* clear VMDq pool/queue selection for RAR 0 */
777 hw->mac.clear_vmdq(hw, 0, BIT_MASK32);
779 hw->addr_ctrl.overflow_promisc = 0;
781 hw->addr_ctrl.rar_used_count = 1;
783 /* Zero out the other receive addresses. */
784 DEBUGOUT("Clearing RAR[1-%d]\n", rar_entries - 1);
785 for (i = 1; i < rar_entries; i++) {
786 wr32(hw, TXGBE_ETHADDRIDX, i);
787 wr32(hw, TXGBE_ETHADDRL, 0);
788 wr32(hw, TXGBE_ETHADDRH, 0);
792 hw->addr_ctrl.mta_in_use = 0;
793 psrctl = rd32(hw, TXGBE_PSRCTL);
794 psrctl &= ~(TXGBE_PSRCTL_ADHF12_MASK | TXGBE_PSRCTL_MCHFENA);
795 psrctl |= TXGBE_PSRCTL_ADHF12(hw->mac.mc_filter_type);
796 wr32(hw, TXGBE_PSRCTL, psrctl);
798 DEBUGOUT(" Clearing MTA\n");
799 for (i = 0; i < hw->mac.mcft_size; i++)
800 wr32(hw, TXGBE_MCADDRTBL(i), 0);
802 txgbe_init_uta_tables(hw);
808 * txgbe_mta_vector - Determines bit-vector in multicast table to set
809 * @hw: pointer to hardware structure
810 * @mc_addr: the multicast address
812 * Extracts the 12 bits, from a multicast address, to determine which
813 * bit-vector to set in the multicast table. The hardware uses 12 bits, from
814 * incoming rx multicast addresses, to determine the bit-vector to check in
815 * the MTA. Which of the 4 combination, of 12-bits, the hardware uses is set
816 * by the MO field of the PSRCTRL. The MO field is set during initialization
819 static s32 txgbe_mta_vector(struct txgbe_hw *hw, u8 *mc_addr)
823 DEBUGFUNC("txgbe_mta_vector");
825 switch (hw->mac.mc_filter_type) {
826 case 0: /* use bits [47:36] of the address */
827 vector = ((mc_addr[4] >> 4) | (((u16)mc_addr[5]) << 4));
829 case 1: /* use bits [46:35] of the address */
830 vector = ((mc_addr[4] >> 3) | (((u16)mc_addr[5]) << 5));
832 case 2: /* use bits [45:34] of the address */
833 vector = ((mc_addr[4] >> 2) | (((u16)mc_addr[5]) << 6));
835 case 3: /* use bits [43:32] of the address */
836 vector = ((mc_addr[4]) | (((u16)mc_addr[5]) << 8));
838 default: /* Invalid mc_filter_type */
839 DEBUGOUT("MC filter type param set incorrectly\n");
844 /* vector can only be 12-bits or boundary will be exceeded */
850 * txgbe_set_mta - Set bit-vector in multicast table
851 * @hw: pointer to hardware structure
852 * @mc_addr: Multicast address
854 * Sets the bit-vector in the multicast table.
856 void txgbe_set_mta(struct txgbe_hw *hw, u8 *mc_addr)
862 DEBUGFUNC("txgbe_set_mta");
864 hw->addr_ctrl.mta_in_use++;
866 vector = txgbe_mta_vector(hw, mc_addr);
867 DEBUGOUT(" bit-vector = 0x%03X\n", vector);
870 * The MTA is a register array of 128 32-bit registers. It is treated
871 * like an array of 4096 bits. We want to set bit
872 * BitArray[vector_value]. So we figure out what register the bit is
873 * in, read it, OR in the new bit, then write back the new value. The
874 * register is determined by the upper 7 bits of the vector value and
875 * the bit within that register are determined by the lower 5 bits of
878 vector_reg = (vector >> 5) & 0x7F;
879 vector_bit = vector & 0x1F;
880 hw->mac.mta_shadow[vector_reg] |= (1 << vector_bit);
884 * txgbe_update_mc_addr_list - Updates MAC list of multicast addresses
885 * @hw: pointer to hardware structure
886 * @mc_addr_list: the list of new multicast addresses
887 * @mc_addr_count: number of addresses
888 * @next: iterator function to walk the multicast address list
889 * @clear: flag, when set clears the table beforehand
891 * When the clear flag is set, the given list replaces any existing list.
892 * Hashes the given addresses into the multicast table.
894 s32 txgbe_update_mc_addr_list(struct txgbe_hw *hw, u8 *mc_addr_list,
895 u32 mc_addr_count, txgbe_mc_addr_itr next,
901 DEBUGFUNC("txgbe_update_mc_addr_list");
904 * Set the new number of MC addresses that we are being requested to
907 hw->addr_ctrl.num_mc_addrs = mc_addr_count;
908 hw->addr_ctrl.mta_in_use = 0;
910 /* Clear mta_shadow */
912 DEBUGOUT(" Clearing MTA\n");
913 memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow));
916 /* Update mta_shadow */
917 for (i = 0; i < mc_addr_count; i++) {
918 DEBUGOUT(" Adding the multicast addresses:\n");
919 txgbe_set_mta(hw, next(hw, &mc_addr_list, &vmdq));
923 for (i = 0; i < hw->mac.mcft_size; i++)
924 wr32a(hw, TXGBE_MCADDRTBL(0), i,
925 hw->mac.mta_shadow[i]);
927 if (hw->addr_ctrl.mta_in_use > 0) {
928 u32 psrctl = rd32(hw, TXGBE_PSRCTL);
929 psrctl &= ~(TXGBE_PSRCTL_ADHF12_MASK | TXGBE_PSRCTL_MCHFENA);
930 psrctl |= TXGBE_PSRCTL_MCHFENA |
931 TXGBE_PSRCTL_ADHF12(hw->mac.mc_filter_type);
932 wr32(hw, TXGBE_PSRCTL, psrctl);
935 DEBUGOUT("txgbe update mc addr list complete\n");
940 * txgbe_fc_enable - Enable flow control
941 * @hw: pointer to hardware structure
943 * Enable flow control according to the current settings.
945 s32 txgbe_fc_enable(struct txgbe_hw *hw)
948 u32 mflcn_reg, fccfg_reg;
953 DEBUGFUNC("txgbe_fc_enable");
955 /* Validate the water mark configuration */
956 if (!hw->fc.pause_time) {
957 err = TXGBE_ERR_INVALID_LINK_SETTINGS;
961 /* Low water mark of zero causes XOFF floods */
962 for (i = 0; i < TXGBE_DCB_TC_MAX; i++) {
963 if ((hw->fc.current_mode & txgbe_fc_tx_pause) &&
964 hw->fc.high_water[i]) {
965 if (!hw->fc.low_water[i] ||
966 hw->fc.low_water[i] >= hw->fc.high_water[i]) {
967 DEBUGOUT("Invalid water mark configuration\n");
968 err = TXGBE_ERR_INVALID_LINK_SETTINGS;
974 /* Negotiate the fc mode to use */
975 hw->mac.fc_autoneg(hw);
977 /* Disable any previous flow control settings */
978 mflcn_reg = rd32(hw, TXGBE_RXFCCFG);
979 mflcn_reg &= ~(TXGBE_RXFCCFG_FC | TXGBE_RXFCCFG_PFC);
981 fccfg_reg = rd32(hw, TXGBE_TXFCCFG);
982 fccfg_reg &= ~(TXGBE_TXFCCFG_FC | TXGBE_TXFCCFG_PFC);
985 * The possible values of fc.current_mode are:
986 * 0: Flow control is completely disabled
987 * 1: Rx flow control is enabled (we can receive pause frames,
988 * but not send pause frames).
989 * 2: Tx flow control is enabled (we can send pause frames but
990 * we do not support receiving pause frames).
991 * 3: Both Rx and Tx flow control (symmetric) are enabled.
994 switch (hw->fc.current_mode) {
997 * Flow control is disabled by software override or autoneg.
998 * The code below will actually disable it in the HW.
1001 case txgbe_fc_rx_pause:
1003 * Rx Flow control is enabled and Tx Flow control is
1004 * disabled by software override. Since there really
1005 * isn't a way to advertise that we are capable of RX
1006 * Pause ONLY, we will advertise that we support both
1007 * symmetric and asymmetric Rx PAUSE. Later, we will
1008 * disable the adapter's ability to send PAUSE frames.
1010 mflcn_reg |= TXGBE_RXFCCFG_FC;
1012 case txgbe_fc_tx_pause:
1014 * Tx Flow control is enabled, and Rx Flow control is
1015 * disabled by software override.
1017 fccfg_reg |= TXGBE_TXFCCFG_FC;
1020 /* Flow control (both Rx and Tx) is enabled by SW override. */
1021 mflcn_reg |= TXGBE_RXFCCFG_FC;
1022 fccfg_reg |= TXGBE_TXFCCFG_FC;
1025 DEBUGOUT("Flow control param set incorrectly\n");
1026 err = TXGBE_ERR_CONFIG;
1030 /* Set 802.3x based flow control settings. */
1031 wr32(hw, TXGBE_RXFCCFG, mflcn_reg);
1032 wr32(hw, TXGBE_TXFCCFG, fccfg_reg);
1034 /* Set up and enable Rx high/low water mark thresholds, enable XON. */
1035 for (i = 0; i < TXGBE_DCB_TC_MAX; i++) {
1036 if ((hw->fc.current_mode & txgbe_fc_tx_pause) &&
1037 hw->fc.high_water[i]) {
1038 fcrtl = TXGBE_FCWTRLO_TH(hw->fc.low_water[i]) |
1040 fcrth = TXGBE_FCWTRHI_TH(hw->fc.high_water[i]) |
1044 * In order to prevent Tx hangs when the internal Tx
1045 * switch is enabled we must set the high water mark
1046 * to the Rx packet buffer size - 24KB. This allows
1047 * the Tx switch to function even under heavy Rx
1051 fcrth = rd32(hw, TXGBE_PBRXSIZE(i)) - 24576;
1053 wr32(hw, TXGBE_FCWTRLO(i), fcrtl);
1054 wr32(hw, TXGBE_FCWTRHI(i), fcrth);
1057 /* Configure pause time (2 TCs per register) */
1058 pause_time = TXGBE_RXFCFSH_TIME(hw->fc.pause_time);
1059 for (i = 0; i < (TXGBE_DCB_TC_MAX / 2); i++)
1060 wr32(hw, TXGBE_FCXOFFTM(i), pause_time * 0x00010001);
1062 /* Configure flow control refresh threshold value */
1063 wr32(hw, TXGBE_RXFCRFSH, hw->fc.pause_time / 2);
1070 * txgbe_negotiate_fc - Negotiate flow control
1071 * @hw: pointer to hardware structure
1072 * @adv_reg: flow control advertised settings
1073 * @lp_reg: link partner's flow control settings
1074 * @adv_sym: symmetric pause bit in advertisement
1075 * @adv_asm: asymmetric pause bit in advertisement
1076 * @lp_sym: symmetric pause bit in link partner advertisement
1077 * @lp_asm: asymmetric pause bit in link partner advertisement
1079 * Find the intersection between advertised settings and link partner's
1080 * advertised settings
1082 s32 txgbe_negotiate_fc(struct txgbe_hw *hw, u32 adv_reg, u32 lp_reg,
1083 u32 adv_sym, u32 adv_asm, u32 lp_sym, u32 lp_asm)
1085 if ((!(adv_reg)) || (!(lp_reg))) {
1086 DEBUGOUT("Local or link partner's advertised flow control "
1087 "settings are NULL. Local: %x, link partner: %x\n",
1089 return TXGBE_ERR_FC_NOT_NEGOTIATED;
1092 if ((adv_reg & adv_sym) && (lp_reg & lp_sym)) {
1094 * Now we need to check if the user selected Rx ONLY
1095 * of pause frames. In this case, we had to advertise
1096 * FULL flow control because we could not advertise RX
1097 * ONLY. Hence, we must now check to see if we need to
1098 * turn OFF the TRANSMISSION of PAUSE frames.
1100 if (hw->fc.requested_mode == txgbe_fc_full) {
1101 hw->fc.current_mode = txgbe_fc_full;
1102 DEBUGOUT("Flow Control = FULL.\n");
1104 hw->fc.current_mode = txgbe_fc_rx_pause;
1105 DEBUGOUT("Flow Control=RX PAUSE frames only\n");
1107 } else if (!(adv_reg & adv_sym) && (adv_reg & adv_asm) &&
1108 (lp_reg & lp_sym) && (lp_reg & lp_asm)) {
1109 hw->fc.current_mode = txgbe_fc_tx_pause;
1110 DEBUGOUT("Flow Control = TX PAUSE frames only.\n");
1111 } else if ((adv_reg & adv_sym) && (adv_reg & adv_asm) &&
1112 !(lp_reg & lp_sym) && (lp_reg & lp_asm)) {
1113 hw->fc.current_mode = txgbe_fc_rx_pause;
1114 DEBUGOUT("Flow Control = RX PAUSE frames only.\n");
1116 hw->fc.current_mode = txgbe_fc_none;
1117 DEBUGOUT("Flow Control = NONE.\n");
1123 * txgbe_fc_autoneg_fiber - Enable flow control on 1 gig fiber
1124 * @hw: pointer to hardware structure
1126 * Enable flow control according on 1 gig fiber.
1128 STATIC s32 txgbe_fc_autoneg_fiber(struct txgbe_hw *hw)
1130 u32 pcs_anadv_reg, pcs_lpab_reg;
1131 s32 err = TXGBE_ERR_FC_NOT_NEGOTIATED;
1134 * On multispeed fiber at 1g, bail out if
1135 * - link is up but AN did not complete, or if
1136 * - link is up and AN completed but timed out
1139 pcs_anadv_reg = rd32_epcs(hw, SR_MII_MMD_AN_ADV);
1140 pcs_lpab_reg = rd32_epcs(hw, SR_MII_MMD_LP_BABL);
1142 err = txgbe_negotiate_fc(hw, pcs_anadv_reg,
1144 SR_MII_MMD_AN_ADV_PAUSE_SYM,
1145 SR_MII_MMD_AN_ADV_PAUSE_ASM,
1146 SR_MII_MMD_AN_ADV_PAUSE_SYM,
1147 SR_MII_MMD_AN_ADV_PAUSE_ASM);
1153 * txgbe_fc_autoneg_backplane - Enable flow control IEEE clause 37
1154 * @hw: pointer to hardware structure
1156 * Enable flow control according to IEEE clause 37.
1158 STATIC s32 txgbe_fc_autoneg_backplane(struct txgbe_hw *hw)
1160 u32 anlp1_reg, autoc_reg;
1161 s32 err = TXGBE_ERR_FC_NOT_NEGOTIATED;
1164 * Read the 10g AN autoc and LP ability registers and resolve
1165 * local flow control settings accordingly
1167 autoc_reg = rd32_epcs(hw, SR_AN_MMD_ADV_REG1);
1168 anlp1_reg = rd32_epcs(hw, SR_AN_MMD_LP_ABL1);
1170 err = txgbe_negotiate_fc(hw, autoc_reg,
1172 SR_AN_MMD_ADV_REG1_PAUSE_SYM,
1173 SR_AN_MMD_ADV_REG1_PAUSE_ASM,
1174 SR_AN_MMD_ADV_REG1_PAUSE_SYM,
1175 SR_AN_MMD_ADV_REG1_PAUSE_ASM);
1181 * txgbe_fc_autoneg_copper - Enable flow control IEEE clause 37
1182 * @hw: pointer to hardware structure
1184 * Enable flow control according to IEEE clause 37.
1186 STATIC s32 txgbe_fc_autoneg_copper(struct txgbe_hw *hw)
1188 u16 technology_ability_reg = 0;
1189 u16 lp_technology_ability_reg = 0;
1191 hw->phy.read_reg(hw, TXGBE_MD_AUTO_NEG_ADVT,
1192 TXGBE_MD_DEV_AUTO_NEG,
1193 &technology_ability_reg);
1194 hw->phy.read_reg(hw, TXGBE_MD_AUTO_NEG_LP,
1195 TXGBE_MD_DEV_AUTO_NEG,
1196 &lp_technology_ability_reg);
1198 return txgbe_negotiate_fc(hw, (u32)technology_ability_reg,
1199 (u32)lp_technology_ability_reg,
1200 TXGBE_TAF_SYM_PAUSE, TXGBE_TAF_ASM_PAUSE,
1201 TXGBE_TAF_SYM_PAUSE, TXGBE_TAF_ASM_PAUSE);
1205 * txgbe_fc_autoneg - Configure flow control
1206 * @hw: pointer to hardware structure
1208 * Compares our advertised flow control capabilities to those advertised by
1209 * our link partner, and determines the proper flow control mode to use.
1211 void txgbe_fc_autoneg(struct txgbe_hw *hw)
1213 s32 err = TXGBE_ERR_FC_NOT_NEGOTIATED;
1217 DEBUGFUNC("txgbe_fc_autoneg");
1220 * AN should have completed when the cable was plugged in.
1221 * Look for reasons to bail out. Bail out if:
1222 * - FC autoneg is disabled, or if
1225 if (hw->fc.disable_fc_autoneg) {
1226 DEBUGOUT("Flow control autoneg is disabled");
1230 hw->mac.check_link(hw, &speed, &link_up, false);
1232 DEBUGOUT("The link is down");
1236 switch (hw->phy.media_type) {
1237 /* Autoneg flow control on fiber adapters */
1238 case txgbe_media_type_fiber_qsfp:
1239 case txgbe_media_type_fiber:
1240 if (speed == TXGBE_LINK_SPEED_1GB_FULL)
1241 err = txgbe_fc_autoneg_fiber(hw);
1244 /* Autoneg flow control on backplane adapters */
1245 case txgbe_media_type_backplane:
1246 err = txgbe_fc_autoneg_backplane(hw);
1249 /* Autoneg flow control on copper adapters */
1250 case txgbe_media_type_copper:
1251 if (txgbe_device_supports_autoneg_fc(hw))
1252 err = txgbe_fc_autoneg_copper(hw);
1261 hw->fc.fc_was_autonegged = true;
1263 hw->fc.fc_was_autonegged = false;
1264 hw->fc.current_mode = hw->fc.requested_mode;
1269 * txgbe_acquire_swfw_sync - Acquire SWFW semaphore
1270 * @hw: pointer to hardware structure
1271 * @mask: Mask to specify which semaphore to acquire
1273 * Acquires the SWFW semaphore through the MNGSEM register for the specified
1274 * function (CSR, PHY0, PHY1, EEPROM, Flash)
1276 s32 txgbe_acquire_swfw_sync(struct txgbe_hw *hw, u32 mask)
1279 u32 swmask = TXGBE_MNGSEM_SW(mask);
1280 u32 fwmask = TXGBE_MNGSEM_FW(mask);
1284 DEBUGFUNC("txgbe_acquire_swfw_sync");
1286 for (i = 0; i < timeout; i++) {
1288 * SW NVM semaphore bit is used for access to all
1289 * SW_FW_SYNC bits (not just NVM)
1291 if (txgbe_get_eeprom_semaphore(hw))
1292 return TXGBE_ERR_SWFW_SYNC;
1294 mngsem = rd32(hw, TXGBE_MNGSEM);
1295 if (mngsem & (fwmask | swmask)) {
1296 /* Resource is currently in use by FW or SW */
1297 txgbe_release_eeprom_semaphore(hw);
1301 wr32(hw, TXGBE_MNGSEM, mngsem);
1302 txgbe_release_eeprom_semaphore(hw);
1307 /* If time expired clear the bits holding the lock and retry */
1308 if (mngsem & (fwmask | swmask))
1309 txgbe_release_swfw_sync(hw, mngsem & (fwmask | swmask));
1312 return TXGBE_ERR_SWFW_SYNC;
1316 * txgbe_release_swfw_sync - Release SWFW semaphore
1317 * @hw: pointer to hardware structure
1318 * @mask: Mask to specify which semaphore to release
1320 * Releases the SWFW semaphore through the MNGSEM register for the specified
1321 * function (CSR, PHY0, PHY1, EEPROM, Flash)
1323 void txgbe_release_swfw_sync(struct txgbe_hw *hw, u32 mask)
1328 DEBUGFUNC("txgbe_release_swfw_sync");
1330 txgbe_get_eeprom_semaphore(hw);
1332 mngsem = rd32(hw, TXGBE_MNGSEM);
1334 wr32(hw, TXGBE_MNGSEM, mngsem);
1336 txgbe_release_eeprom_semaphore(hw);
1340 * txgbe_disable_sec_rx_path - Stops the receive data path
1341 * @hw: pointer to hardware structure
1343 * Stops the receive data path and waits for the HW to internally empty
1344 * the Rx security block
1346 s32 txgbe_disable_sec_rx_path(struct txgbe_hw *hw)
1348 #define TXGBE_MAX_SECRX_POLL 4000
1353 DEBUGFUNC("txgbe_disable_sec_rx_path");
1355 secrxreg = rd32(hw, TXGBE_SECRXCTL);
1356 secrxreg |= TXGBE_SECRXCTL_XDSA;
1357 wr32(hw, TXGBE_SECRXCTL, secrxreg);
1358 for (i = 0; i < TXGBE_MAX_SECRX_POLL; i++) {
1359 secrxreg = rd32(hw, TXGBE_SECRXSTAT);
1360 if (!(secrxreg & TXGBE_SECRXSTAT_RDY))
1361 /* Use interrupt-safe sleep just in case */
1367 /* For informational purposes only */
1368 if (i >= TXGBE_MAX_SECRX_POLL)
1369 DEBUGOUT("Rx unit being enabled before security "
1370 "path fully disabled. Continuing with init.\n");
1376 * txgbe_enable_sec_rx_path - Enables the receive data path
1377 * @hw: pointer to hardware structure
1379 * Enables the receive data path.
1381 s32 txgbe_enable_sec_rx_path(struct txgbe_hw *hw)
1385 DEBUGFUNC("txgbe_enable_sec_rx_path");
1387 secrxreg = rd32(hw, TXGBE_SECRXCTL);
1388 secrxreg &= ~TXGBE_SECRXCTL_XDSA;
1389 wr32(hw, TXGBE_SECRXCTL, secrxreg);
1396 * txgbe_disable_sec_tx_path - Stops the transmit data path
1397 * @hw: pointer to hardware structure
1399 * Stops the transmit data path and waits for the HW to internally empty
1400 * the Tx security block
1402 int txgbe_disable_sec_tx_path(struct txgbe_hw *hw)
1404 #define TXGBE_MAX_SECTX_POLL 40
1409 sectxreg = rd32(hw, TXGBE_SECTXCTL);
1410 sectxreg |= TXGBE_SECTXCTL_XDSA;
1411 wr32(hw, TXGBE_SECTXCTL, sectxreg);
1412 for (i = 0; i < TXGBE_MAX_SECTX_POLL; i++) {
1413 sectxreg = rd32(hw, TXGBE_SECTXSTAT);
1414 if (sectxreg & TXGBE_SECTXSTAT_RDY)
1416 /* Use interrupt-safe sleep just in case */
1420 /* For informational purposes only */
1421 if (i >= TXGBE_MAX_SECTX_POLL)
1422 PMD_DRV_LOG(DEBUG, "Tx unit being enabled before security "
1423 "path fully disabled. Continuing with init.");
1429 * txgbe_enable_sec_tx_path - Enables the transmit data path
1430 * @hw: pointer to hardware structure
1432 * Enables the transmit data path.
1434 int txgbe_enable_sec_tx_path(struct txgbe_hw *hw)
1438 sectxreg = rd32(hw, TXGBE_SECTXCTL);
1439 sectxreg &= ~TXGBE_SECTXCTL_XDSA;
1440 wr32(hw, TXGBE_SECTXCTL, sectxreg);
1447 * txgbe_get_san_mac_addr_offset - Get SAN MAC address offset from the EEPROM
1448 * @hw: pointer to hardware structure
1449 * @san_mac_offset: SAN MAC address offset
1451 * This function will read the EEPROM location for the SAN MAC address
1452 * pointer, and returns the value at that location. This is used in both
1453 * get and set mac_addr routines.
1455 static s32 txgbe_get_san_mac_addr_offset(struct txgbe_hw *hw,
1456 u16 *san_mac_offset)
1460 DEBUGFUNC("txgbe_get_san_mac_addr_offset");
1463 * First read the EEPROM pointer to see if the MAC addresses are
1466 err = hw->rom.readw_sw(hw, TXGBE_SAN_MAC_ADDR_PTR,
1469 DEBUGOUT("eeprom at offset %d failed",
1470 TXGBE_SAN_MAC_ADDR_PTR);
1477 * txgbe_get_san_mac_addr - SAN MAC address retrieval from the EEPROM
1478 * @hw: pointer to hardware structure
1479 * @san_mac_addr: SAN MAC address
1481 * Reads the SAN MAC address from the EEPROM, if it's available. This is
1482 * per-port, so set_lan_id() must be called before reading the addresses.
1483 * set_lan_id() is called by identify_sfp(), but this cannot be relied
1484 * upon for non-SFP connections, so we must call it here.
1486 s32 txgbe_get_san_mac_addr(struct txgbe_hw *hw, u8 *san_mac_addr)
1488 u16 san_mac_data, san_mac_offset;
1492 DEBUGFUNC("txgbe_get_san_mac_addr");
1495 * First read the EEPROM pointer to see if the MAC addresses are
1496 * available. If they're not, no point in calling set_lan_id() here.
1498 err = txgbe_get_san_mac_addr_offset(hw, &san_mac_offset);
1499 if (err || san_mac_offset == 0 || san_mac_offset == 0xFFFF)
1500 goto san_mac_addr_out;
1502 /* apply the port offset to the address offset */
1503 (hw->bus.func) ? (san_mac_offset += TXGBE_SAN_MAC_ADDR_PORT1_OFFSET) :
1504 (san_mac_offset += TXGBE_SAN_MAC_ADDR_PORT0_OFFSET);
1505 for (i = 0; i < 3; i++) {
1506 err = hw->rom.read16(hw, san_mac_offset,
1509 DEBUGOUT("eeprom read at offset %d failed",
1511 goto san_mac_addr_out;
1513 san_mac_addr[i * 2] = (u8)(san_mac_data);
1514 san_mac_addr[i * 2 + 1] = (u8)(san_mac_data >> 8);
1521 * No addresses available in this EEPROM. It's not an
1522 * error though, so just wipe the local address and return.
1524 for (i = 0; i < 6; i++)
1525 san_mac_addr[i] = 0xFF;
1530 * txgbe_set_san_mac_addr - Write the SAN MAC address to the EEPROM
1531 * @hw: pointer to hardware structure
1532 * @san_mac_addr: SAN MAC address
1534 * Write a SAN MAC address to the EEPROM.
1536 s32 txgbe_set_san_mac_addr(struct txgbe_hw *hw, u8 *san_mac_addr)
1539 u16 san_mac_data, san_mac_offset;
1542 DEBUGFUNC("txgbe_set_san_mac_addr");
1544 /* Look for SAN mac address pointer. If not defined, return */
1545 err = txgbe_get_san_mac_addr_offset(hw, &san_mac_offset);
1546 if (err || san_mac_offset == 0 || san_mac_offset == 0xFFFF)
1547 return TXGBE_ERR_NO_SAN_ADDR_PTR;
1549 /* Apply the port offset to the address offset */
1550 (hw->bus.func) ? (san_mac_offset += TXGBE_SAN_MAC_ADDR_PORT1_OFFSET) :
1551 (san_mac_offset += TXGBE_SAN_MAC_ADDR_PORT0_OFFSET);
1553 for (i = 0; i < 3; i++) {
1554 san_mac_data = (u16)((u16)(san_mac_addr[i * 2 + 1]) << 8);
1555 san_mac_data |= (u16)(san_mac_addr[i * 2]);
1556 hw->rom.write16(hw, san_mac_offset, san_mac_data);
1564 * txgbe_clear_vmdq - Disassociate a VMDq pool index from a rx address
1565 * @hw: pointer to hardware struct
1566 * @rar: receive address register index to disassociate
1567 * @vmdq: VMDq pool index to remove from the rar
1569 s32 txgbe_clear_vmdq(struct txgbe_hw *hw, u32 rar, u32 vmdq)
1571 u32 mpsar_lo, mpsar_hi;
1572 u32 rar_entries = hw->mac.num_rar_entries;
1574 DEBUGFUNC("txgbe_clear_vmdq");
1576 /* Make sure we are using a valid rar index range */
1577 if (rar >= rar_entries) {
1578 DEBUGOUT("RAR index %d is out of range.\n", rar);
1579 return TXGBE_ERR_INVALID_ARGUMENT;
1582 wr32(hw, TXGBE_ETHADDRIDX, rar);
1583 mpsar_lo = rd32(hw, TXGBE_ETHADDRASSL);
1584 mpsar_hi = rd32(hw, TXGBE_ETHADDRASSH);
1586 if (TXGBE_REMOVED(hw->hw_addr))
1589 if (!mpsar_lo && !mpsar_hi)
1592 if (vmdq == BIT_MASK32) {
1594 wr32(hw, TXGBE_ETHADDRASSL, 0);
1598 wr32(hw, TXGBE_ETHADDRASSH, 0);
1601 } else if (vmdq < 32) {
1602 mpsar_lo &= ~(1 << vmdq);
1603 wr32(hw, TXGBE_ETHADDRASSL, mpsar_lo);
1605 mpsar_hi &= ~(1 << (vmdq - 32));
1606 wr32(hw, TXGBE_ETHADDRASSH, mpsar_hi);
1609 /* was that the last pool using this rar? */
1610 if (mpsar_lo == 0 && mpsar_hi == 0 &&
1611 rar != 0 && rar != hw->mac.san_mac_rar_index)
1612 hw->mac.clear_rar(hw, rar);
1618 * txgbe_set_vmdq - Associate a VMDq pool index with a rx address
1619 * @hw: pointer to hardware struct
1620 * @rar: receive address register index to associate with a VMDq index
1621 * @vmdq: VMDq pool index
1623 s32 txgbe_set_vmdq(struct txgbe_hw *hw, u32 rar, u32 vmdq)
1626 u32 rar_entries = hw->mac.num_rar_entries;
1628 DEBUGFUNC("txgbe_set_vmdq");
1630 /* Make sure we are using a valid rar index range */
1631 if (rar >= rar_entries) {
1632 DEBUGOUT("RAR index %d is out of range.\n", rar);
1633 return TXGBE_ERR_INVALID_ARGUMENT;
1636 wr32(hw, TXGBE_ETHADDRIDX, rar);
1638 mpsar = rd32(hw, TXGBE_ETHADDRASSL);
1640 wr32(hw, TXGBE_ETHADDRASSL, mpsar);
1642 mpsar = rd32(hw, TXGBE_ETHADDRASSH);
1643 mpsar |= 1 << (vmdq - 32);
1644 wr32(hw, TXGBE_ETHADDRASSH, mpsar);
1650 * txgbe_init_uta_tables - Initialize the Unicast Table Array
1651 * @hw: pointer to hardware structure
1653 s32 txgbe_init_uta_tables(struct txgbe_hw *hw)
1657 DEBUGFUNC("txgbe_init_uta_tables");
1658 DEBUGOUT(" Clearing UTA\n");
1660 for (i = 0; i < 128; i++)
1661 wr32(hw, TXGBE_UCADDRTBL(i), 0);
1667 * txgbe_find_vlvf_slot - find the vlanid or the first empty slot
1668 * @hw: pointer to hardware structure
1669 * @vlan: VLAN id to write to VLAN filter
1670 * @vlvf_bypass: true to find vlanid only, false returns first empty slot if
1674 * return the VLVF index where this VLAN id should be placed
1677 s32 txgbe_find_vlvf_slot(struct txgbe_hw *hw, u32 vlan, bool vlvf_bypass)
1679 s32 regindex, first_empty_slot;
1682 /* short cut the special case */
1686 /* if vlvf_bypass is set we don't want to use an empty slot, we
1687 * will simply bypass the VLVF if there are no entries present in the
1688 * VLVF that contain our VLAN
1690 first_empty_slot = vlvf_bypass ? TXGBE_ERR_NO_SPACE : 0;
1692 /* add VLAN enable bit for comparison */
1693 vlan |= TXGBE_PSRVLAN_EA;
1695 /* Search for the vlan id in the VLVF entries. Save off the first empty
1696 * slot found along the way.
1698 * pre-decrement loop covering (TXGBE_NUM_POOL - 1) .. 1
1700 for (regindex = TXGBE_NUM_POOL; --regindex;) {
1701 wr32(hw, TXGBE_PSRVLANIDX, regindex);
1702 bits = rd32(hw, TXGBE_PSRVLAN);
1705 if (!first_empty_slot && !bits)
1706 first_empty_slot = regindex;
1709 /* If we are here then we didn't find the VLAN. Return first empty
1710 * slot we found during our search, else error.
1712 if (!first_empty_slot)
1713 DEBUGOUT("No space in VLVF.\n");
1715 return first_empty_slot ? first_empty_slot : TXGBE_ERR_NO_SPACE;
1719 * txgbe_set_vfta - Set VLAN filter table
1720 * @hw: pointer to hardware structure
1721 * @vlan: VLAN id to write to VLAN filter
1722 * @vind: VMDq output index that maps queue to VLAN id in VLVFB
1723 * @vlan_on: boolean flag to turn on/off VLAN
1724 * @vlvf_bypass: boolean flag indicating updating default pool is okay
1726 * Turn on/off specified VLAN in the VLAN filter table.
1728 s32 txgbe_set_vfta(struct txgbe_hw *hw, u32 vlan, u32 vind,
1729 bool vlan_on, bool vlvf_bypass)
1731 u32 regidx, vfta_delta, vfta;
1734 DEBUGFUNC("txgbe_set_vfta");
1736 if (vlan > 4095 || vind > 63)
1737 return TXGBE_ERR_PARAM;
1740 * this is a 2 part operation - first the VFTA, then the
1741 * VLVF and VLVFB if VT Mode is set
1742 * We don't write the VFTA until we know the VLVF part succeeded.
1746 * The VFTA is a bitstring made up of 128 32-bit registers
1747 * that enable the particular VLAN id, much like the MTA:
1748 * bits[11-5]: which register
1749 * bits[4-0]: which bit in the register
1752 vfta_delta = 1 << (vlan % 32);
1753 vfta = rd32(hw, TXGBE_VLANTBL(regidx));
1756 * vfta_delta represents the difference between the current value
1757 * of vfta and the value we want in the register. Since the diff
1758 * is an XOR mask we can just update the vfta using an XOR
1760 vfta_delta &= vlan_on ? ~vfta : vfta;
1764 * Call txgbe_set_vlvf to set VLVFB and VLVF
1766 err = txgbe_set_vlvf(hw, vlan, vind, vlan_on, &vfta_delta,
1775 /* Update VFTA now that we are ready for traffic */
1777 wr32(hw, TXGBE_VLANTBL(regidx), vfta);
1783 * txgbe_set_vlvf - Set VLAN Pool Filter
1784 * @hw: pointer to hardware structure
1785 * @vlan: VLAN id to write to VLAN filter
1786 * @vind: VMDq output index that maps queue to VLAN id in PSRVLANPLM
1787 * @vlan_on: boolean flag to turn on/off VLAN in PSRVLAN
1788 * @vfta_delta: pointer to the difference between the current value
1789 * of PSRVLANPLM and the desired value
1790 * @vfta: the desired value of the VFTA
1791 * @vlvf_bypass: boolean flag indicating updating default pool is okay
1793 * Turn on/off specified bit in VLVF table.
1795 s32 txgbe_set_vlvf(struct txgbe_hw *hw, u32 vlan, u32 vind,
1796 bool vlan_on, u32 *vfta_delta, u32 vfta,
1803 DEBUGFUNC("txgbe_set_vlvf");
1805 if (vlan > 4095 || vind > 63)
1806 return TXGBE_ERR_PARAM;
1808 /* If VT Mode is set
1810 * make sure the vlan is in PSRVLAN
1811 * set the vind bit in the matching PSRVLANPLM
1813 * clear the pool bit and possibly the vind
1815 portctl = rd32(hw, TXGBE_PORTCTL);
1816 if (!(portctl & TXGBE_PORTCTL_NUMVT_MASK))
1819 vlvf_index = txgbe_find_vlvf_slot(hw, vlan, vlvf_bypass);
1823 wr32(hw, TXGBE_PSRVLANIDX, vlvf_index);
1824 bits = rd32(hw, TXGBE_PSRVLANPLM(vind / 32));
1826 /* set the pool bit */
1827 bits |= 1 << (vind % 32);
1831 /* clear the pool bit */
1832 bits ^= 1 << (vind % 32);
1835 !rd32(hw, TXGBE_PSRVLANPLM(vind / 32))) {
1836 /* Clear PSRVLANPLM first, then disable PSRVLAN. Otherwise
1837 * we run the risk of stray packets leaking into
1838 * the PF via the default pool
1841 wr32(hw, TXGBE_PSRVLANPLM(vlan / 32), vfta);
1843 /* disable VLVF and clear remaining bit from pool */
1844 wr32(hw, TXGBE_PSRVLAN, 0);
1845 wr32(hw, TXGBE_PSRVLANPLM(vind / 32), 0);
1850 /* If there are still bits set in the PSRVLANPLM registers
1851 * for the VLAN ID indicated we need to see if the
1852 * caller is requesting that we clear the PSRVLANPLM entry bit.
1853 * If the caller has requested that we clear the PSRVLANPLM
1854 * entry bit but there are still pools/VFs using this VLAN
1855 * ID entry then ignore the request. We're not worried
1856 * about the case where we're turning the PSRVLANPLM VLAN ID
1857 * entry bit on, only when requested to turn it off as
1858 * there may be multiple pools and/or VFs using the
1859 * VLAN ID entry. In that case we cannot clear the
1860 * PSRVLANPLM bit until all pools/VFs using that VLAN ID have also
1861 * been cleared. This will be indicated by "bits" being
1867 /* record pool change and enable VLAN ID if not already enabled */
1868 wr32(hw, TXGBE_PSRVLANPLM(vind / 32), bits);
1869 wr32(hw, TXGBE_PSRVLAN, TXGBE_PSRVLAN_EA | vlan);
1875 * txgbe_clear_vfta - Clear VLAN filter table
1876 * @hw: pointer to hardware structure
1878 * Clears the VLAN filer table, and the VMDq index associated with the filter
1880 s32 txgbe_clear_vfta(struct txgbe_hw *hw)
1884 DEBUGFUNC("txgbe_clear_vfta");
1886 for (offset = 0; offset < hw->mac.vft_size; offset++)
1887 wr32(hw, TXGBE_VLANTBL(offset), 0);
1889 for (offset = 0; offset < TXGBE_NUM_POOL; offset++) {
1890 wr32(hw, TXGBE_PSRVLANIDX, offset);
1891 wr32(hw, TXGBE_PSRVLAN, 0);
1892 wr32(hw, TXGBE_PSRVLANPLM(0), 0);
1893 wr32(hw, TXGBE_PSRVLANPLM(1), 0);
1900 * txgbe_need_crosstalk_fix - Determine if we need to do cross talk fix
1901 * @hw: pointer to hardware structure
1903 * Contains the logic to identify if we need to verify link for the
1906 static bool txgbe_need_crosstalk_fix(struct txgbe_hw *hw)
1908 /* Does FW say we need the fix */
1909 if (!hw->need_crosstalk_fix)
1912 /* Only consider SFP+ PHYs i.e. media type fiber */
1913 switch (hw->phy.media_type) {
1914 case txgbe_media_type_fiber:
1915 case txgbe_media_type_fiber_qsfp:
1925 * txgbe_check_mac_link - Determine link and speed status
1926 * @hw: pointer to hardware structure
1927 * @speed: pointer to link speed
1928 * @link_up: true when link is up
1929 * @link_up_wait_to_complete: bool used to wait for link up or not
1931 * Reads the links register to determine if link is up and the current speed
1933 s32 txgbe_check_mac_link(struct txgbe_hw *hw, u32 *speed,
1934 bool *link_up, bool link_up_wait_to_complete)
1936 u32 links_reg, links_orig;
1939 DEBUGFUNC("txgbe_check_mac_link");
1941 /* If Crosstalk fix enabled do the sanity check of making sure
1942 * the SFP+ cage is full.
1944 if (txgbe_need_crosstalk_fix(hw)) {
1947 switch (hw->mac.type) {
1948 case txgbe_mac_raptor:
1949 sfp_cage_full = !rd32m(hw, TXGBE_GPIODATA,
1953 /* sanity check - No SFP+ devices here */
1954 sfp_cage_full = false;
1958 if (!sfp_cage_full) {
1960 *speed = TXGBE_LINK_SPEED_UNKNOWN;
1965 /* clear the old state */
1966 links_orig = rd32(hw, TXGBE_PORTSTAT);
1968 links_reg = rd32(hw, TXGBE_PORTSTAT);
1970 if (links_orig != links_reg) {
1971 DEBUGOUT("LINKS changed from %08X to %08X\n",
1972 links_orig, links_reg);
1975 if (link_up_wait_to_complete) {
1976 for (i = 0; i < hw->mac.max_link_up_time; i++) {
1977 if (!(links_reg & TXGBE_PORTSTAT_UP)) {
1984 links_reg = rd32(hw, TXGBE_PORTSTAT);
1987 if (links_reg & TXGBE_PORTSTAT_UP)
1993 switch (links_reg & TXGBE_PORTSTAT_BW_MASK) {
1994 case TXGBE_PORTSTAT_BW_10G:
1995 *speed = TXGBE_LINK_SPEED_10GB_FULL;
1997 case TXGBE_PORTSTAT_BW_1G:
1998 *speed = TXGBE_LINK_SPEED_1GB_FULL;
2000 case TXGBE_PORTSTAT_BW_100M:
2001 *speed = TXGBE_LINK_SPEED_100M_FULL;
2004 *speed = TXGBE_LINK_SPEED_UNKNOWN;
2011 * txgbe_get_wwn_prefix - Get alternative WWNN/WWPN prefix from
2013 * @hw: pointer to hardware structure
2014 * @wwnn_prefix: the alternative WWNN prefix
2015 * @wwpn_prefix: the alternative WWPN prefix
2017 * This function will read the EEPROM from the alternative SAN MAC address
2018 * block to check the support for the alternative WWNN/WWPN prefix support.
2020 s32 txgbe_get_wwn_prefix(struct txgbe_hw *hw, u16 *wwnn_prefix,
2024 u16 alt_san_mac_blk_offset;
2026 DEBUGFUNC("txgbe_get_wwn_prefix");
2028 /* clear output first */
2029 *wwnn_prefix = 0xFFFF;
2030 *wwpn_prefix = 0xFFFF;
2032 /* check if alternative SAN MAC is supported */
2033 offset = TXGBE_ALT_SAN_MAC_ADDR_BLK_PTR;
2034 if (hw->rom.readw_sw(hw, offset, &alt_san_mac_blk_offset))
2035 goto wwn_prefix_err;
2037 if (alt_san_mac_blk_offset == 0 || alt_san_mac_blk_offset == 0xFFFF)
2038 goto wwn_prefix_out;
2040 /* check capability in alternative san mac address block */
2041 offset = alt_san_mac_blk_offset + TXGBE_ALT_SAN_MAC_ADDR_CAPS_OFFSET;
2042 if (hw->rom.read16(hw, offset, &caps))
2043 goto wwn_prefix_err;
2044 if (!(caps & TXGBE_ALT_SAN_MAC_ADDR_CAPS_ALTWWN))
2045 goto wwn_prefix_out;
2047 /* get the corresponding prefix for WWNN/WWPN */
2048 offset = alt_san_mac_blk_offset + TXGBE_ALT_SAN_MAC_ADDR_WWNN_OFFSET;
2049 if (hw->rom.read16(hw, offset, wwnn_prefix))
2050 DEBUGOUT("eeprom read at offset %d failed", offset);
2052 offset = alt_san_mac_blk_offset + TXGBE_ALT_SAN_MAC_ADDR_WWPN_OFFSET;
2053 if (hw->rom.read16(hw, offset, wwpn_prefix))
2054 goto wwn_prefix_err;
2060 DEBUGOUT("eeprom read at offset %d failed", offset);
2065 * txgbe_set_mac_anti_spoofing - Enable/Disable MAC anti-spoofing
2066 * @hw: pointer to hardware structure
2067 * @enable: enable or disable switch for MAC anti-spoofing
2068 * @vf: Virtual Function pool - VF Pool to set for MAC anti-spoofing
2071 void txgbe_set_mac_anti_spoofing(struct txgbe_hw *hw, bool enable, int vf)
2073 int vf_target_reg = vf >> 3;
2074 int vf_target_shift = vf % 8;
2077 pfvfspoof = rd32(hw, TXGBE_POOLTXASMAC(vf_target_reg));
2079 pfvfspoof |= (1 << vf_target_shift);
2081 pfvfspoof &= ~(1 << vf_target_shift);
2082 wr32(hw, TXGBE_POOLTXASMAC(vf_target_reg), pfvfspoof);
2086 * txgbe_set_ethertype_anti_spoofing - Configure Ethertype anti-spoofing
2087 * @hw: pointer to hardware structure
2088 * @enable: enable or disable switch for Ethertype anti-spoofing
2089 * @vf: Virtual Function pool - VF Pool to set for Ethertype anti-spoofing
2092 void txgbe_set_ethertype_anti_spoofing(struct txgbe_hw *hw,
2093 bool enable, int vf)
2095 int vf_target_reg = vf >> 3;
2096 int vf_target_shift = vf % 8;
2099 pfvfspoof = rd32(hw, TXGBE_POOLTXASET(vf_target_reg));
2101 pfvfspoof |= (1 << vf_target_shift);
2103 pfvfspoof &= ~(1 << vf_target_shift);
2104 wr32(hw, TXGBE_POOLTXASET(vf_target_reg), pfvfspoof);
2108 * txgbe_get_device_caps - Get additional device capabilities
2109 * @hw: pointer to hardware structure
2110 * @device_caps: the EEPROM word with the extra device capabilities
2112 * This function will read the EEPROM location for the device capabilities,
2113 * and return the word through device_caps.
2115 s32 txgbe_get_device_caps(struct txgbe_hw *hw, u16 *device_caps)
2117 DEBUGFUNC("txgbe_get_device_caps");
2119 hw->rom.readw_sw(hw, TXGBE_DEVICE_CAPS, device_caps);
2125 * txgbe_set_pba - Initialize Rx packet buffer
2126 * @hw: pointer to hardware structure
2127 * @num_pb: number of packet buffers to allocate
2128 * @headroom: reserve n KB of headroom
2129 * @strategy: packet buffer allocation strategy
2131 void txgbe_set_pba(struct txgbe_hw *hw, int num_pb, u32 headroom,
2134 u32 pbsize = hw->mac.rx_pb_size;
2136 u32 rxpktsize, txpktsize, txpbthresh;
2138 UNREFERENCED_PARAMETER(hw);
2140 /* Reserve headroom */
2146 /* Divide remaining packet buffer space amongst the number of packet
2147 * buffers requested using supplied strategy.
2150 case PBA_STRATEGY_WEIGHTED:
2151 /* txgbe_dcb_pba_80_48 strategy weight first half of packet
2152 * buffer with 5/8 of the packet buffer space.
2154 rxpktsize = (pbsize * 5) / (num_pb * 4);
2155 pbsize -= rxpktsize * (num_pb / 2);
2157 for (; i < (num_pb / 2); i++)
2158 wr32(hw, TXGBE_PBRXSIZE(i), rxpktsize);
2159 /* fall through - configure remaining packet buffers */
2160 case PBA_STRATEGY_EQUAL:
2161 rxpktsize = (pbsize / (num_pb - i));
2163 for (; i < num_pb; i++)
2164 wr32(hw, TXGBE_PBRXSIZE(i), rxpktsize);
2170 /* Only support an equally distributed Tx packet buffer strategy. */
2171 txpktsize = TXGBE_PBTXSIZE_MAX / num_pb;
2172 txpbthresh = (txpktsize / 1024) - TXGBE_TXPKT_SIZE_MAX;
2173 for (i = 0; i < num_pb; i++) {
2174 wr32(hw, TXGBE_PBTXSIZE(i), txpktsize);
2175 wr32(hw, TXGBE_PBTXDMATH(i), txpbthresh);
2178 /* Clear unused TCs, if any, to zero buffer size*/
2179 for (; i < TXGBE_MAX_UP; i++) {
2180 wr32(hw, TXGBE_PBRXSIZE(i), 0);
2181 wr32(hw, TXGBE_PBTXSIZE(i), 0);
2182 wr32(hw, TXGBE_PBTXDMATH(i), 0);
2187 * txgbe_clear_tx_pending - Clear pending TX work from the PCIe fifo
2188 * @hw: pointer to the hardware structure
2190 * The MACs can experience issues if TX work is still pending
2191 * when a reset occurs. This function prevents this by flushing the PCIe
2192 * buffers on the system.
2194 void txgbe_clear_tx_pending(struct txgbe_hw *hw)
2196 u32 hlreg0, i, poll;
2199 * If double reset is not requested then all transactions should
2200 * already be clear and as such there is no work to do
2202 if (!(hw->mac.flags & TXGBE_FLAGS_DOUBLE_RESET_REQUIRED))
2205 hlreg0 = rd32(hw, TXGBE_PSRCTL);
2206 wr32(hw, TXGBE_PSRCTL, hlreg0 | TXGBE_PSRCTL_LBENA);
2208 /* Wait for a last completion before clearing buffers */
2213 * Before proceeding, make sure that the PCIe block does not have
2214 * transactions pending.
2216 poll = (800 * 11) / 10;
2217 for (i = 0; i < poll; i++)
2220 /* Flush all writes and allow 20usec for all transactions to clear */
2224 /* restore previous register values */
2225 wr32(hw, TXGBE_PSRCTL, hlreg0);
2229 * txgbe_get_thermal_sensor_data - Gathers thermal sensor data
2230 * @hw: pointer to hardware structure
2232 * Returns the thermal sensor data structure
2234 s32 txgbe_get_thermal_sensor_data(struct txgbe_hw *hw)
2236 struct txgbe_thermal_sensor_data *data = &hw->mac.thermal_sensor_data;
2240 DEBUGFUNC("txgbe_get_thermal_sensor_data");
2242 /* Only support thermal sensors attached to physical port 0 */
2243 if (hw->bus.lan_id != 0)
2244 return TXGBE_NOT_IMPLEMENTED;
2246 ts_stat = rd32(hw, TXGBE_TSSTAT);
2247 tsv = (s64)TXGBE_TSSTAT_DATA(ts_stat);
2248 tsv = tsv > 1200 ? tsv : 1200;
2249 tsv = -(48380 << 8) / 1000
2250 + tsv * (31020 << 8) / 100000
2251 - tsv * tsv * (18201 << 8) / 100000000
2252 + tsv * tsv * tsv * (81542 << 8) / 1000000000000
2253 - tsv * tsv * tsv * tsv * (16743 << 8) / 1000000000000000;
2256 data->sensor[0].temp = (s16)tsv;
2262 * txgbe_init_thermal_sensor_thresh - Inits thermal sensor thresholds
2263 * @hw: pointer to hardware structure
2265 * Inits the thermal sensor thresholds according to the NVM map
2266 * and save off the threshold and location values into mac.thermal_sensor_data
2268 s32 txgbe_init_thermal_sensor_thresh(struct txgbe_hw *hw)
2270 struct txgbe_thermal_sensor_data *data = &hw->mac.thermal_sensor_data;
2272 DEBUGFUNC("txgbe_init_thermal_sensor_thresh");
2274 memset(data, 0, sizeof(struct txgbe_thermal_sensor_data));
2276 if (hw->bus.lan_id != 0)
2277 return TXGBE_NOT_IMPLEMENTED;
2279 wr32(hw, TXGBE_TSCTRL, TXGBE_TSCTRL_EVALMD);
2280 wr32(hw, TXGBE_TSINTR,
2281 TXGBE_TSINTR_AEN | TXGBE_TSINTR_DEN);
2282 wr32(hw, TXGBE_TSEN, TXGBE_TSEN_ENA);
2285 data->sensor[0].alarm_thresh = 100;
2286 wr32(hw, TXGBE_TSATHRE, 677);
2287 data->sensor[0].dalarm_thresh = 90;
2288 wr32(hw, TXGBE_TSDTHRE, 614);
2293 void txgbe_disable_rx(struct txgbe_hw *hw)
2297 pfdtxgswc = rd32(hw, TXGBE_PSRCTL);
2298 if (pfdtxgswc & TXGBE_PSRCTL_LBENA) {
2299 pfdtxgswc &= ~TXGBE_PSRCTL_LBENA;
2300 wr32(hw, TXGBE_PSRCTL, pfdtxgswc);
2301 hw->mac.set_lben = true;
2303 hw->mac.set_lben = false;
2306 wr32m(hw, TXGBE_PBRXCTL, TXGBE_PBRXCTL_ENA, 0);
2307 wr32m(hw, TXGBE_MACRXCFG, TXGBE_MACRXCFG_ENA, 0);
2310 void txgbe_enable_rx(struct txgbe_hw *hw)
2314 wr32m(hw, TXGBE_MACRXCFG, TXGBE_MACRXCFG_ENA, TXGBE_MACRXCFG_ENA);
2315 wr32m(hw, TXGBE_PBRXCTL, TXGBE_PBRXCTL_ENA, TXGBE_PBRXCTL_ENA);
2317 if (hw->mac.set_lben) {
2318 pfdtxgswc = rd32(hw, TXGBE_PSRCTL);
2319 pfdtxgswc |= TXGBE_PSRCTL_LBENA;
2320 wr32(hw, TXGBE_PSRCTL, pfdtxgswc);
2321 hw->mac.set_lben = false;
2326 * txgbe_setup_mac_link_multispeed_fiber - Set MAC link speed
2327 * @hw: pointer to hardware structure
2328 * @speed: new link speed
2329 * @autoneg_wait_to_complete: true when waiting for completion is needed
2331 * Set the link speed in the MAC and/or PHY register and restarts link.
2333 s32 txgbe_setup_mac_link_multispeed_fiber(struct txgbe_hw *hw,
2335 bool autoneg_wait_to_complete)
2337 u32 link_speed = TXGBE_LINK_SPEED_UNKNOWN;
2338 u32 highest_link_speed = TXGBE_LINK_SPEED_UNKNOWN;
2342 bool autoneg, link_up = false;
2344 DEBUGFUNC("txgbe_setup_mac_link_multispeed_fiber");
2346 /* Mask off requested but non-supported speeds */
2347 status = hw->mac.get_link_capabilities(hw, &link_speed, &autoneg);
2351 speed &= link_speed;
2353 /* Try each speed one by one, highest priority first. We do this in
2354 * software because 10Gb fiber doesn't support speed autonegotiation.
2356 if (speed & TXGBE_LINK_SPEED_10GB_FULL) {
2358 highest_link_speed = TXGBE_LINK_SPEED_10GB_FULL;
2360 /* Set the module link speed */
2361 switch (hw->phy.media_type) {
2362 case txgbe_media_type_fiber:
2363 hw->mac.set_rate_select_speed(hw,
2364 TXGBE_LINK_SPEED_10GB_FULL);
2366 case txgbe_media_type_fiber_qsfp:
2367 /* QSFP module automatically detects MAC link speed */
2370 DEBUGOUT("Unexpected media type.\n");
2374 /* Allow module to change analog characteristics (1G->10G) */
2377 status = hw->mac.setup_mac_link(hw,
2378 TXGBE_LINK_SPEED_10GB_FULL,
2379 autoneg_wait_to_complete);
2383 /* Flap the Tx laser if it has not already been done */
2384 hw->mac.flap_tx_laser(hw);
2386 /* Wait for the controller to acquire link. Per IEEE 802.3ap,
2387 * Section 73.10.2, we may have to wait up to 500ms if KR is
2388 * attempted. uses the same timing for 10g SFI.
2390 for (i = 0; i < 5; i++) {
2391 /* Wait for the link partner to also set speed */
2394 /* If we have link, just jump out */
2395 status = hw->mac.check_link(hw, &link_speed,
2405 if (speed & TXGBE_LINK_SPEED_1GB_FULL) {
2407 if (highest_link_speed == TXGBE_LINK_SPEED_UNKNOWN)
2408 highest_link_speed = TXGBE_LINK_SPEED_1GB_FULL;
2410 /* Set the module link speed */
2411 switch (hw->phy.media_type) {
2412 case txgbe_media_type_fiber:
2413 hw->mac.set_rate_select_speed(hw,
2414 TXGBE_LINK_SPEED_1GB_FULL);
2416 case txgbe_media_type_fiber_qsfp:
2417 /* QSFP module automatically detects link speed */
2420 DEBUGOUT("Unexpected media type.\n");
2424 /* Allow module to change analog characteristics (10G->1G) */
2427 status = hw->mac.setup_mac_link(hw,
2428 TXGBE_LINK_SPEED_1GB_FULL,
2429 autoneg_wait_to_complete);
2433 /* Flap the Tx laser if it has not already been done */
2434 hw->mac.flap_tx_laser(hw);
2436 /* Wait for the link partner to also set speed */
2439 /* If we have link, just jump out */
2440 status = hw->mac.check_link(hw, &link_speed, &link_up, false);
2448 /* We didn't get link. Configure back to the highest speed we tried,
2449 * (if there was more than one). We call ourselves back with just the
2450 * single highest speed that the user requested.
2453 status = txgbe_setup_mac_link_multispeed_fiber(hw,
2455 autoneg_wait_to_complete);
2458 /* Set autoneg_advertised value based on input link speed */
2459 hw->phy.autoneg_advertised = 0;
2461 if (speed & TXGBE_LINK_SPEED_10GB_FULL)
2462 hw->phy.autoneg_advertised |= TXGBE_LINK_SPEED_10GB_FULL;
2464 if (speed & TXGBE_LINK_SPEED_1GB_FULL)
2465 hw->phy.autoneg_advertised |= TXGBE_LINK_SPEED_1GB_FULL;
2471 * txgbe_init_shared_code - Initialize the shared code
2472 * @hw: pointer to hardware structure
2474 * This will assign function pointers and assign the MAC type and PHY code.
2475 * Does not touch the hardware. This function must be called prior to any
2476 * other function in the shared code. The txgbe_hw structure should be
2477 * memset to 0 prior to calling this function. The following fields in
2478 * hw structure should be filled in prior to calling this function:
2479 * hw_addr, back, device_id, vendor_id, subsystem_device_id,
2480 * subsystem_vendor_id, and revision_id
2482 s32 txgbe_init_shared_code(struct txgbe_hw *hw)
2486 DEBUGFUNC("txgbe_init_shared_code");
2491 txgbe_set_mac_type(hw);
2493 txgbe_init_ops_dummy(hw);
2494 switch (hw->mac.type) {
2495 case txgbe_mac_raptor:
2496 status = txgbe_init_ops_pf(hw);
2498 case txgbe_mac_raptor_vf:
2499 status = txgbe_init_ops_vf(hw);
2502 status = TXGBE_ERR_DEVICE_NOT_SUPPORTED;
2505 hw->mac.max_link_up_time = TXGBE_LINK_UP_TIME;
2507 hw->bus.set_lan_id(hw);
2513 * txgbe_set_mac_type - Sets MAC type
2514 * @hw: pointer to the HW structure
2516 * This function sets the mac type of the adapter based on the
2517 * vendor ID and device ID stored in the hw structure.
2519 s32 txgbe_set_mac_type(struct txgbe_hw *hw)
2523 DEBUGFUNC("txgbe_set_mac_type");
2525 if (hw->vendor_id != PCI_VENDOR_ID_WANGXUN) {
2526 DEBUGOUT("Unsupported vendor id: %x", hw->vendor_id);
2527 return TXGBE_ERR_DEVICE_NOT_SUPPORTED;
2530 switch (hw->device_id) {
2531 case TXGBE_DEV_ID_SP1000:
2532 case TXGBE_DEV_ID_WX1820:
2533 hw->mac.type = txgbe_mac_raptor;
2535 case TXGBE_DEV_ID_SP1000_VF:
2536 case TXGBE_DEV_ID_WX1820_VF:
2537 hw->phy.media_type = txgbe_media_type_virtual;
2538 hw->mac.type = txgbe_mac_raptor_vf;
2541 err = TXGBE_ERR_DEVICE_NOT_SUPPORTED;
2542 DEBUGOUT("Unsupported device id: %x", hw->device_id);
2546 DEBUGOUT("found mac: %d, returns: %d\n",
2551 void txgbe_init_mac_link_ops(struct txgbe_hw *hw)
2553 struct txgbe_mac_info *mac = &hw->mac;
2555 DEBUGFUNC("txgbe_init_mac_link_ops");
2558 * enable the laser control functions for SFP+ fiber
2559 * and MNG not enabled
2561 if (hw->phy.media_type == txgbe_media_type_fiber &&
2562 !txgbe_mng_enabled(hw)) {
2563 mac->disable_tx_laser =
2564 txgbe_disable_tx_laser_multispeed_fiber;
2565 mac->enable_tx_laser =
2566 txgbe_enable_tx_laser_multispeed_fiber;
2567 mac->flap_tx_laser =
2568 txgbe_flap_tx_laser_multispeed_fiber;
2571 if ((hw->phy.media_type == txgbe_media_type_fiber ||
2572 hw->phy.media_type == txgbe_media_type_fiber_qsfp) &&
2573 hw->phy.multispeed_fiber) {
2574 /* Set up dual speed SFP+ support */
2575 mac->setup_link = txgbe_setup_mac_link_multispeed_fiber;
2576 mac->setup_mac_link = txgbe_setup_mac_link;
2577 mac->set_rate_select_speed = txgbe_set_hard_rate_select_speed;
2578 } else if ((hw->phy.media_type == txgbe_media_type_backplane) &&
2579 (hw->phy.smart_speed == txgbe_smart_speed_auto ||
2580 hw->phy.smart_speed == txgbe_smart_speed_on) &&
2581 !txgbe_verify_lesm_fw_enabled_raptor(hw)) {
2582 mac->setup_link = txgbe_setup_mac_link_smartspeed;
2584 mac->setup_link = txgbe_setup_mac_link;
2589 * txgbe_init_phy_raptor - PHY/SFP specific init
2590 * @hw: pointer to hardware structure
2592 * Initialize any function pointers that were not able to be
2593 * set during init_shared_code because the PHY/SFP type was
2594 * not known. Perform the SFP init if necessary.
2597 s32 txgbe_init_phy_raptor(struct txgbe_hw *hw)
2599 struct txgbe_mac_info *mac = &hw->mac;
2600 struct txgbe_phy_info *phy = &hw->phy;
2603 DEBUGFUNC("txgbe_init_phy_raptor");
2605 if ((hw->device_id & 0xFF) == TXGBE_DEV_ID_QSFP) {
2606 /* Store flag indicating I2C bus access control unit. */
2607 hw->phy.qsfp_shared_i2c_bus = TRUE;
2609 /* Initialize access to QSFP+ I2C bus */
2613 /* Identify the PHY or SFP module */
2614 err = phy->identify(hw);
2615 if (err == TXGBE_ERR_SFP_NOT_SUPPORTED)
2616 goto init_phy_ops_out;
2618 /* Setup function pointers based on detected SFP module and speeds */
2619 txgbe_init_mac_link_ops(hw);
2621 /* If copper media, overwrite with copper function pointers */
2622 if (phy->media_type == txgbe_media_type_copper) {
2623 mac->setup_link = txgbe_setup_copper_link_raptor;
2624 mac->get_link_capabilities =
2625 txgbe_get_copper_link_capabilities;
2628 /* Set necessary function pointers based on PHY type */
2629 switch (hw->phy.type) {
2631 phy->setup_link = txgbe_setup_phy_link_tnx;
2632 phy->check_link = txgbe_check_phy_link_tnx;
2642 s32 txgbe_setup_sfp_modules(struct txgbe_hw *hw)
2646 DEBUGFUNC("txgbe_setup_sfp_modules");
2648 if (hw->phy.sfp_type == txgbe_sfp_type_unknown)
2651 txgbe_init_mac_link_ops(hw);
2653 /* PHY config will finish before releasing the semaphore */
2654 err = hw->mac.acquire_swfw_sync(hw, TXGBE_MNGSEM_SWPHY);
2656 return TXGBE_ERR_SWFW_SYNC;
2658 /* Release the semaphore */
2659 hw->mac.release_swfw_sync(hw, TXGBE_MNGSEM_SWPHY);
2661 /* Delay obtaining semaphore again to allow FW access
2662 * prot_autoc_write uses the semaphore too.
2664 msec_delay(hw->rom.semaphore_delay);
2667 DEBUGOUT("sfp module setup not complete\n");
2668 return TXGBE_ERR_SFP_SETUP_NOT_COMPLETE;
2675 * txgbe_prot_autoc_read_raptor - Hides MAC differences needed for AUTOC read
2676 * @hw: pointer to hardware structure
2677 * @locked: Return the if we locked for this read.
2678 * @value: Value we read from AUTOC
2680 * For this part we need to wrap read-modify-writes with a possible
2681 * FW/SW lock. It is assumed this lock will be freed with the next
2682 * prot_autoc_write_raptor().
2684 s32 txgbe_prot_autoc_read_raptor(struct txgbe_hw *hw, bool *locked, u64 *value)
2687 bool lock_state = false;
2689 /* If LESM is on then we need to hold the SW/FW semaphore. */
2690 if (txgbe_verify_lesm_fw_enabled_raptor(hw)) {
2691 err = hw->mac.acquire_swfw_sync(hw,
2692 TXGBE_MNGSEM_SWPHY);
2694 return TXGBE_ERR_SWFW_SYNC;
2700 *locked = lock_state;
2702 *value = txgbe_autoc_read(hw);
2707 * txgbe_prot_autoc_write_raptor - Hides MAC differences needed for AUTOC write
2708 * @hw: pointer to hardware structure
2709 * @autoc: value to write to AUTOC
2710 * @locked: bool to indicate whether the SW/FW lock was already taken by
2711 * previous prot_autoc_read_raptor.
2713 * This part may need to hold the SW/FW lock around all writes to
2714 * AUTOC. Likewise after a write we need to do a pipeline reset.
2716 s32 txgbe_prot_autoc_write_raptor(struct txgbe_hw *hw, bool locked, u64 autoc)
2720 /* Blocked by MNG FW so bail */
2721 if (txgbe_check_reset_blocked(hw))
2724 /* We only need to get the lock if:
2725 * - We didn't do it already (in the read part of a read-modify-write)
2726 * - LESM is enabled.
2728 if (!locked && txgbe_verify_lesm_fw_enabled_raptor(hw)) {
2729 err = hw->mac.acquire_swfw_sync(hw,
2730 TXGBE_MNGSEM_SWPHY);
2732 return TXGBE_ERR_SWFW_SYNC;
2737 txgbe_autoc_write(hw, autoc);
2738 err = txgbe_reset_pipeline_raptor(hw);
2741 /* Free the SW/FW semaphore as we either grabbed it here or
2742 * already had it when this function was called.
2745 hw->mac.release_swfw_sync(hw, TXGBE_MNGSEM_SWPHY);
2751 * txgbe_init_ops_pf - Inits func ptrs and MAC type
2752 * @hw: pointer to hardware structure
2754 * Initialize the function pointers and assign the MAC type.
2755 * Does not touch the hardware.
2757 s32 txgbe_init_ops_pf(struct txgbe_hw *hw)
2759 struct txgbe_bus_info *bus = &hw->bus;
2760 struct txgbe_mac_info *mac = &hw->mac;
2761 struct txgbe_phy_info *phy = &hw->phy;
2762 struct txgbe_rom_info *rom = &hw->rom;
2763 struct txgbe_mbx_info *mbx = &hw->mbx;
2765 DEBUGFUNC("txgbe_init_ops_pf");
2768 bus->set_lan_id = txgbe_set_lan_id_multi_port;
2771 phy->get_media_type = txgbe_get_media_type_raptor;
2772 phy->identify = txgbe_identify_phy;
2773 phy->init = txgbe_init_phy_raptor;
2774 phy->read_reg = txgbe_read_phy_reg;
2775 phy->write_reg = txgbe_write_phy_reg;
2776 phy->read_reg_mdi = txgbe_read_phy_reg_mdi;
2777 phy->write_reg_mdi = txgbe_write_phy_reg_mdi;
2778 phy->setup_link = txgbe_setup_phy_link;
2779 phy->setup_link_speed = txgbe_setup_phy_link_speed;
2780 phy->get_fw_version = txgbe_get_phy_fw_version;
2781 phy->read_i2c_byte = txgbe_read_i2c_byte;
2782 phy->write_i2c_byte = txgbe_write_i2c_byte;
2783 phy->read_i2c_sff8472 = txgbe_read_i2c_sff8472;
2784 phy->read_i2c_eeprom = txgbe_read_i2c_eeprom;
2785 phy->write_i2c_eeprom = txgbe_write_i2c_eeprom;
2786 phy->identify_sfp = txgbe_identify_module;
2787 phy->read_i2c_byte_unlocked = txgbe_read_i2c_byte_unlocked;
2788 phy->write_i2c_byte_unlocked = txgbe_write_i2c_byte_unlocked;
2789 phy->reset = txgbe_reset_phy;
2792 mac->init_hw = txgbe_init_hw;
2793 mac->start_hw = txgbe_start_hw_raptor;
2794 mac->clear_hw_cntrs = txgbe_clear_hw_cntrs;
2795 mac->enable_rx_dma = txgbe_enable_rx_dma_raptor;
2796 mac->get_mac_addr = txgbe_get_mac_addr;
2797 mac->stop_hw = txgbe_stop_hw;
2798 mac->acquire_swfw_sync = txgbe_acquire_swfw_sync;
2799 mac->release_swfw_sync = txgbe_release_swfw_sync;
2800 mac->reset_hw = txgbe_reset_hw;
2801 mac->update_mc_addr_list = txgbe_update_mc_addr_list;
2803 mac->disable_sec_rx_path = txgbe_disable_sec_rx_path;
2804 mac->enable_sec_rx_path = txgbe_enable_sec_rx_path;
2805 mac->disable_sec_tx_path = txgbe_disable_sec_tx_path;
2806 mac->enable_sec_tx_path = txgbe_enable_sec_tx_path;
2807 mac->get_san_mac_addr = txgbe_get_san_mac_addr;
2808 mac->set_san_mac_addr = txgbe_set_san_mac_addr;
2809 mac->get_device_caps = txgbe_get_device_caps;
2810 mac->get_wwn_prefix = txgbe_get_wwn_prefix;
2811 mac->autoc_read = txgbe_autoc_read;
2812 mac->autoc_write = txgbe_autoc_write;
2813 mac->prot_autoc_read = txgbe_prot_autoc_read_raptor;
2814 mac->prot_autoc_write = txgbe_prot_autoc_write_raptor;
2816 /* RAR, Multicast, VLAN */
2817 mac->set_rar = txgbe_set_rar;
2818 mac->clear_rar = txgbe_clear_rar;
2819 mac->init_rx_addrs = txgbe_init_rx_addrs;
2820 mac->enable_rx = txgbe_enable_rx;
2821 mac->disable_rx = txgbe_disable_rx;
2822 mac->set_vmdq = txgbe_set_vmdq;
2823 mac->clear_vmdq = txgbe_clear_vmdq;
2824 mac->set_vfta = txgbe_set_vfta;
2825 mac->set_vlvf = txgbe_set_vlvf;
2826 mac->clear_vfta = txgbe_clear_vfta;
2827 mac->init_uta_tables = txgbe_init_uta_tables;
2828 mac->setup_sfp = txgbe_setup_sfp_modules;
2829 mac->set_mac_anti_spoofing = txgbe_set_mac_anti_spoofing;
2830 mac->set_ethertype_anti_spoofing = txgbe_set_ethertype_anti_spoofing;
2833 mac->fc_enable = txgbe_fc_enable;
2834 mac->setup_fc = txgbe_setup_fc;
2835 mac->fc_autoneg = txgbe_fc_autoneg;
2838 mac->get_link_capabilities = txgbe_get_link_capabilities_raptor;
2839 mac->check_link = txgbe_check_mac_link;
2840 mac->setup_pba = txgbe_set_pba;
2842 /* Manageability interface */
2843 mac->set_fw_drv_ver = txgbe_hic_set_drv_ver;
2844 mac->get_thermal_sensor_data = txgbe_get_thermal_sensor_data;
2845 mac->init_thermal_sensor_thresh = txgbe_init_thermal_sensor_thresh;
2847 mbx->init_params = txgbe_init_mbx_params_pf;
2848 mbx->read = txgbe_read_mbx_pf;
2849 mbx->write = txgbe_write_mbx_pf;
2850 mbx->check_for_msg = txgbe_check_for_msg_pf;
2851 mbx->check_for_ack = txgbe_check_for_ack_pf;
2852 mbx->check_for_rst = txgbe_check_for_rst_pf;
2855 rom->init_params = txgbe_init_eeprom_params;
2856 rom->read16 = txgbe_ee_read16;
2857 rom->readw_buffer = txgbe_ee_readw_buffer;
2858 rom->readw_sw = txgbe_ee_readw_sw;
2859 rom->read32 = txgbe_ee_read32;
2860 rom->write16 = txgbe_ee_write16;
2861 rom->writew_buffer = txgbe_ee_writew_buffer;
2862 rom->writew_sw = txgbe_ee_writew_sw;
2863 rom->write32 = txgbe_ee_write32;
2864 rom->validate_checksum = txgbe_validate_eeprom_checksum;
2865 rom->update_checksum = txgbe_update_eeprom_checksum;
2866 rom->calc_checksum = txgbe_calc_eeprom_checksum;
2868 mac->mcft_size = TXGBE_RAPTOR_MC_TBL_SIZE;
2869 mac->vft_size = TXGBE_RAPTOR_VFT_TBL_SIZE;
2870 mac->num_rar_entries = TXGBE_RAPTOR_RAR_ENTRIES;
2871 mac->rx_pb_size = TXGBE_RAPTOR_RX_PB_SIZE;
2872 mac->max_rx_queues = TXGBE_RAPTOR_MAX_RX_QUEUES;
2873 mac->max_tx_queues = TXGBE_RAPTOR_MAX_TX_QUEUES;
2879 * txgbe_get_link_capabilities_raptor - Determines link capabilities
2880 * @hw: pointer to hardware structure
2881 * @speed: pointer to link speed
2882 * @autoneg: true when autoneg or autotry is enabled
2884 * Determines the link capabilities by reading the AUTOC register.
2886 s32 txgbe_get_link_capabilities_raptor(struct txgbe_hw *hw,
2893 DEBUGFUNC("txgbe_get_link_capabilities_raptor");
2895 /* Check if 1G SFP module. */
2896 if (hw->phy.sfp_type == txgbe_sfp_type_1g_cu_core0 ||
2897 hw->phy.sfp_type == txgbe_sfp_type_1g_cu_core1 ||
2898 hw->phy.sfp_type == txgbe_sfp_type_1g_lx_core0 ||
2899 hw->phy.sfp_type == txgbe_sfp_type_1g_lx_core1 ||
2900 hw->phy.sfp_type == txgbe_sfp_type_1g_sx_core0 ||
2901 hw->phy.sfp_type == txgbe_sfp_type_1g_sx_core1) {
2902 *speed = TXGBE_LINK_SPEED_1GB_FULL;
2908 * Determine link capabilities based on the stored value of AUTOC,
2909 * which represents EEPROM defaults. If AUTOC value has not
2910 * been stored, use the current register values.
2912 if (hw->mac.orig_link_settings_stored)
2913 autoc = hw->mac.orig_autoc;
2915 autoc = hw->mac.autoc_read(hw);
2917 switch (autoc & TXGBE_AUTOC_LMS_MASK) {
2918 case TXGBE_AUTOC_LMS_1G_LINK_NO_AN:
2919 *speed = TXGBE_LINK_SPEED_1GB_FULL;
2923 case TXGBE_AUTOC_LMS_10G_LINK_NO_AN:
2924 *speed = TXGBE_LINK_SPEED_10GB_FULL;
2928 case TXGBE_AUTOC_LMS_1G_AN:
2929 *speed = TXGBE_LINK_SPEED_1GB_FULL;
2933 case TXGBE_AUTOC_LMS_10G:
2934 *speed = TXGBE_LINK_SPEED_10GB_FULL;
2938 case TXGBE_AUTOC_LMS_KX4_KX_KR:
2939 case TXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN:
2940 *speed = TXGBE_LINK_SPEED_UNKNOWN;
2941 if (autoc & TXGBE_AUTOC_KR_SUPP)
2942 *speed |= TXGBE_LINK_SPEED_10GB_FULL;
2943 if (autoc & TXGBE_AUTOC_KX4_SUPP)
2944 *speed |= TXGBE_LINK_SPEED_10GB_FULL;
2945 if (autoc & TXGBE_AUTOC_KX_SUPP)
2946 *speed |= TXGBE_LINK_SPEED_1GB_FULL;
2950 case TXGBE_AUTOC_LMS_KX4_KX_KR_SGMII:
2951 *speed = TXGBE_LINK_SPEED_100M_FULL;
2952 if (autoc & TXGBE_AUTOC_KR_SUPP)
2953 *speed |= TXGBE_LINK_SPEED_10GB_FULL;
2954 if (autoc & TXGBE_AUTOC_KX4_SUPP)
2955 *speed |= TXGBE_LINK_SPEED_10GB_FULL;
2956 if (autoc & TXGBE_AUTOC_KX_SUPP)
2957 *speed |= TXGBE_LINK_SPEED_1GB_FULL;
2961 case TXGBE_AUTOC_LMS_SGMII_1G_100M:
2962 *speed = TXGBE_LINK_SPEED_1GB_FULL |
2963 TXGBE_LINK_SPEED_100M_FULL |
2964 TXGBE_LINK_SPEED_10M_FULL;
2969 return TXGBE_ERR_LINK_SETUP;
2972 if (hw->phy.multispeed_fiber) {
2973 *speed |= TXGBE_LINK_SPEED_10GB_FULL |
2974 TXGBE_LINK_SPEED_1GB_FULL;
2976 /* QSFP must not enable full auto-negotiation
2977 * Limited autoneg is enabled at 1G
2979 if (hw->phy.media_type == txgbe_media_type_fiber_qsfp)
2989 * txgbe_get_media_type_raptor - Get media type
2990 * @hw: pointer to hardware structure
2992 * Returns the media type (fiber, copper, backplane)
2994 u32 txgbe_get_media_type_raptor(struct txgbe_hw *hw)
2998 DEBUGFUNC("txgbe_get_media_type_raptor");
3000 /* Detect if there is a copper PHY attached. */
3001 switch (hw->phy.type) {
3002 case txgbe_phy_cu_unknown:
3004 media_type = txgbe_media_type_copper;
3010 switch (hw->subsystem_device_id & 0xFF) {
3011 case TXGBE_DEV_ID_KR_KX_KX4:
3012 case TXGBE_DEV_ID_MAC_SGMII:
3013 case TXGBE_DEV_ID_MAC_XAUI:
3014 /* Default device ID is mezzanine card KX/KX4 */
3015 media_type = txgbe_media_type_backplane;
3017 case TXGBE_DEV_ID_SFP:
3018 media_type = txgbe_media_type_fiber;
3020 case TXGBE_DEV_ID_QSFP:
3021 media_type = txgbe_media_type_fiber_qsfp;
3023 case TXGBE_DEV_ID_XAUI:
3024 case TXGBE_DEV_ID_SGMII:
3025 media_type = txgbe_media_type_copper;
3027 case TXGBE_DEV_ID_SFI_XAUI:
3028 if (hw->bus.lan_id == 0)
3029 media_type = txgbe_media_type_fiber;
3031 media_type = txgbe_media_type_copper;
3034 media_type = txgbe_media_type_unknown;
3042 * txgbe_start_mac_link_raptor - Setup MAC link settings
3043 * @hw: pointer to hardware structure
3044 * @autoneg_wait_to_complete: true when waiting for completion is needed
3046 * Configures link settings based on values in the txgbe_hw struct.
3047 * Restarts the link. Performs autonegotiation if needed.
3049 s32 txgbe_start_mac_link_raptor(struct txgbe_hw *hw,
3050 bool autoneg_wait_to_complete)
3053 bool got_lock = false;
3055 DEBUGFUNC("txgbe_start_mac_link_raptor");
3057 UNREFERENCED_PARAMETER(autoneg_wait_to_complete);
3059 /* reset_pipeline requires us to hold this lock as it writes to
3062 if (txgbe_verify_lesm_fw_enabled_raptor(hw)) {
3063 status = hw->mac.acquire_swfw_sync(hw, TXGBE_MNGSEM_SWPHY);
3071 txgbe_reset_pipeline_raptor(hw);
3074 hw->mac.release_swfw_sync(hw, TXGBE_MNGSEM_SWPHY);
3076 /* Add delay to filter out noises during initial link setup */
3084 * txgbe_disable_tx_laser_multispeed_fiber - Disable Tx laser
3085 * @hw: pointer to hardware structure
3087 * The base drivers may require better control over SFP+ module
3088 * PHY states. This includes selectively shutting down the Tx
3089 * laser on the PHY, effectively halting physical link.
3091 void txgbe_disable_tx_laser_multispeed_fiber(struct txgbe_hw *hw)
3093 u32 esdp_reg = rd32(hw, TXGBE_GPIODATA);
3095 /* Blocked by MNG FW so bail */
3096 if (txgbe_check_reset_blocked(hw))
3099 /* Disable Tx laser; allow 100us to go dark per spec */
3100 esdp_reg |= (TXGBE_GPIOBIT_0 | TXGBE_GPIOBIT_1);
3101 wr32(hw, TXGBE_GPIODATA, esdp_reg);
3107 * txgbe_enable_tx_laser_multispeed_fiber - Enable Tx laser
3108 * @hw: pointer to hardware structure
3110 * The base drivers may require better control over SFP+ module
3111 * PHY states. This includes selectively turning on the Tx
3112 * laser on the PHY, effectively starting physical link.
3114 void txgbe_enable_tx_laser_multispeed_fiber(struct txgbe_hw *hw)
3116 u32 esdp_reg = rd32(hw, TXGBE_GPIODATA);
3118 /* Enable Tx laser; allow 100ms to light up */
3119 esdp_reg &= ~(TXGBE_GPIOBIT_0 | TXGBE_GPIOBIT_1);
3120 wr32(hw, TXGBE_GPIODATA, esdp_reg);
3126 * txgbe_flap_tx_laser_multispeed_fiber - Flap Tx laser
3127 * @hw: pointer to hardware structure
3129 * When the driver changes the link speeds that it can support,
3130 * it sets autotry_restart to true to indicate that we need to
3131 * initiate a new autotry session with the link partner. To do
3132 * so, we set the speed then disable and re-enable the Tx laser, to
3133 * alert the link partner that it also needs to restart autotry on its
3134 * end. This is consistent with true clause 37 autoneg, which also
3135 * involves a loss of signal.
3137 void txgbe_flap_tx_laser_multispeed_fiber(struct txgbe_hw *hw)
3139 DEBUGFUNC("txgbe_flap_tx_laser_multispeed_fiber");
3141 /* Blocked by MNG FW so bail */
3142 if (txgbe_check_reset_blocked(hw))
3145 if (hw->mac.autotry_restart) {
3146 txgbe_disable_tx_laser_multispeed_fiber(hw);
3147 txgbe_enable_tx_laser_multispeed_fiber(hw);
3148 hw->mac.autotry_restart = false;
3153 * txgbe_set_hard_rate_select_speed - Set module link speed
3154 * @hw: pointer to hardware structure
3155 * @speed: link speed to set
3157 * Set module link speed via RS0/RS1 rate select pins.
3159 void txgbe_set_hard_rate_select_speed(struct txgbe_hw *hw,
3162 u32 esdp_reg = rd32(hw, TXGBE_GPIODATA);
3165 case TXGBE_LINK_SPEED_10GB_FULL:
3166 esdp_reg |= (TXGBE_GPIOBIT_4 | TXGBE_GPIOBIT_5);
3168 case TXGBE_LINK_SPEED_1GB_FULL:
3169 esdp_reg &= ~(TXGBE_GPIOBIT_4 | TXGBE_GPIOBIT_5);
3172 DEBUGOUT("Invalid fixed module speed\n");
3176 wr32(hw, TXGBE_GPIODATA, esdp_reg);
3181 * txgbe_setup_mac_link_smartspeed - Set MAC link speed using SmartSpeed
3182 * @hw: pointer to hardware structure
3183 * @speed: new link speed
3184 * @autoneg_wait_to_complete: true when waiting for completion is needed
3186 * Implements the Intel SmartSpeed algorithm.
3188 s32 txgbe_setup_mac_link_smartspeed(struct txgbe_hw *hw,
3190 bool autoneg_wait_to_complete)
3193 u32 link_speed = TXGBE_LINK_SPEED_UNKNOWN;
3195 bool link_up = false;
3196 u32 autoc_reg = rd32_epcs(hw, SR_AN_MMD_ADV_REG1);
3198 DEBUGFUNC("txgbe_setup_mac_link_smartspeed");
3200 /* Set autoneg_advertised value based on input link speed */
3201 hw->phy.autoneg_advertised = 0;
3203 if (speed & TXGBE_LINK_SPEED_10GB_FULL)
3204 hw->phy.autoneg_advertised |= TXGBE_LINK_SPEED_10GB_FULL;
3206 if (speed & TXGBE_LINK_SPEED_1GB_FULL)
3207 hw->phy.autoneg_advertised |= TXGBE_LINK_SPEED_1GB_FULL;
3209 if (speed & TXGBE_LINK_SPEED_100M_FULL)
3210 hw->phy.autoneg_advertised |= TXGBE_LINK_SPEED_100M_FULL;
3213 * Implement Intel SmartSpeed algorithm. SmartSpeed will reduce the
3214 * autoneg advertisement if link is unable to be established at the
3215 * highest negotiated rate. This can sometimes happen due to integrity
3216 * issues with the physical media connection.
3219 /* First, try to get link with full advertisement */
3220 hw->phy.smart_speed_active = false;
3221 for (j = 0; j < TXGBE_SMARTSPEED_MAX_RETRIES; j++) {
3222 status = txgbe_setup_mac_link(hw, speed,
3223 autoneg_wait_to_complete);
3228 * Wait for the controller to acquire link. Per IEEE 802.3ap,
3229 * Section 73.10.2, we may have to wait up to 500ms if KR is
3230 * attempted, or 200ms if KX/KX4/BX/BX4 is attempted, per
3231 * Table 9 in the AN MAS.
3233 for (i = 0; i < 5; i++) {
3236 /* If we have link, just jump out */
3237 status = hw->mac.check_link(hw, &link_speed, &link_up,
3248 * We didn't get link. If we advertised KR plus one of KX4/KX
3249 * (or BX4/BX), then disable KR and try again.
3251 if (((autoc_reg & TXGBE_AUTOC_KR_SUPP) == 0) ||
3252 ((autoc_reg & TXGBE_AUTOC_KX_SUPP) == 0 &&
3253 (autoc_reg & TXGBE_AUTOC_KX4_SUPP) == 0))
3256 /* Turn SmartSpeed on to disable KR support */
3257 hw->phy.smart_speed_active = true;
3258 status = txgbe_setup_mac_link(hw, speed,
3259 autoneg_wait_to_complete);
3264 * Wait for the controller to acquire link. 600ms will allow for
3265 * the AN link_fail_inhibit_timer as well for multiple cycles of
3266 * parallel detect, both 10g and 1g. This allows for the maximum
3267 * connect attempts as defined in the AN MAS table 73-7.
3269 for (i = 0; i < 6; i++) {
3272 /* If we have link, just jump out */
3273 status = hw->mac.check_link(hw, &link_speed, &link_up, false);
3281 /* We didn't get link. Turn SmartSpeed back off. */
3282 hw->phy.smart_speed_active = false;
3283 status = txgbe_setup_mac_link(hw, speed,
3284 autoneg_wait_to_complete);
3287 if (link_up && link_speed == TXGBE_LINK_SPEED_1GB_FULL)
3288 DEBUGOUT("Smartspeed has downgraded the link speed "
3289 "from the maximum advertised\n");
3294 * txgbe_setup_mac_link - Set MAC link speed
3295 * @hw: pointer to hardware structure
3296 * @speed: new link speed
3297 * @autoneg_wait_to_complete: true when waiting for completion is needed
3299 * Set the link speed in the AUTOC register and restarts link.
3301 s32 txgbe_setup_mac_link(struct txgbe_hw *hw,
3303 bool autoneg_wait_to_complete)
3305 bool autoneg = false;
3308 u64 autoc = hw->mac.autoc_read(hw);
3309 u64 pma_pmd_10gs = autoc & TXGBE_AUTOC_10GS_PMA_PMD_MASK;
3310 u64 pma_pmd_1g = autoc & TXGBE_AUTOC_1G_PMA_PMD_MASK;
3311 u64 link_mode = autoc & TXGBE_AUTOC_LMS_MASK;
3312 u64 current_autoc = autoc;
3316 u32 link_capabilities = TXGBE_LINK_SPEED_UNKNOWN;
3318 DEBUGFUNC("txgbe_setup_mac_link");
3320 /* Check to see if speed passed in is supported. */
3321 status = hw->mac.get_link_capabilities(hw,
3322 &link_capabilities, &autoneg);
3326 speed &= link_capabilities;
3327 if (speed == TXGBE_LINK_SPEED_UNKNOWN)
3328 return TXGBE_ERR_LINK_SETUP;
3330 /* Use stored value (EEPROM defaults) of AUTOC to find KR/KX4 support*/
3331 if (hw->mac.orig_link_settings_stored)
3332 orig_autoc = hw->mac.orig_autoc;
3336 link_mode = autoc & TXGBE_AUTOC_LMS_MASK;
3337 pma_pmd_1g = autoc & TXGBE_AUTOC_1G_PMA_PMD_MASK;
3339 if (link_mode == TXGBE_AUTOC_LMS_KX4_KX_KR ||
3340 link_mode == TXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
3341 link_mode == TXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
3342 /* Set KX4/KX/KR support according to speed requested */
3343 autoc &= ~(TXGBE_AUTOC_KX_SUPP |
3344 TXGBE_AUTOC_KX4_SUPP |
3345 TXGBE_AUTOC_KR_SUPP);
3346 if (speed & TXGBE_LINK_SPEED_10GB_FULL) {
3347 if (orig_autoc & TXGBE_AUTOC_KX4_SUPP)
3348 autoc |= TXGBE_AUTOC_KX4_SUPP;
3349 if ((orig_autoc & TXGBE_AUTOC_KR_SUPP) &&
3350 !hw->phy.smart_speed_active)
3351 autoc |= TXGBE_AUTOC_KR_SUPP;
3353 if (speed & TXGBE_LINK_SPEED_1GB_FULL)
3354 autoc |= TXGBE_AUTOC_KX_SUPP;
3355 } else if ((pma_pmd_1g == TXGBE_AUTOC_1G_SFI) &&
3356 (link_mode == TXGBE_AUTOC_LMS_1G_LINK_NO_AN ||
3357 link_mode == TXGBE_AUTOC_LMS_1G_AN)) {
3358 /* Switch from 1G SFI to 10G SFI if requested */
3359 if (speed == TXGBE_LINK_SPEED_10GB_FULL &&
3360 pma_pmd_10gs == TXGBE_AUTOC_10GS_SFI) {
3361 autoc &= ~TXGBE_AUTOC_LMS_MASK;
3362 autoc |= TXGBE_AUTOC_LMS_10G;
3364 } else if ((pma_pmd_10gs == TXGBE_AUTOC_10GS_SFI) &&
3365 (link_mode == TXGBE_AUTOC_LMS_10G)) {
3366 /* Switch from 10G SFI to 1G SFI if requested */
3367 if (speed == TXGBE_LINK_SPEED_1GB_FULL &&
3368 pma_pmd_1g == TXGBE_AUTOC_1G_SFI) {
3369 autoc &= ~TXGBE_AUTOC_LMS_MASK;
3370 if (autoneg || hw->phy.type == txgbe_phy_qsfp_intel)
3371 autoc |= TXGBE_AUTOC_LMS_1G_AN;
3373 autoc |= TXGBE_AUTOC_LMS_1G_LINK_NO_AN;
3377 if (autoc == current_autoc)
3380 autoc &= ~TXGBE_AUTOC_SPEED_MASK;
3381 autoc |= TXGBE_AUTOC_SPEED(speed);
3382 autoc |= (autoneg ? TXGBE_AUTOC_AUTONEG : 0);
3385 hw->mac.autoc_write(hw, autoc);
3387 /* Only poll for autoneg to complete if specified to do so */
3388 if (autoneg_wait_to_complete) {
3389 if (link_mode == TXGBE_AUTOC_LMS_KX4_KX_KR ||
3390 link_mode == TXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
3391 link_mode == TXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
3392 links_reg = 0; /*Just in case Autoneg time=0*/
3393 for (i = 0; i < TXGBE_AUTO_NEG_TIME; i++) {
3394 links_reg = rd32(hw, TXGBE_PORTSTAT);
3395 if (links_reg & TXGBE_PORTSTAT_UP)
3399 if (!(links_reg & TXGBE_PORTSTAT_UP)) {
3400 status = TXGBE_ERR_AUTONEG_NOT_COMPLETE;
3401 DEBUGOUT("Autoneg did not complete.\n");
3406 /* Add delay to filter out noises during initial link setup */
3413 * txgbe_setup_copper_link_raptor - Set the PHY autoneg advertised field
3414 * @hw: pointer to hardware structure
3415 * @speed: new link speed
3416 * @autoneg_wait_to_complete: true if waiting is needed to complete
3418 * Restarts link on PHY and MAC based on settings passed in.
3420 static s32 txgbe_setup_copper_link_raptor(struct txgbe_hw *hw,
3422 bool autoneg_wait_to_complete)
3426 DEBUGFUNC("txgbe_setup_copper_link_raptor");
3428 /* Setup the PHY according to input speed */
3429 status = hw->phy.setup_link_speed(hw, speed,
3430 autoneg_wait_to_complete);
3432 txgbe_start_mac_link_raptor(hw, autoneg_wait_to_complete);
3438 txgbe_check_flash_load(struct txgbe_hw *hw, u32 check_bit)
3443 /* if there's flash existing */
3444 if (!(rd32(hw, TXGBE_SPISTAT) & TXGBE_SPISTAT_BPFLASH)) {
3445 /* wait hw load flash done */
3446 for (i = 0; i < 10; i++) {
3447 reg = rd32(hw, TXGBE_ILDRSTAT);
3448 if (!(reg & check_bit)) {
3455 err = TXGBE_ERR_FLASH_LOADING_FAILED;
3461 txgbe_reset_misc(struct txgbe_hw *hw)
3466 wr32(hw, TXGBE_ISBADDRL, hw->isb_dma & 0x00000000FFFFFFFF);
3467 wr32(hw, TXGBE_ISBADDRH, hw->isb_dma >> 32);
3469 value = rd32_epcs(hw, SR_XS_PCS_CTRL2);
3470 if ((value & 0x3) != SR_PCS_CTRL2_TYPE_SEL_X)
3471 hw->link_status = TXGBE_LINK_STATUS_NONE;
3473 /* receive packets that size > 2048 */
3474 wr32m(hw, TXGBE_MACRXCFG,
3475 TXGBE_MACRXCFG_JUMBO, TXGBE_MACRXCFG_JUMBO);
3477 wr32m(hw, TXGBE_FRMSZ, TXGBE_FRMSZ_MAX_MASK,
3478 TXGBE_FRMSZ_MAX(TXGBE_FRAME_SIZE_DFT));
3480 /* clear counters on read */
3481 wr32m(hw, TXGBE_MACCNTCTL,
3482 TXGBE_MACCNTCTL_RC, TXGBE_MACCNTCTL_RC);
3484 wr32m(hw, TXGBE_RXFCCFG,
3485 TXGBE_RXFCCFG_FC, TXGBE_RXFCCFG_FC);
3486 wr32m(hw, TXGBE_TXFCCFG,
3487 TXGBE_TXFCCFG_FC, TXGBE_TXFCCFG_FC);
3489 wr32m(hw, TXGBE_MACRXFLT,
3490 TXGBE_MACRXFLT_PROMISC, TXGBE_MACRXFLT_PROMISC);
3492 wr32m(hw, TXGBE_RSTSTAT,
3493 TXGBE_RSTSTAT_TMRINIT_MASK, TXGBE_RSTSTAT_TMRINIT(30));
3495 /* errata 4: initialize mng flex tbl and wakeup flex tbl*/
3496 wr32(hw, TXGBE_MNGFLEXSEL, 0);
3497 for (i = 0; i < 16; i++) {
3498 wr32(hw, TXGBE_MNGFLEXDWL(i), 0);
3499 wr32(hw, TXGBE_MNGFLEXDWH(i), 0);
3500 wr32(hw, TXGBE_MNGFLEXMSK(i), 0);
3502 wr32(hw, TXGBE_LANFLEXSEL, 0);
3503 for (i = 0; i < 16; i++) {
3504 wr32(hw, TXGBE_LANFLEXDWL(i), 0);
3505 wr32(hw, TXGBE_LANFLEXDWH(i), 0);
3506 wr32(hw, TXGBE_LANFLEXMSK(i), 0);
3509 /* set pause frame dst mac addr */
3510 wr32(hw, TXGBE_RXPBPFCDMACL, 0xC2000001);
3511 wr32(hw, TXGBE_RXPBPFCDMACH, 0x0180);
3513 hw->mac.init_thermal_sensor_thresh(hw);
3515 /* enable mac transmitter */
3516 wr32m(hw, TXGBE_MACTXCFG, TXGBE_MACTXCFG_TXE, TXGBE_MACTXCFG_TXE);
3518 for (i = 0; i < 4; i++)
3519 wr32m(hw, TXGBE_IVAR(i), 0x80808080, 0);
3523 * txgbe_reset_hw - Perform hardware reset
3524 * @hw: pointer to hardware structure
3526 * Resets the hardware by resetting the transmit and receive units, masks
3527 * and clears all interrupts, perform a PHY reset, and perform a link (MAC)
3530 s32 txgbe_reset_hw(struct txgbe_hw *hw)
3535 DEBUGFUNC("txgbe_reset_hw");
3537 /* Call adapter stop to disable tx/rx and clear interrupts */
3538 status = hw->mac.stop_hw(hw);
3542 /* flush pending Tx transactions */
3543 txgbe_clear_tx_pending(hw);
3545 /* Identify PHY and related function pointers */
3546 status = hw->phy.init(hw);
3547 if (status == TXGBE_ERR_SFP_NOT_SUPPORTED)
3550 /* Setup SFP module if there is one present. */
3551 if (hw->phy.sfp_setup_needed) {
3552 status = hw->mac.setup_sfp(hw);
3553 hw->phy.sfp_setup_needed = false;
3555 if (status == TXGBE_ERR_SFP_NOT_SUPPORTED)
3559 if (!hw->phy.reset_disable)
3562 /* remember AUTOC from before we reset */
3563 autoc = hw->mac.autoc_read(hw);
3567 * Issue global reset to the MAC. Needs to be SW reset if link is up.
3568 * If link reset is used when link is up, it might reset the PHY when
3569 * mng is using it. If link is down or the flag to force full link
3570 * reset is set, then perform link reset.
3572 if (txgbe_mng_present(hw)) {
3573 txgbe_hic_reset(hw);
3575 wr32(hw, TXGBE_RST, TXGBE_RST_LAN(hw->bus.lan_id));
3580 txgbe_reset_misc(hw);
3582 if (hw->bus.lan_id == 0) {
3583 status = txgbe_check_flash_load(hw,
3584 TXGBE_ILDRSTAT_SWRST_LAN0);
3586 status = txgbe_check_flash_load(hw,
3587 TXGBE_ILDRSTAT_SWRST_LAN1);
3595 * Double resets are required for recovery from certain error
3596 * conditions. Between resets, it is necessary to stall to
3597 * allow time for any pending HW events to complete.
3599 if (hw->mac.flags & TXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
3600 hw->mac.flags &= ~TXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
3605 * Store the original AUTOC/AUTOC2 values if they have not been
3606 * stored off yet. Otherwise restore the stored original
3607 * values since the reset operation sets back to defaults.
3609 if (!hw->mac.orig_link_settings_stored) {
3610 hw->mac.orig_autoc = hw->mac.autoc_read(hw);
3611 hw->mac.autoc_write(hw, hw->mac.orig_autoc);
3612 hw->mac.orig_link_settings_stored = true;
3614 hw->mac.orig_autoc = autoc;
3617 /* Store the permanent mac address */
3618 hw->mac.get_mac_addr(hw, hw->mac.perm_addr);
3621 * Store MAC address from RAR0, clear receive address registers, and
3622 * clear the multicast table. Also reset num_rar_entries to 128,
3623 * since we modify this value when programming the SAN MAC address.
3625 hw->mac.num_rar_entries = 128;
3626 hw->mac.init_rx_addrs(hw);
3628 /* Store the permanent SAN mac address */
3629 hw->mac.get_san_mac_addr(hw, hw->mac.san_addr);
3631 /* Add the SAN MAC address to the RAR only if it's a valid address */
3632 if (txgbe_validate_mac_addr(hw->mac.san_addr) == 0) {
3633 /* Save the SAN MAC RAR index */
3634 hw->mac.san_mac_rar_index = hw->mac.num_rar_entries - 1;
3636 hw->mac.set_rar(hw, hw->mac.san_mac_rar_index,
3637 hw->mac.san_addr, 0, true);
3639 /* clear VMDq pool/queue selection for this RAR */
3640 hw->mac.clear_vmdq(hw, hw->mac.san_mac_rar_index,
3643 /* Reserve the last RAR for the SAN MAC address */
3644 hw->mac.num_rar_entries--;
3647 /* Store the alternative WWNN/WWPN prefix */
3648 hw->mac.get_wwn_prefix(hw, &hw->mac.wwnn_prefix,
3649 &hw->mac.wwpn_prefix);
3655 * txgbe_fdir_check_cmd_complete - poll to check whether FDIRPICMD is complete
3656 * @hw: pointer to hardware structure
3657 * @fdircmd: current value of FDIRCMD register
3659 static s32 txgbe_fdir_check_cmd_complete(struct txgbe_hw *hw, u32 *fdircmd)
3663 for (i = 0; i < TXGBE_FDIRCMD_CMD_POLL; i++) {
3664 *fdircmd = rd32(hw, TXGBE_FDIRPICMD);
3665 if (!(*fdircmd & TXGBE_FDIRPICMD_OP_MASK))
3670 return TXGBE_ERR_FDIR_CMD_INCOMPLETE;
3674 * txgbe_reinit_fdir_tables - Reinitialize Flow Director tables.
3675 * @hw: pointer to hardware structure
3677 s32 txgbe_reinit_fdir_tables(struct txgbe_hw *hw)
3681 u32 fdirctrl = rd32(hw, TXGBE_FDIRCTL);
3683 fdirctrl &= ~TXGBE_FDIRCTL_INITDONE;
3685 DEBUGFUNC("txgbe_reinit_fdir_tables");
3688 * Before starting reinitialization process,
3689 * FDIRPICMD.OP must be zero.
3691 err = txgbe_fdir_check_cmd_complete(hw, &fdircmd);
3693 DEBUGOUT("Flow Director previous command did not complete, aborting table re-initialization.\n");
3697 wr32(hw, TXGBE_FDIRFREE, 0);
3700 * adapters flow director init flow cannot be restarted,
3701 * Workaround silicon errata by performing the following steps
3702 * before re-writing the FDIRCTL control register with the same value.
3703 * - write 1 to bit 8 of FDIRPICMD register &
3704 * - write 0 to bit 8 of FDIRPICMD register
3706 wr32m(hw, TXGBE_FDIRPICMD, TXGBE_FDIRPICMD_CLR, TXGBE_FDIRPICMD_CLR);
3708 wr32m(hw, TXGBE_FDIRPICMD, TXGBE_FDIRPICMD_CLR, 0);
3711 * Clear FDIR Hash register to clear any leftover hashes
3712 * waiting to be programmed.
3714 wr32(hw, TXGBE_FDIRPIHASH, 0x00);
3717 wr32(hw, TXGBE_FDIRCTL, fdirctrl);
3720 /* Poll init-done after we write FDIRCTL register */
3721 for (i = 0; i < TXGBE_FDIR_INIT_DONE_POLL; i++) {
3722 if (rd32m(hw, TXGBE_FDIRCTL, TXGBE_FDIRCTL_INITDONE))
3726 if (i >= TXGBE_FDIR_INIT_DONE_POLL) {
3727 DEBUGOUT("Flow Director Signature poll time exceeded!\n");
3728 return TXGBE_ERR_FDIR_REINIT_FAILED;
3731 /* Clear FDIR statistics registers (read to clear) */
3732 rd32(hw, TXGBE_FDIRUSED);
3733 rd32(hw, TXGBE_FDIRFAIL);
3734 rd32(hw, TXGBE_FDIRMATCH);
3735 rd32(hw, TXGBE_FDIRMISS);
3736 rd32(hw, TXGBE_FDIRLEN);
3742 * txgbe_start_hw_raptor - Prepare hardware for Tx/Rx
3743 * @hw: pointer to hardware structure
3745 * Starts the hardware using the generic start_hw function
3746 * and the generation start_hw function.
3747 * Then performs revision-specific operations, if any.
3749 s32 txgbe_start_hw_raptor(struct txgbe_hw *hw)
3753 DEBUGFUNC("txgbe_start_hw_raptor");
3755 err = txgbe_start_hw(hw);
3759 err = txgbe_start_hw_gen2(hw);
3763 /* We need to run link autotry after the driver loads */
3764 hw->mac.autotry_restart = true;
3771 * txgbe_enable_rx_dma_raptor - Enable the Rx DMA unit
3772 * @hw: pointer to hardware structure
3773 * @regval: register value to write to RXCTRL
3775 * Enables the Rx DMA unit
3777 s32 txgbe_enable_rx_dma_raptor(struct txgbe_hw *hw, u32 regval)
3779 DEBUGFUNC("txgbe_enable_rx_dma_raptor");
3782 * Workaround silicon errata when enabling the Rx datapath.
3783 * If traffic is incoming before we enable the Rx unit, it could hang
3784 * the Rx DMA unit. Therefore, make sure the security engine is
3785 * completely disabled prior to enabling the Rx unit.
3788 hw->mac.disable_sec_rx_path(hw);
3790 if (regval & TXGBE_PBRXCTL_ENA)
3791 txgbe_enable_rx(hw);
3793 txgbe_disable_rx(hw);
3795 hw->mac.enable_sec_rx_path(hw);
3801 * txgbe_verify_lesm_fw_enabled_raptor - Checks LESM FW module state.
3802 * @hw: pointer to hardware structure
3804 * Returns true if the LESM FW module is present and enabled. Otherwise
3805 * returns false. Smart Speed must be disabled if LESM FW module is enabled.
3807 bool txgbe_verify_lesm_fw_enabled_raptor(struct txgbe_hw *hw)
3809 bool lesm_enabled = false;
3810 u16 fw_offset, fw_lesm_param_offset, fw_lesm_state;
3813 DEBUGFUNC("txgbe_verify_lesm_fw_enabled_raptor");
3815 /* get the offset to the Firmware Module block */
3816 status = hw->rom.read16(hw, TXGBE_FW_PTR, &fw_offset);
3818 if (status != 0 || fw_offset == 0 || fw_offset == 0xFFFF)
3821 /* get the offset to the LESM Parameters block */
3822 status = hw->rom.read16(hw, (fw_offset +
3823 TXGBE_FW_LESM_PARAMETERS_PTR),
3824 &fw_lesm_param_offset);
3827 fw_lesm_param_offset == 0 || fw_lesm_param_offset == 0xFFFF)
3830 /* get the LESM state word */
3831 status = hw->rom.read16(hw, (fw_lesm_param_offset +
3832 TXGBE_FW_LESM_STATE_1),
3835 if (status == 0 && (fw_lesm_state & TXGBE_FW_LESM_STATE_ENABLED))
3836 lesm_enabled = true;
3839 lesm_enabled = false;
3840 return lesm_enabled;
3844 * txgbe_reset_pipeline_raptor - perform pipeline reset
3846 * @hw: pointer to hardware structure
3848 * Reset pipeline by asserting Restart_AN together with LMS change to ensure
3849 * full pipeline reset. This function assumes the SW/FW lock is held.
3851 s32 txgbe_reset_pipeline_raptor(struct txgbe_hw *hw)
3856 autoc = hw->mac.autoc_read(hw);
3858 /* Enable link if disabled in NVM */
3859 if (autoc & TXGBE_AUTOC_LINK_DIA_MASK)
3860 autoc &= ~TXGBE_AUTOC_LINK_DIA_MASK;
3862 autoc |= TXGBE_AUTOC_AN_RESTART;
3863 /* Write AUTOC register with toggled LMS[2] bit and Restart_AN */
3864 hw->mac.autoc_write(hw, autoc ^ TXGBE_AUTOC_LMS_AN);
3866 /* Write AUTOC register with original LMS field and Restart_AN */
3867 hw->mac.autoc_write(hw, autoc);