1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2015-2020
5 #include "txgbe_type.h"
10 #include "txgbe_eeprom.h"
11 #include "txgbe_mng.h"
14 #define TXGBE_RAPTOR_MAX_TX_QUEUES 128
15 #define TXGBE_RAPTOR_MAX_RX_QUEUES 128
16 #define TXGBE_RAPTOR_RAR_ENTRIES 128
17 #define TXGBE_RAPTOR_MC_TBL_SIZE 128
18 #define TXGBE_RAPTOR_VFT_TBL_SIZE 128
19 #define TXGBE_RAPTOR_RX_PB_SIZE 512 /*KB*/
21 static s32 txgbe_setup_copper_link_raptor(struct txgbe_hw *hw,
23 bool autoneg_wait_to_complete);
25 static s32 txgbe_mta_vector(struct txgbe_hw *hw, u8 *mc_addr);
26 static s32 txgbe_get_san_mac_addr_offset(struct txgbe_hw *hw,
30 * txgbe_device_supports_autoneg_fc - Check if device supports autonegotiation
32 * @hw: pointer to hardware structure
34 * This function returns true if the device supports flow control
35 * autonegotiation, and false if it does not.
38 bool txgbe_device_supports_autoneg_fc(struct txgbe_hw *hw)
40 bool supported = false;
44 DEBUGFUNC("txgbe_device_supports_autoneg_fc");
46 switch (hw->phy.media_type) {
47 case txgbe_media_type_fiber_qsfp:
48 case txgbe_media_type_fiber:
49 hw->mac.check_link(hw, &speed, &link_up, false);
50 /* if link is down, assume supported */
52 supported = speed == TXGBE_LINK_SPEED_1GB_FULL ?
58 case txgbe_media_type_backplane:
61 case txgbe_media_type_copper:
62 /* only some copper devices support flow control autoneg */
63 switch (hw->device_id) {
64 case TXGBE_DEV_ID_RAPTOR_XAUI:
65 case TXGBE_DEV_ID_RAPTOR_SGMII:
76 DEBUGOUT("Device %x does not support flow control autoneg",
82 * txgbe_setup_fc - Set up flow control
83 * @hw: pointer to hardware structure
85 * Called at init time to set up flow control.
87 s32 txgbe_setup_fc(struct txgbe_hw *hw)
96 DEBUGFUNC("txgbe_setup_fc");
98 /* Validate the requested mode */
99 if (hw->fc.strict_ieee && hw->fc.requested_mode == txgbe_fc_rx_pause) {
100 DEBUGOUT("txgbe_fc_rx_pause not valid in strict IEEE mode\n");
101 err = TXGBE_ERR_INVALID_LINK_SETTINGS;
106 * 10gig parts do not have a word in the EEPROM to determine the
107 * default flow control setting, so we explicitly set it to full.
109 if (hw->fc.requested_mode == txgbe_fc_default)
110 hw->fc.requested_mode = txgbe_fc_full;
113 * Set up the 1G and 10G flow control advertisement registers so the
114 * HW will be able to do fc autoneg once the cable is plugged in. If
115 * we link at 10G, the 1G advertisement is harmless and vice versa.
117 switch (hw->phy.media_type) {
118 case txgbe_media_type_backplane:
119 /* some MAC's need RMW protection on AUTOC */
120 err = hw->mac.prot_autoc_read(hw, &locked, ®_bp);
124 /* fall through - only backplane uses autoc */
125 case txgbe_media_type_fiber_qsfp:
126 case txgbe_media_type_fiber:
127 case txgbe_media_type_copper:
128 hw->phy.read_reg(hw, TXGBE_MD_AUTO_NEG_ADVT,
129 TXGBE_MD_DEV_AUTO_NEG, ®_cu);
136 * The possible values of fc.requested_mode are:
137 * 0: Flow control is completely disabled
138 * 1: Rx flow control is enabled (we can receive pause frames,
139 * but not send pause frames).
140 * 2: Tx flow control is enabled (we can send pause frames but
141 * we do not support receiving pause frames).
142 * 3: Both Rx and Tx flow control (symmetric) are enabled.
145 switch (hw->fc.requested_mode) {
147 /* Flow control completely disabled by software override. */
148 reg &= ~(SR_MII_MMD_AN_ADV_PAUSE_SYM |
149 SR_MII_MMD_AN_ADV_PAUSE_ASM);
150 if (hw->phy.media_type == txgbe_media_type_backplane)
151 reg_bp &= ~(TXGBE_AUTOC_SYM_PAUSE |
152 TXGBE_AUTOC_ASM_PAUSE);
153 else if (hw->phy.media_type == txgbe_media_type_copper)
154 reg_cu &= ~(TXGBE_TAF_SYM_PAUSE | TXGBE_TAF_ASM_PAUSE);
156 case txgbe_fc_tx_pause:
158 * Tx Flow control is enabled, and Rx Flow control is
159 * disabled by software override.
161 reg |= SR_MII_MMD_AN_ADV_PAUSE_ASM;
162 reg &= ~SR_MII_MMD_AN_ADV_PAUSE_SYM;
163 if (hw->phy.media_type == txgbe_media_type_backplane) {
164 reg_bp |= TXGBE_AUTOC_ASM_PAUSE;
165 reg_bp &= ~TXGBE_AUTOC_SYM_PAUSE;
166 } else if (hw->phy.media_type == txgbe_media_type_copper) {
167 reg_cu |= TXGBE_TAF_ASM_PAUSE;
168 reg_cu &= ~TXGBE_TAF_SYM_PAUSE;
170 reg |= SR_MII_MMD_AN_ADV_PAUSE_ASM;
171 reg_bp |= SR_AN_MMD_ADV_REG1_PAUSE_ASM;
173 case txgbe_fc_rx_pause:
175 * Rx Flow control is enabled and Tx Flow control is
176 * disabled by software override. Since there really
177 * isn't a way to advertise that we are capable of RX
178 * Pause ONLY, we will advertise that we support both
179 * symmetric and asymmetric Rx PAUSE, as such we fall
180 * through to the fc_full statement. Later, we will
181 * disable the adapter's ability to send PAUSE frames.
184 /* Flow control (both Rx and Tx) is enabled by SW override. */
185 reg |= SR_MII_MMD_AN_ADV_PAUSE_SYM |
186 SR_MII_MMD_AN_ADV_PAUSE_ASM;
187 if (hw->phy.media_type == txgbe_media_type_backplane)
188 reg_bp |= TXGBE_AUTOC_SYM_PAUSE |
189 TXGBE_AUTOC_ASM_PAUSE;
190 else if (hw->phy.media_type == txgbe_media_type_copper)
191 reg_cu |= TXGBE_TAF_SYM_PAUSE | TXGBE_TAF_ASM_PAUSE;
192 reg |= SR_MII_MMD_AN_ADV_PAUSE_SYM |
193 SR_MII_MMD_AN_ADV_PAUSE_ASM;
194 reg_bp |= SR_AN_MMD_ADV_REG1_PAUSE_SYM |
195 SR_AN_MMD_ADV_REG1_PAUSE_ASM;
198 DEBUGOUT("Flow control param set incorrectly\n");
199 err = TXGBE_ERR_CONFIG;
204 * Enable auto-negotiation between the MAC & PHY;
205 * the MAC will advertise clause 37 flow control.
207 value = rd32_epcs(hw, SR_MII_MMD_AN_ADV);
208 value = (value & ~(SR_MII_MMD_AN_ADV_PAUSE_ASM |
209 SR_MII_MMD_AN_ADV_PAUSE_SYM)) | reg;
210 wr32_epcs(hw, SR_MII_MMD_AN_ADV, value);
213 * AUTOC restart handles negotiation of 1G and 10G on backplane
214 * and copper. There is no need to set the PCS1GCTL register.
217 if (hw->phy.media_type == txgbe_media_type_backplane) {
218 value = rd32_epcs(hw, SR_AN_MMD_ADV_REG1);
219 value = (value & ~(SR_AN_MMD_ADV_REG1_PAUSE_ASM |
220 SR_AN_MMD_ADV_REG1_PAUSE_SYM)) |
222 wr32_epcs(hw, SR_AN_MMD_ADV_REG1, value);
223 } else if ((hw->phy.media_type == txgbe_media_type_copper) &&
224 (txgbe_device_supports_autoneg_fc(hw))) {
225 hw->phy.write_reg(hw, TXGBE_MD_AUTO_NEG_ADVT,
226 TXGBE_MD_DEV_AUTO_NEG, reg_cu);
229 DEBUGOUT("Set up FC; reg = 0x%08X\n", reg);
235 * txgbe_start_hw - Prepare hardware for Tx/Rx
236 * @hw: pointer to hardware structure
238 * Starts the hardware by filling the bus info structure and media type, clears
239 * all on chip counters, initializes receive address registers, multicast
240 * table, VLAN filter table, calls routine to set up link and flow control
241 * settings, and leaves transmit and receive units disabled and uninitialized
243 s32 txgbe_start_hw(struct txgbe_hw *hw)
248 DEBUGFUNC("txgbe_start_hw");
250 /* Set the media type */
251 hw->phy.media_type = hw->phy.get_media_type(hw);
253 /* Clear the VLAN filter table */
254 hw->mac.clear_vfta(hw);
256 /* Clear statistics registers */
257 hw->mac.clear_hw_cntrs(hw);
259 /* Setup flow control */
260 err = txgbe_setup_fc(hw);
261 if (err != 0 && err != TXGBE_NOT_IMPLEMENTED) {
262 DEBUGOUT("Flow control setup failed, returning %d\n", err);
266 /* Cache bit indicating need for crosstalk fix */
267 switch (hw->mac.type) {
268 case txgbe_mac_raptor:
269 hw->mac.get_device_caps(hw, &device_caps);
270 if (device_caps & TXGBE_DEVICE_CAPS_NO_CROSSTALK_WR)
271 hw->need_crosstalk_fix = false;
273 hw->need_crosstalk_fix = true;
276 hw->need_crosstalk_fix = false;
280 /* Clear adapter stopped flag */
281 hw->adapter_stopped = false;
287 * txgbe_start_hw_gen2 - Init sequence for common device family
288 * @hw: pointer to hw structure
290 * Performs the init sequence common to the second generation
293 s32 txgbe_start_hw_gen2(struct txgbe_hw *hw)
297 /* Clear the rate limiters */
298 for (i = 0; i < hw->mac.max_tx_queues; i++) {
299 wr32(hw, TXGBE_ARBPOOLIDX, i);
300 wr32(hw, TXGBE_ARBTXRATE, 0);
304 /* We need to run link autotry after the driver loads */
305 hw->mac.autotry_restart = true;
311 * txgbe_init_hw - Generic hardware initialization
312 * @hw: pointer to hardware structure
314 * Initialize the hardware by resetting the hardware, filling the bus info
315 * structure and media type, clears all on chip counters, initializes receive
316 * address registers, multicast table, VLAN filter table, calls routine to set
317 * up link and flow control settings, and leaves transmit and receive units
318 * disabled and uninitialized
320 s32 txgbe_init_hw(struct txgbe_hw *hw)
324 DEBUGFUNC("txgbe_init_hw");
326 /* Reset the hardware */
327 status = hw->mac.reset_hw(hw);
328 if (status == 0 || status == TXGBE_ERR_SFP_NOT_PRESENT) {
330 status = hw->mac.start_hw(hw);
334 DEBUGOUT("Failed to initialize HW, STATUS = %d\n", status);
340 * txgbe_clear_hw_cntrs - Generic clear hardware counters
341 * @hw: pointer to hardware structure
343 * Clears all hardware statistics counters by reading them from the hardware
344 * Statistics counters are clear on read.
346 s32 txgbe_clear_hw_cntrs(struct txgbe_hw *hw)
350 DEBUGFUNC("txgbe_clear_hw_cntrs");
353 /* don't write clear queue stats */
354 for (i = 0; i < TXGBE_MAX_QP; i++) {
355 hw->qp_last[i].rx_qp_packets = 0;
356 hw->qp_last[i].tx_qp_packets = 0;
357 hw->qp_last[i].rx_qp_bytes = 0;
358 hw->qp_last[i].tx_qp_bytes = 0;
359 hw->qp_last[i].rx_qp_mc_packets = 0;
363 for (i = 0; i < TXGBE_MAX_UP; i++) {
364 rd32(hw, TXGBE_PBRXUPXON(i));
365 rd32(hw, TXGBE_PBRXUPXOFF(i));
366 rd32(hw, TXGBE_PBTXUPXON(i));
367 rd32(hw, TXGBE_PBTXUPXOFF(i));
368 rd32(hw, TXGBE_PBTXUPOFF(i));
370 rd32(hw, TXGBE_PBRXMISS(i));
372 rd32(hw, TXGBE_PBRXLNKXON);
373 rd32(hw, TXGBE_PBRXLNKXOFF);
374 rd32(hw, TXGBE_PBTXLNKXON);
375 rd32(hw, TXGBE_PBTXLNKXOFF);
378 rd32(hw, TXGBE_DMARXPKT);
379 rd32(hw, TXGBE_DMATXPKT);
381 rd64(hw, TXGBE_DMARXOCTL);
382 rd64(hw, TXGBE_DMATXOCTL);
385 rd64(hw, TXGBE_MACRXERRCRCL);
386 rd64(hw, TXGBE_MACRXMPKTL);
387 rd64(hw, TXGBE_MACTXMPKTL);
389 rd64(hw, TXGBE_MACRXPKTL);
390 rd64(hw, TXGBE_MACTXPKTL);
391 rd64(hw, TXGBE_MACRXGBOCTL);
393 rd64(hw, TXGBE_MACRXOCTL);
394 rd32(hw, TXGBE_MACTXOCTL);
396 rd64(hw, TXGBE_MACRX1TO64L);
397 rd64(hw, TXGBE_MACRX65TO127L);
398 rd64(hw, TXGBE_MACRX128TO255L);
399 rd64(hw, TXGBE_MACRX256TO511L);
400 rd64(hw, TXGBE_MACRX512TO1023L);
401 rd64(hw, TXGBE_MACRX1024TOMAXL);
402 rd64(hw, TXGBE_MACTX1TO64L);
403 rd64(hw, TXGBE_MACTX65TO127L);
404 rd64(hw, TXGBE_MACTX128TO255L);
405 rd64(hw, TXGBE_MACTX256TO511L);
406 rd64(hw, TXGBE_MACTX512TO1023L);
407 rd64(hw, TXGBE_MACTX1024TOMAXL);
409 rd64(hw, TXGBE_MACRXERRLENL);
410 rd32(hw, TXGBE_MACRXOVERSIZE);
411 rd32(hw, TXGBE_MACRXJABBER);
414 rd32(hw, TXGBE_FCOECRC);
415 rd32(hw, TXGBE_FCOELAST);
416 rd32(hw, TXGBE_FCOERPDC);
417 rd32(hw, TXGBE_FCOEPRC);
418 rd32(hw, TXGBE_FCOEPTC);
419 rd32(hw, TXGBE_FCOEDWRC);
420 rd32(hw, TXGBE_FCOEDWTC);
422 /* Flow Director Stats */
423 rd32(hw, TXGBE_FDIRMATCH);
424 rd32(hw, TXGBE_FDIRMISS);
425 rd32(hw, TXGBE_FDIRUSED);
426 rd32(hw, TXGBE_FDIRUSED);
427 rd32(hw, TXGBE_FDIRFAIL);
428 rd32(hw, TXGBE_FDIRFAIL);
431 rd32(hw, TXGBE_LSECTX_UTPKT);
432 rd32(hw, TXGBE_LSECTX_ENCPKT);
433 rd32(hw, TXGBE_LSECTX_PROTPKT);
434 rd32(hw, TXGBE_LSECTX_ENCOCT);
435 rd32(hw, TXGBE_LSECTX_PROTOCT);
436 rd32(hw, TXGBE_LSECRX_UTPKT);
437 rd32(hw, TXGBE_LSECRX_BTPKT);
438 rd32(hw, TXGBE_LSECRX_NOSCIPKT);
439 rd32(hw, TXGBE_LSECRX_UNSCIPKT);
440 rd32(hw, TXGBE_LSECRX_DECOCT);
441 rd32(hw, TXGBE_LSECRX_VLDOCT);
442 rd32(hw, TXGBE_LSECRX_UNCHKPKT);
443 rd32(hw, TXGBE_LSECRX_DLYPKT);
444 rd32(hw, TXGBE_LSECRX_LATEPKT);
445 for (i = 0; i < 2; i++) {
446 rd32(hw, TXGBE_LSECRX_OKPKT(i));
447 rd32(hw, TXGBE_LSECRX_INVPKT(i));
448 rd32(hw, TXGBE_LSECRX_BADPKT(i));
450 rd32(hw, TXGBE_LSECRX_INVSAPKT);
451 rd32(hw, TXGBE_LSECRX_BADSAPKT);
457 * txgbe_get_mac_addr - Generic get MAC address
458 * @hw: pointer to hardware structure
459 * @mac_addr: Adapter MAC address
461 * Reads the adapter's MAC address from first Receive Address Register (RAR0)
462 * A reset of the adapter must be performed prior to calling this function
463 * in order for the MAC address to have been loaded from the EEPROM into RAR0
465 s32 txgbe_get_mac_addr(struct txgbe_hw *hw, u8 *mac_addr)
471 DEBUGFUNC("txgbe_get_mac_addr");
473 wr32(hw, TXGBE_ETHADDRIDX, 0);
474 rar_high = rd32(hw, TXGBE_ETHADDRH);
475 rar_low = rd32(hw, TXGBE_ETHADDRL);
477 for (i = 0; i < 2; i++)
478 mac_addr[i] = (u8)(rar_high >> (1 - i) * 8);
480 for (i = 0; i < 4; i++)
481 mac_addr[i + 2] = (u8)(rar_low >> (3 - i) * 8);
487 * txgbe_set_lan_id_multi_port - Set LAN id for PCIe multiple port devices
488 * @hw: pointer to the HW structure
490 * Determines the LAN function id by reading memory-mapped registers and swaps
491 * the port value if requested, and set MAC instance for devices.
493 void txgbe_set_lan_id_multi_port(struct txgbe_hw *hw)
495 struct txgbe_bus_info *bus = &hw->bus;
498 DEBUGFUNC("txgbe_set_lan_id_multi_port_pcie");
500 reg = rd32(hw, TXGBE_PORTSTAT);
501 bus->lan_id = TXGBE_PORTSTAT_ID(reg);
503 /* check for single port */
504 reg = rd32(hw, TXGBE_PWR);
505 if (TXGBE_PWR_LANID(reg) == TXGBE_PWR_LANID_SWAP)
508 bus->func = bus->lan_id;
512 * txgbe_stop_hw - Generic stop Tx/Rx units
513 * @hw: pointer to hardware structure
515 * Sets the adapter_stopped flag within txgbe_hw struct. Clears interrupts,
516 * disables transmit and receive units. The adapter_stopped flag is used by
517 * the shared code and drivers to determine if the adapter is in a stopped
518 * state and should not touch the hardware.
520 s32 txgbe_stop_hw(struct txgbe_hw *hw)
525 DEBUGFUNC("txgbe_stop_hw");
528 * Set the adapter_stopped flag so other driver functions stop touching
531 hw->adapter_stopped = true;
533 /* Disable the receive unit */
534 txgbe_disable_rx(hw);
536 /* Clear interrupt mask to stop interrupts from being generated */
537 wr32(hw, TXGBE_IENMISC, 0);
538 wr32(hw, TXGBE_IMS(0), TXGBE_IMS_MASK);
539 wr32(hw, TXGBE_IMS(1), TXGBE_IMS_MASK);
541 /* Clear any pending interrupts, flush previous writes */
542 wr32(hw, TXGBE_ICRMISC, TXGBE_ICRMISC_MASK);
543 wr32(hw, TXGBE_ICR(0), TXGBE_ICR_MASK);
544 wr32(hw, TXGBE_ICR(1), TXGBE_ICR_MASK);
546 /* Disable the transmit unit. Each queue must be disabled. */
547 for (i = 0; i < hw->mac.max_tx_queues; i++)
548 wr32(hw, TXGBE_TXCFG(i), TXGBE_TXCFG_FLUSH);
550 /* Disable the receive unit by stopping each queue */
551 for (i = 0; i < hw->mac.max_rx_queues; i++) {
552 reg_val = rd32(hw, TXGBE_RXCFG(i));
553 reg_val &= ~TXGBE_RXCFG_ENA;
554 wr32(hw, TXGBE_RXCFG(i), reg_val);
557 /* flush all queues disables */
565 * txgbe_led_on - Turns on the software controllable LEDs.
566 * @hw: pointer to hardware structure
567 * @index: led number to turn on
569 s32 txgbe_led_on(struct txgbe_hw *hw, u32 index)
571 u32 led_reg = rd32(hw, TXGBE_LEDCTL);
573 DEBUGFUNC("txgbe_led_on");
576 return TXGBE_ERR_PARAM;
578 /* To turn on the LED, set mode to ON. */
579 led_reg |= TXGBE_LEDCTL_SEL(index);
580 led_reg |= TXGBE_LEDCTL_ORD(index);
581 wr32(hw, TXGBE_LEDCTL, led_reg);
588 * txgbe_led_off - Turns off the software controllable LEDs.
589 * @hw: pointer to hardware structure
590 * @index: led number to turn off
592 s32 txgbe_led_off(struct txgbe_hw *hw, u32 index)
594 u32 led_reg = rd32(hw, TXGBE_LEDCTL);
596 DEBUGFUNC("txgbe_led_off");
599 return TXGBE_ERR_PARAM;
601 /* To turn off the LED, set mode to OFF. */
602 led_reg &= ~(TXGBE_LEDCTL_SEL(index));
603 led_reg &= ~(TXGBE_LEDCTL_ORD(index));
604 wr32(hw, TXGBE_LEDCTL, led_reg);
611 * txgbe_validate_mac_addr - Validate MAC address
612 * @mac_addr: pointer to MAC address.
614 * Tests a MAC address to ensure it is a valid Individual Address.
616 s32 txgbe_validate_mac_addr(u8 *mac_addr)
620 DEBUGFUNC("txgbe_validate_mac_addr");
622 /* Make sure it is not a multicast address */
623 if (TXGBE_IS_MULTICAST(mac_addr)) {
624 status = TXGBE_ERR_INVALID_MAC_ADDR;
625 /* Not a broadcast address */
626 } else if (TXGBE_IS_BROADCAST(mac_addr)) {
627 status = TXGBE_ERR_INVALID_MAC_ADDR;
628 /* Reject the zero address */
629 } else if (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 &&
630 mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0) {
631 status = TXGBE_ERR_INVALID_MAC_ADDR;
637 * txgbe_set_rar - Set Rx address register
638 * @hw: pointer to hardware structure
639 * @index: Receive address register to write
640 * @addr: Address to put into receive address register
641 * @vmdq: VMDq "set" or "pool" index
642 * @enable_addr: set flag that address is active
644 * Puts an ethernet address into a receive address register.
646 s32 txgbe_set_rar(struct txgbe_hw *hw, u32 index, u8 *addr, u32 vmdq,
649 u32 rar_low, rar_high;
650 u32 rar_entries = hw->mac.num_rar_entries;
652 DEBUGFUNC("txgbe_set_rar");
654 /* Make sure we are using a valid rar index range */
655 if (index >= rar_entries) {
656 DEBUGOUT("RAR index %d is out of range.\n", index);
657 return TXGBE_ERR_INVALID_ARGUMENT;
660 /* setup VMDq pool selection before this RAR gets enabled */
661 hw->mac.set_vmdq(hw, index, vmdq);
664 * HW expects these in little endian so we reverse the byte
665 * order from network order (big endian) to little endian
667 rar_low = TXGBE_ETHADDRL_AD0(addr[5]) |
668 TXGBE_ETHADDRL_AD1(addr[4]) |
669 TXGBE_ETHADDRL_AD2(addr[3]) |
670 TXGBE_ETHADDRL_AD3(addr[2]);
672 * Some parts put the VMDq setting in the extra RAH bits,
673 * so save everything except the lower 16 bits that hold part
674 * of the address and the address valid bit.
676 rar_high = rd32(hw, TXGBE_ETHADDRH);
677 rar_high &= ~TXGBE_ETHADDRH_AD_MASK;
678 rar_high |= (TXGBE_ETHADDRH_AD4(addr[1]) |
679 TXGBE_ETHADDRH_AD5(addr[0]));
681 rar_high &= ~TXGBE_ETHADDRH_VLD;
682 if (enable_addr != 0)
683 rar_high |= TXGBE_ETHADDRH_VLD;
685 wr32(hw, TXGBE_ETHADDRIDX, index);
686 wr32(hw, TXGBE_ETHADDRL, rar_low);
687 wr32(hw, TXGBE_ETHADDRH, rar_high);
693 * txgbe_clear_rar - Remove Rx address register
694 * @hw: pointer to hardware structure
695 * @index: Receive address register to write
697 * Clears an ethernet address from a receive address register.
699 s32 txgbe_clear_rar(struct txgbe_hw *hw, u32 index)
702 u32 rar_entries = hw->mac.num_rar_entries;
704 DEBUGFUNC("txgbe_clear_rar");
706 /* Make sure we are using a valid rar index range */
707 if (index >= rar_entries) {
708 DEBUGOUT("RAR index %d is out of range.\n", index);
709 return TXGBE_ERR_INVALID_ARGUMENT;
713 * Some parts put the VMDq setting in the extra RAH bits,
714 * so save everything except the lower 16 bits that hold part
715 * of the address and the address valid bit.
717 wr32(hw, TXGBE_ETHADDRIDX, index);
718 rar_high = rd32(hw, TXGBE_ETHADDRH);
719 rar_high &= ~(TXGBE_ETHADDRH_AD_MASK | TXGBE_ETHADDRH_VLD);
721 wr32(hw, TXGBE_ETHADDRL, 0);
722 wr32(hw, TXGBE_ETHADDRH, rar_high);
724 /* clear VMDq pool/queue selection for this RAR */
725 hw->mac.clear_vmdq(hw, index, BIT_MASK32);
731 * txgbe_init_rx_addrs - Initializes receive address filters.
732 * @hw: pointer to hardware structure
734 * Places the MAC address in receive address register 0 and clears the rest
735 * of the receive address registers. Clears the multicast table. Assumes
736 * the receiver is in reset when the routine is called.
738 s32 txgbe_init_rx_addrs(struct txgbe_hw *hw)
742 u32 rar_entries = hw->mac.num_rar_entries;
744 DEBUGFUNC("txgbe_init_rx_addrs");
747 * If the current mac address is valid, assume it is a software override
748 * to the permanent address.
749 * Otherwise, use the permanent address from the eeprom.
751 if (txgbe_validate_mac_addr(hw->mac.addr) ==
752 TXGBE_ERR_INVALID_MAC_ADDR) {
753 /* Get the MAC address from the RAR0 for later reference */
754 hw->mac.get_mac_addr(hw, hw->mac.addr);
756 DEBUGOUT(" Keeping Current RAR0 Addr =%.2X %.2X %.2X ",
757 hw->mac.addr[0], hw->mac.addr[1],
759 DEBUGOUT("%.2X %.2X %.2X\n", hw->mac.addr[3],
760 hw->mac.addr[4], hw->mac.addr[5]);
762 /* Setup the receive address. */
763 DEBUGOUT("Overriding MAC Address in RAR[0]\n");
764 DEBUGOUT(" New MAC Addr =%.2X %.2X %.2X ",
765 hw->mac.addr[0], hw->mac.addr[1],
767 DEBUGOUT("%.2X %.2X %.2X\n", hw->mac.addr[3],
768 hw->mac.addr[4], hw->mac.addr[5]);
770 hw->mac.set_rar(hw, 0, hw->mac.addr, 0, true);
773 /* clear VMDq pool/queue selection for RAR 0 */
774 hw->mac.clear_vmdq(hw, 0, BIT_MASK32);
776 hw->addr_ctrl.overflow_promisc = 0;
778 hw->addr_ctrl.rar_used_count = 1;
780 /* Zero out the other receive addresses. */
781 DEBUGOUT("Clearing RAR[1-%d]\n", rar_entries - 1);
782 for (i = 1; i < rar_entries; i++) {
783 wr32(hw, TXGBE_ETHADDRIDX, i);
784 wr32(hw, TXGBE_ETHADDRL, 0);
785 wr32(hw, TXGBE_ETHADDRH, 0);
789 hw->addr_ctrl.mta_in_use = 0;
790 psrctl = rd32(hw, TXGBE_PSRCTL);
791 psrctl &= ~(TXGBE_PSRCTL_ADHF12_MASK | TXGBE_PSRCTL_MCHFENA);
792 psrctl |= TXGBE_PSRCTL_ADHF12(hw->mac.mc_filter_type);
793 wr32(hw, TXGBE_PSRCTL, psrctl);
795 DEBUGOUT(" Clearing MTA\n");
796 for (i = 0; i < hw->mac.mcft_size; i++)
797 wr32(hw, TXGBE_MCADDRTBL(i), 0);
799 txgbe_init_uta_tables(hw);
805 * txgbe_mta_vector - Determines bit-vector in multicast table to set
806 * @hw: pointer to hardware structure
807 * @mc_addr: the multicast address
809 * Extracts the 12 bits, from a multicast address, to determine which
810 * bit-vector to set in the multicast table. The hardware uses 12 bits, from
811 * incoming rx multicast addresses, to determine the bit-vector to check in
812 * the MTA. Which of the 4 combination, of 12-bits, the hardware uses is set
813 * by the MO field of the PSRCTRL. The MO field is set during initialization
816 static s32 txgbe_mta_vector(struct txgbe_hw *hw, u8 *mc_addr)
820 DEBUGFUNC("txgbe_mta_vector");
822 switch (hw->mac.mc_filter_type) {
823 case 0: /* use bits [47:36] of the address */
824 vector = ((mc_addr[4] >> 4) | (((u16)mc_addr[5]) << 4));
826 case 1: /* use bits [46:35] of the address */
827 vector = ((mc_addr[4] >> 3) | (((u16)mc_addr[5]) << 5));
829 case 2: /* use bits [45:34] of the address */
830 vector = ((mc_addr[4] >> 2) | (((u16)mc_addr[5]) << 6));
832 case 3: /* use bits [43:32] of the address */
833 vector = ((mc_addr[4]) | (((u16)mc_addr[5]) << 8));
835 default: /* Invalid mc_filter_type */
836 DEBUGOUT("MC filter type param set incorrectly\n");
841 /* vector can only be 12-bits or boundary will be exceeded */
847 * txgbe_set_mta - Set bit-vector in multicast table
848 * @hw: pointer to hardware structure
849 * @mc_addr: Multicast address
851 * Sets the bit-vector in the multicast table.
853 void txgbe_set_mta(struct txgbe_hw *hw, u8 *mc_addr)
859 DEBUGFUNC("txgbe_set_mta");
861 hw->addr_ctrl.mta_in_use++;
863 vector = txgbe_mta_vector(hw, mc_addr);
864 DEBUGOUT(" bit-vector = 0x%03X\n", vector);
867 * The MTA is a register array of 128 32-bit registers. It is treated
868 * like an array of 4096 bits. We want to set bit
869 * BitArray[vector_value]. So we figure out what register the bit is
870 * in, read it, OR in the new bit, then write back the new value. The
871 * register is determined by the upper 7 bits of the vector value and
872 * the bit within that register are determined by the lower 5 bits of
875 vector_reg = (vector >> 5) & 0x7F;
876 vector_bit = vector & 0x1F;
877 hw->mac.mta_shadow[vector_reg] |= (1 << vector_bit);
881 * txgbe_update_mc_addr_list - Updates MAC list of multicast addresses
882 * @hw: pointer to hardware structure
883 * @mc_addr_list: the list of new multicast addresses
884 * @mc_addr_count: number of addresses
885 * @next: iterator function to walk the multicast address list
886 * @clear: flag, when set clears the table beforehand
888 * When the clear flag is set, the given list replaces any existing list.
889 * Hashes the given addresses into the multicast table.
891 s32 txgbe_update_mc_addr_list(struct txgbe_hw *hw, u8 *mc_addr_list,
892 u32 mc_addr_count, txgbe_mc_addr_itr next,
898 DEBUGFUNC("txgbe_update_mc_addr_list");
901 * Set the new number of MC addresses that we are being requested to
904 hw->addr_ctrl.num_mc_addrs = mc_addr_count;
905 hw->addr_ctrl.mta_in_use = 0;
907 /* Clear mta_shadow */
909 DEBUGOUT(" Clearing MTA\n");
910 memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow));
913 /* Update mta_shadow */
914 for (i = 0; i < mc_addr_count; i++) {
915 DEBUGOUT(" Adding the multicast addresses:\n");
916 txgbe_set_mta(hw, next(hw, &mc_addr_list, &vmdq));
920 for (i = 0; i < hw->mac.mcft_size; i++)
921 wr32a(hw, TXGBE_MCADDRTBL(0), i,
922 hw->mac.mta_shadow[i]);
924 if (hw->addr_ctrl.mta_in_use > 0) {
925 u32 psrctl = rd32(hw, TXGBE_PSRCTL);
926 psrctl &= ~(TXGBE_PSRCTL_ADHF12_MASK | TXGBE_PSRCTL_MCHFENA);
927 psrctl |= TXGBE_PSRCTL_MCHFENA |
928 TXGBE_PSRCTL_ADHF12(hw->mac.mc_filter_type);
929 wr32(hw, TXGBE_PSRCTL, psrctl);
932 DEBUGOUT("txgbe update mc addr list complete\n");
937 * txgbe_fc_enable - Enable flow control
938 * @hw: pointer to hardware structure
940 * Enable flow control according to the current settings.
942 s32 txgbe_fc_enable(struct txgbe_hw *hw)
945 u32 mflcn_reg, fccfg_reg;
950 DEBUGFUNC("txgbe_fc_enable");
952 /* Validate the water mark configuration */
953 if (!hw->fc.pause_time) {
954 err = TXGBE_ERR_INVALID_LINK_SETTINGS;
958 /* Low water mark of zero causes XOFF floods */
959 for (i = 0; i < TXGBE_DCB_TC_MAX; i++) {
960 if ((hw->fc.current_mode & txgbe_fc_tx_pause) &&
961 hw->fc.high_water[i]) {
962 if (!hw->fc.low_water[i] ||
963 hw->fc.low_water[i] >= hw->fc.high_water[i]) {
964 DEBUGOUT("Invalid water mark configuration\n");
965 err = TXGBE_ERR_INVALID_LINK_SETTINGS;
971 /* Negotiate the fc mode to use */
972 hw->mac.fc_autoneg(hw);
974 /* Disable any previous flow control settings */
975 mflcn_reg = rd32(hw, TXGBE_RXFCCFG);
976 mflcn_reg &= ~(TXGBE_RXFCCFG_FC | TXGBE_RXFCCFG_PFC);
978 fccfg_reg = rd32(hw, TXGBE_TXFCCFG);
979 fccfg_reg &= ~(TXGBE_TXFCCFG_FC | TXGBE_TXFCCFG_PFC);
982 * The possible values of fc.current_mode are:
983 * 0: Flow control is completely disabled
984 * 1: Rx flow control is enabled (we can receive pause frames,
985 * but not send pause frames).
986 * 2: Tx flow control is enabled (we can send pause frames but
987 * we do not support receiving pause frames).
988 * 3: Both Rx and Tx flow control (symmetric) are enabled.
991 switch (hw->fc.current_mode) {
994 * Flow control is disabled by software override or autoneg.
995 * The code below will actually disable it in the HW.
998 case txgbe_fc_rx_pause:
1000 * Rx Flow control is enabled and Tx Flow control is
1001 * disabled by software override. Since there really
1002 * isn't a way to advertise that we are capable of RX
1003 * Pause ONLY, we will advertise that we support both
1004 * symmetric and asymmetric Rx PAUSE. Later, we will
1005 * disable the adapter's ability to send PAUSE frames.
1007 mflcn_reg |= TXGBE_RXFCCFG_FC;
1009 case txgbe_fc_tx_pause:
1011 * Tx Flow control is enabled, and Rx Flow control is
1012 * disabled by software override.
1014 fccfg_reg |= TXGBE_TXFCCFG_FC;
1017 /* Flow control (both Rx and Tx) is enabled by SW override. */
1018 mflcn_reg |= TXGBE_RXFCCFG_FC;
1019 fccfg_reg |= TXGBE_TXFCCFG_FC;
1022 DEBUGOUT("Flow control param set incorrectly\n");
1023 err = TXGBE_ERR_CONFIG;
1027 /* Set 802.3x based flow control settings. */
1028 wr32(hw, TXGBE_RXFCCFG, mflcn_reg);
1029 wr32(hw, TXGBE_TXFCCFG, fccfg_reg);
1031 /* Set up and enable Rx high/low water mark thresholds, enable XON. */
1032 for (i = 0; i < TXGBE_DCB_TC_MAX; i++) {
1033 if ((hw->fc.current_mode & txgbe_fc_tx_pause) &&
1034 hw->fc.high_water[i]) {
1035 fcrtl = TXGBE_FCWTRLO_TH(hw->fc.low_water[i]) |
1037 fcrth = TXGBE_FCWTRHI_TH(hw->fc.high_water[i]) |
1041 * In order to prevent Tx hangs when the internal Tx
1042 * switch is enabled we must set the high water mark
1043 * to the Rx packet buffer size - 24KB. This allows
1044 * the Tx switch to function even under heavy Rx
1048 fcrth = rd32(hw, TXGBE_PBRXSIZE(i)) - 24576;
1050 wr32(hw, TXGBE_FCWTRLO(i), fcrtl);
1051 wr32(hw, TXGBE_FCWTRHI(i), fcrth);
1054 /* Configure pause time (2 TCs per register) */
1055 pause_time = TXGBE_RXFCFSH_TIME(hw->fc.pause_time);
1056 for (i = 0; i < (TXGBE_DCB_TC_MAX / 2); i++)
1057 wr32(hw, TXGBE_FCXOFFTM(i), pause_time * 0x00010001);
1059 /* Configure flow control refresh threshold value */
1060 wr32(hw, TXGBE_RXFCRFSH, hw->fc.pause_time / 2);
1067 * txgbe_negotiate_fc - Negotiate flow control
1068 * @hw: pointer to hardware structure
1069 * @adv_reg: flow control advertised settings
1070 * @lp_reg: link partner's flow control settings
1071 * @adv_sym: symmetric pause bit in advertisement
1072 * @adv_asm: asymmetric pause bit in advertisement
1073 * @lp_sym: symmetric pause bit in link partner advertisement
1074 * @lp_asm: asymmetric pause bit in link partner advertisement
1076 * Find the intersection between advertised settings and link partner's
1077 * advertised settings
1079 s32 txgbe_negotiate_fc(struct txgbe_hw *hw, u32 adv_reg, u32 lp_reg,
1080 u32 adv_sym, u32 adv_asm, u32 lp_sym, u32 lp_asm)
1082 if ((!(adv_reg)) || (!(lp_reg))) {
1083 DEBUGOUT("Local or link partner's advertised flow control "
1084 "settings are NULL. Local: %x, link partner: %x\n",
1086 return TXGBE_ERR_FC_NOT_NEGOTIATED;
1089 if ((adv_reg & adv_sym) && (lp_reg & lp_sym)) {
1091 * Now we need to check if the user selected Rx ONLY
1092 * of pause frames. In this case, we had to advertise
1093 * FULL flow control because we could not advertise RX
1094 * ONLY. Hence, we must now check to see if we need to
1095 * turn OFF the TRANSMISSION of PAUSE frames.
1097 if (hw->fc.requested_mode == txgbe_fc_full) {
1098 hw->fc.current_mode = txgbe_fc_full;
1099 DEBUGOUT("Flow Control = FULL.\n");
1101 hw->fc.current_mode = txgbe_fc_rx_pause;
1102 DEBUGOUT("Flow Control=RX PAUSE frames only\n");
1104 } else if (!(adv_reg & adv_sym) && (adv_reg & adv_asm) &&
1105 (lp_reg & lp_sym) && (lp_reg & lp_asm)) {
1106 hw->fc.current_mode = txgbe_fc_tx_pause;
1107 DEBUGOUT("Flow Control = TX PAUSE frames only.\n");
1108 } else if ((adv_reg & adv_sym) && (adv_reg & adv_asm) &&
1109 !(lp_reg & lp_sym) && (lp_reg & lp_asm)) {
1110 hw->fc.current_mode = txgbe_fc_rx_pause;
1111 DEBUGOUT("Flow Control = RX PAUSE frames only.\n");
1113 hw->fc.current_mode = txgbe_fc_none;
1114 DEBUGOUT("Flow Control = NONE.\n");
1120 * txgbe_fc_autoneg_fiber - Enable flow control on 1 gig fiber
1121 * @hw: pointer to hardware structure
1123 * Enable flow control according on 1 gig fiber.
1125 STATIC s32 txgbe_fc_autoneg_fiber(struct txgbe_hw *hw)
1127 u32 pcs_anadv_reg, pcs_lpab_reg;
1128 s32 err = TXGBE_ERR_FC_NOT_NEGOTIATED;
1131 * On multispeed fiber at 1g, bail out if
1132 * - link is up but AN did not complete, or if
1133 * - link is up and AN completed but timed out
1136 pcs_anadv_reg = rd32_epcs(hw, SR_MII_MMD_AN_ADV);
1137 pcs_lpab_reg = rd32_epcs(hw, SR_MII_MMD_LP_BABL);
1139 err = txgbe_negotiate_fc(hw, pcs_anadv_reg,
1141 SR_MII_MMD_AN_ADV_PAUSE_SYM,
1142 SR_MII_MMD_AN_ADV_PAUSE_ASM,
1143 SR_MII_MMD_AN_ADV_PAUSE_SYM,
1144 SR_MII_MMD_AN_ADV_PAUSE_ASM);
1150 * txgbe_fc_autoneg_backplane - Enable flow control IEEE clause 37
1151 * @hw: pointer to hardware structure
1153 * Enable flow control according to IEEE clause 37.
1155 STATIC s32 txgbe_fc_autoneg_backplane(struct txgbe_hw *hw)
1157 u32 anlp1_reg, autoc_reg;
1158 s32 err = TXGBE_ERR_FC_NOT_NEGOTIATED;
1161 * Read the 10g AN autoc and LP ability registers and resolve
1162 * local flow control settings accordingly
1164 autoc_reg = rd32_epcs(hw, SR_AN_MMD_ADV_REG1);
1165 anlp1_reg = rd32_epcs(hw, SR_AN_MMD_LP_ABL1);
1167 err = txgbe_negotiate_fc(hw, autoc_reg,
1169 SR_AN_MMD_ADV_REG1_PAUSE_SYM,
1170 SR_AN_MMD_ADV_REG1_PAUSE_ASM,
1171 SR_AN_MMD_ADV_REG1_PAUSE_SYM,
1172 SR_AN_MMD_ADV_REG1_PAUSE_ASM);
1178 * txgbe_fc_autoneg_copper - Enable flow control IEEE clause 37
1179 * @hw: pointer to hardware structure
1181 * Enable flow control according to IEEE clause 37.
1183 STATIC s32 txgbe_fc_autoneg_copper(struct txgbe_hw *hw)
1185 u16 technology_ability_reg = 0;
1186 u16 lp_technology_ability_reg = 0;
1188 hw->phy.read_reg(hw, TXGBE_MD_AUTO_NEG_ADVT,
1189 TXGBE_MD_DEV_AUTO_NEG,
1190 &technology_ability_reg);
1191 hw->phy.read_reg(hw, TXGBE_MD_AUTO_NEG_LP,
1192 TXGBE_MD_DEV_AUTO_NEG,
1193 &lp_technology_ability_reg);
1195 return txgbe_negotiate_fc(hw, (u32)technology_ability_reg,
1196 (u32)lp_technology_ability_reg,
1197 TXGBE_TAF_SYM_PAUSE, TXGBE_TAF_ASM_PAUSE,
1198 TXGBE_TAF_SYM_PAUSE, TXGBE_TAF_ASM_PAUSE);
1202 * txgbe_fc_autoneg - Configure flow control
1203 * @hw: pointer to hardware structure
1205 * Compares our advertised flow control capabilities to those advertised by
1206 * our link partner, and determines the proper flow control mode to use.
1208 void txgbe_fc_autoneg(struct txgbe_hw *hw)
1210 s32 err = TXGBE_ERR_FC_NOT_NEGOTIATED;
1214 DEBUGFUNC("txgbe_fc_autoneg");
1217 * AN should have completed when the cable was plugged in.
1218 * Look for reasons to bail out. Bail out if:
1219 * - FC autoneg is disabled, or if
1222 if (hw->fc.disable_fc_autoneg) {
1223 DEBUGOUT("Flow control autoneg is disabled");
1227 hw->mac.check_link(hw, &speed, &link_up, false);
1229 DEBUGOUT("The link is down");
1233 switch (hw->phy.media_type) {
1234 /* Autoneg flow control on fiber adapters */
1235 case txgbe_media_type_fiber_qsfp:
1236 case txgbe_media_type_fiber:
1237 if (speed == TXGBE_LINK_SPEED_1GB_FULL)
1238 err = txgbe_fc_autoneg_fiber(hw);
1241 /* Autoneg flow control on backplane adapters */
1242 case txgbe_media_type_backplane:
1243 err = txgbe_fc_autoneg_backplane(hw);
1246 /* Autoneg flow control on copper adapters */
1247 case txgbe_media_type_copper:
1248 if (txgbe_device_supports_autoneg_fc(hw))
1249 err = txgbe_fc_autoneg_copper(hw);
1258 hw->fc.fc_was_autonegged = true;
1260 hw->fc.fc_was_autonegged = false;
1261 hw->fc.current_mode = hw->fc.requested_mode;
1266 * txgbe_acquire_swfw_sync - Acquire SWFW semaphore
1267 * @hw: pointer to hardware structure
1268 * @mask: Mask to specify which semaphore to acquire
1270 * Acquires the SWFW semaphore through the MNGSEM register for the specified
1271 * function (CSR, PHY0, PHY1, EEPROM, Flash)
1273 s32 txgbe_acquire_swfw_sync(struct txgbe_hw *hw, u32 mask)
1276 u32 swmask = TXGBE_MNGSEM_SW(mask);
1277 u32 fwmask = TXGBE_MNGSEM_FW(mask);
1281 DEBUGFUNC("txgbe_acquire_swfw_sync");
1283 for (i = 0; i < timeout; i++) {
1285 * SW NVM semaphore bit is used for access to all
1286 * SW_FW_SYNC bits (not just NVM)
1288 if (txgbe_get_eeprom_semaphore(hw))
1289 return TXGBE_ERR_SWFW_SYNC;
1291 mngsem = rd32(hw, TXGBE_MNGSEM);
1292 if (mngsem & (fwmask | swmask)) {
1293 /* Resource is currently in use by FW or SW */
1294 txgbe_release_eeprom_semaphore(hw);
1298 wr32(hw, TXGBE_MNGSEM, mngsem);
1299 txgbe_release_eeprom_semaphore(hw);
1304 /* If time expired clear the bits holding the lock and retry */
1305 if (mngsem & (fwmask | swmask))
1306 txgbe_release_swfw_sync(hw, mngsem & (fwmask | swmask));
1309 return TXGBE_ERR_SWFW_SYNC;
1313 * txgbe_release_swfw_sync - Release SWFW semaphore
1314 * @hw: pointer to hardware structure
1315 * @mask: Mask to specify which semaphore to release
1317 * Releases the SWFW semaphore through the MNGSEM register for the specified
1318 * function (CSR, PHY0, PHY1, EEPROM, Flash)
1320 void txgbe_release_swfw_sync(struct txgbe_hw *hw, u32 mask)
1325 DEBUGFUNC("txgbe_release_swfw_sync");
1327 txgbe_get_eeprom_semaphore(hw);
1329 mngsem = rd32(hw, TXGBE_MNGSEM);
1331 wr32(hw, TXGBE_MNGSEM, mngsem);
1333 txgbe_release_eeprom_semaphore(hw);
1337 * txgbe_disable_sec_rx_path - Stops the receive data path
1338 * @hw: pointer to hardware structure
1340 * Stops the receive data path and waits for the HW to internally empty
1341 * the Rx security block
1343 s32 txgbe_disable_sec_rx_path(struct txgbe_hw *hw)
1345 #define TXGBE_MAX_SECRX_POLL 4000
1350 DEBUGFUNC("txgbe_disable_sec_rx_path");
1352 secrxreg = rd32(hw, TXGBE_SECRXCTL);
1353 secrxreg |= TXGBE_SECRXCTL_XDSA;
1354 wr32(hw, TXGBE_SECRXCTL, secrxreg);
1355 for (i = 0; i < TXGBE_MAX_SECRX_POLL; i++) {
1356 secrxreg = rd32(hw, TXGBE_SECRXSTAT);
1357 if (!(secrxreg & TXGBE_SECRXSTAT_RDY))
1358 /* Use interrupt-safe sleep just in case */
1364 /* For informational purposes only */
1365 if (i >= TXGBE_MAX_SECRX_POLL)
1366 DEBUGOUT("Rx unit being enabled before security "
1367 "path fully disabled. Continuing with init.\n");
1373 * txgbe_enable_sec_rx_path - Enables the receive data path
1374 * @hw: pointer to hardware structure
1376 * Enables the receive data path.
1378 s32 txgbe_enable_sec_rx_path(struct txgbe_hw *hw)
1382 DEBUGFUNC("txgbe_enable_sec_rx_path");
1384 secrxreg = rd32(hw, TXGBE_SECRXCTL);
1385 secrxreg &= ~TXGBE_SECRXCTL_XDSA;
1386 wr32(hw, TXGBE_SECRXCTL, secrxreg);
1393 * txgbe_disable_sec_tx_path - Stops the transmit data path
1394 * @hw: pointer to hardware structure
1396 * Stops the transmit data path and waits for the HW to internally empty
1397 * the Tx security block
1399 int txgbe_disable_sec_tx_path(struct txgbe_hw *hw)
1401 #define TXGBE_MAX_SECTX_POLL 40
1406 sectxreg = rd32(hw, TXGBE_SECTXCTL);
1407 sectxreg |= TXGBE_SECTXCTL_XDSA;
1408 wr32(hw, TXGBE_SECTXCTL, sectxreg);
1409 for (i = 0; i < TXGBE_MAX_SECTX_POLL; i++) {
1410 sectxreg = rd32(hw, TXGBE_SECTXSTAT);
1411 if (sectxreg & TXGBE_SECTXSTAT_RDY)
1413 /* Use interrupt-safe sleep just in case */
1417 /* For informational purposes only */
1418 if (i >= TXGBE_MAX_SECTX_POLL)
1419 PMD_DRV_LOG(DEBUG, "Tx unit being enabled before security "
1420 "path fully disabled. Continuing with init.");
1426 * txgbe_enable_sec_tx_path - Enables the transmit data path
1427 * @hw: pointer to hardware structure
1429 * Enables the transmit data path.
1431 int txgbe_enable_sec_tx_path(struct txgbe_hw *hw)
1435 sectxreg = rd32(hw, TXGBE_SECTXCTL);
1436 sectxreg &= ~TXGBE_SECTXCTL_XDSA;
1437 wr32(hw, TXGBE_SECTXCTL, sectxreg);
1444 * txgbe_get_san_mac_addr_offset - Get SAN MAC address offset from the EEPROM
1445 * @hw: pointer to hardware structure
1446 * @san_mac_offset: SAN MAC address offset
1448 * This function will read the EEPROM location for the SAN MAC address
1449 * pointer, and returns the value at that location. This is used in both
1450 * get and set mac_addr routines.
1452 static s32 txgbe_get_san_mac_addr_offset(struct txgbe_hw *hw,
1453 u16 *san_mac_offset)
1457 DEBUGFUNC("txgbe_get_san_mac_addr_offset");
1460 * First read the EEPROM pointer to see if the MAC addresses are
1463 err = hw->rom.readw_sw(hw, TXGBE_SAN_MAC_ADDR_PTR,
1466 DEBUGOUT("eeprom at offset %d failed",
1467 TXGBE_SAN_MAC_ADDR_PTR);
1474 * txgbe_get_san_mac_addr - SAN MAC address retrieval from the EEPROM
1475 * @hw: pointer to hardware structure
1476 * @san_mac_addr: SAN MAC address
1478 * Reads the SAN MAC address from the EEPROM, if it's available. This is
1479 * per-port, so set_lan_id() must be called before reading the addresses.
1480 * set_lan_id() is called by identify_sfp(), but this cannot be relied
1481 * upon for non-SFP connections, so we must call it here.
1483 s32 txgbe_get_san_mac_addr(struct txgbe_hw *hw, u8 *san_mac_addr)
1485 u16 san_mac_data, san_mac_offset;
1489 DEBUGFUNC("txgbe_get_san_mac_addr");
1492 * First read the EEPROM pointer to see if the MAC addresses are
1493 * available. If they're not, no point in calling set_lan_id() here.
1495 err = txgbe_get_san_mac_addr_offset(hw, &san_mac_offset);
1496 if (err || san_mac_offset == 0 || san_mac_offset == 0xFFFF)
1497 goto san_mac_addr_out;
1499 /* apply the port offset to the address offset */
1500 (hw->bus.func) ? (san_mac_offset += TXGBE_SAN_MAC_ADDR_PORT1_OFFSET) :
1501 (san_mac_offset += TXGBE_SAN_MAC_ADDR_PORT0_OFFSET);
1502 for (i = 0; i < 3; i++) {
1503 err = hw->rom.read16(hw, san_mac_offset,
1506 DEBUGOUT("eeprom read at offset %d failed",
1508 goto san_mac_addr_out;
1510 san_mac_addr[i * 2] = (u8)(san_mac_data);
1511 san_mac_addr[i * 2 + 1] = (u8)(san_mac_data >> 8);
1518 * No addresses available in this EEPROM. It's not an
1519 * error though, so just wipe the local address and return.
1521 for (i = 0; i < 6; i++)
1522 san_mac_addr[i] = 0xFF;
1527 * txgbe_set_san_mac_addr - Write the SAN MAC address to the EEPROM
1528 * @hw: pointer to hardware structure
1529 * @san_mac_addr: SAN MAC address
1531 * Write a SAN MAC address to the EEPROM.
1533 s32 txgbe_set_san_mac_addr(struct txgbe_hw *hw, u8 *san_mac_addr)
1536 u16 san_mac_data, san_mac_offset;
1539 DEBUGFUNC("txgbe_set_san_mac_addr");
1541 /* Look for SAN mac address pointer. If not defined, return */
1542 err = txgbe_get_san_mac_addr_offset(hw, &san_mac_offset);
1543 if (err || san_mac_offset == 0 || san_mac_offset == 0xFFFF)
1544 return TXGBE_ERR_NO_SAN_ADDR_PTR;
1546 /* Apply the port offset to the address offset */
1547 (hw->bus.func) ? (san_mac_offset += TXGBE_SAN_MAC_ADDR_PORT1_OFFSET) :
1548 (san_mac_offset += TXGBE_SAN_MAC_ADDR_PORT0_OFFSET);
1550 for (i = 0; i < 3; i++) {
1551 san_mac_data = (u16)((u16)(san_mac_addr[i * 2 + 1]) << 8);
1552 san_mac_data |= (u16)(san_mac_addr[i * 2]);
1553 hw->rom.write16(hw, san_mac_offset, san_mac_data);
1561 * txgbe_clear_vmdq - Disassociate a VMDq pool index from a rx address
1562 * @hw: pointer to hardware struct
1563 * @rar: receive address register index to disassociate
1564 * @vmdq: VMDq pool index to remove from the rar
1566 s32 txgbe_clear_vmdq(struct txgbe_hw *hw, u32 rar, u32 vmdq)
1568 u32 mpsar_lo, mpsar_hi;
1569 u32 rar_entries = hw->mac.num_rar_entries;
1571 DEBUGFUNC("txgbe_clear_vmdq");
1573 /* Make sure we are using a valid rar index range */
1574 if (rar >= rar_entries) {
1575 DEBUGOUT("RAR index %d is out of range.\n", rar);
1576 return TXGBE_ERR_INVALID_ARGUMENT;
1579 wr32(hw, TXGBE_ETHADDRIDX, rar);
1580 mpsar_lo = rd32(hw, TXGBE_ETHADDRASSL);
1581 mpsar_hi = rd32(hw, TXGBE_ETHADDRASSH);
1583 if (TXGBE_REMOVED(hw->hw_addr))
1586 if (!mpsar_lo && !mpsar_hi)
1589 if (vmdq == BIT_MASK32) {
1591 wr32(hw, TXGBE_ETHADDRASSL, 0);
1595 wr32(hw, TXGBE_ETHADDRASSH, 0);
1598 } else if (vmdq < 32) {
1599 mpsar_lo &= ~(1 << vmdq);
1600 wr32(hw, TXGBE_ETHADDRASSL, mpsar_lo);
1602 mpsar_hi &= ~(1 << (vmdq - 32));
1603 wr32(hw, TXGBE_ETHADDRASSH, mpsar_hi);
1606 /* was that the last pool using this rar? */
1607 if (mpsar_lo == 0 && mpsar_hi == 0 &&
1608 rar != 0 && rar != hw->mac.san_mac_rar_index)
1609 hw->mac.clear_rar(hw, rar);
1615 * txgbe_set_vmdq - Associate a VMDq pool index with a rx address
1616 * @hw: pointer to hardware struct
1617 * @rar: receive address register index to associate with a VMDq index
1618 * @vmdq: VMDq pool index
1620 s32 txgbe_set_vmdq(struct txgbe_hw *hw, u32 rar, u32 vmdq)
1623 u32 rar_entries = hw->mac.num_rar_entries;
1625 DEBUGFUNC("txgbe_set_vmdq");
1627 /* Make sure we are using a valid rar index range */
1628 if (rar >= rar_entries) {
1629 DEBUGOUT("RAR index %d is out of range.\n", rar);
1630 return TXGBE_ERR_INVALID_ARGUMENT;
1633 wr32(hw, TXGBE_ETHADDRIDX, rar);
1635 mpsar = rd32(hw, TXGBE_ETHADDRASSL);
1637 wr32(hw, TXGBE_ETHADDRASSL, mpsar);
1639 mpsar = rd32(hw, TXGBE_ETHADDRASSH);
1640 mpsar |= 1 << (vmdq - 32);
1641 wr32(hw, TXGBE_ETHADDRASSH, mpsar);
1647 * txgbe_init_uta_tables - Initialize the Unicast Table Array
1648 * @hw: pointer to hardware structure
1650 s32 txgbe_init_uta_tables(struct txgbe_hw *hw)
1654 DEBUGFUNC("txgbe_init_uta_tables");
1655 DEBUGOUT(" Clearing UTA\n");
1657 for (i = 0; i < 128; i++)
1658 wr32(hw, TXGBE_UCADDRTBL(i), 0);
1664 * txgbe_find_vlvf_slot - find the vlanid or the first empty slot
1665 * @hw: pointer to hardware structure
1666 * @vlan: VLAN id to write to VLAN filter
1667 * @vlvf_bypass: true to find vlanid only, false returns first empty slot if
1671 * return the VLVF index where this VLAN id should be placed
1674 s32 txgbe_find_vlvf_slot(struct txgbe_hw *hw, u32 vlan, bool vlvf_bypass)
1676 s32 regindex, first_empty_slot;
1679 /* short cut the special case */
1683 /* if vlvf_bypass is set we don't want to use an empty slot, we
1684 * will simply bypass the VLVF if there are no entries present in the
1685 * VLVF that contain our VLAN
1687 first_empty_slot = vlvf_bypass ? TXGBE_ERR_NO_SPACE : 0;
1689 /* add VLAN enable bit for comparison */
1690 vlan |= TXGBE_PSRVLAN_EA;
1692 /* Search for the vlan id in the VLVF entries. Save off the first empty
1693 * slot found along the way.
1695 * pre-decrement loop covering (TXGBE_NUM_POOL - 1) .. 1
1697 for (regindex = TXGBE_NUM_POOL; --regindex;) {
1698 wr32(hw, TXGBE_PSRVLANIDX, regindex);
1699 bits = rd32(hw, TXGBE_PSRVLAN);
1702 if (!first_empty_slot && !bits)
1703 first_empty_slot = regindex;
1706 /* If we are here then we didn't find the VLAN. Return first empty
1707 * slot we found during our search, else error.
1709 if (!first_empty_slot)
1710 DEBUGOUT("No space in VLVF.\n");
1712 return first_empty_slot ? first_empty_slot : TXGBE_ERR_NO_SPACE;
1716 * txgbe_set_vfta - Set VLAN filter table
1717 * @hw: pointer to hardware structure
1718 * @vlan: VLAN id to write to VLAN filter
1719 * @vind: VMDq output index that maps queue to VLAN id in VLVFB
1720 * @vlan_on: boolean flag to turn on/off VLAN
1721 * @vlvf_bypass: boolean flag indicating updating default pool is okay
1723 * Turn on/off specified VLAN in the VLAN filter table.
1725 s32 txgbe_set_vfta(struct txgbe_hw *hw, u32 vlan, u32 vind,
1726 bool vlan_on, bool vlvf_bypass)
1728 u32 regidx, vfta_delta, vfta;
1731 DEBUGFUNC("txgbe_set_vfta");
1733 if (vlan > 4095 || vind > 63)
1734 return TXGBE_ERR_PARAM;
1737 * this is a 2 part operation - first the VFTA, then the
1738 * VLVF and VLVFB if VT Mode is set
1739 * We don't write the VFTA until we know the VLVF part succeeded.
1743 * The VFTA is a bitstring made up of 128 32-bit registers
1744 * that enable the particular VLAN id, much like the MTA:
1745 * bits[11-5]: which register
1746 * bits[4-0]: which bit in the register
1749 vfta_delta = 1 << (vlan % 32);
1750 vfta = rd32(hw, TXGBE_VLANTBL(regidx));
1753 * vfta_delta represents the difference between the current value
1754 * of vfta and the value we want in the register. Since the diff
1755 * is an XOR mask we can just update the vfta using an XOR
1757 vfta_delta &= vlan_on ? ~vfta : vfta;
1761 * Call txgbe_set_vlvf to set VLVFB and VLVF
1763 err = txgbe_set_vlvf(hw, vlan, vind, vlan_on, &vfta_delta,
1772 /* Update VFTA now that we are ready for traffic */
1774 wr32(hw, TXGBE_VLANTBL(regidx), vfta);
1780 * txgbe_set_vlvf - Set VLAN Pool Filter
1781 * @hw: pointer to hardware structure
1782 * @vlan: VLAN id to write to VLAN filter
1783 * @vind: VMDq output index that maps queue to VLAN id in PSRVLANPLM
1784 * @vlan_on: boolean flag to turn on/off VLAN in PSRVLAN
1785 * @vfta_delta: pointer to the difference between the current value
1786 * of PSRVLANPLM and the desired value
1787 * @vfta: the desired value of the VFTA
1788 * @vlvf_bypass: boolean flag indicating updating default pool is okay
1790 * Turn on/off specified bit in VLVF table.
1792 s32 txgbe_set_vlvf(struct txgbe_hw *hw, u32 vlan, u32 vind,
1793 bool vlan_on, u32 *vfta_delta, u32 vfta,
1800 DEBUGFUNC("txgbe_set_vlvf");
1802 if (vlan > 4095 || vind > 63)
1803 return TXGBE_ERR_PARAM;
1805 /* If VT Mode is set
1807 * make sure the vlan is in PSRVLAN
1808 * set the vind bit in the matching PSRVLANPLM
1810 * clear the pool bit and possibly the vind
1812 portctl = rd32(hw, TXGBE_PORTCTL);
1813 if (!(portctl & TXGBE_PORTCTL_NUMVT_MASK))
1816 vlvf_index = txgbe_find_vlvf_slot(hw, vlan, vlvf_bypass);
1820 wr32(hw, TXGBE_PSRVLANIDX, vlvf_index);
1821 bits = rd32(hw, TXGBE_PSRVLANPLM(vind / 32));
1823 /* set the pool bit */
1824 bits |= 1 << (vind % 32);
1828 /* clear the pool bit */
1829 bits ^= 1 << (vind % 32);
1832 !rd32(hw, TXGBE_PSRVLANPLM(vind / 32))) {
1833 /* Clear PSRVLANPLM first, then disable PSRVLAN. Otherwise
1834 * we run the risk of stray packets leaking into
1835 * the PF via the default pool
1838 wr32(hw, TXGBE_PSRVLANPLM(vlan / 32), vfta);
1840 /* disable VLVF and clear remaining bit from pool */
1841 wr32(hw, TXGBE_PSRVLAN, 0);
1842 wr32(hw, TXGBE_PSRVLANPLM(vind / 32), 0);
1847 /* If there are still bits set in the PSRVLANPLM registers
1848 * for the VLAN ID indicated we need to see if the
1849 * caller is requesting that we clear the PSRVLANPLM entry bit.
1850 * If the caller has requested that we clear the PSRVLANPLM
1851 * entry bit but there are still pools/VFs using this VLAN
1852 * ID entry then ignore the request. We're not worried
1853 * about the case where we're turning the PSRVLANPLM VLAN ID
1854 * entry bit on, only when requested to turn it off as
1855 * there may be multiple pools and/or VFs using the
1856 * VLAN ID entry. In that case we cannot clear the
1857 * PSRVLANPLM bit until all pools/VFs using that VLAN ID have also
1858 * been cleared. This will be indicated by "bits" being
1864 /* record pool change and enable VLAN ID if not already enabled */
1865 wr32(hw, TXGBE_PSRVLANPLM(vind / 32), bits);
1866 wr32(hw, TXGBE_PSRVLAN, TXGBE_PSRVLAN_EA | vlan);
1872 * txgbe_clear_vfta - Clear VLAN filter table
1873 * @hw: pointer to hardware structure
1875 * Clears the VLAN filer table, and the VMDq index associated with the filter
1877 s32 txgbe_clear_vfta(struct txgbe_hw *hw)
1881 DEBUGFUNC("txgbe_clear_vfta");
1883 for (offset = 0; offset < hw->mac.vft_size; offset++)
1884 wr32(hw, TXGBE_VLANTBL(offset), 0);
1886 for (offset = 0; offset < TXGBE_NUM_POOL; offset++) {
1887 wr32(hw, TXGBE_PSRVLANIDX, offset);
1888 wr32(hw, TXGBE_PSRVLAN, 0);
1889 wr32(hw, TXGBE_PSRVLANPLM(0), 0);
1890 wr32(hw, TXGBE_PSRVLANPLM(1), 0);
1897 * txgbe_need_crosstalk_fix - Determine if we need to do cross talk fix
1898 * @hw: pointer to hardware structure
1900 * Contains the logic to identify if we need to verify link for the
1903 static bool txgbe_need_crosstalk_fix(struct txgbe_hw *hw)
1905 /* Does FW say we need the fix */
1906 if (!hw->need_crosstalk_fix)
1909 /* Only consider SFP+ PHYs i.e. media type fiber */
1910 switch (hw->phy.media_type) {
1911 case txgbe_media_type_fiber:
1912 case txgbe_media_type_fiber_qsfp:
1922 * txgbe_check_mac_link - Determine link and speed status
1923 * @hw: pointer to hardware structure
1924 * @speed: pointer to link speed
1925 * @link_up: true when link is up
1926 * @link_up_wait_to_complete: bool used to wait for link up or not
1928 * Reads the links register to determine if link is up and the current speed
1930 s32 txgbe_check_mac_link(struct txgbe_hw *hw, u32 *speed,
1931 bool *link_up, bool link_up_wait_to_complete)
1933 u32 links_reg, links_orig;
1936 DEBUGFUNC("txgbe_check_mac_link");
1938 /* If Crosstalk fix enabled do the sanity check of making sure
1939 * the SFP+ cage is full.
1941 if (txgbe_need_crosstalk_fix(hw)) {
1944 switch (hw->mac.type) {
1945 case txgbe_mac_raptor:
1946 sfp_cage_full = !rd32m(hw, TXGBE_GPIODATA,
1950 /* sanity check - No SFP+ devices here */
1951 sfp_cage_full = false;
1955 if (!sfp_cage_full) {
1957 *speed = TXGBE_LINK_SPEED_UNKNOWN;
1962 /* clear the old state */
1963 links_orig = rd32(hw, TXGBE_PORTSTAT);
1965 links_reg = rd32(hw, TXGBE_PORTSTAT);
1967 if (links_orig != links_reg) {
1968 DEBUGOUT("LINKS changed from %08X to %08X\n",
1969 links_orig, links_reg);
1972 if (link_up_wait_to_complete) {
1973 for (i = 0; i < hw->mac.max_link_up_time; i++) {
1974 if (!(links_reg & TXGBE_PORTSTAT_UP)) {
1981 links_reg = rd32(hw, TXGBE_PORTSTAT);
1984 if (links_reg & TXGBE_PORTSTAT_UP)
1990 switch (links_reg & TXGBE_PORTSTAT_BW_MASK) {
1991 case TXGBE_PORTSTAT_BW_10G:
1992 *speed = TXGBE_LINK_SPEED_10GB_FULL;
1994 case TXGBE_PORTSTAT_BW_1G:
1995 *speed = TXGBE_LINK_SPEED_1GB_FULL;
1997 case TXGBE_PORTSTAT_BW_100M:
1998 *speed = TXGBE_LINK_SPEED_100M_FULL;
2001 *speed = TXGBE_LINK_SPEED_UNKNOWN;
2008 * txgbe_get_wwn_prefix - Get alternative WWNN/WWPN prefix from
2010 * @hw: pointer to hardware structure
2011 * @wwnn_prefix: the alternative WWNN prefix
2012 * @wwpn_prefix: the alternative WWPN prefix
2014 * This function will read the EEPROM from the alternative SAN MAC address
2015 * block to check the support for the alternative WWNN/WWPN prefix support.
2017 s32 txgbe_get_wwn_prefix(struct txgbe_hw *hw, u16 *wwnn_prefix,
2021 u16 alt_san_mac_blk_offset;
2023 DEBUGFUNC("txgbe_get_wwn_prefix");
2025 /* clear output first */
2026 *wwnn_prefix = 0xFFFF;
2027 *wwpn_prefix = 0xFFFF;
2029 /* check if alternative SAN MAC is supported */
2030 offset = TXGBE_ALT_SAN_MAC_ADDR_BLK_PTR;
2031 if (hw->rom.readw_sw(hw, offset, &alt_san_mac_blk_offset))
2032 goto wwn_prefix_err;
2034 if (alt_san_mac_blk_offset == 0 || alt_san_mac_blk_offset == 0xFFFF)
2035 goto wwn_prefix_out;
2037 /* check capability in alternative san mac address block */
2038 offset = alt_san_mac_blk_offset + TXGBE_ALT_SAN_MAC_ADDR_CAPS_OFFSET;
2039 if (hw->rom.read16(hw, offset, &caps))
2040 goto wwn_prefix_err;
2041 if (!(caps & TXGBE_ALT_SAN_MAC_ADDR_CAPS_ALTWWN))
2042 goto wwn_prefix_out;
2044 /* get the corresponding prefix for WWNN/WWPN */
2045 offset = alt_san_mac_blk_offset + TXGBE_ALT_SAN_MAC_ADDR_WWNN_OFFSET;
2046 if (hw->rom.read16(hw, offset, wwnn_prefix))
2047 DEBUGOUT("eeprom read at offset %d failed", offset);
2049 offset = alt_san_mac_blk_offset + TXGBE_ALT_SAN_MAC_ADDR_WWPN_OFFSET;
2050 if (hw->rom.read16(hw, offset, wwpn_prefix))
2051 goto wwn_prefix_err;
2057 DEBUGOUT("eeprom read at offset %d failed", offset);
2062 * txgbe_set_mac_anti_spoofing - Enable/Disable MAC anti-spoofing
2063 * @hw: pointer to hardware structure
2064 * @enable: enable or disable switch for MAC anti-spoofing
2065 * @vf: Virtual Function pool - VF Pool to set for MAC anti-spoofing
2068 void txgbe_set_mac_anti_spoofing(struct txgbe_hw *hw, bool enable, int vf)
2070 int vf_target_reg = vf >> 3;
2071 int vf_target_shift = vf % 8;
2074 pfvfspoof = rd32(hw, TXGBE_POOLTXASMAC(vf_target_reg));
2076 pfvfspoof |= (1 << vf_target_shift);
2078 pfvfspoof &= ~(1 << vf_target_shift);
2079 wr32(hw, TXGBE_POOLTXASMAC(vf_target_reg), pfvfspoof);
2083 * txgbe_set_ethertype_anti_spoofing - Configure Ethertype anti-spoofing
2084 * @hw: pointer to hardware structure
2085 * @enable: enable or disable switch for Ethertype anti-spoofing
2086 * @vf: Virtual Function pool - VF Pool to set for Ethertype anti-spoofing
2089 void txgbe_set_ethertype_anti_spoofing(struct txgbe_hw *hw,
2090 bool enable, int vf)
2092 int vf_target_reg = vf >> 3;
2093 int vf_target_shift = vf % 8;
2096 pfvfspoof = rd32(hw, TXGBE_POOLTXASET(vf_target_reg));
2098 pfvfspoof |= (1 << vf_target_shift);
2100 pfvfspoof &= ~(1 << vf_target_shift);
2101 wr32(hw, TXGBE_POOLTXASET(vf_target_reg), pfvfspoof);
2105 * txgbe_get_device_caps - Get additional device capabilities
2106 * @hw: pointer to hardware structure
2107 * @device_caps: the EEPROM word with the extra device capabilities
2109 * This function will read the EEPROM location for the device capabilities,
2110 * and return the word through device_caps.
2112 s32 txgbe_get_device_caps(struct txgbe_hw *hw, u16 *device_caps)
2114 DEBUGFUNC("txgbe_get_device_caps");
2116 hw->rom.readw_sw(hw, TXGBE_DEVICE_CAPS, device_caps);
2122 * txgbe_set_pba - Initialize Rx packet buffer
2123 * @hw: pointer to hardware structure
2124 * @num_pb: number of packet buffers to allocate
2125 * @headroom: reserve n KB of headroom
2126 * @strategy: packet buffer allocation strategy
2128 void txgbe_set_pba(struct txgbe_hw *hw, int num_pb, u32 headroom,
2131 u32 pbsize = hw->mac.rx_pb_size;
2133 u32 rxpktsize, txpktsize, txpbthresh;
2135 UNREFERENCED_PARAMETER(hw);
2137 /* Reserve headroom */
2143 /* Divide remaining packet buffer space amongst the number of packet
2144 * buffers requested using supplied strategy.
2147 case PBA_STRATEGY_WEIGHTED:
2148 /* txgbe_dcb_pba_80_48 strategy weight first half of packet
2149 * buffer with 5/8 of the packet buffer space.
2151 rxpktsize = (pbsize * 5) / (num_pb * 4);
2152 pbsize -= rxpktsize * (num_pb / 2);
2154 for (; i < (num_pb / 2); i++)
2155 wr32(hw, TXGBE_PBRXSIZE(i), rxpktsize);
2156 /* fall through - configure remaining packet buffers */
2157 case PBA_STRATEGY_EQUAL:
2158 rxpktsize = (pbsize / (num_pb - i));
2160 for (; i < num_pb; i++)
2161 wr32(hw, TXGBE_PBRXSIZE(i), rxpktsize);
2167 /* Only support an equally distributed Tx packet buffer strategy. */
2168 txpktsize = TXGBE_PBTXSIZE_MAX / num_pb;
2169 txpbthresh = (txpktsize / 1024) - TXGBE_TXPKT_SIZE_MAX;
2170 for (i = 0; i < num_pb; i++) {
2171 wr32(hw, TXGBE_PBTXSIZE(i), txpktsize);
2172 wr32(hw, TXGBE_PBTXDMATH(i), txpbthresh);
2175 /* Clear unused TCs, if any, to zero buffer size*/
2176 for (; i < TXGBE_MAX_UP; i++) {
2177 wr32(hw, TXGBE_PBRXSIZE(i), 0);
2178 wr32(hw, TXGBE_PBTXSIZE(i), 0);
2179 wr32(hw, TXGBE_PBTXDMATH(i), 0);
2184 * txgbe_clear_tx_pending - Clear pending TX work from the PCIe fifo
2185 * @hw: pointer to the hardware structure
2187 * The MACs can experience issues if TX work is still pending
2188 * when a reset occurs. This function prevents this by flushing the PCIe
2189 * buffers on the system.
2191 void txgbe_clear_tx_pending(struct txgbe_hw *hw)
2193 u32 hlreg0, i, poll;
2196 * If double reset is not requested then all transactions should
2197 * already be clear and as such there is no work to do
2199 if (!(hw->mac.flags & TXGBE_FLAGS_DOUBLE_RESET_REQUIRED))
2202 hlreg0 = rd32(hw, TXGBE_PSRCTL);
2203 wr32(hw, TXGBE_PSRCTL, hlreg0 | TXGBE_PSRCTL_LBENA);
2205 /* Wait for a last completion before clearing buffers */
2210 * Before proceeding, make sure that the PCIe block does not have
2211 * transactions pending.
2213 poll = (800 * 11) / 10;
2214 for (i = 0; i < poll; i++)
2217 /* Flush all writes and allow 20usec for all transactions to clear */
2221 /* restore previous register values */
2222 wr32(hw, TXGBE_PSRCTL, hlreg0);
2226 * txgbe_get_thermal_sensor_data - Gathers thermal sensor data
2227 * @hw: pointer to hardware structure
2229 * Returns the thermal sensor data structure
2231 s32 txgbe_get_thermal_sensor_data(struct txgbe_hw *hw)
2233 struct txgbe_thermal_sensor_data *data = &hw->mac.thermal_sensor_data;
2237 DEBUGFUNC("txgbe_get_thermal_sensor_data");
2239 /* Only support thermal sensors attached to physical port 0 */
2240 if (hw->bus.lan_id != 0)
2241 return TXGBE_NOT_IMPLEMENTED;
2243 ts_stat = rd32(hw, TXGBE_TSSTAT);
2244 tsv = (s64)TXGBE_TSSTAT_DATA(ts_stat);
2245 tsv = tsv > 1200 ? tsv : 1200;
2246 tsv = -(48380 << 8) / 1000
2247 + tsv * (31020 << 8) / 100000
2248 - tsv * tsv * (18201 << 8) / 100000000
2249 + tsv * tsv * tsv * (81542 << 8) / 1000000000000
2250 - tsv * tsv * tsv * tsv * (16743 << 8) / 1000000000000000;
2253 data->sensor[0].temp = (s16)tsv;
2259 * txgbe_init_thermal_sensor_thresh - Inits thermal sensor thresholds
2260 * @hw: pointer to hardware structure
2262 * Inits the thermal sensor thresholds according to the NVM map
2263 * and save off the threshold and location values into mac.thermal_sensor_data
2265 s32 txgbe_init_thermal_sensor_thresh(struct txgbe_hw *hw)
2267 struct txgbe_thermal_sensor_data *data = &hw->mac.thermal_sensor_data;
2269 DEBUGFUNC("txgbe_init_thermal_sensor_thresh");
2271 memset(data, 0, sizeof(struct txgbe_thermal_sensor_data));
2273 if (hw->bus.lan_id != 0)
2274 return TXGBE_NOT_IMPLEMENTED;
2276 wr32(hw, TXGBE_TSCTRL, TXGBE_TSCTRL_EVALMD);
2277 wr32(hw, TXGBE_TSINTR,
2278 TXGBE_TSINTR_AEN | TXGBE_TSINTR_DEN);
2279 wr32(hw, TXGBE_TSEN, TXGBE_TSEN_ENA);
2282 data->sensor[0].alarm_thresh = 100;
2283 wr32(hw, TXGBE_TSATHRE, 677);
2284 data->sensor[0].dalarm_thresh = 90;
2285 wr32(hw, TXGBE_TSDTHRE, 614);
2290 void txgbe_disable_rx(struct txgbe_hw *hw)
2294 pfdtxgswc = rd32(hw, TXGBE_PSRCTL);
2295 if (pfdtxgswc & TXGBE_PSRCTL_LBENA) {
2296 pfdtxgswc &= ~TXGBE_PSRCTL_LBENA;
2297 wr32(hw, TXGBE_PSRCTL, pfdtxgswc);
2298 hw->mac.set_lben = true;
2300 hw->mac.set_lben = false;
2303 wr32m(hw, TXGBE_PBRXCTL, TXGBE_PBRXCTL_ENA, 0);
2304 wr32m(hw, TXGBE_MACRXCFG, TXGBE_MACRXCFG_ENA, 0);
2307 void txgbe_enable_rx(struct txgbe_hw *hw)
2311 wr32m(hw, TXGBE_MACRXCFG, TXGBE_MACRXCFG_ENA, TXGBE_MACRXCFG_ENA);
2312 wr32m(hw, TXGBE_PBRXCTL, TXGBE_PBRXCTL_ENA, TXGBE_PBRXCTL_ENA);
2314 if (hw->mac.set_lben) {
2315 pfdtxgswc = rd32(hw, TXGBE_PSRCTL);
2316 pfdtxgswc |= TXGBE_PSRCTL_LBENA;
2317 wr32(hw, TXGBE_PSRCTL, pfdtxgswc);
2318 hw->mac.set_lben = false;
2323 * txgbe_setup_mac_link_multispeed_fiber - Set MAC link speed
2324 * @hw: pointer to hardware structure
2325 * @speed: new link speed
2326 * @autoneg_wait_to_complete: true when waiting for completion is needed
2328 * Set the link speed in the MAC and/or PHY register and restarts link.
2330 s32 txgbe_setup_mac_link_multispeed_fiber(struct txgbe_hw *hw,
2332 bool autoneg_wait_to_complete)
2334 u32 link_speed = TXGBE_LINK_SPEED_UNKNOWN;
2335 u32 highest_link_speed = TXGBE_LINK_SPEED_UNKNOWN;
2339 bool autoneg, link_up = false;
2341 DEBUGFUNC("txgbe_setup_mac_link_multispeed_fiber");
2343 /* Mask off requested but non-supported speeds */
2344 status = hw->mac.get_link_capabilities(hw, &link_speed, &autoneg);
2348 speed &= link_speed;
2350 /* Try each speed one by one, highest priority first. We do this in
2351 * software because 10Gb fiber doesn't support speed autonegotiation.
2353 if (speed & TXGBE_LINK_SPEED_10GB_FULL) {
2355 highest_link_speed = TXGBE_LINK_SPEED_10GB_FULL;
2357 /* Set the module link speed */
2358 switch (hw->phy.media_type) {
2359 case txgbe_media_type_fiber:
2360 hw->mac.set_rate_select_speed(hw,
2361 TXGBE_LINK_SPEED_10GB_FULL);
2363 case txgbe_media_type_fiber_qsfp:
2364 /* QSFP module automatically detects MAC link speed */
2367 DEBUGOUT("Unexpected media type.\n");
2371 /* Allow module to change analog characteristics (1G->10G) */
2374 status = hw->mac.setup_mac_link(hw,
2375 TXGBE_LINK_SPEED_10GB_FULL,
2376 autoneg_wait_to_complete);
2380 /* Flap the Tx laser if it has not already been done */
2381 hw->mac.flap_tx_laser(hw);
2383 /* Wait for the controller to acquire link. Per IEEE 802.3ap,
2384 * Section 73.10.2, we may have to wait up to 500ms if KR is
2385 * attempted. uses the same timing for 10g SFI.
2387 for (i = 0; i < 5; i++) {
2388 /* Wait for the link partner to also set speed */
2391 /* If we have link, just jump out */
2392 status = hw->mac.check_link(hw, &link_speed,
2402 if (speed & TXGBE_LINK_SPEED_1GB_FULL) {
2404 if (highest_link_speed == TXGBE_LINK_SPEED_UNKNOWN)
2405 highest_link_speed = TXGBE_LINK_SPEED_1GB_FULL;
2407 /* Set the module link speed */
2408 switch (hw->phy.media_type) {
2409 case txgbe_media_type_fiber:
2410 hw->mac.set_rate_select_speed(hw,
2411 TXGBE_LINK_SPEED_1GB_FULL);
2413 case txgbe_media_type_fiber_qsfp:
2414 /* QSFP module automatically detects link speed */
2417 DEBUGOUT("Unexpected media type.\n");
2421 /* Allow module to change analog characteristics (10G->1G) */
2424 status = hw->mac.setup_mac_link(hw,
2425 TXGBE_LINK_SPEED_1GB_FULL,
2426 autoneg_wait_to_complete);
2430 /* Flap the Tx laser if it has not already been done */
2431 hw->mac.flap_tx_laser(hw);
2433 /* Wait for the link partner to also set speed */
2436 /* If we have link, just jump out */
2437 status = hw->mac.check_link(hw, &link_speed, &link_up, false);
2445 /* We didn't get link. Configure back to the highest speed we tried,
2446 * (if there was more than one). We call ourselves back with just the
2447 * single highest speed that the user requested.
2450 status = txgbe_setup_mac_link_multispeed_fiber(hw,
2452 autoneg_wait_to_complete);
2455 /* Set autoneg_advertised value based on input link speed */
2456 hw->phy.autoneg_advertised = 0;
2458 if (speed & TXGBE_LINK_SPEED_10GB_FULL)
2459 hw->phy.autoneg_advertised |= TXGBE_LINK_SPEED_10GB_FULL;
2461 if (speed & TXGBE_LINK_SPEED_1GB_FULL)
2462 hw->phy.autoneg_advertised |= TXGBE_LINK_SPEED_1GB_FULL;
2468 * txgbe_init_shared_code - Initialize the shared code
2469 * @hw: pointer to hardware structure
2471 * This will assign function pointers and assign the MAC type and PHY code.
2472 * Does not touch the hardware. This function must be called prior to any
2473 * other function in the shared code. The txgbe_hw structure should be
2474 * memset to 0 prior to calling this function. The following fields in
2475 * hw structure should be filled in prior to calling this function:
2476 * hw_addr, back, device_id, vendor_id, subsystem_device_id,
2477 * subsystem_vendor_id, and revision_id
2479 s32 txgbe_init_shared_code(struct txgbe_hw *hw)
2483 DEBUGFUNC("txgbe_init_shared_code");
2488 txgbe_set_mac_type(hw);
2490 txgbe_init_ops_dummy(hw);
2491 switch (hw->mac.type) {
2492 case txgbe_mac_raptor:
2493 status = txgbe_init_ops_pf(hw);
2495 case txgbe_mac_raptor_vf:
2496 status = txgbe_init_ops_vf(hw);
2499 status = TXGBE_ERR_DEVICE_NOT_SUPPORTED;
2502 hw->mac.max_link_up_time = TXGBE_LINK_UP_TIME;
2504 hw->bus.set_lan_id(hw);
2510 * txgbe_set_mac_type - Sets MAC type
2511 * @hw: pointer to the HW structure
2513 * This function sets the mac type of the adapter based on the
2514 * vendor ID and device ID stored in the hw structure.
2516 s32 txgbe_set_mac_type(struct txgbe_hw *hw)
2520 DEBUGFUNC("txgbe_set_mac_type");
2522 if (hw->vendor_id != PCI_VENDOR_ID_WANGXUN) {
2523 DEBUGOUT("Unsupported vendor id: %x", hw->vendor_id);
2524 return TXGBE_ERR_DEVICE_NOT_SUPPORTED;
2527 switch (hw->device_id) {
2528 case TXGBE_DEV_ID_RAPTOR_KR_KX_KX4:
2529 hw->phy.media_type = txgbe_media_type_backplane;
2530 hw->mac.type = txgbe_mac_raptor;
2532 case TXGBE_DEV_ID_RAPTOR_XAUI:
2533 case TXGBE_DEV_ID_RAPTOR_SGMII:
2534 hw->phy.media_type = txgbe_media_type_copper;
2535 hw->mac.type = txgbe_mac_raptor;
2537 case TXGBE_DEV_ID_RAPTOR_SFP:
2538 case TXGBE_DEV_ID_WX1820_SFP:
2539 hw->phy.media_type = txgbe_media_type_fiber;
2540 hw->mac.type = txgbe_mac_raptor;
2542 case TXGBE_DEV_ID_RAPTOR_QSFP:
2543 hw->phy.media_type = txgbe_media_type_fiber_qsfp;
2544 hw->mac.type = txgbe_mac_raptor;
2546 case TXGBE_DEV_ID_RAPTOR_VF:
2547 case TXGBE_DEV_ID_RAPTOR_VF_HV:
2548 hw->phy.media_type = txgbe_media_type_virtual;
2549 hw->mac.type = txgbe_mac_raptor_vf;
2552 err = TXGBE_ERR_DEVICE_NOT_SUPPORTED;
2553 DEBUGOUT("Unsupported device id: %x", hw->device_id);
2557 DEBUGOUT("found mac: %d media: %d, returns: %d\n",
2558 hw->mac.type, hw->phy.media_type, err);
2562 void txgbe_init_mac_link_ops(struct txgbe_hw *hw)
2564 struct txgbe_mac_info *mac = &hw->mac;
2566 DEBUGFUNC("txgbe_init_mac_link_ops");
2569 * enable the laser control functions for SFP+ fiber
2570 * and MNG not enabled
2572 if (hw->phy.media_type == txgbe_media_type_fiber &&
2573 !txgbe_mng_enabled(hw)) {
2574 mac->disable_tx_laser =
2575 txgbe_disable_tx_laser_multispeed_fiber;
2576 mac->enable_tx_laser =
2577 txgbe_enable_tx_laser_multispeed_fiber;
2578 mac->flap_tx_laser =
2579 txgbe_flap_tx_laser_multispeed_fiber;
2582 if ((hw->phy.media_type == txgbe_media_type_fiber ||
2583 hw->phy.media_type == txgbe_media_type_fiber_qsfp) &&
2584 hw->phy.multispeed_fiber) {
2585 /* Set up dual speed SFP+ support */
2586 mac->setup_link = txgbe_setup_mac_link_multispeed_fiber;
2587 mac->setup_mac_link = txgbe_setup_mac_link;
2588 mac->set_rate_select_speed = txgbe_set_hard_rate_select_speed;
2589 } else if ((hw->phy.media_type == txgbe_media_type_backplane) &&
2590 (hw->phy.smart_speed == txgbe_smart_speed_auto ||
2591 hw->phy.smart_speed == txgbe_smart_speed_on) &&
2592 !txgbe_verify_lesm_fw_enabled_raptor(hw)) {
2593 mac->setup_link = txgbe_setup_mac_link_smartspeed;
2595 mac->setup_link = txgbe_setup_mac_link;
2600 * txgbe_init_phy_raptor - PHY/SFP specific init
2601 * @hw: pointer to hardware structure
2603 * Initialize any function pointers that were not able to be
2604 * set during init_shared_code because the PHY/SFP type was
2605 * not known. Perform the SFP init if necessary.
2608 s32 txgbe_init_phy_raptor(struct txgbe_hw *hw)
2610 struct txgbe_mac_info *mac = &hw->mac;
2611 struct txgbe_phy_info *phy = &hw->phy;
2614 DEBUGFUNC("txgbe_init_phy_raptor");
2616 if (hw->device_id == TXGBE_DEV_ID_RAPTOR_QSFP) {
2617 /* Store flag indicating I2C bus access control unit. */
2618 hw->phy.qsfp_shared_i2c_bus = TRUE;
2620 /* Initialize access to QSFP+ I2C bus */
2624 /* Identify the PHY or SFP module */
2625 err = phy->identify(hw);
2626 if (err == TXGBE_ERR_SFP_NOT_SUPPORTED)
2627 goto init_phy_ops_out;
2629 /* Setup function pointers based on detected SFP module and speeds */
2630 txgbe_init_mac_link_ops(hw);
2632 /* If copper media, overwrite with copper function pointers */
2633 if (phy->media_type == txgbe_media_type_copper) {
2634 mac->setup_link = txgbe_setup_copper_link_raptor;
2635 mac->get_link_capabilities =
2636 txgbe_get_copper_link_capabilities;
2639 /* Set necessary function pointers based on PHY type */
2640 switch (hw->phy.type) {
2642 phy->setup_link = txgbe_setup_phy_link_tnx;
2643 phy->check_link = txgbe_check_phy_link_tnx;
2653 s32 txgbe_setup_sfp_modules(struct txgbe_hw *hw)
2657 DEBUGFUNC("txgbe_setup_sfp_modules");
2659 if (hw->phy.sfp_type == txgbe_sfp_type_unknown)
2662 txgbe_init_mac_link_ops(hw);
2664 /* PHY config will finish before releasing the semaphore */
2665 err = hw->mac.acquire_swfw_sync(hw, TXGBE_MNGSEM_SWPHY);
2667 return TXGBE_ERR_SWFW_SYNC;
2669 /* Release the semaphore */
2670 hw->mac.release_swfw_sync(hw, TXGBE_MNGSEM_SWPHY);
2672 /* Delay obtaining semaphore again to allow FW access
2673 * prot_autoc_write uses the semaphore too.
2675 msec_delay(hw->rom.semaphore_delay);
2678 DEBUGOUT("sfp module setup not complete\n");
2679 return TXGBE_ERR_SFP_SETUP_NOT_COMPLETE;
2686 * txgbe_prot_autoc_read_raptor - Hides MAC differences needed for AUTOC read
2687 * @hw: pointer to hardware structure
2688 * @locked: Return the if we locked for this read.
2689 * @value: Value we read from AUTOC
2691 * For this part we need to wrap read-modify-writes with a possible
2692 * FW/SW lock. It is assumed this lock will be freed with the next
2693 * prot_autoc_write_raptor().
2695 s32 txgbe_prot_autoc_read_raptor(struct txgbe_hw *hw, bool *locked, u64 *value)
2698 bool lock_state = false;
2700 /* If LESM is on then we need to hold the SW/FW semaphore. */
2701 if (txgbe_verify_lesm_fw_enabled_raptor(hw)) {
2702 err = hw->mac.acquire_swfw_sync(hw,
2703 TXGBE_MNGSEM_SWPHY);
2705 return TXGBE_ERR_SWFW_SYNC;
2711 *locked = lock_state;
2713 *value = txgbe_autoc_read(hw);
2718 * txgbe_prot_autoc_write_raptor - Hides MAC differences needed for AUTOC write
2719 * @hw: pointer to hardware structure
2720 * @autoc: value to write to AUTOC
2721 * @locked: bool to indicate whether the SW/FW lock was already taken by
2722 * previous prot_autoc_read_raptor.
2724 * This part may need to hold the SW/FW lock around all writes to
2725 * AUTOC. Likewise after a write we need to do a pipeline reset.
2727 s32 txgbe_prot_autoc_write_raptor(struct txgbe_hw *hw, bool locked, u64 autoc)
2731 /* Blocked by MNG FW so bail */
2732 if (txgbe_check_reset_blocked(hw))
2735 /* We only need to get the lock if:
2736 * - We didn't do it already (in the read part of a read-modify-write)
2737 * - LESM is enabled.
2739 if (!locked && txgbe_verify_lesm_fw_enabled_raptor(hw)) {
2740 err = hw->mac.acquire_swfw_sync(hw,
2741 TXGBE_MNGSEM_SWPHY);
2743 return TXGBE_ERR_SWFW_SYNC;
2748 txgbe_autoc_write(hw, autoc);
2749 err = txgbe_reset_pipeline_raptor(hw);
2752 /* Free the SW/FW semaphore as we either grabbed it here or
2753 * already had it when this function was called.
2756 hw->mac.release_swfw_sync(hw, TXGBE_MNGSEM_SWPHY);
2762 * txgbe_init_ops_pf - Inits func ptrs and MAC type
2763 * @hw: pointer to hardware structure
2765 * Initialize the function pointers and assign the MAC type.
2766 * Does not touch the hardware.
2768 s32 txgbe_init_ops_pf(struct txgbe_hw *hw)
2770 struct txgbe_bus_info *bus = &hw->bus;
2771 struct txgbe_mac_info *mac = &hw->mac;
2772 struct txgbe_phy_info *phy = &hw->phy;
2773 struct txgbe_rom_info *rom = &hw->rom;
2774 struct txgbe_mbx_info *mbx = &hw->mbx;
2776 DEBUGFUNC("txgbe_init_ops_pf");
2779 bus->set_lan_id = txgbe_set_lan_id_multi_port;
2782 phy->get_media_type = txgbe_get_media_type_raptor;
2783 phy->identify = txgbe_identify_phy;
2784 phy->init = txgbe_init_phy_raptor;
2785 phy->read_reg = txgbe_read_phy_reg;
2786 phy->write_reg = txgbe_write_phy_reg;
2787 phy->read_reg_mdi = txgbe_read_phy_reg_mdi;
2788 phy->write_reg_mdi = txgbe_write_phy_reg_mdi;
2789 phy->setup_link = txgbe_setup_phy_link;
2790 phy->setup_link_speed = txgbe_setup_phy_link_speed;
2791 phy->read_i2c_byte = txgbe_read_i2c_byte;
2792 phy->write_i2c_byte = txgbe_write_i2c_byte;
2793 phy->read_i2c_sff8472 = txgbe_read_i2c_sff8472;
2794 phy->read_i2c_eeprom = txgbe_read_i2c_eeprom;
2795 phy->write_i2c_eeprom = txgbe_write_i2c_eeprom;
2796 phy->identify_sfp = txgbe_identify_module;
2797 phy->read_i2c_byte_unlocked = txgbe_read_i2c_byte_unlocked;
2798 phy->write_i2c_byte_unlocked = txgbe_write_i2c_byte_unlocked;
2799 phy->reset = txgbe_reset_phy;
2802 mac->init_hw = txgbe_init_hw;
2803 mac->start_hw = txgbe_start_hw_raptor;
2804 mac->clear_hw_cntrs = txgbe_clear_hw_cntrs;
2805 mac->enable_rx_dma = txgbe_enable_rx_dma_raptor;
2806 mac->get_mac_addr = txgbe_get_mac_addr;
2807 mac->stop_hw = txgbe_stop_hw;
2808 mac->acquire_swfw_sync = txgbe_acquire_swfw_sync;
2809 mac->release_swfw_sync = txgbe_release_swfw_sync;
2810 mac->reset_hw = txgbe_reset_hw;
2811 mac->update_mc_addr_list = txgbe_update_mc_addr_list;
2813 mac->disable_sec_rx_path = txgbe_disable_sec_rx_path;
2814 mac->enable_sec_rx_path = txgbe_enable_sec_rx_path;
2815 mac->disable_sec_tx_path = txgbe_disable_sec_tx_path;
2816 mac->enable_sec_tx_path = txgbe_enable_sec_tx_path;
2817 mac->get_san_mac_addr = txgbe_get_san_mac_addr;
2818 mac->set_san_mac_addr = txgbe_set_san_mac_addr;
2819 mac->get_device_caps = txgbe_get_device_caps;
2820 mac->get_wwn_prefix = txgbe_get_wwn_prefix;
2821 mac->autoc_read = txgbe_autoc_read;
2822 mac->autoc_write = txgbe_autoc_write;
2823 mac->prot_autoc_read = txgbe_prot_autoc_read_raptor;
2824 mac->prot_autoc_write = txgbe_prot_autoc_write_raptor;
2826 /* RAR, Multicast, VLAN */
2827 mac->set_rar = txgbe_set_rar;
2828 mac->clear_rar = txgbe_clear_rar;
2829 mac->init_rx_addrs = txgbe_init_rx_addrs;
2830 mac->enable_rx = txgbe_enable_rx;
2831 mac->disable_rx = txgbe_disable_rx;
2832 mac->set_vmdq = txgbe_set_vmdq;
2833 mac->clear_vmdq = txgbe_clear_vmdq;
2834 mac->set_vfta = txgbe_set_vfta;
2835 mac->set_vlvf = txgbe_set_vlvf;
2836 mac->clear_vfta = txgbe_clear_vfta;
2837 mac->init_uta_tables = txgbe_init_uta_tables;
2838 mac->setup_sfp = txgbe_setup_sfp_modules;
2839 mac->set_mac_anti_spoofing = txgbe_set_mac_anti_spoofing;
2840 mac->set_ethertype_anti_spoofing = txgbe_set_ethertype_anti_spoofing;
2843 mac->fc_enable = txgbe_fc_enable;
2844 mac->setup_fc = txgbe_setup_fc;
2845 mac->fc_autoneg = txgbe_fc_autoneg;
2848 mac->get_link_capabilities = txgbe_get_link_capabilities_raptor;
2849 mac->check_link = txgbe_check_mac_link;
2850 mac->setup_pba = txgbe_set_pba;
2852 /* Manageability interface */
2853 mac->set_fw_drv_ver = txgbe_hic_set_drv_ver;
2854 mac->get_thermal_sensor_data = txgbe_get_thermal_sensor_data;
2855 mac->init_thermal_sensor_thresh = txgbe_init_thermal_sensor_thresh;
2857 mbx->init_params = txgbe_init_mbx_params_pf;
2858 mbx->read = txgbe_read_mbx_pf;
2859 mbx->write = txgbe_write_mbx_pf;
2860 mbx->check_for_msg = txgbe_check_for_msg_pf;
2861 mbx->check_for_ack = txgbe_check_for_ack_pf;
2862 mbx->check_for_rst = txgbe_check_for_rst_pf;
2865 rom->init_params = txgbe_init_eeprom_params;
2866 rom->read16 = txgbe_ee_read16;
2867 rom->readw_buffer = txgbe_ee_readw_buffer;
2868 rom->readw_sw = txgbe_ee_readw_sw;
2869 rom->read32 = txgbe_ee_read32;
2870 rom->write16 = txgbe_ee_write16;
2871 rom->writew_buffer = txgbe_ee_writew_buffer;
2872 rom->writew_sw = txgbe_ee_writew_sw;
2873 rom->write32 = txgbe_ee_write32;
2874 rom->validate_checksum = txgbe_validate_eeprom_checksum;
2875 rom->update_checksum = txgbe_update_eeprom_checksum;
2876 rom->calc_checksum = txgbe_calc_eeprom_checksum;
2878 mac->mcft_size = TXGBE_RAPTOR_MC_TBL_SIZE;
2879 mac->vft_size = TXGBE_RAPTOR_VFT_TBL_SIZE;
2880 mac->num_rar_entries = TXGBE_RAPTOR_RAR_ENTRIES;
2881 mac->rx_pb_size = TXGBE_RAPTOR_RX_PB_SIZE;
2882 mac->max_rx_queues = TXGBE_RAPTOR_MAX_RX_QUEUES;
2883 mac->max_tx_queues = TXGBE_RAPTOR_MAX_TX_QUEUES;
2889 * txgbe_get_link_capabilities_raptor - Determines link capabilities
2890 * @hw: pointer to hardware structure
2891 * @speed: pointer to link speed
2892 * @autoneg: true when autoneg or autotry is enabled
2894 * Determines the link capabilities by reading the AUTOC register.
2896 s32 txgbe_get_link_capabilities_raptor(struct txgbe_hw *hw,
2903 DEBUGFUNC("txgbe_get_link_capabilities_raptor");
2905 /* Check if 1G SFP module. */
2906 if (hw->phy.sfp_type == txgbe_sfp_type_1g_cu_core0 ||
2907 hw->phy.sfp_type == txgbe_sfp_type_1g_cu_core1 ||
2908 hw->phy.sfp_type == txgbe_sfp_type_1g_lx_core0 ||
2909 hw->phy.sfp_type == txgbe_sfp_type_1g_lx_core1 ||
2910 hw->phy.sfp_type == txgbe_sfp_type_1g_sx_core0 ||
2911 hw->phy.sfp_type == txgbe_sfp_type_1g_sx_core1) {
2912 *speed = TXGBE_LINK_SPEED_1GB_FULL;
2918 * Determine link capabilities based on the stored value of AUTOC,
2919 * which represents EEPROM defaults. If AUTOC value has not
2920 * been stored, use the current register values.
2922 if (hw->mac.orig_link_settings_stored)
2923 autoc = hw->mac.orig_autoc;
2925 autoc = hw->mac.autoc_read(hw);
2927 switch (autoc & TXGBE_AUTOC_LMS_MASK) {
2928 case TXGBE_AUTOC_LMS_1G_LINK_NO_AN:
2929 *speed = TXGBE_LINK_SPEED_1GB_FULL;
2933 case TXGBE_AUTOC_LMS_10G_LINK_NO_AN:
2934 *speed = TXGBE_LINK_SPEED_10GB_FULL;
2938 case TXGBE_AUTOC_LMS_1G_AN:
2939 *speed = TXGBE_LINK_SPEED_1GB_FULL;
2943 case TXGBE_AUTOC_LMS_10G:
2944 *speed = TXGBE_LINK_SPEED_10GB_FULL;
2948 case TXGBE_AUTOC_LMS_KX4_KX_KR:
2949 case TXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN:
2950 *speed = TXGBE_LINK_SPEED_UNKNOWN;
2951 if (autoc & TXGBE_AUTOC_KR_SUPP)
2952 *speed |= TXGBE_LINK_SPEED_10GB_FULL;
2953 if (autoc & TXGBE_AUTOC_KX4_SUPP)
2954 *speed |= TXGBE_LINK_SPEED_10GB_FULL;
2955 if (autoc & TXGBE_AUTOC_KX_SUPP)
2956 *speed |= TXGBE_LINK_SPEED_1GB_FULL;
2960 case TXGBE_AUTOC_LMS_KX4_KX_KR_SGMII:
2961 *speed = TXGBE_LINK_SPEED_100M_FULL;
2962 if (autoc & TXGBE_AUTOC_KR_SUPP)
2963 *speed |= TXGBE_LINK_SPEED_10GB_FULL;
2964 if (autoc & TXGBE_AUTOC_KX4_SUPP)
2965 *speed |= TXGBE_LINK_SPEED_10GB_FULL;
2966 if (autoc & TXGBE_AUTOC_KX_SUPP)
2967 *speed |= TXGBE_LINK_SPEED_1GB_FULL;
2971 case TXGBE_AUTOC_LMS_SGMII_1G_100M:
2972 *speed = TXGBE_LINK_SPEED_1GB_FULL |
2973 TXGBE_LINK_SPEED_100M_FULL |
2974 TXGBE_LINK_SPEED_10M_FULL;
2979 return TXGBE_ERR_LINK_SETUP;
2982 if (hw->phy.multispeed_fiber) {
2983 *speed |= TXGBE_LINK_SPEED_10GB_FULL |
2984 TXGBE_LINK_SPEED_1GB_FULL;
2986 /* QSFP must not enable full auto-negotiation
2987 * Limited autoneg is enabled at 1G
2989 if (hw->phy.media_type == txgbe_media_type_fiber_qsfp)
2999 * txgbe_get_media_type_raptor - Get media type
3000 * @hw: pointer to hardware structure
3002 * Returns the media type (fiber, copper, backplane)
3004 u32 txgbe_get_media_type_raptor(struct txgbe_hw *hw)
3008 DEBUGFUNC("txgbe_get_media_type_raptor");
3010 /* Detect if there is a copper PHY attached. */
3011 switch (hw->phy.type) {
3012 case txgbe_phy_cu_unknown:
3014 media_type = txgbe_media_type_copper;
3020 switch (hw->device_id) {
3021 case TXGBE_DEV_ID_RAPTOR_KR_KX_KX4:
3022 /* Default device ID is mezzanine card KX/KX4 */
3023 media_type = txgbe_media_type_backplane;
3025 case TXGBE_DEV_ID_RAPTOR_SFP:
3026 case TXGBE_DEV_ID_WX1820_SFP:
3027 media_type = txgbe_media_type_fiber;
3029 case TXGBE_DEV_ID_RAPTOR_QSFP:
3030 media_type = txgbe_media_type_fiber_qsfp;
3032 case TXGBE_DEV_ID_RAPTOR_XAUI:
3033 case TXGBE_DEV_ID_RAPTOR_SGMII:
3034 media_type = txgbe_media_type_copper;
3037 media_type = txgbe_media_type_unknown;
3045 * txgbe_start_mac_link_raptor - Setup MAC link settings
3046 * @hw: pointer to hardware structure
3047 * @autoneg_wait_to_complete: true when waiting for completion is needed
3049 * Configures link settings based on values in the txgbe_hw struct.
3050 * Restarts the link. Performs autonegotiation if needed.
3052 s32 txgbe_start_mac_link_raptor(struct txgbe_hw *hw,
3053 bool autoneg_wait_to_complete)
3056 bool got_lock = false;
3058 DEBUGFUNC("txgbe_start_mac_link_raptor");
3060 UNREFERENCED_PARAMETER(autoneg_wait_to_complete);
3062 /* reset_pipeline requires us to hold this lock as it writes to
3065 if (txgbe_verify_lesm_fw_enabled_raptor(hw)) {
3066 status = hw->mac.acquire_swfw_sync(hw, TXGBE_MNGSEM_SWPHY);
3074 txgbe_reset_pipeline_raptor(hw);
3077 hw->mac.release_swfw_sync(hw, TXGBE_MNGSEM_SWPHY);
3079 /* Add delay to filter out noises during initial link setup */
3087 * txgbe_disable_tx_laser_multispeed_fiber - Disable Tx laser
3088 * @hw: pointer to hardware structure
3090 * The base drivers may require better control over SFP+ module
3091 * PHY states. This includes selectively shutting down the Tx
3092 * laser on the PHY, effectively halting physical link.
3094 void txgbe_disable_tx_laser_multispeed_fiber(struct txgbe_hw *hw)
3096 u32 esdp_reg = rd32(hw, TXGBE_GPIODATA);
3098 /* Blocked by MNG FW so bail */
3099 if (txgbe_check_reset_blocked(hw))
3102 /* Disable Tx laser; allow 100us to go dark per spec */
3103 esdp_reg |= (TXGBE_GPIOBIT_0 | TXGBE_GPIOBIT_1);
3104 wr32(hw, TXGBE_GPIODATA, esdp_reg);
3110 * txgbe_enable_tx_laser_multispeed_fiber - Enable Tx laser
3111 * @hw: pointer to hardware structure
3113 * The base drivers may require better control over SFP+ module
3114 * PHY states. This includes selectively turning on the Tx
3115 * laser on the PHY, effectively starting physical link.
3117 void txgbe_enable_tx_laser_multispeed_fiber(struct txgbe_hw *hw)
3119 u32 esdp_reg = rd32(hw, TXGBE_GPIODATA);
3121 /* Enable Tx laser; allow 100ms to light up */
3122 esdp_reg &= ~(TXGBE_GPIOBIT_0 | TXGBE_GPIOBIT_1);
3123 wr32(hw, TXGBE_GPIODATA, esdp_reg);
3129 * txgbe_flap_tx_laser_multispeed_fiber - Flap Tx laser
3130 * @hw: pointer to hardware structure
3132 * When the driver changes the link speeds that it can support,
3133 * it sets autotry_restart to true to indicate that we need to
3134 * initiate a new autotry session with the link partner. To do
3135 * so, we set the speed then disable and re-enable the Tx laser, to
3136 * alert the link partner that it also needs to restart autotry on its
3137 * end. This is consistent with true clause 37 autoneg, which also
3138 * involves a loss of signal.
3140 void txgbe_flap_tx_laser_multispeed_fiber(struct txgbe_hw *hw)
3142 DEBUGFUNC("txgbe_flap_tx_laser_multispeed_fiber");
3144 /* Blocked by MNG FW so bail */
3145 if (txgbe_check_reset_blocked(hw))
3148 if (hw->mac.autotry_restart) {
3149 txgbe_disable_tx_laser_multispeed_fiber(hw);
3150 txgbe_enable_tx_laser_multispeed_fiber(hw);
3151 hw->mac.autotry_restart = false;
3156 * txgbe_set_hard_rate_select_speed - Set module link speed
3157 * @hw: pointer to hardware structure
3158 * @speed: link speed to set
3160 * Set module link speed via RS0/RS1 rate select pins.
3162 void txgbe_set_hard_rate_select_speed(struct txgbe_hw *hw,
3165 u32 esdp_reg = rd32(hw, TXGBE_GPIODATA);
3168 case TXGBE_LINK_SPEED_10GB_FULL:
3169 esdp_reg |= (TXGBE_GPIOBIT_4 | TXGBE_GPIOBIT_5);
3171 case TXGBE_LINK_SPEED_1GB_FULL:
3172 esdp_reg &= ~(TXGBE_GPIOBIT_4 | TXGBE_GPIOBIT_5);
3175 DEBUGOUT("Invalid fixed module speed\n");
3179 wr32(hw, TXGBE_GPIODATA, esdp_reg);
3184 * txgbe_setup_mac_link_smartspeed - Set MAC link speed using SmartSpeed
3185 * @hw: pointer to hardware structure
3186 * @speed: new link speed
3187 * @autoneg_wait_to_complete: true when waiting for completion is needed
3189 * Implements the Intel SmartSpeed algorithm.
3191 s32 txgbe_setup_mac_link_smartspeed(struct txgbe_hw *hw,
3193 bool autoneg_wait_to_complete)
3196 u32 link_speed = TXGBE_LINK_SPEED_UNKNOWN;
3198 bool link_up = false;
3199 u32 autoc_reg = rd32_epcs(hw, SR_AN_MMD_ADV_REG1);
3201 DEBUGFUNC("txgbe_setup_mac_link_smartspeed");
3203 /* Set autoneg_advertised value based on input link speed */
3204 hw->phy.autoneg_advertised = 0;
3206 if (speed & TXGBE_LINK_SPEED_10GB_FULL)
3207 hw->phy.autoneg_advertised |= TXGBE_LINK_SPEED_10GB_FULL;
3209 if (speed & TXGBE_LINK_SPEED_1GB_FULL)
3210 hw->phy.autoneg_advertised |= TXGBE_LINK_SPEED_1GB_FULL;
3212 if (speed & TXGBE_LINK_SPEED_100M_FULL)
3213 hw->phy.autoneg_advertised |= TXGBE_LINK_SPEED_100M_FULL;
3216 * Implement Intel SmartSpeed algorithm. SmartSpeed will reduce the
3217 * autoneg advertisement if link is unable to be established at the
3218 * highest negotiated rate. This can sometimes happen due to integrity
3219 * issues with the physical media connection.
3222 /* First, try to get link with full advertisement */
3223 hw->phy.smart_speed_active = false;
3224 for (j = 0; j < TXGBE_SMARTSPEED_MAX_RETRIES; j++) {
3225 status = txgbe_setup_mac_link(hw, speed,
3226 autoneg_wait_to_complete);
3231 * Wait for the controller to acquire link. Per IEEE 802.3ap,
3232 * Section 73.10.2, we may have to wait up to 500ms if KR is
3233 * attempted, or 200ms if KX/KX4/BX/BX4 is attempted, per
3234 * Table 9 in the AN MAS.
3236 for (i = 0; i < 5; i++) {
3239 /* If we have link, just jump out */
3240 status = hw->mac.check_link(hw, &link_speed, &link_up,
3251 * We didn't get link. If we advertised KR plus one of KX4/KX
3252 * (or BX4/BX), then disable KR and try again.
3254 if (((autoc_reg & TXGBE_AUTOC_KR_SUPP) == 0) ||
3255 ((autoc_reg & TXGBE_AUTOC_KX_SUPP) == 0 &&
3256 (autoc_reg & TXGBE_AUTOC_KX4_SUPP) == 0))
3259 /* Turn SmartSpeed on to disable KR support */
3260 hw->phy.smart_speed_active = true;
3261 status = txgbe_setup_mac_link(hw, speed,
3262 autoneg_wait_to_complete);
3267 * Wait for the controller to acquire link. 600ms will allow for
3268 * the AN link_fail_inhibit_timer as well for multiple cycles of
3269 * parallel detect, both 10g and 1g. This allows for the maximum
3270 * connect attempts as defined in the AN MAS table 73-7.
3272 for (i = 0; i < 6; i++) {
3275 /* If we have link, just jump out */
3276 status = hw->mac.check_link(hw, &link_speed, &link_up, false);
3284 /* We didn't get link. Turn SmartSpeed back off. */
3285 hw->phy.smart_speed_active = false;
3286 status = txgbe_setup_mac_link(hw, speed,
3287 autoneg_wait_to_complete);
3290 if (link_up && link_speed == TXGBE_LINK_SPEED_1GB_FULL)
3291 DEBUGOUT("Smartspeed has downgraded the link speed "
3292 "from the maximum advertised\n");
3297 * txgbe_setup_mac_link - Set MAC link speed
3298 * @hw: pointer to hardware structure
3299 * @speed: new link speed
3300 * @autoneg_wait_to_complete: true when waiting for completion is needed
3302 * Set the link speed in the AUTOC register and restarts link.
3304 s32 txgbe_setup_mac_link(struct txgbe_hw *hw,
3306 bool autoneg_wait_to_complete)
3308 bool autoneg = false;
3311 u64 autoc = hw->mac.autoc_read(hw);
3312 u64 pma_pmd_10gs = autoc & TXGBE_AUTOC_10GS_PMA_PMD_MASK;
3313 u64 pma_pmd_1g = autoc & TXGBE_AUTOC_1G_PMA_PMD_MASK;
3314 u64 link_mode = autoc & TXGBE_AUTOC_LMS_MASK;
3315 u64 current_autoc = autoc;
3319 u32 link_capabilities = TXGBE_LINK_SPEED_UNKNOWN;
3321 DEBUGFUNC("txgbe_setup_mac_link");
3323 /* Check to see if speed passed in is supported. */
3324 status = hw->mac.get_link_capabilities(hw,
3325 &link_capabilities, &autoneg);
3329 speed &= link_capabilities;
3330 if (speed == TXGBE_LINK_SPEED_UNKNOWN)
3331 return TXGBE_ERR_LINK_SETUP;
3333 /* Use stored value (EEPROM defaults) of AUTOC to find KR/KX4 support*/
3334 if (hw->mac.orig_link_settings_stored)
3335 orig_autoc = hw->mac.orig_autoc;
3339 link_mode = autoc & TXGBE_AUTOC_LMS_MASK;
3340 pma_pmd_1g = autoc & TXGBE_AUTOC_1G_PMA_PMD_MASK;
3342 if (link_mode == TXGBE_AUTOC_LMS_KX4_KX_KR ||
3343 link_mode == TXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
3344 link_mode == TXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
3345 /* Set KX4/KX/KR support according to speed requested */
3346 autoc &= ~(TXGBE_AUTOC_KX_SUPP |
3347 TXGBE_AUTOC_KX4_SUPP |
3348 TXGBE_AUTOC_KR_SUPP);
3349 if (speed & TXGBE_LINK_SPEED_10GB_FULL) {
3350 if (orig_autoc & TXGBE_AUTOC_KX4_SUPP)
3351 autoc |= TXGBE_AUTOC_KX4_SUPP;
3352 if ((orig_autoc & TXGBE_AUTOC_KR_SUPP) &&
3353 !hw->phy.smart_speed_active)
3354 autoc |= TXGBE_AUTOC_KR_SUPP;
3356 if (speed & TXGBE_LINK_SPEED_1GB_FULL)
3357 autoc |= TXGBE_AUTOC_KX_SUPP;
3358 } else if ((pma_pmd_1g == TXGBE_AUTOC_1G_SFI) &&
3359 (link_mode == TXGBE_AUTOC_LMS_1G_LINK_NO_AN ||
3360 link_mode == TXGBE_AUTOC_LMS_1G_AN)) {
3361 /* Switch from 1G SFI to 10G SFI if requested */
3362 if (speed == TXGBE_LINK_SPEED_10GB_FULL &&
3363 pma_pmd_10gs == TXGBE_AUTOC_10GS_SFI) {
3364 autoc &= ~TXGBE_AUTOC_LMS_MASK;
3365 autoc |= TXGBE_AUTOC_LMS_10G;
3367 } else if ((pma_pmd_10gs == TXGBE_AUTOC_10GS_SFI) &&
3368 (link_mode == TXGBE_AUTOC_LMS_10G)) {
3369 /* Switch from 10G SFI to 1G SFI if requested */
3370 if (speed == TXGBE_LINK_SPEED_1GB_FULL &&
3371 pma_pmd_1g == TXGBE_AUTOC_1G_SFI) {
3372 autoc &= ~TXGBE_AUTOC_LMS_MASK;
3373 if (autoneg || hw->phy.type == txgbe_phy_qsfp_intel)
3374 autoc |= TXGBE_AUTOC_LMS_1G_AN;
3376 autoc |= TXGBE_AUTOC_LMS_1G_LINK_NO_AN;
3380 if (autoc == current_autoc)
3383 autoc &= ~TXGBE_AUTOC_SPEED_MASK;
3384 autoc |= TXGBE_AUTOC_SPEED(speed);
3385 autoc |= (autoneg ? TXGBE_AUTOC_AUTONEG : 0);
3388 hw->mac.autoc_write(hw, autoc);
3390 /* Only poll for autoneg to complete if specified to do so */
3391 if (autoneg_wait_to_complete) {
3392 if (link_mode == TXGBE_AUTOC_LMS_KX4_KX_KR ||
3393 link_mode == TXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
3394 link_mode == TXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
3395 links_reg = 0; /*Just in case Autoneg time=0*/
3396 for (i = 0; i < TXGBE_AUTO_NEG_TIME; i++) {
3397 links_reg = rd32(hw, TXGBE_PORTSTAT);
3398 if (links_reg & TXGBE_PORTSTAT_UP)
3402 if (!(links_reg & TXGBE_PORTSTAT_UP)) {
3403 status = TXGBE_ERR_AUTONEG_NOT_COMPLETE;
3404 DEBUGOUT("Autoneg did not complete.\n");
3409 /* Add delay to filter out noises during initial link setup */
3416 * txgbe_setup_copper_link_raptor - Set the PHY autoneg advertised field
3417 * @hw: pointer to hardware structure
3418 * @speed: new link speed
3419 * @autoneg_wait_to_complete: true if waiting is needed to complete
3421 * Restarts link on PHY and MAC based on settings passed in.
3423 static s32 txgbe_setup_copper_link_raptor(struct txgbe_hw *hw,
3425 bool autoneg_wait_to_complete)
3429 DEBUGFUNC("txgbe_setup_copper_link_raptor");
3431 /* Setup the PHY according to input speed */
3432 status = hw->phy.setup_link_speed(hw, speed,
3433 autoneg_wait_to_complete);
3435 txgbe_start_mac_link_raptor(hw, autoneg_wait_to_complete);
3441 txgbe_check_flash_load(struct txgbe_hw *hw, u32 check_bit)
3446 /* if there's flash existing */
3447 if (!(rd32(hw, TXGBE_SPISTAT) & TXGBE_SPISTAT_BPFLASH)) {
3448 /* wait hw load flash done */
3449 for (i = 0; i < 10; i++) {
3450 reg = rd32(hw, TXGBE_ILDRSTAT);
3451 if (!(reg & check_bit)) {
3458 err = TXGBE_ERR_FLASH_LOADING_FAILED;
3464 txgbe_reset_misc(struct txgbe_hw *hw)
3469 wr32(hw, TXGBE_ISBADDRL, hw->isb_dma & 0x00000000FFFFFFFF);
3470 wr32(hw, TXGBE_ISBADDRH, hw->isb_dma >> 32);
3472 value = rd32_epcs(hw, SR_XS_PCS_CTRL2);
3473 if ((value & 0x3) != SR_PCS_CTRL2_TYPE_SEL_X)
3474 hw->link_status = TXGBE_LINK_STATUS_NONE;
3476 /* receive packets that size > 2048 */
3477 wr32m(hw, TXGBE_MACRXCFG,
3478 TXGBE_MACRXCFG_JUMBO, TXGBE_MACRXCFG_JUMBO);
3480 wr32m(hw, TXGBE_FRMSZ, TXGBE_FRMSZ_MAX_MASK,
3481 TXGBE_FRMSZ_MAX(TXGBE_FRAME_SIZE_DFT));
3483 /* clear counters on read */
3484 wr32m(hw, TXGBE_MACCNTCTL,
3485 TXGBE_MACCNTCTL_RC, TXGBE_MACCNTCTL_RC);
3487 wr32m(hw, TXGBE_RXFCCFG,
3488 TXGBE_RXFCCFG_FC, TXGBE_RXFCCFG_FC);
3489 wr32m(hw, TXGBE_TXFCCFG,
3490 TXGBE_TXFCCFG_FC, TXGBE_TXFCCFG_FC);
3492 wr32m(hw, TXGBE_MACRXFLT,
3493 TXGBE_MACRXFLT_PROMISC, TXGBE_MACRXFLT_PROMISC);
3495 wr32m(hw, TXGBE_RSTSTAT,
3496 TXGBE_RSTSTAT_TMRINIT_MASK, TXGBE_RSTSTAT_TMRINIT(30));
3498 /* errata 4: initialize mng flex tbl and wakeup flex tbl*/
3499 wr32(hw, TXGBE_MNGFLEXSEL, 0);
3500 for (i = 0; i < 16; i++) {
3501 wr32(hw, TXGBE_MNGFLEXDWL(i), 0);
3502 wr32(hw, TXGBE_MNGFLEXDWH(i), 0);
3503 wr32(hw, TXGBE_MNGFLEXMSK(i), 0);
3505 wr32(hw, TXGBE_LANFLEXSEL, 0);
3506 for (i = 0; i < 16; i++) {
3507 wr32(hw, TXGBE_LANFLEXDWL(i), 0);
3508 wr32(hw, TXGBE_LANFLEXDWH(i), 0);
3509 wr32(hw, TXGBE_LANFLEXMSK(i), 0);
3512 /* set pause frame dst mac addr */
3513 wr32(hw, TXGBE_RXPBPFCDMACL, 0xC2000001);
3514 wr32(hw, TXGBE_RXPBPFCDMACH, 0x0180);
3516 hw->mac.init_thermal_sensor_thresh(hw);
3518 /* enable mac transmitter */
3519 wr32m(hw, TXGBE_MACTXCFG, TXGBE_MACTXCFG_TXE, TXGBE_MACTXCFG_TXE);
3521 for (i = 0; i < 4; i++)
3522 wr32m(hw, TXGBE_IVAR(i), 0x80808080, 0);
3526 * txgbe_reset_hw - Perform hardware reset
3527 * @hw: pointer to hardware structure
3529 * Resets the hardware by resetting the transmit and receive units, masks
3530 * and clears all interrupts, perform a PHY reset, and perform a link (MAC)
3533 s32 txgbe_reset_hw(struct txgbe_hw *hw)
3538 DEBUGFUNC("txgbe_reset_hw");
3540 /* Call adapter stop to disable tx/rx and clear interrupts */
3541 status = hw->mac.stop_hw(hw);
3545 /* flush pending Tx transactions */
3546 txgbe_clear_tx_pending(hw);
3548 /* Identify PHY and related function pointers */
3549 status = hw->phy.init(hw);
3550 if (status == TXGBE_ERR_SFP_NOT_SUPPORTED)
3553 /* Setup SFP module if there is one present. */
3554 if (hw->phy.sfp_setup_needed) {
3555 status = hw->mac.setup_sfp(hw);
3556 hw->phy.sfp_setup_needed = false;
3558 if (status == TXGBE_ERR_SFP_NOT_SUPPORTED)
3562 if (!hw->phy.reset_disable)
3565 /* remember AUTOC from before we reset */
3566 autoc = hw->mac.autoc_read(hw);
3570 * Issue global reset to the MAC. Needs to be SW reset if link is up.
3571 * If link reset is used when link is up, it might reset the PHY when
3572 * mng is using it. If link is down or the flag to force full link
3573 * reset is set, then perform link reset.
3575 if (txgbe_mng_present(hw)) {
3576 txgbe_hic_reset(hw);
3578 wr32(hw, TXGBE_RST, TXGBE_RST_LAN(hw->bus.lan_id));
3583 txgbe_reset_misc(hw);
3585 if (hw->bus.lan_id == 0) {
3586 status = txgbe_check_flash_load(hw,
3587 TXGBE_ILDRSTAT_SWRST_LAN0);
3589 status = txgbe_check_flash_load(hw,
3590 TXGBE_ILDRSTAT_SWRST_LAN1);
3598 * Double resets are required for recovery from certain error
3599 * conditions. Between resets, it is necessary to stall to
3600 * allow time for any pending HW events to complete.
3602 if (hw->mac.flags & TXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
3603 hw->mac.flags &= ~TXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
3608 * Store the original AUTOC/AUTOC2 values if they have not been
3609 * stored off yet. Otherwise restore the stored original
3610 * values since the reset operation sets back to defaults.
3612 if (!hw->mac.orig_link_settings_stored) {
3613 hw->mac.orig_autoc = hw->mac.autoc_read(hw);
3614 hw->mac.autoc_write(hw, hw->mac.orig_autoc);
3615 hw->mac.orig_link_settings_stored = true;
3617 hw->mac.orig_autoc = autoc;
3620 /* Store the permanent mac address */
3621 hw->mac.get_mac_addr(hw, hw->mac.perm_addr);
3624 * Store MAC address from RAR0, clear receive address registers, and
3625 * clear the multicast table. Also reset num_rar_entries to 128,
3626 * since we modify this value when programming the SAN MAC address.
3628 hw->mac.num_rar_entries = 128;
3629 hw->mac.init_rx_addrs(hw);
3631 /* Store the permanent SAN mac address */
3632 hw->mac.get_san_mac_addr(hw, hw->mac.san_addr);
3634 /* Add the SAN MAC address to the RAR only if it's a valid address */
3635 if (txgbe_validate_mac_addr(hw->mac.san_addr) == 0) {
3636 /* Save the SAN MAC RAR index */
3637 hw->mac.san_mac_rar_index = hw->mac.num_rar_entries - 1;
3639 hw->mac.set_rar(hw, hw->mac.san_mac_rar_index,
3640 hw->mac.san_addr, 0, true);
3642 /* clear VMDq pool/queue selection for this RAR */
3643 hw->mac.clear_vmdq(hw, hw->mac.san_mac_rar_index,
3646 /* Reserve the last RAR for the SAN MAC address */
3647 hw->mac.num_rar_entries--;
3650 /* Store the alternative WWNN/WWPN prefix */
3651 hw->mac.get_wwn_prefix(hw, &hw->mac.wwnn_prefix,
3652 &hw->mac.wwpn_prefix);
3658 * txgbe_fdir_check_cmd_complete - poll to check whether FDIRPICMD is complete
3659 * @hw: pointer to hardware structure
3660 * @fdircmd: current value of FDIRCMD register
3662 static s32 txgbe_fdir_check_cmd_complete(struct txgbe_hw *hw, u32 *fdircmd)
3666 for (i = 0; i < TXGBE_FDIRCMD_CMD_POLL; i++) {
3667 *fdircmd = rd32(hw, TXGBE_FDIRPICMD);
3668 if (!(*fdircmd & TXGBE_FDIRPICMD_OP_MASK))
3673 return TXGBE_ERR_FDIR_CMD_INCOMPLETE;
3677 * txgbe_reinit_fdir_tables - Reinitialize Flow Director tables.
3678 * @hw: pointer to hardware structure
3680 s32 txgbe_reinit_fdir_tables(struct txgbe_hw *hw)
3684 u32 fdirctrl = rd32(hw, TXGBE_FDIRCTL);
3686 fdirctrl &= ~TXGBE_FDIRCTL_INITDONE;
3688 DEBUGFUNC("txgbe_reinit_fdir_tables");
3691 * Before starting reinitialization process,
3692 * FDIRPICMD.OP must be zero.
3694 err = txgbe_fdir_check_cmd_complete(hw, &fdircmd);
3696 DEBUGOUT("Flow Director previous command did not complete, aborting table re-initialization.\n");
3700 wr32(hw, TXGBE_FDIRFREE, 0);
3703 * adapters flow director init flow cannot be restarted,
3704 * Workaround silicon errata by performing the following steps
3705 * before re-writing the FDIRCTL control register with the same value.
3706 * - write 1 to bit 8 of FDIRPICMD register &
3707 * - write 0 to bit 8 of FDIRPICMD register
3709 wr32m(hw, TXGBE_FDIRPICMD, TXGBE_FDIRPICMD_CLR, TXGBE_FDIRPICMD_CLR);
3711 wr32m(hw, TXGBE_FDIRPICMD, TXGBE_FDIRPICMD_CLR, 0);
3714 * Clear FDIR Hash register to clear any leftover hashes
3715 * waiting to be programmed.
3717 wr32(hw, TXGBE_FDIRPIHASH, 0x00);
3720 wr32(hw, TXGBE_FDIRCTL, fdirctrl);
3723 /* Poll init-done after we write FDIRCTL register */
3724 for (i = 0; i < TXGBE_FDIR_INIT_DONE_POLL; i++) {
3725 if (rd32m(hw, TXGBE_FDIRCTL, TXGBE_FDIRCTL_INITDONE))
3729 if (i >= TXGBE_FDIR_INIT_DONE_POLL) {
3730 DEBUGOUT("Flow Director Signature poll time exceeded!\n");
3731 return TXGBE_ERR_FDIR_REINIT_FAILED;
3734 /* Clear FDIR statistics registers (read to clear) */
3735 rd32(hw, TXGBE_FDIRUSED);
3736 rd32(hw, TXGBE_FDIRFAIL);
3737 rd32(hw, TXGBE_FDIRMATCH);
3738 rd32(hw, TXGBE_FDIRMISS);
3739 rd32(hw, TXGBE_FDIRLEN);
3745 * txgbe_start_hw_raptor - Prepare hardware for Tx/Rx
3746 * @hw: pointer to hardware structure
3748 * Starts the hardware using the generic start_hw function
3749 * and the generation start_hw function.
3750 * Then performs revision-specific operations, if any.
3752 s32 txgbe_start_hw_raptor(struct txgbe_hw *hw)
3756 DEBUGFUNC("txgbe_start_hw_raptor");
3758 err = txgbe_start_hw(hw);
3762 err = txgbe_start_hw_gen2(hw);
3766 /* We need to run link autotry after the driver loads */
3767 hw->mac.autotry_restart = true;
3774 * txgbe_enable_rx_dma_raptor - Enable the Rx DMA unit
3775 * @hw: pointer to hardware structure
3776 * @regval: register value to write to RXCTRL
3778 * Enables the Rx DMA unit
3780 s32 txgbe_enable_rx_dma_raptor(struct txgbe_hw *hw, u32 regval)
3782 DEBUGFUNC("txgbe_enable_rx_dma_raptor");
3785 * Workaround silicon errata when enabling the Rx datapath.
3786 * If traffic is incoming before we enable the Rx unit, it could hang
3787 * the Rx DMA unit. Therefore, make sure the security engine is
3788 * completely disabled prior to enabling the Rx unit.
3791 hw->mac.disable_sec_rx_path(hw);
3793 if (regval & TXGBE_PBRXCTL_ENA)
3794 txgbe_enable_rx(hw);
3796 txgbe_disable_rx(hw);
3798 hw->mac.enable_sec_rx_path(hw);
3804 * txgbe_verify_lesm_fw_enabled_raptor - Checks LESM FW module state.
3805 * @hw: pointer to hardware structure
3807 * Returns true if the LESM FW module is present and enabled. Otherwise
3808 * returns false. Smart Speed must be disabled if LESM FW module is enabled.
3810 bool txgbe_verify_lesm_fw_enabled_raptor(struct txgbe_hw *hw)
3812 bool lesm_enabled = false;
3813 u16 fw_offset, fw_lesm_param_offset, fw_lesm_state;
3816 DEBUGFUNC("txgbe_verify_lesm_fw_enabled_raptor");
3818 /* get the offset to the Firmware Module block */
3819 status = hw->rom.read16(hw, TXGBE_FW_PTR, &fw_offset);
3821 if (status != 0 || fw_offset == 0 || fw_offset == 0xFFFF)
3824 /* get the offset to the LESM Parameters block */
3825 status = hw->rom.read16(hw, (fw_offset +
3826 TXGBE_FW_LESM_PARAMETERS_PTR),
3827 &fw_lesm_param_offset);
3830 fw_lesm_param_offset == 0 || fw_lesm_param_offset == 0xFFFF)
3833 /* get the LESM state word */
3834 status = hw->rom.read16(hw, (fw_lesm_param_offset +
3835 TXGBE_FW_LESM_STATE_1),
3838 if (status == 0 && (fw_lesm_state & TXGBE_FW_LESM_STATE_ENABLED))
3839 lesm_enabled = true;
3842 lesm_enabled = false;
3843 return lesm_enabled;
3847 * txgbe_reset_pipeline_raptor - perform pipeline reset
3849 * @hw: pointer to hardware structure
3851 * Reset pipeline by asserting Restart_AN together with LMS change to ensure
3852 * full pipeline reset. This function assumes the SW/FW lock is held.
3854 s32 txgbe_reset_pipeline_raptor(struct txgbe_hw *hw)
3859 autoc = hw->mac.autoc_read(hw);
3861 /* Enable link if disabled in NVM */
3862 if (autoc & TXGBE_AUTOC_LINK_DIA_MASK)
3863 autoc &= ~TXGBE_AUTOC_LINK_DIA_MASK;
3865 autoc |= TXGBE_AUTOC_AN_RESTART;
3866 /* Write AUTOC register with toggled LMS[2] bit and Restart_AN */
3867 hw->mac.autoc_write(hw, autoc ^ TXGBE_AUTOC_LMS_AN);
3869 /* Write AUTOC register with original LMS field and Restart_AN */
3870 hw->mac.autoc_write(hw, autoc);