1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2015-2020
5 #include "txgbe_type.h"
10 #include "txgbe_eeprom.h"
11 #include "txgbe_mng.h"
14 #define TXGBE_RAPTOR_MAX_TX_QUEUES 128
15 #define TXGBE_RAPTOR_MAX_RX_QUEUES 128
16 #define TXGBE_RAPTOR_RAR_ENTRIES 128
17 #define TXGBE_RAPTOR_MC_TBL_SIZE 128
18 #define TXGBE_RAPTOR_VFT_TBL_SIZE 128
19 #define TXGBE_RAPTOR_RX_PB_SIZE 512 /*KB*/
21 static s32 txgbe_setup_copper_link_raptor(struct txgbe_hw *hw,
23 bool autoneg_wait_to_complete);
25 static s32 txgbe_mta_vector(struct txgbe_hw *hw, u8 *mc_addr);
26 static s32 txgbe_get_san_mac_addr_offset(struct txgbe_hw *hw,
30 * txgbe_device_supports_autoneg_fc - Check if device supports autonegotiation
32 * @hw: pointer to hardware structure
34 * This function returns true if the device supports flow control
35 * autonegotiation, and false if it does not.
38 bool txgbe_device_supports_autoneg_fc(struct txgbe_hw *hw)
40 bool supported = false;
44 DEBUGFUNC("txgbe_device_supports_autoneg_fc");
46 switch (hw->phy.media_type) {
47 case txgbe_media_type_fiber_qsfp:
48 case txgbe_media_type_fiber:
49 hw->mac.check_link(hw, &speed, &link_up, false);
50 /* if link is down, assume supported */
52 supported = speed == TXGBE_LINK_SPEED_1GB_FULL ?
58 case txgbe_media_type_backplane:
61 case txgbe_media_type_copper:
62 /* only some copper devices support flow control autoneg */
63 switch (hw->subsystem_device_id & 0xFF) {
64 case TXGBE_DEV_ID_XAUI:
65 case TXGBE_DEV_ID_SGMII:
76 DEBUGOUT("Device %x does not support flow control autoneg",
82 * txgbe_setup_fc - Set up flow control
83 * @hw: pointer to hardware structure
85 * Called at init time to set up flow control.
87 s32 txgbe_setup_fc(struct txgbe_hw *hw)
95 DEBUGFUNC("txgbe_setup_fc");
97 /* Validate the requested mode */
98 if (hw->fc.strict_ieee && hw->fc.requested_mode == txgbe_fc_rx_pause) {
99 DEBUGOUT("txgbe_fc_rx_pause not valid in strict IEEE mode\n");
100 err = TXGBE_ERR_INVALID_LINK_SETTINGS;
105 * 10gig parts do not have a word in the EEPROM to determine the
106 * default flow control setting, so we explicitly set it to full.
108 if (hw->fc.requested_mode == txgbe_fc_default)
109 hw->fc.requested_mode = txgbe_fc_full;
112 * The possible values of fc.requested_mode are:
113 * 0: Flow control is completely disabled
114 * 1: Rx flow control is enabled (we can receive pause frames,
115 * but not send pause frames).
116 * 2: Tx flow control is enabled (we can send pause frames but
117 * we do not support receiving pause frames).
118 * 3: Both Rx and Tx flow control (symmetric) are enabled.
121 switch (hw->fc.requested_mode) {
123 /* Flow control completely disabled by software override. */
125 case txgbe_fc_tx_pause:
127 * Tx Flow control is enabled, and Rx Flow control is
128 * disabled by software override.
130 reg |= SR_MII_MMD_AN_ADV_PAUSE_ASM;
131 reg_bp |= SR_AN_MMD_ADV_REG1_PAUSE_ASM;
133 case txgbe_fc_rx_pause:
135 * Rx Flow control is enabled and Tx Flow control is
136 * disabled by software override. Since there really
137 * isn't a way to advertise that we are capable of RX
138 * Pause ONLY, we will advertise that we support both
139 * symmetric and asymmetric Rx PAUSE, as such we fall
140 * through to the fc_full statement. Later, we will
141 * disable the adapter's ability to send PAUSE frames.
144 /* Flow control (both Rx and Tx) is enabled by SW override. */
145 reg |= SR_MII_MMD_AN_ADV_PAUSE_SYM |
146 SR_MII_MMD_AN_ADV_PAUSE_ASM;
147 reg_bp |= SR_AN_MMD_ADV_REG1_PAUSE_SYM |
148 SR_AN_MMD_ADV_REG1_PAUSE_ASM;
151 DEBUGOUT("Flow control param set incorrectly\n");
152 err = TXGBE_ERR_CONFIG;
157 * Enable auto-negotiation between the MAC & PHY;
158 * the MAC will advertise clause 37 flow control.
160 value = rd32_epcs(hw, SR_MII_MMD_AN_ADV);
161 value = (value & ~(SR_MII_MMD_AN_ADV_PAUSE_ASM |
162 SR_MII_MMD_AN_ADV_PAUSE_SYM)) | reg;
163 wr32_epcs(hw, SR_MII_MMD_AN_ADV, value);
166 * AUTOC restart handles negotiation of 1G and 10G on backplane
167 * and copper. There is no need to set the PCS1GCTL register.
170 if (hw->phy.media_type == txgbe_media_type_backplane) {
171 value = rd32_epcs(hw, SR_AN_MMD_ADV_REG1);
172 value = (value & ~(SR_AN_MMD_ADV_REG1_PAUSE_ASM |
173 SR_AN_MMD_ADV_REG1_PAUSE_SYM)) |
175 wr32_epcs(hw, SR_AN_MMD_ADV_REG1, value);
176 } else if ((hw->phy.media_type == txgbe_media_type_copper) &&
177 (txgbe_device_supports_autoneg_fc(hw))) {
178 hw->phy.write_reg(hw, TXGBE_MD_AUTO_NEG_ADVT,
179 TXGBE_MD_DEV_AUTO_NEG, reg_cu);
182 DEBUGOUT("Set up FC; reg = 0x%08X\n", reg);
188 * txgbe_start_hw - Prepare hardware for Tx/Rx
189 * @hw: pointer to hardware structure
191 * Starts the hardware by filling the bus info structure and media type, clears
192 * all on chip counters, initializes receive address registers, multicast
193 * table, VLAN filter table, calls routine to set up link and flow control
194 * settings, and leaves transmit and receive units disabled and uninitialized
196 s32 txgbe_start_hw(struct txgbe_hw *hw)
201 DEBUGFUNC("txgbe_start_hw");
203 /* Set the media type */
204 hw->phy.media_type = hw->phy.get_media_type(hw);
206 /* Clear the VLAN filter table */
207 hw->mac.clear_vfta(hw);
209 /* Clear statistics registers */
210 hw->mac.clear_hw_cntrs(hw);
212 /* Setup flow control */
213 err = txgbe_setup_fc(hw);
214 if (err != 0 && err != TXGBE_NOT_IMPLEMENTED) {
215 DEBUGOUT("Flow control setup failed, returning %d\n", err);
219 /* Cache bit indicating need for crosstalk fix */
220 switch (hw->mac.type) {
221 case txgbe_mac_raptor:
222 hw->mac.get_device_caps(hw, &device_caps);
223 if (device_caps & TXGBE_DEVICE_CAPS_NO_CROSSTALK_WR)
224 hw->need_crosstalk_fix = false;
226 hw->need_crosstalk_fix = true;
229 hw->need_crosstalk_fix = false;
233 /* Clear adapter stopped flag */
234 hw->adapter_stopped = false;
240 * txgbe_start_hw_gen2 - Init sequence for common device family
241 * @hw: pointer to hw structure
243 * Performs the init sequence common to the second generation
246 s32 txgbe_start_hw_gen2(struct txgbe_hw *hw)
250 /* Clear the rate limiters */
251 for (i = 0; i < hw->mac.max_tx_queues; i++) {
252 wr32(hw, TXGBE_ARBPOOLIDX, i);
253 wr32(hw, TXGBE_ARBTXRATE, 0);
257 /* We need to run link autotry after the driver loads */
258 hw->mac.autotry_restart = true;
264 * txgbe_init_hw - Generic hardware initialization
265 * @hw: pointer to hardware structure
267 * Initialize the hardware by resetting the hardware, filling the bus info
268 * structure and media type, clears all on chip counters, initializes receive
269 * address registers, multicast table, VLAN filter table, calls routine to set
270 * up link and flow control settings, and leaves transmit and receive units
271 * disabled and uninitialized
273 s32 txgbe_init_hw(struct txgbe_hw *hw)
277 DEBUGFUNC("txgbe_init_hw");
279 /* Get firmware version */
280 hw->phy.get_fw_version(hw, &hw->fw_version);
282 /* Reset the hardware */
283 status = hw->mac.reset_hw(hw);
284 if (status == 0 || status == TXGBE_ERR_SFP_NOT_PRESENT) {
286 status = hw->mac.start_hw(hw);
290 DEBUGOUT("Failed to initialize HW, STATUS = %d\n", status);
296 * txgbe_clear_hw_cntrs - Generic clear hardware counters
297 * @hw: pointer to hardware structure
299 * Clears all hardware statistics counters by reading them from the hardware
300 * Statistics counters are clear on read.
302 s32 txgbe_clear_hw_cntrs(struct txgbe_hw *hw)
306 DEBUGFUNC("txgbe_clear_hw_cntrs");
309 /* don't write clear queue stats */
310 for (i = 0; i < TXGBE_MAX_QP; i++) {
311 hw->qp_last[i].rx_qp_packets = 0;
312 hw->qp_last[i].tx_qp_packets = 0;
313 hw->qp_last[i].rx_qp_bytes = 0;
314 hw->qp_last[i].tx_qp_bytes = 0;
315 hw->qp_last[i].rx_qp_mc_packets = 0;
319 for (i = 0; i < TXGBE_MAX_UP; i++) {
320 rd32(hw, TXGBE_PBRXUPXON(i));
321 rd32(hw, TXGBE_PBRXUPXOFF(i));
322 rd32(hw, TXGBE_PBTXUPXON(i));
323 rd32(hw, TXGBE_PBTXUPXOFF(i));
324 rd32(hw, TXGBE_PBTXUPOFF(i));
326 rd32(hw, TXGBE_PBRXMISS(i));
328 rd32(hw, TXGBE_PBRXLNKXON);
329 rd32(hw, TXGBE_PBRXLNKXOFF);
330 rd32(hw, TXGBE_PBTXLNKXON);
331 rd32(hw, TXGBE_PBTXLNKXOFF);
334 rd32(hw, TXGBE_DMARXPKT);
335 rd32(hw, TXGBE_DMATXPKT);
337 rd64(hw, TXGBE_DMARXOCTL);
338 rd64(hw, TXGBE_DMATXOCTL);
341 rd64(hw, TXGBE_MACRXERRCRCL);
342 rd64(hw, TXGBE_MACRXMPKTL);
343 rd64(hw, TXGBE_MACTXMPKTL);
345 rd64(hw, TXGBE_MACRXPKTL);
346 rd64(hw, TXGBE_MACTXPKTL);
347 rd64(hw, TXGBE_MACRXGBOCTL);
349 rd64(hw, TXGBE_MACRXOCTL);
350 rd32(hw, TXGBE_MACTXOCTL);
352 rd64(hw, TXGBE_MACRX1TO64L);
353 rd64(hw, TXGBE_MACRX65TO127L);
354 rd64(hw, TXGBE_MACRX128TO255L);
355 rd64(hw, TXGBE_MACRX256TO511L);
356 rd64(hw, TXGBE_MACRX512TO1023L);
357 rd64(hw, TXGBE_MACRX1024TOMAXL);
358 rd64(hw, TXGBE_MACTX1TO64L);
359 rd64(hw, TXGBE_MACTX65TO127L);
360 rd64(hw, TXGBE_MACTX128TO255L);
361 rd64(hw, TXGBE_MACTX256TO511L);
362 rd64(hw, TXGBE_MACTX512TO1023L);
363 rd64(hw, TXGBE_MACTX1024TOMAXL);
365 rd64(hw, TXGBE_MACRXERRLENL);
366 rd32(hw, TXGBE_MACRXOVERSIZE);
367 rd32(hw, TXGBE_MACRXJABBER);
370 rd32(hw, TXGBE_FCOECRC);
371 rd32(hw, TXGBE_FCOELAST);
372 rd32(hw, TXGBE_FCOERPDC);
373 rd32(hw, TXGBE_FCOEPRC);
374 rd32(hw, TXGBE_FCOEPTC);
375 rd32(hw, TXGBE_FCOEDWRC);
376 rd32(hw, TXGBE_FCOEDWTC);
378 /* Flow Director Stats */
379 rd32(hw, TXGBE_FDIRMATCH);
380 rd32(hw, TXGBE_FDIRMISS);
381 rd32(hw, TXGBE_FDIRUSED);
382 rd32(hw, TXGBE_FDIRUSED);
383 rd32(hw, TXGBE_FDIRFAIL);
384 rd32(hw, TXGBE_FDIRFAIL);
387 rd32(hw, TXGBE_LSECTX_UTPKT);
388 rd32(hw, TXGBE_LSECTX_ENCPKT);
389 rd32(hw, TXGBE_LSECTX_PROTPKT);
390 rd32(hw, TXGBE_LSECTX_ENCOCT);
391 rd32(hw, TXGBE_LSECTX_PROTOCT);
392 rd32(hw, TXGBE_LSECRX_UTPKT);
393 rd32(hw, TXGBE_LSECRX_BTPKT);
394 rd32(hw, TXGBE_LSECRX_NOSCIPKT);
395 rd32(hw, TXGBE_LSECRX_UNSCIPKT);
396 rd32(hw, TXGBE_LSECRX_DECOCT);
397 rd32(hw, TXGBE_LSECRX_VLDOCT);
398 rd32(hw, TXGBE_LSECRX_UNCHKPKT);
399 rd32(hw, TXGBE_LSECRX_DLYPKT);
400 rd32(hw, TXGBE_LSECRX_LATEPKT);
401 for (i = 0; i < 2; i++) {
402 rd32(hw, TXGBE_LSECRX_OKPKT(i));
403 rd32(hw, TXGBE_LSECRX_INVPKT(i));
404 rd32(hw, TXGBE_LSECRX_BADPKT(i));
406 rd32(hw, TXGBE_LSECRX_INVSAPKT);
407 rd32(hw, TXGBE_LSECRX_BADSAPKT);
413 * txgbe_get_mac_addr - Generic get MAC address
414 * @hw: pointer to hardware structure
415 * @mac_addr: Adapter MAC address
417 * Reads the adapter's MAC address from first Receive Address Register (RAR0)
418 * A reset of the adapter must be performed prior to calling this function
419 * in order for the MAC address to have been loaded from the EEPROM into RAR0
421 s32 txgbe_get_mac_addr(struct txgbe_hw *hw, u8 *mac_addr)
427 DEBUGFUNC("txgbe_get_mac_addr");
429 wr32(hw, TXGBE_ETHADDRIDX, 0);
430 rar_high = rd32(hw, TXGBE_ETHADDRH);
431 rar_low = rd32(hw, TXGBE_ETHADDRL);
433 for (i = 0; i < 2; i++)
434 mac_addr[i] = (u8)(rar_high >> (1 - i) * 8);
436 for (i = 0; i < 4; i++)
437 mac_addr[i + 2] = (u8)(rar_low >> (3 - i) * 8);
443 * txgbe_set_lan_id_multi_port - Set LAN id for PCIe multiple port devices
444 * @hw: pointer to the HW structure
446 * Determines the LAN function id by reading memory-mapped registers and swaps
447 * the port value if requested, and set MAC instance for devices.
449 void txgbe_set_lan_id_multi_port(struct txgbe_hw *hw)
451 struct txgbe_bus_info *bus = &hw->bus;
454 DEBUGFUNC("txgbe_set_lan_id_multi_port_pcie");
456 reg = rd32(hw, TXGBE_PORTSTAT);
457 bus->lan_id = TXGBE_PORTSTAT_ID(reg);
459 /* check for single port */
460 reg = rd32(hw, TXGBE_PWR);
461 if (TXGBE_PWR_LANID(reg) == TXGBE_PWR_LANID_SWAP)
464 bus->func = bus->lan_id;
468 * txgbe_stop_hw - Generic stop Tx/Rx units
469 * @hw: pointer to hardware structure
471 * Sets the adapter_stopped flag within txgbe_hw struct. Clears interrupts,
472 * disables transmit and receive units. The adapter_stopped flag is used by
473 * the shared code and drivers to determine if the adapter is in a stopped
474 * state and should not touch the hardware.
476 s32 txgbe_stop_hw(struct txgbe_hw *hw)
481 DEBUGFUNC("txgbe_stop_hw");
484 * Set the adapter_stopped flag so other driver functions stop touching
487 hw->adapter_stopped = true;
489 /* Disable the receive unit */
490 txgbe_disable_rx(hw);
492 /* Clear interrupt mask to stop interrupts from being generated */
493 wr32(hw, TXGBE_IENMISC, 0);
494 wr32(hw, TXGBE_IMS(0), TXGBE_IMS_MASK);
495 wr32(hw, TXGBE_IMS(1), TXGBE_IMS_MASK);
497 /* Clear any pending interrupts, flush previous writes */
498 wr32(hw, TXGBE_ICRMISC, TXGBE_ICRMISC_MASK);
499 wr32(hw, TXGBE_ICR(0), TXGBE_ICR_MASK);
500 wr32(hw, TXGBE_ICR(1), TXGBE_ICR_MASK);
502 /* Disable the transmit unit. Each queue must be disabled. */
503 for (i = 0; i < hw->mac.max_tx_queues; i++)
504 wr32(hw, TXGBE_TXCFG(i), TXGBE_TXCFG_FLUSH);
506 /* Disable the receive unit by stopping each queue */
507 for (i = 0; i < hw->mac.max_rx_queues; i++) {
508 reg_val = rd32(hw, TXGBE_RXCFG(i));
509 reg_val &= ~TXGBE_RXCFG_ENA;
510 wr32(hw, TXGBE_RXCFG(i), reg_val);
513 /* flush all queues disables */
521 * txgbe_led_on - Turns on the software controllable LEDs.
522 * @hw: pointer to hardware structure
523 * @index: led number to turn on
525 s32 txgbe_led_on(struct txgbe_hw *hw, u32 index)
527 u32 led_reg = rd32(hw, TXGBE_LEDCTL);
529 DEBUGFUNC("txgbe_led_on");
532 return TXGBE_ERR_PARAM;
534 /* To turn on the LED, set mode to ON. */
535 led_reg |= TXGBE_LEDCTL_SEL(index);
536 led_reg |= TXGBE_LEDCTL_ORD(index);
537 wr32(hw, TXGBE_LEDCTL, led_reg);
544 * txgbe_led_off - Turns off the software controllable LEDs.
545 * @hw: pointer to hardware structure
546 * @index: led number to turn off
548 s32 txgbe_led_off(struct txgbe_hw *hw, u32 index)
550 u32 led_reg = rd32(hw, TXGBE_LEDCTL);
552 DEBUGFUNC("txgbe_led_off");
555 return TXGBE_ERR_PARAM;
557 /* To turn off the LED, set mode to OFF. */
558 led_reg &= ~(TXGBE_LEDCTL_SEL(index));
559 led_reg &= ~(TXGBE_LEDCTL_ORD(index));
560 wr32(hw, TXGBE_LEDCTL, led_reg);
567 * txgbe_validate_mac_addr - Validate MAC address
568 * @mac_addr: pointer to MAC address.
570 * Tests a MAC address to ensure it is a valid Individual Address.
572 s32 txgbe_validate_mac_addr(u8 *mac_addr)
576 DEBUGFUNC("txgbe_validate_mac_addr");
578 /* Make sure it is not a multicast address */
579 if (TXGBE_IS_MULTICAST(mac_addr)) {
580 status = TXGBE_ERR_INVALID_MAC_ADDR;
581 /* Not a broadcast address */
582 } else if (TXGBE_IS_BROADCAST(mac_addr)) {
583 status = TXGBE_ERR_INVALID_MAC_ADDR;
584 /* Reject the zero address */
585 } else if (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 &&
586 mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0) {
587 status = TXGBE_ERR_INVALID_MAC_ADDR;
593 * txgbe_set_rar - Set Rx address register
594 * @hw: pointer to hardware structure
595 * @index: Receive address register to write
596 * @addr: Address to put into receive address register
597 * @vmdq: VMDq "set" or "pool" index
598 * @enable_addr: set flag that address is active
600 * Puts an ethernet address into a receive address register.
602 s32 txgbe_set_rar(struct txgbe_hw *hw, u32 index, u8 *addr, u32 vmdq,
605 u32 rar_low, rar_high;
606 u32 rar_entries = hw->mac.num_rar_entries;
608 DEBUGFUNC("txgbe_set_rar");
610 /* Make sure we are using a valid rar index range */
611 if (index >= rar_entries) {
612 DEBUGOUT("RAR index %d is out of range.\n", index);
613 return TXGBE_ERR_INVALID_ARGUMENT;
616 /* setup VMDq pool selection before this RAR gets enabled */
617 hw->mac.set_vmdq(hw, index, vmdq);
620 * HW expects these in little endian so we reverse the byte
621 * order from network order (big endian) to little endian
623 rar_low = TXGBE_ETHADDRL_AD0(addr[5]) |
624 TXGBE_ETHADDRL_AD1(addr[4]) |
625 TXGBE_ETHADDRL_AD2(addr[3]) |
626 TXGBE_ETHADDRL_AD3(addr[2]);
628 * Some parts put the VMDq setting in the extra RAH bits,
629 * so save everything except the lower 16 bits that hold part
630 * of the address and the address valid bit.
632 rar_high = rd32(hw, TXGBE_ETHADDRH);
633 rar_high &= ~TXGBE_ETHADDRH_AD_MASK;
634 rar_high |= (TXGBE_ETHADDRH_AD4(addr[1]) |
635 TXGBE_ETHADDRH_AD5(addr[0]));
637 rar_high &= ~TXGBE_ETHADDRH_VLD;
638 if (enable_addr != 0)
639 rar_high |= TXGBE_ETHADDRH_VLD;
641 wr32(hw, TXGBE_ETHADDRIDX, index);
642 wr32(hw, TXGBE_ETHADDRL, rar_low);
643 wr32(hw, TXGBE_ETHADDRH, rar_high);
649 * txgbe_clear_rar - Remove Rx address register
650 * @hw: pointer to hardware structure
651 * @index: Receive address register to write
653 * Clears an ethernet address from a receive address register.
655 s32 txgbe_clear_rar(struct txgbe_hw *hw, u32 index)
658 u32 rar_entries = hw->mac.num_rar_entries;
660 DEBUGFUNC("txgbe_clear_rar");
662 /* Make sure we are using a valid rar index range */
663 if (index >= rar_entries) {
664 DEBUGOUT("RAR index %d is out of range.\n", index);
665 return TXGBE_ERR_INVALID_ARGUMENT;
669 * Some parts put the VMDq setting in the extra RAH bits,
670 * so save everything except the lower 16 bits that hold part
671 * of the address and the address valid bit.
673 wr32(hw, TXGBE_ETHADDRIDX, index);
674 rar_high = rd32(hw, TXGBE_ETHADDRH);
675 rar_high &= ~(TXGBE_ETHADDRH_AD_MASK | TXGBE_ETHADDRH_VLD);
677 wr32(hw, TXGBE_ETHADDRL, 0);
678 wr32(hw, TXGBE_ETHADDRH, rar_high);
680 /* clear VMDq pool/queue selection for this RAR */
681 hw->mac.clear_vmdq(hw, index, BIT_MASK32);
687 * txgbe_init_rx_addrs - Initializes receive address filters.
688 * @hw: pointer to hardware structure
690 * Places the MAC address in receive address register 0 and clears the rest
691 * of the receive address registers. Clears the multicast table. Assumes
692 * the receiver is in reset when the routine is called.
694 s32 txgbe_init_rx_addrs(struct txgbe_hw *hw)
698 u32 rar_entries = hw->mac.num_rar_entries;
700 DEBUGFUNC("txgbe_init_rx_addrs");
703 * If the current mac address is valid, assume it is a software override
704 * to the permanent address.
705 * Otherwise, use the permanent address from the eeprom.
707 if (txgbe_validate_mac_addr(hw->mac.addr) ==
708 TXGBE_ERR_INVALID_MAC_ADDR) {
709 /* Get the MAC address from the RAR0 for later reference */
710 hw->mac.get_mac_addr(hw, hw->mac.addr);
712 DEBUGOUT(" Keeping Current RAR0 Addr =%.2X %.2X %.2X ",
713 hw->mac.addr[0], hw->mac.addr[1],
715 DEBUGOUT("%.2X %.2X %.2X\n", hw->mac.addr[3],
716 hw->mac.addr[4], hw->mac.addr[5]);
718 /* Setup the receive address. */
719 DEBUGOUT("Overriding MAC Address in RAR[0]\n");
720 DEBUGOUT(" New MAC Addr =%.2X %.2X %.2X ",
721 hw->mac.addr[0], hw->mac.addr[1],
723 DEBUGOUT("%.2X %.2X %.2X\n", hw->mac.addr[3],
724 hw->mac.addr[4], hw->mac.addr[5]);
726 hw->mac.set_rar(hw, 0, hw->mac.addr, 0, true);
729 /* clear VMDq pool/queue selection for RAR 0 */
730 hw->mac.clear_vmdq(hw, 0, BIT_MASK32);
732 hw->addr_ctrl.overflow_promisc = 0;
734 hw->addr_ctrl.rar_used_count = 1;
736 /* Zero out the other receive addresses. */
737 DEBUGOUT("Clearing RAR[1-%d]\n", rar_entries - 1);
738 for (i = 1; i < rar_entries; i++) {
739 wr32(hw, TXGBE_ETHADDRIDX, i);
740 wr32(hw, TXGBE_ETHADDRL, 0);
741 wr32(hw, TXGBE_ETHADDRH, 0);
745 hw->addr_ctrl.mta_in_use = 0;
746 psrctl = rd32(hw, TXGBE_PSRCTL);
747 psrctl &= ~(TXGBE_PSRCTL_ADHF12_MASK | TXGBE_PSRCTL_MCHFENA);
748 psrctl |= TXGBE_PSRCTL_ADHF12(hw->mac.mc_filter_type);
749 wr32(hw, TXGBE_PSRCTL, psrctl);
751 DEBUGOUT(" Clearing MTA\n");
752 for (i = 0; i < hw->mac.mcft_size; i++)
753 wr32(hw, TXGBE_MCADDRTBL(i), 0);
755 txgbe_init_uta_tables(hw);
761 * txgbe_mta_vector - Determines bit-vector in multicast table to set
762 * @hw: pointer to hardware structure
763 * @mc_addr: the multicast address
765 * Extracts the 12 bits, from a multicast address, to determine which
766 * bit-vector to set in the multicast table. The hardware uses 12 bits, from
767 * incoming rx multicast addresses, to determine the bit-vector to check in
768 * the MTA. Which of the 4 combination, of 12-bits, the hardware uses is set
769 * by the MO field of the PSRCTRL. The MO field is set during initialization
772 static s32 txgbe_mta_vector(struct txgbe_hw *hw, u8 *mc_addr)
776 DEBUGFUNC("txgbe_mta_vector");
778 switch (hw->mac.mc_filter_type) {
779 case 0: /* use bits [47:36] of the address */
780 vector = ((mc_addr[4] >> 4) | (((u16)mc_addr[5]) << 4));
782 case 1: /* use bits [46:35] of the address */
783 vector = ((mc_addr[4] >> 3) | (((u16)mc_addr[5]) << 5));
785 case 2: /* use bits [45:34] of the address */
786 vector = ((mc_addr[4] >> 2) | (((u16)mc_addr[5]) << 6));
788 case 3: /* use bits [43:32] of the address */
789 vector = ((mc_addr[4]) | (((u16)mc_addr[5]) << 8));
791 default: /* Invalid mc_filter_type */
792 DEBUGOUT("MC filter type param set incorrectly\n");
797 /* vector can only be 12-bits or boundary will be exceeded */
803 * txgbe_set_mta - Set bit-vector in multicast table
804 * @hw: pointer to hardware structure
805 * @mc_addr: Multicast address
807 * Sets the bit-vector in the multicast table.
809 void txgbe_set_mta(struct txgbe_hw *hw, u8 *mc_addr)
815 DEBUGFUNC("txgbe_set_mta");
817 hw->addr_ctrl.mta_in_use++;
819 vector = txgbe_mta_vector(hw, mc_addr);
820 DEBUGOUT(" bit-vector = 0x%03X\n", vector);
823 * The MTA is a register array of 128 32-bit registers. It is treated
824 * like an array of 4096 bits. We want to set bit
825 * BitArray[vector_value]. So we figure out what register the bit is
826 * in, read it, OR in the new bit, then write back the new value. The
827 * register is determined by the upper 7 bits of the vector value and
828 * the bit within that register are determined by the lower 5 bits of
831 vector_reg = (vector >> 5) & 0x7F;
832 vector_bit = vector & 0x1F;
833 hw->mac.mta_shadow[vector_reg] |= (1 << vector_bit);
837 * txgbe_update_mc_addr_list - Updates MAC list of multicast addresses
838 * @hw: pointer to hardware structure
839 * @mc_addr_list: the list of new multicast addresses
840 * @mc_addr_count: number of addresses
841 * @next: iterator function to walk the multicast address list
842 * @clear: flag, when set clears the table beforehand
844 * When the clear flag is set, the given list replaces any existing list.
845 * Hashes the given addresses into the multicast table.
847 s32 txgbe_update_mc_addr_list(struct txgbe_hw *hw, u8 *mc_addr_list,
848 u32 mc_addr_count, txgbe_mc_addr_itr next,
854 DEBUGFUNC("txgbe_update_mc_addr_list");
857 * Set the new number of MC addresses that we are being requested to
860 hw->addr_ctrl.num_mc_addrs = mc_addr_count;
861 hw->addr_ctrl.mta_in_use = 0;
863 /* Clear mta_shadow */
865 DEBUGOUT(" Clearing MTA\n");
866 memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow));
869 /* Update mta_shadow */
870 for (i = 0; i < mc_addr_count; i++) {
871 DEBUGOUT(" Adding the multicast addresses:\n");
872 txgbe_set_mta(hw, next(hw, &mc_addr_list, &vmdq));
876 for (i = 0; i < hw->mac.mcft_size; i++)
877 wr32a(hw, TXGBE_MCADDRTBL(0), i,
878 hw->mac.mta_shadow[i]);
880 if (hw->addr_ctrl.mta_in_use > 0) {
881 u32 psrctl = rd32(hw, TXGBE_PSRCTL);
882 psrctl &= ~(TXGBE_PSRCTL_ADHF12_MASK | TXGBE_PSRCTL_MCHFENA);
883 psrctl |= TXGBE_PSRCTL_MCHFENA |
884 TXGBE_PSRCTL_ADHF12(hw->mac.mc_filter_type);
885 wr32(hw, TXGBE_PSRCTL, psrctl);
888 DEBUGOUT("txgbe update mc addr list complete\n");
893 * txgbe_fc_enable - Enable flow control
894 * @hw: pointer to hardware structure
896 * Enable flow control according to the current settings.
898 s32 txgbe_fc_enable(struct txgbe_hw *hw)
901 u32 mflcn_reg, fccfg_reg;
906 DEBUGFUNC("txgbe_fc_enable");
908 /* Validate the water mark configuration */
909 if (!hw->fc.pause_time) {
910 err = TXGBE_ERR_INVALID_LINK_SETTINGS;
914 /* Low water mark of zero causes XOFF floods */
915 for (i = 0; i < TXGBE_DCB_TC_MAX; i++) {
916 if ((hw->fc.current_mode & txgbe_fc_tx_pause) &&
917 hw->fc.high_water[i]) {
918 if (!hw->fc.low_water[i] ||
919 hw->fc.low_water[i] >= hw->fc.high_water[i]) {
920 DEBUGOUT("Invalid water mark configuration\n");
921 err = TXGBE_ERR_INVALID_LINK_SETTINGS;
927 /* Negotiate the fc mode to use */
928 hw->mac.fc_autoneg(hw);
930 /* Disable any previous flow control settings */
931 mflcn_reg = rd32(hw, TXGBE_RXFCCFG);
932 mflcn_reg &= ~(TXGBE_RXFCCFG_FC | TXGBE_RXFCCFG_PFC);
934 fccfg_reg = rd32(hw, TXGBE_TXFCCFG);
935 fccfg_reg &= ~(TXGBE_TXFCCFG_FC | TXGBE_TXFCCFG_PFC);
938 * The possible values of fc.current_mode are:
939 * 0: Flow control is completely disabled
940 * 1: Rx flow control is enabled (we can receive pause frames,
941 * but not send pause frames).
942 * 2: Tx flow control is enabled (we can send pause frames but
943 * we do not support receiving pause frames).
944 * 3: Both Rx and Tx flow control (symmetric) are enabled.
947 switch (hw->fc.current_mode) {
950 * Flow control is disabled by software override or autoneg.
951 * The code below will actually disable it in the HW.
954 case txgbe_fc_rx_pause:
956 * Rx Flow control is enabled and Tx Flow control is
957 * disabled by software override. Since there really
958 * isn't a way to advertise that we are capable of RX
959 * Pause ONLY, we will advertise that we support both
960 * symmetric and asymmetric Rx PAUSE. Later, we will
961 * disable the adapter's ability to send PAUSE frames.
963 mflcn_reg |= TXGBE_RXFCCFG_FC;
965 case txgbe_fc_tx_pause:
967 * Tx Flow control is enabled, and Rx Flow control is
968 * disabled by software override.
970 fccfg_reg |= TXGBE_TXFCCFG_FC;
973 /* Flow control (both Rx and Tx) is enabled by SW override. */
974 mflcn_reg |= TXGBE_RXFCCFG_FC;
975 fccfg_reg |= TXGBE_TXFCCFG_FC;
978 DEBUGOUT("Flow control param set incorrectly\n");
979 err = TXGBE_ERR_CONFIG;
983 /* Set 802.3x based flow control settings. */
984 wr32(hw, TXGBE_RXFCCFG, mflcn_reg);
985 wr32(hw, TXGBE_TXFCCFG, fccfg_reg);
987 /* Set up and enable Rx high/low water mark thresholds, enable XON. */
988 for (i = 0; i < TXGBE_DCB_TC_MAX; i++) {
989 if ((hw->fc.current_mode & txgbe_fc_tx_pause) &&
990 hw->fc.high_water[i]) {
991 fcrtl = TXGBE_FCWTRLO_TH(hw->fc.low_water[i]) |
993 fcrth = TXGBE_FCWTRHI_TH(hw->fc.high_water[i]) |
997 * In order to prevent Tx hangs when the internal Tx
998 * switch is enabled we must set the high water mark
999 * to the Rx packet buffer size - 24KB. This allows
1000 * the Tx switch to function even under heavy Rx
1004 fcrth = rd32(hw, TXGBE_PBRXSIZE(i)) - 24576;
1006 wr32(hw, TXGBE_FCWTRLO(i), fcrtl);
1007 wr32(hw, TXGBE_FCWTRHI(i), fcrth);
1010 /* Configure pause time (2 TCs per register) */
1011 pause_time = TXGBE_RXFCFSH_TIME(hw->fc.pause_time);
1012 for (i = 0; i < (TXGBE_DCB_TC_MAX / 2); i++)
1013 wr32(hw, TXGBE_FCXOFFTM(i), pause_time * 0x00010001);
1015 /* Configure flow control refresh threshold value */
1016 wr32(hw, TXGBE_RXFCRFSH, hw->fc.pause_time / 2);
1023 * txgbe_negotiate_fc - Negotiate flow control
1024 * @hw: pointer to hardware structure
1025 * @adv_reg: flow control advertised settings
1026 * @lp_reg: link partner's flow control settings
1027 * @adv_sym: symmetric pause bit in advertisement
1028 * @adv_asm: asymmetric pause bit in advertisement
1029 * @lp_sym: symmetric pause bit in link partner advertisement
1030 * @lp_asm: asymmetric pause bit in link partner advertisement
1032 * Find the intersection between advertised settings and link partner's
1033 * advertised settings
1035 s32 txgbe_negotiate_fc(struct txgbe_hw *hw, u32 adv_reg, u32 lp_reg,
1036 u32 adv_sym, u32 adv_asm, u32 lp_sym, u32 lp_asm)
1038 if ((!(adv_reg)) || (!(lp_reg))) {
1039 DEBUGOUT("Local or link partner's advertised flow control "
1040 "settings are NULL. Local: %x, link partner: %x\n",
1042 return TXGBE_ERR_FC_NOT_NEGOTIATED;
1045 if ((adv_reg & adv_sym) && (lp_reg & lp_sym)) {
1047 * Now we need to check if the user selected Rx ONLY
1048 * of pause frames. In this case, we had to advertise
1049 * FULL flow control because we could not advertise RX
1050 * ONLY. Hence, we must now check to see if we need to
1051 * turn OFF the TRANSMISSION of PAUSE frames.
1053 if (hw->fc.requested_mode == txgbe_fc_full) {
1054 hw->fc.current_mode = txgbe_fc_full;
1055 DEBUGOUT("Flow Control = FULL.\n");
1057 hw->fc.current_mode = txgbe_fc_rx_pause;
1058 DEBUGOUT("Flow Control=RX PAUSE frames only\n");
1060 } else if (!(adv_reg & adv_sym) && (adv_reg & adv_asm) &&
1061 (lp_reg & lp_sym) && (lp_reg & lp_asm)) {
1062 hw->fc.current_mode = txgbe_fc_tx_pause;
1063 DEBUGOUT("Flow Control = TX PAUSE frames only.\n");
1064 } else if ((adv_reg & adv_sym) && (adv_reg & adv_asm) &&
1065 !(lp_reg & lp_sym) && (lp_reg & lp_asm)) {
1066 hw->fc.current_mode = txgbe_fc_rx_pause;
1067 DEBUGOUT("Flow Control = RX PAUSE frames only.\n");
1069 hw->fc.current_mode = txgbe_fc_none;
1070 DEBUGOUT("Flow Control = NONE.\n");
1076 * txgbe_fc_autoneg_fiber - Enable flow control on 1 gig fiber
1077 * @hw: pointer to hardware structure
1079 * Enable flow control according on 1 gig fiber.
1081 STATIC s32 txgbe_fc_autoneg_fiber(struct txgbe_hw *hw)
1083 u32 pcs_anadv_reg, pcs_lpab_reg;
1084 s32 err = TXGBE_ERR_FC_NOT_NEGOTIATED;
1087 * On multispeed fiber at 1g, bail out if
1088 * - link is up but AN did not complete, or if
1089 * - link is up and AN completed but timed out
1092 pcs_anadv_reg = rd32_epcs(hw, SR_MII_MMD_AN_ADV);
1093 pcs_lpab_reg = rd32_epcs(hw, SR_MII_MMD_LP_BABL);
1095 err = txgbe_negotiate_fc(hw, pcs_anadv_reg,
1097 SR_MII_MMD_AN_ADV_PAUSE_SYM,
1098 SR_MII_MMD_AN_ADV_PAUSE_ASM,
1099 SR_MII_MMD_AN_ADV_PAUSE_SYM,
1100 SR_MII_MMD_AN_ADV_PAUSE_ASM);
1106 * txgbe_fc_autoneg_backplane - Enable flow control IEEE clause 37
1107 * @hw: pointer to hardware structure
1109 * Enable flow control according to IEEE clause 37.
1111 STATIC s32 txgbe_fc_autoneg_backplane(struct txgbe_hw *hw)
1113 u32 anlp1_reg, autoc_reg;
1114 s32 err = TXGBE_ERR_FC_NOT_NEGOTIATED;
1117 * Read the 10g AN autoc and LP ability registers and resolve
1118 * local flow control settings accordingly
1120 autoc_reg = rd32_epcs(hw, SR_AN_MMD_ADV_REG1);
1121 anlp1_reg = rd32_epcs(hw, SR_AN_MMD_LP_ABL1);
1123 err = txgbe_negotiate_fc(hw, autoc_reg,
1125 SR_AN_MMD_ADV_REG1_PAUSE_SYM,
1126 SR_AN_MMD_ADV_REG1_PAUSE_ASM,
1127 SR_AN_MMD_ADV_REG1_PAUSE_SYM,
1128 SR_AN_MMD_ADV_REG1_PAUSE_ASM);
1134 * txgbe_fc_autoneg_copper - Enable flow control IEEE clause 37
1135 * @hw: pointer to hardware structure
1137 * Enable flow control according to IEEE clause 37.
1139 STATIC s32 txgbe_fc_autoneg_copper(struct txgbe_hw *hw)
1141 u16 technology_ability_reg = 0;
1142 u16 lp_technology_ability_reg = 0;
1144 hw->phy.read_reg(hw, TXGBE_MD_AUTO_NEG_ADVT,
1145 TXGBE_MD_DEV_AUTO_NEG,
1146 &technology_ability_reg);
1147 hw->phy.read_reg(hw, TXGBE_MD_AUTO_NEG_LP,
1148 TXGBE_MD_DEV_AUTO_NEG,
1149 &lp_technology_ability_reg);
1151 return txgbe_negotiate_fc(hw, (u32)technology_ability_reg,
1152 (u32)lp_technology_ability_reg,
1153 TXGBE_TAF_SYM_PAUSE, TXGBE_TAF_ASM_PAUSE,
1154 TXGBE_TAF_SYM_PAUSE, TXGBE_TAF_ASM_PAUSE);
1158 * txgbe_fc_autoneg - Configure flow control
1159 * @hw: pointer to hardware structure
1161 * Compares our advertised flow control capabilities to those advertised by
1162 * our link partner, and determines the proper flow control mode to use.
1164 void txgbe_fc_autoneg(struct txgbe_hw *hw)
1166 s32 err = TXGBE_ERR_FC_NOT_NEGOTIATED;
1170 DEBUGFUNC("txgbe_fc_autoneg");
1173 * AN should have completed when the cable was plugged in.
1174 * Look for reasons to bail out. Bail out if:
1175 * - FC autoneg is disabled, or if
1178 if (hw->fc.disable_fc_autoneg) {
1179 DEBUGOUT("Flow control autoneg is disabled");
1183 hw->mac.check_link(hw, &speed, &link_up, false);
1185 DEBUGOUT("The link is down");
1189 switch (hw->phy.media_type) {
1190 /* Autoneg flow control on fiber adapters */
1191 case txgbe_media_type_fiber_qsfp:
1192 case txgbe_media_type_fiber:
1193 if (speed == TXGBE_LINK_SPEED_1GB_FULL)
1194 err = txgbe_fc_autoneg_fiber(hw);
1197 /* Autoneg flow control on backplane adapters */
1198 case txgbe_media_type_backplane:
1199 err = txgbe_fc_autoneg_backplane(hw);
1202 /* Autoneg flow control on copper adapters */
1203 case txgbe_media_type_copper:
1204 if (txgbe_device_supports_autoneg_fc(hw))
1205 err = txgbe_fc_autoneg_copper(hw);
1214 hw->fc.fc_was_autonegged = true;
1216 hw->fc.fc_was_autonegged = false;
1217 hw->fc.current_mode = hw->fc.requested_mode;
1222 * txgbe_acquire_swfw_sync - Acquire SWFW semaphore
1223 * @hw: pointer to hardware structure
1224 * @mask: Mask to specify which semaphore to acquire
1226 * Acquires the SWFW semaphore through the MNGSEM register for the specified
1227 * function (CSR, PHY0, PHY1, EEPROM, Flash)
1229 s32 txgbe_acquire_swfw_sync(struct txgbe_hw *hw, u32 mask)
1232 u32 swmask = TXGBE_MNGSEM_SW(mask);
1233 u32 fwmask = TXGBE_MNGSEM_FW(mask);
1237 DEBUGFUNC("txgbe_acquire_swfw_sync");
1239 for (i = 0; i < timeout; i++) {
1241 * SW NVM semaphore bit is used for access to all
1242 * SW_FW_SYNC bits (not just NVM)
1244 if (txgbe_get_eeprom_semaphore(hw))
1245 return TXGBE_ERR_SWFW_SYNC;
1247 mngsem = rd32(hw, TXGBE_MNGSEM);
1248 if (mngsem & (fwmask | swmask)) {
1249 /* Resource is currently in use by FW or SW */
1250 txgbe_release_eeprom_semaphore(hw);
1254 wr32(hw, TXGBE_MNGSEM, mngsem);
1255 txgbe_release_eeprom_semaphore(hw);
1260 /* If time expired clear the bits holding the lock and retry */
1261 if (mngsem & (fwmask | swmask))
1262 txgbe_release_swfw_sync(hw, mngsem & (fwmask | swmask));
1265 return TXGBE_ERR_SWFW_SYNC;
1269 * txgbe_release_swfw_sync - Release SWFW semaphore
1270 * @hw: pointer to hardware structure
1271 * @mask: Mask to specify which semaphore to release
1273 * Releases the SWFW semaphore through the MNGSEM register for the specified
1274 * function (CSR, PHY0, PHY1, EEPROM, Flash)
1276 void txgbe_release_swfw_sync(struct txgbe_hw *hw, u32 mask)
1281 DEBUGFUNC("txgbe_release_swfw_sync");
1283 txgbe_get_eeprom_semaphore(hw);
1285 mngsem = rd32(hw, TXGBE_MNGSEM);
1287 wr32(hw, TXGBE_MNGSEM, mngsem);
1289 txgbe_release_eeprom_semaphore(hw);
1293 * txgbe_disable_sec_rx_path - Stops the receive data path
1294 * @hw: pointer to hardware structure
1296 * Stops the receive data path and waits for the HW to internally empty
1297 * the Rx security block
1299 s32 txgbe_disable_sec_rx_path(struct txgbe_hw *hw)
1301 #define TXGBE_MAX_SECRX_POLL 4000
1306 DEBUGFUNC("txgbe_disable_sec_rx_path");
1308 secrxreg = rd32(hw, TXGBE_SECRXCTL);
1309 secrxreg |= TXGBE_SECRXCTL_XDSA;
1310 wr32(hw, TXGBE_SECRXCTL, secrxreg);
1311 for (i = 0; i < TXGBE_MAX_SECRX_POLL; i++) {
1312 secrxreg = rd32(hw, TXGBE_SECRXSTAT);
1313 if (!(secrxreg & TXGBE_SECRXSTAT_RDY))
1314 /* Use interrupt-safe sleep just in case */
1320 /* For informational purposes only */
1321 if (i >= TXGBE_MAX_SECRX_POLL)
1322 DEBUGOUT("Rx unit being enabled before security "
1323 "path fully disabled. Continuing with init.\n");
1329 * txgbe_enable_sec_rx_path - Enables the receive data path
1330 * @hw: pointer to hardware structure
1332 * Enables the receive data path.
1334 s32 txgbe_enable_sec_rx_path(struct txgbe_hw *hw)
1338 DEBUGFUNC("txgbe_enable_sec_rx_path");
1340 secrxreg = rd32(hw, TXGBE_SECRXCTL);
1341 secrxreg &= ~TXGBE_SECRXCTL_XDSA;
1342 wr32(hw, TXGBE_SECRXCTL, secrxreg);
1349 * txgbe_disable_sec_tx_path - Stops the transmit data path
1350 * @hw: pointer to hardware structure
1352 * Stops the transmit data path and waits for the HW to internally empty
1353 * the Tx security block
1355 int txgbe_disable_sec_tx_path(struct txgbe_hw *hw)
1357 #define TXGBE_MAX_SECTX_POLL 40
1362 sectxreg = rd32(hw, TXGBE_SECTXCTL);
1363 sectxreg |= TXGBE_SECTXCTL_XDSA;
1364 wr32(hw, TXGBE_SECTXCTL, sectxreg);
1365 for (i = 0; i < TXGBE_MAX_SECTX_POLL; i++) {
1366 sectxreg = rd32(hw, TXGBE_SECTXSTAT);
1367 if (sectxreg & TXGBE_SECTXSTAT_RDY)
1369 /* Use interrupt-safe sleep just in case */
1373 /* For informational purposes only */
1374 if (i >= TXGBE_MAX_SECTX_POLL)
1375 PMD_DRV_LOG(DEBUG, "Tx unit being enabled before security "
1376 "path fully disabled. Continuing with init.");
1382 * txgbe_enable_sec_tx_path - Enables the transmit data path
1383 * @hw: pointer to hardware structure
1385 * Enables the transmit data path.
1387 int txgbe_enable_sec_tx_path(struct txgbe_hw *hw)
1391 sectxreg = rd32(hw, TXGBE_SECTXCTL);
1392 sectxreg &= ~TXGBE_SECTXCTL_XDSA;
1393 wr32(hw, TXGBE_SECTXCTL, sectxreg);
1400 * txgbe_get_san_mac_addr_offset - Get SAN MAC address offset from the EEPROM
1401 * @hw: pointer to hardware structure
1402 * @san_mac_offset: SAN MAC address offset
1404 * This function will read the EEPROM location for the SAN MAC address
1405 * pointer, and returns the value at that location. This is used in both
1406 * get and set mac_addr routines.
1408 static s32 txgbe_get_san_mac_addr_offset(struct txgbe_hw *hw,
1409 u16 *san_mac_offset)
1413 DEBUGFUNC("txgbe_get_san_mac_addr_offset");
1416 * First read the EEPROM pointer to see if the MAC addresses are
1419 err = hw->rom.readw_sw(hw, TXGBE_SAN_MAC_ADDR_PTR,
1422 DEBUGOUT("eeprom at offset %d failed",
1423 TXGBE_SAN_MAC_ADDR_PTR);
1430 * txgbe_get_san_mac_addr - SAN MAC address retrieval from the EEPROM
1431 * @hw: pointer to hardware structure
1432 * @san_mac_addr: SAN MAC address
1434 * Reads the SAN MAC address from the EEPROM, if it's available. This is
1435 * per-port, so set_lan_id() must be called before reading the addresses.
1436 * set_lan_id() is called by identify_sfp(), but this cannot be relied
1437 * upon for non-SFP connections, so we must call it here.
1439 s32 txgbe_get_san_mac_addr(struct txgbe_hw *hw, u8 *san_mac_addr)
1441 u16 san_mac_data, san_mac_offset;
1445 DEBUGFUNC("txgbe_get_san_mac_addr");
1448 * First read the EEPROM pointer to see if the MAC addresses are
1449 * available. If they're not, no point in calling set_lan_id() here.
1451 err = txgbe_get_san_mac_addr_offset(hw, &san_mac_offset);
1452 if (err || san_mac_offset == 0 || san_mac_offset == 0xFFFF)
1453 goto san_mac_addr_out;
1455 /* apply the port offset to the address offset */
1456 (hw->bus.func) ? (san_mac_offset += TXGBE_SAN_MAC_ADDR_PORT1_OFFSET) :
1457 (san_mac_offset += TXGBE_SAN_MAC_ADDR_PORT0_OFFSET);
1458 for (i = 0; i < 3; i++) {
1459 err = hw->rom.read16(hw, san_mac_offset,
1462 DEBUGOUT("eeprom read at offset %d failed",
1464 goto san_mac_addr_out;
1466 san_mac_addr[i * 2] = (u8)(san_mac_data);
1467 san_mac_addr[i * 2 + 1] = (u8)(san_mac_data >> 8);
1474 * No addresses available in this EEPROM. It's not an
1475 * error though, so just wipe the local address and return.
1477 for (i = 0; i < 6; i++)
1478 san_mac_addr[i] = 0xFF;
1483 * txgbe_set_san_mac_addr - Write the SAN MAC address to the EEPROM
1484 * @hw: pointer to hardware structure
1485 * @san_mac_addr: SAN MAC address
1487 * Write a SAN MAC address to the EEPROM.
1489 s32 txgbe_set_san_mac_addr(struct txgbe_hw *hw, u8 *san_mac_addr)
1492 u16 san_mac_data, san_mac_offset;
1495 DEBUGFUNC("txgbe_set_san_mac_addr");
1497 /* Look for SAN mac address pointer. If not defined, return */
1498 err = txgbe_get_san_mac_addr_offset(hw, &san_mac_offset);
1499 if (err || san_mac_offset == 0 || san_mac_offset == 0xFFFF)
1500 return TXGBE_ERR_NO_SAN_ADDR_PTR;
1502 /* Apply the port offset to the address offset */
1503 (hw->bus.func) ? (san_mac_offset += TXGBE_SAN_MAC_ADDR_PORT1_OFFSET) :
1504 (san_mac_offset += TXGBE_SAN_MAC_ADDR_PORT0_OFFSET);
1506 for (i = 0; i < 3; i++) {
1507 san_mac_data = (u16)((u16)(san_mac_addr[i * 2 + 1]) << 8);
1508 san_mac_data |= (u16)(san_mac_addr[i * 2]);
1509 hw->rom.write16(hw, san_mac_offset, san_mac_data);
1517 * txgbe_clear_vmdq - Disassociate a VMDq pool index from a rx address
1518 * @hw: pointer to hardware struct
1519 * @rar: receive address register index to disassociate
1520 * @vmdq: VMDq pool index to remove from the rar
1522 s32 txgbe_clear_vmdq(struct txgbe_hw *hw, u32 rar, u32 vmdq)
1524 u32 mpsar_lo, mpsar_hi;
1525 u32 rar_entries = hw->mac.num_rar_entries;
1527 DEBUGFUNC("txgbe_clear_vmdq");
1529 /* Make sure we are using a valid rar index range */
1530 if (rar >= rar_entries) {
1531 DEBUGOUT("RAR index %d is out of range.\n", rar);
1532 return TXGBE_ERR_INVALID_ARGUMENT;
1535 wr32(hw, TXGBE_ETHADDRIDX, rar);
1536 mpsar_lo = rd32(hw, TXGBE_ETHADDRASSL);
1537 mpsar_hi = rd32(hw, TXGBE_ETHADDRASSH);
1539 if (TXGBE_REMOVED(hw->hw_addr))
1542 if (!mpsar_lo && !mpsar_hi)
1545 if (vmdq == BIT_MASK32) {
1547 wr32(hw, TXGBE_ETHADDRASSL, 0);
1551 wr32(hw, TXGBE_ETHADDRASSH, 0);
1554 } else if (vmdq < 32) {
1555 mpsar_lo &= ~(1 << vmdq);
1556 wr32(hw, TXGBE_ETHADDRASSL, mpsar_lo);
1558 mpsar_hi &= ~(1 << (vmdq - 32));
1559 wr32(hw, TXGBE_ETHADDRASSH, mpsar_hi);
1562 /* was that the last pool using this rar? */
1563 if (mpsar_lo == 0 && mpsar_hi == 0 &&
1564 rar != 0 && rar != hw->mac.san_mac_rar_index)
1565 hw->mac.clear_rar(hw, rar);
1571 * txgbe_set_vmdq - Associate a VMDq pool index with a rx address
1572 * @hw: pointer to hardware struct
1573 * @rar: receive address register index to associate with a VMDq index
1574 * @vmdq: VMDq pool index
1576 s32 txgbe_set_vmdq(struct txgbe_hw *hw, u32 rar, u32 vmdq)
1579 u32 rar_entries = hw->mac.num_rar_entries;
1581 DEBUGFUNC("txgbe_set_vmdq");
1583 /* Make sure we are using a valid rar index range */
1584 if (rar >= rar_entries) {
1585 DEBUGOUT("RAR index %d is out of range.\n", rar);
1586 return TXGBE_ERR_INVALID_ARGUMENT;
1589 wr32(hw, TXGBE_ETHADDRIDX, rar);
1591 mpsar = rd32(hw, TXGBE_ETHADDRASSL);
1593 wr32(hw, TXGBE_ETHADDRASSL, mpsar);
1595 mpsar = rd32(hw, TXGBE_ETHADDRASSH);
1596 mpsar |= 1 << (vmdq - 32);
1597 wr32(hw, TXGBE_ETHADDRASSH, mpsar);
1603 * txgbe_init_uta_tables - Initialize the Unicast Table Array
1604 * @hw: pointer to hardware structure
1606 s32 txgbe_init_uta_tables(struct txgbe_hw *hw)
1610 DEBUGFUNC("txgbe_init_uta_tables");
1611 DEBUGOUT(" Clearing UTA\n");
1613 for (i = 0; i < 128; i++)
1614 wr32(hw, TXGBE_UCADDRTBL(i), 0);
1620 * txgbe_find_vlvf_slot - find the vlanid or the first empty slot
1621 * @hw: pointer to hardware structure
1622 * @vlan: VLAN id to write to VLAN filter
1623 * @vlvf_bypass: true to find vlanid only, false returns first empty slot if
1627 * return the VLVF index where this VLAN id should be placed
1630 s32 txgbe_find_vlvf_slot(struct txgbe_hw *hw, u32 vlan, bool vlvf_bypass)
1632 s32 regindex, first_empty_slot;
1635 /* short cut the special case */
1639 /* if vlvf_bypass is set we don't want to use an empty slot, we
1640 * will simply bypass the VLVF if there are no entries present in the
1641 * VLVF that contain our VLAN
1643 first_empty_slot = vlvf_bypass ? TXGBE_ERR_NO_SPACE : 0;
1645 /* add VLAN enable bit for comparison */
1646 vlan |= TXGBE_PSRVLAN_EA;
1648 /* Search for the vlan id in the VLVF entries. Save off the first empty
1649 * slot found along the way.
1651 * pre-decrement loop covering (TXGBE_NUM_POOL - 1) .. 1
1653 for (regindex = TXGBE_NUM_POOL; --regindex;) {
1654 wr32(hw, TXGBE_PSRVLANIDX, regindex);
1655 bits = rd32(hw, TXGBE_PSRVLAN);
1658 if (!first_empty_slot && !bits)
1659 first_empty_slot = regindex;
1662 /* If we are here then we didn't find the VLAN. Return first empty
1663 * slot we found during our search, else error.
1665 if (!first_empty_slot)
1666 DEBUGOUT("No space in VLVF.\n");
1668 return first_empty_slot ? first_empty_slot : TXGBE_ERR_NO_SPACE;
1672 * txgbe_set_vfta - Set VLAN filter table
1673 * @hw: pointer to hardware structure
1674 * @vlan: VLAN id to write to VLAN filter
1675 * @vind: VMDq output index that maps queue to VLAN id in VLVFB
1676 * @vlan_on: boolean flag to turn on/off VLAN
1677 * @vlvf_bypass: boolean flag indicating updating default pool is okay
1679 * Turn on/off specified VLAN in the VLAN filter table.
1681 s32 txgbe_set_vfta(struct txgbe_hw *hw, u32 vlan, u32 vind,
1682 bool vlan_on, bool vlvf_bypass)
1684 u32 regidx, vfta_delta, vfta;
1687 DEBUGFUNC("txgbe_set_vfta");
1689 if (vlan > 4095 || vind > 63)
1690 return TXGBE_ERR_PARAM;
1693 * this is a 2 part operation - first the VFTA, then the
1694 * VLVF and VLVFB if VT Mode is set
1695 * We don't write the VFTA until we know the VLVF part succeeded.
1699 * The VFTA is a bitstring made up of 128 32-bit registers
1700 * that enable the particular VLAN id, much like the MTA:
1701 * bits[11-5]: which register
1702 * bits[4-0]: which bit in the register
1705 vfta_delta = 1 << (vlan % 32);
1706 vfta = rd32(hw, TXGBE_VLANTBL(regidx));
1709 * vfta_delta represents the difference between the current value
1710 * of vfta and the value we want in the register. Since the diff
1711 * is an XOR mask we can just update the vfta using an XOR
1713 vfta_delta &= vlan_on ? ~vfta : vfta;
1717 * Call txgbe_set_vlvf to set VLVFB and VLVF
1719 err = txgbe_set_vlvf(hw, vlan, vind, vlan_on, &vfta_delta,
1728 /* Update VFTA now that we are ready for traffic */
1730 wr32(hw, TXGBE_VLANTBL(regidx), vfta);
1736 * txgbe_set_vlvf - Set VLAN Pool Filter
1737 * @hw: pointer to hardware structure
1738 * @vlan: VLAN id to write to VLAN filter
1739 * @vind: VMDq output index that maps queue to VLAN id in PSRVLANPLM
1740 * @vlan_on: boolean flag to turn on/off VLAN in PSRVLAN
1741 * @vfta_delta: pointer to the difference between the current value
1742 * of PSRVLANPLM and the desired value
1743 * @vfta: the desired value of the VFTA
1744 * @vlvf_bypass: boolean flag indicating updating default pool is okay
1746 * Turn on/off specified bit in VLVF table.
1748 s32 txgbe_set_vlvf(struct txgbe_hw *hw, u32 vlan, u32 vind,
1749 bool vlan_on, u32 *vfta_delta, u32 vfta,
1756 DEBUGFUNC("txgbe_set_vlvf");
1758 if (vlan > 4095 || vind > 63)
1759 return TXGBE_ERR_PARAM;
1761 /* If VT Mode is set
1763 * make sure the vlan is in PSRVLAN
1764 * set the vind bit in the matching PSRVLANPLM
1766 * clear the pool bit and possibly the vind
1768 portctl = rd32(hw, TXGBE_PORTCTL);
1769 if (!(portctl & TXGBE_PORTCTL_NUMVT_MASK))
1772 vlvf_index = txgbe_find_vlvf_slot(hw, vlan, vlvf_bypass);
1776 wr32(hw, TXGBE_PSRVLANIDX, vlvf_index);
1777 bits = rd32(hw, TXGBE_PSRVLANPLM(vind / 32));
1779 /* set the pool bit */
1780 bits |= 1 << (vind % 32);
1784 /* clear the pool bit */
1785 bits ^= 1 << (vind % 32);
1788 !rd32(hw, TXGBE_PSRVLANPLM(vind / 32))) {
1789 /* Clear PSRVLANPLM first, then disable PSRVLAN. Otherwise
1790 * we run the risk of stray packets leaking into
1791 * the PF via the default pool
1794 wr32(hw, TXGBE_PSRVLANPLM(vlan / 32), vfta);
1796 /* disable VLVF and clear remaining bit from pool */
1797 wr32(hw, TXGBE_PSRVLAN, 0);
1798 wr32(hw, TXGBE_PSRVLANPLM(vind / 32), 0);
1803 /* If there are still bits set in the PSRVLANPLM registers
1804 * for the VLAN ID indicated we need to see if the
1805 * caller is requesting that we clear the PSRVLANPLM entry bit.
1806 * If the caller has requested that we clear the PSRVLANPLM
1807 * entry bit but there are still pools/VFs using this VLAN
1808 * ID entry then ignore the request. We're not worried
1809 * about the case where we're turning the PSRVLANPLM VLAN ID
1810 * entry bit on, only when requested to turn it off as
1811 * there may be multiple pools and/or VFs using the
1812 * VLAN ID entry. In that case we cannot clear the
1813 * PSRVLANPLM bit until all pools/VFs using that VLAN ID have also
1814 * been cleared. This will be indicated by "bits" being
1820 /* record pool change and enable VLAN ID if not already enabled */
1821 wr32(hw, TXGBE_PSRVLANPLM(vind / 32), bits);
1822 wr32(hw, TXGBE_PSRVLAN, TXGBE_PSRVLAN_EA | vlan);
1828 * txgbe_clear_vfta - Clear VLAN filter table
1829 * @hw: pointer to hardware structure
1831 * Clears the VLAN filer table, and the VMDq index associated with the filter
1833 s32 txgbe_clear_vfta(struct txgbe_hw *hw)
1837 DEBUGFUNC("txgbe_clear_vfta");
1839 for (offset = 0; offset < hw->mac.vft_size; offset++)
1840 wr32(hw, TXGBE_VLANTBL(offset), 0);
1842 for (offset = 0; offset < TXGBE_NUM_POOL; offset++) {
1843 wr32(hw, TXGBE_PSRVLANIDX, offset);
1844 wr32(hw, TXGBE_PSRVLAN, 0);
1845 wr32(hw, TXGBE_PSRVLANPLM(0), 0);
1846 wr32(hw, TXGBE_PSRVLANPLM(1), 0);
1853 * txgbe_need_crosstalk_fix - Determine if we need to do cross talk fix
1854 * @hw: pointer to hardware structure
1856 * Contains the logic to identify if we need to verify link for the
1859 static bool txgbe_need_crosstalk_fix(struct txgbe_hw *hw)
1861 /* Does FW say we need the fix */
1862 if (!hw->need_crosstalk_fix)
1865 /* Only consider SFP+ PHYs i.e. media type fiber */
1866 switch (hw->phy.media_type) {
1867 case txgbe_media_type_fiber:
1868 case txgbe_media_type_fiber_qsfp:
1878 * txgbe_check_mac_link - Determine link and speed status
1879 * @hw: pointer to hardware structure
1880 * @speed: pointer to link speed
1881 * @link_up: true when link is up
1882 * @link_up_wait_to_complete: bool used to wait for link up or not
1884 * Reads the links register to determine if link is up and the current speed
1886 s32 txgbe_check_mac_link(struct txgbe_hw *hw, u32 *speed,
1887 bool *link_up, bool link_up_wait_to_complete)
1889 u32 links_reg, links_orig;
1892 DEBUGFUNC("txgbe_check_mac_link");
1894 /* If Crosstalk fix enabled do the sanity check of making sure
1895 * the SFP+ cage is full.
1897 if (txgbe_need_crosstalk_fix(hw)) {
1900 switch (hw->mac.type) {
1901 case txgbe_mac_raptor:
1902 sfp_cage_full = !rd32m(hw, TXGBE_GPIODATA,
1906 /* sanity check - No SFP+ devices here */
1907 sfp_cage_full = false;
1911 if (!sfp_cage_full) {
1913 *speed = TXGBE_LINK_SPEED_UNKNOWN;
1918 /* clear the old state */
1919 links_orig = rd32(hw, TXGBE_PORTSTAT);
1921 links_reg = rd32(hw, TXGBE_PORTSTAT);
1923 if (links_orig != links_reg) {
1924 DEBUGOUT("LINKS changed from %08X to %08X\n",
1925 links_orig, links_reg);
1928 if (link_up_wait_to_complete) {
1929 for (i = 0; i < hw->mac.max_link_up_time; i++) {
1930 if (!(links_reg & TXGBE_PORTSTAT_UP)) {
1937 links_reg = rd32(hw, TXGBE_PORTSTAT);
1940 if (links_reg & TXGBE_PORTSTAT_UP)
1946 switch (links_reg & TXGBE_PORTSTAT_BW_MASK) {
1947 case TXGBE_PORTSTAT_BW_10G:
1948 *speed = TXGBE_LINK_SPEED_10GB_FULL;
1950 case TXGBE_PORTSTAT_BW_1G:
1951 *speed = TXGBE_LINK_SPEED_1GB_FULL;
1953 case TXGBE_PORTSTAT_BW_100M:
1954 *speed = TXGBE_LINK_SPEED_100M_FULL;
1957 *speed = TXGBE_LINK_SPEED_UNKNOWN;
1964 * txgbe_get_wwn_prefix - Get alternative WWNN/WWPN prefix from
1966 * @hw: pointer to hardware structure
1967 * @wwnn_prefix: the alternative WWNN prefix
1968 * @wwpn_prefix: the alternative WWPN prefix
1970 * This function will read the EEPROM from the alternative SAN MAC address
1971 * block to check the support for the alternative WWNN/WWPN prefix support.
1973 s32 txgbe_get_wwn_prefix(struct txgbe_hw *hw, u16 *wwnn_prefix,
1977 u16 alt_san_mac_blk_offset;
1979 DEBUGFUNC("txgbe_get_wwn_prefix");
1981 /* clear output first */
1982 *wwnn_prefix = 0xFFFF;
1983 *wwpn_prefix = 0xFFFF;
1985 /* check if alternative SAN MAC is supported */
1986 offset = TXGBE_ALT_SAN_MAC_ADDR_BLK_PTR;
1987 if (hw->rom.readw_sw(hw, offset, &alt_san_mac_blk_offset))
1988 goto wwn_prefix_err;
1990 if (alt_san_mac_blk_offset == 0 || alt_san_mac_blk_offset == 0xFFFF)
1991 goto wwn_prefix_out;
1993 /* check capability in alternative san mac address block */
1994 offset = alt_san_mac_blk_offset + TXGBE_ALT_SAN_MAC_ADDR_CAPS_OFFSET;
1995 if (hw->rom.read16(hw, offset, &caps))
1996 goto wwn_prefix_err;
1997 if (!(caps & TXGBE_ALT_SAN_MAC_ADDR_CAPS_ALTWWN))
1998 goto wwn_prefix_out;
2000 /* get the corresponding prefix for WWNN/WWPN */
2001 offset = alt_san_mac_blk_offset + TXGBE_ALT_SAN_MAC_ADDR_WWNN_OFFSET;
2002 if (hw->rom.read16(hw, offset, wwnn_prefix))
2003 DEBUGOUT("eeprom read at offset %d failed", offset);
2005 offset = alt_san_mac_blk_offset + TXGBE_ALT_SAN_MAC_ADDR_WWPN_OFFSET;
2006 if (hw->rom.read16(hw, offset, wwpn_prefix))
2007 goto wwn_prefix_err;
2013 DEBUGOUT("eeprom read at offset %d failed", offset);
2018 * txgbe_set_mac_anti_spoofing - Enable/Disable MAC anti-spoofing
2019 * @hw: pointer to hardware structure
2020 * @enable: enable or disable switch for MAC anti-spoofing
2021 * @vf: Virtual Function pool - VF Pool to set for MAC anti-spoofing
2024 void txgbe_set_mac_anti_spoofing(struct txgbe_hw *hw, bool enable, int vf)
2026 int vf_target_reg = vf >> 3;
2027 int vf_target_shift = vf % 8;
2030 pfvfspoof = rd32(hw, TXGBE_POOLTXASMAC(vf_target_reg));
2032 pfvfspoof |= (1 << vf_target_shift);
2034 pfvfspoof &= ~(1 << vf_target_shift);
2035 wr32(hw, TXGBE_POOLTXASMAC(vf_target_reg), pfvfspoof);
2039 * txgbe_set_ethertype_anti_spoofing - Configure Ethertype anti-spoofing
2040 * @hw: pointer to hardware structure
2041 * @enable: enable or disable switch for Ethertype anti-spoofing
2042 * @vf: Virtual Function pool - VF Pool to set for Ethertype anti-spoofing
2045 void txgbe_set_ethertype_anti_spoofing(struct txgbe_hw *hw,
2046 bool enable, int vf)
2048 int vf_target_reg = vf >> 3;
2049 int vf_target_shift = vf % 8;
2052 pfvfspoof = rd32(hw, TXGBE_POOLTXASET(vf_target_reg));
2054 pfvfspoof |= (1 << vf_target_shift);
2056 pfvfspoof &= ~(1 << vf_target_shift);
2057 wr32(hw, TXGBE_POOLTXASET(vf_target_reg), pfvfspoof);
2061 * txgbe_get_device_caps - Get additional device capabilities
2062 * @hw: pointer to hardware structure
2063 * @device_caps: the EEPROM word with the extra device capabilities
2065 * This function will read the EEPROM location for the device capabilities,
2066 * and return the word through device_caps.
2068 s32 txgbe_get_device_caps(struct txgbe_hw *hw, u16 *device_caps)
2070 DEBUGFUNC("txgbe_get_device_caps");
2072 hw->rom.readw_sw(hw, TXGBE_DEVICE_CAPS, device_caps);
2078 * txgbe_set_pba - Initialize Rx packet buffer
2079 * @hw: pointer to hardware structure
2080 * @num_pb: number of packet buffers to allocate
2081 * @headroom: reserve n KB of headroom
2082 * @strategy: packet buffer allocation strategy
2084 void txgbe_set_pba(struct txgbe_hw *hw, int num_pb, u32 headroom,
2087 u32 pbsize = hw->mac.rx_pb_size;
2089 u32 rxpktsize, txpktsize, txpbthresh;
2091 UNREFERENCED_PARAMETER(hw);
2093 /* Reserve headroom */
2099 /* Divide remaining packet buffer space amongst the number of packet
2100 * buffers requested using supplied strategy.
2103 case PBA_STRATEGY_WEIGHTED:
2104 /* txgbe_dcb_pba_80_48 strategy weight first half of packet
2105 * buffer with 5/8 of the packet buffer space.
2107 rxpktsize = (pbsize * 5) / (num_pb * 4);
2108 pbsize -= rxpktsize * (num_pb / 2);
2110 for (; i < (num_pb / 2); i++)
2111 wr32(hw, TXGBE_PBRXSIZE(i), rxpktsize);
2112 /* fall through - configure remaining packet buffers */
2113 case PBA_STRATEGY_EQUAL:
2114 rxpktsize = (pbsize / (num_pb - i));
2116 for (; i < num_pb; i++)
2117 wr32(hw, TXGBE_PBRXSIZE(i), rxpktsize);
2123 /* Only support an equally distributed Tx packet buffer strategy. */
2124 txpktsize = TXGBE_PBTXSIZE_MAX / num_pb;
2125 txpbthresh = (txpktsize / 1024) - TXGBE_TXPKT_SIZE_MAX;
2126 for (i = 0; i < num_pb; i++) {
2127 wr32(hw, TXGBE_PBTXSIZE(i), txpktsize);
2128 wr32(hw, TXGBE_PBTXDMATH(i), txpbthresh);
2131 /* Clear unused TCs, if any, to zero buffer size*/
2132 for (; i < TXGBE_MAX_UP; i++) {
2133 wr32(hw, TXGBE_PBRXSIZE(i), 0);
2134 wr32(hw, TXGBE_PBTXSIZE(i), 0);
2135 wr32(hw, TXGBE_PBTXDMATH(i), 0);
2140 * txgbe_clear_tx_pending - Clear pending TX work from the PCIe fifo
2141 * @hw: pointer to the hardware structure
2143 * The MACs can experience issues if TX work is still pending
2144 * when a reset occurs. This function prevents this by flushing the PCIe
2145 * buffers on the system.
2147 void txgbe_clear_tx_pending(struct txgbe_hw *hw)
2149 u32 hlreg0, i, poll;
2152 * If double reset is not requested then all transactions should
2153 * already be clear and as such there is no work to do
2155 if (!(hw->mac.flags & TXGBE_FLAGS_DOUBLE_RESET_REQUIRED))
2158 hlreg0 = rd32(hw, TXGBE_PSRCTL);
2159 wr32(hw, TXGBE_PSRCTL, hlreg0 | TXGBE_PSRCTL_LBENA);
2161 /* Wait for a last completion before clearing buffers */
2166 * Before proceeding, make sure that the PCIe block does not have
2167 * transactions pending.
2169 poll = (800 * 11) / 10;
2170 for (i = 0; i < poll; i++)
2173 /* Flush all writes and allow 20usec for all transactions to clear */
2177 /* restore previous register values */
2178 wr32(hw, TXGBE_PSRCTL, hlreg0);
2182 * txgbe_get_thermal_sensor_data - Gathers thermal sensor data
2183 * @hw: pointer to hardware structure
2185 * Returns the thermal sensor data structure
2187 s32 txgbe_get_thermal_sensor_data(struct txgbe_hw *hw)
2189 struct txgbe_thermal_sensor_data *data = &hw->mac.thermal_sensor_data;
2193 DEBUGFUNC("txgbe_get_thermal_sensor_data");
2195 /* Only support thermal sensors attached to physical port 0 */
2196 if (hw->bus.lan_id != 0)
2197 return TXGBE_NOT_IMPLEMENTED;
2199 ts_stat = rd32(hw, TXGBE_TSSTAT);
2200 tsv = (s64)TXGBE_TSSTAT_DATA(ts_stat);
2201 tsv = tsv > 1200 ? tsv : 1200;
2202 tsv = -(48380 << 8) / 1000
2203 + tsv * (31020 << 8) / 100000
2204 - tsv * tsv * (18201 << 8) / 100000000
2205 + tsv * tsv * tsv * (81542 << 8) / 1000000000000
2206 - tsv * tsv * tsv * tsv * (16743 << 8) / 1000000000000000;
2209 data->sensor[0].temp = (s16)tsv;
2215 * txgbe_init_thermal_sensor_thresh - Inits thermal sensor thresholds
2216 * @hw: pointer to hardware structure
2218 * Inits the thermal sensor thresholds according to the NVM map
2219 * and save off the threshold and location values into mac.thermal_sensor_data
2221 s32 txgbe_init_thermal_sensor_thresh(struct txgbe_hw *hw)
2223 struct txgbe_thermal_sensor_data *data = &hw->mac.thermal_sensor_data;
2225 DEBUGFUNC("txgbe_init_thermal_sensor_thresh");
2227 memset(data, 0, sizeof(struct txgbe_thermal_sensor_data));
2229 if (hw->bus.lan_id != 0)
2230 return TXGBE_NOT_IMPLEMENTED;
2232 wr32(hw, TXGBE_TSCTRL, TXGBE_TSCTRL_EVALMD);
2233 wr32(hw, TXGBE_TSINTR,
2234 TXGBE_TSINTR_AEN | TXGBE_TSINTR_DEN);
2235 wr32(hw, TXGBE_TSEN, TXGBE_TSEN_ENA);
2238 data->sensor[0].alarm_thresh = 100;
2239 wr32(hw, TXGBE_TSATHRE, 677);
2240 data->sensor[0].dalarm_thresh = 90;
2241 wr32(hw, TXGBE_TSDTHRE, 614);
2246 void txgbe_disable_rx(struct txgbe_hw *hw)
2250 pfdtxgswc = rd32(hw, TXGBE_PSRCTL);
2251 if (pfdtxgswc & TXGBE_PSRCTL_LBENA) {
2252 pfdtxgswc &= ~TXGBE_PSRCTL_LBENA;
2253 wr32(hw, TXGBE_PSRCTL, pfdtxgswc);
2254 hw->mac.set_lben = true;
2256 hw->mac.set_lben = false;
2259 wr32m(hw, TXGBE_PBRXCTL, TXGBE_PBRXCTL_ENA, 0);
2260 wr32m(hw, TXGBE_MACRXCFG, TXGBE_MACRXCFG_ENA, 0);
2263 void txgbe_enable_rx(struct txgbe_hw *hw)
2267 wr32m(hw, TXGBE_MACRXCFG, TXGBE_MACRXCFG_ENA, TXGBE_MACRXCFG_ENA);
2268 wr32m(hw, TXGBE_PBRXCTL, TXGBE_PBRXCTL_ENA, TXGBE_PBRXCTL_ENA);
2270 if (hw->mac.set_lben) {
2271 pfdtxgswc = rd32(hw, TXGBE_PSRCTL);
2272 pfdtxgswc |= TXGBE_PSRCTL_LBENA;
2273 wr32(hw, TXGBE_PSRCTL, pfdtxgswc);
2274 hw->mac.set_lben = false;
2279 * txgbe_setup_mac_link_multispeed_fiber - Set MAC link speed
2280 * @hw: pointer to hardware structure
2281 * @speed: new link speed
2282 * @autoneg_wait_to_complete: true when waiting for completion is needed
2284 * Set the link speed in the MAC and/or PHY register and restarts link.
2286 s32 txgbe_setup_mac_link_multispeed_fiber(struct txgbe_hw *hw,
2288 bool autoneg_wait_to_complete)
2290 u32 link_speed = TXGBE_LINK_SPEED_UNKNOWN;
2291 u32 highest_link_speed = TXGBE_LINK_SPEED_UNKNOWN;
2295 bool autoneg, link_up = false;
2297 DEBUGFUNC("txgbe_setup_mac_link_multispeed_fiber");
2299 /* Mask off requested but non-supported speeds */
2300 status = hw->mac.get_link_capabilities(hw, &link_speed, &autoneg);
2304 speed &= link_speed;
2306 /* Try each speed one by one, highest priority first. We do this in
2307 * software because 10Gb fiber doesn't support speed autonegotiation.
2309 if (speed & TXGBE_LINK_SPEED_10GB_FULL) {
2311 highest_link_speed = TXGBE_LINK_SPEED_10GB_FULL;
2313 /* Set the module link speed */
2314 switch (hw->phy.media_type) {
2315 case txgbe_media_type_fiber:
2316 hw->mac.set_rate_select_speed(hw,
2317 TXGBE_LINK_SPEED_10GB_FULL);
2319 case txgbe_media_type_fiber_qsfp:
2320 /* QSFP module automatically detects MAC link speed */
2323 DEBUGOUT("Unexpected media type.\n");
2327 /* Allow module to change analog characteristics (1G->10G) */
2330 status = hw->mac.setup_mac_link(hw,
2331 TXGBE_LINK_SPEED_10GB_FULL,
2332 autoneg_wait_to_complete);
2336 /* Flap the Tx laser if it has not already been done */
2337 hw->mac.flap_tx_laser(hw);
2339 /* Wait for the controller to acquire link. Per IEEE 802.3ap,
2340 * Section 73.10.2, we may have to wait up to 500ms if KR is
2341 * attempted. uses the same timing for 10g SFI.
2343 for (i = 0; i < 5; i++) {
2344 /* Wait for the link partner to also set speed */
2347 /* If we have link, just jump out */
2348 status = hw->mac.check_link(hw, &link_speed,
2358 if (speed & TXGBE_LINK_SPEED_1GB_FULL) {
2360 if (highest_link_speed == TXGBE_LINK_SPEED_UNKNOWN)
2361 highest_link_speed = TXGBE_LINK_SPEED_1GB_FULL;
2363 /* Set the module link speed */
2364 switch (hw->phy.media_type) {
2365 case txgbe_media_type_fiber:
2366 hw->mac.set_rate_select_speed(hw,
2367 TXGBE_LINK_SPEED_1GB_FULL);
2369 case txgbe_media_type_fiber_qsfp:
2370 /* QSFP module automatically detects link speed */
2373 DEBUGOUT("Unexpected media type.\n");
2377 /* Allow module to change analog characteristics (10G->1G) */
2380 status = hw->mac.setup_mac_link(hw,
2381 TXGBE_LINK_SPEED_1GB_FULL,
2382 autoneg_wait_to_complete);
2386 /* Flap the Tx laser if it has not already been done */
2387 hw->mac.flap_tx_laser(hw);
2389 /* Wait for the link partner to also set speed */
2392 /* If we have link, just jump out */
2393 status = hw->mac.check_link(hw, &link_speed, &link_up, false);
2401 /* We didn't get link. Configure back to the highest speed we tried,
2402 * (if there was more than one). We call ourselves back with just the
2403 * single highest speed that the user requested.
2406 status = txgbe_setup_mac_link_multispeed_fiber(hw,
2408 autoneg_wait_to_complete);
2411 /* Set autoneg_advertised value based on input link speed */
2412 hw->phy.autoneg_advertised = 0;
2414 if (speed & TXGBE_LINK_SPEED_10GB_FULL)
2415 hw->phy.autoneg_advertised |= TXGBE_LINK_SPEED_10GB_FULL;
2417 if (speed & TXGBE_LINK_SPEED_1GB_FULL)
2418 hw->phy.autoneg_advertised |= TXGBE_LINK_SPEED_1GB_FULL;
2424 * txgbe_init_shared_code - Initialize the shared code
2425 * @hw: pointer to hardware structure
2427 * This will assign function pointers and assign the MAC type and PHY code.
2428 * Does not touch the hardware. This function must be called prior to any
2429 * other function in the shared code. The txgbe_hw structure should be
2430 * memset to 0 prior to calling this function. The following fields in
2431 * hw structure should be filled in prior to calling this function:
2432 * hw_addr, back, device_id, vendor_id, subsystem_device_id,
2433 * subsystem_vendor_id, and revision_id
2435 s32 txgbe_init_shared_code(struct txgbe_hw *hw)
2439 DEBUGFUNC("txgbe_init_shared_code");
2444 txgbe_set_mac_type(hw);
2446 txgbe_init_ops_dummy(hw);
2447 switch (hw->mac.type) {
2448 case txgbe_mac_raptor:
2449 status = txgbe_init_ops_pf(hw);
2451 case txgbe_mac_raptor_vf:
2452 status = txgbe_init_ops_vf(hw);
2455 status = TXGBE_ERR_DEVICE_NOT_SUPPORTED;
2458 hw->mac.max_link_up_time = TXGBE_LINK_UP_TIME;
2460 hw->bus.set_lan_id(hw);
2466 * txgbe_set_mac_type - Sets MAC type
2467 * @hw: pointer to the HW structure
2469 * This function sets the mac type of the adapter based on the
2470 * vendor ID and device ID stored in the hw structure.
2472 s32 txgbe_set_mac_type(struct txgbe_hw *hw)
2476 DEBUGFUNC("txgbe_set_mac_type");
2478 if (hw->vendor_id != PCI_VENDOR_ID_WANGXUN) {
2479 DEBUGOUT("Unsupported vendor id: %x", hw->vendor_id);
2480 return TXGBE_ERR_DEVICE_NOT_SUPPORTED;
2483 switch (hw->device_id) {
2484 case TXGBE_DEV_ID_SP1000:
2485 case TXGBE_DEV_ID_WX1820:
2486 hw->mac.type = txgbe_mac_raptor;
2488 case TXGBE_DEV_ID_SP1000_VF:
2489 case TXGBE_DEV_ID_WX1820_VF:
2490 hw->phy.media_type = txgbe_media_type_virtual;
2491 hw->mac.type = txgbe_mac_raptor_vf;
2494 err = TXGBE_ERR_DEVICE_NOT_SUPPORTED;
2495 DEBUGOUT("Unsupported device id: %x", hw->device_id);
2499 DEBUGOUT("found mac: %d, returns: %d\n",
2504 void txgbe_init_mac_link_ops(struct txgbe_hw *hw)
2506 struct txgbe_mac_info *mac = &hw->mac;
2508 DEBUGFUNC("txgbe_init_mac_link_ops");
2511 * enable the laser control functions for SFP+ fiber
2512 * and MNG not enabled
2514 if (hw->phy.media_type == txgbe_media_type_fiber &&
2515 !txgbe_mng_enabled(hw)) {
2516 mac->disable_tx_laser =
2517 txgbe_disable_tx_laser_multispeed_fiber;
2518 mac->enable_tx_laser =
2519 txgbe_enable_tx_laser_multispeed_fiber;
2520 mac->flap_tx_laser =
2521 txgbe_flap_tx_laser_multispeed_fiber;
2524 if ((hw->phy.media_type == txgbe_media_type_fiber ||
2525 hw->phy.media_type == txgbe_media_type_fiber_qsfp) &&
2526 hw->phy.multispeed_fiber) {
2527 /* Set up dual speed SFP+ support */
2528 mac->setup_link = txgbe_setup_mac_link_multispeed_fiber;
2529 mac->setup_mac_link = txgbe_setup_mac_link;
2530 mac->set_rate_select_speed = txgbe_set_hard_rate_select_speed;
2532 mac->setup_link = txgbe_setup_mac_link;
2533 mac->set_rate_select_speed = txgbe_set_hard_rate_select_speed;
2538 * txgbe_init_phy_raptor - PHY/SFP specific init
2539 * @hw: pointer to hardware structure
2541 * Initialize any function pointers that were not able to be
2542 * set during init_shared_code because the PHY/SFP type was
2543 * not known. Perform the SFP init if necessary.
2546 s32 txgbe_init_phy_raptor(struct txgbe_hw *hw)
2548 struct txgbe_mac_info *mac = &hw->mac;
2549 struct txgbe_phy_info *phy = &hw->phy;
2552 DEBUGFUNC("txgbe_init_phy_raptor");
2554 if ((hw->device_id & 0xFF) == TXGBE_DEV_ID_QSFP) {
2555 /* Store flag indicating I2C bus access control unit. */
2556 hw->phy.qsfp_shared_i2c_bus = TRUE;
2558 /* Initialize access to QSFP+ I2C bus */
2562 /* Identify the PHY or SFP module */
2563 err = phy->identify(hw);
2564 if (err == TXGBE_ERR_SFP_NOT_SUPPORTED)
2565 goto init_phy_ops_out;
2567 /* Setup function pointers based on detected SFP module and speeds */
2568 txgbe_init_mac_link_ops(hw);
2570 /* If copper media, overwrite with copper function pointers */
2571 if (phy->media_type == txgbe_media_type_copper) {
2572 mac->setup_link = txgbe_setup_copper_link_raptor;
2573 mac->get_link_capabilities =
2574 txgbe_get_copper_link_capabilities;
2577 if (phy->media_type == txgbe_media_type_backplane) {
2578 mac->kr_handle = txgbe_kr_handle;
2579 mac->bp_down_event = txgbe_bp_down_event;
2582 /* Set necessary function pointers based on PHY type */
2583 switch (hw->phy.type) {
2585 phy->setup_link = txgbe_setup_phy_link_tnx;
2586 phy->check_link = txgbe_check_phy_link_tnx;
2596 s32 txgbe_setup_sfp_modules(struct txgbe_hw *hw)
2600 DEBUGFUNC("txgbe_setup_sfp_modules");
2602 if (hw->phy.sfp_type == txgbe_sfp_type_unknown)
2605 txgbe_init_mac_link_ops(hw);
2607 /* PHY config will finish before releasing the semaphore */
2608 err = hw->mac.acquire_swfw_sync(hw, TXGBE_MNGSEM_SWPHY);
2610 return TXGBE_ERR_SWFW_SYNC;
2612 /* Release the semaphore */
2613 hw->mac.release_swfw_sync(hw, TXGBE_MNGSEM_SWPHY);
2615 /* Delay obtaining semaphore again to allow FW access
2616 * prot_autoc_write uses the semaphore too.
2618 msec_delay(hw->rom.semaphore_delay);
2621 DEBUGOUT("sfp module setup not complete\n");
2622 return TXGBE_ERR_SFP_SETUP_NOT_COMPLETE;
2629 * txgbe_prot_autoc_read_raptor - Hides MAC differences needed for AUTOC read
2630 * @hw: pointer to hardware structure
2631 * @locked: Return the if we locked for this read.
2632 * @value: Value we read from AUTOC
2634 * For this part we need to wrap read-modify-writes with a possible
2635 * FW/SW lock. It is assumed this lock will be freed with the next
2636 * prot_autoc_write_raptor().
2638 s32 txgbe_prot_autoc_read_raptor(struct txgbe_hw *hw, bool *locked, u64 *value)
2641 bool lock_state = false;
2643 /* If LESM is on then we need to hold the SW/FW semaphore. */
2644 if (txgbe_verify_lesm_fw_enabled_raptor(hw)) {
2645 err = hw->mac.acquire_swfw_sync(hw,
2646 TXGBE_MNGSEM_SWPHY);
2648 return TXGBE_ERR_SWFW_SYNC;
2654 *locked = lock_state;
2656 *value = txgbe_autoc_read(hw);
2661 * txgbe_prot_autoc_write_raptor - Hides MAC differences needed for AUTOC write
2662 * @hw: pointer to hardware structure
2663 * @autoc: value to write to AUTOC
2664 * @locked: bool to indicate whether the SW/FW lock was already taken by
2665 * previous prot_autoc_read_raptor.
2667 * This part may need to hold the SW/FW lock around all writes to
2668 * AUTOC. Likewise after a write we need to do a pipeline reset.
2670 s32 txgbe_prot_autoc_write_raptor(struct txgbe_hw *hw, bool locked, u64 autoc)
2674 /* Blocked by MNG FW so bail */
2675 if (txgbe_check_reset_blocked(hw))
2678 /* We only need to get the lock if:
2679 * - We didn't do it already (in the read part of a read-modify-write)
2680 * - LESM is enabled.
2682 if (!locked && txgbe_verify_lesm_fw_enabled_raptor(hw)) {
2683 err = hw->mac.acquire_swfw_sync(hw,
2684 TXGBE_MNGSEM_SWPHY);
2686 return TXGBE_ERR_SWFW_SYNC;
2691 txgbe_autoc_write(hw, autoc);
2692 err = txgbe_reset_pipeline_raptor(hw);
2695 /* Free the SW/FW semaphore as we either grabbed it here or
2696 * already had it when this function was called.
2699 hw->mac.release_swfw_sync(hw, TXGBE_MNGSEM_SWPHY);
2705 * txgbe_init_ops_pf - Inits func ptrs and MAC type
2706 * @hw: pointer to hardware structure
2708 * Initialize the function pointers and assign the MAC type.
2709 * Does not touch the hardware.
2711 s32 txgbe_init_ops_pf(struct txgbe_hw *hw)
2713 struct txgbe_bus_info *bus = &hw->bus;
2714 struct txgbe_mac_info *mac = &hw->mac;
2715 struct txgbe_phy_info *phy = &hw->phy;
2716 struct txgbe_rom_info *rom = &hw->rom;
2717 struct txgbe_mbx_info *mbx = &hw->mbx;
2719 DEBUGFUNC("txgbe_init_ops_pf");
2722 bus->set_lan_id = txgbe_set_lan_id_multi_port;
2725 phy->get_media_type = txgbe_get_media_type_raptor;
2726 phy->identify = txgbe_identify_phy;
2727 phy->init = txgbe_init_phy_raptor;
2728 phy->read_reg = txgbe_read_phy_reg;
2729 phy->write_reg = txgbe_write_phy_reg;
2730 phy->read_reg_mdi = txgbe_read_phy_reg_mdi;
2731 phy->write_reg_mdi = txgbe_write_phy_reg_mdi;
2732 phy->setup_link = txgbe_setup_phy_link;
2733 phy->setup_link_speed = txgbe_setup_phy_link_speed;
2734 phy->get_fw_version = txgbe_get_phy_fw_version;
2735 phy->read_i2c_byte = txgbe_read_i2c_byte;
2736 phy->write_i2c_byte = txgbe_write_i2c_byte;
2737 phy->read_i2c_sff8472 = txgbe_read_i2c_sff8472;
2738 phy->read_i2c_eeprom = txgbe_read_i2c_eeprom;
2739 phy->write_i2c_eeprom = txgbe_write_i2c_eeprom;
2740 phy->identify_sfp = txgbe_identify_module;
2741 phy->read_i2c_byte_unlocked = txgbe_read_i2c_byte_unlocked;
2742 phy->write_i2c_byte_unlocked = txgbe_write_i2c_byte_unlocked;
2743 phy->reset = txgbe_reset_phy;
2746 mac->init_hw = txgbe_init_hw;
2747 mac->start_hw = txgbe_start_hw_raptor;
2748 mac->clear_hw_cntrs = txgbe_clear_hw_cntrs;
2749 mac->enable_rx_dma = txgbe_enable_rx_dma_raptor;
2750 mac->get_mac_addr = txgbe_get_mac_addr;
2751 mac->stop_hw = txgbe_stop_hw;
2752 mac->acquire_swfw_sync = txgbe_acquire_swfw_sync;
2753 mac->release_swfw_sync = txgbe_release_swfw_sync;
2754 mac->reset_hw = txgbe_reset_hw;
2755 mac->update_mc_addr_list = txgbe_update_mc_addr_list;
2757 mac->disable_sec_rx_path = txgbe_disable_sec_rx_path;
2758 mac->enable_sec_rx_path = txgbe_enable_sec_rx_path;
2759 mac->disable_sec_tx_path = txgbe_disable_sec_tx_path;
2760 mac->enable_sec_tx_path = txgbe_enable_sec_tx_path;
2761 mac->get_san_mac_addr = txgbe_get_san_mac_addr;
2762 mac->set_san_mac_addr = txgbe_set_san_mac_addr;
2763 mac->get_device_caps = txgbe_get_device_caps;
2764 mac->get_wwn_prefix = txgbe_get_wwn_prefix;
2765 mac->autoc_read = txgbe_autoc_read;
2766 mac->autoc_write = txgbe_autoc_write;
2767 mac->prot_autoc_read = txgbe_prot_autoc_read_raptor;
2768 mac->prot_autoc_write = txgbe_prot_autoc_write_raptor;
2770 /* RAR, Multicast, VLAN */
2771 mac->set_rar = txgbe_set_rar;
2772 mac->clear_rar = txgbe_clear_rar;
2773 mac->init_rx_addrs = txgbe_init_rx_addrs;
2774 mac->enable_rx = txgbe_enable_rx;
2775 mac->disable_rx = txgbe_disable_rx;
2776 mac->set_vmdq = txgbe_set_vmdq;
2777 mac->clear_vmdq = txgbe_clear_vmdq;
2778 mac->set_vfta = txgbe_set_vfta;
2779 mac->set_vlvf = txgbe_set_vlvf;
2780 mac->clear_vfta = txgbe_clear_vfta;
2781 mac->init_uta_tables = txgbe_init_uta_tables;
2782 mac->setup_sfp = txgbe_setup_sfp_modules;
2783 mac->set_mac_anti_spoofing = txgbe_set_mac_anti_spoofing;
2784 mac->set_ethertype_anti_spoofing = txgbe_set_ethertype_anti_spoofing;
2787 mac->fc_enable = txgbe_fc_enable;
2788 mac->setup_fc = txgbe_setup_fc;
2789 mac->fc_autoneg = txgbe_fc_autoneg;
2792 mac->get_link_capabilities = txgbe_get_link_capabilities_raptor;
2793 mac->check_link = txgbe_check_mac_link;
2794 mac->setup_pba = txgbe_set_pba;
2796 /* Manageability interface */
2797 mac->set_fw_drv_ver = txgbe_hic_set_drv_ver;
2798 mac->get_thermal_sensor_data = txgbe_get_thermal_sensor_data;
2799 mac->init_thermal_sensor_thresh = txgbe_init_thermal_sensor_thresh;
2801 mbx->init_params = txgbe_init_mbx_params_pf;
2802 mbx->read = txgbe_read_mbx_pf;
2803 mbx->write = txgbe_write_mbx_pf;
2804 mbx->check_for_msg = txgbe_check_for_msg_pf;
2805 mbx->check_for_ack = txgbe_check_for_ack_pf;
2806 mbx->check_for_rst = txgbe_check_for_rst_pf;
2809 rom->init_params = txgbe_init_eeprom_params;
2810 rom->read16 = txgbe_ee_read16;
2811 rom->readw_buffer = txgbe_ee_readw_buffer;
2812 rom->readw_sw = txgbe_ee_readw_sw;
2813 rom->read32 = txgbe_ee_read32;
2814 rom->write16 = txgbe_ee_write16;
2815 rom->writew_buffer = txgbe_ee_writew_buffer;
2816 rom->writew_sw = txgbe_ee_writew_sw;
2817 rom->write32 = txgbe_ee_write32;
2818 rom->validate_checksum = txgbe_validate_eeprom_checksum;
2819 rom->update_checksum = txgbe_update_eeprom_checksum;
2820 rom->calc_checksum = txgbe_calc_eeprom_checksum;
2822 mac->mcft_size = TXGBE_RAPTOR_MC_TBL_SIZE;
2823 mac->vft_size = TXGBE_RAPTOR_VFT_TBL_SIZE;
2824 mac->num_rar_entries = TXGBE_RAPTOR_RAR_ENTRIES;
2825 mac->rx_pb_size = TXGBE_RAPTOR_RX_PB_SIZE;
2826 mac->max_rx_queues = TXGBE_RAPTOR_MAX_RX_QUEUES;
2827 mac->max_tx_queues = TXGBE_RAPTOR_MAX_TX_QUEUES;
2833 * txgbe_get_link_capabilities_raptor - Determines link capabilities
2834 * @hw: pointer to hardware structure
2835 * @speed: pointer to link speed
2836 * @autoneg: true when autoneg or autotry is enabled
2838 * Determines the link capabilities by reading the AUTOC register.
2840 s32 txgbe_get_link_capabilities_raptor(struct txgbe_hw *hw,
2847 DEBUGFUNC("txgbe_get_link_capabilities_raptor");
2849 /* Check if 1G SFP module. */
2850 if (hw->phy.sfp_type == txgbe_sfp_type_1g_cu_core0 ||
2851 hw->phy.sfp_type == txgbe_sfp_type_1g_cu_core1 ||
2852 hw->phy.sfp_type == txgbe_sfp_type_1g_lx_core0 ||
2853 hw->phy.sfp_type == txgbe_sfp_type_1g_lx_core1 ||
2854 hw->phy.sfp_type == txgbe_sfp_type_1g_sx_core0 ||
2855 hw->phy.sfp_type == txgbe_sfp_type_1g_sx_core1) {
2856 *speed = TXGBE_LINK_SPEED_1GB_FULL;
2862 * Determine link capabilities based on the stored value of AUTOC,
2863 * which represents EEPROM defaults. If AUTOC value has not
2864 * been stored, use the current register values.
2866 if (hw->mac.orig_link_settings_stored)
2867 autoc = hw->mac.orig_autoc;
2869 autoc = hw->mac.autoc_read(hw);
2871 switch (autoc & TXGBE_AUTOC_LMS_MASK) {
2872 case TXGBE_AUTOC_LMS_1G_LINK_NO_AN:
2873 *speed = TXGBE_LINK_SPEED_1GB_FULL;
2877 case TXGBE_AUTOC_LMS_10G_LINK_NO_AN:
2878 *speed = TXGBE_LINK_SPEED_10GB_FULL;
2882 case TXGBE_AUTOC_LMS_1G_AN:
2883 *speed = TXGBE_LINK_SPEED_1GB_FULL;
2887 case TXGBE_AUTOC_LMS_10G:
2888 *speed = TXGBE_LINK_SPEED_10GB_FULL;
2892 case TXGBE_AUTOC_LMS_KX4_KX_KR:
2893 case TXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN:
2894 *speed = TXGBE_LINK_SPEED_UNKNOWN;
2895 if (autoc & TXGBE_AUTOC_KR_SUPP)
2896 *speed |= TXGBE_LINK_SPEED_10GB_FULL;
2897 if (autoc & TXGBE_AUTOC_KX4_SUPP)
2898 *speed |= TXGBE_LINK_SPEED_10GB_FULL;
2899 if (autoc & TXGBE_AUTOC_KX_SUPP)
2900 *speed |= TXGBE_LINK_SPEED_1GB_FULL;
2904 case TXGBE_AUTOC_LMS_KX4_KX_KR_SGMII:
2905 *speed = TXGBE_LINK_SPEED_100M_FULL;
2906 if (autoc & TXGBE_AUTOC_KR_SUPP)
2907 *speed |= TXGBE_LINK_SPEED_10GB_FULL;
2908 if (autoc & TXGBE_AUTOC_KX4_SUPP)
2909 *speed |= TXGBE_LINK_SPEED_10GB_FULL;
2910 if (autoc & TXGBE_AUTOC_KX_SUPP)
2911 *speed |= TXGBE_LINK_SPEED_1GB_FULL;
2915 case TXGBE_AUTOC_LMS_SGMII_1G_100M:
2916 *speed = TXGBE_LINK_SPEED_1GB_FULL |
2917 TXGBE_LINK_SPEED_100M_FULL |
2918 TXGBE_LINK_SPEED_10M_FULL;
2923 return TXGBE_ERR_LINK_SETUP;
2926 if (hw->phy.multispeed_fiber) {
2927 *speed |= TXGBE_LINK_SPEED_10GB_FULL |
2928 TXGBE_LINK_SPEED_1GB_FULL;
2930 /* QSFP must not enable full auto-negotiation
2931 * Limited autoneg is enabled at 1G
2933 if (hw->phy.media_type == txgbe_media_type_fiber_qsfp)
2943 * txgbe_get_media_type_raptor - Get media type
2944 * @hw: pointer to hardware structure
2946 * Returns the media type (fiber, copper, backplane)
2948 u32 txgbe_get_media_type_raptor(struct txgbe_hw *hw)
2952 DEBUGFUNC("txgbe_get_media_type_raptor");
2954 if (hw->phy.ffe_set)
2955 txgbe_bp_mode_set(hw);
2957 /* Detect if there is a copper PHY attached. */
2958 switch (hw->phy.type) {
2959 case txgbe_phy_cu_unknown:
2961 media_type = txgbe_media_type_copper;
2967 switch (hw->subsystem_device_id & 0xFF) {
2968 case TXGBE_DEV_ID_KR_KX_KX4:
2969 case TXGBE_DEV_ID_MAC_SGMII:
2970 case TXGBE_DEV_ID_MAC_XAUI:
2971 /* Default device ID is mezzanine card KX/KX4 */
2972 media_type = txgbe_media_type_backplane;
2974 case TXGBE_DEV_ID_SFP:
2975 media_type = txgbe_media_type_fiber;
2977 case TXGBE_DEV_ID_QSFP:
2978 media_type = txgbe_media_type_fiber_qsfp;
2980 case TXGBE_DEV_ID_XAUI:
2981 case TXGBE_DEV_ID_SGMII:
2982 media_type = txgbe_media_type_copper;
2984 case TXGBE_DEV_ID_SFI_XAUI:
2985 if (hw->bus.lan_id == 0)
2986 media_type = txgbe_media_type_fiber;
2988 media_type = txgbe_media_type_copper;
2991 media_type = txgbe_media_type_unknown;
2999 * txgbe_start_mac_link_raptor - Setup MAC link settings
3000 * @hw: pointer to hardware structure
3001 * @autoneg_wait_to_complete: true when waiting for completion is needed
3003 * Configures link settings based on values in the txgbe_hw struct.
3004 * Restarts the link. Performs autonegotiation if needed.
3006 s32 txgbe_start_mac_link_raptor(struct txgbe_hw *hw,
3007 bool autoneg_wait_to_complete)
3010 bool got_lock = false;
3012 DEBUGFUNC("txgbe_start_mac_link_raptor");
3014 UNREFERENCED_PARAMETER(autoneg_wait_to_complete);
3016 /* reset_pipeline requires us to hold this lock as it writes to
3019 if (txgbe_verify_lesm_fw_enabled_raptor(hw)) {
3020 status = hw->mac.acquire_swfw_sync(hw, TXGBE_MNGSEM_SWPHY);
3028 txgbe_reset_pipeline_raptor(hw);
3031 hw->mac.release_swfw_sync(hw, TXGBE_MNGSEM_SWPHY);
3033 /* Add delay to filter out noises during initial link setup */
3041 * txgbe_disable_tx_laser_multispeed_fiber - Disable Tx laser
3042 * @hw: pointer to hardware structure
3044 * The base drivers may require better control over SFP+ module
3045 * PHY states. This includes selectively shutting down the Tx
3046 * laser on the PHY, effectively halting physical link.
3048 void txgbe_disable_tx_laser_multispeed_fiber(struct txgbe_hw *hw)
3050 u32 esdp_reg = rd32(hw, TXGBE_GPIODATA);
3052 /* Blocked by MNG FW so bail */
3053 if (txgbe_check_reset_blocked(hw))
3056 /* Disable Tx laser; allow 100us to go dark per spec */
3057 esdp_reg |= (TXGBE_GPIOBIT_0 | TXGBE_GPIOBIT_1);
3058 wr32(hw, TXGBE_GPIODATA, esdp_reg);
3064 * txgbe_enable_tx_laser_multispeed_fiber - Enable Tx laser
3065 * @hw: pointer to hardware structure
3067 * The base drivers may require better control over SFP+ module
3068 * PHY states. This includes selectively turning on the Tx
3069 * laser on the PHY, effectively starting physical link.
3071 void txgbe_enable_tx_laser_multispeed_fiber(struct txgbe_hw *hw)
3073 u32 esdp_reg = rd32(hw, TXGBE_GPIODATA);
3075 /* Enable Tx laser; allow 100ms to light up */
3076 esdp_reg &= ~(TXGBE_GPIOBIT_0 | TXGBE_GPIOBIT_1);
3077 wr32(hw, TXGBE_GPIODATA, esdp_reg);
3083 * txgbe_flap_tx_laser_multispeed_fiber - Flap Tx laser
3084 * @hw: pointer to hardware structure
3086 * When the driver changes the link speeds that it can support,
3087 * it sets autotry_restart to true to indicate that we need to
3088 * initiate a new autotry session with the link partner. To do
3089 * so, we set the speed then disable and re-enable the Tx laser, to
3090 * alert the link partner that it also needs to restart autotry on its
3091 * end. This is consistent with true clause 37 autoneg, which also
3092 * involves a loss of signal.
3094 void txgbe_flap_tx_laser_multispeed_fiber(struct txgbe_hw *hw)
3096 DEBUGFUNC("txgbe_flap_tx_laser_multispeed_fiber");
3098 /* Blocked by MNG FW so bail */
3099 if (txgbe_check_reset_blocked(hw))
3102 if (hw->mac.autotry_restart) {
3103 txgbe_disable_tx_laser_multispeed_fiber(hw);
3104 txgbe_enable_tx_laser_multispeed_fiber(hw);
3105 hw->mac.autotry_restart = false;
3110 * txgbe_set_hard_rate_select_speed - Set module link speed
3111 * @hw: pointer to hardware structure
3112 * @speed: link speed to set
3114 * Set module link speed via RS0/RS1 rate select pins.
3116 void txgbe_set_hard_rate_select_speed(struct txgbe_hw *hw,
3119 u32 esdp_reg = rd32(hw, TXGBE_GPIODATA);
3122 case TXGBE_LINK_SPEED_10GB_FULL:
3123 esdp_reg |= (TXGBE_GPIOBIT_4 | TXGBE_GPIOBIT_5);
3125 case TXGBE_LINK_SPEED_1GB_FULL:
3126 esdp_reg &= ~(TXGBE_GPIOBIT_4 | TXGBE_GPIOBIT_5);
3129 DEBUGOUT("Invalid fixed module speed\n");
3133 wr32(hw, TXGBE_GPIODATA, esdp_reg);
3138 * txgbe_setup_mac_link_smartspeed - Set MAC link speed using SmartSpeed
3139 * @hw: pointer to hardware structure
3140 * @speed: new link speed
3141 * @autoneg_wait_to_complete: true when waiting for completion is needed
3143 * Implements the Intel SmartSpeed algorithm.
3145 s32 txgbe_setup_mac_link_smartspeed(struct txgbe_hw *hw,
3147 bool autoneg_wait_to_complete)
3150 u32 link_speed = TXGBE_LINK_SPEED_UNKNOWN;
3152 bool link_up = false;
3153 u32 autoc_reg = rd32_epcs(hw, SR_AN_MMD_ADV_REG1);
3155 DEBUGFUNC("txgbe_setup_mac_link_smartspeed");
3157 /* Set autoneg_advertised value based on input link speed */
3158 hw->phy.autoneg_advertised = 0;
3160 if (speed & TXGBE_LINK_SPEED_10GB_FULL)
3161 hw->phy.autoneg_advertised |= TXGBE_LINK_SPEED_10GB_FULL;
3163 if (speed & TXGBE_LINK_SPEED_1GB_FULL)
3164 hw->phy.autoneg_advertised |= TXGBE_LINK_SPEED_1GB_FULL;
3166 if (speed & TXGBE_LINK_SPEED_100M_FULL)
3167 hw->phy.autoneg_advertised |= TXGBE_LINK_SPEED_100M_FULL;
3170 * Implement Intel SmartSpeed algorithm. SmartSpeed will reduce the
3171 * autoneg advertisement if link is unable to be established at the
3172 * highest negotiated rate. This can sometimes happen due to integrity
3173 * issues with the physical media connection.
3176 /* First, try to get link with full advertisement */
3177 hw->phy.smart_speed_active = false;
3178 for (j = 0; j < TXGBE_SMARTSPEED_MAX_RETRIES; j++) {
3179 status = txgbe_setup_mac_link(hw, speed,
3180 autoneg_wait_to_complete);
3185 * Wait for the controller to acquire link. Per IEEE 802.3ap,
3186 * Section 73.10.2, we may have to wait up to 500ms if KR is
3187 * attempted, or 200ms if KX/KX4/BX/BX4 is attempted, per
3188 * Table 9 in the AN MAS.
3190 for (i = 0; i < 5; i++) {
3193 /* If we have link, just jump out */
3194 status = hw->mac.check_link(hw, &link_speed, &link_up,
3205 * We didn't get link. If we advertised KR plus one of KX4/KX
3206 * (or BX4/BX), then disable KR and try again.
3208 if (((autoc_reg & TXGBE_AUTOC_KR_SUPP) == 0) ||
3209 ((autoc_reg & TXGBE_AUTOC_KX_SUPP) == 0 &&
3210 (autoc_reg & TXGBE_AUTOC_KX4_SUPP) == 0))
3213 /* Turn SmartSpeed on to disable KR support */
3214 hw->phy.smart_speed_active = true;
3215 status = txgbe_setup_mac_link(hw, speed,
3216 autoneg_wait_to_complete);
3221 * Wait for the controller to acquire link. 600ms will allow for
3222 * the AN link_fail_inhibit_timer as well for multiple cycles of
3223 * parallel detect, both 10g and 1g. This allows for the maximum
3224 * connect attempts as defined in the AN MAS table 73-7.
3226 for (i = 0; i < 6; i++) {
3229 /* If we have link, just jump out */
3230 status = hw->mac.check_link(hw, &link_speed, &link_up, false);
3238 /* We didn't get link. Turn SmartSpeed back off. */
3239 hw->phy.smart_speed_active = false;
3240 status = txgbe_setup_mac_link(hw, speed,
3241 autoneg_wait_to_complete);
3244 if (link_up && link_speed == TXGBE_LINK_SPEED_1GB_FULL)
3245 DEBUGOUT("Smartspeed has downgraded the link speed "
3246 "from the maximum advertised\n");
3251 * txgbe_setup_mac_link - Set MAC link speed
3252 * @hw: pointer to hardware structure
3253 * @speed: new link speed
3254 * @autoneg_wait_to_complete: true when waiting for completion is needed
3256 * Set the link speed in the AUTOC register and restarts link.
3258 s32 txgbe_setup_mac_link(struct txgbe_hw *hw,
3260 bool autoneg_wait_to_complete)
3262 bool autoneg = false;
3265 u64 autoc = hw->mac.autoc_read(hw);
3266 u64 pma_pmd_10gs = autoc & TXGBE_AUTOC_10GS_PMA_PMD_MASK;
3267 u64 pma_pmd_1g = autoc & TXGBE_AUTOC_1G_PMA_PMD_MASK;
3268 u64 link_mode = autoc & TXGBE_AUTOC_LMS_MASK;
3270 u32 link_capabilities = TXGBE_LINK_SPEED_UNKNOWN;
3272 DEBUGFUNC("txgbe_setup_mac_link");
3273 UNREFERENCED_PARAMETER(autoneg_wait_to_complete);
3275 /* Check to see if speed passed in is supported. */
3276 status = hw->mac.get_link_capabilities(hw,
3277 &link_capabilities, &autoneg);
3281 speed &= link_capabilities;
3282 if (speed == TXGBE_LINK_SPEED_UNKNOWN)
3283 return TXGBE_ERR_LINK_SETUP;
3285 /* Use stored value (EEPROM defaults) of AUTOC to find KR/KX4 support*/
3286 if (hw->mac.orig_link_settings_stored)
3287 orig_autoc = hw->mac.orig_autoc;
3291 link_mode = autoc & TXGBE_AUTOC_LMS_MASK;
3292 pma_pmd_1g = autoc & TXGBE_AUTOC_1G_PMA_PMD_MASK;
3294 if (link_mode == TXGBE_AUTOC_LMS_KX4_KX_KR ||
3295 link_mode == TXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
3296 link_mode == TXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
3297 /* Set KX4/KX/KR support according to speed requested */
3298 autoc &= ~(TXGBE_AUTOC_KX_SUPP |
3299 TXGBE_AUTOC_KX4_SUPP |
3300 TXGBE_AUTOC_KR_SUPP);
3301 if (speed & TXGBE_LINK_SPEED_10GB_FULL) {
3302 if (orig_autoc & TXGBE_AUTOC_KX4_SUPP)
3303 autoc |= TXGBE_AUTOC_KX4_SUPP;
3304 if (orig_autoc & TXGBE_AUTOC_KR_SUPP)
3305 autoc |= TXGBE_AUTOC_KR_SUPP;
3307 if (speed & TXGBE_LINK_SPEED_1GB_FULL)
3308 autoc |= TXGBE_AUTOC_KX_SUPP;
3309 } else if ((pma_pmd_1g == TXGBE_AUTOC_1G_SFI) &&
3310 (link_mode == TXGBE_AUTOC_LMS_1G_LINK_NO_AN ||
3311 link_mode == TXGBE_AUTOC_LMS_1G_AN)) {
3312 /* Switch from 1G SFI to 10G SFI if requested */
3313 if (speed == TXGBE_LINK_SPEED_10GB_FULL &&
3314 pma_pmd_10gs == TXGBE_AUTOC_10GS_SFI) {
3315 autoc &= ~TXGBE_AUTOC_LMS_MASK;
3316 autoc |= TXGBE_AUTOC_LMS_10G;
3318 } else if ((pma_pmd_10gs == TXGBE_AUTOC_10GS_SFI) &&
3319 (link_mode == TXGBE_AUTOC_LMS_10G)) {
3320 /* Switch from 10G SFI to 1G SFI if requested */
3321 if (speed == TXGBE_LINK_SPEED_1GB_FULL &&
3322 pma_pmd_1g == TXGBE_AUTOC_1G_SFI) {
3323 autoc &= ~TXGBE_AUTOC_LMS_MASK;
3324 if (autoneg || hw->phy.type == txgbe_phy_qsfp_intel)
3325 autoc |= TXGBE_AUTOC_LMS_1G_AN;
3327 autoc |= TXGBE_AUTOC_LMS_1G_LINK_NO_AN;
3331 autoc &= ~TXGBE_AUTOC_SPEED_MASK;
3332 autoc |= TXGBE_AUTOC_SPEED(speed);
3333 autoc &= ~TXGBE_AUTOC_AUTONEG;
3334 autoc |= (autoneg ? TXGBE_AUTOC_AUTONEG : 0);
3337 hw->mac.autoc_write(hw, autoc);
3339 /* Add delay to filter out noises during initial link setup */
3346 * txgbe_setup_copper_link_raptor - Set the PHY autoneg advertised field
3347 * @hw: pointer to hardware structure
3348 * @speed: new link speed
3349 * @autoneg_wait_to_complete: true if waiting is needed to complete
3351 * Restarts link on PHY and MAC based on settings passed in.
3353 static s32 txgbe_setup_copper_link_raptor(struct txgbe_hw *hw,
3355 bool autoneg_wait_to_complete)
3359 DEBUGFUNC("txgbe_setup_copper_link_raptor");
3361 /* Setup the PHY according to input speed */
3362 status = hw->phy.setup_link_speed(hw, speed,
3363 autoneg_wait_to_complete);
3365 txgbe_start_mac_link_raptor(hw, autoneg_wait_to_complete);
3371 txgbe_check_flash_load(struct txgbe_hw *hw, u32 check_bit)
3376 /* if there's flash existing */
3377 if (!(rd32(hw, TXGBE_SPISTAT) & TXGBE_SPISTAT_BPFLASH)) {
3378 /* wait hw load flash done */
3379 for (i = 0; i < 10; i++) {
3380 reg = rd32(hw, TXGBE_ILDRSTAT);
3381 if (!(reg & check_bit)) {
3388 err = TXGBE_ERR_FLASH_LOADING_FAILED;
3394 txgbe_reset_misc(struct txgbe_hw *hw)
3399 wr32(hw, TXGBE_ISBADDRL, hw->isb_dma & 0x00000000FFFFFFFF);
3400 wr32(hw, TXGBE_ISBADDRH, hw->isb_dma >> 32);
3402 value = rd32_epcs(hw, SR_XS_PCS_CTRL2);
3403 if ((value & 0x3) != SR_PCS_CTRL2_TYPE_SEL_X)
3404 hw->link_status = TXGBE_LINK_STATUS_NONE;
3406 /* receive packets that size > 2048 */
3407 wr32m(hw, TXGBE_MACRXCFG,
3408 TXGBE_MACRXCFG_JUMBO, TXGBE_MACRXCFG_JUMBO);
3410 wr32m(hw, TXGBE_FRMSZ, TXGBE_FRMSZ_MAX_MASK,
3411 TXGBE_FRMSZ_MAX(TXGBE_FRAME_SIZE_DFT));
3413 /* clear counters on read */
3414 wr32m(hw, TXGBE_MACCNTCTL,
3415 TXGBE_MACCNTCTL_RC, TXGBE_MACCNTCTL_RC);
3417 wr32m(hw, TXGBE_RXFCCFG,
3418 TXGBE_RXFCCFG_FC, TXGBE_RXFCCFG_FC);
3419 wr32m(hw, TXGBE_TXFCCFG,
3420 TXGBE_TXFCCFG_FC, TXGBE_TXFCCFG_FC);
3422 wr32m(hw, TXGBE_MACRXFLT,
3423 TXGBE_MACRXFLT_PROMISC, TXGBE_MACRXFLT_PROMISC);
3425 wr32m(hw, TXGBE_RSTSTAT,
3426 TXGBE_RSTSTAT_TMRINIT_MASK, TXGBE_RSTSTAT_TMRINIT(30));
3428 /* errata 4: initialize mng flex tbl and wakeup flex tbl*/
3429 wr32(hw, TXGBE_MNGFLEXSEL, 0);
3430 for (i = 0; i < 16; i++) {
3431 wr32(hw, TXGBE_MNGFLEXDWL(i), 0);
3432 wr32(hw, TXGBE_MNGFLEXDWH(i), 0);
3433 wr32(hw, TXGBE_MNGFLEXMSK(i), 0);
3435 wr32(hw, TXGBE_LANFLEXSEL, 0);
3436 for (i = 0; i < 16; i++) {
3437 wr32(hw, TXGBE_LANFLEXDWL(i), 0);
3438 wr32(hw, TXGBE_LANFLEXDWH(i), 0);
3439 wr32(hw, TXGBE_LANFLEXMSK(i), 0);
3442 /* set pause frame dst mac addr */
3443 wr32(hw, TXGBE_RXPBPFCDMACL, 0xC2000001);
3444 wr32(hw, TXGBE_RXPBPFCDMACH, 0x0180);
3446 hw->mac.init_thermal_sensor_thresh(hw);
3448 /* enable mac transmitter */
3449 wr32m(hw, TXGBE_MACTXCFG, TXGBE_MACTXCFG_TXE, TXGBE_MACTXCFG_TXE);
3451 hw->mac.autoc = hw->mac.orig_autoc;
3452 for (i = 0; i < 4; i++)
3453 wr32m(hw, TXGBE_IVAR(i), 0x80808080, 0);
3457 * txgbe_reset_hw - Perform hardware reset
3458 * @hw: pointer to hardware structure
3460 * Resets the hardware by resetting the transmit and receive units, masks
3461 * and clears all interrupts, perform a PHY reset, and perform a link (MAC)
3464 s32 txgbe_reset_hw(struct txgbe_hw *hw)
3469 DEBUGFUNC("txgbe_reset_hw");
3471 /* Call adapter stop to disable tx/rx and clear interrupts */
3472 status = hw->mac.stop_hw(hw);
3476 /* flush pending Tx transactions */
3477 txgbe_clear_tx_pending(hw);
3479 /* Identify PHY and related function pointers */
3480 status = hw->phy.init(hw);
3481 if (status == TXGBE_ERR_SFP_NOT_SUPPORTED)
3484 /* Setup SFP module if there is one present. */
3485 if (hw->phy.sfp_setup_needed) {
3486 status = hw->mac.setup_sfp(hw);
3487 hw->phy.sfp_setup_needed = false;
3489 if (status == TXGBE_ERR_SFP_NOT_SUPPORTED)
3493 if (!hw->phy.reset_disable)
3496 /* remember AUTOC from before we reset */
3497 autoc = hw->mac.autoc_read(hw);
3501 * Issue global reset to the MAC. Needs to be SW reset if link is up.
3502 * If link reset is used when link is up, it might reset the PHY when
3503 * mng is using it. If link is down or the flag to force full link
3504 * reset is set, then perform link reset.
3506 if (txgbe_mng_present(hw)) {
3507 txgbe_hic_reset(hw);
3509 wr32(hw, TXGBE_RST, TXGBE_RST_LAN(hw->bus.lan_id));
3514 txgbe_reset_misc(hw);
3516 if (hw->bus.lan_id == 0) {
3517 status = txgbe_check_flash_load(hw,
3518 TXGBE_ILDRSTAT_SWRST_LAN0);
3520 status = txgbe_check_flash_load(hw,
3521 TXGBE_ILDRSTAT_SWRST_LAN1);
3529 * Double resets are required for recovery from certain error
3530 * conditions. Between resets, it is necessary to stall to
3531 * allow time for any pending HW events to complete.
3533 if (hw->mac.flags & TXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
3534 hw->mac.flags &= ~TXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
3539 * Store the original AUTOC/AUTOC2 values if they have not been
3540 * stored off yet. Otherwise restore the stored original
3541 * values since the reset operation sets back to defaults.
3543 if (!hw->mac.orig_link_settings_stored) {
3544 hw->mac.orig_autoc = hw->mac.autoc_read(hw);
3545 hw->mac.orig_link_settings_stored = true;
3547 hw->mac.orig_autoc = autoc;
3550 if (hw->phy.ffe_set) {
3551 /* Make sure phy power is up */
3554 /* A temporary solution to set phy */
3555 txgbe_set_phy_temp(hw);
3558 /* Store the permanent mac address */
3559 hw->mac.get_mac_addr(hw, hw->mac.perm_addr);
3562 * Store MAC address from RAR0, clear receive address registers, and
3563 * clear the multicast table. Also reset num_rar_entries to 128,
3564 * since we modify this value when programming the SAN MAC address.
3566 hw->mac.num_rar_entries = 128;
3567 hw->mac.init_rx_addrs(hw);
3569 /* Store the permanent SAN mac address */
3570 hw->mac.get_san_mac_addr(hw, hw->mac.san_addr);
3572 /* Add the SAN MAC address to the RAR only if it's a valid address */
3573 if (txgbe_validate_mac_addr(hw->mac.san_addr) == 0) {
3574 /* Save the SAN MAC RAR index */
3575 hw->mac.san_mac_rar_index = hw->mac.num_rar_entries - 1;
3577 hw->mac.set_rar(hw, hw->mac.san_mac_rar_index,
3578 hw->mac.san_addr, 0, true);
3580 /* clear VMDq pool/queue selection for this RAR */
3581 hw->mac.clear_vmdq(hw, hw->mac.san_mac_rar_index,
3584 /* Reserve the last RAR for the SAN MAC address */
3585 hw->mac.num_rar_entries--;
3588 /* Store the alternative WWNN/WWPN prefix */
3589 hw->mac.get_wwn_prefix(hw, &hw->mac.wwnn_prefix,
3590 &hw->mac.wwpn_prefix);
3596 * txgbe_fdir_check_cmd_complete - poll to check whether FDIRPICMD is complete
3597 * @hw: pointer to hardware structure
3598 * @fdircmd: current value of FDIRCMD register
3600 static s32 txgbe_fdir_check_cmd_complete(struct txgbe_hw *hw, u32 *fdircmd)
3604 for (i = 0; i < TXGBE_FDIRCMD_CMD_POLL; i++) {
3605 *fdircmd = rd32(hw, TXGBE_FDIRPICMD);
3606 if (!(*fdircmd & TXGBE_FDIRPICMD_OP_MASK))
3611 return TXGBE_ERR_FDIR_CMD_INCOMPLETE;
3615 * txgbe_reinit_fdir_tables - Reinitialize Flow Director tables.
3616 * @hw: pointer to hardware structure
3618 s32 txgbe_reinit_fdir_tables(struct txgbe_hw *hw)
3622 u32 fdirctrl = rd32(hw, TXGBE_FDIRCTL);
3624 fdirctrl &= ~TXGBE_FDIRCTL_INITDONE;
3626 DEBUGFUNC("txgbe_reinit_fdir_tables");
3629 * Before starting reinitialization process,
3630 * FDIRPICMD.OP must be zero.
3632 err = txgbe_fdir_check_cmd_complete(hw, &fdircmd);
3634 DEBUGOUT("Flow Director previous command did not complete, aborting table re-initialization.\n");
3638 wr32(hw, TXGBE_FDIRFREE, 0);
3641 * adapters flow director init flow cannot be restarted,
3642 * Workaround silicon errata by performing the following steps
3643 * before re-writing the FDIRCTL control register with the same value.
3644 * - write 1 to bit 8 of FDIRPICMD register &
3645 * - write 0 to bit 8 of FDIRPICMD register
3647 wr32m(hw, TXGBE_FDIRPICMD, TXGBE_FDIRPICMD_CLR, TXGBE_FDIRPICMD_CLR);
3649 wr32m(hw, TXGBE_FDIRPICMD, TXGBE_FDIRPICMD_CLR, 0);
3652 * Clear FDIR Hash register to clear any leftover hashes
3653 * waiting to be programmed.
3655 wr32(hw, TXGBE_FDIRPIHASH, 0x00);
3658 wr32(hw, TXGBE_FDIRCTL, fdirctrl);
3661 /* Poll init-done after we write FDIRCTL register */
3662 for (i = 0; i < TXGBE_FDIR_INIT_DONE_POLL; i++) {
3663 if (rd32m(hw, TXGBE_FDIRCTL, TXGBE_FDIRCTL_INITDONE))
3667 if (i >= TXGBE_FDIR_INIT_DONE_POLL) {
3668 DEBUGOUT("Flow Director Signature poll time exceeded!\n");
3669 return TXGBE_ERR_FDIR_REINIT_FAILED;
3672 /* Clear FDIR statistics registers (read to clear) */
3673 rd32(hw, TXGBE_FDIRUSED);
3674 rd32(hw, TXGBE_FDIRFAIL);
3675 rd32(hw, TXGBE_FDIRMATCH);
3676 rd32(hw, TXGBE_FDIRMISS);
3677 rd32(hw, TXGBE_FDIRLEN);
3683 * txgbe_start_hw_raptor - Prepare hardware for Tx/Rx
3684 * @hw: pointer to hardware structure
3686 * Starts the hardware using the generic start_hw function
3687 * and the generation start_hw function.
3688 * Then performs revision-specific operations, if any.
3690 s32 txgbe_start_hw_raptor(struct txgbe_hw *hw)
3694 DEBUGFUNC("txgbe_start_hw_raptor");
3696 err = txgbe_start_hw(hw);
3700 err = txgbe_start_hw_gen2(hw);
3704 /* We need to run link autotry after the driver loads */
3705 hw->mac.autotry_restart = true;
3712 * txgbe_enable_rx_dma_raptor - Enable the Rx DMA unit
3713 * @hw: pointer to hardware structure
3714 * @regval: register value to write to RXCTRL
3716 * Enables the Rx DMA unit
3718 s32 txgbe_enable_rx_dma_raptor(struct txgbe_hw *hw, u32 regval)
3720 DEBUGFUNC("txgbe_enable_rx_dma_raptor");
3723 * Workaround silicon errata when enabling the Rx datapath.
3724 * If traffic is incoming before we enable the Rx unit, it could hang
3725 * the Rx DMA unit. Therefore, make sure the security engine is
3726 * completely disabled prior to enabling the Rx unit.
3729 hw->mac.disable_sec_rx_path(hw);
3731 if (regval & TXGBE_PBRXCTL_ENA)
3732 txgbe_enable_rx(hw);
3734 txgbe_disable_rx(hw);
3736 hw->mac.enable_sec_rx_path(hw);
3742 * txgbe_verify_lesm_fw_enabled_raptor - Checks LESM FW module state.
3743 * @hw: pointer to hardware structure
3745 * Returns true if the LESM FW module is present and enabled. Otherwise
3746 * returns false. Smart Speed must be disabled if LESM FW module is enabled.
3748 bool txgbe_verify_lesm_fw_enabled_raptor(struct txgbe_hw *hw)
3750 bool lesm_enabled = false;
3751 u16 fw_offset, fw_lesm_param_offset, fw_lesm_state;
3754 DEBUGFUNC("txgbe_verify_lesm_fw_enabled_raptor");
3756 /* get the offset to the Firmware Module block */
3757 status = hw->rom.read16(hw, TXGBE_FW_PTR, &fw_offset);
3759 if (status != 0 || fw_offset == 0 || fw_offset == 0xFFFF)
3762 /* get the offset to the LESM Parameters block */
3763 status = hw->rom.read16(hw, (fw_offset +
3764 TXGBE_FW_LESM_PARAMETERS_PTR),
3765 &fw_lesm_param_offset);
3768 fw_lesm_param_offset == 0 || fw_lesm_param_offset == 0xFFFF)
3771 /* get the LESM state word */
3772 status = hw->rom.read16(hw, (fw_lesm_param_offset +
3773 TXGBE_FW_LESM_STATE_1),
3776 if (status == 0 && (fw_lesm_state & TXGBE_FW_LESM_STATE_ENABLED))
3777 lesm_enabled = true;
3780 lesm_enabled = false;
3781 return lesm_enabled;
3785 * txgbe_reset_pipeline_raptor - perform pipeline reset
3787 * @hw: pointer to hardware structure
3789 * Reset pipeline by asserting Restart_AN together with LMS change to ensure
3790 * full pipeline reset. This function assumes the SW/FW lock is held.
3792 s32 txgbe_reset_pipeline_raptor(struct txgbe_hw *hw)
3797 autoc = hw->mac.autoc_read(hw);
3799 /* Enable link if disabled in NVM */
3800 if (autoc & TXGBE_AUTOC_LINK_DIA_MASK)
3801 autoc &= ~TXGBE_AUTOC_LINK_DIA_MASK;
3803 autoc |= TXGBE_AUTOC_AN_RESTART;
3804 /* Write AUTOC register with toggled LMS[2] bit and Restart_AN */
3805 hw->mac.autoc_write(hw, autoc ^ TXGBE_AUTOC_LMS_AN);
3807 /* Write AUTOC register with original LMS field and Restart_AN */
3808 hw->mac.autoc_write(hw, autoc);