1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2015-2020
5 #include "txgbe_type.h"
7 #include "txgbe_eeprom.h"
11 #define TXGBE_RAPTOR_MAX_TX_QUEUES 128
12 #define TXGBE_RAPTOR_MAX_RX_QUEUES 128
13 #define TXGBE_RAPTOR_RAR_ENTRIES 128
14 #define TXGBE_RAPTOR_MC_TBL_SIZE 128
16 static s32 txgbe_setup_copper_link_raptor(struct txgbe_hw *hw,
18 bool autoneg_wait_to_complete);
20 static s32 txgbe_mta_vector(struct txgbe_hw *hw, u8 *mc_addr);
21 static s32 txgbe_get_san_mac_addr_offset(struct txgbe_hw *hw,
25 * txgbe_start_hw - Prepare hardware for Tx/Rx
26 * @hw: pointer to hardware structure
28 * Starts the hardware by filling the bus info structure and media type, clears
29 * all on chip counters, initializes receive address registers, multicast
30 * table, VLAN filter table, calls routine to set up link and flow control
31 * settings, and leaves transmit and receive units disabled and uninitialized
33 s32 txgbe_start_hw(struct txgbe_hw *hw)
37 DEBUGFUNC("txgbe_start_hw");
39 /* Set the media type */
40 hw->phy.media_type = hw->phy.get_media_type(hw);
42 /* Clear statistics registers */
43 hw->mac.clear_hw_cntrs(hw);
45 /* Cache bit indicating need for crosstalk fix */
46 switch (hw->mac.type) {
47 case txgbe_mac_raptor:
48 hw->mac.get_device_caps(hw, &device_caps);
49 if (device_caps & TXGBE_DEVICE_CAPS_NO_CROSSTALK_WR)
50 hw->need_crosstalk_fix = false;
52 hw->need_crosstalk_fix = true;
55 hw->need_crosstalk_fix = false;
59 /* Clear adapter stopped flag */
60 hw->adapter_stopped = false;
66 * txgbe_start_hw_gen2 - Init sequence for common device family
67 * @hw: pointer to hw structure
69 * Performs the init sequence common to the second generation
72 s32 txgbe_start_hw_gen2(struct txgbe_hw *hw)
76 /* Clear the rate limiters */
77 for (i = 0; i < hw->mac.max_tx_queues; i++) {
78 wr32(hw, TXGBE_ARBPOOLIDX, i);
79 wr32(hw, TXGBE_ARBTXRATE, 0);
83 /* We need to run link autotry after the driver loads */
84 hw->mac.autotry_restart = true;
90 * txgbe_init_hw - Generic hardware initialization
91 * @hw: pointer to hardware structure
93 * Initialize the hardware by resetting the hardware, filling the bus info
94 * structure and media type, clears all on chip counters, initializes receive
95 * address registers, multicast table, VLAN filter table, calls routine to set
96 * up link and flow control settings, and leaves transmit and receive units
97 * disabled and uninitialized
99 s32 txgbe_init_hw(struct txgbe_hw *hw)
103 DEBUGFUNC("txgbe_init_hw");
105 /* Reset the hardware */
106 status = hw->mac.reset_hw(hw);
107 if (status == 0 || status == TXGBE_ERR_SFP_NOT_PRESENT) {
109 status = hw->mac.start_hw(hw);
113 DEBUGOUT("Failed to initialize HW, STATUS = %d\n", status);
119 * txgbe_clear_hw_cntrs - Generic clear hardware counters
120 * @hw: pointer to hardware structure
122 * Clears all hardware statistics counters by reading them from the hardware
123 * Statistics counters are clear on read.
125 s32 txgbe_clear_hw_cntrs(struct txgbe_hw *hw)
129 DEBUGFUNC("txgbe_clear_hw_cntrs");
132 /* don't write clear queue stats */
133 for (i = 0; i < TXGBE_MAX_QP; i++) {
134 hw->qp_last[i].rx_qp_packets = 0;
135 hw->qp_last[i].tx_qp_packets = 0;
136 hw->qp_last[i].rx_qp_bytes = 0;
137 hw->qp_last[i].tx_qp_bytes = 0;
138 hw->qp_last[i].rx_qp_mc_packets = 0;
142 for (i = 0; i < TXGBE_MAX_UP; i++) {
143 rd32(hw, TXGBE_PBRXUPXON(i));
144 rd32(hw, TXGBE_PBRXUPXOFF(i));
145 rd32(hw, TXGBE_PBTXUPXON(i));
146 rd32(hw, TXGBE_PBTXUPXOFF(i));
147 rd32(hw, TXGBE_PBTXUPOFF(i));
149 rd32(hw, TXGBE_PBRXMISS(i));
151 rd32(hw, TXGBE_PBRXLNKXON);
152 rd32(hw, TXGBE_PBRXLNKXOFF);
153 rd32(hw, TXGBE_PBTXLNKXON);
154 rd32(hw, TXGBE_PBTXLNKXOFF);
157 rd32(hw, TXGBE_DMARXPKT);
158 rd32(hw, TXGBE_DMATXPKT);
160 rd64(hw, TXGBE_DMARXOCTL);
161 rd64(hw, TXGBE_DMATXOCTL);
164 rd64(hw, TXGBE_MACRXERRCRCL);
165 rd64(hw, TXGBE_MACRXMPKTL);
166 rd64(hw, TXGBE_MACTXMPKTL);
168 rd64(hw, TXGBE_MACRXPKTL);
169 rd64(hw, TXGBE_MACTXPKTL);
170 rd64(hw, TXGBE_MACRXGBOCTL);
172 rd64(hw, TXGBE_MACRXOCTL);
173 rd32(hw, TXGBE_MACTXOCTL);
175 rd64(hw, TXGBE_MACRX1TO64L);
176 rd64(hw, TXGBE_MACRX65TO127L);
177 rd64(hw, TXGBE_MACRX128TO255L);
178 rd64(hw, TXGBE_MACRX256TO511L);
179 rd64(hw, TXGBE_MACRX512TO1023L);
180 rd64(hw, TXGBE_MACRX1024TOMAXL);
181 rd64(hw, TXGBE_MACTX1TO64L);
182 rd64(hw, TXGBE_MACTX65TO127L);
183 rd64(hw, TXGBE_MACTX128TO255L);
184 rd64(hw, TXGBE_MACTX256TO511L);
185 rd64(hw, TXGBE_MACTX512TO1023L);
186 rd64(hw, TXGBE_MACTX1024TOMAXL);
188 rd64(hw, TXGBE_MACRXERRLENL);
189 rd32(hw, TXGBE_MACRXOVERSIZE);
190 rd32(hw, TXGBE_MACRXJABBER);
193 rd32(hw, TXGBE_FCOECRC);
194 rd32(hw, TXGBE_FCOELAST);
195 rd32(hw, TXGBE_FCOERPDC);
196 rd32(hw, TXGBE_FCOEPRC);
197 rd32(hw, TXGBE_FCOEPTC);
198 rd32(hw, TXGBE_FCOEDWRC);
199 rd32(hw, TXGBE_FCOEDWTC);
201 /* Flow Director Stats */
202 rd32(hw, TXGBE_FDIRMATCH);
203 rd32(hw, TXGBE_FDIRMISS);
204 rd32(hw, TXGBE_FDIRUSED);
205 rd32(hw, TXGBE_FDIRUSED);
206 rd32(hw, TXGBE_FDIRFAIL);
207 rd32(hw, TXGBE_FDIRFAIL);
210 rd32(hw, TXGBE_LSECTX_UTPKT);
211 rd32(hw, TXGBE_LSECTX_ENCPKT);
212 rd32(hw, TXGBE_LSECTX_PROTPKT);
213 rd32(hw, TXGBE_LSECTX_ENCOCT);
214 rd32(hw, TXGBE_LSECTX_PROTOCT);
215 rd32(hw, TXGBE_LSECRX_UTPKT);
216 rd32(hw, TXGBE_LSECRX_BTPKT);
217 rd32(hw, TXGBE_LSECRX_NOSCIPKT);
218 rd32(hw, TXGBE_LSECRX_UNSCIPKT);
219 rd32(hw, TXGBE_LSECRX_DECOCT);
220 rd32(hw, TXGBE_LSECRX_VLDOCT);
221 rd32(hw, TXGBE_LSECRX_UNCHKPKT);
222 rd32(hw, TXGBE_LSECRX_DLYPKT);
223 rd32(hw, TXGBE_LSECRX_LATEPKT);
224 for (i = 0; i < 2; i++) {
225 rd32(hw, TXGBE_LSECRX_OKPKT(i));
226 rd32(hw, TXGBE_LSECRX_INVPKT(i));
227 rd32(hw, TXGBE_LSECRX_BADPKT(i));
229 rd32(hw, TXGBE_LSECRX_INVSAPKT);
230 rd32(hw, TXGBE_LSECRX_BADSAPKT);
236 * txgbe_get_mac_addr - Generic get MAC address
237 * @hw: pointer to hardware structure
238 * @mac_addr: Adapter MAC address
240 * Reads the adapter's MAC address from first Receive Address Register (RAR0)
241 * A reset of the adapter must be performed prior to calling this function
242 * in order for the MAC address to have been loaded from the EEPROM into RAR0
244 s32 txgbe_get_mac_addr(struct txgbe_hw *hw, u8 *mac_addr)
250 DEBUGFUNC("txgbe_get_mac_addr");
252 wr32(hw, TXGBE_ETHADDRIDX, 0);
253 rar_high = rd32(hw, TXGBE_ETHADDRH);
254 rar_low = rd32(hw, TXGBE_ETHADDRL);
256 for (i = 0; i < 2; i++)
257 mac_addr[i] = (u8)(rar_high >> (1 - i) * 8);
259 for (i = 0; i < 4; i++)
260 mac_addr[i + 2] = (u8)(rar_low >> (3 - i) * 8);
266 * txgbe_set_lan_id_multi_port - Set LAN id for PCIe multiple port devices
267 * @hw: pointer to the HW structure
269 * Determines the LAN function id by reading memory-mapped registers and swaps
270 * the port value if requested, and set MAC instance for devices.
272 void txgbe_set_lan_id_multi_port(struct txgbe_hw *hw)
274 struct txgbe_bus_info *bus = &hw->bus;
277 DEBUGFUNC("txgbe_set_lan_id_multi_port_pcie");
279 reg = rd32(hw, TXGBE_PORTSTAT);
280 bus->lan_id = TXGBE_PORTSTAT_ID(reg);
282 /* check for single port */
283 reg = rd32(hw, TXGBE_PWR);
284 if (TXGBE_PWR_LANID(reg) == TXGBE_PWR_LANID_SWAP)
287 bus->func = bus->lan_id;
291 * txgbe_stop_hw - Generic stop Tx/Rx units
292 * @hw: pointer to hardware structure
294 * Sets the adapter_stopped flag within txgbe_hw struct. Clears interrupts,
295 * disables transmit and receive units. The adapter_stopped flag is used by
296 * the shared code and drivers to determine if the adapter is in a stopped
297 * state and should not touch the hardware.
299 s32 txgbe_stop_hw(struct txgbe_hw *hw)
304 DEBUGFUNC("txgbe_stop_hw");
307 * Set the adapter_stopped flag so other driver functions stop touching
310 hw->adapter_stopped = true;
312 /* Disable the receive unit */
313 txgbe_disable_rx(hw);
315 /* Clear interrupt mask to stop interrupts from being generated */
316 wr32(hw, TXGBE_IENMISC, 0);
317 wr32(hw, TXGBE_IMS(0), TXGBE_IMS_MASK);
318 wr32(hw, TXGBE_IMS(1), TXGBE_IMS_MASK);
320 /* Clear any pending interrupts, flush previous writes */
321 wr32(hw, TXGBE_ICRMISC, TXGBE_ICRMISC_MASK);
322 wr32(hw, TXGBE_ICR(0), TXGBE_ICR_MASK);
323 wr32(hw, TXGBE_ICR(1), TXGBE_ICR_MASK);
325 /* Disable the transmit unit. Each queue must be disabled. */
326 for (i = 0; i < hw->mac.max_tx_queues; i++)
327 wr32(hw, TXGBE_TXCFG(i), TXGBE_TXCFG_FLUSH);
329 /* Disable the receive unit by stopping each queue */
330 for (i = 0; i < hw->mac.max_rx_queues; i++) {
331 reg_val = rd32(hw, TXGBE_RXCFG(i));
332 reg_val &= ~TXGBE_RXCFG_ENA;
333 wr32(hw, TXGBE_RXCFG(i), reg_val);
336 /* flush all queues disables */
344 * txgbe_validate_mac_addr - Validate MAC address
345 * @mac_addr: pointer to MAC address.
347 * Tests a MAC address to ensure it is a valid Individual Address.
349 s32 txgbe_validate_mac_addr(u8 *mac_addr)
353 DEBUGFUNC("txgbe_validate_mac_addr");
355 /* Make sure it is not a multicast address */
356 if (TXGBE_IS_MULTICAST(mac_addr)) {
357 status = TXGBE_ERR_INVALID_MAC_ADDR;
358 /* Not a broadcast address */
359 } else if (TXGBE_IS_BROADCAST(mac_addr)) {
360 status = TXGBE_ERR_INVALID_MAC_ADDR;
361 /* Reject the zero address */
362 } else if (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 &&
363 mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0) {
364 status = TXGBE_ERR_INVALID_MAC_ADDR;
370 * txgbe_set_rar - Set Rx address register
371 * @hw: pointer to hardware structure
372 * @index: Receive address register to write
373 * @addr: Address to put into receive address register
374 * @vmdq: VMDq "set" or "pool" index
375 * @enable_addr: set flag that address is active
377 * Puts an ethernet address into a receive address register.
379 s32 txgbe_set_rar(struct txgbe_hw *hw, u32 index, u8 *addr, u32 vmdq,
382 u32 rar_low, rar_high;
383 u32 rar_entries = hw->mac.num_rar_entries;
385 DEBUGFUNC("txgbe_set_rar");
387 /* Make sure we are using a valid rar index range */
388 if (index >= rar_entries) {
389 DEBUGOUT("RAR index %d is out of range.\n", index);
390 return TXGBE_ERR_INVALID_ARGUMENT;
393 /* setup VMDq pool selection before this RAR gets enabled */
394 hw->mac.set_vmdq(hw, index, vmdq);
397 * HW expects these in little endian so we reverse the byte
398 * order from network order (big endian) to little endian
400 rar_low = TXGBE_ETHADDRL_AD0(addr[5]) |
401 TXGBE_ETHADDRL_AD1(addr[4]) |
402 TXGBE_ETHADDRL_AD2(addr[3]) |
403 TXGBE_ETHADDRL_AD3(addr[2]);
405 * Some parts put the VMDq setting in the extra RAH bits,
406 * so save everything except the lower 16 bits that hold part
407 * of the address and the address valid bit.
409 rar_high = rd32(hw, TXGBE_ETHADDRH);
410 rar_high &= ~TXGBE_ETHADDRH_AD_MASK;
411 rar_high |= (TXGBE_ETHADDRH_AD4(addr[1]) |
412 TXGBE_ETHADDRH_AD5(addr[0]));
414 rar_high &= ~TXGBE_ETHADDRH_VLD;
415 if (enable_addr != 0)
416 rar_high |= TXGBE_ETHADDRH_VLD;
418 wr32(hw, TXGBE_ETHADDRIDX, index);
419 wr32(hw, TXGBE_ETHADDRL, rar_low);
420 wr32(hw, TXGBE_ETHADDRH, rar_high);
426 * txgbe_clear_rar - Remove Rx address register
427 * @hw: pointer to hardware structure
428 * @index: Receive address register to write
430 * Clears an ethernet address from a receive address register.
432 s32 txgbe_clear_rar(struct txgbe_hw *hw, u32 index)
435 u32 rar_entries = hw->mac.num_rar_entries;
437 DEBUGFUNC("txgbe_clear_rar");
439 /* Make sure we are using a valid rar index range */
440 if (index >= rar_entries) {
441 DEBUGOUT("RAR index %d is out of range.\n", index);
442 return TXGBE_ERR_INVALID_ARGUMENT;
446 * Some parts put the VMDq setting in the extra RAH bits,
447 * so save everything except the lower 16 bits that hold part
448 * of the address and the address valid bit.
450 wr32(hw, TXGBE_ETHADDRIDX, index);
451 rar_high = rd32(hw, TXGBE_ETHADDRH);
452 rar_high &= ~(TXGBE_ETHADDRH_AD_MASK | TXGBE_ETHADDRH_VLD);
454 wr32(hw, TXGBE_ETHADDRL, 0);
455 wr32(hw, TXGBE_ETHADDRH, rar_high);
457 /* clear VMDq pool/queue selection for this RAR */
458 hw->mac.clear_vmdq(hw, index, BIT_MASK32);
464 * txgbe_init_rx_addrs - Initializes receive address filters.
465 * @hw: pointer to hardware structure
467 * Places the MAC address in receive address register 0 and clears the rest
468 * of the receive address registers. Clears the multicast table. Assumes
469 * the receiver is in reset when the routine is called.
471 s32 txgbe_init_rx_addrs(struct txgbe_hw *hw)
475 u32 rar_entries = hw->mac.num_rar_entries;
477 DEBUGFUNC("txgbe_init_rx_addrs");
480 * If the current mac address is valid, assume it is a software override
481 * to the permanent address.
482 * Otherwise, use the permanent address from the eeprom.
484 if (txgbe_validate_mac_addr(hw->mac.addr) ==
485 TXGBE_ERR_INVALID_MAC_ADDR) {
486 /* Get the MAC address from the RAR0 for later reference */
487 hw->mac.get_mac_addr(hw, hw->mac.addr);
489 DEBUGOUT(" Keeping Current RAR0 Addr =%.2X %.2X %.2X ",
490 hw->mac.addr[0], hw->mac.addr[1],
492 DEBUGOUT("%.2X %.2X %.2X\n", hw->mac.addr[3],
493 hw->mac.addr[4], hw->mac.addr[5]);
495 /* Setup the receive address. */
496 DEBUGOUT("Overriding MAC Address in RAR[0]\n");
497 DEBUGOUT(" New MAC Addr =%.2X %.2X %.2X ",
498 hw->mac.addr[0], hw->mac.addr[1],
500 DEBUGOUT("%.2X %.2X %.2X\n", hw->mac.addr[3],
501 hw->mac.addr[4], hw->mac.addr[5]);
503 hw->mac.set_rar(hw, 0, hw->mac.addr, 0, true);
506 /* clear VMDq pool/queue selection for RAR 0 */
507 hw->mac.clear_vmdq(hw, 0, BIT_MASK32);
509 hw->addr_ctrl.overflow_promisc = 0;
511 hw->addr_ctrl.rar_used_count = 1;
513 /* Zero out the other receive addresses. */
514 DEBUGOUT("Clearing RAR[1-%d]\n", rar_entries - 1);
515 for (i = 1; i < rar_entries; i++) {
516 wr32(hw, TXGBE_ETHADDRIDX, i);
517 wr32(hw, TXGBE_ETHADDRL, 0);
518 wr32(hw, TXGBE_ETHADDRH, 0);
522 hw->addr_ctrl.mta_in_use = 0;
523 psrctl = rd32(hw, TXGBE_PSRCTL);
524 psrctl &= ~(TXGBE_PSRCTL_ADHF12_MASK | TXGBE_PSRCTL_MCHFENA);
525 psrctl |= TXGBE_PSRCTL_ADHF12(hw->mac.mc_filter_type);
526 wr32(hw, TXGBE_PSRCTL, psrctl);
528 DEBUGOUT(" Clearing MTA\n");
529 for (i = 0; i < hw->mac.mcft_size; i++)
530 wr32(hw, TXGBE_MCADDRTBL(i), 0);
532 txgbe_init_uta_tables(hw);
538 * txgbe_mta_vector - Determines bit-vector in multicast table to set
539 * @hw: pointer to hardware structure
540 * @mc_addr: the multicast address
542 * Extracts the 12 bits, from a multicast address, to determine which
543 * bit-vector to set in the multicast table. The hardware uses 12 bits, from
544 * incoming rx multicast addresses, to determine the bit-vector to check in
545 * the MTA. Which of the 4 combination, of 12-bits, the hardware uses is set
546 * by the MO field of the PSRCTRL. The MO field is set during initialization
549 static s32 txgbe_mta_vector(struct txgbe_hw *hw, u8 *mc_addr)
553 DEBUGFUNC("txgbe_mta_vector");
555 switch (hw->mac.mc_filter_type) {
556 case 0: /* use bits [47:36] of the address */
557 vector = ((mc_addr[4] >> 4) | (((u16)mc_addr[5]) << 4));
559 case 1: /* use bits [46:35] of the address */
560 vector = ((mc_addr[4] >> 3) | (((u16)mc_addr[5]) << 5));
562 case 2: /* use bits [45:34] of the address */
563 vector = ((mc_addr[4] >> 2) | (((u16)mc_addr[5]) << 6));
565 case 3: /* use bits [43:32] of the address */
566 vector = ((mc_addr[4]) | (((u16)mc_addr[5]) << 8));
568 default: /* Invalid mc_filter_type */
569 DEBUGOUT("MC filter type param set incorrectly\n");
574 /* vector can only be 12-bits or boundary will be exceeded */
580 * txgbe_set_mta - Set bit-vector in multicast table
581 * @hw: pointer to hardware structure
582 * @mc_addr: Multicast address
584 * Sets the bit-vector in the multicast table.
586 void txgbe_set_mta(struct txgbe_hw *hw, u8 *mc_addr)
592 DEBUGFUNC("txgbe_set_mta");
594 hw->addr_ctrl.mta_in_use++;
596 vector = txgbe_mta_vector(hw, mc_addr);
597 DEBUGOUT(" bit-vector = 0x%03X\n", vector);
600 * The MTA is a register array of 128 32-bit registers. It is treated
601 * like an array of 4096 bits. We want to set bit
602 * BitArray[vector_value]. So we figure out what register the bit is
603 * in, read it, OR in the new bit, then write back the new value. The
604 * register is determined by the upper 7 bits of the vector value and
605 * the bit within that register are determined by the lower 5 bits of
608 vector_reg = (vector >> 5) & 0x7F;
609 vector_bit = vector & 0x1F;
610 hw->mac.mta_shadow[vector_reg] |= (1 << vector_bit);
614 * txgbe_update_mc_addr_list - Updates MAC list of multicast addresses
615 * @hw: pointer to hardware structure
616 * @mc_addr_list: the list of new multicast addresses
617 * @mc_addr_count: number of addresses
618 * @next: iterator function to walk the multicast address list
619 * @clear: flag, when set clears the table beforehand
621 * When the clear flag is set, the given list replaces any existing list.
622 * Hashes the given addresses into the multicast table.
624 s32 txgbe_update_mc_addr_list(struct txgbe_hw *hw, u8 *mc_addr_list,
625 u32 mc_addr_count, txgbe_mc_addr_itr next,
631 DEBUGFUNC("txgbe_update_mc_addr_list");
634 * Set the new number of MC addresses that we are being requested to
637 hw->addr_ctrl.num_mc_addrs = mc_addr_count;
638 hw->addr_ctrl.mta_in_use = 0;
640 /* Clear mta_shadow */
642 DEBUGOUT(" Clearing MTA\n");
643 memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow));
646 /* Update mta_shadow */
647 for (i = 0; i < mc_addr_count; i++) {
648 DEBUGOUT(" Adding the multicast addresses:\n");
649 txgbe_set_mta(hw, next(hw, &mc_addr_list, &vmdq));
653 for (i = 0; i < hw->mac.mcft_size; i++)
654 wr32a(hw, TXGBE_MCADDRTBL(0), i,
655 hw->mac.mta_shadow[i]);
657 if (hw->addr_ctrl.mta_in_use > 0) {
658 u32 psrctl = rd32(hw, TXGBE_PSRCTL);
659 psrctl &= ~(TXGBE_PSRCTL_ADHF12_MASK | TXGBE_PSRCTL_MCHFENA);
660 psrctl |= TXGBE_PSRCTL_MCHFENA |
661 TXGBE_PSRCTL_ADHF12(hw->mac.mc_filter_type);
662 wr32(hw, TXGBE_PSRCTL, psrctl);
665 DEBUGOUT("txgbe update mc addr list complete\n");
670 * txgbe_disable_sec_rx_path - Stops the receive data path
671 * @hw: pointer to hardware structure
673 * Stops the receive data path and waits for the HW to internally empty
674 * the Rx security block
676 s32 txgbe_disable_sec_rx_path(struct txgbe_hw *hw)
678 #define TXGBE_MAX_SECRX_POLL 4000
683 DEBUGFUNC("txgbe_disable_sec_rx_path");
685 secrxreg = rd32(hw, TXGBE_SECRXCTL);
686 secrxreg |= TXGBE_SECRXCTL_XDSA;
687 wr32(hw, TXGBE_SECRXCTL, secrxreg);
688 for (i = 0; i < TXGBE_MAX_SECRX_POLL; i++) {
689 secrxreg = rd32(hw, TXGBE_SECRXSTAT);
690 if (!(secrxreg & TXGBE_SECRXSTAT_RDY))
691 /* Use interrupt-safe sleep just in case */
697 /* For informational purposes only */
698 if (i >= TXGBE_MAX_SECRX_POLL)
699 DEBUGOUT("Rx unit being enabled before security "
700 "path fully disabled. Continuing with init.\n");
706 * txgbe_enable_sec_rx_path - Enables the receive data path
707 * @hw: pointer to hardware structure
709 * Enables the receive data path.
711 s32 txgbe_enable_sec_rx_path(struct txgbe_hw *hw)
715 DEBUGFUNC("txgbe_enable_sec_rx_path");
717 secrxreg = rd32(hw, TXGBE_SECRXCTL);
718 secrxreg &= ~TXGBE_SECRXCTL_XDSA;
719 wr32(hw, TXGBE_SECRXCTL, secrxreg);
726 * txgbe_disable_sec_tx_path - Stops the transmit data path
727 * @hw: pointer to hardware structure
729 * Stops the transmit data path and waits for the HW to internally empty
730 * the Tx security block
732 int txgbe_disable_sec_tx_path(struct txgbe_hw *hw)
734 #define TXGBE_MAX_SECTX_POLL 40
739 sectxreg = rd32(hw, TXGBE_SECTXCTL);
740 sectxreg |= TXGBE_SECTXCTL_XDSA;
741 wr32(hw, TXGBE_SECTXCTL, sectxreg);
742 for (i = 0; i < TXGBE_MAX_SECTX_POLL; i++) {
743 sectxreg = rd32(hw, TXGBE_SECTXSTAT);
744 if (sectxreg & TXGBE_SECTXSTAT_RDY)
746 /* Use interrupt-safe sleep just in case */
750 /* For informational purposes only */
751 if (i >= TXGBE_MAX_SECTX_POLL)
752 PMD_DRV_LOG(DEBUG, "Tx unit being enabled before security "
753 "path fully disabled. Continuing with init.");
759 * txgbe_enable_sec_tx_path - Enables the transmit data path
760 * @hw: pointer to hardware structure
762 * Enables the transmit data path.
764 int txgbe_enable_sec_tx_path(struct txgbe_hw *hw)
768 sectxreg = rd32(hw, TXGBE_SECTXCTL);
769 sectxreg &= ~TXGBE_SECTXCTL_XDSA;
770 wr32(hw, TXGBE_SECTXCTL, sectxreg);
777 * txgbe_get_san_mac_addr_offset - Get SAN MAC address offset from the EEPROM
778 * @hw: pointer to hardware structure
779 * @san_mac_offset: SAN MAC address offset
781 * This function will read the EEPROM location for the SAN MAC address
782 * pointer, and returns the value at that location. This is used in both
783 * get and set mac_addr routines.
785 static s32 txgbe_get_san_mac_addr_offset(struct txgbe_hw *hw,
790 DEBUGFUNC("txgbe_get_san_mac_addr_offset");
793 * First read the EEPROM pointer to see if the MAC addresses are
796 err = hw->rom.readw_sw(hw, TXGBE_SAN_MAC_ADDR_PTR,
799 DEBUGOUT("eeprom at offset %d failed",
800 TXGBE_SAN_MAC_ADDR_PTR);
807 * txgbe_get_san_mac_addr - SAN MAC address retrieval from the EEPROM
808 * @hw: pointer to hardware structure
809 * @san_mac_addr: SAN MAC address
811 * Reads the SAN MAC address from the EEPROM, if it's available. This is
812 * per-port, so set_lan_id() must be called before reading the addresses.
813 * set_lan_id() is called by identify_sfp(), but this cannot be relied
814 * upon for non-SFP connections, so we must call it here.
816 s32 txgbe_get_san_mac_addr(struct txgbe_hw *hw, u8 *san_mac_addr)
818 u16 san_mac_data, san_mac_offset;
822 DEBUGFUNC("txgbe_get_san_mac_addr");
825 * First read the EEPROM pointer to see if the MAC addresses are
826 * available. If they're not, no point in calling set_lan_id() here.
828 err = txgbe_get_san_mac_addr_offset(hw, &san_mac_offset);
829 if (err || san_mac_offset == 0 || san_mac_offset == 0xFFFF)
830 goto san_mac_addr_out;
832 /* apply the port offset to the address offset */
833 (hw->bus.func) ? (san_mac_offset += TXGBE_SAN_MAC_ADDR_PORT1_OFFSET) :
834 (san_mac_offset += TXGBE_SAN_MAC_ADDR_PORT0_OFFSET);
835 for (i = 0; i < 3; i++) {
836 err = hw->rom.read16(hw, san_mac_offset,
839 DEBUGOUT("eeprom read at offset %d failed",
841 goto san_mac_addr_out;
843 san_mac_addr[i * 2] = (u8)(san_mac_data);
844 san_mac_addr[i * 2 + 1] = (u8)(san_mac_data >> 8);
851 * No addresses available in this EEPROM. It's not an
852 * error though, so just wipe the local address and return.
854 for (i = 0; i < 6; i++)
855 san_mac_addr[i] = 0xFF;
860 * txgbe_set_san_mac_addr - Write the SAN MAC address to the EEPROM
861 * @hw: pointer to hardware structure
862 * @san_mac_addr: SAN MAC address
864 * Write a SAN MAC address to the EEPROM.
866 s32 txgbe_set_san_mac_addr(struct txgbe_hw *hw, u8 *san_mac_addr)
869 u16 san_mac_data, san_mac_offset;
872 DEBUGFUNC("txgbe_set_san_mac_addr");
874 /* Look for SAN mac address pointer. If not defined, return */
875 err = txgbe_get_san_mac_addr_offset(hw, &san_mac_offset);
876 if (err || san_mac_offset == 0 || san_mac_offset == 0xFFFF)
877 return TXGBE_ERR_NO_SAN_ADDR_PTR;
879 /* Apply the port offset to the address offset */
880 (hw->bus.func) ? (san_mac_offset += TXGBE_SAN_MAC_ADDR_PORT1_OFFSET) :
881 (san_mac_offset += TXGBE_SAN_MAC_ADDR_PORT0_OFFSET);
883 for (i = 0; i < 3; i++) {
884 san_mac_data = (u16)((u16)(san_mac_addr[i * 2 + 1]) << 8);
885 san_mac_data |= (u16)(san_mac_addr[i * 2]);
886 hw->rom.write16(hw, san_mac_offset, san_mac_data);
894 * txgbe_init_uta_tables - Initialize the Unicast Table Array
895 * @hw: pointer to hardware structure
897 s32 txgbe_init_uta_tables(struct txgbe_hw *hw)
901 DEBUGFUNC("txgbe_init_uta_tables");
902 DEBUGOUT(" Clearing UTA\n");
904 for (i = 0; i < 128; i++)
905 wr32(hw, TXGBE_UCADDRTBL(i), 0);
911 * txgbe_need_crosstalk_fix - Determine if we need to do cross talk fix
912 * @hw: pointer to hardware structure
914 * Contains the logic to identify if we need to verify link for the
917 static bool txgbe_need_crosstalk_fix(struct txgbe_hw *hw)
919 /* Does FW say we need the fix */
920 if (!hw->need_crosstalk_fix)
923 /* Only consider SFP+ PHYs i.e. media type fiber */
924 switch (hw->phy.media_type) {
925 case txgbe_media_type_fiber:
926 case txgbe_media_type_fiber_qsfp:
936 * txgbe_check_mac_link - Determine link and speed status
937 * @hw: pointer to hardware structure
938 * @speed: pointer to link speed
939 * @link_up: true when link is up
940 * @link_up_wait_to_complete: bool used to wait for link up or not
942 * Reads the links register to determine if link is up and the current speed
944 s32 txgbe_check_mac_link(struct txgbe_hw *hw, u32 *speed,
945 bool *link_up, bool link_up_wait_to_complete)
947 u32 links_reg, links_orig;
950 DEBUGFUNC("txgbe_check_mac_link");
952 /* If Crosstalk fix enabled do the sanity check of making sure
953 * the SFP+ cage is full.
955 if (txgbe_need_crosstalk_fix(hw)) {
958 switch (hw->mac.type) {
959 case txgbe_mac_raptor:
960 sfp_cage_full = !rd32m(hw, TXGBE_GPIODATA,
964 /* sanity check - No SFP+ devices here */
965 sfp_cage_full = false;
969 if (!sfp_cage_full) {
971 *speed = TXGBE_LINK_SPEED_UNKNOWN;
976 /* clear the old state */
977 links_orig = rd32(hw, TXGBE_PORTSTAT);
979 links_reg = rd32(hw, TXGBE_PORTSTAT);
981 if (links_orig != links_reg) {
982 DEBUGOUT("LINKS changed from %08X to %08X\n",
983 links_orig, links_reg);
986 if (link_up_wait_to_complete) {
987 for (i = 0; i < hw->mac.max_link_up_time; i++) {
988 if (!(links_reg & TXGBE_PORTSTAT_UP)) {
995 links_reg = rd32(hw, TXGBE_PORTSTAT);
998 if (links_reg & TXGBE_PORTSTAT_UP)
1004 switch (links_reg & TXGBE_PORTSTAT_BW_MASK) {
1005 case TXGBE_PORTSTAT_BW_10G:
1006 *speed = TXGBE_LINK_SPEED_10GB_FULL;
1008 case TXGBE_PORTSTAT_BW_1G:
1009 *speed = TXGBE_LINK_SPEED_1GB_FULL;
1011 case TXGBE_PORTSTAT_BW_100M:
1012 *speed = TXGBE_LINK_SPEED_100M_FULL;
1015 *speed = TXGBE_LINK_SPEED_UNKNOWN;
1022 * txgbe_get_device_caps - Get additional device capabilities
1023 * @hw: pointer to hardware structure
1024 * @device_caps: the EEPROM word with the extra device capabilities
1026 * This function will read the EEPROM location for the device capabilities,
1027 * and return the word through device_caps.
1029 s32 txgbe_get_device_caps(struct txgbe_hw *hw, u16 *device_caps)
1031 DEBUGFUNC("txgbe_get_device_caps");
1033 hw->rom.readw_sw(hw, TXGBE_DEVICE_CAPS, device_caps);
1039 * txgbe_clear_tx_pending - Clear pending TX work from the PCIe fifo
1040 * @hw: pointer to the hardware structure
1042 * The MACs can experience issues if TX work is still pending
1043 * when a reset occurs. This function prevents this by flushing the PCIe
1044 * buffers on the system.
1046 void txgbe_clear_tx_pending(struct txgbe_hw *hw)
1048 u32 hlreg0, i, poll;
1051 * If double reset is not requested then all transactions should
1052 * already be clear and as such there is no work to do
1054 if (!(hw->mac.flags & TXGBE_FLAGS_DOUBLE_RESET_REQUIRED))
1057 hlreg0 = rd32(hw, TXGBE_PSRCTL);
1058 wr32(hw, TXGBE_PSRCTL, hlreg0 | TXGBE_PSRCTL_LBENA);
1060 /* Wait for a last completion before clearing buffers */
1065 * Before proceeding, make sure that the PCIe block does not have
1066 * transactions pending.
1068 poll = (800 * 11) / 10;
1069 for (i = 0; i < poll; i++)
1072 /* Flush all writes and allow 20usec for all transactions to clear */
1076 /* restore previous register values */
1077 wr32(hw, TXGBE_PSRCTL, hlreg0);
1081 * txgbe_get_thermal_sensor_data - Gathers thermal sensor data
1082 * @hw: pointer to hardware structure
1084 * Returns the thermal sensor data structure
1086 s32 txgbe_get_thermal_sensor_data(struct txgbe_hw *hw)
1088 struct txgbe_thermal_sensor_data *data = &hw->mac.thermal_sensor_data;
1092 DEBUGFUNC("txgbe_get_thermal_sensor_data");
1094 /* Only support thermal sensors attached to physical port 0 */
1095 if (hw->bus.lan_id != 0)
1096 return TXGBE_NOT_IMPLEMENTED;
1098 ts_stat = rd32(hw, TXGBE_TSSTAT);
1099 tsv = (s64)TXGBE_TSSTAT_DATA(ts_stat);
1100 tsv = tsv > 1200 ? tsv : 1200;
1101 tsv = -(48380 << 8) / 1000
1102 + tsv * (31020 << 8) / 100000
1103 - tsv * tsv * (18201 << 8) / 100000000
1104 + tsv * tsv * tsv * (81542 << 8) / 1000000000000
1105 - tsv * tsv * tsv * tsv * (16743 << 8) / 1000000000000000;
1108 data->sensor[0].temp = (s16)tsv;
1114 * txgbe_init_thermal_sensor_thresh - Inits thermal sensor thresholds
1115 * @hw: pointer to hardware structure
1117 * Inits the thermal sensor thresholds according to the NVM map
1118 * and save off the threshold and location values into mac.thermal_sensor_data
1120 s32 txgbe_init_thermal_sensor_thresh(struct txgbe_hw *hw)
1122 struct txgbe_thermal_sensor_data *data = &hw->mac.thermal_sensor_data;
1124 DEBUGFUNC("txgbe_init_thermal_sensor_thresh");
1126 memset(data, 0, sizeof(struct txgbe_thermal_sensor_data));
1128 if (hw->bus.lan_id != 0)
1129 return TXGBE_NOT_IMPLEMENTED;
1131 wr32(hw, TXGBE_TSCTRL, TXGBE_TSCTRL_EVALMD);
1132 wr32(hw, TXGBE_TSINTR,
1133 TXGBE_TSINTR_AEN | TXGBE_TSINTR_DEN);
1134 wr32(hw, TXGBE_TSEN, TXGBE_TSEN_ENA);
1137 data->sensor[0].alarm_thresh = 100;
1138 wr32(hw, TXGBE_TSATHRE, 677);
1139 data->sensor[0].dalarm_thresh = 90;
1140 wr32(hw, TXGBE_TSDTHRE, 614);
1145 void txgbe_disable_rx(struct txgbe_hw *hw)
1149 pfdtxgswc = rd32(hw, TXGBE_PSRCTL);
1150 if (pfdtxgswc & TXGBE_PSRCTL_LBENA) {
1151 pfdtxgswc &= ~TXGBE_PSRCTL_LBENA;
1152 wr32(hw, TXGBE_PSRCTL, pfdtxgswc);
1153 hw->mac.set_lben = true;
1155 hw->mac.set_lben = false;
1158 wr32m(hw, TXGBE_PBRXCTL, TXGBE_PBRXCTL_ENA, 0);
1159 wr32m(hw, TXGBE_MACRXCFG, TXGBE_MACRXCFG_ENA, 0);
1162 void txgbe_enable_rx(struct txgbe_hw *hw)
1166 wr32m(hw, TXGBE_MACRXCFG, TXGBE_MACRXCFG_ENA, TXGBE_MACRXCFG_ENA);
1167 wr32m(hw, TXGBE_PBRXCTL, TXGBE_PBRXCTL_ENA, TXGBE_PBRXCTL_ENA);
1169 if (hw->mac.set_lben) {
1170 pfdtxgswc = rd32(hw, TXGBE_PSRCTL);
1171 pfdtxgswc |= TXGBE_PSRCTL_LBENA;
1172 wr32(hw, TXGBE_PSRCTL, pfdtxgswc);
1173 hw->mac.set_lben = false;
1178 * txgbe_setup_mac_link_multispeed_fiber - Set MAC link speed
1179 * @hw: pointer to hardware structure
1180 * @speed: new link speed
1181 * @autoneg_wait_to_complete: true when waiting for completion is needed
1183 * Set the link speed in the MAC and/or PHY register and restarts link.
1185 s32 txgbe_setup_mac_link_multispeed_fiber(struct txgbe_hw *hw,
1187 bool autoneg_wait_to_complete)
1189 u32 link_speed = TXGBE_LINK_SPEED_UNKNOWN;
1190 u32 highest_link_speed = TXGBE_LINK_SPEED_UNKNOWN;
1194 bool autoneg, link_up = false;
1196 DEBUGFUNC("txgbe_setup_mac_link_multispeed_fiber");
1198 /* Mask off requested but non-supported speeds */
1199 status = hw->mac.get_link_capabilities(hw, &link_speed, &autoneg);
1203 speed &= link_speed;
1205 /* Try each speed one by one, highest priority first. We do this in
1206 * software because 10Gb fiber doesn't support speed autonegotiation.
1208 if (speed & TXGBE_LINK_SPEED_10GB_FULL) {
1210 highest_link_speed = TXGBE_LINK_SPEED_10GB_FULL;
1212 /* Set the module link speed */
1213 switch (hw->phy.media_type) {
1214 case txgbe_media_type_fiber:
1215 hw->mac.set_rate_select_speed(hw,
1216 TXGBE_LINK_SPEED_10GB_FULL);
1218 case txgbe_media_type_fiber_qsfp:
1219 /* QSFP module automatically detects MAC link speed */
1222 DEBUGOUT("Unexpected media type.\n");
1226 /* Allow module to change analog characteristics (1G->10G) */
1229 status = hw->mac.setup_mac_link(hw,
1230 TXGBE_LINK_SPEED_10GB_FULL,
1231 autoneg_wait_to_complete);
1235 /* Flap the Tx laser if it has not already been done */
1236 hw->mac.flap_tx_laser(hw);
1238 /* Wait for the controller to acquire link. Per IEEE 802.3ap,
1239 * Section 73.10.2, we may have to wait up to 500ms if KR is
1240 * attempted. uses the same timing for 10g SFI.
1242 for (i = 0; i < 5; i++) {
1243 /* Wait for the link partner to also set speed */
1246 /* If we have link, just jump out */
1247 status = hw->mac.check_link(hw, &link_speed,
1257 if (speed & TXGBE_LINK_SPEED_1GB_FULL) {
1259 if (highest_link_speed == TXGBE_LINK_SPEED_UNKNOWN)
1260 highest_link_speed = TXGBE_LINK_SPEED_1GB_FULL;
1262 /* Set the module link speed */
1263 switch (hw->phy.media_type) {
1264 case txgbe_media_type_fiber:
1265 hw->mac.set_rate_select_speed(hw,
1266 TXGBE_LINK_SPEED_1GB_FULL);
1268 case txgbe_media_type_fiber_qsfp:
1269 /* QSFP module automatically detects link speed */
1272 DEBUGOUT("Unexpected media type.\n");
1276 /* Allow module to change analog characteristics (10G->1G) */
1279 status = hw->mac.setup_mac_link(hw,
1280 TXGBE_LINK_SPEED_1GB_FULL,
1281 autoneg_wait_to_complete);
1285 /* Flap the Tx laser if it has not already been done */
1286 hw->mac.flap_tx_laser(hw);
1288 /* Wait for the link partner to also set speed */
1291 /* If we have link, just jump out */
1292 status = hw->mac.check_link(hw, &link_speed, &link_up, false);
1300 /* We didn't get link. Configure back to the highest speed we tried,
1301 * (if there was more than one). We call ourselves back with just the
1302 * single highest speed that the user requested.
1305 status = txgbe_setup_mac_link_multispeed_fiber(hw,
1307 autoneg_wait_to_complete);
1310 /* Set autoneg_advertised value based on input link speed */
1311 hw->phy.autoneg_advertised = 0;
1313 if (speed & TXGBE_LINK_SPEED_10GB_FULL)
1314 hw->phy.autoneg_advertised |= TXGBE_LINK_SPEED_10GB_FULL;
1316 if (speed & TXGBE_LINK_SPEED_1GB_FULL)
1317 hw->phy.autoneg_advertised |= TXGBE_LINK_SPEED_1GB_FULL;
1323 * txgbe_init_shared_code - Initialize the shared code
1324 * @hw: pointer to hardware structure
1326 * This will assign function pointers and assign the MAC type and PHY code.
1327 * Does not touch the hardware. This function must be called prior to any
1328 * other function in the shared code. The txgbe_hw structure should be
1329 * memset to 0 prior to calling this function. The following fields in
1330 * hw structure should be filled in prior to calling this function:
1331 * hw_addr, back, device_id, vendor_id, subsystem_device_id,
1332 * subsystem_vendor_id, and revision_id
1334 s32 txgbe_init_shared_code(struct txgbe_hw *hw)
1338 DEBUGFUNC("txgbe_init_shared_code");
1343 txgbe_set_mac_type(hw);
1345 txgbe_init_ops_dummy(hw);
1346 switch (hw->mac.type) {
1347 case txgbe_mac_raptor:
1348 status = txgbe_init_ops_pf(hw);
1351 status = TXGBE_ERR_DEVICE_NOT_SUPPORTED;
1354 hw->mac.max_link_up_time = TXGBE_LINK_UP_TIME;
1356 hw->bus.set_lan_id(hw);
1362 * txgbe_set_mac_type - Sets MAC type
1363 * @hw: pointer to the HW structure
1365 * This function sets the mac type of the adapter based on the
1366 * vendor ID and device ID stored in the hw structure.
1368 s32 txgbe_set_mac_type(struct txgbe_hw *hw)
1372 DEBUGFUNC("txgbe_set_mac_type");
1374 if (hw->vendor_id != PCI_VENDOR_ID_WANGXUN) {
1375 DEBUGOUT("Unsupported vendor id: %x", hw->vendor_id);
1376 return TXGBE_ERR_DEVICE_NOT_SUPPORTED;
1379 switch (hw->device_id) {
1380 case TXGBE_DEV_ID_RAPTOR_KR_KX_KX4:
1381 hw->phy.media_type = txgbe_media_type_backplane;
1382 hw->mac.type = txgbe_mac_raptor;
1384 case TXGBE_DEV_ID_RAPTOR_XAUI:
1385 case TXGBE_DEV_ID_RAPTOR_SGMII:
1386 hw->phy.media_type = txgbe_media_type_copper;
1387 hw->mac.type = txgbe_mac_raptor;
1389 case TXGBE_DEV_ID_RAPTOR_SFP:
1390 case TXGBE_DEV_ID_WX1820_SFP:
1391 hw->phy.media_type = txgbe_media_type_fiber;
1392 hw->mac.type = txgbe_mac_raptor;
1394 case TXGBE_DEV_ID_RAPTOR_QSFP:
1395 hw->phy.media_type = txgbe_media_type_fiber_qsfp;
1396 hw->mac.type = txgbe_mac_raptor;
1398 case TXGBE_DEV_ID_RAPTOR_VF:
1399 case TXGBE_DEV_ID_RAPTOR_VF_HV:
1400 hw->phy.media_type = txgbe_media_type_virtual;
1401 hw->mac.type = txgbe_mac_raptor_vf;
1404 err = TXGBE_ERR_DEVICE_NOT_SUPPORTED;
1405 DEBUGOUT("Unsupported device id: %x", hw->device_id);
1409 DEBUGOUT("found mac: %d media: %d, returns: %d\n",
1410 hw->mac.type, hw->phy.media_type, err);
1414 void txgbe_init_mac_link_ops(struct txgbe_hw *hw)
1416 struct txgbe_mac_info *mac = &hw->mac;
1418 DEBUGFUNC("txgbe_init_mac_link_ops");
1421 * enable the laser control functions for SFP+ fiber
1422 * and MNG not enabled
1424 if (hw->phy.media_type == txgbe_media_type_fiber &&
1425 !txgbe_mng_enabled(hw)) {
1426 mac->disable_tx_laser =
1427 txgbe_disable_tx_laser_multispeed_fiber;
1428 mac->enable_tx_laser =
1429 txgbe_enable_tx_laser_multispeed_fiber;
1430 mac->flap_tx_laser =
1431 txgbe_flap_tx_laser_multispeed_fiber;
1434 if ((hw->phy.media_type == txgbe_media_type_fiber ||
1435 hw->phy.media_type == txgbe_media_type_fiber_qsfp) &&
1436 hw->phy.multispeed_fiber) {
1437 /* Set up dual speed SFP+ support */
1438 mac->setup_link = txgbe_setup_mac_link_multispeed_fiber;
1439 mac->setup_mac_link = txgbe_setup_mac_link;
1440 mac->set_rate_select_speed = txgbe_set_hard_rate_select_speed;
1441 } else if ((hw->phy.media_type == txgbe_media_type_backplane) &&
1442 (hw->phy.smart_speed == txgbe_smart_speed_auto ||
1443 hw->phy.smart_speed == txgbe_smart_speed_on) &&
1444 !txgbe_verify_lesm_fw_enabled_raptor(hw)) {
1445 mac->setup_link = txgbe_setup_mac_link_smartspeed;
1447 mac->setup_link = txgbe_setup_mac_link;
1452 * txgbe_init_phy_raptor - PHY/SFP specific init
1453 * @hw: pointer to hardware structure
1455 * Initialize any function pointers that were not able to be
1456 * set during init_shared_code because the PHY/SFP type was
1457 * not known. Perform the SFP init if necessary.
1460 s32 txgbe_init_phy_raptor(struct txgbe_hw *hw)
1462 struct txgbe_mac_info *mac = &hw->mac;
1463 struct txgbe_phy_info *phy = &hw->phy;
1466 DEBUGFUNC("txgbe_init_phy_raptor");
1468 if (hw->device_id == TXGBE_DEV_ID_RAPTOR_QSFP) {
1469 /* Store flag indicating I2C bus access control unit. */
1470 hw->phy.qsfp_shared_i2c_bus = TRUE;
1472 /* Initialize access to QSFP+ I2C bus */
1476 /* Identify the PHY or SFP module */
1477 err = phy->identify(hw);
1478 if (err == TXGBE_ERR_SFP_NOT_SUPPORTED)
1479 goto init_phy_ops_out;
1481 /* Setup function pointers based on detected SFP module and speeds */
1482 txgbe_init_mac_link_ops(hw);
1484 /* If copper media, overwrite with copper function pointers */
1485 if (phy->media_type == txgbe_media_type_copper) {
1486 mac->setup_link = txgbe_setup_copper_link_raptor;
1487 mac->get_link_capabilities =
1488 txgbe_get_copper_link_capabilities;
1491 /* Set necessary function pointers based on PHY type */
1492 switch (hw->phy.type) {
1494 phy->setup_link = txgbe_setup_phy_link_tnx;
1495 phy->check_link = txgbe_check_phy_link_tnx;
1505 s32 txgbe_setup_sfp_modules(struct txgbe_hw *hw)
1509 DEBUGFUNC("txgbe_setup_sfp_modules");
1511 if (hw->phy.sfp_type == txgbe_sfp_type_unknown)
1514 txgbe_init_mac_link_ops(hw);
1516 /* PHY config will finish before releasing the semaphore */
1517 err = hw->mac.acquire_swfw_sync(hw, TXGBE_MNGSEM_SWPHY);
1519 return TXGBE_ERR_SWFW_SYNC;
1521 /* Release the semaphore */
1522 hw->mac.release_swfw_sync(hw, TXGBE_MNGSEM_SWPHY);
1524 /* Delay obtaining semaphore again to allow FW access
1525 * prot_autoc_write uses the semaphore too.
1527 msec_delay(hw->rom.semaphore_delay);
1530 DEBUGOUT("sfp module setup not complete\n");
1531 return TXGBE_ERR_SFP_SETUP_NOT_COMPLETE;
1538 * txgbe_init_ops_pf - Inits func ptrs and MAC type
1539 * @hw: pointer to hardware structure
1541 * Initialize the function pointers and assign the MAC type.
1542 * Does not touch the hardware.
1544 s32 txgbe_init_ops_pf(struct txgbe_hw *hw)
1546 struct txgbe_bus_info *bus = &hw->bus;
1547 struct txgbe_mac_info *mac = &hw->mac;
1548 struct txgbe_phy_info *phy = &hw->phy;
1549 struct txgbe_rom_info *rom = &hw->rom;
1551 DEBUGFUNC("txgbe_init_ops_pf");
1554 bus->set_lan_id = txgbe_set_lan_id_multi_port;
1557 phy->get_media_type = txgbe_get_media_type_raptor;
1558 phy->identify = txgbe_identify_phy;
1559 phy->init = txgbe_init_phy_raptor;
1560 phy->read_reg = txgbe_read_phy_reg;
1561 phy->write_reg = txgbe_write_phy_reg;
1562 phy->read_reg_mdi = txgbe_read_phy_reg_mdi;
1563 phy->write_reg_mdi = txgbe_write_phy_reg_mdi;
1564 phy->setup_link = txgbe_setup_phy_link;
1565 phy->setup_link_speed = txgbe_setup_phy_link_speed;
1566 phy->read_i2c_byte = txgbe_read_i2c_byte;
1567 phy->write_i2c_byte = txgbe_write_i2c_byte;
1568 phy->read_i2c_eeprom = txgbe_read_i2c_eeprom;
1569 phy->write_i2c_eeprom = txgbe_write_i2c_eeprom;
1570 phy->reset = txgbe_reset_phy;
1573 mac->init_hw = txgbe_init_hw;
1574 mac->start_hw = txgbe_start_hw_raptor;
1575 mac->clear_hw_cntrs = txgbe_clear_hw_cntrs;
1576 mac->enable_rx_dma = txgbe_enable_rx_dma_raptor;
1577 mac->get_mac_addr = txgbe_get_mac_addr;
1578 mac->stop_hw = txgbe_stop_hw;
1579 mac->reset_hw = txgbe_reset_hw;
1581 mac->disable_sec_rx_path = txgbe_disable_sec_rx_path;
1582 mac->enable_sec_rx_path = txgbe_enable_sec_rx_path;
1583 mac->disable_sec_tx_path = txgbe_disable_sec_tx_path;
1584 mac->enable_sec_tx_path = txgbe_enable_sec_tx_path;
1585 mac->get_san_mac_addr = txgbe_get_san_mac_addr;
1586 mac->set_san_mac_addr = txgbe_set_san_mac_addr;
1587 mac->get_device_caps = txgbe_get_device_caps;
1588 mac->autoc_read = txgbe_autoc_read;
1589 mac->autoc_write = txgbe_autoc_write;
1591 mac->set_rar = txgbe_set_rar;
1592 mac->clear_rar = txgbe_clear_rar;
1593 mac->init_rx_addrs = txgbe_init_rx_addrs;
1594 mac->enable_rx = txgbe_enable_rx;
1595 mac->disable_rx = txgbe_disable_rx;
1596 mac->init_uta_tables = txgbe_init_uta_tables;
1597 mac->setup_sfp = txgbe_setup_sfp_modules;
1599 mac->get_link_capabilities = txgbe_get_link_capabilities_raptor;
1600 mac->check_link = txgbe_check_mac_link;
1602 /* Manageability interface */
1603 mac->get_thermal_sensor_data = txgbe_get_thermal_sensor_data;
1604 mac->init_thermal_sensor_thresh = txgbe_init_thermal_sensor_thresh;
1607 rom->init_params = txgbe_init_eeprom_params;
1608 rom->read16 = txgbe_ee_read16;
1609 rom->readw_buffer = txgbe_ee_readw_buffer;
1610 rom->readw_sw = txgbe_ee_readw_sw;
1611 rom->read32 = txgbe_ee_read32;
1612 rom->write16 = txgbe_ee_write16;
1613 rom->writew_buffer = txgbe_ee_writew_buffer;
1614 rom->writew_sw = txgbe_ee_writew_sw;
1615 rom->write32 = txgbe_ee_write32;
1616 rom->validate_checksum = txgbe_validate_eeprom_checksum;
1617 rom->update_checksum = txgbe_update_eeprom_checksum;
1618 rom->calc_checksum = txgbe_calc_eeprom_checksum;
1620 mac->mcft_size = TXGBE_RAPTOR_MC_TBL_SIZE;
1621 mac->num_rar_entries = TXGBE_RAPTOR_RAR_ENTRIES;
1622 mac->max_rx_queues = TXGBE_RAPTOR_MAX_RX_QUEUES;
1623 mac->max_tx_queues = TXGBE_RAPTOR_MAX_TX_QUEUES;
1629 * txgbe_get_link_capabilities_raptor - Determines link capabilities
1630 * @hw: pointer to hardware structure
1631 * @speed: pointer to link speed
1632 * @autoneg: true when autoneg or autotry is enabled
1634 * Determines the link capabilities by reading the AUTOC register.
1636 s32 txgbe_get_link_capabilities_raptor(struct txgbe_hw *hw,
1643 DEBUGFUNC("txgbe_get_link_capabilities_raptor");
1645 /* Check if 1G SFP module. */
1646 if (hw->phy.sfp_type == txgbe_sfp_type_1g_cu_core0 ||
1647 hw->phy.sfp_type == txgbe_sfp_type_1g_cu_core1 ||
1648 hw->phy.sfp_type == txgbe_sfp_type_1g_lx_core0 ||
1649 hw->phy.sfp_type == txgbe_sfp_type_1g_lx_core1 ||
1650 hw->phy.sfp_type == txgbe_sfp_type_1g_sx_core0 ||
1651 hw->phy.sfp_type == txgbe_sfp_type_1g_sx_core1) {
1652 *speed = TXGBE_LINK_SPEED_1GB_FULL;
1658 * Determine link capabilities based on the stored value of AUTOC,
1659 * which represents EEPROM defaults. If AUTOC value has not
1660 * been stored, use the current register values.
1662 if (hw->mac.orig_link_settings_stored)
1663 autoc = hw->mac.orig_autoc;
1665 autoc = hw->mac.autoc_read(hw);
1667 switch (autoc & TXGBE_AUTOC_LMS_MASK) {
1668 case TXGBE_AUTOC_LMS_1G_LINK_NO_AN:
1669 *speed = TXGBE_LINK_SPEED_1GB_FULL;
1673 case TXGBE_AUTOC_LMS_10G_LINK_NO_AN:
1674 *speed = TXGBE_LINK_SPEED_10GB_FULL;
1678 case TXGBE_AUTOC_LMS_1G_AN:
1679 *speed = TXGBE_LINK_SPEED_1GB_FULL;
1683 case TXGBE_AUTOC_LMS_10G:
1684 *speed = TXGBE_LINK_SPEED_10GB_FULL;
1688 case TXGBE_AUTOC_LMS_KX4_KX_KR:
1689 case TXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN:
1690 *speed = TXGBE_LINK_SPEED_UNKNOWN;
1691 if (autoc & TXGBE_AUTOC_KR_SUPP)
1692 *speed |= TXGBE_LINK_SPEED_10GB_FULL;
1693 if (autoc & TXGBE_AUTOC_KX4_SUPP)
1694 *speed |= TXGBE_LINK_SPEED_10GB_FULL;
1695 if (autoc & TXGBE_AUTOC_KX_SUPP)
1696 *speed |= TXGBE_LINK_SPEED_1GB_FULL;
1700 case TXGBE_AUTOC_LMS_KX4_KX_KR_SGMII:
1701 *speed = TXGBE_LINK_SPEED_100M_FULL;
1702 if (autoc & TXGBE_AUTOC_KR_SUPP)
1703 *speed |= TXGBE_LINK_SPEED_10GB_FULL;
1704 if (autoc & TXGBE_AUTOC_KX4_SUPP)
1705 *speed |= TXGBE_LINK_SPEED_10GB_FULL;
1706 if (autoc & TXGBE_AUTOC_KX_SUPP)
1707 *speed |= TXGBE_LINK_SPEED_1GB_FULL;
1711 case TXGBE_AUTOC_LMS_SGMII_1G_100M:
1712 *speed = TXGBE_LINK_SPEED_1GB_FULL |
1713 TXGBE_LINK_SPEED_100M_FULL |
1714 TXGBE_LINK_SPEED_10M_FULL;
1719 return TXGBE_ERR_LINK_SETUP;
1722 if (hw->phy.multispeed_fiber) {
1723 *speed |= TXGBE_LINK_SPEED_10GB_FULL |
1724 TXGBE_LINK_SPEED_1GB_FULL;
1726 /* QSFP must not enable full auto-negotiation
1727 * Limited autoneg is enabled at 1G
1729 if (hw->phy.media_type == txgbe_media_type_fiber_qsfp)
1739 * txgbe_get_media_type_raptor - Get media type
1740 * @hw: pointer to hardware structure
1742 * Returns the media type (fiber, copper, backplane)
1744 u32 txgbe_get_media_type_raptor(struct txgbe_hw *hw)
1748 DEBUGFUNC("txgbe_get_media_type_raptor");
1750 /* Detect if there is a copper PHY attached. */
1751 switch (hw->phy.type) {
1752 case txgbe_phy_cu_unknown:
1754 media_type = txgbe_media_type_copper;
1760 switch (hw->device_id) {
1761 case TXGBE_DEV_ID_RAPTOR_KR_KX_KX4:
1762 /* Default device ID is mezzanine card KX/KX4 */
1763 media_type = txgbe_media_type_backplane;
1765 case TXGBE_DEV_ID_RAPTOR_SFP:
1766 case TXGBE_DEV_ID_WX1820_SFP:
1767 media_type = txgbe_media_type_fiber;
1769 case TXGBE_DEV_ID_RAPTOR_QSFP:
1770 media_type = txgbe_media_type_fiber_qsfp;
1772 case TXGBE_DEV_ID_RAPTOR_XAUI:
1773 case TXGBE_DEV_ID_RAPTOR_SGMII:
1774 media_type = txgbe_media_type_copper;
1777 media_type = txgbe_media_type_unknown;
1785 * txgbe_start_mac_link_raptor - Setup MAC link settings
1786 * @hw: pointer to hardware structure
1787 * @autoneg_wait_to_complete: true when waiting for completion is needed
1789 * Configures link settings based on values in the txgbe_hw struct.
1790 * Restarts the link. Performs autonegotiation if needed.
1792 s32 txgbe_start_mac_link_raptor(struct txgbe_hw *hw,
1793 bool autoneg_wait_to_complete)
1796 bool got_lock = false;
1798 DEBUGFUNC("txgbe_start_mac_link_raptor");
1800 UNREFERENCED_PARAMETER(autoneg_wait_to_complete);
1802 /* reset_pipeline requires us to hold this lock as it writes to
1805 if (txgbe_verify_lesm_fw_enabled_raptor(hw)) {
1806 status = hw->mac.acquire_swfw_sync(hw, TXGBE_MNGSEM_SWPHY);
1814 txgbe_reset_pipeline_raptor(hw);
1817 hw->mac.release_swfw_sync(hw, TXGBE_MNGSEM_SWPHY);
1819 /* Add delay to filter out noises during initial link setup */
1827 * txgbe_disable_tx_laser_multispeed_fiber - Disable Tx laser
1828 * @hw: pointer to hardware structure
1830 * The base drivers may require better control over SFP+ module
1831 * PHY states. This includes selectively shutting down the Tx
1832 * laser on the PHY, effectively halting physical link.
1834 void txgbe_disable_tx_laser_multispeed_fiber(struct txgbe_hw *hw)
1836 u32 esdp_reg = rd32(hw, TXGBE_GPIODATA);
1838 /* Blocked by MNG FW so bail */
1839 if (txgbe_check_reset_blocked(hw))
1842 /* Disable Tx laser; allow 100us to go dark per spec */
1843 esdp_reg |= (TXGBE_GPIOBIT_0 | TXGBE_GPIOBIT_1);
1844 wr32(hw, TXGBE_GPIODATA, esdp_reg);
1850 * txgbe_enable_tx_laser_multispeed_fiber - Enable Tx laser
1851 * @hw: pointer to hardware structure
1853 * The base drivers may require better control over SFP+ module
1854 * PHY states. This includes selectively turning on the Tx
1855 * laser on the PHY, effectively starting physical link.
1857 void txgbe_enable_tx_laser_multispeed_fiber(struct txgbe_hw *hw)
1859 u32 esdp_reg = rd32(hw, TXGBE_GPIODATA);
1861 /* Enable Tx laser; allow 100ms to light up */
1862 esdp_reg &= ~(TXGBE_GPIOBIT_0 | TXGBE_GPIOBIT_1);
1863 wr32(hw, TXGBE_GPIODATA, esdp_reg);
1869 * txgbe_flap_tx_laser_multispeed_fiber - Flap Tx laser
1870 * @hw: pointer to hardware structure
1872 * When the driver changes the link speeds that it can support,
1873 * it sets autotry_restart to true to indicate that we need to
1874 * initiate a new autotry session with the link partner. To do
1875 * so, we set the speed then disable and re-enable the Tx laser, to
1876 * alert the link partner that it also needs to restart autotry on its
1877 * end. This is consistent with true clause 37 autoneg, which also
1878 * involves a loss of signal.
1880 void txgbe_flap_tx_laser_multispeed_fiber(struct txgbe_hw *hw)
1882 DEBUGFUNC("txgbe_flap_tx_laser_multispeed_fiber");
1884 /* Blocked by MNG FW so bail */
1885 if (txgbe_check_reset_blocked(hw))
1888 if (hw->mac.autotry_restart) {
1889 txgbe_disable_tx_laser_multispeed_fiber(hw);
1890 txgbe_enable_tx_laser_multispeed_fiber(hw);
1891 hw->mac.autotry_restart = false;
1896 * txgbe_set_hard_rate_select_speed - Set module link speed
1897 * @hw: pointer to hardware structure
1898 * @speed: link speed to set
1900 * Set module link speed via RS0/RS1 rate select pins.
1902 void txgbe_set_hard_rate_select_speed(struct txgbe_hw *hw,
1905 u32 esdp_reg = rd32(hw, TXGBE_GPIODATA);
1908 case TXGBE_LINK_SPEED_10GB_FULL:
1909 esdp_reg |= (TXGBE_GPIOBIT_4 | TXGBE_GPIOBIT_5);
1911 case TXGBE_LINK_SPEED_1GB_FULL:
1912 esdp_reg &= ~(TXGBE_GPIOBIT_4 | TXGBE_GPIOBIT_5);
1915 DEBUGOUT("Invalid fixed module speed\n");
1919 wr32(hw, TXGBE_GPIODATA, esdp_reg);
1924 * txgbe_setup_mac_link_smartspeed - Set MAC link speed using SmartSpeed
1925 * @hw: pointer to hardware structure
1926 * @speed: new link speed
1927 * @autoneg_wait_to_complete: true when waiting for completion is needed
1929 * Implements the Intel SmartSpeed algorithm.
1931 s32 txgbe_setup_mac_link_smartspeed(struct txgbe_hw *hw,
1933 bool autoneg_wait_to_complete)
1936 u32 link_speed = TXGBE_LINK_SPEED_UNKNOWN;
1938 bool link_up = false;
1939 u32 autoc_reg = rd32_epcs(hw, SR_AN_MMD_ADV_REG1);
1941 DEBUGFUNC("txgbe_setup_mac_link_smartspeed");
1943 /* Set autoneg_advertised value based on input link speed */
1944 hw->phy.autoneg_advertised = 0;
1946 if (speed & TXGBE_LINK_SPEED_10GB_FULL)
1947 hw->phy.autoneg_advertised |= TXGBE_LINK_SPEED_10GB_FULL;
1949 if (speed & TXGBE_LINK_SPEED_1GB_FULL)
1950 hw->phy.autoneg_advertised |= TXGBE_LINK_SPEED_1GB_FULL;
1952 if (speed & TXGBE_LINK_SPEED_100M_FULL)
1953 hw->phy.autoneg_advertised |= TXGBE_LINK_SPEED_100M_FULL;
1956 * Implement Intel SmartSpeed algorithm. SmartSpeed will reduce the
1957 * autoneg advertisement if link is unable to be established at the
1958 * highest negotiated rate. This can sometimes happen due to integrity
1959 * issues with the physical media connection.
1962 /* First, try to get link with full advertisement */
1963 hw->phy.smart_speed_active = false;
1964 for (j = 0; j < TXGBE_SMARTSPEED_MAX_RETRIES; j++) {
1965 status = txgbe_setup_mac_link(hw, speed,
1966 autoneg_wait_to_complete);
1971 * Wait for the controller to acquire link. Per IEEE 802.3ap,
1972 * Section 73.10.2, we may have to wait up to 500ms if KR is
1973 * attempted, or 200ms if KX/KX4/BX/BX4 is attempted, per
1974 * Table 9 in the AN MAS.
1976 for (i = 0; i < 5; i++) {
1979 /* If we have link, just jump out */
1980 status = hw->mac.check_link(hw, &link_speed, &link_up,
1991 * We didn't get link. If we advertised KR plus one of KX4/KX
1992 * (or BX4/BX), then disable KR and try again.
1994 if (((autoc_reg & TXGBE_AUTOC_KR_SUPP) == 0) ||
1995 ((autoc_reg & TXGBE_AUTOC_KX_SUPP) == 0 &&
1996 (autoc_reg & TXGBE_AUTOC_KX4_SUPP) == 0))
1999 /* Turn SmartSpeed on to disable KR support */
2000 hw->phy.smart_speed_active = true;
2001 status = txgbe_setup_mac_link(hw, speed,
2002 autoneg_wait_to_complete);
2007 * Wait for the controller to acquire link. 600ms will allow for
2008 * the AN link_fail_inhibit_timer as well for multiple cycles of
2009 * parallel detect, both 10g and 1g. This allows for the maximum
2010 * connect attempts as defined in the AN MAS table 73-7.
2012 for (i = 0; i < 6; i++) {
2015 /* If we have link, just jump out */
2016 status = hw->mac.check_link(hw, &link_speed, &link_up, false);
2024 /* We didn't get link. Turn SmartSpeed back off. */
2025 hw->phy.smart_speed_active = false;
2026 status = txgbe_setup_mac_link(hw, speed,
2027 autoneg_wait_to_complete);
2030 if (link_up && link_speed == TXGBE_LINK_SPEED_1GB_FULL)
2031 DEBUGOUT("Smartspeed has downgraded the link speed "
2032 "from the maximum advertised\n");
2037 * txgbe_setup_mac_link - Set MAC link speed
2038 * @hw: pointer to hardware structure
2039 * @speed: new link speed
2040 * @autoneg_wait_to_complete: true when waiting for completion is needed
2042 * Set the link speed in the AUTOC register and restarts link.
2044 s32 txgbe_setup_mac_link(struct txgbe_hw *hw,
2046 bool autoneg_wait_to_complete)
2048 bool autoneg = false;
2051 u64 autoc = hw->mac.autoc_read(hw);
2052 u64 pma_pmd_10gs = autoc & TXGBE_AUTOC_10GS_PMA_PMD_MASK;
2053 u64 pma_pmd_1g = autoc & TXGBE_AUTOC_1G_PMA_PMD_MASK;
2054 u64 link_mode = autoc & TXGBE_AUTOC_LMS_MASK;
2055 u64 current_autoc = autoc;
2059 u32 link_capabilities = TXGBE_LINK_SPEED_UNKNOWN;
2061 DEBUGFUNC("txgbe_setup_mac_link");
2063 /* Check to see if speed passed in is supported. */
2064 status = hw->mac.get_link_capabilities(hw,
2065 &link_capabilities, &autoneg);
2069 speed &= link_capabilities;
2070 if (speed == TXGBE_LINK_SPEED_UNKNOWN)
2071 return TXGBE_ERR_LINK_SETUP;
2073 /* Use stored value (EEPROM defaults) of AUTOC to find KR/KX4 support*/
2074 if (hw->mac.orig_link_settings_stored)
2075 orig_autoc = hw->mac.orig_autoc;
2079 link_mode = autoc & TXGBE_AUTOC_LMS_MASK;
2080 pma_pmd_1g = autoc & TXGBE_AUTOC_1G_PMA_PMD_MASK;
2082 if (link_mode == TXGBE_AUTOC_LMS_KX4_KX_KR ||
2083 link_mode == TXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
2084 link_mode == TXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
2085 /* Set KX4/KX/KR support according to speed requested */
2086 autoc &= ~(TXGBE_AUTOC_KX_SUPP |
2087 TXGBE_AUTOC_KX4_SUPP |
2088 TXGBE_AUTOC_KR_SUPP);
2089 if (speed & TXGBE_LINK_SPEED_10GB_FULL) {
2090 if (orig_autoc & TXGBE_AUTOC_KX4_SUPP)
2091 autoc |= TXGBE_AUTOC_KX4_SUPP;
2092 if ((orig_autoc & TXGBE_AUTOC_KR_SUPP) &&
2093 !hw->phy.smart_speed_active)
2094 autoc |= TXGBE_AUTOC_KR_SUPP;
2096 if (speed & TXGBE_LINK_SPEED_1GB_FULL)
2097 autoc |= TXGBE_AUTOC_KX_SUPP;
2098 } else if ((pma_pmd_1g == TXGBE_AUTOC_1G_SFI) &&
2099 (link_mode == TXGBE_AUTOC_LMS_1G_LINK_NO_AN ||
2100 link_mode == TXGBE_AUTOC_LMS_1G_AN)) {
2101 /* Switch from 1G SFI to 10G SFI if requested */
2102 if (speed == TXGBE_LINK_SPEED_10GB_FULL &&
2103 pma_pmd_10gs == TXGBE_AUTOC_10GS_SFI) {
2104 autoc &= ~TXGBE_AUTOC_LMS_MASK;
2105 autoc |= TXGBE_AUTOC_LMS_10G;
2107 } else if ((pma_pmd_10gs == TXGBE_AUTOC_10GS_SFI) &&
2108 (link_mode == TXGBE_AUTOC_LMS_10G)) {
2109 /* Switch from 10G SFI to 1G SFI if requested */
2110 if (speed == TXGBE_LINK_SPEED_1GB_FULL &&
2111 pma_pmd_1g == TXGBE_AUTOC_1G_SFI) {
2112 autoc &= ~TXGBE_AUTOC_LMS_MASK;
2113 if (autoneg || hw->phy.type == txgbe_phy_qsfp_intel)
2114 autoc |= TXGBE_AUTOC_LMS_1G_AN;
2116 autoc |= TXGBE_AUTOC_LMS_1G_LINK_NO_AN;
2120 if (autoc == current_autoc)
2123 autoc &= ~TXGBE_AUTOC_SPEED_MASK;
2124 autoc |= TXGBE_AUTOC_SPEED(speed);
2125 autoc |= (autoneg ? TXGBE_AUTOC_AUTONEG : 0);
2128 hw->mac.autoc_write(hw, autoc);
2130 /* Only poll for autoneg to complete if specified to do so */
2131 if (autoneg_wait_to_complete) {
2132 if (link_mode == TXGBE_AUTOC_LMS_KX4_KX_KR ||
2133 link_mode == TXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
2134 link_mode == TXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
2135 links_reg = 0; /*Just in case Autoneg time=0*/
2136 for (i = 0; i < TXGBE_AUTO_NEG_TIME; i++) {
2137 links_reg = rd32(hw, TXGBE_PORTSTAT);
2138 if (links_reg & TXGBE_PORTSTAT_UP)
2142 if (!(links_reg & TXGBE_PORTSTAT_UP)) {
2143 status = TXGBE_ERR_AUTONEG_NOT_COMPLETE;
2144 DEBUGOUT("Autoneg did not complete.\n");
2149 /* Add delay to filter out noises during initial link setup */
2156 * txgbe_setup_copper_link_raptor - Set the PHY autoneg advertised field
2157 * @hw: pointer to hardware structure
2158 * @speed: new link speed
2159 * @autoneg_wait_to_complete: true if waiting is needed to complete
2161 * Restarts link on PHY and MAC based on settings passed in.
2163 static s32 txgbe_setup_copper_link_raptor(struct txgbe_hw *hw,
2165 bool autoneg_wait_to_complete)
2169 DEBUGFUNC("txgbe_setup_copper_link_raptor");
2171 /* Setup the PHY according to input speed */
2172 status = hw->phy.setup_link_speed(hw, speed,
2173 autoneg_wait_to_complete);
2175 txgbe_start_mac_link_raptor(hw, autoneg_wait_to_complete);
2181 txgbe_check_flash_load(struct txgbe_hw *hw, u32 check_bit)
2186 /* if there's flash existing */
2187 if (!(rd32(hw, TXGBE_SPISTAT) & TXGBE_SPISTAT_BPFLASH)) {
2188 /* wait hw load flash done */
2189 for (i = 0; i < 10; i++) {
2190 reg = rd32(hw, TXGBE_ILDRSTAT);
2191 if (!(reg & check_bit)) {
2198 err = TXGBE_ERR_FLASH_LOADING_FAILED;
2204 txgbe_reset_misc(struct txgbe_hw *hw)
2209 wr32(hw, TXGBE_ISBADDRL, hw->isb_dma & 0x00000000FFFFFFFF);
2210 wr32(hw, TXGBE_ISBADDRH, hw->isb_dma >> 32);
2212 value = rd32_epcs(hw, SR_XS_PCS_CTRL2);
2213 if ((value & 0x3) != SR_PCS_CTRL2_TYPE_SEL_X)
2214 hw->link_status = TXGBE_LINK_STATUS_NONE;
2216 /* receive packets that size > 2048 */
2217 wr32m(hw, TXGBE_MACRXCFG,
2218 TXGBE_MACRXCFG_JUMBO, TXGBE_MACRXCFG_JUMBO);
2220 wr32m(hw, TXGBE_FRMSZ, TXGBE_FRMSZ_MAX_MASK,
2221 TXGBE_FRMSZ_MAX(TXGBE_FRAME_SIZE_DFT));
2223 /* clear counters on read */
2224 wr32m(hw, TXGBE_MACCNTCTL,
2225 TXGBE_MACCNTCTL_RC, TXGBE_MACCNTCTL_RC);
2227 wr32m(hw, TXGBE_RXFCCFG,
2228 TXGBE_RXFCCFG_FC, TXGBE_RXFCCFG_FC);
2229 wr32m(hw, TXGBE_TXFCCFG,
2230 TXGBE_TXFCCFG_FC, TXGBE_TXFCCFG_FC);
2232 wr32m(hw, TXGBE_MACRXFLT,
2233 TXGBE_MACRXFLT_PROMISC, TXGBE_MACRXFLT_PROMISC);
2235 wr32m(hw, TXGBE_RSTSTAT,
2236 TXGBE_RSTSTAT_TMRINIT_MASK, TXGBE_RSTSTAT_TMRINIT(30));
2238 /* errata 4: initialize mng flex tbl and wakeup flex tbl*/
2239 wr32(hw, TXGBE_MNGFLEXSEL, 0);
2240 for (i = 0; i < 16; i++) {
2241 wr32(hw, TXGBE_MNGFLEXDWL(i), 0);
2242 wr32(hw, TXGBE_MNGFLEXDWH(i), 0);
2243 wr32(hw, TXGBE_MNGFLEXMSK(i), 0);
2245 wr32(hw, TXGBE_LANFLEXSEL, 0);
2246 for (i = 0; i < 16; i++) {
2247 wr32(hw, TXGBE_LANFLEXDWL(i), 0);
2248 wr32(hw, TXGBE_LANFLEXDWH(i), 0);
2249 wr32(hw, TXGBE_LANFLEXMSK(i), 0);
2252 /* set pause frame dst mac addr */
2253 wr32(hw, TXGBE_RXPBPFCDMACL, 0xC2000001);
2254 wr32(hw, TXGBE_RXPBPFCDMACH, 0x0180);
2256 hw->mac.init_thermal_sensor_thresh(hw);
2258 /* enable mac transmitter */
2259 wr32m(hw, TXGBE_MACTXCFG, TXGBE_MACTXCFG_TXE, TXGBE_MACTXCFG_TXE);
2261 for (i = 0; i < 4; i++)
2262 wr32m(hw, TXGBE_IVAR(i), 0x80808080, 0);
2266 * txgbe_reset_hw - Perform hardware reset
2267 * @hw: pointer to hardware structure
2269 * Resets the hardware by resetting the transmit and receive units, masks
2270 * and clears all interrupts, perform a PHY reset, and perform a link (MAC)
2273 s32 txgbe_reset_hw(struct txgbe_hw *hw)
2278 DEBUGFUNC("txgbe_reset_hw");
2280 /* Call adapter stop to disable tx/rx and clear interrupts */
2281 status = hw->mac.stop_hw(hw);
2285 /* flush pending Tx transactions */
2286 txgbe_clear_tx_pending(hw);
2288 /* Identify PHY and related function pointers */
2289 status = hw->phy.init(hw);
2290 if (status == TXGBE_ERR_SFP_NOT_SUPPORTED)
2293 /* Setup SFP module if there is one present. */
2294 if (hw->phy.sfp_setup_needed) {
2295 status = hw->mac.setup_sfp(hw);
2296 hw->phy.sfp_setup_needed = false;
2298 if (status == TXGBE_ERR_SFP_NOT_SUPPORTED)
2302 if (!hw->phy.reset_disable)
2305 /* remember AUTOC from before we reset */
2306 autoc = hw->mac.autoc_read(hw);
2310 * Issue global reset to the MAC. Needs to be SW reset if link is up.
2311 * If link reset is used when link is up, it might reset the PHY when
2312 * mng is using it. If link is down or the flag to force full link
2313 * reset is set, then perform link reset.
2315 if (txgbe_mng_present(hw)) {
2316 txgbe_hic_reset(hw);
2318 wr32(hw, TXGBE_RST, TXGBE_RST_LAN(hw->bus.lan_id));
2323 txgbe_reset_misc(hw);
2325 if (hw->bus.lan_id == 0) {
2326 status = txgbe_check_flash_load(hw,
2327 TXGBE_ILDRSTAT_SWRST_LAN0);
2329 status = txgbe_check_flash_load(hw,
2330 TXGBE_ILDRSTAT_SWRST_LAN1);
2338 * Double resets are required for recovery from certain error
2339 * conditions. Between resets, it is necessary to stall to
2340 * allow time for any pending HW events to complete.
2342 if (hw->mac.flags & TXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
2343 hw->mac.flags &= ~TXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
2348 * Store the original AUTOC/AUTOC2 values if they have not been
2349 * stored off yet. Otherwise restore the stored original
2350 * values since the reset operation sets back to defaults.
2352 if (!hw->mac.orig_link_settings_stored) {
2353 hw->mac.orig_autoc = hw->mac.autoc_read(hw);
2354 hw->mac.autoc_write(hw, hw->mac.orig_autoc);
2355 hw->mac.orig_link_settings_stored = true;
2357 hw->mac.orig_autoc = autoc;
2360 /* Store the permanent mac address */
2361 hw->mac.get_mac_addr(hw, hw->mac.perm_addr);
2364 * Store MAC address from RAR0, clear receive address registers, and
2365 * clear the multicast table. Also reset num_rar_entries to 128,
2366 * since we modify this value when programming the SAN MAC address.
2368 hw->mac.num_rar_entries = 128;
2369 hw->mac.init_rx_addrs(hw);
2371 /* Store the permanent SAN mac address */
2372 hw->mac.get_san_mac_addr(hw, hw->mac.san_addr);
2374 /* Add the SAN MAC address to the RAR only if it's a valid address */
2375 if (txgbe_validate_mac_addr(hw->mac.san_addr) == 0) {
2376 /* Save the SAN MAC RAR index */
2377 hw->mac.san_mac_rar_index = hw->mac.num_rar_entries - 1;
2379 hw->mac.set_rar(hw, hw->mac.san_mac_rar_index,
2380 hw->mac.san_addr, 0, true);
2382 /* clear VMDq pool/queue selection for this RAR */
2383 hw->mac.clear_vmdq(hw, hw->mac.san_mac_rar_index,
2386 /* Reserve the last RAR for the SAN MAC address */
2387 hw->mac.num_rar_entries--;
2390 /* Store the alternative WWNN/WWPN prefix */
2391 hw->mac.get_wwn_prefix(hw, &hw->mac.wwnn_prefix,
2392 &hw->mac.wwpn_prefix);
2398 * txgbe_start_hw_raptor - Prepare hardware for Tx/Rx
2399 * @hw: pointer to hardware structure
2401 * Starts the hardware using the generic start_hw function
2402 * and the generation start_hw function.
2403 * Then performs revision-specific operations, if any.
2405 s32 txgbe_start_hw_raptor(struct txgbe_hw *hw)
2409 DEBUGFUNC("txgbe_start_hw_raptor");
2411 err = txgbe_start_hw(hw);
2415 err = txgbe_start_hw_gen2(hw);
2419 /* We need to run link autotry after the driver loads */
2420 hw->mac.autotry_restart = true;
2427 * txgbe_enable_rx_dma_raptor - Enable the Rx DMA unit
2428 * @hw: pointer to hardware structure
2429 * @regval: register value to write to RXCTRL
2431 * Enables the Rx DMA unit
2433 s32 txgbe_enable_rx_dma_raptor(struct txgbe_hw *hw, u32 regval)
2435 DEBUGFUNC("txgbe_enable_rx_dma_raptor");
2438 * Workaround silicon errata when enabling the Rx datapath.
2439 * If traffic is incoming before we enable the Rx unit, it could hang
2440 * the Rx DMA unit. Therefore, make sure the security engine is
2441 * completely disabled prior to enabling the Rx unit.
2444 hw->mac.disable_sec_rx_path(hw);
2446 if (regval & TXGBE_PBRXCTL_ENA)
2447 txgbe_enable_rx(hw);
2449 txgbe_disable_rx(hw);
2451 hw->mac.enable_sec_rx_path(hw);
2457 * txgbe_verify_lesm_fw_enabled_raptor - Checks LESM FW module state.
2458 * @hw: pointer to hardware structure
2460 * Returns true if the LESM FW module is present and enabled. Otherwise
2461 * returns false. Smart Speed must be disabled if LESM FW module is enabled.
2463 bool txgbe_verify_lesm_fw_enabled_raptor(struct txgbe_hw *hw)
2465 bool lesm_enabled = false;
2466 u16 fw_offset, fw_lesm_param_offset, fw_lesm_state;
2469 DEBUGFUNC("txgbe_verify_lesm_fw_enabled_raptor");
2471 /* get the offset to the Firmware Module block */
2472 status = hw->rom.read16(hw, TXGBE_FW_PTR, &fw_offset);
2474 if (status != 0 || fw_offset == 0 || fw_offset == 0xFFFF)
2477 /* get the offset to the LESM Parameters block */
2478 status = hw->rom.read16(hw, (fw_offset +
2479 TXGBE_FW_LESM_PARAMETERS_PTR),
2480 &fw_lesm_param_offset);
2483 fw_lesm_param_offset == 0 || fw_lesm_param_offset == 0xFFFF)
2486 /* get the LESM state word */
2487 status = hw->rom.read16(hw, (fw_lesm_param_offset +
2488 TXGBE_FW_LESM_STATE_1),
2491 if (status == 0 && (fw_lesm_state & TXGBE_FW_LESM_STATE_ENABLED))
2492 lesm_enabled = true;
2495 lesm_enabled = false;
2496 return lesm_enabled;
2500 * txgbe_reset_pipeline_raptor - perform pipeline reset
2502 * @hw: pointer to hardware structure
2504 * Reset pipeline by asserting Restart_AN together with LMS change to ensure
2505 * full pipeline reset. This function assumes the SW/FW lock is held.
2507 s32 txgbe_reset_pipeline_raptor(struct txgbe_hw *hw)
2512 autoc = hw->mac.autoc_read(hw);
2514 /* Enable link if disabled in NVM */
2515 if (autoc & TXGBE_AUTOC_LINK_DIA_MASK)
2516 autoc &= ~TXGBE_AUTOC_LINK_DIA_MASK;
2518 autoc |= TXGBE_AUTOC_AN_RESTART;
2519 /* Write AUTOC register with toggled LMS[2] bit and Restart_AN */
2520 hw->mac.autoc_write(hw, autoc ^ TXGBE_AUTOC_LMS_AN);
2522 /* Write AUTOC register with original LMS field and Restart_AN */
2523 hw->mac.autoc_write(hw, autoc);