1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2015-2020
5 #include "txgbe_type.h"
9 #include "txgbe_eeprom.h"
10 #include "txgbe_mng.h"
13 #define TXGBE_RAPTOR_MAX_TX_QUEUES 128
14 #define TXGBE_RAPTOR_MAX_RX_QUEUES 128
15 #define TXGBE_RAPTOR_RAR_ENTRIES 128
16 #define TXGBE_RAPTOR_MC_TBL_SIZE 128
17 #define TXGBE_RAPTOR_VFT_TBL_SIZE 128
18 #define TXGBE_RAPTOR_RX_PB_SIZE 512 /*KB*/
20 static s32 txgbe_setup_copper_link_raptor(struct txgbe_hw *hw,
22 bool autoneg_wait_to_complete);
24 static s32 txgbe_mta_vector(struct txgbe_hw *hw, u8 *mc_addr);
25 static s32 txgbe_get_san_mac_addr_offset(struct txgbe_hw *hw,
29 * txgbe_device_supports_autoneg_fc - Check if device supports autonegotiation
31 * @hw: pointer to hardware structure
33 * This function returns true if the device supports flow control
34 * autonegotiation, and false if it does not.
37 bool txgbe_device_supports_autoneg_fc(struct txgbe_hw *hw)
39 bool supported = false;
43 DEBUGFUNC("txgbe_device_supports_autoneg_fc");
45 switch (hw->phy.media_type) {
46 case txgbe_media_type_fiber_qsfp:
47 case txgbe_media_type_fiber:
48 hw->mac.check_link(hw, &speed, &link_up, false);
49 /* if link is down, assume supported */
51 supported = speed == TXGBE_LINK_SPEED_1GB_FULL ?
57 case txgbe_media_type_backplane:
60 case txgbe_media_type_copper:
61 /* only some copper devices support flow control autoneg */
62 switch (hw->device_id) {
63 case TXGBE_DEV_ID_RAPTOR_XAUI:
64 case TXGBE_DEV_ID_RAPTOR_SGMII:
75 DEBUGOUT("Device %x does not support flow control autoneg",
81 * txgbe_setup_fc - Set up flow control
82 * @hw: pointer to hardware structure
84 * Called at init time to set up flow control.
86 s32 txgbe_setup_fc(struct txgbe_hw *hw)
95 DEBUGFUNC("txgbe_setup_fc");
97 /* Validate the requested mode */
98 if (hw->fc.strict_ieee && hw->fc.requested_mode == txgbe_fc_rx_pause) {
99 DEBUGOUT("txgbe_fc_rx_pause not valid in strict IEEE mode\n");
100 err = TXGBE_ERR_INVALID_LINK_SETTINGS;
105 * 10gig parts do not have a word in the EEPROM to determine the
106 * default flow control setting, so we explicitly set it to full.
108 if (hw->fc.requested_mode == txgbe_fc_default)
109 hw->fc.requested_mode = txgbe_fc_full;
112 * Set up the 1G and 10G flow control advertisement registers so the
113 * HW will be able to do fc autoneg once the cable is plugged in. If
114 * we link at 10G, the 1G advertisement is harmless and vice versa.
116 switch (hw->phy.media_type) {
117 case txgbe_media_type_backplane:
118 /* some MAC's need RMW protection on AUTOC */
119 err = hw->mac.prot_autoc_read(hw, &locked, ®_bp);
123 /* fall through - only backplane uses autoc */
124 case txgbe_media_type_fiber_qsfp:
125 case txgbe_media_type_fiber:
126 case txgbe_media_type_copper:
127 hw->phy.read_reg(hw, TXGBE_MD_AUTO_NEG_ADVT,
128 TXGBE_MD_DEV_AUTO_NEG, ®_cu);
135 * The possible values of fc.requested_mode are:
136 * 0: Flow control is completely disabled
137 * 1: Rx flow control is enabled (we can receive pause frames,
138 * but not send pause frames).
139 * 2: Tx flow control is enabled (we can send pause frames but
140 * we do not support receiving pause frames).
141 * 3: Both Rx and Tx flow control (symmetric) are enabled.
144 switch (hw->fc.requested_mode) {
146 /* Flow control completely disabled by software override. */
147 reg &= ~(SR_MII_MMD_AN_ADV_PAUSE_SYM |
148 SR_MII_MMD_AN_ADV_PAUSE_ASM);
149 if (hw->phy.media_type == txgbe_media_type_backplane)
150 reg_bp &= ~(TXGBE_AUTOC_SYM_PAUSE |
151 TXGBE_AUTOC_ASM_PAUSE);
152 else if (hw->phy.media_type == txgbe_media_type_copper)
153 reg_cu &= ~(TXGBE_TAF_SYM_PAUSE | TXGBE_TAF_ASM_PAUSE);
155 case txgbe_fc_tx_pause:
157 * Tx Flow control is enabled, and Rx Flow control is
158 * disabled by software override.
160 reg |= SR_MII_MMD_AN_ADV_PAUSE_ASM;
161 reg &= ~SR_MII_MMD_AN_ADV_PAUSE_SYM;
162 if (hw->phy.media_type == txgbe_media_type_backplane) {
163 reg_bp |= TXGBE_AUTOC_ASM_PAUSE;
164 reg_bp &= ~TXGBE_AUTOC_SYM_PAUSE;
165 } else if (hw->phy.media_type == txgbe_media_type_copper) {
166 reg_cu |= TXGBE_TAF_ASM_PAUSE;
167 reg_cu &= ~TXGBE_TAF_SYM_PAUSE;
169 reg |= SR_MII_MMD_AN_ADV_PAUSE_ASM;
170 reg_bp |= SR_AN_MMD_ADV_REG1_PAUSE_ASM;
172 case txgbe_fc_rx_pause:
174 * Rx Flow control is enabled and Tx Flow control is
175 * disabled by software override. Since there really
176 * isn't a way to advertise that we are capable of RX
177 * Pause ONLY, we will advertise that we support both
178 * symmetric and asymmetric Rx PAUSE, as such we fall
179 * through to the fc_full statement. Later, we will
180 * disable the adapter's ability to send PAUSE frames.
183 /* Flow control (both Rx and Tx) is enabled by SW override. */
184 reg |= SR_MII_MMD_AN_ADV_PAUSE_SYM |
185 SR_MII_MMD_AN_ADV_PAUSE_ASM;
186 if (hw->phy.media_type == txgbe_media_type_backplane)
187 reg_bp |= TXGBE_AUTOC_SYM_PAUSE |
188 TXGBE_AUTOC_ASM_PAUSE;
189 else if (hw->phy.media_type == txgbe_media_type_copper)
190 reg_cu |= TXGBE_TAF_SYM_PAUSE | TXGBE_TAF_ASM_PAUSE;
191 reg |= SR_MII_MMD_AN_ADV_PAUSE_SYM |
192 SR_MII_MMD_AN_ADV_PAUSE_ASM;
193 reg_bp |= SR_AN_MMD_ADV_REG1_PAUSE_SYM |
194 SR_AN_MMD_ADV_REG1_PAUSE_ASM;
197 DEBUGOUT("Flow control param set incorrectly\n");
198 err = TXGBE_ERR_CONFIG;
203 * Enable auto-negotiation between the MAC & PHY;
204 * the MAC will advertise clause 37 flow control.
206 value = rd32_epcs(hw, SR_MII_MMD_AN_ADV);
207 value = (value & ~(SR_MII_MMD_AN_ADV_PAUSE_ASM |
208 SR_MII_MMD_AN_ADV_PAUSE_SYM)) | reg;
209 wr32_epcs(hw, SR_MII_MMD_AN_ADV, value);
212 * AUTOC restart handles negotiation of 1G and 10G on backplane
213 * and copper. There is no need to set the PCS1GCTL register.
216 if (hw->phy.media_type == txgbe_media_type_backplane) {
217 value = rd32_epcs(hw, SR_AN_MMD_ADV_REG1);
218 value = (value & ~(SR_AN_MMD_ADV_REG1_PAUSE_ASM |
219 SR_AN_MMD_ADV_REG1_PAUSE_SYM)) |
221 wr32_epcs(hw, SR_AN_MMD_ADV_REG1, value);
222 } else if ((hw->phy.media_type == txgbe_media_type_copper) &&
223 (txgbe_device_supports_autoneg_fc(hw))) {
224 hw->phy.write_reg(hw, TXGBE_MD_AUTO_NEG_ADVT,
225 TXGBE_MD_DEV_AUTO_NEG, reg_cu);
228 DEBUGOUT("Set up FC; reg = 0x%08X\n", reg);
234 * txgbe_start_hw - Prepare hardware for Tx/Rx
235 * @hw: pointer to hardware structure
237 * Starts the hardware by filling the bus info structure and media type, clears
238 * all on chip counters, initializes receive address registers, multicast
239 * table, VLAN filter table, calls routine to set up link and flow control
240 * settings, and leaves transmit and receive units disabled and uninitialized
242 s32 txgbe_start_hw(struct txgbe_hw *hw)
247 DEBUGFUNC("txgbe_start_hw");
249 /* Set the media type */
250 hw->phy.media_type = hw->phy.get_media_type(hw);
252 /* Clear the VLAN filter table */
253 hw->mac.clear_vfta(hw);
255 /* Clear statistics registers */
256 hw->mac.clear_hw_cntrs(hw);
258 /* Setup flow control */
259 err = txgbe_setup_fc(hw);
260 if (err != 0 && err != TXGBE_NOT_IMPLEMENTED) {
261 DEBUGOUT("Flow control setup failed, returning %d\n", err);
265 /* Cache bit indicating need for crosstalk fix */
266 switch (hw->mac.type) {
267 case txgbe_mac_raptor:
268 hw->mac.get_device_caps(hw, &device_caps);
269 if (device_caps & TXGBE_DEVICE_CAPS_NO_CROSSTALK_WR)
270 hw->need_crosstalk_fix = false;
272 hw->need_crosstalk_fix = true;
275 hw->need_crosstalk_fix = false;
279 /* Clear adapter stopped flag */
280 hw->adapter_stopped = false;
286 * txgbe_start_hw_gen2 - Init sequence for common device family
287 * @hw: pointer to hw structure
289 * Performs the init sequence common to the second generation
292 s32 txgbe_start_hw_gen2(struct txgbe_hw *hw)
296 /* Clear the rate limiters */
297 for (i = 0; i < hw->mac.max_tx_queues; i++) {
298 wr32(hw, TXGBE_ARBPOOLIDX, i);
299 wr32(hw, TXGBE_ARBTXRATE, 0);
303 /* We need to run link autotry after the driver loads */
304 hw->mac.autotry_restart = true;
310 * txgbe_init_hw - Generic hardware initialization
311 * @hw: pointer to hardware structure
313 * Initialize the hardware by resetting the hardware, filling the bus info
314 * structure and media type, clears all on chip counters, initializes receive
315 * address registers, multicast table, VLAN filter table, calls routine to set
316 * up link and flow control settings, and leaves transmit and receive units
317 * disabled and uninitialized
319 s32 txgbe_init_hw(struct txgbe_hw *hw)
323 DEBUGFUNC("txgbe_init_hw");
325 /* Reset the hardware */
326 status = hw->mac.reset_hw(hw);
327 if (status == 0 || status == TXGBE_ERR_SFP_NOT_PRESENT) {
329 status = hw->mac.start_hw(hw);
333 DEBUGOUT("Failed to initialize HW, STATUS = %d\n", status);
339 * txgbe_clear_hw_cntrs - Generic clear hardware counters
340 * @hw: pointer to hardware structure
342 * Clears all hardware statistics counters by reading them from the hardware
343 * Statistics counters are clear on read.
345 s32 txgbe_clear_hw_cntrs(struct txgbe_hw *hw)
349 DEBUGFUNC("txgbe_clear_hw_cntrs");
352 /* don't write clear queue stats */
353 for (i = 0; i < TXGBE_MAX_QP; i++) {
354 hw->qp_last[i].rx_qp_packets = 0;
355 hw->qp_last[i].tx_qp_packets = 0;
356 hw->qp_last[i].rx_qp_bytes = 0;
357 hw->qp_last[i].tx_qp_bytes = 0;
358 hw->qp_last[i].rx_qp_mc_packets = 0;
362 for (i = 0; i < TXGBE_MAX_UP; i++) {
363 rd32(hw, TXGBE_PBRXUPXON(i));
364 rd32(hw, TXGBE_PBRXUPXOFF(i));
365 rd32(hw, TXGBE_PBTXUPXON(i));
366 rd32(hw, TXGBE_PBTXUPXOFF(i));
367 rd32(hw, TXGBE_PBTXUPOFF(i));
369 rd32(hw, TXGBE_PBRXMISS(i));
371 rd32(hw, TXGBE_PBRXLNKXON);
372 rd32(hw, TXGBE_PBRXLNKXOFF);
373 rd32(hw, TXGBE_PBTXLNKXON);
374 rd32(hw, TXGBE_PBTXLNKXOFF);
377 rd32(hw, TXGBE_DMARXPKT);
378 rd32(hw, TXGBE_DMATXPKT);
380 rd64(hw, TXGBE_DMARXOCTL);
381 rd64(hw, TXGBE_DMATXOCTL);
384 rd64(hw, TXGBE_MACRXERRCRCL);
385 rd64(hw, TXGBE_MACRXMPKTL);
386 rd64(hw, TXGBE_MACTXMPKTL);
388 rd64(hw, TXGBE_MACRXPKTL);
389 rd64(hw, TXGBE_MACTXPKTL);
390 rd64(hw, TXGBE_MACRXGBOCTL);
392 rd64(hw, TXGBE_MACRXOCTL);
393 rd32(hw, TXGBE_MACTXOCTL);
395 rd64(hw, TXGBE_MACRX1TO64L);
396 rd64(hw, TXGBE_MACRX65TO127L);
397 rd64(hw, TXGBE_MACRX128TO255L);
398 rd64(hw, TXGBE_MACRX256TO511L);
399 rd64(hw, TXGBE_MACRX512TO1023L);
400 rd64(hw, TXGBE_MACRX1024TOMAXL);
401 rd64(hw, TXGBE_MACTX1TO64L);
402 rd64(hw, TXGBE_MACTX65TO127L);
403 rd64(hw, TXGBE_MACTX128TO255L);
404 rd64(hw, TXGBE_MACTX256TO511L);
405 rd64(hw, TXGBE_MACTX512TO1023L);
406 rd64(hw, TXGBE_MACTX1024TOMAXL);
408 rd64(hw, TXGBE_MACRXERRLENL);
409 rd32(hw, TXGBE_MACRXOVERSIZE);
410 rd32(hw, TXGBE_MACRXJABBER);
413 rd32(hw, TXGBE_FCOECRC);
414 rd32(hw, TXGBE_FCOELAST);
415 rd32(hw, TXGBE_FCOERPDC);
416 rd32(hw, TXGBE_FCOEPRC);
417 rd32(hw, TXGBE_FCOEPTC);
418 rd32(hw, TXGBE_FCOEDWRC);
419 rd32(hw, TXGBE_FCOEDWTC);
421 /* Flow Director Stats */
422 rd32(hw, TXGBE_FDIRMATCH);
423 rd32(hw, TXGBE_FDIRMISS);
424 rd32(hw, TXGBE_FDIRUSED);
425 rd32(hw, TXGBE_FDIRUSED);
426 rd32(hw, TXGBE_FDIRFAIL);
427 rd32(hw, TXGBE_FDIRFAIL);
430 rd32(hw, TXGBE_LSECTX_UTPKT);
431 rd32(hw, TXGBE_LSECTX_ENCPKT);
432 rd32(hw, TXGBE_LSECTX_PROTPKT);
433 rd32(hw, TXGBE_LSECTX_ENCOCT);
434 rd32(hw, TXGBE_LSECTX_PROTOCT);
435 rd32(hw, TXGBE_LSECRX_UTPKT);
436 rd32(hw, TXGBE_LSECRX_BTPKT);
437 rd32(hw, TXGBE_LSECRX_NOSCIPKT);
438 rd32(hw, TXGBE_LSECRX_UNSCIPKT);
439 rd32(hw, TXGBE_LSECRX_DECOCT);
440 rd32(hw, TXGBE_LSECRX_VLDOCT);
441 rd32(hw, TXGBE_LSECRX_UNCHKPKT);
442 rd32(hw, TXGBE_LSECRX_DLYPKT);
443 rd32(hw, TXGBE_LSECRX_LATEPKT);
444 for (i = 0; i < 2; i++) {
445 rd32(hw, TXGBE_LSECRX_OKPKT(i));
446 rd32(hw, TXGBE_LSECRX_INVPKT(i));
447 rd32(hw, TXGBE_LSECRX_BADPKT(i));
449 rd32(hw, TXGBE_LSECRX_INVSAPKT);
450 rd32(hw, TXGBE_LSECRX_BADSAPKT);
456 * txgbe_get_mac_addr - Generic get MAC address
457 * @hw: pointer to hardware structure
458 * @mac_addr: Adapter MAC address
460 * Reads the adapter's MAC address from first Receive Address Register (RAR0)
461 * A reset of the adapter must be performed prior to calling this function
462 * in order for the MAC address to have been loaded from the EEPROM into RAR0
464 s32 txgbe_get_mac_addr(struct txgbe_hw *hw, u8 *mac_addr)
470 DEBUGFUNC("txgbe_get_mac_addr");
472 wr32(hw, TXGBE_ETHADDRIDX, 0);
473 rar_high = rd32(hw, TXGBE_ETHADDRH);
474 rar_low = rd32(hw, TXGBE_ETHADDRL);
476 for (i = 0; i < 2; i++)
477 mac_addr[i] = (u8)(rar_high >> (1 - i) * 8);
479 for (i = 0; i < 4; i++)
480 mac_addr[i + 2] = (u8)(rar_low >> (3 - i) * 8);
486 * txgbe_set_lan_id_multi_port - Set LAN id for PCIe multiple port devices
487 * @hw: pointer to the HW structure
489 * Determines the LAN function id by reading memory-mapped registers and swaps
490 * the port value if requested, and set MAC instance for devices.
492 void txgbe_set_lan_id_multi_port(struct txgbe_hw *hw)
494 struct txgbe_bus_info *bus = &hw->bus;
497 DEBUGFUNC("txgbe_set_lan_id_multi_port_pcie");
499 reg = rd32(hw, TXGBE_PORTSTAT);
500 bus->lan_id = TXGBE_PORTSTAT_ID(reg);
502 /* check for single port */
503 reg = rd32(hw, TXGBE_PWR);
504 if (TXGBE_PWR_LANID(reg) == TXGBE_PWR_LANID_SWAP)
507 bus->func = bus->lan_id;
511 * txgbe_stop_hw - Generic stop Tx/Rx units
512 * @hw: pointer to hardware structure
514 * Sets the adapter_stopped flag within txgbe_hw struct. Clears interrupts,
515 * disables transmit and receive units. The adapter_stopped flag is used by
516 * the shared code and drivers to determine if the adapter is in a stopped
517 * state and should not touch the hardware.
519 s32 txgbe_stop_hw(struct txgbe_hw *hw)
524 DEBUGFUNC("txgbe_stop_hw");
527 * Set the adapter_stopped flag so other driver functions stop touching
530 hw->adapter_stopped = true;
532 /* Disable the receive unit */
533 txgbe_disable_rx(hw);
535 /* Clear interrupt mask to stop interrupts from being generated */
536 wr32(hw, TXGBE_IENMISC, 0);
537 wr32(hw, TXGBE_IMS(0), TXGBE_IMS_MASK);
538 wr32(hw, TXGBE_IMS(1), TXGBE_IMS_MASK);
540 /* Clear any pending interrupts, flush previous writes */
541 wr32(hw, TXGBE_ICRMISC, TXGBE_ICRMISC_MASK);
542 wr32(hw, TXGBE_ICR(0), TXGBE_ICR_MASK);
543 wr32(hw, TXGBE_ICR(1), TXGBE_ICR_MASK);
545 /* Disable the transmit unit. Each queue must be disabled. */
546 for (i = 0; i < hw->mac.max_tx_queues; i++)
547 wr32(hw, TXGBE_TXCFG(i), TXGBE_TXCFG_FLUSH);
549 /* Disable the receive unit by stopping each queue */
550 for (i = 0; i < hw->mac.max_rx_queues; i++) {
551 reg_val = rd32(hw, TXGBE_RXCFG(i));
552 reg_val &= ~TXGBE_RXCFG_ENA;
553 wr32(hw, TXGBE_RXCFG(i), reg_val);
556 /* flush all queues disables */
564 * txgbe_led_on - Turns on the software controllable LEDs.
565 * @hw: pointer to hardware structure
566 * @index: led number to turn on
568 s32 txgbe_led_on(struct txgbe_hw *hw, u32 index)
570 u32 led_reg = rd32(hw, TXGBE_LEDCTL);
572 DEBUGFUNC("txgbe_led_on");
575 return TXGBE_ERR_PARAM;
577 /* To turn on the LED, set mode to ON. */
578 led_reg |= TXGBE_LEDCTL_SEL(index);
579 led_reg |= TXGBE_LEDCTL_ORD(index);
580 wr32(hw, TXGBE_LEDCTL, led_reg);
587 * txgbe_led_off - Turns off the software controllable LEDs.
588 * @hw: pointer to hardware structure
589 * @index: led number to turn off
591 s32 txgbe_led_off(struct txgbe_hw *hw, u32 index)
593 u32 led_reg = rd32(hw, TXGBE_LEDCTL);
595 DEBUGFUNC("txgbe_led_off");
598 return TXGBE_ERR_PARAM;
600 /* To turn off the LED, set mode to OFF. */
601 led_reg &= ~(TXGBE_LEDCTL_SEL(index));
602 led_reg &= ~(TXGBE_LEDCTL_ORD(index));
603 wr32(hw, TXGBE_LEDCTL, led_reg);
610 * txgbe_validate_mac_addr - Validate MAC address
611 * @mac_addr: pointer to MAC address.
613 * Tests a MAC address to ensure it is a valid Individual Address.
615 s32 txgbe_validate_mac_addr(u8 *mac_addr)
619 DEBUGFUNC("txgbe_validate_mac_addr");
621 /* Make sure it is not a multicast address */
622 if (TXGBE_IS_MULTICAST(mac_addr)) {
623 status = TXGBE_ERR_INVALID_MAC_ADDR;
624 /* Not a broadcast address */
625 } else if (TXGBE_IS_BROADCAST(mac_addr)) {
626 status = TXGBE_ERR_INVALID_MAC_ADDR;
627 /* Reject the zero address */
628 } else if (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 &&
629 mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0) {
630 status = TXGBE_ERR_INVALID_MAC_ADDR;
636 * txgbe_set_rar - Set Rx address register
637 * @hw: pointer to hardware structure
638 * @index: Receive address register to write
639 * @addr: Address to put into receive address register
640 * @vmdq: VMDq "set" or "pool" index
641 * @enable_addr: set flag that address is active
643 * Puts an ethernet address into a receive address register.
645 s32 txgbe_set_rar(struct txgbe_hw *hw, u32 index, u8 *addr, u32 vmdq,
648 u32 rar_low, rar_high;
649 u32 rar_entries = hw->mac.num_rar_entries;
651 DEBUGFUNC("txgbe_set_rar");
653 /* Make sure we are using a valid rar index range */
654 if (index >= rar_entries) {
655 DEBUGOUT("RAR index %d is out of range.\n", index);
656 return TXGBE_ERR_INVALID_ARGUMENT;
659 /* setup VMDq pool selection before this RAR gets enabled */
660 hw->mac.set_vmdq(hw, index, vmdq);
663 * HW expects these in little endian so we reverse the byte
664 * order from network order (big endian) to little endian
666 rar_low = TXGBE_ETHADDRL_AD0(addr[5]) |
667 TXGBE_ETHADDRL_AD1(addr[4]) |
668 TXGBE_ETHADDRL_AD2(addr[3]) |
669 TXGBE_ETHADDRL_AD3(addr[2]);
671 * Some parts put the VMDq setting in the extra RAH bits,
672 * so save everything except the lower 16 bits that hold part
673 * of the address and the address valid bit.
675 rar_high = rd32(hw, TXGBE_ETHADDRH);
676 rar_high &= ~TXGBE_ETHADDRH_AD_MASK;
677 rar_high |= (TXGBE_ETHADDRH_AD4(addr[1]) |
678 TXGBE_ETHADDRH_AD5(addr[0]));
680 rar_high &= ~TXGBE_ETHADDRH_VLD;
681 if (enable_addr != 0)
682 rar_high |= TXGBE_ETHADDRH_VLD;
684 wr32(hw, TXGBE_ETHADDRIDX, index);
685 wr32(hw, TXGBE_ETHADDRL, rar_low);
686 wr32(hw, TXGBE_ETHADDRH, rar_high);
692 * txgbe_clear_rar - Remove Rx address register
693 * @hw: pointer to hardware structure
694 * @index: Receive address register to write
696 * Clears an ethernet address from a receive address register.
698 s32 txgbe_clear_rar(struct txgbe_hw *hw, u32 index)
701 u32 rar_entries = hw->mac.num_rar_entries;
703 DEBUGFUNC("txgbe_clear_rar");
705 /* Make sure we are using a valid rar index range */
706 if (index >= rar_entries) {
707 DEBUGOUT("RAR index %d is out of range.\n", index);
708 return TXGBE_ERR_INVALID_ARGUMENT;
712 * Some parts put the VMDq setting in the extra RAH bits,
713 * so save everything except the lower 16 bits that hold part
714 * of the address and the address valid bit.
716 wr32(hw, TXGBE_ETHADDRIDX, index);
717 rar_high = rd32(hw, TXGBE_ETHADDRH);
718 rar_high &= ~(TXGBE_ETHADDRH_AD_MASK | TXGBE_ETHADDRH_VLD);
720 wr32(hw, TXGBE_ETHADDRL, 0);
721 wr32(hw, TXGBE_ETHADDRH, rar_high);
723 /* clear VMDq pool/queue selection for this RAR */
724 hw->mac.clear_vmdq(hw, index, BIT_MASK32);
730 * txgbe_init_rx_addrs - Initializes receive address filters.
731 * @hw: pointer to hardware structure
733 * Places the MAC address in receive address register 0 and clears the rest
734 * of the receive address registers. Clears the multicast table. Assumes
735 * the receiver is in reset when the routine is called.
737 s32 txgbe_init_rx_addrs(struct txgbe_hw *hw)
741 u32 rar_entries = hw->mac.num_rar_entries;
743 DEBUGFUNC("txgbe_init_rx_addrs");
746 * If the current mac address is valid, assume it is a software override
747 * to the permanent address.
748 * Otherwise, use the permanent address from the eeprom.
750 if (txgbe_validate_mac_addr(hw->mac.addr) ==
751 TXGBE_ERR_INVALID_MAC_ADDR) {
752 /* Get the MAC address from the RAR0 for later reference */
753 hw->mac.get_mac_addr(hw, hw->mac.addr);
755 DEBUGOUT(" Keeping Current RAR0 Addr =%.2X %.2X %.2X ",
756 hw->mac.addr[0], hw->mac.addr[1],
758 DEBUGOUT("%.2X %.2X %.2X\n", hw->mac.addr[3],
759 hw->mac.addr[4], hw->mac.addr[5]);
761 /* Setup the receive address. */
762 DEBUGOUT("Overriding MAC Address in RAR[0]\n");
763 DEBUGOUT(" New MAC Addr =%.2X %.2X %.2X ",
764 hw->mac.addr[0], hw->mac.addr[1],
766 DEBUGOUT("%.2X %.2X %.2X\n", hw->mac.addr[3],
767 hw->mac.addr[4], hw->mac.addr[5]);
769 hw->mac.set_rar(hw, 0, hw->mac.addr, 0, true);
772 /* clear VMDq pool/queue selection for RAR 0 */
773 hw->mac.clear_vmdq(hw, 0, BIT_MASK32);
775 hw->addr_ctrl.overflow_promisc = 0;
777 hw->addr_ctrl.rar_used_count = 1;
779 /* Zero out the other receive addresses. */
780 DEBUGOUT("Clearing RAR[1-%d]\n", rar_entries - 1);
781 for (i = 1; i < rar_entries; i++) {
782 wr32(hw, TXGBE_ETHADDRIDX, i);
783 wr32(hw, TXGBE_ETHADDRL, 0);
784 wr32(hw, TXGBE_ETHADDRH, 0);
788 hw->addr_ctrl.mta_in_use = 0;
789 psrctl = rd32(hw, TXGBE_PSRCTL);
790 psrctl &= ~(TXGBE_PSRCTL_ADHF12_MASK | TXGBE_PSRCTL_MCHFENA);
791 psrctl |= TXGBE_PSRCTL_ADHF12(hw->mac.mc_filter_type);
792 wr32(hw, TXGBE_PSRCTL, psrctl);
794 DEBUGOUT(" Clearing MTA\n");
795 for (i = 0; i < hw->mac.mcft_size; i++)
796 wr32(hw, TXGBE_MCADDRTBL(i), 0);
798 txgbe_init_uta_tables(hw);
804 * txgbe_mta_vector - Determines bit-vector in multicast table to set
805 * @hw: pointer to hardware structure
806 * @mc_addr: the multicast address
808 * Extracts the 12 bits, from a multicast address, to determine which
809 * bit-vector to set in the multicast table. The hardware uses 12 bits, from
810 * incoming rx multicast addresses, to determine the bit-vector to check in
811 * the MTA. Which of the 4 combination, of 12-bits, the hardware uses is set
812 * by the MO field of the PSRCTRL. The MO field is set during initialization
815 static s32 txgbe_mta_vector(struct txgbe_hw *hw, u8 *mc_addr)
819 DEBUGFUNC("txgbe_mta_vector");
821 switch (hw->mac.mc_filter_type) {
822 case 0: /* use bits [47:36] of the address */
823 vector = ((mc_addr[4] >> 4) | (((u16)mc_addr[5]) << 4));
825 case 1: /* use bits [46:35] of the address */
826 vector = ((mc_addr[4] >> 3) | (((u16)mc_addr[5]) << 5));
828 case 2: /* use bits [45:34] of the address */
829 vector = ((mc_addr[4] >> 2) | (((u16)mc_addr[5]) << 6));
831 case 3: /* use bits [43:32] of the address */
832 vector = ((mc_addr[4]) | (((u16)mc_addr[5]) << 8));
834 default: /* Invalid mc_filter_type */
835 DEBUGOUT("MC filter type param set incorrectly\n");
840 /* vector can only be 12-bits or boundary will be exceeded */
846 * txgbe_set_mta - Set bit-vector in multicast table
847 * @hw: pointer to hardware structure
848 * @mc_addr: Multicast address
850 * Sets the bit-vector in the multicast table.
852 void txgbe_set_mta(struct txgbe_hw *hw, u8 *mc_addr)
858 DEBUGFUNC("txgbe_set_mta");
860 hw->addr_ctrl.mta_in_use++;
862 vector = txgbe_mta_vector(hw, mc_addr);
863 DEBUGOUT(" bit-vector = 0x%03X\n", vector);
866 * The MTA is a register array of 128 32-bit registers. It is treated
867 * like an array of 4096 bits. We want to set bit
868 * BitArray[vector_value]. So we figure out what register the bit is
869 * in, read it, OR in the new bit, then write back the new value. The
870 * register is determined by the upper 7 bits of the vector value and
871 * the bit within that register are determined by the lower 5 bits of
874 vector_reg = (vector >> 5) & 0x7F;
875 vector_bit = vector & 0x1F;
876 hw->mac.mta_shadow[vector_reg] |= (1 << vector_bit);
880 * txgbe_update_mc_addr_list - Updates MAC list of multicast addresses
881 * @hw: pointer to hardware structure
882 * @mc_addr_list: the list of new multicast addresses
883 * @mc_addr_count: number of addresses
884 * @next: iterator function to walk the multicast address list
885 * @clear: flag, when set clears the table beforehand
887 * When the clear flag is set, the given list replaces any existing list.
888 * Hashes the given addresses into the multicast table.
890 s32 txgbe_update_mc_addr_list(struct txgbe_hw *hw, u8 *mc_addr_list,
891 u32 mc_addr_count, txgbe_mc_addr_itr next,
897 DEBUGFUNC("txgbe_update_mc_addr_list");
900 * Set the new number of MC addresses that we are being requested to
903 hw->addr_ctrl.num_mc_addrs = mc_addr_count;
904 hw->addr_ctrl.mta_in_use = 0;
906 /* Clear mta_shadow */
908 DEBUGOUT(" Clearing MTA\n");
909 memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow));
912 /* Update mta_shadow */
913 for (i = 0; i < mc_addr_count; i++) {
914 DEBUGOUT(" Adding the multicast addresses:\n");
915 txgbe_set_mta(hw, next(hw, &mc_addr_list, &vmdq));
919 for (i = 0; i < hw->mac.mcft_size; i++)
920 wr32a(hw, TXGBE_MCADDRTBL(0), i,
921 hw->mac.mta_shadow[i]);
923 if (hw->addr_ctrl.mta_in_use > 0) {
924 u32 psrctl = rd32(hw, TXGBE_PSRCTL);
925 psrctl &= ~(TXGBE_PSRCTL_ADHF12_MASK | TXGBE_PSRCTL_MCHFENA);
926 psrctl |= TXGBE_PSRCTL_MCHFENA |
927 TXGBE_PSRCTL_ADHF12(hw->mac.mc_filter_type);
928 wr32(hw, TXGBE_PSRCTL, psrctl);
931 DEBUGOUT("txgbe update mc addr list complete\n");
936 * txgbe_fc_enable - Enable flow control
937 * @hw: pointer to hardware structure
939 * Enable flow control according to the current settings.
941 s32 txgbe_fc_enable(struct txgbe_hw *hw)
944 u32 mflcn_reg, fccfg_reg;
949 DEBUGFUNC("txgbe_fc_enable");
951 /* Validate the water mark configuration */
952 if (!hw->fc.pause_time) {
953 err = TXGBE_ERR_INVALID_LINK_SETTINGS;
957 /* Low water mark of zero causes XOFF floods */
958 for (i = 0; i < TXGBE_DCB_TC_MAX; i++) {
959 if ((hw->fc.current_mode & txgbe_fc_tx_pause) &&
960 hw->fc.high_water[i]) {
961 if (!hw->fc.low_water[i] ||
962 hw->fc.low_water[i] >= hw->fc.high_water[i]) {
963 DEBUGOUT("Invalid water mark configuration\n");
964 err = TXGBE_ERR_INVALID_LINK_SETTINGS;
970 /* Negotiate the fc mode to use */
971 hw->mac.fc_autoneg(hw);
973 /* Disable any previous flow control settings */
974 mflcn_reg = rd32(hw, TXGBE_RXFCCFG);
975 mflcn_reg &= ~(TXGBE_RXFCCFG_FC | TXGBE_RXFCCFG_PFC);
977 fccfg_reg = rd32(hw, TXGBE_TXFCCFG);
978 fccfg_reg &= ~(TXGBE_TXFCCFG_FC | TXGBE_TXFCCFG_PFC);
981 * The possible values of fc.current_mode are:
982 * 0: Flow control is completely disabled
983 * 1: Rx flow control is enabled (we can receive pause frames,
984 * but not send pause frames).
985 * 2: Tx flow control is enabled (we can send pause frames but
986 * we do not support receiving pause frames).
987 * 3: Both Rx and Tx flow control (symmetric) are enabled.
990 switch (hw->fc.current_mode) {
993 * Flow control is disabled by software override or autoneg.
994 * The code below will actually disable it in the HW.
997 case txgbe_fc_rx_pause:
999 * Rx Flow control is enabled and Tx Flow control is
1000 * disabled by software override. Since there really
1001 * isn't a way to advertise that we are capable of RX
1002 * Pause ONLY, we will advertise that we support both
1003 * symmetric and asymmetric Rx PAUSE. Later, we will
1004 * disable the adapter's ability to send PAUSE frames.
1006 mflcn_reg |= TXGBE_RXFCCFG_FC;
1008 case txgbe_fc_tx_pause:
1010 * Tx Flow control is enabled, and Rx Flow control is
1011 * disabled by software override.
1013 fccfg_reg |= TXGBE_TXFCCFG_FC;
1016 /* Flow control (both Rx and Tx) is enabled by SW override. */
1017 mflcn_reg |= TXGBE_RXFCCFG_FC;
1018 fccfg_reg |= TXGBE_TXFCCFG_FC;
1021 DEBUGOUT("Flow control param set incorrectly\n");
1022 err = TXGBE_ERR_CONFIG;
1026 /* Set 802.3x based flow control settings. */
1027 wr32(hw, TXGBE_RXFCCFG, mflcn_reg);
1028 wr32(hw, TXGBE_TXFCCFG, fccfg_reg);
1030 /* Set up and enable Rx high/low water mark thresholds, enable XON. */
1031 for (i = 0; i < TXGBE_DCB_TC_MAX; i++) {
1032 if ((hw->fc.current_mode & txgbe_fc_tx_pause) &&
1033 hw->fc.high_water[i]) {
1034 fcrtl = TXGBE_FCWTRLO_TH(hw->fc.low_water[i]) |
1036 fcrth = TXGBE_FCWTRHI_TH(hw->fc.high_water[i]) |
1040 * In order to prevent Tx hangs when the internal Tx
1041 * switch is enabled we must set the high water mark
1042 * to the Rx packet buffer size - 24KB. This allows
1043 * the Tx switch to function even under heavy Rx
1047 fcrth = rd32(hw, TXGBE_PBRXSIZE(i)) - 24576;
1049 wr32(hw, TXGBE_FCWTRLO(i), fcrtl);
1050 wr32(hw, TXGBE_FCWTRHI(i), fcrth);
1053 /* Configure pause time (2 TCs per register) */
1054 pause_time = TXGBE_RXFCFSH_TIME(hw->fc.pause_time);
1055 for (i = 0; i < (TXGBE_DCB_TC_MAX / 2); i++)
1056 wr32(hw, TXGBE_FCXOFFTM(i), pause_time * 0x00010001);
1058 /* Configure flow control refresh threshold value */
1059 wr32(hw, TXGBE_RXFCRFSH, hw->fc.pause_time / 2);
1066 * txgbe_negotiate_fc - Negotiate flow control
1067 * @hw: pointer to hardware structure
1068 * @adv_reg: flow control advertised settings
1069 * @lp_reg: link partner's flow control settings
1070 * @adv_sym: symmetric pause bit in advertisement
1071 * @adv_asm: asymmetric pause bit in advertisement
1072 * @lp_sym: symmetric pause bit in link partner advertisement
1073 * @lp_asm: asymmetric pause bit in link partner advertisement
1075 * Find the intersection between advertised settings and link partner's
1076 * advertised settings
1078 s32 txgbe_negotiate_fc(struct txgbe_hw *hw, u32 adv_reg, u32 lp_reg,
1079 u32 adv_sym, u32 adv_asm, u32 lp_sym, u32 lp_asm)
1081 if ((!(adv_reg)) || (!(lp_reg))) {
1082 DEBUGOUT("Local or link partner's advertised flow control "
1083 "settings are NULL. Local: %x, link partner: %x\n",
1085 return TXGBE_ERR_FC_NOT_NEGOTIATED;
1088 if ((adv_reg & adv_sym) && (lp_reg & lp_sym)) {
1090 * Now we need to check if the user selected Rx ONLY
1091 * of pause frames. In this case, we had to advertise
1092 * FULL flow control because we could not advertise RX
1093 * ONLY. Hence, we must now check to see if we need to
1094 * turn OFF the TRANSMISSION of PAUSE frames.
1096 if (hw->fc.requested_mode == txgbe_fc_full) {
1097 hw->fc.current_mode = txgbe_fc_full;
1098 DEBUGOUT("Flow Control = FULL.\n");
1100 hw->fc.current_mode = txgbe_fc_rx_pause;
1101 DEBUGOUT("Flow Control=RX PAUSE frames only\n");
1103 } else if (!(adv_reg & adv_sym) && (adv_reg & adv_asm) &&
1104 (lp_reg & lp_sym) && (lp_reg & lp_asm)) {
1105 hw->fc.current_mode = txgbe_fc_tx_pause;
1106 DEBUGOUT("Flow Control = TX PAUSE frames only.\n");
1107 } else if ((adv_reg & adv_sym) && (adv_reg & adv_asm) &&
1108 !(lp_reg & lp_sym) && (lp_reg & lp_asm)) {
1109 hw->fc.current_mode = txgbe_fc_rx_pause;
1110 DEBUGOUT("Flow Control = RX PAUSE frames only.\n");
1112 hw->fc.current_mode = txgbe_fc_none;
1113 DEBUGOUT("Flow Control = NONE.\n");
1119 * txgbe_fc_autoneg_fiber - Enable flow control on 1 gig fiber
1120 * @hw: pointer to hardware structure
1122 * Enable flow control according on 1 gig fiber.
1124 STATIC s32 txgbe_fc_autoneg_fiber(struct txgbe_hw *hw)
1126 u32 pcs_anadv_reg, pcs_lpab_reg;
1127 s32 err = TXGBE_ERR_FC_NOT_NEGOTIATED;
1130 * On multispeed fiber at 1g, bail out if
1131 * - link is up but AN did not complete, or if
1132 * - link is up and AN completed but timed out
1135 pcs_anadv_reg = rd32_epcs(hw, SR_MII_MMD_AN_ADV);
1136 pcs_lpab_reg = rd32_epcs(hw, SR_MII_MMD_LP_BABL);
1138 err = txgbe_negotiate_fc(hw, pcs_anadv_reg,
1140 SR_MII_MMD_AN_ADV_PAUSE_SYM,
1141 SR_MII_MMD_AN_ADV_PAUSE_ASM,
1142 SR_MII_MMD_AN_ADV_PAUSE_SYM,
1143 SR_MII_MMD_AN_ADV_PAUSE_ASM);
1149 * txgbe_fc_autoneg_backplane - Enable flow control IEEE clause 37
1150 * @hw: pointer to hardware structure
1152 * Enable flow control according to IEEE clause 37.
1154 STATIC s32 txgbe_fc_autoneg_backplane(struct txgbe_hw *hw)
1156 u32 anlp1_reg, autoc_reg;
1157 s32 err = TXGBE_ERR_FC_NOT_NEGOTIATED;
1160 * Read the 10g AN autoc and LP ability registers and resolve
1161 * local flow control settings accordingly
1163 autoc_reg = rd32_epcs(hw, SR_AN_MMD_ADV_REG1);
1164 anlp1_reg = rd32_epcs(hw, SR_AN_MMD_LP_ABL1);
1166 err = txgbe_negotiate_fc(hw, autoc_reg,
1168 SR_AN_MMD_ADV_REG1_PAUSE_SYM,
1169 SR_AN_MMD_ADV_REG1_PAUSE_ASM,
1170 SR_AN_MMD_ADV_REG1_PAUSE_SYM,
1171 SR_AN_MMD_ADV_REG1_PAUSE_ASM);
1177 * txgbe_fc_autoneg_copper - Enable flow control IEEE clause 37
1178 * @hw: pointer to hardware structure
1180 * Enable flow control according to IEEE clause 37.
1182 STATIC s32 txgbe_fc_autoneg_copper(struct txgbe_hw *hw)
1184 u16 technology_ability_reg = 0;
1185 u16 lp_technology_ability_reg = 0;
1187 hw->phy.read_reg(hw, TXGBE_MD_AUTO_NEG_ADVT,
1188 TXGBE_MD_DEV_AUTO_NEG,
1189 &technology_ability_reg);
1190 hw->phy.read_reg(hw, TXGBE_MD_AUTO_NEG_LP,
1191 TXGBE_MD_DEV_AUTO_NEG,
1192 &lp_technology_ability_reg);
1194 return txgbe_negotiate_fc(hw, (u32)technology_ability_reg,
1195 (u32)lp_technology_ability_reg,
1196 TXGBE_TAF_SYM_PAUSE, TXGBE_TAF_ASM_PAUSE,
1197 TXGBE_TAF_SYM_PAUSE, TXGBE_TAF_ASM_PAUSE);
1201 * txgbe_fc_autoneg - Configure flow control
1202 * @hw: pointer to hardware structure
1204 * Compares our advertised flow control capabilities to those advertised by
1205 * our link partner, and determines the proper flow control mode to use.
1207 void txgbe_fc_autoneg(struct txgbe_hw *hw)
1209 s32 err = TXGBE_ERR_FC_NOT_NEGOTIATED;
1213 DEBUGFUNC("txgbe_fc_autoneg");
1216 * AN should have completed when the cable was plugged in.
1217 * Look for reasons to bail out. Bail out if:
1218 * - FC autoneg is disabled, or if
1221 if (hw->fc.disable_fc_autoneg) {
1222 DEBUGOUT("Flow control autoneg is disabled");
1226 hw->mac.check_link(hw, &speed, &link_up, false);
1228 DEBUGOUT("The link is down");
1232 switch (hw->phy.media_type) {
1233 /* Autoneg flow control on fiber adapters */
1234 case txgbe_media_type_fiber_qsfp:
1235 case txgbe_media_type_fiber:
1236 if (speed == TXGBE_LINK_SPEED_1GB_FULL)
1237 err = txgbe_fc_autoneg_fiber(hw);
1240 /* Autoneg flow control on backplane adapters */
1241 case txgbe_media_type_backplane:
1242 err = txgbe_fc_autoneg_backplane(hw);
1245 /* Autoneg flow control on copper adapters */
1246 case txgbe_media_type_copper:
1247 if (txgbe_device_supports_autoneg_fc(hw))
1248 err = txgbe_fc_autoneg_copper(hw);
1257 hw->fc.fc_was_autonegged = true;
1259 hw->fc.fc_was_autonegged = false;
1260 hw->fc.current_mode = hw->fc.requested_mode;
1265 * txgbe_acquire_swfw_sync - Acquire SWFW semaphore
1266 * @hw: pointer to hardware structure
1267 * @mask: Mask to specify which semaphore to acquire
1269 * Acquires the SWFW semaphore through the MNGSEM register for the specified
1270 * function (CSR, PHY0, PHY1, EEPROM, Flash)
1272 s32 txgbe_acquire_swfw_sync(struct txgbe_hw *hw, u32 mask)
1275 u32 swmask = TXGBE_MNGSEM_SW(mask);
1276 u32 fwmask = TXGBE_MNGSEM_FW(mask);
1280 DEBUGFUNC("txgbe_acquire_swfw_sync");
1282 for (i = 0; i < timeout; i++) {
1284 * SW NVM semaphore bit is used for access to all
1285 * SW_FW_SYNC bits (not just NVM)
1287 if (txgbe_get_eeprom_semaphore(hw))
1288 return TXGBE_ERR_SWFW_SYNC;
1290 mngsem = rd32(hw, TXGBE_MNGSEM);
1291 if (mngsem & (fwmask | swmask)) {
1292 /* Resource is currently in use by FW or SW */
1293 txgbe_release_eeprom_semaphore(hw);
1297 wr32(hw, TXGBE_MNGSEM, mngsem);
1298 txgbe_release_eeprom_semaphore(hw);
1303 /* If time expired clear the bits holding the lock and retry */
1304 if (mngsem & (fwmask | swmask))
1305 txgbe_release_swfw_sync(hw, mngsem & (fwmask | swmask));
1308 return TXGBE_ERR_SWFW_SYNC;
1312 * txgbe_release_swfw_sync - Release SWFW semaphore
1313 * @hw: pointer to hardware structure
1314 * @mask: Mask to specify which semaphore to release
1316 * Releases the SWFW semaphore through the MNGSEM register for the specified
1317 * function (CSR, PHY0, PHY1, EEPROM, Flash)
1319 void txgbe_release_swfw_sync(struct txgbe_hw *hw, u32 mask)
1324 DEBUGFUNC("txgbe_release_swfw_sync");
1326 txgbe_get_eeprom_semaphore(hw);
1328 mngsem = rd32(hw, TXGBE_MNGSEM);
1330 wr32(hw, TXGBE_MNGSEM, mngsem);
1332 txgbe_release_eeprom_semaphore(hw);
1336 * txgbe_disable_sec_rx_path - Stops the receive data path
1337 * @hw: pointer to hardware structure
1339 * Stops the receive data path and waits for the HW to internally empty
1340 * the Rx security block
1342 s32 txgbe_disable_sec_rx_path(struct txgbe_hw *hw)
1344 #define TXGBE_MAX_SECRX_POLL 4000
1349 DEBUGFUNC("txgbe_disable_sec_rx_path");
1351 secrxreg = rd32(hw, TXGBE_SECRXCTL);
1352 secrxreg |= TXGBE_SECRXCTL_XDSA;
1353 wr32(hw, TXGBE_SECRXCTL, secrxreg);
1354 for (i = 0; i < TXGBE_MAX_SECRX_POLL; i++) {
1355 secrxreg = rd32(hw, TXGBE_SECRXSTAT);
1356 if (!(secrxreg & TXGBE_SECRXSTAT_RDY))
1357 /* Use interrupt-safe sleep just in case */
1363 /* For informational purposes only */
1364 if (i >= TXGBE_MAX_SECRX_POLL)
1365 DEBUGOUT("Rx unit being enabled before security "
1366 "path fully disabled. Continuing with init.\n");
1372 * txgbe_enable_sec_rx_path - Enables the receive data path
1373 * @hw: pointer to hardware structure
1375 * Enables the receive data path.
1377 s32 txgbe_enable_sec_rx_path(struct txgbe_hw *hw)
1381 DEBUGFUNC("txgbe_enable_sec_rx_path");
1383 secrxreg = rd32(hw, TXGBE_SECRXCTL);
1384 secrxreg &= ~TXGBE_SECRXCTL_XDSA;
1385 wr32(hw, TXGBE_SECRXCTL, secrxreg);
1392 * txgbe_disable_sec_tx_path - Stops the transmit data path
1393 * @hw: pointer to hardware structure
1395 * Stops the transmit data path and waits for the HW to internally empty
1396 * the Tx security block
1398 int txgbe_disable_sec_tx_path(struct txgbe_hw *hw)
1400 #define TXGBE_MAX_SECTX_POLL 40
1405 sectxreg = rd32(hw, TXGBE_SECTXCTL);
1406 sectxreg |= TXGBE_SECTXCTL_XDSA;
1407 wr32(hw, TXGBE_SECTXCTL, sectxreg);
1408 for (i = 0; i < TXGBE_MAX_SECTX_POLL; i++) {
1409 sectxreg = rd32(hw, TXGBE_SECTXSTAT);
1410 if (sectxreg & TXGBE_SECTXSTAT_RDY)
1412 /* Use interrupt-safe sleep just in case */
1416 /* For informational purposes only */
1417 if (i >= TXGBE_MAX_SECTX_POLL)
1418 PMD_DRV_LOG(DEBUG, "Tx unit being enabled before security "
1419 "path fully disabled. Continuing with init.");
1425 * txgbe_enable_sec_tx_path - Enables the transmit data path
1426 * @hw: pointer to hardware structure
1428 * Enables the transmit data path.
1430 int txgbe_enable_sec_tx_path(struct txgbe_hw *hw)
1434 sectxreg = rd32(hw, TXGBE_SECTXCTL);
1435 sectxreg &= ~TXGBE_SECTXCTL_XDSA;
1436 wr32(hw, TXGBE_SECTXCTL, sectxreg);
1443 * txgbe_get_san_mac_addr_offset - Get SAN MAC address offset from the EEPROM
1444 * @hw: pointer to hardware structure
1445 * @san_mac_offset: SAN MAC address offset
1447 * This function will read the EEPROM location for the SAN MAC address
1448 * pointer, and returns the value at that location. This is used in both
1449 * get and set mac_addr routines.
1451 static s32 txgbe_get_san_mac_addr_offset(struct txgbe_hw *hw,
1452 u16 *san_mac_offset)
1456 DEBUGFUNC("txgbe_get_san_mac_addr_offset");
1459 * First read the EEPROM pointer to see if the MAC addresses are
1462 err = hw->rom.readw_sw(hw, TXGBE_SAN_MAC_ADDR_PTR,
1465 DEBUGOUT("eeprom at offset %d failed",
1466 TXGBE_SAN_MAC_ADDR_PTR);
1473 * txgbe_get_san_mac_addr - SAN MAC address retrieval from the EEPROM
1474 * @hw: pointer to hardware structure
1475 * @san_mac_addr: SAN MAC address
1477 * Reads the SAN MAC address from the EEPROM, if it's available. This is
1478 * per-port, so set_lan_id() must be called before reading the addresses.
1479 * set_lan_id() is called by identify_sfp(), but this cannot be relied
1480 * upon for non-SFP connections, so we must call it here.
1482 s32 txgbe_get_san_mac_addr(struct txgbe_hw *hw, u8 *san_mac_addr)
1484 u16 san_mac_data, san_mac_offset;
1488 DEBUGFUNC("txgbe_get_san_mac_addr");
1491 * First read the EEPROM pointer to see if the MAC addresses are
1492 * available. If they're not, no point in calling set_lan_id() here.
1494 err = txgbe_get_san_mac_addr_offset(hw, &san_mac_offset);
1495 if (err || san_mac_offset == 0 || san_mac_offset == 0xFFFF)
1496 goto san_mac_addr_out;
1498 /* apply the port offset to the address offset */
1499 (hw->bus.func) ? (san_mac_offset += TXGBE_SAN_MAC_ADDR_PORT1_OFFSET) :
1500 (san_mac_offset += TXGBE_SAN_MAC_ADDR_PORT0_OFFSET);
1501 for (i = 0; i < 3; i++) {
1502 err = hw->rom.read16(hw, san_mac_offset,
1505 DEBUGOUT("eeprom read at offset %d failed",
1507 goto san_mac_addr_out;
1509 san_mac_addr[i * 2] = (u8)(san_mac_data);
1510 san_mac_addr[i * 2 + 1] = (u8)(san_mac_data >> 8);
1517 * No addresses available in this EEPROM. It's not an
1518 * error though, so just wipe the local address and return.
1520 for (i = 0; i < 6; i++)
1521 san_mac_addr[i] = 0xFF;
1526 * txgbe_set_san_mac_addr - Write the SAN MAC address to the EEPROM
1527 * @hw: pointer to hardware structure
1528 * @san_mac_addr: SAN MAC address
1530 * Write a SAN MAC address to the EEPROM.
1532 s32 txgbe_set_san_mac_addr(struct txgbe_hw *hw, u8 *san_mac_addr)
1535 u16 san_mac_data, san_mac_offset;
1538 DEBUGFUNC("txgbe_set_san_mac_addr");
1540 /* Look for SAN mac address pointer. If not defined, return */
1541 err = txgbe_get_san_mac_addr_offset(hw, &san_mac_offset);
1542 if (err || san_mac_offset == 0 || san_mac_offset == 0xFFFF)
1543 return TXGBE_ERR_NO_SAN_ADDR_PTR;
1545 /* Apply the port offset to the address offset */
1546 (hw->bus.func) ? (san_mac_offset += TXGBE_SAN_MAC_ADDR_PORT1_OFFSET) :
1547 (san_mac_offset += TXGBE_SAN_MAC_ADDR_PORT0_OFFSET);
1549 for (i = 0; i < 3; i++) {
1550 san_mac_data = (u16)((u16)(san_mac_addr[i * 2 + 1]) << 8);
1551 san_mac_data |= (u16)(san_mac_addr[i * 2]);
1552 hw->rom.write16(hw, san_mac_offset, san_mac_data);
1560 * txgbe_clear_vmdq - Disassociate a VMDq pool index from a rx address
1561 * @hw: pointer to hardware struct
1562 * @rar: receive address register index to disassociate
1563 * @vmdq: VMDq pool index to remove from the rar
1565 s32 txgbe_clear_vmdq(struct txgbe_hw *hw, u32 rar, u32 vmdq)
1567 u32 mpsar_lo, mpsar_hi;
1568 u32 rar_entries = hw->mac.num_rar_entries;
1570 DEBUGFUNC("txgbe_clear_vmdq");
1572 /* Make sure we are using a valid rar index range */
1573 if (rar >= rar_entries) {
1574 DEBUGOUT("RAR index %d is out of range.\n", rar);
1575 return TXGBE_ERR_INVALID_ARGUMENT;
1578 wr32(hw, TXGBE_ETHADDRIDX, rar);
1579 mpsar_lo = rd32(hw, TXGBE_ETHADDRASSL);
1580 mpsar_hi = rd32(hw, TXGBE_ETHADDRASSH);
1582 if (TXGBE_REMOVED(hw->hw_addr))
1585 if (!mpsar_lo && !mpsar_hi)
1588 if (vmdq == BIT_MASK32) {
1590 wr32(hw, TXGBE_ETHADDRASSL, 0);
1594 wr32(hw, TXGBE_ETHADDRASSH, 0);
1597 } else if (vmdq < 32) {
1598 mpsar_lo &= ~(1 << vmdq);
1599 wr32(hw, TXGBE_ETHADDRASSL, mpsar_lo);
1601 mpsar_hi &= ~(1 << (vmdq - 32));
1602 wr32(hw, TXGBE_ETHADDRASSH, mpsar_hi);
1605 /* was that the last pool using this rar? */
1606 if (mpsar_lo == 0 && mpsar_hi == 0 &&
1607 rar != 0 && rar != hw->mac.san_mac_rar_index)
1608 hw->mac.clear_rar(hw, rar);
1614 * txgbe_set_vmdq - Associate a VMDq pool index with a rx address
1615 * @hw: pointer to hardware struct
1616 * @rar: receive address register index to associate with a VMDq index
1617 * @vmdq: VMDq pool index
1619 s32 txgbe_set_vmdq(struct txgbe_hw *hw, u32 rar, u32 vmdq)
1622 u32 rar_entries = hw->mac.num_rar_entries;
1624 DEBUGFUNC("txgbe_set_vmdq");
1626 /* Make sure we are using a valid rar index range */
1627 if (rar >= rar_entries) {
1628 DEBUGOUT("RAR index %d is out of range.\n", rar);
1629 return TXGBE_ERR_INVALID_ARGUMENT;
1632 wr32(hw, TXGBE_ETHADDRIDX, rar);
1634 mpsar = rd32(hw, TXGBE_ETHADDRASSL);
1636 wr32(hw, TXGBE_ETHADDRASSL, mpsar);
1638 mpsar = rd32(hw, TXGBE_ETHADDRASSH);
1639 mpsar |= 1 << (vmdq - 32);
1640 wr32(hw, TXGBE_ETHADDRASSH, mpsar);
1646 * txgbe_init_uta_tables - Initialize the Unicast Table Array
1647 * @hw: pointer to hardware structure
1649 s32 txgbe_init_uta_tables(struct txgbe_hw *hw)
1653 DEBUGFUNC("txgbe_init_uta_tables");
1654 DEBUGOUT(" Clearing UTA\n");
1656 for (i = 0; i < 128; i++)
1657 wr32(hw, TXGBE_UCADDRTBL(i), 0);
1663 * txgbe_find_vlvf_slot - find the vlanid or the first empty slot
1664 * @hw: pointer to hardware structure
1665 * @vlan: VLAN id to write to VLAN filter
1666 * @vlvf_bypass: true to find vlanid only, false returns first empty slot if
1670 * return the VLVF index where this VLAN id should be placed
1673 s32 txgbe_find_vlvf_slot(struct txgbe_hw *hw, u32 vlan, bool vlvf_bypass)
1675 s32 regindex, first_empty_slot;
1678 /* short cut the special case */
1682 /* if vlvf_bypass is set we don't want to use an empty slot, we
1683 * will simply bypass the VLVF if there are no entries present in the
1684 * VLVF that contain our VLAN
1686 first_empty_slot = vlvf_bypass ? TXGBE_ERR_NO_SPACE : 0;
1688 /* add VLAN enable bit for comparison */
1689 vlan |= TXGBE_PSRVLAN_EA;
1691 /* Search for the vlan id in the VLVF entries. Save off the first empty
1692 * slot found along the way.
1694 * pre-decrement loop covering (TXGBE_NUM_POOL - 1) .. 1
1696 for (regindex = TXGBE_NUM_POOL; --regindex;) {
1697 wr32(hw, TXGBE_PSRVLANIDX, regindex);
1698 bits = rd32(hw, TXGBE_PSRVLAN);
1701 if (!first_empty_slot && !bits)
1702 first_empty_slot = regindex;
1705 /* If we are here then we didn't find the VLAN. Return first empty
1706 * slot we found during our search, else error.
1708 if (!first_empty_slot)
1709 DEBUGOUT("No space in VLVF.\n");
1711 return first_empty_slot ? first_empty_slot : TXGBE_ERR_NO_SPACE;
1715 * txgbe_set_vfta - Set VLAN filter table
1716 * @hw: pointer to hardware structure
1717 * @vlan: VLAN id to write to VLAN filter
1718 * @vind: VMDq output index that maps queue to VLAN id in VLVFB
1719 * @vlan_on: boolean flag to turn on/off VLAN
1720 * @vlvf_bypass: boolean flag indicating updating default pool is okay
1722 * Turn on/off specified VLAN in the VLAN filter table.
1724 s32 txgbe_set_vfta(struct txgbe_hw *hw, u32 vlan, u32 vind,
1725 bool vlan_on, bool vlvf_bypass)
1727 u32 regidx, vfta_delta, vfta;
1730 DEBUGFUNC("txgbe_set_vfta");
1732 if (vlan > 4095 || vind > 63)
1733 return TXGBE_ERR_PARAM;
1736 * this is a 2 part operation - first the VFTA, then the
1737 * VLVF and VLVFB if VT Mode is set
1738 * We don't write the VFTA until we know the VLVF part succeeded.
1742 * The VFTA is a bitstring made up of 128 32-bit registers
1743 * that enable the particular VLAN id, much like the MTA:
1744 * bits[11-5]: which register
1745 * bits[4-0]: which bit in the register
1748 vfta_delta = 1 << (vlan % 32);
1749 vfta = rd32(hw, TXGBE_VLANTBL(regidx));
1752 * vfta_delta represents the difference between the current value
1753 * of vfta and the value we want in the register. Since the diff
1754 * is an XOR mask we can just update the vfta using an XOR
1756 vfta_delta &= vlan_on ? ~vfta : vfta;
1760 * Call txgbe_set_vlvf to set VLVFB and VLVF
1762 err = txgbe_set_vlvf(hw, vlan, vind, vlan_on, &vfta_delta,
1771 /* Update VFTA now that we are ready for traffic */
1773 wr32(hw, TXGBE_VLANTBL(regidx), vfta);
1779 * txgbe_set_vlvf - Set VLAN Pool Filter
1780 * @hw: pointer to hardware structure
1781 * @vlan: VLAN id to write to VLAN filter
1782 * @vind: VMDq output index that maps queue to VLAN id in PSRVLANPLM
1783 * @vlan_on: boolean flag to turn on/off VLAN in PSRVLAN
1784 * @vfta_delta: pointer to the difference between the current value
1785 * of PSRVLANPLM and the desired value
1786 * @vfta: the desired value of the VFTA
1787 * @vlvf_bypass: boolean flag indicating updating default pool is okay
1789 * Turn on/off specified bit in VLVF table.
1791 s32 txgbe_set_vlvf(struct txgbe_hw *hw, u32 vlan, u32 vind,
1792 bool vlan_on, u32 *vfta_delta, u32 vfta,
1799 DEBUGFUNC("txgbe_set_vlvf");
1801 if (vlan > 4095 || vind > 63)
1802 return TXGBE_ERR_PARAM;
1804 /* If VT Mode is set
1806 * make sure the vlan is in PSRVLAN
1807 * set the vind bit in the matching PSRVLANPLM
1809 * clear the pool bit and possibly the vind
1811 portctl = rd32(hw, TXGBE_PORTCTL);
1812 if (!(portctl & TXGBE_PORTCTL_NUMVT_MASK))
1815 vlvf_index = txgbe_find_vlvf_slot(hw, vlan, vlvf_bypass);
1819 wr32(hw, TXGBE_PSRVLANIDX, vlvf_index);
1820 bits = rd32(hw, TXGBE_PSRVLANPLM(vind / 32));
1822 /* set the pool bit */
1823 bits |= 1 << (vind % 32);
1827 /* clear the pool bit */
1828 bits ^= 1 << (vind % 32);
1831 !rd32(hw, TXGBE_PSRVLANPLM(vind / 32))) {
1832 /* Clear PSRVLANPLM first, then disable PSRVLAN. Otherwise
1833 * we run the risk of stray packets leaking into
1834 * the PF via the default pool
1837 wr32(hw, TXGBE_PSRVLANPLM(vlan / 32), vfta);
1839 /* disable VLVF and clear remaining bit from pool */
1840 wr32(hw, TXGBE_PSRVLAN, 0);
1841 wr32(hw, TXGBE_PSRVLANPLM(vind / 32), 0);
1846 /* If there are still bits set in the PSRVLANPLM registers
1847 * for the VLAN ID indicated we need to see if the
1848 * caller is requesting that we clear the PSRVLANPLM entry bit.
1849 * If the caller has requested that we clear the PSRVLANPLM
1850 * entry bit but there are still pools/VFs using this VLAN
1851 * ID entry then ignore the request. We're not worried
1852 * about the case where we're turning the PSRVLANPLM VLAN ID
1853 * entry bit on, only when requested to turn it off as
1854 * there may be multiple pools and/or VFs using the
1855 * VLAN ID entry. In that case we cannot clear the
1856 * PSRVLANPLM bit until all pools/VFs using that VLAN ID have also
1857 * been cleared. This will be indicated by "bits" being
1863 /* record pool change and enable VLAN ID if not already enabled */
1864 wr32(hw, TXGBE_PSRVLANPLM(vind / 32), bits);
1865 wr32(hw, TXGBE_PSRVLAN, TXGBE_PSRVLAN_EA | vlan);
1871 * txgbe_clear_vfta - Clear VLAN filter table
1872 * @hw: pointer to hardware structure
1874 * Clears the VLAN filer table, and the VMDq index associated with the filter
1876 s32 txgbe_clear_vfta(struct txgbe_hw *hw)
1880 DEBUGFUNC("txgbe_clear_vfta");
1882 for (offset = 0; offset < hw->mac.vft_size; offset++)
1883 wr32(hw, TXGBE_VLANTBL(offset), 0);
1885 for (offset = 0; offset < TXGBE_NUM_POOL; offset++) {
1886 wr32(hw, TXGBE_PSRVLANIDX, offset);
1887 wr32(hw, TXGBE_PSRVLAN, 0);
1888 wr32(hw, TXGBE_PSRVLANPLM(0), 0);
1889 wr32(hw, TXGBE_PSRVLANPLM(1), 0);
1896 * txgbe_need_crosstalk_fix - Determine if we need to do cross talk fix
1897 * @hw: pointer to hardware structure
1899 * Contains the logic to identify if we need to verify link for the
1902 static bool txgbe_need_crosstalk_fix(struct txgbe_hw *hw)
1904 /* Does FW say we need the fix */
1905 if (!hw->need_crosstalk_fix)
1908 /* Only consider SFP+ PHYs i.e. media type fiber */
1909 switch (hw->phy.media_type) {
1910 case txgbe_media_type_fiber:
1911 case txgbe_media_type_fiber_qsfp:
1921 * txgbe_check_mac_link - Determine link and speed status
1922 * @hw: pointer to hardware structure
1923 * @speed: pointer to link speed
1924 * @link_up: true when link is up
1925 * @link_up_wait_to_complete: bool used to wait for link up or not
1927 * Reads the links register to determine if link is up and the current speed
1929 s32 txgbe_check_mac_link(struct txgbe_hw *hw, u32 *speed,
1930 bool *link_up, bool link_up_wait_to_complete)
1932 u32 links_reg, links_orig;
1935 DEBUGFUNC("txgbe_check_mac_link");
1937 /* If Crosstalk fix enabled do the sanity check of making sure
1938 * the SFP+ cage is full.
1940 if (txgbe_need_crosstalk_fix(hw)) {
1943 switch (hw->mac.type) {
1944 case txgbe_mac_raptor:
1945 sfp_cage_full = !rd32m(hw, TXGBE_GPIODATA,
1949 /* sanity check - No SFP+ devices here */
1950 sfp_cage_full = false;
1954 if (!sfp_cage_full) {
1956 *speed = TXGBE_LINK_SPEED_UNKNOWN;
1961 /* clear the old state */
1962 links_orig = rd32(hw, TXGBE_PORTSTAT);
1964 links_reg = rd32(hw, TXGBE_PORTSTAT);
1966 if (links_orig != links_reg) {
1967 DEBUGOUT("LINKS changed from %08X to %08X\n",
1968 links_orig, links_reg);
1971 if (link_up_wait_to_complete) {
1972 for (i = 0; i < hw->mac.max_link_up_time; i++) {
1973 if (!(links_reg & TXGBE_PORTSTAT_UP)) {
1980 links_reg = rd32(hw, TXGBE_PORTSTAT);
1983 if (links_reg & TXGBE_PORTSTAT_UP)
1989 switch (links_reg & TXGBE_PORTSTAT_BW_MASK) {
1990 case TXGBE_PORTSTAT_BW_10G:
1991 *speed = TXGBE_LINK_SPEED_10GB_FULL;
1993 case TXGBE_PORTSTAT_BW_1G:
1994 *speed = TXGBE_LINK_SPEED_1GB_FULL;
1996 case TXGBE_PORTSTAT_BW_100M:
1997 *speed = TXGBE_LINK_SPEED_100M_FULL;
2000 *speed = TXGBE_LINK_SPEED_UNKNOWN;
2007 * txgbe_get_wwn_prefix - Get alternative WWNN/WWPN prefix from
2009 * @hw: pointer to hardware structure
2010 * @wwnn_prefix: the alternative WWNN prefix
2011 * @wwpn_prefix: the alternative WWPN prefix
2013 * This function will read the EEPROM from the alternative SAN MAC address
2014 * block to check the support for the alternative WWNN/WWPN prefix support.
2016 s32 txgbe_get_wwn_prefix(struct txgbe_hw *hw, u16 *wwnn_prefix,
2020 u16 alt_san_mac_blk_offset;
2022 DEBUGFUNC("txgbe_get_wwn_prefix");
2024 /* clear output first */
2025 *wwnn_prefix = 0xFFFF;
2026 *wwpn_prefix = 0xFFFF;
2028 /* check if alternative SAN MAC is supported */
2029 offset = TXGBE_ALT_SAN_MAC_ADDR_BLK_PTR;
2030 if (hw->rom.readw_sw(hw, offset, &alt_san_mac_blk_offset))
2031 goto wwn_prefix_err;
2033 if (alt_san_mac_blk_offset == 0 || alt_san_mac_blk_offset == 0xFFFF)
2034 goto wwn_prefix_out;
2036 /* check capability in alternative san mac address block */
2037 offset = alt_san_mac_blk_offset + TXGBE_ALT_SAN_MAC_ADDR_CAPS_OFFSET;
2038 if (hw->rom.read16(hw, offset, &caps))
2039 goto wwn_prefix_err;
2040 if (!(caps & TXGBE_ALT_SAN_MAC_ADDR_CAPS_ALTWWN))
2041 goto wwn_prefix_out;
2043 /* get the corresponding prefix for WWNN/WWPN */
2044 offset = alt_san_mac_blk_offset + TXGBE_ALT_SAN_MAC_ADDR_WWNN_OFFSET;
2045 if (hw->rom.read16(hw, offset, wwnn_prefix))
2046 DEBUGOUT("eeprom read at offset %d failed", offset);
2048 offset = alt_san_mac_blk_offset + TXGBE_ALT_SAN_MAC_ADDR_WWPN_OFFSET;
2049 if (hw->rom.read16(hw, offset, wwpn_prefix))
2050 goto wwn_prefix_err;
2056 DEBUGOUT("eeprom read at offset %d failed", offset);
2061 * txgbe_set_mac_anti_spoofing - Enable/Disable MAC anti-spoofing
2062 * @hw: pointer to hardware structure
2063 * @enable: enable or disable switch for MAC anti-spoofing
2064 * @vf: Virtual Function pool - VF Pool to set for MAC anti-spoofing
2067 void txgbe_set_mac_anti_spoofing(struct txgbe_hw *hw, bool enable, int vf)
2069 int vf_target_reg = vf >> 3;
2070 int vf_target_shift = vf % 8;
2073 pfvfspoof = rd32(hw, TXGBE_POOLTXASMAC(vf_target_reg));
2075 pfvfspoof |= (1 << vf_target_shift);
2077 pfvfspoof &= ~(1 << vf_target_shift);
2078 wr32(hw, TXGBE_POOLTXASMAC(vf_target_reg), pfvfspoof);
2082 * txgbe_set_ethertype_anti_spoofing - Configure Ethertype anti-spoofing
2083 * @hw: pointer to hardware structure
2084 * @enable: enable or disable switch for Ethertype anti-spoofing
2085 * @vf: Virtual Function pool - VF Pool to set for Ethertype anti-spoofing
2088 void txgbe_set_ethertype_anti_spoofing(struct txgbe_hw *hw,
2089 bool enable, int vf)
2091 int vf_target_reg = vf >> 3;
2092 int vf_target_shift = vf % 8;
2095 pfvfspoof = rd32(hw, TXGBE_POOLTXASET(vf_target_reg));
2097 pfvfspoof |= (1 << vf_target_shift);
2099 pfvfspoof &= ~(1 << vf_target_shift);
2100 wr32(hw, TXGBE_POOLTXASET(vf_target_reg), pfvfspoof);
2104 * txgbe_get_device_caps - Get additional device capabilities
2105 * @hw: pointer to hardware structure
2106 * @device_caps: the EEPROM word with the extra device capabilities
2108 * This function will read the EEPROM location for the device capabilities,
2109 * and return the word through device_caps.
2111 s32 txgbe_get_device_caps(struct txgbe_hw *hw, u16 *device_caps)
2113 DEBUGFUNC("txgbe_get_device_caps");
2115 hw->rom.readw_sw(hw, TXGBE_DEVICE_CAPS, device_caps);
2121 * txgbe_set_pba - Initialize Rx packet buffer
2122 * @hw: pointer to hardware structure
2123 * @num_pb: number of packet buffers to allocate
2124 * @headroom: reserve n KB of headroom
2125 * @strategy: packet buffer allocation strategy
2127 void txgbe_set_pba(struct txgbe_hw *hw, int num_pb, u32 headroom,
2130 u32 pbsize = hw->mac.rx_pb_size;
2132 u32 rxpktsize, txpktsize, txpbthresh;
2134 UNREFERENCED_PARAMETER(hw);
2136 /* Reserve headroom */
2142 /* Divide remaining packet buffer space amongst the number of packet
2143 * buffers requested using supplied strategy.
2146 case PBA_STRATEGY_WEIGHTED:
2147 /* txgbe_dcb_pba_80_48 strategy weight first half of packet
2148 * buffer with 5/8 of the packet buffer space.
2150 rxpktsize = (pbsize * 5) / (num_pb * 4);
2151 pbsize -= rxpktsize * (num_pb / 2);
2153 for (; i < (num_pb / 2); i++)
2154 wr32(hw, TXGBE_PBRXSIZE(i), rxpktsize);
2155 /* fall through - configure remaining packet buffers */
2156 case PBA_STRATEGY_EQUAL:
2157 rxpktsize = (pbsize / (num_pb - i));
2159 for (; i < num_pb; i++)
2160 wr32(hw, TXGBE_PBRXSIZE(i), rxpktsize);
2166 /* Only support an equally distributed Tx packet buffer strategy. */
2167 txpktsize = TXGBE_PBTXSIZE_MAX / num_pb;
2168 txpbthresh = (txpktsize / 1024) - TXGBE_TXPKT_SIZE_MAX;
2169 for (i = 0; i < num_pb; i++) {
2170 wr32(hw, TXGBE_PBTXSIZE(i), txpktsize);
2171 wr32(hw, TXGBE_PBTXDMATH(i), txpbthresh);
2174 /* Clear unused TCs, if any, to zero buffer size*/
2175 for (; i < TXGBE_MAX_UP; i++) {
2176 wr32(hw, TXGBE_PBRXSIZE(i), 0);
2177 wr32(hw, TXGBE_PBTXSIZE(i), 0);
2178 wr32(hw, TXGBE_PBTXDMATH(i), 0);
2183 * txgbe_clear_tx_pending - Clear pending TX work from the PCIe fifo
2184 * @hw: pointer to the hardware structure
2186 * The MACs can experience issues if TX work is still pending
2187 * when a reset occurs. This function prevents this by flushing the PCIe
2188 * buffers on the system.
2190 void txgbe_clear_tx_pending(struct txgbe_hw *hw)
2192 u32 hlreg0, i, poll;
2195 * If double reset is not requested then all transactions should
2196 * already be clear and as such there is no work to do
2198 if (!(hw->mac.flags & TXGBE_FLAGS_DOUBLE_RESET_REQUIRED))
2201 hlreg0 = rd32(hw, TXGBE_PSRCTL);
2202 wr32(hw, TXGBE_PSRCTL, hlreg0 | TXGBE_PSRCTL_LBENA);
2204 /* Wait for a last completion before clearing buffers */
2209 * Before proceeding, make sure that the PCIe block does not have
2210 * transactions pending.
2212 poll = (800 * 11) / 10;
2213 for (i = 0; i < poll; i++)
2216 /* Flush all writes and allow 20usec for all transactions to clear */
2220 /* restore previous register values */
2221 wr32(hw, TXGBE_PSRCTL, hlreg0);
2225 * txgbe_get_thermal_sensor_data - Gathers thermal sensor data
2226 * @hw: pointer to hardware structure
2228 * Returns the thermal sensor data structure
2230 s32 txgbe_get_thermal_sensor_data(struct txgbe_hw *hw)
2232 struct txgbe_thermal_sensor_data *data = &hw->mac.thermal_sensor_data;
2236 DEBUGFUNC("txgbe_get_thermal_sensor_data");
2238 /* Only support thermal sensors attached to physical port 0 */
2239 if (hw->bus.lan_id != 0)
2240 return TXGBE_NOT_IMPLEMENTED;
2242 ts_stat = rd32(hw, TXGBE_TSSTAT);
2243 tsv = (s64)TXGBE_TSSTAT_DATA(ts_stat);
2244 tsv = tsv > 1200 ? tsv : 1200;
2245 tsv = -(48380 << 8) / 1000
2246 + tsv * (31020 << 8) / 100000
2247 - tsv * tsv * (18201 << 8) / 100000000
2248 + tsv * tsv * tsv * (81542 << 8) / 1000000000000
2249 - tsv * tsv * tsv * tsv * (16743 << 8) / 1000000000000000;
2252 data->sensor[0].temp = (s16)tsv;
2258 * txgbe_init_thermal_sensor_thresh - Inits thermal sensor thresholds
2259 * @hw: pointer to hardware structure
2261 * Inits the thermal sensor thresholds according to the NVM map
2262 * and save off the threshold and location values into mac.thermal_sensor_data
2264 s32 txgbe_init_thermal_sensor_thresh(struct txgbe_hw *hw)
2266 struct txgbe_thermal_sensor_data *data = &hw->mac.thermal_sensor_data;
2268 DEBUGFUNC("txgbe_init_thermal_sensor_thresh");
2270 memset(data, 0, sizeof(struct txgbe_thermal_sensor_data));
2272 if (hw->bus.lan_id != 0)
2273 return TXGBE_NOT_IMPLEMENTED;
2275 wr32(hw, TXGBE_TSCTRL, TXGBE_TSCTRL_EVALMD);
2276 wr32(hw, TXGBE_TSINTR,
2277 TXGBE_TSINTR_AEN | TXGBE_TSINTR_DEN);
2278 wr32(hw, TXGBE_TSEN, TXGBE_TSEN_ENA);
2281 data->sensor[0].alarm_thresh = 100;
2282 wr32(hw, TXGBE_TSATHRE, 677);
2283 data->sensor[0].dalarm_thresh = 90;
2284 wr32(hw, TXGBE_TSDTHRE, 614);
2289 void txgbe_disable_rx(struct txgbe_hw *hw)
2293 pfdtxgswc = rd32(hw, TXGBE_PSRCTL);
2294 if (pfdtxgswc & TXGBE_PSRCTL_LBENA) {
2295 pfdtxgswc &= ~TXGBE_PSRCTL_LBENA;
2296 wr32(hw, TXGBE_PSRCTL, pfdtxgswc);
2297 hw->mac.set_lben = true;
2299 hw->mac.set_lben = false;
2302 wr32m(hw, TXGBE_PBRXCTL, TXGBE_PBRXCTL_ENA, 0);
2303 wr32m(hw, TXGBE_MACRXCFG, TXGBE_MACRXCFG_ENA, 0);
2306 void txgbe_enable_rx(struct txgbe_hw *hw)
2310 wr32m(hw, TXGBE_MACRXCFG, TXGBE_MACRXCFG_ENA, TXGBE_MACRXCFG_ENA);
2311 wr32m(hw, TXGBE_PBRXCTL, TXGBE_PBRXCTL_ENA, TXGBE_PBRXCTL_ENA);
2313 if (hw->mac.set_lben) {
2314 pfdtxgswc = rd32(hw, TXGBE_PSRCTL);
2315 pfdtxgswc |= TXGBE_PSRCTL_LBENA;
2316 wr32(hw, TXGBE_PSRCTL, pfdtxgswc);
2317 hw->mac.set_lben = false;
2322 * txgbe_setup_mac_link_multispeed_fiber - Set MAC link speed
2323 * @hw: pointer to hardware structure
2324 * @speed: new link speed
2325 * @autoneg_wait_to_complete: true when waiting for completion is needed
2327 * Set the link speed in the MAC and/or PHY register and restarts link.
2329 s32 txgbe_setup_mac_link_multispeed_fiber(struct txgbe_hw *hw,
2331 bool autoneg_wait_to_complete)
2333 u32 link_speed = TXGBE_LINK_SPEED_UNKNOWN;
2334 u32 highest_link_speed = TXGBE_LINK_SPEED_UNKNOWN;
2338 bool autoneg, link_up = false;
2340 DEBUGFUNC("txgbe_setup_mac_link_multispeed_fiber");
2342 /* Mask off requested but non-supported speeds */
2343 status = hw->mac.get_link_capabilities(hw, &link_speed, &autoneg);
2347 speed &= link_speed;
2349 /* Try each speed one by one, highest priority first. We do this in
2350 * software because 10Gb fiber doesn't support speed autonegotiation.
2352 if (speed & TXGBE_LINK_SPEED_10GB_FULL) {
2354 highest_link_speed = TXGBE_LINK_SPEED_10GB_FULL;
2356 /* Set the module link speed */
2357 switch (hw->phy.media_type) {
2358 case txgbe_media_type_fiber:
2359 hw->mac.set_rate_select_speed(hw,
2360 TXGBE_LINK_SPEED_10GB_FULL);
2362 case txgbe_media_type_fiber_qsfp:
2363 /* QSFP module automatically detects MAC link speed */
2366 DEBUGOUT("Unexpected media type.\n");
2370 /* Allow module to change analog characteristics (1G->10G) */
2373 status = hw->mac.setup_mac_link(hw,
2374 TXGBE_LINK_SPEED_10GB_FULL,
2375 autoneg_wait_to_complete);
2379 /* Flap the Tx laser if it has not already been done */
2380 hw->mac.flap_tx_laser(hw);
2382 /* Wait for the controller to acquire link. Per IEEE 802.3ap,
2383 * Section 73.10.2, we may have to wait up to 500ms if KR is
2384 * attempted. uses the same timing for 10g SFI.
2386 for (i = 0; i < 5; i++) {
2387 /* Wait for the link partner to also set speed */
2390 /* If we have link, just jump out */
2391 status = hw->mac.check_link(hw, &link_speed,
2401 if (speed & TXGBE_LINK_SPEED_1GB_FULL) {
2403 if (highest_link_speed == TXGBE_LINK_SPEED_UNKNOWN)
2404 highest_link_speed = TXGBE_LINK_SPEED_1GB_FULL;
2406 /* Set the module link speed */
2407 switch (hw->phy.media_type) {
2408 case txgbe_media_type_fiber:
2409 hw->mac.set_rate_select_speed(hw,
2410 TXGBE_LINK_SPEED_1GB_FULL);
2412 case txgbe_media_type_fiber_qsfp:
2413 /* QSFP module automatically detects link speed */
2416 DEBUGOUT("Unexpected media type.\n");
2420 /* Allow module to change analog characteristics (10G->1G) */
2423 status = hw->mac.setup_mac_link(hw,
2424 TXGBE_LINK_SPEED_1GB_FULL,
2425 autoneg_wait_to_complete);
2429 /* Flap the Tx laser if it has not already been done */
2430 hw->mac.flap_tx_laser(hw);
2432 /* Wait for the link partner to also set speed */
2435 /* If we have link, just jump out */
2436 status = hw->mac.check_link(hw, &link_speed, &link_up, false);
2444 /* We didn't get link. Configure back to the highest speed we tried,
2445 * (if there was more than one). We call ourselves back with just the
2446 * single highest speed that the user requested.
2449 status = txgbe_setup_mac_link_multispeed_fiber(hw,
2451 autoneg_wait_to_complete);
2454 /* Set autoneg_advertised value based on input link speed */
2455 hw->phy.autoneg_advertised = 0;
2457 if (speed & TXGBE_LINK_SPEED_10GB_FULL)
2458 hw->phy.autoneg_advertised |= TXGBE_LINK_SPEED_10GB_FULL;
2460 if (speed & TXGBE_LINK_SPEED_1GB_FULL)
2461 hw->phy.autoneg_advertised |= TXGBE_LINK_SPEED_1GB_FULL;
2467 * txgbe_init_shared_code - Initialize the shared code
2468 * @hw: pointer to hardware structure
2470 * This will assign function pointers and assign the MAC type and PHY code.
2471 * Does not touch the hardware. This function must be called prior to any
2472 * other function in the shared code. The txgbe_hw structure should be
2473 * memset to 0 prior to calling this function. The following fields in
2474 * hw structure should be filled in prior to calling this function:
2475 * hw_addr, back, device_id, vendor_id, subsystem_device_id,
2476 * subsystem_vendor_id, and revision_id
2478 s32 txgbe_init_shared_code(struct txgbe_hw *hw)
2482 DEBUGFUNC("txgbe_init_shared_code");
2487 txgbe_set_mac_type(hw);
2489 txgbe_init_ops_dummy(hw);
2490 switch (hw->mac.type) {
2491 case txgbe_mac_raptor:
2492 status = txgbe_init_ops_pf(hw);
2495 status = TXGBE_ERR_DEVICE_NOT_SUPPORTED;
2498 hw->mac.max_link_up_time = TXGBE_LINK_UP_TIME;
2500 hw->bus.set_lan_id(hw);
2506 * txgbe_set_mac_type - Sets MAC type
2507 * @hw: pointer to the HW structure
2509 * This function sets the mac type of the adapter based on the
2510 * vendor ID and device ID stored in the hw structure.
2512 s32 txgbe_set_mac_type(struct txgbe_hw *hw)
2516 DEBUGFUNC("txgbe_set_mac_type");
2518 if (hw->vendor_id != PCI_VENDOR_ID_WANGXUN) {
2519 DEBUGOUT("Unsupported vendor id: %x", hw->vendor_id);
2520 return TXGBE_ERR_DEVICE_NOT_SUPPORTED;
2523 switch (hw->device_id) {
2524 case TXGBE_DEV_ID_RAPTOR_KR_KX_KX4:
2525 hw->phy.media_type = txgbe_media_type_backplane;
2526 hw->mac.type = txgbe_mac_raptor;
2528 case TXGBE_DEV_ID_RAPTOR_XAUI:
2529 case TXGBE_DEV_ID_RAPTOR_SGMII:
2530 hw->phy.media_type = txgbe_media_type_copper;
2531 hw->mac.type = txgbe_mac_raptor;
2533 case TXGBE_DEV_ID_RAPTOR_SFP:
2534 case TXGBE_DEV_ID_WX1820_SFP:
2535 hw->phy.media_type = txgbe_media_type_fiber;
2536 hw->mac.type = txgbe_mac_raptor;
2538 case TXGBE_DEV_ID_RAPTOR_QSFP:
2539 hw->phy.media_type = txgbe_media_type_fiber_qsfp;
2540 hw->mac.type = txgbe_mac_raptor;
2542 case TXGBE_DEV_ID_RAPTOR_VF:
2543 case TXGBE_DEV_ID_RAPTOR_VF_HV:
2544 hw->phy.media_type = txgbe_media_type_virtual;
2545 hw->mac.type = txgbe_mac_raptor_vf;
2548 err = TXGBE_ERR_DEVICE_NOT_SUPPORTED;
2549 DEBUGOUT("Unsupported device id: %x", hw->device_id);
2553 DEBUGOUT("found mac: %d media: %d, returns: %d\n",
2554 hw->mac.type, hw->phy.media_type, err);
2558 void txgbe_init_mac_link_ops(struct txgbe_hw *hw)
2560 struct txgbe_mac_info *mac = &hw->mac;
2562 DEBUGFUNC("txgbe_init_mac_link_ops");
2565 * enable the laser control functions for SFP+ fiber
2566 * and MNG not enabled
2568 if (hw->phy.media_type == txgbe_media_type_fiber &&
2569 !txgbe_mng_enabled(hw)) {
2570 mac->disable_tx_laser =
2571 txgbe_disable_tx_laser_multispeed_fiber;
2572 mac->enable_tx_laser =
2573 txgbe_enable_tx_laser_multispeed_fiber;
2574 mac->flap_tx_laser =
2575 txgbe_flap_tx_laser_multispeed_fiber;
2578 if ((hw->phy.media_type == txgbe_media_type_fiber ||
2579 hw->phy.media_type == txgbe_media_type_fiber_qsfp) &&
2580 hw->phy.multispeed_fiber) {
2581 /* Set up dual speed SFP+ support */
2582 mac->setup_link = txgbe_setup_mac_link_multispeed_fiber;
2583 mac->setup_mac_link = txgbe_setup_mac_link;
2584 mac->set_rate_select_speed = txgbe_set_hard_rate_select_speed;
2585 } else if ((hw->phy.media_type == txgbe_media_type_backplane) &&
2586 (hw->phy.smart_speed == txgbe_smart_speed_auto ||
2587 hw->phy.smart_speed == txgbe_smart_speed_on) &&
2588 !txgbe_verify_lesm_fw_enabled_raptor(hw)) {
2589 mac->setup_link = txgbe_setup_mac_link_smartspeed;
2591 mac->setup_link = txgbe_setup_mac_link;
2596 * txgbe_init_phy_raptor - PHY/SFP specific init
2597 * @hw: pointer to hardware structure
2599 * Initialize any function pointers that were not able to be
2600 * set during init_shared_code because the PHY/SFP type was
2601 * not known. Perform the SFP init if necessary.
2604 s32 txgbe_init_phy_raptor(struct txgbe_hw *hw)
2606 struct txgbe_mac_info *mac = &hw->mac;
2607 struct txgbe_phy_info *phy = &hw->phy;
2610 DEBUGFUNC("txgbe_init_phy_raptor");
2612 if (hw->device_id == TXGBE_DEV_ID_RAPTOR_QSFP) {
2613 /* Store flag indicating I2C bus access control unit. */
2614 hw->phy.qsfp_shared_i2c_bus = TRUE;
2616 /* Initialize access to QSFP+ I2C bus */
2620 /* Identify the PHY or SFP module */
2621 err = phy->identify(hw);
2622 if (err == TXGBE_ERR_SFP_NOT_SUPPORTED)
2623 goto init_phy_ops_out;
2625 /* Setup function pointers based on detected SFP module and speeds */
2626 txgbe_init_mac_link_ops(hw);
2628 /* If copper media, overwrite with copper function pointers */
2629 if (phy->media_type == txgbe_media_type_copper) {
2630 mac->setup_link = txgbe_setup_copper_link_raptor;
2631 mac->get_link_capabilities =
2632 txgbe_get_copper_link_capabilities;
2635 /* Set necessary function pointers based on PHY type */
2636 switch (hw->phy.type) {
2638 phy->setup_link = txgbe_setup_phy_link_tnx;
2639 phy->check_link = txgbe_check_phy_link_tnx;
2649 s32 txgbe_setup_sfp_modules(struct txgbe_hw *hw)
2653 DEBUGFUNC("txgbe_setup_sfp_modules");
2655 if (hw->phy.sfp_type == txgbe_sfp_type_unknown)
2658 txgbe_init_mac_link_ops(hw);
2660 /* PHY config will finish before releasing the semaphore */
2661 err = hw->mac.acquire_swfw_sync(hw, TXGBE_MNGSEM_SWPHY);
2663 return TXGBE_ERR_SWFW_SYNC;
2665 /* Release the semaphore */
2666 hw->mac.release_swfw_sync(hw, TXGBE_MNGSEM_SWPHY);
2668 /* Delay obtaining semaphore again to allow FW access
2669 * prot_autoc_write uses the semaphore too.
2671 msec_delay(hw->rom.semaphore_delay);
2674 DEBUGOUT("sfp module setup not complete\n");
2675 return TXGBE_ERR_SFP_SETUP_NOT_COMPLETE;
2682 * txgbe_prot_autoc_read_raptor - Hides MAC differences needed for AUTOC read
2683 * @hw: pointer to hardware structure
2684 * @locked: Return the if we locked for this read.
2685 * @value: Value we read from AUTOC
2687 * For this part we need to wrap read-modify-writes with a possible
2688 * FW/SW lock. It is assumed this lock will be freed with the next
2689 * prot_autoc_write_raptor().
2691 s32 txgbe_prot_autoc_read_raptor(struct txgbe_hw *hw, bool *locked, u64 *value)
2694 bool lock_state = false;
2696 /* If LESM is on then we need to hold the SW/FW semaphore. */
2697 if (txgbe_verify_lesm_fw_enabled_raptor(hw)) {
2698 err = hw->mac.acquire_swfw_sync(hw,
2699 TXGBE_MNGSEM_SWPHY);
2701 return TXGBE_ERR_SWFW_SYNC;
2707 *locked = lock_state;
2709 *value = txgbe_autoc_read(hw);
2714 * txgbe_prot_autoc_write_raptor - Hides MAC differences needed for AUTOC write
2715 * @hw: pointer to hardware structure
2716 * @autoc: value to write to AUTOC
2717 * @locked: bool to indicate whether the SW/FW lock was already taken by
2718 * previous prot_autoc_read_raptor.
2720 * This part may need to hold the SW/FW lock around all writes to
2721 * AUTOC. Likewise after a write we need to do a pipeline reset.
2723 s32 txgbe_prot_autoc_write_raptor(struct txgbe_hw *hw, bool locked, u64 autoc)
2727 /* Blocked by MNG FW so bail */
2728 if (txgbe_check_reset_blocked(hw))
2731 /* We only need to get the lock if:
2732 * - We didn't do it already (in the read part of a read-modify-write)
2733 * - LESM is enabled.
2735 if (!locked && txgbe_verify_lesm_fw_enabled_raptor(hw)) {
2736 err = hw->mac.acquire_swfw_sync(hw,
2737 TXGBE_MNGSEM_SWPHY);
2739 return TXGBE_ERR_SWFW_SYNC;
2744 txgbe_autoc_write(hw, autoc);
2745 err = txgbe_reset_pipeline_raptor(hw);
2748 /* Free the SW/FW semaphore as we either grabbed it here or
2749 * already had it when this function was called.
2752 hw->mac.release_swfw_sync(hw, TXGBE_MNGSEM_SWPHY);
2758 * txgbe_init_ops_pf - Inits func ptrs and MAC type
2759 * @hw: pointer to hardware structure
2761 * Initialize the function pointers and assign the MAC type.
2762 * Does not touch the hardware.
2764 s32 txgbe_init_ops_pf(struct txgbe_hw *hw)
2766 struct txgbe_bus_info *bus = &hw->bus;
2767 struct txgbe_mac_info *mac = &hw->mac;
2768 struct txgbe_phy_info *phy = &hw->phy;
2769 struct txgbe_rom_info *rom = &hw->rom;
2770 struct txgbe_mbx_info *mbx = &hw->mbx;
2772 DEBUGFUNC("txgbe_init_ops_pf");
2775 bus->set_lan_id = txgbe_set_lan_id_multi_port;
2778 phy->get_media_type = txgbe_get_media_type_raptor;
2779 phy->identify = txgbe_identify_phy;
2780 phy->init = txgbe_init_phy_raptor;
2781 phy->read_reg = txgbe_read_phy_reg;
2782 phy->write_reg = txgbe_write_phy_reg;
2783 phy->read_reg_mdi = txgbe_read_phy_reg_mdi;
2784 phy->write_reg_mdi = txgbe_write_phy_reg_mdi;
2785 phy->setup_link = txgbe_setup_phy_link;
2786 phy->setup_link_speed = txgbe_setup_phy_link_speed;
2787 phy->read_i2c_byte = txgbe_read_i2c_byte;
2788 phy->write_i2c_byte = txgbe_write_i2c_byte;
2789 phy->read_i2c_sff8472 = txgbe_read_i2c_sff8472;
2790 phy->read_i2c_eeprom = txgbe_read_i2c_eeprom;
2791 phy->write_i2c_eeprom = txgbe_write_i2c_eeprom;
2792 phy->identify_sfp = txgbe_identify_module;
2793 phy->read_i2c_byte_unlocked = txgbe_read_i2c_byte_unlocked;
2794 phy->write_i2c_byte_unlocked = txgbe_write_i2c_byte_unlocked;
2795 phy->reset = txgbe_reset_phy;
2798 mac->init_hw = txgbe_init_hw;
2799 mac->start_hw = txgbe_start_hw_raptor;
2800 mac->clear_hw_cntrs = txgbe_clear_hw_cntrs;
2801 mac->enable_rx_dma = txgbe_enable_rx_dma_raptor;
2802 mac->get_mac_addr = txgbe_get_mac_addr;
2803 mac->stop_hw = txgbe_stop_hw;
2804 mac->acquire_swfw_sync = txgbe_acquire_swfw_sync;
2805 mac->release_swfw_sync = txgbe_release_swfw_sync;
2806 mac->reset_hw = txgbe_reset_hw;
2808 mac->disable_sec_rx_path = txgbe_disable_sec_rx_path;
2809 mac->enable_sec_rx_path = txgbe_enable_sec_rx_path;
2810 mac->disable_sec_tx_path = txgbe_disable_sec_tx_path;
2811 mac->enable_sec_tx_path = txgbe_enable_sec_tx_path;
2812 mac->get_san_mac_addr = txgbe_get_san_mac_addr;
2813 mac->set_san_mac_addr = txgbe_set_san_mac_addr;
2814 mac->get_device_caps = txgbe_get_device_caps;
2815 mac->get_wwn_prefix = txgbe_get_wwn_prefix;
2816 mac->autoc_read = txgbe_autoc_read;
2817 mac->autoc_write = txgbe_autoc_write;
2818 mac->prot_autoc_read = txgbe_prot_autoc_read_raptor;
2819 mac->prot_autoc_write = txgbe_prot_autoc_write_raptor;
2821 /* RAR, Multicast, VLAN */
2822 mac->set_rar = txgbe_set_rar;
2823 mac->clear_rar = txgbe_clear_rar;
2824 mac->init_rx_addrs = txgbe_init_rx_addrs;
2825 mac->enable_rx = txgbe_enable_rx;
2826 mac->disable_rx = txgbe_disable_rx;
2827 mac->set_vmdq = txgbe_set_vmdq;
2828 mac->clear_vmdq = txgbe_clear_vmdq;
2829 mac->set_vfta = txgbe_set_vfta;
2830 mac->set_vlvf = txgbe_set_vlvf;
2831 mac->clear_vfta = txgbe_clear_vfta;
2832 mac->init_uta_tables = txgbe_init_uta_tables;
2833 mac->setup_sfp = txgbe_setup_sfp_modules;
2834 mac->set_mac_anti_spoofing = txgbe_set_mac_anti_spoofing;
2835 mac->set_ethertype_anti_spoofing = txgbe_set_ethertype_anti_spoofing;
2838 mac->fc_enable = txgbe_fc_enable;
2839 mac->setup_fc = txgbe_setup_fc;
2840 mac->fc_autoneg = txgbe_fc_autoneg;
2843 mac->get_link_capabilities = txgbe_get_link_capabilities_raptor;
2844 mac->check_link = txgbe_check_mac_link;
2845 mac->setup_pba = txgbe_set_pba;
2847 /* Manageability interface */
2848 mac->set_fw_drv_ver = txgbe_hic_set_drv_ver;
2849 mac->get_thermal_sensor_data = txgbe_get_thermal_sensor_data;
2850 mac->init_thermal_sensor_thresh = txgbe_init_thermal_sensor_thresh;
2852 mbx->init_params = txgbe_init_mbx_params_pf;
2853 mbx->read = txgbe_read_mbx_pf;
2854 mbx->write = txgbe_write_mbx_pf;
2855 mbx->check_for_msg = txgbe_check_for_msg_pf;
2856 mbx->check_for_ack = txgbe_check_for_ack_pf;
2857 mbx->check_for_rst = txgbe_check_for_rst_pf;
2860 rom->init_params = txgbe_init_eeprom_params;
2861 rom->read16 = txgbe_ee_read16;
2862 rom->readw_buffer = txgbe_ee_readw_buffer;
2863 rom->readw_sw = txgbe_ee_readw_sw;
2864 rom->read32 = txgbe_ee_read32;
2865 rom->write16 = txgbe_ee_write16;
2866 rom->writew_buffer = txgbe_ee_writew_buffer;
2867 rom->writew_sw = txgbe_ee_writew_sw;
2868 rom->write32 = txgbe_ee_write32;
2869 rom->validate_checksum = txgbe_validate_eeprom_checksum;
2870 rom->update_checksum = txgbe_update_eeprom_checksum;
2871 rom->calc_checksum = txgbe_calc_eeprom_checksum;
2873 mac->mcft_size = TXGBE_RAPTOR_MC_TBL_SIZE;
2874 mac->vft_size = TXGBE_RAPTOR_VFT_TBL_SIZE;
2875 mac->num_rar_entries = TXGBE_RAPTOR_RAR_ENTRIES;
2876 mac->rx_pb_size = TXGBE_RAPTOR_RX_PB_SIZE;
2877 mac->max_rx_queues = TXGBE_RAPTOR_MAX_RX_QUEUES;
2878 mac->max_tx_queues = TXGBE_RAPTOR_MAX_TX_QUEUES;
2884 * txgbe_get_link_capabilities_raptor - Determines link capabilities
2885 * @hw: pointer to hardware structure
2886 * @speed: pointer to link speed
2887 * @autoneg: true when autoneg or autotry is enabled
2889 * Determines the link capabilities by reading the AUTOC register.
2891 s32 txgbe_get_link_capabilities_raptor(struct txgbe_hw *hw,
2898 DEBUGFUNC("txgbe_get_link_capabilities_raptor");
2900 /* Check if 1G SFP module. */
2901 if (hw->phy.sfp_type == txgbe_sfp_type_1g_cu_core0 ||
2902 hw->phy.sfp_type == txgbe_sfp_type_1g_cu_core1 ||
2903 hw->phy.sfp_type == txgbe_sfp_type_1g_lx_core0 ||
2904 hw->phy.sfp_type == txgbe_sfp_type_1g_lx_core1 ||
2905 hw->phy.sfp_type == txgbe_sfp_type_1g_sx_core0 ||
2906 hw->phy.sfp_type == txgbe_sfp_type_1g_sx_core1) {
2907 *speed = TXGBE_LINK_SPEED_1GB_FULL;
2913 * Determine link capabilities based on the stored value of AUTOC,
2914 * which represents EEPROM defaults. If AUTOC value has not
2915 * been stored, use the current register values.
2917 if (hw->mac.orig_link_settings_stored)
2918 autoc = hw->mac.orig_autoc;
2920 autoc = hw->mac.autoc_read(hw);
2922 switch (autoc & TXGBE_AUTOC_LMS_MASK) {
2923 case TXGBE_AUTOC_LMS_1G_LINK_NO_AN:
2924 *speed = TXGBE_LINK_SPEED_1GB_FULL;
2928 case TXGBE_AUTOC_LMS_10G_LINK_NO_AN:
2929 *speed = TXGBE_LINK_SPEED_10GB_FULL;
2933 case TXGBE_AUTOC_LMS_1G_AN:
2934 *speed = TXGBE_LINK_SPEED_1GB_FULL;
2938 case TXGBE_AUTOC_LMS_10G:
2939 *speed = TXGBE_LINK_SPEED_10GB_FULL;
2943 case TXGBE_AUTOC_LMS_KX4_KX_KR:
2944 case TXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN:
2945 *speed = TXGBE_LINK_SPEED_UNKNOWN;
2946 if (autoc & TXGBE_AUTOC_KR_SUPP)
2947 *speed |= TXGBE_LINK_SPEED_10GB_FULL;
2948 if (autoc & TXGBE_AUTOC_KX4_SUPP)
2949 *speed |= TXGBE_LINK_SPEED_10GB_FULL;
2950 if (autoc & TXGBE_AUTOC_KX_SUPP)
2951 *speed |= TXGBE_LINK_SPEED_1GB_FULL;
2955 case TXGBE_AUTOC_LMS_KX4_KX_KR_SGMII:
2956 *speed = TXGBE_LINK_SPEED_100M_FULL;
2957 if (autoc & TXGBE_AUTOC_KR_SUPP)
2958 *speed |= TXGBE_LINK_SPEED_10GB_FULL;
2959 if (autoc & TXGBE_AUTOC_KX4_SUPP)
2960 *speed |= TXGBE_LINK_SPEED_10GB_FULL;
2961 if (autoc & TXGBE_AUTOC_KX_SUPP)
2962 *speed |= TXGBE_LINK_SPEED_1GB_FULL;
2966 case TXGBE_AUTOC_LMS_SGMII_1G_100M:
2967 *speed = TXGBE_LINK_SPEED_1GB_FULL |
2968 TXGBE_LINK_SPEED_100M_FULL |
2969 TXGBE_LINK_SPEED_10M_FULL;
2974 return TXGBE_ERR_LINK_SETUP;
2977 if (hw->phy.multispeed_fiber) {
2978 *speed |= TXGBE_LINK_SPEED_10GB_FULL |
2979 TXGBE_LINK_SPEED_1GB_FULL;
2981 /* QSFP must not enable full auto-negotiation
2982 * Limited autoneg is enabled at 1G
2984 if (hw->phy.media_type == txgbe_media_type_fiber_qsfp)
2994 * txgbe_get_media_type_raptor - Get media type
2995 * @hw: pointer to hardware structure
2997 * Returns the media type (fiber, copper, backplane)
2999 u32 txgbe_get_media_type_raptor(struct txgbe_hw *hw)
3003 DEBUGFUNC("txgbe_get_media_type_raptor");
3005 /* Detect if there is a copper PHY attached. */
3006 switch (hw->phy.type) {
3007 case txgbe_phy_cu_unknown:
3009 media_type = txgbe_media_type_copper;
3015 switch (hw->device_id) {
3016 case TXGBE_DEV_ID_RAPTOR_KR_KX_KX4:
3017 /* Default device ID is mezzanine card KX/KX4 */
3018 media_type = txgbe_media_type_backplane;
3020 case TXGBE_DEV_ID_RAPTOR_SFP:
3021 case TXGBE_DEV_ID_WX1820_SFP:
3022 media_type = txgbe_media_type_fiber;
3024 case TXGBE_DEV_ID_RAPTOR_QSFP:
3025 media_type = txgbe_media_type_fiber_qsfp;
3027 case TXGBE_DEV_ID_RAPTOR_XAUI:
3028 case TXGBE_DEV_ID_RAPTOR_SGMII:
3029 media_type = txgbe_media_type_copper;
3032 media_type = txgbe_media_type_unknown;
3040 * txgbe_start_mac_link_raptor - Setup MAC link settings
3041 * @hw: pointer to hardware structure
3042 * @autoneg_wait_to_complete: true when waiting for completion is needed
3044 * Configures link settings based on values in the txgbe_hw struct.
3045 * Restarts the link. Performs autonegotiation if needed.
3047 s32 txgbe_start_mac_link_raptor(struct txgbe_hw *hw,
3048 bool autoneg_wait_to_complete)
3051 bool got_lock = false;
3053 DEBUGFUNC("txgbe_start_mac_link_raptor");
3055 UNREFERENCED_PARAMETER(autoneg_wait_to_complete);
3057 /* reset_pipeline requires us to hold this lock as it writes to
3060 if (txgbe_verify_lesm_fw_enabled_raptor(hw)) {
3061 status = hw->mac.acquire_swfw_sync(hw, TXGBE_MNGSEM_SWPHY);
3069 txgbe_reset_pipeline_raptor(hw);
3072 hw->mac.release_swfw_sync(hw, TXGBE_MNGSEM_SWPHY);
3074 /* Add delay to filter out noises during initial link setup */
3082 * txgbe_disable_tx_laser_multispeed_fiber - Disable Tx laser
3083 * @hw: pointer to hardware structure
3085 * The base drivers may require better control over SFP+ module
3086 * PHY states. This includes selectively shutting down the Tx
3087 * laser on the PHY, effectively halting physical link.
3089 void txgbe_disable_tx_laser_multispeed_fiber(struct txgbe_hw *hw)
3091 u32 esdp_reg = rd32(hw, TXGBE_GPIODATA);
3093 /* Blocked by MNG FW so bail */
3094 if (txgbe_check_reset_blocked(hw))
3097 /* Disable Tx laser; allow 100us to go dark per spec */
3098 esdp_reg |= (TXGBE_GPIOBIT_0 | TXGBE_GPIOBIT_1);
3099 wr32(hw, TXGBE_GPIODATA, esdp_reg);
3105 * txgbe_enable_tx_laser_multispeed_fiber - Enable Tx laser
3106 * @hw: pointer to hardware structure
3108 * The base drivers may require better control over SFP+ module
3109 * PHY states. This includes selectively turning on the Tx
3110 * laser on the PHY, effectively starting physical link.
3112 void txgbe_enable_tx_laser_multispeed_fiber(struct txgbe_hw *hw)
3114 u32 esdp_reg = rd32(hw, TXGBE_GPIODATA);
3116 /* Enable Tx laser; allow 100ms to light up */
3117 esdp_reg &= ~(TXGBE_GPIOBIT_0 | TXGBE_GPIOBIT_1);
3118 wr32(hw, TXGBE_GPIODATA, esdp_reg);
3124 * txgbe_flap_tx_laser_multispeed_fiber - Flap Tx laser
3125 * @hw: pointer to hardware structure
3127 * When the driver changes the link speeds that it can support,
3128 * it sets autotry_restart to true to indicate that we need to
3129 * initiate a new autotry session with the link partner. To do
3130 * so, we set the speed then disable and re-enable the Tx laser, to
3131 * alert the link partner that it also needs to restart autotry on its
3132 * end. This is consistent with true clause 37 autoneg, which also
3133 * involves a loss of signal.
3135 void txgbe_flap_tx_laser_multispeed_fiber(struct txgbe_hw *hw)
3137 DEBUGFUNC("txgbe_flap_tx_laser_multispeed_fiber");
3139 /* Blocked by MNG FW so bail */
3140 if (txgbe_check_reset_blocked(hw))
3143 if (hw->mac.autotry_restart) {
3144 txgbe_disable_tx_laser_multispeed_fiber(hw);
3145 txgbe_enable_tx_laser_multispeed_fiber(hw);
3146 hw->mac.autotry_restart = false;
3151 * txgbe_set_hard_rate_select_speed - Set module link speed
3152 * @hw: pointer to hardware structure
3153 * @speed: link speed to set
3155 * Set module link speed via RS0/RS1 rate select pins.
3157 void txgbe_set_hard_rate_select_speed(struct txgbe_hw *hw,
3160 u32 esdp_reg = rd32(hw, TXGBE_GPIODATA);
3163 case TXGBE_LINK_SPEED_10GB_FULL:
3164 esdp_reg |= (TXGBE_GPIOBIT_4 | TXGBE_GPIOBIT_5);
3166 case TXGBE_LINK_SPEED_1GB_FULL:
3167 esdp_reg &= ~(TXGBE_GPIOBIT_4 | TXGBE_GPIOBIT_5);
3170 DEBUGOUT("Invalid fixed module speed\n");
3174 wr32(hw, TXGBE_GPIODATA, esdp_reg);
3179 * txgbe_setup_mac_link_smartspeed - Set MAC link speed using SmartSpeed
3180 * @hw: pointer to hardware structure
3181 * @speed: new link speed
3182 * @autoneg_wait_to_complete: true when waiting for completion is needed
3184 * Implements the Intel SmartSpeed algorithm.
3186 s32 txgbe_setup_mac_link_smartspeed(struct txgbe_hw *hw,
3188 bool autoneg_wait_to_complete)
3191 u32 link_speed = TXGBE_LINK_SPEED_UNKNOWN;
3193 bool link_up = false;
3194 u32 autoc_reg = rd32_epcs(hw, SR_AN_MMD_ADV_REG1);
3196 DEBUGFUNC("txgbe_setup_mac_link_smartspeed");
3198 /* Set autoneg_advertised value based on input link speed */
3199 hw->phy.autoneg_advertised = 0;
3201 if (speed & TXGBE_LINK_SPEED_10GB_FULL)
3202 hw->phy.autoneg_advertised |= TXGBE_LINK_SPEED_10GB_FULL;
3204 if (speed & TXGBE_LINK_SPEED_1GB_FULL)
3205 hw->phy.autoneg_advertised |= TXGBE_LINK_SPEED_1GB_FULL;
3207 if (speed & TXGBE_LINK_SPEED_100M_FULL)
3208 hw->phy.autoneg_advertised |= TXGBE_LINK_SPEED_100M_FULL;
3211 * Implement Intel SmartSpeed algorithm. SmartSpeed will reduce the
3212 * autoneg advertisement if link is unable to be established at the
3213 * highest negotiated rate. This can sometimes happen due to integrity
3214 * issues with the physical media connection.
3217 /* First, try to get link with full advertisement */
3218 hw->phy.smart_speed_active = false;
3219 for (j = 0; j < TXGBE_SMARTSPEED_MAX_RETRIES; j++) {
3220 status = txgbe_setup_mac_link(hw, speed,
3221 autoneg_wait_to_complete);
3226 * Wait for the controller to acquire link. Per IEEE 802.3ap,
3227 * Section 73.10.2, we may have to wait up to 500ms if KR is
3228 * attempted, or 200ms if KX/KX4/BX/BX4 is attempted, per
3229 * Table 9 in the AN MAS.
3231 for (i = 0; i < 5; i++) {
3234 /* If we have link, just jump out */
3235 status = hw->mac.check_link(hw, &link_speed, &link_up,
3246 * We didn't get link. If we advertised KR plus one of KX4/KX
3247 * (or BX4/BX), then disable KR and try again.
3249 if (((autoc_reg & TXGBE_AUTOC_KR_SUPP) == 0) ||
3250 ((autoc_reg & TXGBE_AUTOC_KX_SUPP) == 0 &&
3251 (autoc_reg & TXGBE_AUTOC_KX4_SUPP) == 0))
3254 /* Turn SmartSpeed on to disable KR support */
3255 hw->phy.smart_speed_active = true;
3256 status = txgbe_setup_mac_link(hw, speed,
3257 autoneg_wait_to_complete);
3262 * Wait for the controller to acquire link. 600ms will allow for
3263 * the AN link_fail_inhibit_timer as well for multiple cycles of
3264 * parallel detect, both 10g and 1g. This allows for the maximum
3265 * connect attempts as defined in the AN MAS table 73-7.
3267 for (i = 0; i < 6; i++) {
3270 /* If we have link, just jump out */
3271 status = hw->mac.check_link(hw, &link_speed, &link_up, false);
3279 /* We didn't get link. Turn SmartSpeed back off. */
3280 hw->phy.smart_speed_active = false;
3281 status = txgbe_setup_mac_link(hw, speed,
3282 autoneg_wait_to_complete);
3285 if (link_up && link_speed == TXGBE_LINK_SPEED_1GB_FULL)
3286 DEBUGOUT("Smartspeed has downgraded the link speed "
3287 "from the maximum advertised\n");
3292 * txgbe_setup_mac_link - Set MAC link speed
3293 * @hw: pointer to hardware structure
3294 * @speed: new link speed
3295 * @autoneg_wait_to_complete: true when waiting for completion is needed
3297 * Set the link speed in the AUTOC register and restarts link.
3299 s32 txgbe_setup_mac_link(struct txgbe_hw *hw,
3301 bool autoneg_wait_to_complete)
3303 bool autoneg = false;
3306 u64 autoc = hw->mac.autoc_read(hw);
3307 u64 pma_pmd_10gs = autoc & TXGBE_AUTOC_10GS_PMA_PMD_MASK;
3308 u64 pma_pmd_1g = autoc & TXGBE_AUTOC_1G_PMA_PMD_MASK;
3309 u64 link_mode = autoc & TXGBE_AUTOC_LMS_MASK;
3310 u64 current_autoc = autoc;
3314 u32 link_capabilities = TXGBE_LINK_SPEED_UNKNOWN;
3316 DEBUGFUNC("txgbe_setup_mac_link");
3318 /* Check to see if speed passed in is supported. */
3319 status = hw->mac.get_link_capabilities(hw,
3320 &link_capabilities, &autoneg);
3324 speed &= link_capabilities;
3325 if (speed == TXGBE_LINK_SPEED_UNKNOWN)
3326 return TXGBE_ERR_LINK_SETUP;
3328 /* Use stored value (EEPROM defaults) of AUTOC to find KR/KX4 support*/
3329 if (hw->mac.orig_link_settings_stored)
3330 orig_autoc = hw->mac.orig_autoc;
3334 link_mode = autoc & TXGBE_AUTOC_LMS_MASK;
3335 pma_pmd_1g = autoc & TXGBE_AUTOC_1G_PMA_PMD_MASK;
3337 if (link_mode == TXGBE_AUTOC_LMS_KX4_KX_KR ||
3338 link_mode == TXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
3339 link_mode == TXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
3340 /* Set KX4/KX/KR support according to speed requested */
3341 autoc &= ~(TXGBE_AUTOC_KX_SUPP |
3342 TXGBE_AUTOC_KX4_SUPP |
3343 TXGBE_AUTOC_KR_SUPP);
3344 if (speed & TXGBE_LINK_SPEED_10GB_FULL) {
3345 if (orig_autoc & TXGBE_AUTOC_KX4_SUPP)
3346 autoc |= TXGBE_AUTOC_KX4_SUPP;
3347 if ((orig_autoc & TXGBE_AUTOC_KR_SUPP) &&
3348 !hw->phy.smart_speed_active)
3349 autoc |= TXGBE_AUTOC_KR_SUPP;
3351 if (speed & TXGBE_LINK_SPEED_1GB_FULL)
3352 autoc |= TXGBE_AUTOC_KX_SUPP;
3353 } else if ((pma_pmd_1g == TXGBE_AUTOC_1G_SFI) &&
3354 (link_mode == TXGBE_AUTOC_LMS_1G_LINK_NO_AN ||
3355 link_mode == TXGBE_AUTOC_LMS_1G_AN)) {
3356 /* Switch from 1G SFI to 10G SFI if requested */
3357 if (speed == TXGBE_LINK_SPEED_10GB_FULL &&
3358 pma_pmd_10gs == TXGBE_AUTOC_10GS_SFI) {
3359 autoc &= ~TXGBE_AUTOC_LMS_MASK;
3360 autoc |= TXGBE_AUTOC_LMS_10G;
3362 } else if ((pma_pmd_10gs == TXGBE_AUTOC_10GS_SFI) &&
3363 (link_mode == TXGBE_AUTOC_LMS_10G)) {
3364 /* Switch from 10G SFI to 1G SFI if requested */
3365 if (speed == TXGBE_LINK_SPEED_1GB_FULL &&
3366 pma_pmd_1g == TXGBE_AUTOC_1G_SFI) {
3367 autoc &= ~TXGBE_AUTOC_LMS_MASK;
3368 if (autoneg || hw->phy.type == txgbe_phy_qsfp_intel)
3369 autoc |= TXGBE_AUTOC_LMS_1G_AN;
3371 autoc |= TXGBE_AUTOC_LMS_1G_LINK_NO_AN;
3375 if (autoc == current_autoc)
3378 autoc &= ~TXGBE_AUTOC_SPEED_MASK;
3379 autoc |= TXGBE_AUTOC_SPEED(speed);
3380 autoc |= (autoneg ? TXGBE_AUTOC_AUTONEG : 0);
3383 hw->mac.autoc_write(hw, autoc);
3385 /* Only poll for autoneg to complete if specified to do so */
3386 if (autoneg_wait_to_complete) {
3387 if (link_mode == TXGBE_AUTOC_LMS_KX4_KX_KR ||
3388 link_mode == TXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
3389 link_mode == TXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
3390 links_reg = 0; /*Just in case Autoneg time=0*/
3391 for (i = 0; i < TXGBE_AUTO_NEG_TIME; i++) {
3392 links_reg = rd32(hw, TXGBE_PORTSTAT);
3393 if (links_reg & TXGBE_PORTSTAT_UP)
3397 if (!(links_reg & TXGBE_PORTSTAT_UP)) {
3398 status = TXGBE_ERR_AUTONEG_NOT_COMPLETE;
3399 DEBUGOUT("Autoneg did not complete.\n");
3404 /* Add delay to filter out noises during initial link setup */
3411 * txgbe_setup_copper_link_raptor - Set the PHY autoneg advertised field
3412 * @hw: pointer to hardware structure
3413 * @speed: new link speed
3414 * @autoneg_wait_to_complete: true if waiting is needed to complete
3416 * Restarts link on PHY and MAC based on settings passed in.
3418 static s32 txgbe_setup_copper_link_raptor(struct txgbe_hw *hw,
3420 bool autoneg_wait_to_complete)
3424 DEBUGFUNC("txgbe_setup_copper_link_raptor");
3426 /* Setup the PHY according to input speed */
3427 status = hw->phy.setup_link_speed(hw, speed,
3428 autoneg_wait_to_complete);
3430 txgbe_start_mac_link_raptor(hw, autoneg_wait_to_complete);
3436 txgbe_check_flash_load(struct txgbe_hw *hw, u32 check_bit)
3441 /* if there's flash existing */
3442 if (!(rd32(hw, TXGBE_SPISTAT) & TXGBE_SPISTAT_BPFLASH)) {
3443 /* wait hw load flash done */
3444 for (i = 0; i < 10; i++) {
3445 reg = rd32(hw, TXGBE_ILDRSTAT);
3446 if (!(reg & check_bit)) {
3453 err = TXGBE_ERR_FLASH_LOADING_FAILED;
3459 txgbe_reset_misc(struct txgbe_hw *hw)
3464 wr32(hw, TXGBE_ISBADDRL, hw->isb_dma & 0x00000000FFFFFFFF);
3465 wr32(hw, TXGBE_ISBADDRH, hw->isb_dma >> 32);
3467 value = rd32_epcs(hw, SR_XS_PCS_CTRL2);
3468 if ((value & 0x3) != SR_PCS_CTRL2_TYPE_SEL_X)
3469 hw->link_status = TXGBE_LINK_STATUS_NONE;
3471 /* receive packets that size > 2048 */
3472 wr32m(hw, TXGBE_MACRXCFG,
3473 TXGBE_MACRXCFG_JUMBO, TXGBE_MACRXCFG_JUMBO);
3475 wr32m(hw, TXGBE_FRMSZ, TXGBE_FRMSZ_MAX_MASK,
3476 TXGBE_FRMSZ_MAX(TXGBE_FRAME_SIZE_DFT));
3478 /* clear counters on read */
3479 wr32m(hw, TXGBE_MACCNTCTL,
3480 TXGBE_MACCNTCTL_RC, TXGBE_MACCNTCTL_RC);
3482 wr32m(hw, TXGBE_RXFCCFG,
3483 TXGBE_RXFCCFG_FC, TXGBE_RXFCCFG_FC);
3484 wr32m(hw, TXGBE_TXFCCFG,
3485 TXGBE_TXFCCFG_FC, TXGBE_TXFCCFG_FC);
3487 wr32m(hw, TXGBE_MACRXFLT,
3488 TXGBE_MACRXFLT_PROMISC, TXGBE_MACRXFLT_PROMISC);
3490 wr32m(hw, TXGBE_RSTSTAT,
3491 TXGBE_RSTSTAT_TMRINIT_MASK, TXGBE_RSTSTAT_TMRINIT(30));
3493 /* errata 4: initialize mng flex tbl and wakeup flex tbl*/
3494 wr32(hw, TXGBE_MNGFLEXSEL, 0);
3495 for (i = 0; i < 16; i++) {
3496 wr32(hw, TXGBE_MNGFLEXDWL(i), 0);
3497 wr32(hw, TXGBE_MNGFLEXDWH(i), 0);
3498 wr32(hw, TXGBE_MNGFLEXMSK(i), 0);
3500 wr32(hw, TXGBE_LANFLEXSEL, 0);
3501 for (i = 0; i < 16; i++) {
3502 wr32(hw, TXGBE_LANFLEXDWL(i), 0);
3503 wr32(hw, TXGBE_LANFLEXDWH(i), 0);
3504 wr32(hw, TXGBE_LANFLEXMSK(i), 0);
3507 /* set pause frame dst mac addr */
3508 wr32(hw, TXGBE_RXPBPFCDMACL, 0xC2000001);
3509 wr32(hw, TXGBE_RXPBPFCDMACH, 0x0180);
3511 hw->mac.init_thermal_sensor_thresh(hw);
3513 /* enable mac transmitter */
3514 wr32m(hw, TXGBE_MACTXCFG, TXGBE_MACTXCFG_TXE, TXGBE_MACTXCFG_TXE);
3516 for (i = 0; i < 4; i++)
3517 wr32m(hw, TXGBE_IVAR(i), 0x80808080, 0);
3521 * txgbe_reset_hw - Perform hardware reset
3522 * @hw: pointer to hardware structure
3524 * Resets the hardware by resetting the transmit and receive units, masks
3525 * and clears all interrupts, perform a PHY reset, and perform a link (MAC)
3528 s32 txgbe_reset_hw(struct txgbe_hw *hw)
3533 DEBUGFUNC("txgbe_reset_hw");
3535 /* Call adapter stop to disable tx/rx and clear interrupts */
3536 status = hw->mac.stop_hw(hw);
3540 /* flush pending Tx transactions */
3541 txgbe_clear_tx_pending(hw);
3543 /* Identify PHY and related function pointers */
3544 status = hw->phy.init(hw);
3545 if (status == TXGBE_ERR_SFP_NOT_SUPPORTED)
3548 /* Setup SFP module if there is one present. */
3549 if (hw->phy.sfp_setup_needed) {
3550 status = hw->mac.setup_sfp(hw);
3551 hw->phy.sfp_setup_needed = false;
3553 if (status == TXGBE_ERR_SFP_NOT_SUPPORTED)
3557 if (!hw->phy.reset_disable)
3560 /* remember AUTOC from before we reset */
3561 autoc = hw->mac.autoc_read(hw);
3565 * Issue global reset to the MAC. Needs to be SW reset if link is up.
3566 * If link reset is used when link is up, it might reset the PHY when
3567 * mng is using it. If link is down or the flag to force full link
3568 * reset is set, then perform link reset.
3570 if (txgbe_mng_present(hw)) {
3571 txgbe_hic_reset(hw);
3573 wr32(hw, TXGBE_RST, TXGBE_RST_LAN(hw->bus.lan_id));
3578 txgbe_reset_misc(hw);
3580 if (hw->bus.lan_id == 0) {
3581 status = txgbe_check_flash_load(hw,
3582 TXGBE_ILDRSTAT_SWRST_LAN0);
3584 status = txgbe_check_flash_load(hw,
3585 TXGBE_ILDRSTAT_SWRST_LAN1);
3593 * Double resets are required for recovery from certain error
3594 * conditions. Between resets, it is necessary to stall to
3595 * allow time for any pending HW events to complete.
3597 if (hw->mac.flags & TXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
3598 hw->mac.flags &= ~TXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
3603 * Store the original AUTOC/AUTOC2 values if they have not been
3604 * stored off yet. Otherwise restore the stored original
3605 * values since the reset operation sets back to defaults.
3607 if (!hw->mac.orig_link_settings_stored) {
3608 hw->mac.orig_autoc = hw->mac.autoc_read(hw);
3609 hw->mac.autoc_write(hw, hw->mac.orig_autoc);
3610 hw->mac.orig_link_settings_stored = true;
3612 hw->mac.orig_autoc = autoc;
3615 /* Store the permanent mac address */
3616 hw->mac.get_mac_addr(hw, hw->mac.perm_addr);
3619 * Store MAC address from RAR0, clear receive address registers, and
3620 * clear the multicast table. Also reset num_rar_entries to 128,
3621 * since we modify this value when programming the SAN MAC address.
3623 hw->mac.num_rar_entries = 128;
3624 hw->mac.init_rx_addrs(hw);
3626 /* Store the permanent SAN mac address */
3627 hw->mac.get_san_mac_addr(hw, hw->mac.san_addr);
3629 /* Add the SAN MAC address to the RAR only if it's a valid address */
3630 if (txgbe_validate_mac_addr(hw->mac.san_addr) == 0) {
3631 /* Save the SAN MAC RAR index */
3632 hw->mac.san_mac_rar_index = hw->mac.num_rar_entries - 1;
3634 hw->mac.set_rar(hw, hw->mac.san_mac_rar_index,
3635 hw->mac.san_addr, 0, true);
3637 /* clear VMDq pool/queue selection for this RAR */
3638 hw->mac.clear_vmdq(hw, hw->mac.san_mac_rar_index,
3641 /* Reserve the last RAR for the SAN MAC address */
3642 hw->mac.num_rar_entries--;
3645 /* Store the alternative WWNN/WWPN prefix */
3646 hw->mac.get_wwn_prefix(hw, &hw->mac.wwnn_prefix,
3647 &hw->mac.wwpn_prefix);
3653 * txgbe_start_hw_raptor - Prepare hardware for Tx/Rx
3654 * @hw: pointer to hardware structure
3656 * Starts the hardware using the generic start_hw function
3657 * and the generation start_hw function.
3658 * Then performs revision-specific operations, if any.
3660 s32 txgbe_start_hw_raptor(struct txgbe_hw *hw)
3664 DEBUGFUNC("txgbe_start_hw_raptor");
3666 err = txgbe_start_hw(hw);
3670 err = txgbe_start_hw_gen2(hw);
3674 /* We need to run link autotry after the driver loads */
3675 hw->mac.autotry_restart = true;
3682 * txgbe_enable_rx_dma_raptor - Enable the Rx DMA unit
3683 * @hw: pointer to hardware structure
3684 * @regval: register value to write to RXCTRL
3686 * Enables the Rx DMA unit
3688 s32 txgbe_enable_rx_dma_raptor(struct txgbe_hw *hw, u32 regval)
3690 DEBUGFUNC("txgbe_enable_rx_dma_raptor");
3693 * Workaround silicon errata when enabling the Rx datapath.
3694 * If traffic is incoming before we enable the Rx unit, it could hang
3695 * the Rx DMA unit. Therefore, make sure the security engine is
3696 * completely disabled prior to enabling the Rx unit.
3699 hw->mac.disable_sec_rx_path(hw);
3701 if (regval & TXGBE_PBRXCTL_ENA)
3702 txgbe_enable_rx(hw);
3704 txgbe_disable_rx(hw);
3706 hw->mac.enable_sec_rx_path(hw);
3712 * txgbe_verify_lesm_fw_enabled_raptor - Checks LESM FW module state.
3713 * @hw: pointer to hardware structure
3715 * Returns true if the LESM FW module is present and enabled. Otherwise
3716 * returns false. Smart Speed must be disabled if LESM FW module is enabled.
3718 bool txgbe_verify_lesm_fw_enabled_raptor(struct txgbe_hw *hw)
3720 bool lesm_enabled = false;
3721 u16 fw_offset, fw_lesm_param_offset, fw_lesm_state;
3724 DEBUGFUNC("txgbe_verify_lesm_fw_enabled_raptor");
3726 /* get the offset to the Firmware Module block */
3727 status = hw->rom.read16(hw, TXGBE_FW_PTR, &fw_offset);
3729 if (status != 0 || fw_offset == 0 || fw_offset == 0xFFFF)
3732 /* get the offset to the LESM Parameters block */
3733 status = hw->rom.read16(hw, (fw_offset +
3734 TXGBE_FW_LESM_PARAMETERS_PTR),
3735 &fw_lesm_param_offset);
3738 fw_lesm_param_offset == 0 || fw_lesm_param_offset == 0xFFFF)
3741 /* get the LESM state word */
3742 status = hw->rom.read16(hw, (fw_lesm_param_offset +
3743 TXGBE_FW_LESM_STATE_1),
3746 if (status == 0 && (fw_lesm_state & TXGBE_FW_LESM_STATE_ENABLED))
3747 lesm_enabled = true;
3750 lesm_enabled = false;
3751 return lesm_enabled;
3755 * txgbe_reset_pipeline_raptor - perform pipeline reset
3757 * @hw: pointer to hardware structure
3759 * Reset pipeline by asserting Restart_AN together with LMS change to ensure
3760 * full pipeline reset. This function assumes the SW/FW lock is held.
3762 s32 txgbe_reset_pipeline_raptor(struct txgbe_hw *hw)
3767 autoc = hw->mac.autoc_read(hw);
3769 /* Enable link if disabled in NVM */
3770 if (autoc & TXGBE_AUTOC_LINK_DIA_MASK)
3771 autoc &= ~TXGBE_AUTOC_LINK_DIA_MASK;
3773 autoc |= TXGBE_AUTOC_AN_RESTART;
3774 /* Write AUTOC register with toggled LMS[2] bit and Restart_AN */
3775 hw->mac.autoc_write(hw, autoc ^ TXGBE_AUTOC_LMS_AN);
3777 /* Write AUTOC register with original LMS field and Restart_AN */
3778 hw->mac.autoc_write(hw, autoc);