1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2015-2020
5 #include "txgbe_type.h"
8 #include "txgbe_eeprom.h"
12 #define TXGBE_RAPTOR_MAX_TX_QUEUES 128
13 #define TXGBE_RAPTOR_MAX_RX_QUEUES 128
14 #define TXGBE_RAPTOR_RAR_ENTRIES 128
15 #define TXGBE_RAPTOR_MC_TBL_SIZE 128
16 #define TXGBE_RAPTOR_VFT_TBL_SIZE 128
18 static s32 txgbe_setup_copper_link_raptor(struct txgbe_hw *hw,
20 bool autoneg_wait_to_complete);
22 static s32 txgbe_mta_vector(struct txgbe_hw *hw, u8 *mc_addr);
23 static s32 txgbe_get_san_mac_addr_offset(struct txgbe_hw *hw,
27 * txgbe_start_hw - Prepare hardware for Tx/Rx
28 * @hw: pointer to hardware structure
30 * Starts the hardware by filling the bus info structure and media type, clears
31 * all on chip counters, initializes receive address registers, multicast
32 * table, VLAN filter table, calls routine to set up link and flow control
33 * settings, and leaves transmit and receive units disabled and uninitialized
35 s32 txgbe_start_hw(struct txgbe_hw *hw)
39 DEBUGFUNC("txgbe_start_hw");
41 /* Set the media type */
42 hw->phy.media_type = hw->phy.get_media_type(hw);
44 /* Clear the VLAN filter table */
45 hw->mac.clear_vfta(hw);
47 /* Clear statistics registers */
48 hw->mac.clear_hw_cntrs(hw);
50 /* Cache bit indicating need for crosstalk fix */
51 switch (hw->mac.type) {
52 case txgbe_mac_raptor:
53 hw->mac.get_device_caps(hw, &device_caps);
54 if (device_caps & TXGBE_DEVICE_CAPS_NO_CROSSTALK_WR)
55 hw->need_crosstalk_fix = false;
57 hw->need_crosstalk_fix = true;
60 hw->need_crosstalk_fix = false;
64 /* Clear adapter stopped flag */
65 hw->adapter_stopped = false;
71 * txgbe_start_hw_gen2 - Init sequence for common device family
72 * @hw: pointer to hw structure
74 * Performs the init sequence common to the second generation
77 s32 txgbe_start_hw_gen2(struct txgbe_hw *hw)
81 /* Clear the rate limiters */
82 for (i = 0; i < hw->mac.max_tx_queues; i++) {
83 wr32(hw, TXGBE_ARBPOOLIDX, i);
84 wr32(hw, TXGBE_ARBTXRATE, 0);
88 /* We need to run link autotry after the driver loads */
89 hw->mac.autotry_restart = true;
95 * txgbe_init_hw - Generic hardware initialization
96 * @hw: pointer to hardware structure
98 * Initialize the hardware by resetting the hardware, filling the bus info
99 * structure and media type, clears all on chip counters, initializes receive
100 * address registers, multicast table, VLAN filter table, calls routine to set
101 * up link and flow control settings, and leaves transmit and receive units
102 * disabled and uninitialized
104 s32 txgbe_init_hw(struct txgbe_hw *hw)
108 DEBUGFUNC("txgbe_init_hw");
110 /* Reset the hardware */
111 status = hw->mac.reset_hw(hw);
112 if (status == 0 || status == TXGBE_ERR_SFP_NOT_PRESENT) {
114 status = hw->mac.start_hw(hw);
118 DEBUGOUT("Failed to initialize HW, STATUS = %d\n", status);
124 * txgbe_clear_hw_cntrs - Generic clear hardware counters
125 * @hw: pointer to hardware structure
127 * Clears all hardware statistics counters by reading them from the hardware
128 * Statistics counters are clear on read.
130 s32 txgbe_clear_hw_cntrs(struct txgbe_hw *hw)
134 DEBUGFUNC("txgbe_clear_hw_cntrs");
137 /* don't write clear queue stats */
138 for (i = 0; i < TXGBE_MAX_QP; i++) {
139 hw->qp_last[i].rx_qp_packets = 0;
140 hw->qp_last[i].tx_qp_packets = 0;
141 hw->qp_last[i].rx_qp_bytes = 0;
142 hw->qp_last[i].tx_qp_bytes = 0;
143 hw->qp_last[i].rx_qp_mc_packets = 0;
147 for (i = 0; i < TXGBE_MAX_UP; i++) {
148 rd32(hw, TXGBE_PBRXUPXON(i));
149 rd32(hw, TXGBE_PBRXUPXOFF(i));
150 rd32(hw, TXGBE_PBTXUPXON(i));
151 rd32(hw, TXGBE_PBTXUPXOFF(i));
152 rd32(hw, TXGBE_PBTXUPOFF(i));
154 rd32(hw, TXGBE_PBRXMISS(i));
156 rd32(hw, TXGBE_PBRXLNKXON);
157 rd32(hw, TXGBE_PBRXLNKXOFF);
158 rd32(hw, TXGBE_PBTXLNKXON);
159 rd32(hw, TXGBE_PBTXLNKXOFF);
162 rd32(hw, TXGBE_DMARXPKT);
163 rd32(hw, TXGBE_DMATXPKT);
165 rd64(hw, TXGBE_DMARXOCTL);
166 rd64(hw, TXGBE_DMATXOCTL);
169 rd64(hw, TXGBE_MACRXERRCRCL);
170 rd64(hw, TXGBE_MACRXMPKTL);
171 rd64(hw, TXGBE_MACTXMPKTL);
173 rd64(hw, TXGBE_MACRXPKTL);
174 rd64(hw, TXGBE_MACTXPKTL);
175 rd64(hw, TXGBE_MACRXGBOCTL);
177 rd64(hw, TXGBE_MACRXOCTL);
178 rd32(hw, TXGBE_MACTXOCTL);
180 rd64(hw, TXGBE_MACRX1TO64L);
181 rd64(hw, TXGBE_MACRX65TO127L);
182 rd64(hw, TXGBE_MACRX128TO255L);
183 rd64(hw, TXGBE_MACRX256TO511L);
184 rd64(hw, TXGBE_MACRX512TO1023L);
185 rd64(hw, TXGBE_MACRX1024TOMAXL);
186 rd64(hw, TXGBE_MACTX1TO64L);
187 rd64(hw, TXGBE_MACTX65TO127L);
188 rd64(hw, TXGBE_MACTX128TO255L);
189 rd64(hw, TXGBE_MACTX256TO511L);
190 rd64(hw, TXGBE_MACTX512TO1023L);
191 rd64(hw, TXGBE_MACTX1024TOMAXL);
193 rd64(hw, TXGBE_MACRXERRLENL);
194 rd32(hw, TXGBE_MACRXOVERSIZE);
195 rd32(hw, TXGBE_MACRXJABBER);
198 rd32(hw, TXGBE_FCOECRC);
199 rd32(hw, TXGBE_FCOELAST);
200 rd32(hw, TXGBE_FCOERPDC);
201 rd32(hw, TXGBE_FCOEPRC);
202 rd32(hw, TXGBE_FCOEPTC);
203 rd32(hw, TXGBE_FCOEDWRC);
204 rd32(hw, TXGBE_FCOEDWTC);
206 /* Flow Director Stats */
207 rd32(hw, TXGBE_FDIRMATCH);
208 rd32(hw, TXGBE_FDIRMISS);
209 rd32(hw, TXGBE_FDIRUSED);
210 rd32(hw, TXGBE_FDIRUSED);
211 rd32(hw, TXGBE_FDIRFAIL);
212 rd32(hw, TXGBE_FDIRFAIL);
215 rd32(hw, TXGBE_LSECTX_UTPKT);
216 rd32(hw, TXGBE_LSECTX_ENCPKT);
217 rd32(hw, TXGBE_LSECTX_PROTPKT);
218 rd32(hw, TXGBE_LSECTX_ENCOCT);
219 rd32(hw, TXGBE_LSECTX_PROTOCT);
220 rd32(hw, TXGBE_LSECRX_UTPKT);
221 rd32(hw, TXGBE_LSECRX_BTPKT);
222 rd32(hw, TXGBE_LSECRX_NOSCIPKT);
223 rd32(hw, TXGBE_LSECRX_UNSCIPKT);
224 rd32(hw, TXGBE_LSECRX_DECOCT);
225 rd32(hw, TXGBE_LSECRX_VLDOCT);
226 rd32(hw, TXGBE_LSECRX_UNCHKPKT);
227 rd32(hw, TXGBE_LSECRX_DLYPKT);
228 rd32(hw, TXGBE_LSECRX_LATEPKT);
229 for (i = 0; i < 2; i++) {
230 rd32(hw, TXGBE_LSECRX_OKPKT(i));
231 rd32(hw, TXGBE_LSECRX_INVPKT(i));
232 rd32(hw, TXGBE_LSECRX_BADPKT(i));
234 rd32(hw, TXGBE_LSECRX_INVSAPKT);
235 rd32(hw, TXGBE_LSECRX_BADSAPKT);
241 * txgbe_get_mac_addr - Generic get MAC address
242 * @hw: pointer to hardware structure
243 * @mac_addr: Adapter MAC address
245 * Reads the adapter's MAC address from first Receive Address Register (RAR0)
246 * A reset of the adapter must be performed prior to calling this function
247 * in order for the MAC address to have been loaded from the EEPROM into RAR0
249 s32 txgbe_get_mac_addr(struct txgbe_hw *hw, u8 *mac_addr)
255 DEBUGFUNC("txgbe_get_mac_addr");
257 wr32(hw, TXGBE_ETHADDRIDX, 0);
258 rar_high = rd32(hw, TXGBE_ETHADDRH);
259 rar_low = rd32(hw, TXGBE_ETHADDRL);
261 for (i = 0; i < 2; i++)
262 mac_addr[i] = (u8)(rar_high >> (1 - i) * 8);
264 for (i = 0; i < 4; i++)
265 mac_addr[i + 2] = (u8)(rar_low >> (3 - i) * 8);
271 * txgbe_set_lan_id_multi_port - Set LAN id for PCIe multiple port devices
272 * @hw: pointer to the HW structure
274 * Determines the LAN function id by reading memory-mapped registers and swaps
275 * the port value if requested, and set MAC instance for devices.
277 void txgbe_set_lan_id_multi_port(struct txgbe_hw *hw)
279 struct txgbe_bus_info *bus = &hw->bus;
282 DEBUGFUNC("txgbe_set_lan_id_multi_port_pcie");
284 reg = rd32(hw, TXGBE_PORTSTAT);
285 bus->lan_id = TXGBE_PORTSTAT_ID(reg);
287 /* check for single port */
288 reg = rd32(hw, TXGBE_PWR);
289 if (TXGBE_PWR_LANID(reg) == TXGBE_PWR_LANID_SWAP)
292 bus->func = bus->lan_id;
296 * txgbe_stop_hw - Generic stop Tx/Rx units
297 * @hw: pointer to hardware structure
299 * Sets the adapter_stopped flag within txgbe_hw struct. Clears interrupts,
300 * disables transmit and receive units. The adapter_stopped flag is used by
301 * the shared code and drivers to determine if the adapter is in a stopped
302 * state and should not touch the hardware.
304 s32 txgbe_stop_hw(struct txgbe_hw *hw)
309 DEBUGFUNC("txgbe_stop_hw");
312 * Set the adapter_stopped flag so other driver functions stop touching
315 hw->adapter_stopped = true;
317 /* Disable the receive unit */
318 txgbe_disable_rx(hw);
320 /* Clear interrupt mask to stop interrupts from being generated */
321 wr32(hw, TXGBE_IENMISC, 0);
322 wr32(hw, TXGBE_IMS(0), TXGBE_IMS_MASK);
323 wr32(hw, TXGBE_IMS(1), TXGBE_IMS_MASK);
325 /* Clear any pending interrupts, flush previous writes */
326 wr32(hw, TXGBE_ICRMISC, TXGBE_ICRMISC_MASK);
327 wr32(hw, TXGBE_ICR(0), TXGBE_ICR_MASK);
328 wr32(hw, TXGBE_ICR(1), TXGBE_ICR_MASK);
330 /* Disable the transmit unit. Each queue must be disabled. */
331 for (i = 0; i < hw->mac.max_tx_queues; i++)
332 wr32(hw, TXGBE_TXCFG(i), TXGBE_TXCFG_FLUSH);
334 /* Disable the receive unit by stopping each queue */
335 for (i = 0; i < hw->mac.max_rx_queues; i++) {
336 reg_val = rd32(hw, TXGBE_RXCFG(i));
337 reg_val &= ~TXGBE_RXCFG_ENA;
338 wr32(hw, TXGBE_RXCFG(i), reg_val);
341 /* flush all queues disables */
349 * txgbe_validate_mac_addr - Validate MAC address
350 * @mac_addr: pointer to MAC address.
352 * Tests a MAC address to ensure it is a valid Individual Address.
354 s32 txgbe_validate_mac_addr(u8 *mac_addr)
358 DEBUGFUNC("txgbe_validate_mac_addr");
360 /* Make sure it is not a multicast address */
361 if (TXGBE_IS_MULTICAST(mac_addr)) {
362 status = TXGBE_ERR_INVALID_MAC_ADDR;
363 /* Not a broadcast address */
364 } else if (TXGBE_IS_BROADCAST(mac_addr)) {
365 status = TXGBE_ERR_INVALID_MAC_ADDR;
366 /* Reject the zero address */
367 } else if (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 &&
368 mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0) {
369 status = TXGBE_ERR_INVALID_MAC_ADDR;
375 * txgbe_set_rar - Set Rx address register
376 * @hw: pointer to hardware structure
377 * @index: Receive address register to write
378 * @addr: Address to put into receive address register
379 * @vmdq: VMDq "set" or "pool" index
380 * @enable_addr: set flag that address is active
382 * Puts an ethernet address into a receive address register.
384 s32 txgbe_set_rar(struct txgbe_hw *hw, u32 index, u8 *addr, u32 vmdq,
387 u32 rar_low, rar_high;
388 u32 rar_entries = hw->mac.num_rar_entries;
390 DEBUGFUNC("txgbe_set_rar");
392 /* Make sure we are using a valid rar index range */
393 if (index >= rar_entries) {
394 DEBUGOUT("RAR index %d is out of range.\n", index);
395 return TXGBE_ERR_INVALID_ARGUMENT;
398 /* setup VMDq pool selection before this RAR gets enabled */
399 hw->mac.set_vmdq(hw, index, vmdq);
402 * HW expects these in little endian so we reverse the byte
403 * order from network order (big endian) to little endian
405 rar_low = TXGBE_ETHADDRL_AD0(addr[5]) |
406 TXGBE_ETHADDRL_AD1(addr[4]) |
407 TXGBE_ETHADDRL_AD2(addr[3]) |
408 TXGBE_ETHADDRL_AD3(addr[2]);
410 * Some parts put the VMDq setting in the extra RAH bits,
411 * so save everything except the lower 16 bits that hold part
412 * of the address and the address valid bit.
414 rar_high = rd32(hw, TXGBE_ETHADDRH);
415 rar_high &= ~TXGBE_ETHADDRH_AD_MASK;
416 rar_high |= (TXGBE_ETHADDRH_AD4(addr[1]) |
417 TXGBE_ETHADDRH_AD5(addr[0]));
419 rar_high &= ~TXGBE_ETHADDRH_VLD;
420 if (enable_addr != 0)
421 rar_high |= TXGBE_ETHADDRH_VLD;
423 wr32(hw, TXGBE_ETHADDRIDX, index);
424 wr32(hw, TXGBE_ETHADDRL, rar_low);
425 wr32(hw, TXGBE_ETHADDRH, rar_high);
431 * txgbe_clear_rar - Remove Rx address register
432 * @hw: pointer to hardware structure
433 * @index: Receive address register to write
435 * Clears an ethernet address from a receive address register.
437 s32 txgbe_clear_rar(struct txgbe_hw *hw, u32 index)
440 u32 rar_entries = hw->mac.num_rar_entries;
442 DEBUGFUNC("txgbe_clear_rar");
444 /* Make sure we are using a valid rar index range */
445 if (index >= rar_entries) {
446 DEBUGOUT("RAR index %d is out of range.\n", index);
447 return TXGBE_ERR_INVALID_ARGUMENT;
451 * Some parts put the VMDq setting in the extra RAH bits,
452 * so save everything except the lower 16 bits that hold part
453 * of the address and the address valid bit.
455 wr32(hw, TXGBE_ETHADDRIDX, index);
456 rar_high = rd32(hw, TXGBE_ETHADDRH);
457 rar_high &= ~(TXGBE_ETHADDRH_AD_MASK | TXGBE_ETHADDRH_VLD);
459 wr32(hw, TXGBE_ETHADDRL, 0);
460 wr32(hw, TXGBE_ETHADDRH, rar_high);
462 /* clear VMDq pool/queue selection for this RAR */
463 hw->mac.clear_vmdq(hw, index, BIT_MASK32);
469 * txgbe_init_rx_addrs - Initializes receive address filters.
470 * @hw: pointer to hardware structure
472 * Places the MAC address in receive address register 0 and clears the rest
473 * of the receive address registers. Clears the multicast table. Assumes
474 * the receiver is in reset when the routine is called.
476 s32 txgbe_init_rx_addrs(struct txgbe_hw *hw)
480 u32 rar_entries = hw->mac.num_rar_entries;
482 DEBUGFUNC("txgbe_init_rx_addrs");
485 * If the current mac address is valid, assume it is a software override
486 * to the permanent address.
487 * Otherwise, use the permanent address from the eeprom.
489 if (txgbe_validate_mac_addr(hw->mac.addr) ==
490 TXGBE_ERR_INVALID_MAC_ADDR) {
491 /* Get the MAC address from the RAR0 for later reference */
492 hw->mac.get_mac_addr(hw, hw->mac.addr);
494 DEBUGOUT(" Keeping Current RAR0 Addr =%.2X %.2X %.2X ",
495 hw->mac.addr[0], hw->mac.addr[1],
497 DEBUGOUT("%.2X %.2X %.2X\n", hw->mac.addr[3],
498 hw->mac.addr[4], hw->mac.addr[5]);
500 /* Setup the receive address. */
501 DEBUGOUT("Overriding MAC Address in RAR[0]\n");
502 DEBUGOUT(" New MAC Addr =%.2X %.2X %.2X ",
503 hw->mac.addr[0], hw->mac.addr[1],
505 DEBUGOUT("%.2X %.2X %.2X\n", hw->mac.addr[3],
506 hw->mac.addr[4], hw->mac.addr[5]);
508 hw->mac.set_rar(hw, 0, hw->mac.addr, 0, true);
511 /* clear VMDq pool/queue selection for RAR 0 */
512 hw->mac.clear_vmdq(hw, 0, BIT_MASK32);
514 hw->addr_ctrl.overflow_promisc = 0;
516 hw->addr_ctrl.rar_used_count = 1;
518 /* Zero out the other receive addresses. */
519 DEBUGOUT("Clearing RAR[1-%d]\n", rar_entries - 1);
520 for (i = 1; i < rar_entries; i++) {
521 wr32(hw, TXGBE_ETHADDRIDX, i);
522 wr32(hw, TXGBE_ETHADDRL, 0);
523 wr32(hw, TXGBE_ETHADDRH, 0);
527 hw->addr_ctrl.mta_in_use = 0;
528 psrctl = rd32(hw, TXGBE_PSRCTL);
529 psrctl &= ~(TXGBE_PSRCTL_ADHF12_MASK | TXGBE_PSRCTL_MCHFENA);
530 psrctl |= TXGBE_PSRCTL_ADHF12(hw->mac.mc_filter_type);
531 wr32(hw, TXGBE_PSRCTL, psrctl);
533 DEBUGOUT(" Clearing MTA\n");
534 for (i = 0; i < hw->mac.mcft_size; i++)
535 wr32(hw, TXGBE_MCADDRTBL(i), 0);
537 txgbe_init_uta_tables(hw);
543 * txgbe_mta_vector - Determines bit-vector in multicast table to set
544 * @hw: pointer to hardware structure
545 * @mc_addr: the multicast address
547 * Extracts the 12 bits, from a multicast address, to determine which
548 * bit-vector to set in the multicast table. The hardware uses 12 bits, from
549 * incoming rx multicast addresses, to determine the bit-vector to check in
550 * the MTA. Which of the 4 combination, of 12-bits, the hardware uses is set
551 * by the MO field of the PSRCTRL. The MO field is set during initialization
554 static s32 txgbe_mta_vector(struct txgbe_hw *hw, u8 *mc_addr)
558 DEBUGFUNC("txgbe_mta_vector");
560 switch (hw->mac.mc_filter_type) {
561 case 0: /* use bits [47:36] of the address */
562 vector = ((mc_addr[4] >> 4) | (((u16)mc_addr[5]) << 4));
564 case 1: /* use bits [46:35] of the address */
565 vector = ((mc_addr[4] >> 3) | (((u16)mc_addr[5]) << 5));
567 case 2: /* use bits [45:34] of the address */
568 vector = ((mc_addr[4] >> 2) | (((u16)mc_addr[5]) << 6));
570 case 3: /* use bits [43:32] of the address */
571 vector = ((mc_addr[4]) | (((u16)mc_addr[5]) << 8));
573 default: /* Invalid mc_filter_type */
574 DEBUGOUT("MC filter type param set incorrectly\n");
579 /* vector can only be 12-bits or boundary will be exceeded */
585 * txgbe_set_mta - Set bit-vector in multicast table
586 * @hw: pointer to hardware structure
587 * @mc_addr: Multicast address
589 * Sets the bit-vector in the multicast table.
591 void txgbe_set_mta(struct txgbe_hw *hw, u8 *mc_addr)
597 DEBUGFUNC("txgbe_set_mta");
599 hw->addr_ctrl.mta_in_use++;
601 vector = txgbe_mta_vector(hw, mc_addr);
602 DEBUGOUT(" bit-vector = 0x%03X\n", vector);
605 * The MTA is a register array of 128 32-bit registers. It is treated
606 * like an array of 4096 bits. We want to set bit
607 * BitArray[vector_value]. So we figure out what register the bit is
608 * in, read it, OR in the new bit, then write back the new value. The
609 * register is determined by the upper 7 bits of the vector value and
610 * the bit within that register are determined by the lower 5 bits of
613 vector_reg = (vector >> 5) & 0x7F;
614 vector_bit = vector & 0x1F;
615 hw->mac.mta_shadow[vector_reg] |= (1 << vector_bit);
619 * txgbe_update_mc_addr_list - Updates MAC list of multicast addresses
620 * @hw: pointer to hardware structure
621 * @mc_addr_list: the list of new multicast addresses
622 * @mc_addr_count: number of addresses
623 * @next: iterator function to walk the multicast address list
624 * @clear: flag, when set clears the table beforehand
626 * When the clear flag is set, the given list replaces any existing list.
627 * Hashes the given addresses into the multicast table.
629 s32 txgbe_update_mc_addr_list(struct txgbe_hw *hw, u8 *mc_addr_list,
630 u32 mc_addr_count, txgbe_mc_addr_itr next,
636 DEBUGFUNC("txgbe_update_mc_addr_list");
639 * Set the new number of MC addresses that we are being requested to
642 hw->addr_ctrl.num_mc_addrs = mc_addr_count;
643 hw->addr_ctrl.mta_in_use = 0;
645 /* Clear mta_shadow */
647 DEBUGOUT(" Clearing MTA\n");
648 memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow));
651 /* Update mta_shadow */
652 for (i = 0; i < mc_addr_count; i++) {
653 DEBUGOUT(" Adding the multicast addresses:\n");
654 txgbe_set_mta(hw, next(hw, &mc_addr_list, &vmdq));
658 for (i = 0; i < hw->mac.mcft_size; i++)
659 wr32a(hw, TXGBE_MCADDRTBL(0), i,
660 hw->mac.mta_shadow[i]);
662 if (hw->addr_ctrl.mta_in_use > 0) {
663 u32 psrctl = rd32(hw, TXGBE_PSRCTL);
664 psrctl &= ~(TXGBE_PSRCTL_ADHF12_MASK | TXGBE_PSRCTL_MCHFENA);
665 psrctl |= TXGBE_PSRCTL_MCHFENA |
666 TXGBE_PSRCTL_ADHF12(hw->mac.mc_filter_type);
667 wr32(hw, TXGBE_PSRCTL, psrctl);
670 DEBUGOUT("txgbe update mc addr list complete\n");
675 * txgbe_acquire_swfw_sync - Acquire SWFW semaphore
676 * @hw: pointer to hardware structure
677 * @mask: Mask to specify which semaphore to acquire
679 * Acquires the SWFW semaphore through the MNGSEM register for the specified
680 * function (CSR, PHY0, PHY1, EEPROM, Flash)
682 s32 txgbe_acquire_swfw_sync(struct txgbe_hw *hw, u32 mask)
685 u32 swmask = TXGBE_MNGSEM_SW(mask);
686 u32 fwmask = TXGBE_MNGSEM_FW(mask);
690 DEBUGFUNC("txgbe_acquire_swfw_sync");
692 for (i = 0; i < timeout; i++) {
694 * SW NVM semaphore bit is used for access to all
695 * SW_FW_SYNC bits (not just NVM)
697 if (txgbe_get_eeprom_semaphore(hw))
698 return TXGBE_ERR_SWFW_SYNC;
700 mngsem = rd32(hw, TXGBE_MNGSEM);
701 if (mngsem & (fwmask | swmask)) {
702 /* Resource is currently in use by FW or SW */
703 txgbe_release_eeprom_semaphore(hw);
707 wr32(hw, TXGBE_MNGSEM, mngsem);
708 txgbe_release_eeprom_semaphore(hw);
713 /* If time expired clear the bits holding the lock and retry */
714 if (mngsem & (fwmask | swmask))
715 txgbe_release_swfw_sync(hw, mngsem & (fwmask | swmask));
718 return TXGBE_ERR_SWFW_SYNC;
722 * txgbe_release_swfw_sync - Release SWFW semaphore
723 * @hw: pointer to hardware structure
724 * @mask: Mask to specify which semaphore to release
726 * Releases the SWFW semaphore through the MNGSEM register for the specified
727 * function (CSR, PHY0, PHY1, EEPROM, Flash)
729 void txgbe_release_swfw_sync(struct txgbe_hw *hw, u32 mask)
734 DEBUGFUNC("txgbe_release_swfw_sync");
736 txgbe_get_eeprom_semaphore(hw);
738 mngsem = rd32(hw, TXGBE_MNGSEM);
740 wr32(hw, TXGBE_MNGSEM, mngsem);
742 txgbe_release_eeprom_semaphore(hw);
746 * txgbe_disable_sec_rx_path - Stops the receive data path
747 * @hw: pointer to hardware structure
749 * Stops the receive data path and waits for the HW to internally empty
750 * the Rx security block
752 s32 txgbe_disable_sec_rx_path(struct txgbe_hw *hw)
754 #define TXGBE_MAX_SECRX_POLL 4000
759 DEBUGFUNC("txgbe_disable_sec_rx_path");
761 secrxreg = rd32(hw, TXGBE_SECRXCTL);
762 secrxreg |= TXGBE_SECRXCTL_XDSA;
763 wr32(hw, TXGBE_SECRXCTL, secrxreg);
764 for (i = 0; i < TXGBE_MAX_SECRX_POLL; i++) {
765 secrxreg = rd32(hw, TXGBE_SECRXSTAT);
766 if (!(secrxreg & TXGBE_SECRXSTAT_RDY))
767 /* Use interrupt-safe sleep just in case */
773 /* For informational purposes only */
774 if (i >= TXGBE_MAX_SECRX_POLL)
775 DEBUGOUT("Rx unit being enabled before security "
776 "path fully disabled. Continuing with init.\n");
782 * txgbe_enable_sec_rx_path - Enables the receive data path
783 * @hw: pointer to hardware structure
785 * Enables the receive data path.
787 s32 txgbe_enable_sec_rx_path(struct txgbe_hw *hw)
791 DEBUGFUNC("txgbe_enable_sec_rx_path");
793 secrxreg = rd32(hw, TXGBE_SECRXCTL);
794 secrxreg &= ~TXGBE_SECRXCTL_XDSA;
795 wr32(hw, TXGBE_SECRXCTL, secrxreg);
802 * txgbe_disable_sec_tx_path - Stops the transmit data path
803 * @hw: pointer to hardware structure
805 * Stops the transmit data path and waits for the HW to internally empty
806 * the Tx security block
808 int txgbe_disable_sec_tx_path(struct txgbe_hw *hw)
810 #define TXGBE_MAX_SECTX_POLL 40
815 sectxreg = rd32(hw, TXGBE_SECTXCTL);
816 sectxreg |= TXGBE_SECTXCTL_XDSA;
817 wr32(hw, TXGBE_SECTXCTL, sectxreg);
818 for (i = 0; i < TXGBE_MAX_SECTX_POLL; i++) {
819 sectxreg = rd32(hw, TXGBE_SECTXSTAT);
820 if (sectxreg & TXGBE_SECTXSTAT_RDY)
822 /* Use interrupt-safe sleep just in case */
826 /* For informational purposes only */
827 if (i >= TXGBE_MAX_SECTX_POLL)
828 PMD_DRV_LOG(DEBUG, "Tx unit being enabled before security "
829 "path fully disabled. Continuing with init.");
835 * txgbe_enable_sec_tx_path - Enables the transmit data path
836 * @hw: pointer to hardware structure
838 * Enables the transmit data path.
840 int txgbe_enable_sec_tx_path(struct txgbe_hw *hw)
844 sectxreg = rd32(hw, TXGBE_SECTXCTL);
845 sectxreg &= ~TXGBE_SECTXCTL_XDSA;
846 wr32(hw, TXGBE_SECTXCTL, sectxreg);
853 * txgbe_get_san_mac_addr_offset - Get SAN MAC address offset from the EEPROM
854 * @hw: pointer to hardware structure
855 * @san_mac_offset: SAN MAC address offset
857 * This function will read the EEPROM location for the SAN MAC address
858 * pointer, and returns the value at that location. This is used in both
859 * get and set mac_addr routines.
861 static s32 txgbe_get_san_mac_addr_offset(struct txgbe_hw *hw,
866 DEBUGFUNC("txgbe_get_san_mac_addr_offset");
869 * First read the EEPROM pointer to see if the MAC addresses are
872 err = hw->rom.readw_sw(hw, TXGBE_SAN_MAC_ADDR_PTR,
875 DEBUGOUT("eeprom at offset %d failed",
876 TXGBE_SAN_MAC_ADDR_PTR);
883 * txgbe_get_san_mac_addr - SAN MAC address retrieval from the EEPROM
884 * @hw: pointer to hardware structure
885 * @san_mac_addr: SAN MAC address
887 * Reads the SAN MAC address from the EEPROM, if it's available. This is
888 * per-port, so set_lan_id() must be called before reading the addresses.
889 * set_lan_id() is called by identify_sfp(), but this cannot be relied
890 * upon for non-SFP connections, so we must call it here.
892 s32 txgbe_get_san_mac_addr(struct txgbe_hw *hw, u8 *san_mac_addr)
894 u16 san_mac_data, san_mac_offset;
898 DEBUGFUNC("txgbe_get_san_mac_addr");
901 * First read the EEPROM pointer to see if the MAC addresses are
902 * available. If they're not, no point in calling set_lan_id() here.
904 err = txgbe_get_san_mac_addr_offset(hw, &san_mac_offset);
905 if (err || san_mac_offset == 0 || san_mac_offset == 0xFFFF)
906 goto san_mac_addr_out;
908 /* apply the port offset to the address offset */
909 (hw->bus.func) ? (san_mac_offset += TXGBE_SAN_MAC_ADDR_PORT1_OFFSET) :
910 (san_mac_offset += TXGBE_SAN_MAC_ADDR_PORT0_OFFSET);
911 for (i = 0; i < 3; i++) {
912 err = hw->rom.read16(hw, san_mac_offset,
915 DEBUGOUT("eeprom read at offset %d failed",
917 goto san_mac_addr_out;
919 san_mac_addr[i * 2] = (u8)(san_mac_data);
920 san_mac_addr[i * 2 + 1] = (u8)(san_mac_data >> 8);
927 * No addresses available in this EEPROM. It's not an
928 * error though, so just wipe the local address and return.
930 for (i = 0; i < 6; i++)
931 san_mac_addr[i] = 0xFF;
936 * txgbe_set_san_mac_addr - Write the SAN MAC address to the EEPROM
937 * @hw: pointer to hardware structure
938 * @san_mac_addr: SAN MAC address
940 * Write a SAN MAC address to the EEPROM.
942 s32 txgbe_set_san_mac_addr(struct txgbe_hw *hw, u8 *san_mac_addr)
945 u16 san_mac_data, san_mac_offset;
948 DEBUGFUNC("txgbe_set_san_mac_addr");
950 /* Look for SAN mac address pointer. If not defined, return */
951 err = txgbe_get_san_mac_addr_offset(hw, &san_mac_offset);
952 if (err || san_mac_offset == 0 || san_mac_offset == 0xFFFF)
953 return TXGBE_ERR_NO_SAN_ADDR_PTR;
955 /* Apply the port offset to the address offset */
956 (hw->bus.func) ? (san_mac_offset += TXGBE_SAN_MAC_ADDR_PORT1_OFFSET) :
957 (san_mac_offset += TXGBE_SAN_MAC_ADDR_PORT0_OFFSET);
959 for (i = 0; i < 3; i++) {
960 san_mac_data = (u16)((u16)(san_mac_addr[i * 2 + 1]) << 8);
961 san_mac_data |= (u16)(san_mac_addr[i * 2]);
962 hw->rom.write16(hw, san_mac_offset, san_mac_data);
970 * txgbe_clear_vmdq - Disassociate a VMDq pool index from a rx address
971 * @hw: pointer to hardware struct
972 * @rar: receive address register index to disassociate
973 * @vmdq: VMDq pool index to remove from the rar
975 s32 txgbe_clear_vmdq(struct txgbe_hw *hw, u32 rar, u32 vmdq)
977 u32 mpsar_lo, mpsar_hi;
978 u32 rar_entries = hw->mac.num_rar_entries;
980 DEBUGFUNC("txgbe_clear_vmdq");
982 /* Make sure we are using a valid rar index range */
983 if (rar >= rar_entries) {
984 DEBUGOUT("RAR index %d is out of range.\n", rar);
985 return TXGBE_ERR_INVALID_ARGUMENT;
988 wr32(hw, TXGBE_ETHADDRIDX, rar);
989 mpsar_lo = rd32(hw, TXGBE_ETHADDRASSL);
990 mpsar_hi = rd32(hw, TXGBE_ETHADDRASSH);
992 if (TXGBE_REMOVED(hw->hw_addr))
995 if (!mpsar_lo && !mpsar_hi)
998 if (vmdq == BIT_MASK32) {
1000 wr32(hw, TXGBE_ETHADDRASSL, 0);
1004 wr32(hw, TXGBE_ETHADDRASSH, 0);
1007 } else if (vmdq < 32) {
1008 mpsar_lo &= ~(1 << vmdq);
1009 wr32(hw, TXGBE_ETHADDRASSL, mpsar_lo);
1011 mpsar_hi &= ~(1 << (vmdq - 32));
1012 wr32(hw, TXGBE_ETHADDRASSH, mpsar_hi);
1015 /* was that the last pool using this rar? */
1016 if (mpsar_lo == 0 && mpsar_hi == 0 &&
1017 rar != 0 && rar != hw->mac.san_mac_rar_index)
1018 hw->mac.clear_rar(hw, rar);
1024 * txgbe_set_vmdq - Associate a VMDq pool index with a rx address
1025 * @hw: pointer to hardware struct
1026 * @rar: receive address register index to associate with a VMDq index
1027 * @vmdq: VMDq pool index
1029 s32 txgbe_set_vmdq(struct txgbe_hw *hw, u32 rar, u32 vmdq)
1032 u32 rar_entries = hw->mac.num_rar_entries;
1034 DEBUGFUNC("txgbe_set_vmdq");
1036 /* Make sure we are using a valid rar index range */
1037 if (rar >= rar_entries) {
1038 DEBUGOUT("RAR index %d is out of range.\n", rar);
1039 return TXGBE_ERR_INVALID_ARGUMENT;
1042 wr32(hw, TXGBE_ETHADDRIDX, rar);
1044 mpsar = rd32(hw, TXGBE_ETHADDRASSL);
1046 wr32(hw, TXGBE_ETHADDRASSL, mpsar);
1048 mpsar = rd32(hw, TXGBE_ETHADDRASSH);
1049 mpsar |= 1 << (vmdq - 32);
1050 wr32(hw, TXGBE_ETHADDRASSH, mpsar);
1056 * txgbe_init_uta_tables - Initialize the Unicast Table Array
1057 * @hw: pointer to hardware structure
1059 s32 txgbe_init_uta_tables(struct txgbe_hw *hw)
1063 DEBUGFUNC("txgbe_init_uta_tables");
1064 DEBUGOUT(" Clearing UTA\n");
1066 for (i = 0; i < 128; i++)
1067 wr32(hw, TXGBE_UCADDRTBL(i), 0);
1073 * txgbe_find_vlvf_slot - find the vlanid or the first empty slot
1074 * @hw: pointer to hardware structure
1075 * @vlan: VLAN id to write to VLAN filter
1076 * @vlvf_bypass: true to find vlanid only, false returns first empty slot if
1080 * return the VLVF index where this VLAN id should be placed
1083 s32 txgbe_find_vlvf_slot(struct txgbe_hw *hw, u32 vlan, bool vlvf_bypass)
1085 s32 regindex, first_empty_slot;
1088 /* short cut the special case */
1092 /* if vlvf_bypass is set we don't want to use an empty slot, we
1093 * will simply bypass the VLVF if there are no entries present in the
1094 * VLVF that contain our VLAN
1096 first_empty_slot = vlvf_bypass ? TXGBE_ERR_NO_SPACE : 0;
1098 /* add VLAN enable bit for comparison */
1099 vlan |= TXGBE_PSRVLAN_EA;
1101 /* Search for the vlan id in the VLVF entries. Save off the first empty
1102 * slot found along the way.
1104 * pre-decrement loop covering (TXGBE_NUM_POOL - 1) .. 1
1106 for (regindex = TXGBE_NUM_POOL; --regindex;) {
1107 wr32(hw, TXGBE_PSRVLANIDX, regindex);
1108 bits = rd32(hw, TXGBE_PSRVLAN);
1111 if (!first_empty_slot && !bits)
1112 first_empty_slot = regindex;
1115 /* If we are here then we didn't find the VLAN. Return first empty
1116 * slot we found during our search, else error.
1118 if (!first_empty_slot)
1119 DEBUGOUT("No space in VLVF.\n");
1121 return first_empty_slot ? first_empty_slot : TXGBE_ERR_NO_SPACE;
1125 * txgbe_set_vfta - Set VLAN filter table
1126 * @hw: pointer to hardware structure
1127 * @vlan: VLAN id to write to VLAN filter
1128 * @vind: VMDq output index that maps queue to VLAN id in VLVFB
1129 * @vlan_on: boolean flag to turn on/off VLAN
1130 * @vlvf_bypass: boolean flag indicating updating default pool is okay
1132 * Turn on/off specified VLAN in the VLAN filter table.
1134 s32 txgbe_set_vfta(struct txgbe_hw *hw, u32 vlan, u32 vind,
1135 bool vlan_on, bool vlvf_bypass)
1137 u32 regidx, vfta_delta, vfta;
1140 DEBUGFUNC("txgbe_set_vfta");
1142 if (vlan > 4095 || vind > 63)
1143 return TXGBE_ERR_PARAM;
1146 * this is a 2 part operation - first the VFTA, then the
1147 * VLVF and VLVFB if VT Mode is set
1148 * We don't write the VFTA until we know the VLVF part succeeded.
1152 * The VFTA is a bitstring made up of 128 32-bit registers
1153 * that enable the particular VLAN id, much like the MTA:
1154 * bits[11-5]: which register
1155 * bits[4-0]: which bit in the register
1158 vfta_delta = 1 << (vlan % 32);
1159 vfta = rd32(hw, TXGBE_VLANTBL(regidx));
1162 * vfta_delta represents the difference between the current value
1163 * of vfta and the value we want in the register. Since the diff
1164 * is an XOR mask we can just update the vfta using an XOR
1166 vfta_delta &= vlan_on ? ~vfta : vfta;
1170 * Call txgbe_set_vlvf to set VLVFB and VLVF
1172 err = txgbe_set_vlvf(hw, vlan, vind, vlan_on, &vfta_delta,
1181 /* Update VFTA now that we are ready for traffic */
1183 wr32(hw, TXGBE_VLANTBL(regidx), vfta);
1189 * txgbe_set_vlvf - Set VLAN Pool Filter
1190 * @hw: pointer to hardware structure
1191 * @vlan: VLAN id to write to VLAN filter
1192 * @vind: VMDq output index that maps queue to VLAN id in PSRVLANPLM
1193 * @vlan_on: boolean flag to turn on/off VLAN in PSRVLAN
1194 * @vfta_delta: pointer to the difference between the current value
1195 * of PSRVLANPLM and the desired value
1196 * @vfta: the desired value of the VFTA
1197 * @vlvf_bypass: boolean flag indicating updating default pool is okay
1199 * Turn on/off specified bit in VLVF table.
1201 s32 txgbe_set_vlvf(struct txgbe_hw *hw, u32 vlan, u32 vind,
1202 bool vlan_on, u32 *vfta_delta, u32 vfta,
1209 DEBUGFUNC("txgbe_set_vlvf");
1211 if (vlan > 4095 || vind > 63)
1212 return TXGBE_ERR_PARAM;
1214 /* If VT Mode is set
1216 * make sure the vlan is in PSRVLAN
1217 * set the vind bit in the matching PSRVLANPLM
1219 * clear the pool bit and possibly the vind
1221 portctl = rd32(hw, TXGBE_PORTCTL);
1222 if (!(portctl & TXGBE_PORTCTL_NUMVT_MASK))
1225 vlvf_index = txgbe_find_vlvf_slot(hw, vlan, vlvf_bypass);
1229 wr32(hw, TXGBE_PSRVLANIDX, vlvf_index);
1230 bits = rd32(hw, TXGBE_PSRVLANPLM(vind / 32));
1232 /* set the pool bit */
1233 bits |= 1 << (vind % 32);
1237 /* clear the pool bit */
1238 bits ^= 1 << (vind % 32);
1241 !rd32(hw, TXGBE_PSRVLANPLM(vind / 32))) {
1242 /* Clear PSRVLANPLM first, then disable PSRVLAN. Otherwise
1243 * we run the risk of stray packets leaking into
1244 * the PF via the default pool
1247 wr32(hw, TXGBE_PSRVLANPLM(vlan / 32), vfta);
1249 /* disable VLVF and clear remaining bit from pool */
1250 wr32(hw, TXGBE_PSRVLAN, 0);
1251 wr32(hw, TXGBE_PSRVLANPLM(vind / 32), 0);
1256 /* If there are still bits set in the PSRVLANPLM registers
1257 * for the VLAN ID indicated we need to see if the
1258 * caller is requesting that we clear the PSRVLANPLM entry bit.
1259 * If the caller has requested that we clear the PSRVLANPLM
1260 * entry bit but there are still pools/VFs using this VLAN
1261 * ID entry then ignore the request. We're not worried
1262 * about the case where we're turning the PSRVLANPLM VLAN ID
1263 * entry bit on, only when requested to turn it off as
1264 * there may be multiple pools and/or VFs using the
1265 * VLAN ID entry. In that case we cannot clear the
1266 * PSRVLANPLM bit until all pools/VFs using that VLAN ID have also
1267 * been cleared. This will be indicated by "bits" being
1273 /* record pool change and enable VLAN ID if not already enabled */
1274 wr32(hw, TXGBE_PSRVLANPLM(vind / 32), bits);
1275 wr32(hw, TXGBE_PSRVLAN, TXGBE_PSRVLAN_EA | vlan);
1281 * txgbe_clear_vfta - Clear VLAN filter table
1282 * @hw: pointer to hardware structure
1284 * Clears the VLAN filer table, and the VMDq index associated with the filter
1286 s32 txgbe_clear_vfta(struct txgbe_hw *hw)
1290 DEBUGFUNC("txgbe_clear_vfta");
1292 for (offset = 0; offset < hw->mac.vft_size; offset++)
1293 wr32(hw, TXGBE_VLANTBL(offset), 0);
1295 for (offset = 0; offset < TXGBE_NUM_POOL; offset++) {
1296 wr32(hw, TXGBE_PSRVLANIDX, offset);
1297 wr32(hw, TXGBE_PSRVLAN, 0);
1298 wr32(hw, TXGBE_PSRVLANPLM(0), 0);
1299 wr32(hw, TXGBE_PSRVLANPLM(1), 0);
1306 * txgbe_need_crosstalk_fix - Determine if we need to do cross talk fix
1307 * @hw: pointer to hardware structure
1309 * Contains the logic to identify if we need to verify link for the
1312 static bool txgbe_need_crosstalk_fix(struct txgbe_hw *hw)
1314 /* Does FW say we need the fix */
1315 if (!hw->need_crosstalk_fix)
1318 /* Only consider SFP+ PHYs i.e. media type fiber */
1319 switch (hw->phy.media_type) {
1320 case txgbe_media_type_fiber:
1321 case txgbe_media_type_fiber_qsfp:
1331 * txgbe_check_mac_link - Determine link and speed status
1332 * @hw: pointer to hardware structure
1333 * @speed: pointer to link speed
1334 * @link_up: true when link is up
1335 * @link_up_wait_to_complete: bool used to wait for link up or not
1337 * Reads the links register to determine if link is up and the current speed
1339 s32 txgbe_check_mac_link(struct txgbe_hw *hw, u32 *speed,
1340 bool *link_up, bool link_up_wait_to_complete)
1342 u32 links_reg, links_orig;
1345 DEBUGFUNC("txgbe_check_mac_link");
1347 /* If Crosstalk fix enabled do the sanity check of making sure
1348 * the SFP+ cage is full.
1350 if (txgbe_need_crosstalk_fix(hw)) {
1353 switch (hw->mac.type) {
1354 case txgbe_mac_raptor:
1355 sfp_cage_full = !rd32m(hw, TXGBE_GPIODATA,
1359 /* sanity check - No SFP+ devices here */
1360 sfp_cage_full = false;
1364 if (!sfp_cage_full) {
1366 *speed = TXGBE_LINK_SPEED_UNKNOWN;
1371 /* clear the old state */
1372 links_orig = rd32(hw, TXGBE_PORTSTAT);
1374 links_reg = rd32(hw, TXGBE_PORTSTAT);
1376 if (links_orig != links_reg) {
1377 DEBUGOUT("LINKS changed from %08X to %08X\n",
1378 links_orig, links_reg);
1381 if (link_up_wait_to_complete) {
1382 for (i = 0; i < hw->mac.max_link_up_time; i++) {
1383 if (!(links_reg & TXGBE_PORTSTAT_UP)) {
1390 links_reg = rd32(hw, TXGBE_PORTSTAT);
1393 if (links_reg & TXGBE_PORTSTAT_UP)
1399 switch (links_reg & TXGBE_PORTSTAT_BW_MASK) {
1400 case TXGBE_PORTSTAT_BW_10G:
1401 *speed = TXGBE_LINK_SPEED_10GB_FULL;
1403 case TXGBE_PORTSTAT_BW_1G:
1404 *speed = TXGBE_LINK_SPEED_1GB_FULL;
1406 case TXGBE_PORTSTAT_BW_100M:
1407 *speed = TXGBE_LINK_SPEED_100M_FULL;
1410 *speed = TXGBE_LINK_SPEED_UNKNOWN;
1417 * txgbe_get_wwn_prefix - Get alternative WWNN/WWPN prefix from
1419 * @hw: pointer to hardware structure
1420 * @wwnn_prefix: the alternative WWNN prefix
1421 * @wwpn_prefix: the alternative WWPN prefix
1423 * This function will read the EEPROM from the alternative SAN MAC address
1424 * block to check the support for the alternative WWNN/WWPN prefix support.
1426 s32 txgbe_get_wwn_prefix(struct txgbe_hw *hw, u16 *wwnn_prefix,
1430 u16 alt_san_mac_blk_offset;
1432 DEBUGFUNC("txgbe_get_wwn_prefix");
1434 /* clear output first */
1435 *wwnn_prefix = 0xFFFF;
1436 *wwpn_prefix = 0xFFFF;
1438 /* check if alternative SAN MAC is supported */
1439 offset = TXGBE_ALT_SAN_MAC_ADDR_BLK_PTR;
1440 if (hw->rom.readw_sw(hw, offset, &alt_san_mac_blk_offset))
1441 goto wwn_prefix_err;
1443 if (alt_san_mac_blk_offset == 0 || alt_san_mac_blk_offset == 0xFFFF)
1444 goto wwn_prefix_out;
1446 /* check capability in alternative san mac address block */
1447 offset = alt_san_mac_blk_offset + TXGBE_ALT_SAN_MAC_ADDR_CAPS_OFFSET;
1448 if (hw->rom.read16(hw, offset, &caps))
1449 goto wwn_prefix_err;
1450 if (!(caps & TXGBE_ALT_SAN_MAC_ADDR_CAPS_ALTWWN))
1451 goto wwn_prefix_out;
1453 /* get the corresponding prefix for WWNN/WWPN */
1454 offset = alt_san_mac_blk_offset + TXGBE_ALT_SAN_MAC_ADDR_WWNN_OFFSET;
1455 if (hw->rom.read16(hw, offset, wwnn_prefix))
1456 DEBUGOUT("eeprom read at offset %d failed", offset);
1458 offset = alt_san_mac_blk_offset + TXGBE_ALT_SAN_MAC_ADDR_WWPN_OFFSET;
1459 if (hw->rom.read16(hw, offset, wwpn_prefix))
1460 goto wwn_prefix_err;
1466 DEBUGOUT("eeprom read at offset %d failed", offset);
1471 * txgbe_set_mac_anti_spoofing - Enable/Disable MAC anti-spoofing
1472 * @hw: pointer to hardware structure
1473 * @enable: enable or disable switch for MAC anti-spoofing
1474 * @vf: Virtual Function pool - VF Pool to set for MAC anti-spoofing
1477 void txgbe_set_mac_anti_spoofing(struct txgbe_hw *hw, bool enable, int vf)
1479 int vf_target_reg = vf >> 3;
1480 int vf_target_shift = vf % 8;
1483 pfvfspoof = rd32(hw, TXGBE_POOLTXASMAC(vf_target_reg));
1485 pfvfspoof |= (1 << vf_target_shift);
1487 pfvfspoof &= ~(1 << vf_target_shift);
1488 wr32(hw, TXGBE_POOLTXASMAC(vf_target_reg), pfvfspoof);
1492 * txgbe_set_ethertype_anti_spoofing - Configure Ethertype anti-spoofing
1493 * @hw: pointer to hardware structure
1494 * @enable: enable or disable switch for Ethertype anti-spoofing
1495 * @vf: Virtual Function pool - VF Pool to set for Ethertype anti-spoofing
1498 void txgbe_set_ethertype_anti_spoofing(struct txgbe_hw *hw,
1499 bool enable, int vf)
1501 int vf_target_reg = vf >> 3;
1502 int vf_target_shift = vf % 8;
1505 pfvfspoof = rd32(hw, TXGBE_POOLTXASET(vf_target_reg));
1507 pfvfspoof |= (1 << vf_target_shift);
1509 pfvfspoof &= ~(1 << vf_target_shift);
1510 wr32(hw, TXGBE_POOLTXASET(vf_target_reg), pfvfspoof);
1514 * txgbe_get_device_caps - Get additional device capabilities
1515 * @hw: pointer to hardware structure
1516 * @device_caps: the EEPROM word with the extra device capabilities
1518 * This function will read the EEPROM location for the device capabilities,
1519 * and return the word through device_caps.
1521 s32 txgbe_get_device_caps(struct txgbe_hw *hw, u16 *device_caps)
1523 DEBUGFUNC("txgbe_get_device_caps");
1525 hw->rom.readw_sw(hw, TXGBE_DEVICE_CAPS, device_caps);
1531 * txgbe_clear_tx_pending - Clear pending TX work from the PCIe fifo
1532 * @hw: pointer to the hardware structure
1534 * The MACs can experience issues if TX work is still pending
1535 * when a reset occurs. This function prevents this by flushing the PCIe
1536 * buffers on the system.
1538 void txgbe_clear_tx_pending(struct txgbe_hw *hw)
1540 u32 hlreg0, i, poll;
1543 * If double reset is not requested then all transactions should
1544 * already be clear and as such there is no work to do
1546 if (!(hw->mac.flags & TXGBE_FLAGS_DOUBLE_RESET_REQUIRED))
1549 hlreg0 = rd32(hw, TXGBE_PSRCTL);
1550 wr32(hw, TXGBE_PSRCTL, hlreg0 | TXGBE_PSRCTL_LBENA);
1552 /* Wait for a last completion before clearing buffers */
1557 * Before proceeding, make sure that the PCIe block does not have
1558 * transactions pending.
1560 poll = (800 * 11) / 10;
1561 for (i = 0; i < poll; i++)
1564 /* Flush all writes and allow 20usec for all transactions to clear */
1568 /* restore previous register values */
1569 wr32(hw, TXGBE_PSRCTL, hlreg0);
1573 * txgbe_get_thermal_sensor_data - Gathers thermal sensor data
1574 * @hw: pointer to hardware structure
1576 * Returns the thermal sensor data structure
1578 s32 txgbe_get_thermal_sensor_data(struct txgbe_hw *hw)
1580 struct txgbe_thermal_sensor_data *data = &hw->mac.thermal_sensor_data;
1584 DEBUGFUNC("txgbe_get_thermal_sensor_data");
1586 /* Only support thermal sensors attached to physical port 0 */
1587 if (hw->bus.lan_id != 0)
1588 return TXGBE_NOT_IMPLEMENTED;
1590 ts_stat = rd32(hw, TXGBE_TSSTAT);
1591 tsv = (s64)TXGBE_TSSTAT_DATA(ts_stat);
1592 tsv = tsv > 1200 ? tsv : 1200;
1593 tsv = -(48380 << 8) / 1000
1594 + tsv * (31020 << 8) / 100000
1595 - tsv * tsv * (18201 << 8) / 100000000
1596 + tsv * tsv * tsv * (81542 << 8) / 1000000000000
1597 - tsv * tsv * tsv * tsv * (16743 << 8) / 1000000000000000;
1600 data->sensor[0].temp = (s16)tsv;
1606 * txgbe_init_thermal_sensor_thresh - Inits thermal sensor thresholds
1607 * @hw: pointer to hardware structure
1609 * Inits the thermal sensor thresholds according to the NVM map
1610 * and save off the threshold and location values into mac.thermal_sensor_data
1612 s32 txgbe_init_thermal_sensor_thresh(struct txgbe_hw *hw)
1614 struct txgbe_thermal_sensor_data *data = &hw->mac.thermal_sensor_data;
1616 DEBUGFUNC("txgbe_init_thermal_sensor_thresh");
1618 memset(data, 0, sizeof(struct txgbe_thermal_sensor_data));
1620 if (hw->bus.lan_id != 0)
1621 return TXGBE_NOT_IMPLEMENTED;
1623 wr32(hw, TXGBE_TSCTRL, TXGBE_TSCTRL_EVALMD);
1624 wr32(hw, TXGBE_TSINTR,
1625 TXGBE_TSINTR_AEN | TXGBE_TSINTR_DEN);
1626 wr32(hw, TXGBE_TSEN, TXGBE_TSEN_ENA);
1629 data->sensor[0].alarm_thresh = 100;
1630 wr32(hw, TXGBE_TSATHRE, 677);
1631 data->sensor[0].dalarm_thresh = 90;
1632 wr32(hw, TXGBE_TSDTHRE, 614);
1637 void txgbe_disable_rx(struct txgbe_hw *hw)
1641 pfdtxgswc = rd32(hw, TXGBE_PSRCTL);
1642 if (pfdtxgswc & TXGBE_PSRCTL_LBENA) {
1643 pfdtxgswc &= ~TXGBE_PSRCTL_LBENA;
1644 wr32(hw, TXGBE_PSRCTL, pfdtxgswc);
1645 hw->mac.set_lben = true;
1647 hw->mac.set_lben = false;
1650 wr32m(hw, TXGBE_PBRXCTL, TXGBE_PBRXCTL_ENA, 0);
1651 wr32m(hw, TXGBE_MACRXCFG, TXGBE_MACRXCFG_ENA, 0);
1654 void txgbe_enable_rx(struct txgbe_hw *hw)
1658 wr32m(hw, TXGBE_MACRXCFG, TXGBE_MACRXCFG_ENA, TXGBE_MACRXCFG_ENA);
1659 wr32m(hw, TXGBE_PBRXCTL, TXGBE_PBRXCTL_ENA, TXGBE_PBRXCTL_ENA);
1661 if (hw->mac.set_lben) {
1662 pfdtxgswc = rd32(hw, TXGBE_PSRCTL);
1663 pfdtxgswc |= TXGBE_PSRCTL_LBENA;
1664 wr32(hw, TXGBE_PSRCTL, pfdtxgswc);
1665 hw->mac.set_lben = false;
1670 * txgbe_setup_mac_link_multispeed_fiber - Set MAC link speed
1671 * @hw: pointer to hardware structure
1672 * @speed: new link speed
1673 * @autoneg_wait_to_complete: true when waiting for completion is needed
1675 * Set the link speed in the MAC and/or PHY register and restarts link.
1677 s32 txgbe_setup_mac_link_multispeed_fiber(struct txgbe_hw *hw,
1679 bool autoneg_wait_to_complete)
1681 u32 link_speed = TXGBE_LINK_SPEED_UNKNOWN;
1682 u32 highest_link_speed = TXGBE_LINK_SPEED_UNKNOWN;
1686 bool autoneg, link_up = false;
1688 DEBUGFUNC("txgbe_setup_mac_link_multispeed_fiber");
1690 /* Mask off requested but non-supported speeds */
1691 status = hw->mac.get_link_capabilities(hw, &link_speed, &autoneg);
1695 speed &= link_speed;
1697 /* Try each speed one by one, highest priority first. We do this in
1698 * software because 10Gb fiber doesn't support speed autonegotiation.
1700 if (speed & TXGBE_LINK_SPEED_10GB_FULL) {
1702 highest_link_speed = TXGBE_LINK_SPEED_10GB_FULL;
1704 /* Set the module link speed */
1705 switch (hw->phy.media_type) {
1706 case txgbe_media_type_fiber:
1707 hw->mac.set_rate_select_speed(hw,
1708 TXGBE_LINK_SPEED_10GB_FULL);
1710 case txgbe_media_type_fiber_qsfp:
1711 /* QSFP module automatically detects MAC link speed */
1714 DEBUGOUT("Unexpected media type.\n");
1718 /* Allow module to change analog characteristics (1G->10G) */
1721 status = hw->mac.setup_mac_link(hw,
1722 TXGBE_LINK_SPEED_10GB_FULL,
1723 autoneg_wait_to_complete);
1727 /* Flap the Tx laser if it has not already been done */
1728 hw->mac.flap_tx_laser(hw);
1730 /* Wait for the controller to acquire link. Per IEEE 802.3ap,
1731 * Section 73.10.2, we may have to wait up to 500ms if KR is
1732 * attempted. uses the same timing for 10g SFI.
1734 for (i = 0; i < 5; i++) {
1735 /* Wait for the link partner to also set speed */
1738 /* If we have link, just jump out */
1739 status = hw->mac.check_link(hw, &link_speed,
1749 if (speed & TXGBE_LINK_SPEED_1GB_FULL) {
1751 if (highest_link_speed == TXGBE_LINK_SPEED_UNKNOWN)
1752 highest_link_speed = TXGBE_LINK_SPEED_1GB_FULL;
1754 /* Set the module link speed */
1755 switch (hw->phy.media_type) {
1756 case txgbe_media_type_fiber:
1757 hw->mac.set_rate_select_speed(hw,
1758 TXGBE_LINK_SPEED_1GB_FULL);
1760 case txgbe_media_type_fiber_qsfp:
1761 /* QSFP module automatically detects link speed */
1764 DEBUGOUT("Unexpected media type.\n");
1768 /* Allow module to change analog characteristics (10G->1G) */
1771 status = hw->mac.setup_mac_link(hw,
1772 TXGBE_LINK_SPEED_1GB_FULL,
1773 autoneg_wait_to_complete);
1777 /* Flap the Tx laser if it has not already been done */
1778 hw->mac.flap_tx_laser(hw);
1780 /* Wait for the link partner to also set speed */
1783 /* If we have link, just jump out */
1784 status = hw->mac.check_link(hw, &link_speed, &link_up, false);
1792 /* We didn't get link. Configure back to the highest speed we tried,
1793 * (if there was more than one). We call ourselves back with just the
1794 * single highest speed that the user requested.
1797 status = txgbe_setup_mac_link_multispeed_fiber(hw,
1799 autoneg_wait_to_complete);
1802 /* Set autoneg_advertised value based on input link speed */
1803 hw->phy.autoneg_advertised = 0;
1805 if (speed & TXGBE_LINK_SPEED_10GB_FULL)
1806 hw->phy.autoneg_advertised |= TXGBE_LINK_SPEED_10GB_FULL;
1808 if (speed & TXGBE_LINK_SPEED_1GB_FULL)
1809 hw->phy.autoneg_advertised |= TXGBE_LINK_SPEED_1GB_FULL;
1815 * txgbe_init_shared_code - Initialize the shared code
1816 * @hw: pointer to hardware structure
1818 * This will assign function pointers and assign the MAC type and PHY code.
1819 * Does not touch the hardware. This function must be called prior to any
1820 * other function in the shared code. The txgbe_hw structure should be
1821 * memset to 0 prior to calling this function. The following fields in
1822 * hw structure should be filled in prior to calling this function:
1823 * hw_addr, back, device_id, vendor_id, subsystem_device_id,
1824 * subsystem_vendor_id, and revision_id
1826 s32 txgbe_init_shared_code(struct txgbe_hw *hw)
1830 DEBUGFUNC("txgbe_init_shared_code");
1835 txgbe_set_mac_type(hw);
1837 txgbe_init_ops_dummy(hw);
1838 switch (hw->mac.type) {
1839 case txgbe_mac_raptor:
1840 status = txgbe_init_ops_pf(hw);
1843 status = TXGBE_ERR_DEVICE_NOT_SUPPORTED;
1846 hw->mac.max_link_up_time = TXGBE_LINK_UP_TIME;
1848 hw->bus.set_lan_id(hw);
1854 * txgbe_set_mac_type - Sets MAC type
1855 * @hw: pointer to the HW structure
1857 * This function sets the mac type of the adapter based on the
1858 * vendor ID and device ID stored in the hw structure.
1860 s32 txgbe_set_mac_type(struct txgbe_hw *hw)
1864 DEBUGFUNC("txgbe_set_mac_type");
1866 if (hw->vendor_id != PCI_VENDOR_ID_WANGXUN) {
1867 DEBUGOUT("Unsupported vendor id: %x", hw->vendor_id);
1868 return TXGBE_ERR_DEVICE_NOT_SUPPORTED;
1871 switch (hw->device_id) {
1872 case TXGBE_DEV_ID_RAPTOR_KR_KX_KX4:
1873 hw->phy.media_type = txgbe_media_type_backplane;
1874 hw->mac.type = txgbe_mac_raptor;
1876 case TXGBE_DEV_ID_RAPTOR_XAUI:
1877 case TXGBE_DEV_ID_RAPTOR_SGMII:
1878 hw->phy.media_type = txgbe_media_type_copper;
1879 hw->mac.type = txgbe_mac_raptor;
1881 case TXGBE_DEV_ID_RAPTOR_SFP:
1882 case TXGBE_DEV_ID_WX1820_SFP:
1883 hw->phy.media_type = txgbe_media_type_fiber;
1884 hw->mac.type = txgbe_mac_raptor;
1886 case TXGBE_DEV_ID_RAPTOR_QSFP:
1887 hw->phy.media_type = txgbe_media_type_fiber_qsfp;
1888 hw->mac.type = txgbe_mac_raptor;
1890 case TXGBE_DEV_ID_RAPTOR_VF:
1891 case TXGBE_DEV_ID_RAPTOR_VF_HV:
1892 hw->phy.media_type = txgbe_media_type_virtual;
1893 hw->mac.type = txgbe_mac_raptor_vf;
1896 err = TXGBE_ERR_DEVICE_NOT_SUPPORTED;
1897 DEBUGOUT("Unsupported device id: %x", hw->device_id);
1901 DEBUGOUT("found mac: %d media: %d, returns: %d\n",
1902 hw->mac.type, hw->phy.media_type, err);
1906 void txgbe_init_mac_link_ops(struct txgbe_hw *hw)
1908 struct txgbe_mac_info *mac = &hw->mac;
1910 DEBUGFUNC("txgbe_init_mac_link_ops");
1913 * enable the laser control functions for SFP+ fiber
1914 * and MNG not enabled
1916 if (hw->phy.media_type == txgbe_media_type_fiber &&
1917 !txgbe_mng_enabled(hw)) {
1918 mac->disable_tx_laser =
1919 txgbe_disable_tx_laser_multispeed_fiber;
1920 mac->enable_tx_laser =
1921 txgbe_enable_tx_laser_multispeed_fiber;
1922 mac->flap_tx_laser =
1923 txgbe_flap_tx_laser_multispeed_fiber;
1926 if ((hw->phy.media_type == txgbe_media_type_fiber ||
1927 hw->phy.media_type == txgbe_media_type_fiber_qsfp) &&
1928 hw->phy.multispeed_fiber) {
1929 /* Set up dual speed SFP+ support */
1930 mac->setup_link = txgbe_setup_mac_link_multispeed_fiber;
1931 mac->setup_mac_link = txgbe_setup_mac_link;
1932 mac->set_rate_select_speed = txgbe_set_hard_rate_select_speed;
1933 } else if ((hw->phy.media_type == txgbe_media_type_backplane) &&
1934 (hw->phy.smart_speed == txgbe_smart_speed_auto ||
1935 hw->phy.smart_speed == txgbe_smart_speed_on) &&
1936 !txgbe_verify_lesm_fw_enabled_raptor(hw)) {
1937 mac->setup_link = txgbe_setup_mac_link_smartspeed;
1939 mac->setup_link = txgbe_setup_mac_link;
1944 * txgbe_init_phy_raptor - PHY/SFP specific init
1945 * @hw: pointer to hardware structure
1947 * Initialize any function pointers that were not able to be
1948 * set during init_shared_code because the PHY/SFP type was
1949 * not known. Perform the SFP init if necessary.
1952 s32 txgbe_init_phy_raptor(struct txgbe_hw *hw)
1954 struct txgbe_mac_info *mac = &hw->mac;
1955 struct txgbe_phy_info *phy = &hw->phy;
1958 DEBUGFUNC("txgbe_init_phy_raptor");
1960 if (hw->device_id == TXGBE_DEV_ID_RAPTOR_QSFP) {
1961 /* Store flag indicating I2C bus access control unit. */
1962 hw->phy.qsfp_shared_i2c_bus = TRUE;
1964 /* Initialize access to QSFP+ I2C bus */
1968 /* Identify the PHY or SFP module */
1969 err = phy->identify(hw);
1970 if (err == TXGBE_ERR_SFP_NOT_SUPPORTED)
1971 goto init_phy_ops_out;
1973 /* Setup function pointers based on detected SFP module and speeds */
1974 txgbe_init_mac_link_ops(hw);
1976 /* If copper media, overwrite with copper function pointers */
1977 if (phy->media_type == txgbe_media_type_copper) {
1978 mac->setup_link = txgbe_setup_copper_link_raptor;
1979 mac->get_link_capabilities =
1980 txgbe_get_copper_link_capabilities;
1983 /* Set necessary function pointers based on PHY type */
1984 switch (hw->phy.type) {
1986 phy->setup_link = txgbe_setup_phy_link_tnx;
1987 phy->check_link = txgbe_check_phy_link_tnx;
1997 s32 txgbe_setup_sfp_modules(struct txgbe_hw *hw)
2001 DEBUGFUNC("txgbe_setup_sfp_modules");
2003 if (hw->phy.sfp_type == txgbe_sfp_type_unknown)
2006 txgbe_init_mac_link_ops(hw);
2008 /* PHY config will finish before releasing the semaphore */
2009 err = hw->mac.acquire_swfw_sync(hw, TXGBE_MNGSEM_SWPHY);
2011 return TXGBE_ERR_SWFW_SYNC;
2013 /* Release the semaphore */
2014 hw->mac.release_swfw_sync(hw, TXGBE_MNGSEM_SWPHY);
2016 /* Delay obtaining semaphore again to allow FW access
2017 * prot_autoc_write uses the semaphore too.
2019 msec_delay(hw->rom.semaphore_delay);
2022 DEBUGOUT("sfp module setup not complete\n");
2023 return TXGBE_ERR_SFP_SETUP_NOT_COMPLETE;
2030 * txgbe_init_ops_pf - Inits func ptrs and MAC type
2031 * @hw: pointer to hardware structure
2033 * Initialize the function pointers and assign the MAC type.
2034 * Does not touch the hardware.
2036 s32 txgbe_init_ops_pf(struct txgbe_hw *hw)
2038 struct txgbe_bus_info *bus = &hw->bus;
2039 struct txgbe_mac_info *mac = &hw->mac;
2040 struct txgbe_phy_info *phy = &hw->phy;
2041 struct txgbe_rom_info *rom = &hw->rom;
2042 struct txgbe_mbx_info *mbx = &hw->mbx;
2044 DEBUGFUNC("txgbe_init_ops_pf");
2047 bus->set_lan_id = txgbe_set_lan_id_multi_port;
2050 phy->get_media_type = txgbe_get_media_type_raptor;
2051 phy->identify = txgbe_identify_phy;
2052 phy->init = txgbe_init_phy_raptor;
2053 phy->read_reg = txgbe_read_phy_reg;
2054 phy->write_reg = txgbe_write_phy_reg;
2055 phy->read_reg_mdi = txgbe_read_phy_reg_mdi;
2056 phy->write_reg_mdi = txgbe_write_phy_reg_mdi;
2057 phy->setup_link = txgbe_setup_phy_link;
2058 phy->setup_link_speed = txgbe_setup_phy_link_speed;
2059 phy->read_i2c_byte = txgbe_read_i2c_byte;
2060 phy->write_i2c_byte = txgbe_write_i2c_byte;
2061 phy->read_i2c_eeprom = txgbe_read_i2c_eeprom;
2062 phy->write_i2c_eeprom = txgbe_write_i2c_eeprom;
2063 phy->reset = txgbe_reset_phy;
2066 mac->init_hw = txgbe_init_hw;
2067 mac->start_hw = txgbe_start_hw_raptor;
2068 mac->clear_hw_cntrs = txgbe_clear_hw_cntrs;
2069 mac->enable_rx_dma = txgbe_enable_rx_dma_raptor;
2070 mac->get_mac_addr = txgbe_get_mac_addr;
2071 mac->stop_hw = txgbe_stop_hw;
2072 mac->acquire_swfw_sync = txgbe_acquire_swfw_sync;
2073 mac->release_swfw_sync = txgbe_release_swfw_sync;
2074 mac->reset_hw = txgbe_reset_hw;
2076 mac->disable_sec_rx_path = txgbe_disable_sec_rx_path;
2077 mac->enable_sec_rx_path = txgbe_enable_sec_rx_path;
2078 mac->disable_sec_tx_path = txgbe_disable_sec_tx_path;
2079 mac->enable_sec_tx_path = txgbe_enable_sec_tx_path;
2080 mac->get_san_mac_addr = txgbe_get_san_mac_addr;
2081 mac->set_san_mac_addr = txgbe_set_san_mac_addr;
2082 mac->get_device_caps = txgbe_get_device_caps;
2083 mac->get_wwn_prefix = txgbe_get_wwn_prefix;
2084 mac->autoc_read = txgbe_autoc_read;
2085 mac->autoc_write = txgbe_autoc_write;
2087 /* RAR, Multicast, VLAN */
2088 mac->set_rar = txgbe_set_rar;
2089 mac->clear_rar = txgbe_clear_rar;
2090 mac->init_rx_addrs = txgbe_init_rx_addrs;
2091 mac->enable_rx = txgbe_enable_rx;
2092 mac->disable_rx = txgbe_disable_rx;
2093 mac->set_vmdq = txgbe_set_vmdq;
2094 mac->clear_vmdq = txgbe_clear_vmdq;
2095 mac->set_vfta = txgbe_set_vfta;
2096 mac->set_vlvf = txgbe_set_vlvf;
2097 mac->clear_vfta = txgbe_clear_vfta;
2098 mac->init_uta_tables = txgbe_init_uta_tables;
2099 mac->setup_sfp = txgbe_setup_sfp_modules;
2100 mac->set_mac_anti_spoofing = txgbe_set_mac_anti_spoofing;
2101 mac->set_ethertype_anti_spoofing = txgbe_set_ethertype_anti_spoofing;
2104 mac->get_link_capabilities = txgbe_get_link_capabilities_raptor;
2105 mac->check_link = txgbe_check_mac_link;
2107 /* Manageability interface */
2108 mac->set_fw_drv_ver = txgbe_hic_set_drv_ver;
2109 mac->get_thermal_sensor_data = txgbe_get_thermal_sensor_data;
2110 mac->init_thermal_sensor_thresh = txgbe_init_thermal_sensor_thresh;
2112 mbx->init_params = txgbe_init_mbx_params_pf;
2113 mbx->read = txgbe_read_mbx_pf;
2114 mbx->write = txgbe_write_mbx_pf;
2115 mbx->check_for_msg = txgbe_check_for_msg_pf;
2116 mbx->check_for_ack = txgbe_check_for_ack_pf;
2117 mbx->check_for_rst = txgbe_check_for_rst_pf;
2120 rom->init_params = txgbe_init_eeprom_params;
2121 rom->read16 = txgbe_ee_read16;
2122 rom->readw_buffer = txgbe_ee_readw_buffer;
2123 rom->readw_sw = txgbe_ee_readw_sw;
2124 rom->read32 = txgbe_ee_read32;
2125 rom->write16 = txgbe_ee_write16;
2126 rom->writew_buffer = txgbe_ee_writew_buffer;
2127 rom->writew_sw = txgbe_ee_writew_sw;
2128 rom->write32 = txgbe_ee_write32;
2129 rom->validate_checksum = txgbe_validate_eeprom_checksum;
2130 rom->update_checksum = txgbe_update_eeprom_checksum;
2131 rom->calc_checksum = txgbe_calc_eeprom_checksum;
2133 mac->mcft_size = TXGBE_RAPTOR_MC_TBL_SIZE;
2134 mac->vft_size = TXGBE_RAPTOR_VFT_TBL_SIZE;
2135 mac->num_rar_entries = TXGBE_RAPTOR_RAR_ENTRIES;
2136 mac->max_rx_queues = TXGBE_RAPTOR_MAX_RX_QUEUES;
2137 mac->max_tx_queues = TXGBE_RAPTOR_MAX_TX_QUEUES;
2143 * txgbe_get_link_capabilities_raptor - Determines link capabilities
2144 * @hw: pointer to hardware structure
2145 * @speed: pointer to link speed
2146 * @autoneg: true when autoneg or autotry is enabled
2148 * Determines the link capabilities by reading the AUTOC register.
2150 s32 txgbe_get_link_capabilities_raptor(struct txgbe_hw *hw,
2157 DEBUGFUNC("txgbe_get_link_capabilities_raptor");
2159 /* Check if 1G SFP module. */
2160 if (hw->phy.sfp_type == txgbe_sfp_type_1g_cu_core0 ||
2161 hw->phy.sfp_type == txgbe_sfp_type_1g_cu_core1 ||
2162 hw->phy.sfp_type == txgbe_sfp_type_1g_lx_core0 ||
2163 hw->phy.sfp_type == txgbe_sfp_type_1g_lx_core1 ||
2164 hw->phy.sfp_type == txgbe_sfp_type_1g_sx_core0 ||
2165 hw->phy.sfp_type == txgbe_sfp_type_1g_sx_core1) {
2166 *speed = TXGBE_LINK_SPEED_1GB_FULL;
2172 * Determine link capabilities based on the stored value of AUTOC,
2173 * which represents EEPROM defaults. If AUTOC value has not
2174 * been stored, use the current register values.
2176 if (hw->mac.orig_link_settings_stored)
2177 autoc = hw->mac.orig_autoc;
2179 autoc = hw->mac.autoc_read(hw);
2181 switch (autoc & TXGBE_AUTOC_LMS_MASK) {
2182 case TXGBE_AUTOC_LMS_1G_LINK_NO_AN:
2183 *speed = TXGBE_LINK_SPEED_1GB_FULL;
2187 case TXGBE_AUTOC_LMS_10G_LINK_NO_AN:
2188 *speed = TXGBE_LINK_SPEED_10GB_FULL;
2192 case TXGBE_AUTOC_LMS_1G_AN:
2193 *speed = TXGBE_LINK_SPEED_1GB_FULL;
2197 case TXGBE_AUTOC_LMS_10G:
2198 *speed = TXGBE_LINK_SPEED_10GB_FULL;
2202 case TXGBE_AUTOC_LMS_KX4_KX_KR:
2203 case TXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN:
2204 *speed = TXGBE_LINK_SPEED_UNKNOWN;
2205 if (autoc & TXGBE_AUTOC_KR_SUPP)
2206 *speed |= TXGBE_LINK_SPEED_10GB_FULL;
2207 if (autoc & TXGBE_AUTOC_KX4_SUPP)
2208 *speed |= TXGBE_LINK_SPEED_10GB_FULL;
2209 if (autoc & TXGBE_AUTOC_KX_SUPP)
2210 *speed |= TXGBE_LINK_SPEED_1GB_FULL;
2214 case TXGBE_AUTOC_LMS_KX4_KX_KR_SGMII:
2215 *speed = TXGBE_LINK_SPEED_100M_FULL;
2216 if (autoc & TXGBE_AUTOC_KR_SUPP)
2217 *speed |= TXGBE_LINK_SPEED_10GB_FULL;
2218 if (autoc & TXGBE_AUTOC_KX4_SUPP)
2219 *speed |= TXGBE_LINK_SPEED_10GB_FULL;
2220 if (autoc & TXGBE_AUTOC_KX_SUPP)
2221 *speed |= TXGBE_LINK_SPEED_1GB_FULL;
2225 case TXGBE_AUTOC_LMS_SGMII_1G_100M:
2226 *speed = TXGBE_LINK_SPEED_1GB_FULL |
2227 TXGBE_LINK_SPEED_100M_FULL |
2228 TXGBE_LINK_SPEED_10M_FULL;
2233 return TXGBE_ERR_LINK_SETUP;
2236 if (hw->phy.multispeed_fiber) {
2237 *speed |= TXGBE_LINK_SPEED_10GB_FULL |
2238 TXGBE_LINK_SPEED_1GB_FULL;
2240 /* QSFP must not enable full auto-negotiation
2241 * Limited autoneg is enabled at 1G
2243 if (hw->phy.media_type == txgbe_media_type_fiber_qsfp)
2253 * txgbe_get_media_type_raptor - Get media type
2254 * @hw: pointer to hardware structure
2256 * Returns the media type (fiber, copper, backplane)
2258 u32 txgbe_get_media_type_raptor(struct txgbe_hw *hw)
2262 DEBUGFUNC("txgbe_get_media_type_raptor");
2264 /* Detect if there is a copper PHY attached. */
2265 switch (hw->phy.type) {
2266 case txgbe_phy_cu_unknown:
2268 media_type = txgbe_media_type_copper;
2274 switch (hw->device_id) {
2275 case TXGBE_DEV_ID_RAPTOR_KR_KX_KX4:
2276 /* Default device ID is mezzanine card KX/KX4 */
2277 media_type = txgbe_media_type_backplane;
2279 case TXGBE_DEV_ID_RAPTOR_SFP:
2280 case TXGBE_DEV_ID_WX1820_SFP:
2281 media_type = txgbe_media_type_fiber;
2283 case TXGBE_DEV_ID_RAPTOR_QSFP:
2284 media_type = txgbe_media_type_fiber_qsfp;
2286 case TXGBE_DEV_ID_RAPTOR_XAUI:
2287 case TXGBE_DEV_ID_RAPTOR_SGMII:
2288 media_type = txgbe_media_type_copper;
2291 media_type = txgbe_media_type_unknown;
2299 * txgbe_start_mac_link_raptor - Setup MAC link settings
2300 * @hw: pointer to hardware structure
2301 * @autoneg_wait_to_complete: true when waiting for completion is needed
2303 * Configures link settings based on values in the txgbe_hw struct.
2304 * Restarts the link. Performs autonegotiation if needed.
2306 s32 txgbe_start_mac_link_raptor(struct txgbe_hw *hw,
2307 bool autoneg_wait_to_complete)
2310 bool got_lock = false;
2312 DEBUGFUNC("txgbe_start_mac_link_raptor");
2314 UNREFERENCED_PARAMETER(autoneg_wait_to_complete);
2316 /* reset_pipeline requires us to hold this lock as it writes to
2319 if (txgbe_verify_lesm_fw_enabled_raptor(hw)) {
2320 status = hw->mac.acquire_swfw_sync(hw, TXGBE_MNGSEM_SWPHY);
2328 txgbe_reset_pipeline_raptor(hw);
2331 hw->mac.release_swfw_sync(hw, TXGBE_MNGSEM_SWPHY);
2333 /* Add delay to filter out noises during initial link setup */
2341 * txgbe_disable_tx_laser_multispeed_fiber - Disable Tx laser
2342 * @hw: pointer to hardware structure
2344 * The base drivers may require better control over SFP+ module
2345 * PHY states. This includes selectively shutting down the Tx
2346 * laser on the PHY, effectively halting physical link.
2348 void txgbe_disable_tx_laser_multispeed_fiber(struct txgbe_hw *hw)
2350 u32 esdp_reg = rd32(hw, TXGBE_GPIODATA);
2352 /* Blocked by MNG FW so bail */
2353 if (txgbe_check_reset_blocked(hw))
2356 /* Disable Tx laser; allow 100us to go dark per spec */
2357 esdp_reg |= (TXGBE_GPIOBIT_0 | TXGBE_GPIOBIT_1);
2358 wr32(hw, TXGBE_GPIODATA, esdp_reg);
2364 * txgbe_enable_tx_laser_multispeed_fiber - Enable Tx laser
2365 * @hw: pointer to hardware structure
2367 * The base drivers may require better control over SFP+ module
2368 * PHY states. This includes selectively turning on the Tx
2369 * laser on the PHY, effectively starting physical link.
2371 void txgbe_enable_tx_laser_multispeed_fiber(struct txgbe_hw *hw)
2373 u32 esdp_reg = rd32(hw, TXGBE_GPIODATA);
2375 /* Enable Tx laser; allow 100ms to light up */
2376 esdp_reg &= ~(TXGBE_GPIOBIT_0 | TXGBE_GPIOBIT_1);
2377 wr32(hw, TXGBE_GPIODATA, esdp_reg);
2383 * txgbe_flap_tx_laser_multispeed_fiber - Flap Tx laser
2384 * @hw: pointer to hardware structure
2386 * When the driver changes the link speeds that it can support,
2387 * it sets autotry_restart to true to indicate that we need to
2388 * initiate a new autotry session with the link partner. To do
2389 * so, we set the speed then disable and re-enable the Tx laser, to
2390 * alert the link partner that it also needs to restart autotry on its
2391 * end. This is consistent with true clause 37 autoneg, which also
2392 * involves a loss of signal.
2394 void txgbe_flap_tx_laser_multispeed_fiber(struct txgbe_hw *hw)
2396 DEBUGFUNC("txgbe_flap_tx_laser_multispeed_fiber");
2398 /* Blocked by MNG FW so bail */
2399 if (txgbe_check_reset_blocked(hw))
2402 if (hw->mac.autotry_restart) {
2403 txgbe_disable_tx_laser_multispeed_fiber(hw);
2404 txgbe_enable_tx_laser_multispeed_fiber(hw);
2405 hw->mac.autotry_restart = false;
2410 * txgbe_set_hard_rate_select_speed - Set module link speed
2411 * @hw: pointer to hardware structure
2412 * @speed: link speed to set
2414 * Set module link speed via RS0/RS1 rate select pins.
2416 void txgbe_set_hard_rate_select_speed(struct txgbe_hw *hw,
2419 u32 esdp_reg = rd32(hw, TXGBE_GPIODATA);
2422 case TXGBE_LINK_SPEED_10GB_FULL:
2423 esdp_reg |= (TXGBE_GPIOBIT_4 | TXGBE_GPIOBIT_5);
2425 case TXGBE_LINK_SPEED_1GB_FULL:
2426 esdp_reg &= ~(TXGBE_GPIOBIT_4 | TXGBE_GPIOBIT_5);
2429 DEBUGOUT("Invalid fixed module speed\n");
2433 wr32(hw, TXGBE_GPIODATA, esdp_reg);
2438 * txgbe_setup_mac_link_smartspeed - Set MAC link speed using SmartSpeed
2439 * @hw: pointer to hardware structure
2440 * @speed: new link speed
2441 * @autoneg_wait_to_complete: true when waiting for completion is needed
2443 * Implements the Intel SmartSpeed algorithm.
2445 s32 txgbe_setup_mac_link_smartspeed(struct txgbe_hw *hw,
2447 bool autoneg_wait_to_complete)
2450 u32 link_speed = TXGBE_LINK_SPEED_UNKNOWN;
2452 bool link_up = false;
2453 u32 autoc_reg = rd32_epcs(hw, SR_AN_MMD_ADV_REG1);
2455 DEBUGFUNC("txgbe_setup_mac_link_smartspeed");
2457 /* Set autoneg_advertised value based on input link speed */
2458 hw->phy.autoneg_advertised = 0;
2460 if (speed & TXGBE_LINK_SPEED_10GB_FULL)
2461 hw->phy.autoneg_advertised |= TXGBE_LINK_SPEED_10GB_FULL;
2463 if (speed & TXGBE_LINK_SPEED_1GB_FULL)
2464 hw->phy.autoneg_advertised |= TXGBE_LINK_SPEED_1GB_FULL;
2466 if (speed & TXGBE_LINK_SPEED_100M_FULL)
2467 hw->phy.autoneg_advertised |= TXGBE_LINK_SPEED_100M_FULL;
2470 * Implement Intel SmartSpeed algorithm. SmartSpeed will reduce the
2471 * autoneg advertisement if link is unable to be established at the
2472 * highest negotiated rate. This can sometimes happen due to integrity
2473 * issues with the physical media connection.
2476 /* First, try to get link with full advertisement */
2477 hw->phy.smart_speed_active = false;
2478 for (j = 0; j < TXGBE_SMARTSPEED_MAX_RETRIES; j++) {
2479 status = txgbe_setup_mac_link(hw, speed,
2480 autoneg_wait_to_complete);
2485 * Wait for the controller to acquire link. Per IEEE 802.3ap,
2486 * Section 73.10.2, we may have to wait up to 500ms if KR is
2487 * attempted, or 200ms if KX/KX4/BX/BX4 is attempted, per
2488 * Table 9 in the AN MAS.
2490 for (i = 0; i < 5; i++) {
2493 /* If we have link, just jump out */
2494 status = hw->mac.check_link(hw, &link_speed, &link_up,
2505 * We didn't get link. If we advertised KR plus one of KX4/KX
2506 * (or BX4/BX), then disable KR and try again.
2508 if (((autoc_reg & TXGBE_AUTOC_KR_SUPP) == 0) ||
2509 ((autoc_reg & TXGBE_AUTOC_KX_SUPP) == 0 &&
2510 (autoc_reg & TXGBE_AUTOC_KX4_SUPP) == 0))
2513 /* Turn SmartSpeed on to disable KR support */
2514 hw->phy.smart_speed_active = true;
2515 status = txgbe_setup_mac_link(hw, speed,
2516 autoneg_wait_to_complete);
2521 * Wait for the controller to acquire link. 600ms will allow for
2522 * the AN link_fail_inhibit_timer as well for multiple cycles of
2523 * parallel detect, both 10g and 1g. This allows for the maximum
2524 * connect attempts as defined in the AN MAS table 73-7.
2526 for (i = 0; i < 6; i++) {
2529 /* If we have link, just jump out */
2530 status = hw->mac.check_link(hw, &link_speed, &link_up, false);
2538 /* We didn't get link. Turn SmartSpeed back off. */
2539 hw->phy.smart_speed_active = false;
2540 status = txgbe_setup_mac_link(hw, speed,
2541 autoneg_wait_to_complete);
2544 if (link_up && link_speed == TXGBE_LINK_SPEED_1GB_FULL)
2545 DEBUGOUT("Smartspeed has downgraded the link speed "
2546 "from the maximum advertised\n");
2551 * txgbe_setup_mac_link - Set MAC link speed
2552 * @hw: pointer to hardware structure
2553 * @speed: new link speed
2554 * @autoneg_wait_to_complete: true when waiting for completion is needed
2556 * Set the link speed in the AUTOC register and restarts link.
2558 s32 txgbe_setup_mac_link(struct txgbe_hw *hw,
2560 bool autoneg_wait_to_complete)
2562 bool autoneg = false;
2565 u64 autoc = hw->mac.autoc_read(hw);
2566 u64 pma_pmd_10gs = autoc & TXGBE_AUTOC_10GS_PMA_PMD_MASK;
2567 u64 pma_pmd_1g = autoc & TXGBE_AUTOC_1G_PMA_PMD_MASK;
2568 u64 link_mode = autoc & TXGBE_AUTOC_LMS_MASK;
2569 u64 current_autoc = autoc;
2573 u32 link_capabilities = TXGBE_LINK_SPEED_UNKNOWN;
2575 DEBUGFUNC("txgbe_setup_mac_link");
2577 /* Check to see if speed passed in is supported. */
2578 status = hw->mac.get_link_capabilities(hw,
2579 &link_capabilities, &autoneg);
2583 speed &= link_capabilities;
2584 if (speed == TXGBE_LINK_SPEED_UNKNOWN)
2585 return TXGBE_ERR_LINK_SETUP;
2587 /* Use stored value (EEPROM defaults) of AUTOC to find KR/KX4 support*/
2588 if (hw->mac.orig_link_settings_stored)
2589 orig_autoc = hw->mac.orig_autoc;
2593 link_mode = autoc & TXGBE_AUTOC_LMS_MASK;
2594 pma_pmd_1g = autoc & TXGBE_AUTOC_1G_PMA_PMD_MASK;
2596 if (link_mode == TXGBE_AUTOC_LMS_KX4_KX_KR ||
2597 link_mode == TXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
2598 link_mode == TXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
2599 /* Set KX4/KX/KR support according to speed requested */
2600 autoc &= ~(TXGBE_AUTOC_KX_SUPP |
2601 TXGBE_AUTOC_KX4_SUPP |
2602 TXGBE_AUTOC_KR_SUPP);
2603 if (speed & TXGBE_LINK_SPEED_10GB_FULL) {
2604 if (orig_autoc & TXGBE_AUTOC_KX4_SUPP)
2605 autoc |= TXGBE_AUTOC_KX4_SUPP;
2606 if ((orig_autoc & TXGBE_AUTOC_KR_SUPP) &&
2607 !hw->phy.smart_speed_active)
2608 autoc |= TXGBE_AUTOC_KR_SUPP;
2610 if (speed & TXGBE_LINK_SPEED_1GB_FULL)
2611 autoc |= TXGBE_AUTOC_KX_SUPP;
2612 } else if ((pma_pmd_1g == TXGBE_AUTOC_1G_SFI) &&
2613 (link_mode == TXGBE_AUTOC_LMS_1G_LINK_NO_AN ||
2614 link_mode == TXGBE_AUTOC_LMS_1G_AN)) {
2615 /* Switch from 1G SFI to 10G SFI if requested */
2616 if (speed == TXGBE_LINK_SPEED_10GB_FULL &&
2617 pma_pmd_10gs == TXGBE_AUTOC_10GS_SFI) {
2618 autoc &= ~TXGBE_AUTOC_LMS_MASK;
2619 autoc |= TXGBE_AUTOC_LMS_10G;
2621 } else if ((pma_pmd_10gs == TXGBE_AUTOC_10GS_SFI) &&
2622 (link_mode == TXGBE_AUTOC_LMS_10G)) {
2623 /* Switch from 10G SFI to 1G SFI if requested */
2624 if (speed == TXGBE_LINK_SPEED_1GB_FULL &&
2625 pma_pmd_1g == TXGBE_AUTOC_1G_SFI) {
2626 autoc &= ~TXGBE_AUTOC_LMS_MASK;
2627 if (autoneg || hw->phy.type == txgbe_phy_qsfp_intel)
2628 autoc |= TXGBE_AUTOC_LMS_1G_AN;
2630 autoc |= TXGBE_AUTOC_LMS_1G_LINK_NO_AN;
2634 if (autoc == current_autoc)
2637 autoc &= ~TXGBE_AUTOC_SPEED_MASK;
2638 autoc |= TXGBE_AUTOC_SPEED(speed);
2639 autoc |= (autoneg ? TXGBE_AUTOC_AUTONEG : 0);
2642 hw->mac.autoc_write(hw, autoc);
2644 /* Only poll for autoneg to complete if specified to do so */
2645 if (autoneg_wait_to_complete) {
2646 if (link_mode == TXGBE_AUTOC_LMS_KX4_KX_KR ||
2647 link_mode == TXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
2648 link_mode == TXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
2649 links_reg = 0; /*Just in case Autoneg time=0*/
2650 for (i = 0; i < TXGBE_AUTO_NEG_TIME; i++) {
2651 links_reg = rd32(hw, TXGBE_PORTSTAT);
2652 if (links_reg & TXGBE_PORTSTAT_UP)
2656 if (!(links_reg & TXGBE_PORTSTAT_UP)) {
2657 status = TXGBE_ERR_AUTONEG_NOT_COMPLETE;
2658 DEBUGOUT("Autoneg did not complete.\n");
2663 /* Add delay to filter out noises during initial link setup */
2670 * txgbe_setup_copper_link_raptor - Set the PHY autoneg advertised field
2671 * @hw: pointer to hardware structure
2672 * @speed: new link speed
2673 * @autoneg_wait_to_complete: true if waiting is needed to complete
2675 * Restarts link on PHY and MAC based on settings passed in.
2677 static s32 txgbe_setup_copper_link_raptor(struct txgbe_hw *hw,
2679 bool autoneg_wait_to_complete)
2683 DEBUGFUNC("txgbe_setup_copper_link_raptor");
2685 /* Setup the PHY according to input speed */
2686 status = hw->phy.setup_link_speed(hw, speed,
2687 autoneg_wait_to_complete);
2689 txgbe_start_mac_link_raptor(hw, autoneg_wait_to_complete);
2695 txgbe_check_flash_load(struct txgbe_hw *hw, u32 check_bit)
2700 /* if there's flash existing */
2701 if (!(rd32(hw, TXGBE_SPISTAT) & TXGBE_SPISTAT_BPFLASH)) {
2702 /* wait hw load flash done */
2703 for (i = 0; i < 10; i++) {
2704 reg = rd32(hw, TXGBE_ILDRSTAT);
2705 if (!(reg & check_bit)) {
2712 err = TXGBE_ERR_FLASH_LOADING_FAILED;
2718 txgbe_reset_misc(struct txgbe_hw *hw)
2723 wr32(hw, TXGBE_ISBADDRL, hw->isb_dma & 0x00000000FFFFFFFF);
2724 wr32(hw, TXGBE_ISBADDRH, hw->isb_dma >> 32);
2726 value = rd32_epcs(hw, SR_XS_PCS_CTRL2);
2727 if ((value & 0x3) != SR_PCS_CTRL2_TYPE_SEL_X)
2728 hw->link_status = TXGBE_LINK_STATUS_NONE;
2730 /* receive packets that size > 2048 */
2731 wr32m(hw, TXGBE_MACRXCFG,
2732 TXGBE_MACRXCFG_JUMBO, TXGBE_MACRXCFG_JUMBO);
2734 wr32m(hw, TXGBE_FRMSZ, TXGBE_FRMSZ_MAX_MASK,
2735 TXGBE_FRMSZ_MAX(TXGBE_FRAME_SIZE_DFT));
2737 /* clear counters on read */
2738 wr32m(hw, TXGBE_MACCNTCTL,
2739 TXGBE_MACCNTCTL_RC, TXGBE_MACCNTCTL_RC);
2741 wr32m(hw, TXGBE_RXFCCFG,
2742 TXGBE_RXFCCFG_FC, TXGBE_RXFCCFG_FC);
2743 wr32m(hw, TXGBE_TXFCCFG,
2744 TXGBE_TXFCCFG_FC, TXGBE_TXFCCFG_FC);
2746 wr32m(hw, TXGBE_MACRXFLT,
2747 TXGBE_MACRXFLT_PROMISC, TXGBE_MACRXFLT_PROMISC);
2749 wr32m(hw, TXGBE_RSTSTAT,
2750 TXGBE_RSTSTAT_TMRINIT_MASK, TXGBE_RSTSTAT_TMRINIT(30));
2752 /* errata 4: initialize mng flex tbl and wakeup flex tbl*/
2753 wr32(hw, TXGBE_MNGFLEXSEL, 0);
2754 for (i = 0; i < 16; i++) {
2755 wr32(hw, TXGBE_MNGFLEXDWL(i), 0);
2756 wr32(hw, TXGBE_MNGFLEXDWH(i), 0);
2757 wr32(hw, TXGBE_MNGFLEXMSK(i), 0);
2759 wr32(hw, TXGBE_LANFLEXSEL, 0);
2760 for (i = 0; i < 16; i++) {
2761 wr32(hw, TXGBE_LANFLEXDWL(i), 0);
2762 wr32(hw, TXGBE_LANFLEXDWH(i), 0);
2763 wr32(hw, TXGBE_LANFLEXMSK(i), 0);
2766 /* set pause frame dst mac addr */
2767 wr32(hw, TXGBE_RXPBPFCDMACL, 0xC2000001);
2768 wr32(hw, TXGBE_RXPBPFCDMACH, 0x0180);
2770 hw->mac.init_thermal_sensor_thresh(hw);
2772 /* enable mac transmitter */
2773 wr32m(hw, TXGBE_MACTXCFG, TXGBE_MACTXCFG_TXE, TXGBE_MACTXCFG_TXE);
2775 for (i = 0; i < 4; i++)
2776 wr32m(hw, TXGBE_IVAR(i), 0x80808080, 0);
2780 * txgbe_reset_hw - Perform hardware reset
2781 * @hw: pointer to hardware structure
2783 * Resets the hardware by resetting the transmit and receive units, masks
2784 * and clears all interrupts, perform a PHY reset, and perform a link (MAC)
2787 s32 txgbe_reset_hw(struct txgbe_hw *hw)
2792 DEBUGFUNC("txgbe_reset_hw");
2794 /* Call adapter stop to disable tx/rx and clear interrupts */
2795 status = hw->mac.stop_hw(hw);
2799 /* flush pending Tx transactions */
2800 txgbe_clear_tx_pending(hw);
2802 /* Identify PHY and related function pointers */
2803 status = hw->phy.init(hw);
2804 if (status == TXGBE_ERR_SFP_NOT_SUPPORTED)
2807 /* Setup SFP module if there is one present. */
2808 if (hw->phy.sfp_setup_needed) {
2809 status = hw->mac.setup_sfp(hw);
2810 hw->phy.sfp_setup_needed = false;
2812 if (status == TXGBE_ERR_SFP_NOT_SUPPORTED)
2816 if (!hw->phy.reset_disable)
2819 /* remember AUTOC from before we reset */
2820 autoc = hw->mac.autoc_read(hw);
2824 * Issue global reset to the MAC. Needs to be SW reset if link is up.
2825 * If link reset is used when link is up, it might reset the PHY when
2826 * mng is using it. If link is down or the flag to force full link
2827 * reset is set, then perform link reset.
2829 if (txgbe_mng_present(hw)) {
2830 txgbe_hic_reset(hw);
2832 wr32(hw, TXGBE_RST, TXGBE_RST_LAN(hw->bus.lan_id));
2837 txgbe_reset_misc(hw);
2839 if (hw->bus.lan_id == 0) {
2840 status = txgbe_check_flash_load(hw,
2841 TXGBE_ILDRSTAT_SWRST_LAN0);
2843 status = txgbe_check_flash_load(hw,
2844 TXGBE_ILDRSTAT_SWRST_LAN1);
2852 * Double resets are required for recovery from certain error
2853 * conditions. Between resets, it is necessary to stall to
2854 * allow time for any pending HW events to complete.
2856 if (hw->mac.flags & TXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
2857 hw->mac.flags &= ~TXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
2862 * Store the original AUTOC/AUTOC2 values if they have not been
2863 * stored off yet. Otherwise restore the stored original
2864 * values since the reset operation sets back to defaults.
2866 if (!hw->mac.orig_link_settings_stored) {
2867 hw->mac.orig_autoc = hw->mac.autoc_read(hw);
2868 hw->mac.autoc_write(hw, hw->mac.orig_autoc);
2869 hw->mac.orig_link_settings_stored = true;
2871 hw->mac.orig_autoc = autoc;
2874 /* Store the permanent mac address */
2875 hw->mac.get_mac_addr(hw, hw->mac.perm_addr);
2878 * Store MAC address from RAR0, clear receive address registers, and
2879 * clear the multicast table. Also reset num_rar_entries to 128,
2880 * since we modify this value when programming the SAN MAC address.
2882 hw->mac.num_rar_entries = 128;
2883 hw->mac.init_rx_addrs(hw);
2885 /* Store the permanent SAN mac address */
2886 hw->mac.get_san_mac_addr(hw, hw->mac.san_addr);
2888 /* Add the SAN MAC address to the RAR only if it's a valid address */
2889 if (txgbe_validate_mac_addr(hw->mac.san_addr) == 0) {
2890 /* Save the SAN MAC RAR index */
2891 hw->mac.san_mac_rar_index = hw->mac.num_rar_entries - 1;
2893 hw->mac.set_rar(hw, hw->mac.san_mac_rar_index,
2894 hw->mac.san_addr, 0, true);
2896 /* clear VMDq pool/queue selection for this RAR */
2897 hw->mac.clear_vmdq(hw, hw->mac.san_mac_rar_index,
2900 /* Reserve the last RAR for the SAN MAC address */
2901 hw->mac.num_rar_entries--;
2904 /* Store the alternative WWNN/WWPN prefix */
2905 hw->mac.get_wwn_prefix(hw, &hw->mac.wwnn_prefix,
2906 &hw->mac.wwpn_prefix);
2912 * txgbe_start_hw_raptor - Prepare hardware for Tx/Rx
2913 * @hw: pointer to hardware structure
2915 * Starts the hardware using the generic start_hw function
2916 * and the generation start_hw function.
2917 * Then performs revision-specific operations, if any.
2919 s32 txgbe_start_hw_raptor(struct txgbe_hw *hw)
2923 DEBUGFUNC("txgbe_start_hw_raptor");
2925 err = txgbe_start_hw(hw);
2929 err = txgbe_start_hw_gen2(hw);
2933 /* We need to run link autotry after the driver loads */
2934 hw->mac.autotry_restart = true;
2941 * txgbe_enable_rx_dma_raptor - Enable the Rx DMA unit
2942 * @hw: pointer to hardware structure
2943 * @regval: register value to write to RXCTRL
2945 * Enables the Rx DMA unit
2947 s32 txgbe_enable_rx_dma_raptor(struct txgbe_hw *hw, u32 regval)
2949 DEBUGFUNC("txgbe_enable_rx_dma_raptor");
2952 * Workaround silicon errata when enabling the Rx datapath.
2953 * If traffic is incoming before we enable the Rx unit, it could hang
2954 * the Rx DMA unit. Therefore, make sure the security engine is
2955 * completely disabled prior to enabling the Rx unit.
2958 hw->mac.disable_sec_rx_path(hw);
2960 if (regval & TXGBE_PBRXCTL_ENA)
2961 txgbe_enable_rx(hw);
2963 txgbe_disable_rx(hw);
2965 hw->mac.enable_sec_rx_path(hw);
2971 * txgbe_verify_lesm_fw_enabled_raptor - Checks LESM FW module state.
2972 * @hw: pointer to hardware structure
2974 * Returns true if the LESM FW module is present and enabled. Otherwise
2975 * returns false. Smart Speed must be disabled if LESM FW module is enabled.
2977 bool txgbe_verify_lesm_fw_enabled_raptor(struct txgbe_hw *hw)
2979 bool lesm_enabled = false;
2980 u16 fw_offset, fw_lesm_param_offset, fw_lesm_state;
2983 DEBUGFUNC("txgbe_verify_lesm_fw_enabled_raptor");
2985 /* get the offset to the Firmware Module block */
2986 status = hw->rom.read16(hw, TXGBE_FW_PTR, &fw_offset);
2988 if (status != 0 || fw_offset == 0 || fw_offset == 0xFFFF)
2991 /* get the offset to the LESM Parameters block */
2992 status = hw->rom.read16(hw, (fw_offset +
2993 TXGBE_FW_LESM_PARAMETERS_PTR),
2994 &fw_lesm_param_offset);
2997 fw_lesm_param_offset == 0 || fw_lesm_param_offset == 0xFFFF)
3000 /* get the LESM state word */
3001 status = hw->rom.read16(hw, (fw_lesm_param_offset +
3002 TXGBE_FW_LESM_STATE_1),
3005 if (status == 0 && (fw_lesm_state & TXGBE_FW_LESM_STATE_ENABLED))
3006 lesm_enabled = true;
3009 lesm_enabled = false;
3010 return lesm_enabled;
3014 * txgbe_reset_pipeline_raptor - perform pipeline reset
3016 * @hw: pointer to hardware structure
3018 * Reset pipeline by asserting Restart_AN together with LMS change to ensure
3019 * full pipeline reset. This function assumes the SW/FW lock is held.
3021 s32 txgbe_reset_pipeline_raptor(struct txgbe_hw *hw)
3026 autoc = hw->mac.autoc_read(hw);
3028 /* Enable link if disabled in NVM */
3029 if (autoc & TXGBE_AUTOC_LINK_DIA_MASK)
3030 autoc &= ~TXGBE_AUTOC_LINK_DIA_MASK;
3032 autoc |= TXGBE_AUTOC_AN_RESTART;
3033 /* Write AUTOC register with toggled LMS[2] bit and Restart_AN */
3034 hw->mac.autoc_write(hw, autoc ^ TXGBE_AUTOC_LMS_AN);
3036 /* Write AUTOC register with original LMS field and Restart_AN */
3037 hw->mac.autoc_write(hw, autoc);