1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2015-2020
5 #include "txgbe_type.h"
7 #include "txgbe_eeprom.h"
11 #define TXGBE_RAPTOR_MAX_TX_QUEUES 128
12 #define TXGBE_RAPTOR_MAX_RX_QUEUES 128
13 #define TXGBE_RAPTOR_RAR_ENTRIES 128
14 #define TXGBE_RAPTOR_MC_TBL_SIZE 128
16 static s32 txgbe_setup_copper_link_raptor(struct txgbe_hw *hw,
18 bool autoneg_wait_to_complete);
20 static s32 txgbe_mta_vector(struct txgbe_hw *hw, u8 *mc_addr);
21 static s32 txgbe_get_san_mac_addr_offset(struct txgbe_hw *hw,
25 * txgbe_start_hw - Prepare hardware for Tx/Rx
26 * @hw: pointer to hardware structure
28 * Starts the hardware by filling the bus info structure and media type, clears
29 * all on chip counters, initializes receive address registers, multicast
30 * table, VLAN filter table, calls routine to set up link and flow control
31 * settings, and leaves transmit and receive units disabled and uninitialized
33 s32 txgbe_start_hw(struct txgbe_hw *hw)
37 DEBUGFUNC("txgbe_start_hw");
39 /* Set the media type */
40 hw->phy.media_type = hw->phy.get_media_type(hw);
42 /* Clear statistics registers */
43 hw->mac.clear_hw_cntrs(hw);
45 /* Cache bit indicating need for crosstalk fix */
46 switch (hw->mac.type) {
47 case txgbe_mac_raptor:
48 hw->mac.get_device_caps(hw, &device_caps);
49 if (device_caps & TXGBE_DEVICE_CAPS_NO_CROSSTALK_WR)
50 hw->need_crosstalk_fix = false;
52 hw->need_crosstalk_fix = true;
55 hw->need_crosstalk_fix = false;
59 /* Clear adapter stopped flag */
60 hw->adapter_stopped = false;
66 * txgbe_start_hw_gen2 - Init sequence for common device family
67 * @hw: pointer to hw structure
69 * Performs the init sequence common to the second generation
72 s32 txgbe_start_hw_gen2(struct txgbe_hw *hw)
76 /* Clear the rate limiters */
77 for (i = 0; i < hw->mac.max_tx_queues; i++) {
78 wr32(hw, TXGBE_ARBPOOLIDX, i);
79 wr32(hw, TXGBE_ARBTXRATE, 0);
83 /* We need to run link autotry after the driver loads */
84 hw->mac.autotry_restart = true;
90 * txgbe_init_hw - Generic hardware initialization
91 * @hw: pointer to hardware structure
93 * Initialize the hardware by resetting the hardware, filling the bus info
94 * structure and media type, clears all on chip counters, initializes receive
95 * address registers, multicast table, VLAN filter table, calls routine to set
96 * up link and flow control settings, and leaves transmit and receive units
97 * disabled and uninitialized
99 s32 txgbe_init_hw(struct txgbe_hw *hw)
103 DEBUGFUNC("txgbe_init_hw");
105 /* Reset the hardware */
106 status = hw->mac.reset_hw(hw);
107 if (status == 0 || status == TXGBE_ERR_SFP_NOT_PRESENT) {
109 status = hw->mac.start_hw(hw);
113 DEBUGOUT("Failed to initialize HW, STATUS = %d\n", status);
119 * txgbe_get_mac_addr - Generic get MAC address
120 * @hw: pointer to hardware structure
121 * @mac_addr: Adapter MAC address
123 * Reads the adapter's MAC address from first Receive Address Register (RAR0)
124 * A reset of the adapter must be performed prior to calling this function
125 * in order for the MAC address to have been loaded from the EEPROM into RAR0
127 s32 txgbe_get_mac_addr(struct txgbe_hw *hw, u8 *mac_addr)
133 DEBUGFUNC("txgbe_get_mac_addr");
135 wr32(hw, TXGBE_ETHADDRIDX, 0);
136 rar_high = rd32(hw, TXGBE_ETHADDRH);
137 rar_low = rd32(hw, TXGBE_ETHADDRL);
139 for (i = 0; i < 2; i++)
140 mac_addr[i] = (u8)(rar_high >> (1 - i) * 8);
142 for (i = 0; i < 4; i++)
143 mac_addr[i + 2] = (u8)(rar_low >> (3 - i) * 8);
149 * txgbe_set_lan_id_multi_port - Set LAN id for PCIe multiple port devices
150 * @hw: pointer to the HW structure
152 * Determines the LAN function id by reading memory-mapped registers and swaps
153 * the port value if requested, and set MAC instance for devices.
155 void txgbe_set_lan_id_multi_port(struct txgbe_hw *hw)
157 struct txgbe_bus_info *bus = &hw->bus;
160 DEBUGFUNC("txgbe_set_lan_id_multi_port_pcie");
162 reg = rd32(hw, TXGBE_PORTSTAT);
163 bus->lan_id = TXGBE_PORTSTAT_ID(reg);
165 /* check for single port */
166 reg = rd32(hw, TXGBE_PWR);
167 if (TXGBE_PWR_LANID(reg) == TXGBE_PWR_LANID_SWAP)
170 bus->func = bus->lan_id;
174 * txgbe_stop_hw - Generic stop Tx/Rx units
175 * @hw: pointer to hardware structure
177 * Sets the adapter_stopped flag within txgbe_hw struct. Clears interrupts,
178 * disables transmit and receive units. The adapter_stopped flag is used by
179 * the shared code and drivers to determine if the adapter is in a stopped
180 * state and should not touch the hardware.
182 s32 txgbe_stop_hw(struct txgbe_hw *hw)
187 DEBUGFUNC("txgbe_stop_hw");
190 * Set the adapter_stopped flag so other driver functions stop touching
193 hw->adapter_stopped = true;
195 /* Disable the receive unit */
196 txgbe_disable_rx(hw);
198 /* Clear interrupt mask to stop interrupts from being generated */
199 wr32(hw, TXGBE_IENMISC, 0);
200 wr32(hw, TXGBE_IMS(0), TXGBE_IMS_MASK);
201 wr32(hw, TXGBE_IMS(1), TXGBE_IMS_MASK);
203 /* Clear any pending interrupts, flush previous writes */
204 wr32(hw, TXGBE_ICRMISC, TXGBE_ICRMISC_MASK);
205 wr32(hw, TXGBE_ICR(0), TXGBE_ICR_MASK);
206 wr32(hw, TXGBE_ICR(1), TXGBE_ICR_MASK);
208 /* Disable the transmit unit. Each queue must be disabled. */
209 for (i = 0; i < hw->mac.max_tx_queues; i++)
210 wr32(hw, TXGBE_TXCFG(i), TXGBE_TXCFG_FLUSH);
212 /* Disable the receive unit by stopping each queue */
213 for (i = 0; i < hw->mac.max_rx_queues; i++) {
214 reg_val = rd32(hw, TXGBE_RXCFG(i));
215 reg_val &= ~TXGBE_RXCFG_ENA;
216 wr32(hw, TXGBE_RXCFG(i), reg_val);
219 /* flush all queues disables */
227 * txgbe_validate_mac_addr - Validate MAC address
228 * @mac_addr: pointer to MAC address.
230 * Tests a MAC address to ensure it is a valid Individual Address.
232 s32 txgbe_validate_mac_addr(u8 *mac_addr)
236 DEBUGFUNC("txgbe_validate_mac_addr");
238 /* Make sure it is not a multicast address */
239 if (TXGBE_IS_MULTICAST(mac_addr)) {
240 status = TXGBE_ERR_INVALID_MAC_ADDR;
241 /* Not a broadcast address */
242 } else if (TXGBE_IS_BROADCAST(mac_addr)) {
243 status = TXGBE_ERR_INVALID_MAC_ADDR;
244 /* Reject the zero address */
245 } else if (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 &&
246 mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0) {
247 status = TXGBE_ERR_INVALID_MAC_ADDR;
253 * txgbe_set_rar - Set Rx address register
254 * @hw: pointer to hardware structure
255 * @index: Receive address register to write
256 * @addr: Address to put into receive address register
257 * @vmdq: VMDq "set" or "pool" index
258 * @enable_addr: set flag that address is active
260 * Puts an ethernet address into a receive address register.
262 s32 txgbe_set_rar(struct txgbe_hw *hw, u32 index, u8 *addr, u32 vmdq,
265 u32 rar_low, rar_high;
266 u32 rar_entries = hw->mac.num_rar_entries;
268 DEBUGFUNC("txgbe_set_rar");
270 /* Make sure we are using a valid rar index range */
271 if (index >= rar_entries) {
272 DEBUGOUT("RAR index %d is out of range.\n", index);
273 return TXGBE_ERR_INVALID_ARGUMENT;
276 /* setup VMDq pool selection before this RAR gets enabled */
277 hw->mac.set_vmdq(hw, index, vmdq);
280 * HW expects these in little endian so we reverse the byte
281 * order from network order (big endian) to little endian
283 rar_low = TXGBE_ETHADDRL_AD0(addr[5]) |
284 TXGBE_ETHADDRL_AD1(addr[4]) |
285 TXGBE_ETHADDRL_AD2(addr[3]) |
286 TXGBE_ETHADDRL_AD3(addr[2]);
288 * Some parts put the VMDq setting in the extra RAH bits,
289 * so save everything except the lower 16 bits that hold part
290 * of the address and the address valid bit.
292 rar_high = rd32(hw, TXGBE_ETHADDRH);
293 rar_high &= ~TXGBE_ETHADDRH_AD_MASK;
294 rar_high |= (TXGBE_ETHADDRH_AD4(addr[1]) |
295 TXGBE_ETHADDRH_AD5(addr[0]));
297 rar_high &= ~TXGBE_ETHADDRH_VLD;
298 if (enable_addr != 0)
299 rar_high |= TXGBE_ETHADDRH_VLD;
301 wr32(hw, TXGBE_ETHADDRIDX, index);
302 wr32(hw, TXGBE_ETHADDRL, rar_low);
303 wr32(hw, TXGBE_ETHADDRH, rar_high);
309 * txgbe_clear_rar - Remove Rx address register
310 * @hw: pointer to hardware structure
311 * @index: Receive address register to write
313 * Clears an ethernet address from a receive address register.
315 s32 txgbe_clear_rar(struct txgbe_hw *hw, u32 index)
318 u32 rar_entries = hw->mac.num_rar_entries;
320 DEBUGFUNC("txgbe_clear_rar");
322 /* Make sure we are using a valid rar index range */
323 if (index >= rar_entries) {
324 DEBUGOUT("RAR index %d is out of range.\n", index);
325 return TXGBE_ERR_INVALID_ARGUMENT;
329 * Some parts put the VMDq setting in the extra RAH bits,
330 * so save everything except the lower 16 bits that hold part
331 * of the address and the address valid bit.
333 wr32(hw, TXGBE_ETHADDRIDX, index);
334 rar_high = rd32(hw, TXGBE_ETHADDRH);
335 rar_high &= ~(TXGBE_ETHADDRH_AD_MASK | TXGBE_ETHADDRH_VLD);
337 wr32(hw, TXGBE_ETHADDRL, 0);
338 wr32(hw, TXGBE_ETHADDRH, rar_high);
340 /* clear VMDq pool/queue selection for this RAR */
341 hw->mac.clear_vmdq(hw, index, BIT_MASK32);
347 * txgbe_init_rx_addrs - Initializes receive address filters.
348 * @hw: pointer to hardware structure
350 * Places the MAC address in receive address register 0 and clears the rest
351 * of the receive address registers. Clears the multicast table. Assumes
352 * the receiver is in reset when the routine is called.
354 s32 txgbe_init_rx_addrs(struct txgbe_hw *hw)
358 u32 rar_entries = hw->mac.num_rar_entries;
360 DEBUGFUNC("txgbe_init_rx_addrs");
363 * If the current mac address is valid, assume it is a software override
364 * to the permanent address.
365 * Otherwise, use the permanent address from the eeprom.
367 if (txgbe_validate_mac_addr(hw->mac.addr) ==
368 TXGBE_ERR_INVALID_MAC_ADDR) {
369 /* Get the MAC address from the RAR0 for later reference */
370 hw->mac.get_mac_addr(hw, hw->mac.addr);
372 DEBUGOUT(" Keeping Current RAR0 Addr =%.2X %.2X %.2X ",
373 hw->mac.addr[0], hw->mac.addr[1],
375 DEBUGOUT("%.2X %.2X %.2X\n", hw->mac.addr[3],
376 hw->mac.addr[4], hw->mac.addr[5]);
378 /* Setup the receive address. */
379 DEBUGOUT("Overriding MAC Address in RAR[0]\n");
380 DEBUGOUT(" New MAC Addr =%.2X %.2X %.2X ",
381 hw->mac.addr[0], hw->mac.addr[1],
383 DEBUGOUT("%.2X %.2X %.2X\n", hw->mac.addr[3],
384 hw->mac.addr[4], hw->mac.addr[5]);
386 hw->mac.set_rar(hw, 0, hw->mac.addr, 0, true);
389 /* clear VMDq pool/queue selection for RAR 0 */
390 hw->mac.clear_vmdq(hw, 0, BIT_MASK32);
392 hw->addr_ctrl.overflow_promisc = 0;
394 hw->addr_ctrl.rar_used_count = 1;
396 /* Zero out the other receive addresses. */
397 DEBUGOUT("Clearing RAR[1-%d]\n", rar_entries - 1);
398 for (i = 1; i < rar_entries; i++) {
399 wr32(hw, TXGBE_ETHADDRIDX, i);
400 wr32(hw, TXGBE_ETHADDRL, 0);
401 wr32(hw, TXGBE_ETHADDRH, 0);
405 hw->addr_ctrl.mta_in_use = 0;
406 psrctl = rd32(hw, TXGBE_PSRCTL);
407 psrctl &= ~(TXGBE_PSRCTL_ADHF12_MASK | TXGBE_PSRCTL_MCHFENA);
408 psrctl |= TXGBE_PSRCTL_ADHF12(hw->mac.mc_filter_type);
409 wr32(hw, TXGBE_PSRCTL, psrctl);
411 DEBUGOUT(" Clearing MTA\n");
412 for (i = 0; i < hw->mac.mcft_size; i++)
413 wr32(hw, TXGBE_MCADDRTBL(i), 0);
415 txgbe_init_uta_tables(hw);
421 * txgbe_mta_vector - Determines bit-vector in multicast table to set
422 * @hw: pointer to hardware structure
423 * @mc_addr: the multicast address
425 * Extracts the 12 bits, from a multicast address, to determine which
426 * bit-vector to set in the multicast table. The hardware uses 12 bits, from
427 * incoming rx multicast addresses, to determine the bit-vector to check in
428 * the MTA. Which of the 4 combination, of 12-bits, the hardware uses is set
429 * by the MO field of the PSRCTRL. The MO field is set during initialization
432 static s32 txgbe_mta_vector(struct txgbe_hw *hw, u8 *mc_addr)
436 DEBUGFUNC("txgbe_mta_vector");
438 switch (hw->mac.mc_filter_type) {
439 case 0: /* use bits [47:36] of the address */
440 vector = ((mc_addr[4] >> 4) | (((u16)mc_addr[5]) << 4));
442 case 1: /* use bits [46:35] of the address */
443 vector = ((mc_addr[4] >> 3) | (((u16)mc_addr[5]) << 5));
445 case 2: /* use bits [45:34] of the address */
446 vector = ((mc_addr[4] >> 2) | (((u16)mc_addr[5]) << 6));
448 case 3: /* use bits [43:32] of the address */
449 vector = ((mc_addr[4]) | (((u16)mc_addr[5]) << 8));
451 default: /* Invalid mc_filter_type */
452 DEBUGOUT("MC filter type param set incorrectly\n");
457 /* vector can only be 12-bits or boundary will be exceeded */
463 * txgbe_set_mta - Set bit-vector in multicast table
464 * @hw: pointer to hardware structure
465 * @mc_addr: Multicast address
467 * Sets the bit-vector in the multicast table.
469 void txgbe_set_mta(struct txgbe_hw *hw, u8 *mc_addr)
475 DEBUGFUNC("txgbe_set_mta");
477 hw->addr_ctrl.mta_in_use++;
479 vector = txgbe_mta_vector(hw, mc_addr);
480 DEBUGOUT(" bit-vector = 0x%03X\n", vector);
483 * The MTA is a register array of 128 32-bit registers. It is treated
484 * like an array of 4096 bits. We want to set bit
485 * BitArray[vector_value]. So we figure out what register the bit is
486 * in, read it, OR in the new bit, then write back the new value. The
487 * register is determined by the upper 7 bits of the vector value and
488 * the bit within that register are determined by the lower 5 bits of
491 vector_reg = (vector >> 5) & 0x7F;
492 vector_bit = vector & 0x1F;
493 hw->mac.mta_shadow[vector_reg] |= (1 << vector_bit);
497 * txgbe_update_mc_addr_list - Updates MAC list of multicast addresses
498 * @hw: pointer to hardware structure
499 * @mc_addr_list: the list of new multicast addresses
500 * @mc_addr_count: number of addresses
501 * @next: iterator function to walk the multicast address list
502 * @clear: flag, when set clears the table beforehand
504 * When the clear flag is set, the given list replaces any existing list.
505 * Hashes the given addresses into the multicast table.
507 s32 txgbe_update_mc_addr_list(struct txgbe_hw *hw, u8 *mc_addr_list,
508 u32 mc_addr_count, txgbe_mc_addr_itr next,
514 DEBUGFUNC("txgbe_update_mc_addr_list");
517 * Set the new number of MC addresses that we are being requested to
520 hw->addr_ctrl.num_mc_addrs = mc_addr_count;
521 hw->addr_ctrl.mta_in_use = 0;
523 /* Clear mta_shadow */
525 DEBUGOUT(" Clearing MTA\n");
526 memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow));
529 /* Update mta_shadow */
530 for (i = 0; i < mc_addr_count; i++) {
531 DEBUGOUT(" Adding the multicast addresses:\n");
532 txgbe_set_mta(hw, next(hw, &mc_addr_list, &vmdq));
536 for (i = 0; i < hw->mac.mcft_size; i++)
537 wr32a(hw, TXGBE_MCADDRTBL(0), i,
538 hw->mac.mta_shadow[i]);
540 if (hw->addr_ctrl.mta_in_use > 0) {
541 u32 psrctl = rd32(hw, TXGBE_PSRCTL);
542 psrctl &= ~(TXGBE_PSRCTL_ADHF12_MASK | TXGBE_PSRCTL_MCHFENA);
543 psrctl |= TXGBE_PSRCTL_MCHFENA |
544 TXGBE_PSRCTL_ADHF12(hw->mac.mc_filter_type);
545 wr32(hw, TXGBE_PSRCTL, psrctl);
548 DEBUGOUT("txgbe update mc addr list complete\n");
553 * txgbe_disable_sec_rx_path - Stops the receive data path
554 * @hw: pointer to hardware structure
556 * Stops the receive data path and waits for the HW to internally empty
557 * the Rx security block
559 s32 txgbe_disable_sec_rx_path(struct txgbe_hw *hw)
561 #define TXGBE_MAX_SECRX_POLL 4000
566 DEBUGFUNC("txgbe_disable_sec_rx_path");
568 secrxreg = rd32(hw, TXGBE_SECRXCTL);
569 secrxreg |= TXGBE_SECRXCTL_XDSA;
570 wr32(hw, TXGBE_SECRXCTL, secrxreg);
571 for (i = 0; i < TXGBE_MAX_SECRX_POLL; i++) {
572 secrxreg = rd32(hw, TXGBE_SECRXSTAT);
573 if (!(secrxreg & TXGBE_SECRXSTAT_RDY))
574 /* Use interrupt-safe sleep just in case */
580 /* For informational purposes only */
581 if (i >= TXGBE_MAX_SECRX_POLL)
582 DEBUGOUT("Rx unit being enabled before security "
583 "path fully disabled. Continuing with init.\n");
589 * txgbe_enable_sec_rx_path - Enables the receive data path
590 * @hw: pointer to hardware structure
592 * Enables the receive data path.
594 s32 txgbe_enable_sec_rx_path(struct txgbe_hw *hw)
598 DEBUGFUNC("txgbe_enable_sec_rx_path");
600 secrxreg = rd32(hw, TXGBE_SECRXCTL);
601 secrxreg &= ~TXGBE_SECRXCTL_XDSA;
602 wr32(hw, TXGBE_SECRXCTL, secrxreg);
609 * txgbe_disable_sec_tx_path - Stops the transmit data path
610 * @hw: pointer to hardware structure
612 * Stops the transmit data path and waits for the HW to internally empty
613 * the Tx security block
615 int txgbe_disable_sec_tx_path(struct txgbe_hw *hw)
617 #define TXGBE_MAX_SECTX_POLL 40
622 sectxreg = rd32(hw, TXGBE_SECTXCTL);
623 sectxreg |= TXGBE_SECTXCTL_XDSA;
624 wr32(hw, TXGBE_SECTXCTL, sectxreg);
625 for (i = 0; i < TXGBE_MAX_SECTX_POLL; i++) {
626 sectxreg = rd32(hw, TXGBE_SECTXSTAT);
627 if (sectxreg & TXGBE_SECTXSTAT_RDY)
629 /* Use interrupt-safe sleep just in case */
633 /* For informational purposes only */
634 if (i >= TXGBE_MAX_SECTX_POLL)
635 PMD_DRV_LOG(DEBUG, "Tx unit being enabled before security "
636 "path fully disabled. Continuing with init.");
642 * txgbe_enable_sec_tx_path - Enables the transmit data path
643 * @hw: pointer to hardware structure
645 * Enables the transmit data path.
647 int txgbe_enable_sec_tx_path(struct txgbe_hw *hw)
651 sectxreg = rd32(hw, TXGBE_SECTXCTL);
652 sectxreg &= ~TXGBE_SECTXCTL_XDSA;
653 wr32(hw, TXGBE_SECTXCTL, sectxreg);
660 * txgbe_get_san_mac_addr_offset - Get SAN MAC address offset from the EEPROM
661 * @hw: pointer to hardware structure
662 * @san_mac_offset: SAN MAC address offset
664 * This function will read the EEPROM location for the SAN MAC address
665 * pointer, and returns the value at that location. This is used in both
666 * get and set mac_addr routines.
668 static s32 txgbe_get_san_mac_addr_offset(struct txgbe_hw *hw,
673 DEBUGFUNC("txgbe_get_san_mac_addr_offset");
676 * First read the EEPROM pointer to see if the MAC addresses are
679 err = hw->rom.readw_sw(hw, TXGBE_SAN_MAC_ADDR_PTR,
682 DEBUGOUT("eeprom at offset %d failed",
683 TXGBE_SAN_MAC_ADDR_PTR);
690 * txgbe_get_san_mac_addr - SAN MAC address retrieval from the EEPROM
691 * @hw: pointer to hardware structure
692 * @san_mac_addr: SAN MAC address
694 * Reads the SAN MAC address from the EEPROM, if it's available. This is
695 * per-port, so set_lan_id() must be called before reading the addresses.
696 * set_lan_id() is called by identify_sfp(), but this cannot be relied
697 * upon for non-SFP connections, so we must call it here.
699 s32 txgbe_get_san_mac_addr(struct txgbe_hw *hw, u8 *san_mac_addr)
701 u16 san_mac_data, san_mac_offset;
705 DEBUGFUNC("txgbe_get_san_mac_addr");
708 * First read the EEPROM pointer to see if the MAC addresses are
709 * available. If they're not, no point in calling set_lan_id() here.
711 err = txgbe_get_san_mac_addr_offset(hw, &san_mac_offset);
712 if (err || san_mac_offset == 0 || san_mac_offset == 0xFFFF)
713 goto san_mac_addr_out;
715 /* apply the port offset to the address offset */
716 (hw->bus.func) ? (san_mac_offset += TXGBE_SAN_MAC_ADDR_PORT1_OFFSET) :
717 (san_mac_offset += TXGBE_SAN_MAC_ADDR_PORT0_OFFSET);
718 for (i = 0; i < 3; i++) {
719 err = hw->rom.read16(hw, san_mac_offset,
722 DEBUGOUT("eeprom read at offset %d failed",
724 goto san_mac_addr_out;
726 san_mac_addr[i * 2] = (u8)(san_mac_data);
727 san_mac_addr[i * 2 + 1] = (u8)(san_mac_data >> 8);
734 * No addresses available in this EEPROM. It's not an
735 * error though, so just wipe the local address and return.
737 for (i = 0; i < 6; i++)
738 san_mac_addr[i] = 0xFF;
743 * txgbe_set_san_mac_addr - Write the SAN MAC address to the EEPROM
744 * @hw: pointer to hardware structure
745 * @san_mac_addr: SAN MAC address
747 * Write a SAN MAC address to the EEPROM.
749 s32 txgbe_set_san_mac_addr(struct txgbe_hw *hw, u8 *san_mac_addr)
752 u16 san_mac_data, san_mac_offset;
755 DEBUGFUNC("txgbe_set_san_mac_addr");
757 /* Look for SAN mac address pointer. If not defined, return */
758 err = txgbe_get_san_mac_addr_offset(hw, &san_mac_offset);
759 if (err || san_mac_offset == 0 || san_mac_offset == 0xFFFF)
760 return TXGBE_ERR_NO_SAN_ADDR_PTR;
762 /* Apply the port offset to the address offset */
763 (hw->bus.func) ? (san_mac_offset += TXGBE_SAN_MAC_ADDR_PORT1_OFFSET) :
764 (san_mac_offset += TXGBE_SAN_MAC_ADDR_PORT0_OFFSET);
766 for (i = 0; i < 3; i++) {
767 san_mac_data = (u16)((u16)(san_mac_addr[i * 2 + 1]) << 8);
768 san_mac_data |= (u16)(san_mac_addr[i * 2]);
769 hw->rom.write16(hw, san_mac_offset, san_mac_data);
777 * txgbe_init_uta_tables - Initialize the Unicast Table Array
778 * @hw: pointer to hardware structure
780 s32 txgbe_init_uta_tables(struct txgbe_hw *hw)
784 DEBUGFUNC("txgbe_init_uta_tables");
785 DEBUGOUT(" Clearing UTA\n");
787 for (i = 0; i < 128; i++)
788 wr32(hw, TXGBE_UCADDRTBL(i), 0);
794 * txgbe_need_crosstalk_fix - Determine if we need to do cross talk fix
795 * @hw: pointer to hardware structure
797 * Contains the logic to identify if we need to verify link for the
800 static bool txgbe_need_crosstalk_fix(struct txgbe_hw *hw)
802 /* Does FW say we need the fix */
803 if (!hw->need_crosstalk_fix)
806 /* Only consider SFP+ PHYs i.e. media type fiber */
807 switch (hw->phy.media_type) {
808 case txgbe_media_type_fiber:
809 case txgbe_media_type_fiber_qsfp:
819 * txgbe_check_mac_link - Determine link and speed status
820 * @hw: pointer to hardware structure
821 * @speed: pointer to link speed
822 * @link_up: true when link is up
823 * @link_up_wait_to_complete: bool used to wait for link up or not
825 * Reads the links register to determine if link is up and the current speed
827 s32 txgbe_check_mac_link(struct txgbe_hw *hw, u32 *speed,
828 bool *link_up, bool link_up_wait_to_complete)
830 u32 links_reg, links_orig;
833 DEBUGFUNC("txgbe_check_mac_link");
835 /* If Crosstalk fix enabled do the sanity check of making sure
836 * the SFP+ cage is full.
838 if (txgbe_need_crosstalk_fix(hw)) {
841 switch (hw->mac.type) {
842 case txgbe_mac_raptor:
843 sfp_cage_full = !rd32m(hw, TXGBE_GPIODATA,
847 /* sanity check - No SFP+ devices here */
848 sfp_cage_full = false;
852 if (!sfp_cage_full) {
854 *speed = TXGBE_LINK_SPEED_UNKNOWN;
859 /* clear the old state */
860 links_orig = rd32(hw, TXGBE_PORTSTAT);
862 links_reg = rd32(hw, TXGBE_PORTSTAT);
864 if (links_orig != links_reg) {
865 DEBUGOUT("LINKS changed from %08X to %08X\n",
866 links_orig, links_reg);
869 if (link_up_wait_to_complete) {
870 for (i = 0; i < hw->mac.max_link_up_time; i++) {
871 if (!(links_reg & TXGBE_PORTSTAT_UP)) {
878 links_reg = rd32(hw, TXGBE_PORTSTAT);
881 if (links_reg & TXGBE_PORTSTAT_UP)
887 switch (links_reg & TXGBE_PORTSTAT_BW_MASK) {
888 case TXGBE_PORTSTAT_BW_10G:
889 *speed = TXGBE_LINK_SPEED_10GB_FULL;
891 case TXGBE_PORTSTAT_BW_1G:
892 *speed = TXGBE_LINK_SPEED_1GB_FULL;
894 case TXGBE_PORTSTAT_BW_100M:
895 *speed = TXGBE_LINK_SPEED_100M_FULL;
898 *speed = TXGBE_LINK_SPEED_UNKNOWN;
905 * txgbe_get_device_caps - Get additional device capabilities
906 * @hw: pointer to hardware structure
907 * @device_caps: the EEPROM word with the extra device capabilities
909 * This function will read the EEPROM location for the device capabilities,
910 * and return the word through device_caps.
912 s32 txgbe_get_device_caps(struct txgbe_hw *hw, u16 *device_caps)
914 DEBUGFUNC("txgbe_get_device_caps");
916 hw->rom.readw_sw(hw, TXGBE_DEVICE_CAPS, device_caps);
922 * txgbe_clear_tx_pending - Clear pending TX work from the PCIe fifo
923 * @hw: pointer to the hardware structure
925 * The MACs can experience issues if TX work is still pending
926 * when a reset occurs. This function prevents this by flushing the PCIe
927 * buffers on the system.
929 void txgbe_clear_tx_pending(struct txgbe_hw *hw)
934 * If double reset is not requested then all transactions should
935 * already be clear and as such there is no work to do
937 if (!(hw->mac.flags & TXGBE_FLAGS_DOUBLE_RESET_REQUIRED))
940 hlreg0 = rd32(hw, TXGBE_PSRCTL);
941 wr32(hw, TXGBE_PSRCTL, hlreg0 | TXGBE_PSRCTL_LBENA);
943 /* Wait for a last completion before clearing buffers */
948 * Before proceeding, make sure that the PCIe block does not have
949 * transactions pending.
951 poll = (800 * 11) / 10;
952 for (i = 0; i < poll; i++)
955 /* Flush all writes and allow 20usec for all transactions to clear */
959 /* restore previous register values */
960 wr32(hw, TXGBE_PSRCTL, hlreg0);
963 void txgbe_disable_rx(struct txgbe_hw *hw)
967 pfdtxgswc = rd32(hw, TXGBE_PSRCTL);
968 if (pfdtxgswc & TXGBE_PSRCTL_LBENA) {
969 pfdtxgswc &= ~TXGBE_PSRCTL_LBENA;
970 wr32(hw, TXGBE_PSRCTL, pfdtxgswc);
971 hw->mac.set_lben = true;
973 hw->mac.set_lben = false;
976 wr32m(hw, TXGBE_PBRXCTL, TXGBE_PBRXCTL_ENA, 0);
977 wr32m(hw, TXGBE_MACRXCFG, TXGBE_MACRXCFG_ENA, 0);
980 void txgbe_enable_rx(struct txgbe_hw *hw)
984 wr32m(hw, TXGBE_MACRXCFG, TXGBE_MACRXCFG_ENA, TXGBE_MACRXCFG_ENA);
985 wr32m(hw, TXGBE_PBRXCTL, TXGBE_PBRXCTL_ENA, TXGBE_PBRXCTL_ENA);
987 if (hw->mac.set_lben) {
988 pfdtxgswc = rd32(hw, TXGBE_PSRCTL);
989 pfdtxgswc |= TXGBE_PSRCTL_LBENA;
990 wr32(hw, TXGBE_PSRCTL, pfdtxgswc);
991 hw->mac.set_lben = false;
996 * txgbe_setup_mac_link_multispeed_fiber - Set MAC link speed
997 * @hw: pointer to hardware structure
998 * @speed: new link speed
999 * @autoneg_wait_to_complete: true when waiting for completion is needed
1001 * Set the link speed in the MAC and/or PHY register and restarts link.
1003 s32 txgbe_setup_mac_link_multispeed_fiber(struct txgbe_hw *hw,
1005 bool autoneg_wait_to_complete)
1007 u32 link_speed = TXGBE_LINK_SPEED_UNKNOWN;
1008 u32 highest_link_speed = TXGBE_LINK_SPEED_UNKNOWN;
1012 bool autoneg, link_up = false;
1014 DEBUGFUNC("txgbe_setup_mac_link_multispeed_fiber");
1016 /* Mask off requested but non-supported speeds */
1017 status = hw->mac.get_link_capabilities(hw, &link_speed, &autoneg);
1021 speed &= link_speed;
1023 /* Try each speed one by one, highest priority first. We do this in
1024 * software because 10Gb fiber doesn't support speed autonegotiation.
1026 if (speed & TXGBE_LINK_SPEED_10GB_FULL) {
1028 highest_link_speed = TXGBE_LINK_SPEED_10GB_FULL;
1030 /* Set the module link speed */
1031 switch (hw->phy.media_type) {
1032 case txgbe_media_type_fiber:
1033 hw->mac.set_rate_select_speed(hw,
1034 TXGBE_LINK_SPEED_10GB_FULL);
1036 case txgbe_media_type_fiber_qsfp:
1037 /* QSFP module automatically detects MAC link speed */
1040 DEBUGOUT("Unexpected media type.\n");
1044 /* Allow module to change analog characteristics (1G->10G) */
1047 status = hw->mac.setup_mac_link(hw,
1048 TXGBE_LINK_SPEED_10GB_FULL,
1049 autoneg_wait_to_complete);
1053 /* Flap the Tx laser if it has not already been done */
1054 hw->mac.flap_tx_laser(hw);
1056 /* Wait for the controller to acquire link. Per IEEE 802.3ap,
1057 * Section 73.10.2, we may have to wait up to 500ms if KR is
1058 * attempted. uses the same timing for 10g SFI.
1060 for (i = 0; i < 5; i++) {
1061 /* Wait for the link partner to also set speed */
1064 /* If we have link, just jump out */
1065 status = hw->mac.check_link(hw, &link_speed,
1075 if (speed & TXGBE_LINK_SPEED_1GB_FULL) {
1077 if (highest_link_speed == TXGBE_LINK_SPEED_UNKNOWN)
1078 highest_link_speed = TXGBE_LINK_SPEED_1GB_FULL;
1080 /* Set the module link speed */
1081 switch (hw->phy.media_type) {
1082 case txgbe_media_type_fiber:
1083 hw->mac.set_rate_select_speed(hw,
1084 TXGBE_LINK_SPEED_1GB_FULL);
1086 case txgbe_media_type_fiber_qsfp:
1087 /* QSFP module automatically detects link speed */
1090 DEBUGOUT("Unexpected media type.\n");
1094 /* Allow module to change analog characteristics (10G->1G) */
1097 status = hw->mac.setup_mac_link(hw,
1098 TXGBE_LINK_SPEED_1GB_FULL,
1099 autoneg_wait_to_complete);
1103 /* Flap the Tx laser if it has not already been done */
1104 hw->mac.flap_tx_laser(hw);
1106 /* Wait for the link partner to also set speed */
1109 /* If we have link, just jump out */
1110 status = hw->mac.check_link(hw, &link_speed, &link_up, false);
1118 /* We didn't get link. Configure back to the highest speed we tried,
1119 * (if there was more than one). We call ourselves back with just the
1120 * single highest speed that the user requested.
1123 status = txgbe_setup_mac_link_multispeed_fiber(hw,
1125 autoneg_wait_to_complete);
1128 /* Set autoneg_advertised value based on input link speed */
1129 hw->phy.autoneg_advertised = 0;
1131 if (speed & TXGBE_LINK_SPEED_10GB_FULL)
1132 hw->phy.autoneg_advertised |= TXGBE_LINK_SPEED_10GB_FULL;
1134 if (speed & TXGBE_LINK_SPEED_1GB_FULL)
1135 hw->phy.autoneg_advertised |= TXGBE_LINK_SPEED_1GB_FULL;
1141 * txgbe_init_shared_code - Initialize the shared code
1142 * @hw: pointer to hardware structure
1144 * This will assign function pointers and assign the MAC type and PHY code.
1145 * Does not touch the hardware. This function must be called prior to any
1146 * other function in the shared code. The txgbe_hw structure should be
1147 * memset to 0 prior to calling this function. The following fields in
1148 * hw structure should be filled in prior to calling this function:
1149 * hw_addr, back, device_id, vendor_id, subsystem_device_id,
1150 * subsystem_vendor_id, and revision_id
1152 s32 txgbe_init_shared_code(struct txgbe_hw *hw)
1156 DEBUGFUNC("txgbe_init_shared_code");
1161 txgbe_set_mac_type(hw);
1163 txgbe_init_ops_dummy(hw);
1164 switch (hw->mac.type) {
1165 case txgbe_mac_raptor:
1166 status = txgbe_init_ops_pf(hw);
1169 status = TXGBE_ERR_DEVICE_NOT_SUPPORTED;
1172 hw->mac.max_link_up_time = TXGBE_LINK_UP_TIME;
1174 hw->bus.set_lan_id(hw);
1180 * txgbe_set_mac_type - Sets MAC type
1181 * @hw: pointer to the HW structure
1183 * This function sets the mac type of the adapter based on the
1184 * vendor ID and device ID stored in the hw structure.
1186 s32 txgbe_set_mac_type(struct txgbe_hw *hw)
1190 DEBUGFUNC("txgbe_set_mac_type");
1192 if (hw->vendor_id != PCI_VENDOR_ID_WANGXUN) {
1193 DEBUGOUT("Unsupported vendor id: %x", hw->vendor_id);
1194 return TXGBE_ERR_DEVICE_NOT_SUPPORTED;
1197 switch (hw->device_id) {
1198 case TXGBE_DEV_ID_RAPTOR_KR_KX_KX4:
1199 hw->phy.media_type = txgbe_media_type_backplane;
1200 hw->mac.type = txgbe_mac_raptor;
1202 case TXGBE_DEV_ID_RAPTOR_XAUI:
1203 case TXGBE_DEV_ID_RAPTOR_SGMII:
1204 hw->phy.media_type = txgbe_media_type_copper;
1205 hw->mac.type = txgbe_mac_raptor;
1207 case TXGBE_DEV_ID_RAPTOR_SFP:
1208 case TXGBE_DEV_ID_WX1820_SFP:
1209 hw->phy.media_type = txgbe_media_type_fiber;
1210 hw->mac.type = txgbe_mac_raptor;
1212 case TXGBE_DEV_ID_RAPTOR_QSFP:
1213 hw->phy.media_type = txgbe_media_type_fiber_qsfp;
1214 hw->mac.type = txgbe_mac_raptor;
1216 case TXGBE_DEV_ID_RAPTOR_VF:
1217 case TXGBE_DEV_ID_RAPTOR_VF_HV:
1218 hw->phy.media_type = txgbe_media_type_virtual;
1219 hw->mac.type = txgbe_mac_raptor_vf;
1222 err = TXGBE_ERR_DEVICE_NOT_SUPPORTED;
1223 DEBUGOUT("Unsupported device id: %x", hw->device_id);
1227 DEBUGOUT("found mac: %d media: %d, returns: %d\n",
1228 hw->mac.type, hw->phy.media_type, err);
1232 void txgbe_init_mac_link_ops(struct txgbe_hw *hw)
1234 struct txgbe_mac_info *mac = &hw->mac;
1236 DEBUGFUNC("txgbe_init_mac_link_ops");
1239 * enable the laser control functions for SFP+ fiber
1240 * and MNG not enabled
1242 if (hw->phy.media_type == txgbe_media_type_fiber &&
1243 !txgbe_mng_enabled(hw)) {
1244 mac->disable_tx_laser =
1245 txgbe_disable_tx_laser_multispeed_fiber;
1246 mac->enable_tx_laser =
1247 txgbe_enable_tx_laser_multispeed_fiber;
1248 mac->flap_tx_laser =
1249 txgbe_flap_tx_laser_multispeed_fiber;
1252 if ((hw->phy.media_type == txgbe_media_type_fiber ||
1253 hw->phy.media_type == txgbe_media_type_fiber_qsfp) &&
1254 hw->phy.multispeed_fiber) {
1255 /* Set up dual speed SFP+ support */
1256 mac->setup_link = txgbe_setup_mac_link_multispeed_fiber;
1257 mac->setup_mac_link = txgbe_setup_mac_link;
1258 mac->set_rate_select_speed = txgbe_set_hard_rate_select_speed;
1259 } else if ((hw->phy.media_type == txgbe_media_type_backplane) &&
1260 (hw->phy.smart_speed == txgbe_smart_speed_auto ||
1261 hw->phy.smart_speed == txgbe_smart_speed_on) &&
1262 !txgbe_verify_lesm_fw_enabled_raptor(hw)) {
1263 mac->setup_link = txgbe_setup_mac_link_smartspeed;
1265 mac->setup_link = txgbe_setup_mac_link;
1270 * txgbe_init_phy_raptor - PHY/SFP specific init
1271 * @hw: pointer to hardware structure
1273 * Initialize any function pointers that were not able to be
1274 * set during init_shared_code because the PHY/SFP type was
1275 * not known. Perform the SFP init if necessary.
1278 s32 txgbe_init_phy_raptor(struct txgbe_hw *hw)
1280 struct txgbe_mac_info *mac = &hw->mac;
1281 struct txgbe_phy_info *phy = &hw->phy;
1284 DEBUGFUNC("txgbe_init_phy_raptor");
1286 if (hw->device_id == TXGBE_DEV_ID_RAPTOR_QSFP) {
1287 /* Store flag indicating I2C bus access control unit. */
1288 hw->phy.qsfp_shared_i2c_bus = TRUE;
1290 /* Initialize access to QSFP+ I2C bus */
1294 /* Identify the PHY or SFP module */
1295 err = phy->identify(hw);
1296 if (err == TXGBE_ERR_SFP_NOT_SUPPORTED)
1297 goto init_phy_ops_out;
1299 /* Setup function pointers based on detected SFP module and speeds */
1300 txgbe_init_mac_link_ops(hw);
1302 /* If copper media, overwrite with copper function pointers */
1303 if (phy->media_type == txgbe_media_type_copper) {
1304 mac->setup_link = txgbe_setup_copper_link_raptor;
1305 mac->get_link_capabilities =
1306 txgbe_get_copper_link_capabilities;
1309 /* Set necessary function pointers based on PHY type */
1310 switch (hw->phy.type) {
1312 phy->setup_link = txgbe_setup_phy_link_tnx;
1313 phy->check_link = txgbe_check_phy_link_tnx;
1323 s32 txgbe_setup_sfp_modules(struct txgbe_hw *hw)
1327 DEBUGFUNC("txgbe_setup_sfp_modules");
1329 if (hw->phy.sfp_type == txgbe_sfp_type_unknown)
1332 txgbe_init_mac_link_ops(hw);
1334 /* PHY config will finish before releasing the semaphore */
1335 err = hw->mac.acquire_swfw_sync(hw, TXGBE_MNGSEM_SWPHY);
1337 return TXGBE_ERR_SWFW_SYNC;
1339 /* Release the semaphore */
1340 hw->mac.release_swfw_sync(hw, TXGBE_MNGSEM_SWPHY);
1342 /* Delay obtaining semaphore again to allow FW access
1343 * prot_autoc_write uses the semaphore too.
1345 msec_delay(hw->rom.semaphore_delay);
1348 DEBUGOUT("sfp module setup not complete\n");
1349 return TXGBE_ERR_SFP_SETUP_NOT_COMPLETE;
1356 * txgbe_init_ops_pf - Inits func ptrs and MAC type
1357 * @hw: pointer to hardware structure
1359 * Initialize the function pointers and assign the MAC type.
1360 * Does not touch the hardware.
1362 s32 txgbe_init_ops_pf(struct txgbe_hw *hw)
1364 struct txgbe_bus_info *bus = &hw->bus;
1365 struct txgbe_mac_info *mac = &hw->mac;
1366 struct txgbe_phy_info *phy = &hw->phy;
1367 struct txgbe_rom_info *rom = &hw->rom;
1369 DEBUGFUNC("txgbe_init_ops_pf");
1372 bus->set_lan_id = txgbe_set_lan_id_multi_port;
1375 phy->get_media_type = txgbe_get_media_type_raptor;
1376 phy->identify = txgbe_identify_phy;
1377 phy->init = txgbe_init_phy_raptor;
1378 phy->read_reg = txgbe_read_phy_reg;
1379 phy->write_reg = txgbe_write_phy_reg;
1380 phy->read_reg_mdi = txgbe_read_phy_reg_mdi;
1381 phy->write_reg_mdi = txgbe_write_phy_reg_mdi;
1382 phy->setup_link = txgbe_setup_phy_link;
1383 phy->setup_link_speed = txgbe_setup_phy_link_speed;
1384 phy->read_i2c_byte = txgbe_read_i2c_byte;
1385 phy->write_i2c_byte = txgbe_write_i2c_byte;
1386 phy->read_i2c_eeprom = txgbe_read_i2c_eeprom;
1387 phy->write_i2c_eeprom = txgbe_write_i2c_eeprom;
1388 phy->reset = txgbe_reset_phy;
1391 mac->init_hw = txgbe_init_hw;
1392 mac->start_hw = txgbe_start_hw_raptor;
1393 mac->enable_rx_dma = txgbe_enable_rx_dma_raptor;
1394 mac->get_mac_addr = txgbe_get_mac_addr;
1395 mac->stop_hw = txgbe_stop_hw;
1396 mac->reset_hw = txgbe_reset_hw;
1398 mac->disable_sec_rx_path = txgbe_disable_sec_rx_path;
1399 mac->enable_sec_rx_path = txgbe_enable_sec_rx_path;
1400 mac->disable_sec_tx_path = txgbe_disable_sec_tx_path;
1401 mac->enable_sec_tx_path = txgbe_enable_sec_tx_path;
1402 mac->get_san_mac_addr = txgbe_get_san_mac_addr;
1403 mac->set_san_mac_addr = txgbe_set_san_mac_addr;
1404 mac->get_device_caps = txgbe_get_device_caps;
1405 mac->autoc_read = txgbe_autoc_read;
1406 mac->autoc_write = txgbe_autoc_write;
1408 mac->set_rar = txgbe_set_rar;
1409 mac->clear_rar = txgbe_clear_rar;
1410 mac->init_rx_addrs = txgbe_init_rx_addrs;
1411 mac->enable_rx = txgbe_enable_rx;
1412 mac->disable_rx = txgbe_disable_rx;
1413 mac->init_uta_tables = txgbe_init_uta_tables;
1414 mac->setup_sfp = txgbe_setup_sfp_modules;
1416 mac->get_link_capabilities = txgbe_get_link_capabilities_raptor;
1417 mac->check_link = txgbe_check_mac_link;
1420 rom->init_params = txgbe_init_eeprom_params;
1421 rom->read16 = txgbe_ee_read16;
1422 rom->readw_buffer = txgbe_ee_readw_buffer;
1423 rom->readw_sw = txgbe_ee_readw_sw;
1424 rom->read32 = txgbe_ee_read32;
1425 rom->write16 = txgbe_ee_write16;
1426 rom->writew_buffer = txgbe_ee_writew_buffer;
1427 rom->writew_sw = txgbe_ee_writew_sw;
1428 rom->write32 = txgbe_ee_write32;
1429 rom->validate_checksum = txgbe_validate_eeprom_checksum;
1430 rom->update_checksum = txgbe_update_eeprom_checksum;
1431 rom->calc_checksum = txgbe_calc_eeprom_checksum;
1433 mac->mcft_size = TXGBE_RAPTOR_MC_TBL_SIZE;
1434 mac->num_rar_entries = TXGBE_RAPTOR_RAR_ENTRIES;
1435 mac->max_rx_queues = TXGBE_RAPTOR_MAX_RX_QUEUES;
1436 mac->max_tx_queues = TXGBE_RAPTOR_MAX_TX_QUEUES;
1442 * txgbe_get_link_capabilities_raptor - Determines link capabilities
1443 * @hw: pointer to hardware structure
1444 * @speed: pointer to link speed
1445 * @autoneg: true when autoneg or autotry is enabled
1447 * Determines the link capabilities by reading the AUTOC register.
1449 s32 txgbe_get_link_capabilities_raptor(struct txgbe_hw *hw,
1456 DEBUGFUNC("txgbe_get_link_capabilities_raptor");
1458 /* Check if 1G SFP module. */
1459 if (hw->phy.sfp_type == txgbe_sfp_type_1g_cu_core0 ||
1460 hw->phy.sfp_type == txgbe_sfp_type_1g_cu_core1 ||
1461 hw->phy.sfp_type == txgbe_sfp_type_1g_lx_core0 ||
1462 hw->phy.sfp_type == txgbe_sfp_type_1g_lx_core1 ||
1463 hw->phy.sfp_type == txgbe_sfp_type_1g_sx_core0 ||
1464 hw->phy.sfp_type == txgbe_sfp_type_1g_sx_core1) {
1465 *speed = TXGBE_LINK_SPEED_1GB_FULL;
1471 * Determine link capabilities based on the stored value of AUTOC,
1472 * which represents EEPROM defaults. If AUTOC value has not
1473 * been stored, use the current register values.
1475 if (hw->mac.orig_link_settings_stored)
1476 autoc = hw->mac.orig_autoc;
1478 autoc = hw->mac.autoc_read(hw);
1480 switch (autoc & TXGBE_AUTOC_LMS_MASK) {
1481 case TXGBE_AUTOC_LMS_1G_LINK_NO_AN:
1482 *speed = TXGBE_LINK_SPEED_1GB_FULL;
1486 case TXGBE_AUTOC_LMS_10G_LINK_NO_AN:
1487 *speed = TXGBE_LINK_SPEED_10GB_FULL;
1491 case TXGBE_AUTOC_LMS_1G_AN:
1492 *speed = TXGBE_LINK_SPEED_1GB_FULL;
1496 case TXGBE_AUTOC_LMS_10G:
1497 *speed = TXGBE_LINK_SPEED_10GB_FULL;
1501 case TXGBE_AUTOC_LMS_KX4_KX_KR:
1502 case TXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN:
1503 *speed = TXGBE_LINK_SPEED_UNKNOWN;
1504 if (autoc & TXGBE_AUTOC_KR_SUPP)
1505 *speed |= TXGBE_LINK_SPEED_10GB_FULL;
1506 if (autoc & TXGBE_AUTOC_KX4_SUPP)
1507 *speed |= TXGBE_LINK_SPEED_10GB_FULL;
1508 if (autoc & TXGBE_AUTOC_KX_SUPP)
1509 *speed |= TXGBE_LINK_SPEED_1GB_FULL;
1513 case TXGBE_AUTOC_LMS_KX4_KX_KR_SGMII:
1514 *speed = TXGBE_LINK_SPEED_100M_FULL;
1515 if (autoc & TXGBE_AUTOC_KR_SUPP)
1516 *speed |= TXGBE_LINK_SPEED_10GB_FULL;
1517 if (autoc & TXGBE_AUTOC_KX4_SUPP)
1518 *speed |= TXGBE_LINK_SPEED_10GB_FULL;
1519 if (autoc & TXGBE_AUTOC_KX_SUPP)
1520 *speed |= TXGBE_LINK_SPEED_1GB_FULL;
1524 case TXGBE_AUTOC_LMS_SGMII_1G_100M:
1525 *speed = TXGBE_LINK_SPEED_1GB_FULL |
1526 TXGBE_LINK_SPEED_100M_FULL |
1527 TXGBE_LINK_SPEED_10M_FULL;
1532 return TXGBE_ERR_LINK_SETUP;
1535 if (hw->phy.multispeed_fiber) {
1536 *speed |= TXGBE_LINK_SPEED_10GB_FULL |
1537 TXGBE_LINK_SPEED_1GB_FULL;
1539 /* QSFP must not enable full auto-negotiation
1540 * Limited autoneg is enabled at 1G
1542 if (hw->phy.media_type == txgbe_media_type_fiber_qsfp)
1552 * txgbe_get_media_type_raptor - Get media type
1553 * @hw: pointer to hardware structure
1555 * Returns the media type (fiber, copper, backplane)
1557 u32 txgbe_get_media_type_raptor(struct txgbe_hw *hw)
1561 DEBUGFUNC("txgbe_get_media_type_raptor");
1563 /* Detect if there is a copper PHY attached. */
1564 switch (hw->phy.type) {
1565 case txgbe_phy_cu_unknown:
1567 media_type = txgbe_media_type_copper;
1573 switch (hw->device_id) {
1574 case TXGBE_DEV_ID_RAPTOR_KR_KX_KX4:
1575 /* Default device ID is mezzanine card KX/KX4 */
1576 media_type = txgbe_media_type_backplane;
1578 case TXGBE_DEV_ID_RAPTOR_SFP:
1579 case TXGBE_DEV_ID_WX1820_SFP:
1580 media_type = txgbe_media_type_fiber;
1582 case TXGBE_DEV_ID_RAPTOR_QSFP:
1583 media_type = txgbe_media_type_fiber_qsfp;
1585 case TXGBE_DEV_ID_RAPTOR_XAUI:
1586 case TXGBE_DEV_ID_RAPTOR_SGMII:
1587 media_type = txgbe_media_type_copper;
1590 media_type = txgbe_media_type_unknown;
1598 * txgbe_start_mac_link_raptor - Setup MAC link settings
1599 * @hw: pointer to hardware structure
1600 * @autoneg_wait_to_complete: true when waiting for completion is needed
1602 * Configures link settings based on values in the txgbe_hw struct.
1603 * Restarts the link. Performs autonegotiation if needed.
1605 s32 txgbe_start_mac_link_raptor(struct txgbe_hw *hw,
1606 bool autoneg_wait_to_complete)
1609 bool got_lock = false;
1611 DEBUGFUNC("txgbe_start_mac_link_raptor");
1613 UNREFERENCED_PARAMETER(autoneg_wait_to_complete);
1615 /* reset_pipeline requires us to hold this lock as it writes to
1618 if (txgbe_verify_lesm_fw_enabled_raptor(hw)) {
1619 status = hw->mac.acquire_swfw_sync(hw, TXGBE_MNGSEM_SWPHY);
1627 txgbe_reset_pipeline_raptor(hw);
1630 hw->mac.release_swfw_sync(hw, TXGBE_MNGSEM_SWPHY);
1632 /* Add delay to filter out noises during initial link setup */
1640 * txgbe_disable_tx_laser_multispeed_fiber - Disable Tx laser
1641 * @hw: pointer to hardware structure
1643 * The base drivers may require better control over SFP+ module
1644 * PHY states. This includes selectively shutting down the Tx
1645 * laser on the PHY, effectively halting physical link.
1647 void txgbe_disable_tx_laser_multispeed_fiber(struct txgbe_hw *hw)
1649 u32 esdp_reg = rd32(hw, TXGBE_GPIODATA);
1651 /* Blocked by MNG FW so bail */
1652 if (txgbe_check_reset_blocked(hw))
1655 /* Disable Tx laser; allow 100us to go dark per spec */
1656 esdp_reg |= (TXGBE_GPIOBIT_0 | TXGBE_GPIOBIT_1);
1657 wr32(hw, TXGBE_GPIODATA, esdp_reg);
1663 * txgbe_enable_tx_laser_multispeed_fiber - Enable Tx laser
1664 * @hw: pointer to hardware structure
1666 * The base drivers may require better control over SFP+ module
1667 * PHY states. This includes selectively turning on the Tx
1668 * laser on the PHY, effectively starting physical link.
1670 void txgbe_enable_tx_laser_multispeed_fiber(struct txgbe_hw *hw)
1672 u32 esdp_reg = rd32(hw, TXGBE_GPIODATA);
1674 /* Enable Tx laser; allow 100ms to light up */
1675 esdp_reg &= ~(TXGBE_GPIOBIT_0 | TXGBE_GPIOBIT_1);
1676 wr32(hw, TXGBE_GPIODATA, esdp_reg);
1682 * txgbe_flap_tx_laser_multispeed_fiber - Flap Tx laser
1683 * @hw: pointer to hardware structure
1685 * When the driver changes the link speeds that it can support,
1686 * it sets autotry_restart to true to indicate that we need to
1687 * initiate a new autotry session with the link partner. To do
1688 * so, we set the speed then disable and re-enable the Tx laser, to
1689 * alert the link partner that it also needs to restart autotry on its
1690 * end. This is consistent with true clause 37 autoneg, which also
1691 * involves a loss of signal.
1693 void txgbe_flap_tx_laser_multispeed_fiber(struct txgbe_hw *hw)
1695 DEBUGFUNC("txgbe_flap_tx_laser_multispeed_fiber");
1697 /* Blocked by MNG FW so bail */
1698 if (txgbe_check_reset_blocked(hw))
1701 if (hw->mac.autotry_restart) {
1702 txgbe_disable_tx_laser_multispeed_fiber(hw);
1703 txgbe_enable_tx_laser_multispeed_fiber(hw);
1704 hw->mac.autotry_restart = false;
1709 * txgbe_set_hard_rate_select_speed - Set module link speed
1710 * @hw: pointer to hardware structure
1711 * @speed: link speed to set
1713 * Set module link speed via RS0/RS1 rate select pins.
1715 void txgbe_set_hard_rate_select_speed(struct txgbe_hw *hw,
1718 u32 esdp_reg = rd32(hw, TXGBE_GPIODATA);
1721 case TXGBE_LINK_SPEED_10GB_FULL:
1722 esdp_reg |= (TXGBE_GPIOBIT_4 | TXGBE_GPIOBIT_5);
1724 case TXGBE_LINK_SPEED_1GB_FULL:
1725 esdp_reg &= ~(TXGBE_GPIOBIT_4 | TXGBE_GPIOBIT_5);
1728 DEBUGOUT("Invalid fixed module speed\n");
1732 wr32(hw, TXGBE_GPIODATA, esdp_reg);
1737 * txgbe_setup_mac_link_smartspeed - Set MAC link speed using SmartSpeed
1738 * @hw: pointer to hardware structure
1739 * @speed: new link speed
1740 * @autoneg_wait_to_complete: true when waiting for completion is needed
1742 * Implements the Intel SmartSpeed algorithm.
1744 s32 txgbe_setup_mac_link_smartspeed(struct txgbe_hw *hw,
1746 bool autoneg_wait_to_complete)
1749 u32 link_speed = TXGBE_LINK_SPEED_UNKNOWN;
1751 bool link_up = false;
1752 u32 autoc_reg = rd32_epcs(hw, SR_AN_MMD_ADV_REG1);
1754 DEBUGFUNC("txgbe_setup_mac_link_smartspeed");
1756 /* Set autoneg_advertised value based on input link speed */
1757 hw->phy.autoneg_advertised = 0;
1759 if (speed & TXGBE_LINK_SPEED_10GB_FULL)
1760 hw->phy.autoneg_advertised |= TXGBE_LINK_SPEED_10GB_FULL;
1762 if (speed & TXGBE_LINK_SPEED_1GB_FULL)
1763 hw->phy.autoneg_advertised |= TXGBE_LINK_SPEED_1GB_FULL;
1765 if (speed & TXGBE_LINK_SPEED_100M_FULL)
1766 hw->phy.autoneg_advertised |= TXGBE_LINK_SPEED_100M_FULL;
1769 * Implement Intel SmartSpeed algorithm. SmartSpeed will reduce the
1770 * autoneg advertisement if link is unable to be established at the
1771 * highest negotiated rate. This can sometimes happen due to integrity
1772 * issues with the physical media connection.
1775 /* First, try to get link with full advertisement */
1776 hw->phy.smart_speed_active = false;
1777 for (j = 0; j < TXGBE_SMARTSPEED_MAX_RETRIES; j++) {
1778 status = txgbe_setup_mac_link(hw, speed,
1779 autoneg_wait_to_complete);
1784 * Wait for the controller to acquire link. Per IEEE 802.3ap,
1785 * Section 73.10.2, we may have to wait up to 500ms if KR is
1786 * attempted, or 200ms if KX/KX4/BX/BX4 is attempted, per
1787 * Table 9 in the AN MAS.
1789 for (i = 0; i < 5; i++) {
1792 /* If we have link, just jump out */
1793 status = hw->mac.check_link(hw, &link_speed, &link_up,
1804 * We didn't get link. If we advertised KR plus one of KX4/KX
1805 * (or BX4/BX), then disable KR and try again.
1807 if (((autoc_reg & TXGBE_AUTOC_KR_SUPP) == 0) ||
1808 ((autoc_reg & TXGBE_AUTOC_KX_SUPP) == 0 &&
1809 (autoc_reg & TXGBE_AUTOC_KX4_SUPP) == 0))
1812 /* Turn SmartSpeed on to disable KR support */
1813 hw->phy.smart_speed_active = true;
1814 status = txgbe_setup_mac_link(hw, speed,
1815 autoneg_wait_to_complete);
1820 * Wait for the controller to acquire link. 600ms will allow for
1821 * the AN link_fail_inhibit_timer as well for multiple cycles of
1822 * parallel detect, both 10g and 1g. This allows for the maximum
1823 * connect attempts as defined in the AN MAS table 73-7.
1825 for (i = 0; i < 6; i++) {
1828 /* If we have link, just jump out */
1829 status = hw->mac.check_link(hw, &link_speed, &link_up, false);
1837 /* We didn't get link. Turn SmartSpeed back off. */
1838 hw->phy.smart_speed_active = false;
1839 status = txgbe_setup_mac_link(hw, speed,
1840 autoneg_wait_to_complete);
1843 if (link_up && link_speed == TXGBE_LINK_SPEED_1GB_FULL)
1844 DEBUGOUT("Smartspeed has downgraded the link speed "
1845 "from the maximum advertised\n");
1850 * txgbe_setup_mac_link - Set MAC link speed
1851 * @hw: pointer to hardware structure
1852 * @speed: new link speed
1853 * @autoneg_wait_to_complete: true when waiting for completion is needed
1855 * Set the link speed in the AUTOC register and restarts link.
1857 s32 txgbe_setup_mac_link(struct txgbe_hw *hw,
1859 bool autoneg_wait_to_complete)
1861 bool autoneg = false;
1864 u64 autoc = hw->mac.autoc_read(hw);
1865 u64 pma_pmd_10gs = autoc & TXGBE_AUTOC_10GS_PMA_PMD_MASK;
1866 u64 pma_pmd_1g = autoc & TXGBE_AUTOC_1G_PMA_PMD_MASK;
1867 u64 link_mode = autoc & TXGBE_AUTOC_LMS_MASK;
1868 u64 current_autoc = autoc;
1872 u32 link_capabilities = TXGBE_LINK_SPEED_UNKNOWN;
1874 DEBUGFUNC("txgbe_setup_mac_link");
1876 /* Check to see if speed passed in is supported. */
1877 status = hw->mac.get_link_capabilities(hw,
1878 &link_capabilities, &autoneg);
1882 speed &= link_capabilities;
1883 if (speed == TXGBE_LINK_SPEED_UNKNOWN)
1884 return TXGBE_ERR_LINK_SETUP;
1886 /* Use stored value (EEPROM defaults) of AUTOC to find KR/KX4 support*/
1887 if (hw->mac.orig_link_settings_stored)
1888 orig_autoc = hw->mac.orig_autoc;
1892 link_mode = autoc & TXGBE_AUTOC_LMS_MASK;
1893 pma_pmd_1g = autoc & TXGBE_AUTOC_1G_PMA_PMD_MASK;
1895 if (link_mode == TXGBE_AUTOC_LMS_KX4_KX_KR ||
1896 link_mode == TXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
1897 link_mode == TXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
1898 /* Set KX4/KX/KR support according to speed requested */
1899 autoc &= ~(TXGBE_AUTOC_KX_SUPP |
1900 TXGBE_AUTOC_KX4_SUPP |
1901 TXGBE_AUTOC_KR_SUPP);
1902 if (speed & TXGBE_LINK_SPEED_10GB_FULL) {
1903 if (orig_autoc & TXGBE_AUTOC_KX4_SUPP)
1904 autoc |= TXGBE_AUTOC_KX4_SUPP;
1905 if ((orig_autoc & TXGBE_AUTOC_KR_SUPP) &&
1906 !hw->phy.smart_speed_active)
1907 autoc |= TXGBE_AUTOC_KR_SUPP;
1909 if (speed & TXGBE_LINK_SPEED_1GB_FULL)
1910 autoc |= TXGBE_AUTOC_KX_SUPP;
1911 } else if ((pma_pmd_1g == TXGBE_AUTOC_1G_SFI) &&
1912 (link_mode == TXGBE_AUTOC_LMS_1G_LINK_NO_AN ||
1913 link_mode == TXGBE_AUTOC_LMS_1G_AN)) {
1914 /* Switch from 1G SFI to 10G SFI if requested */
1915 if (speed == TXGBE_LINK_SPEED_10GB_FULL &&
1916 pma_pmd_10gs == TXGBE_AUTOC_10GS_SFI) {
1917 autoc &= ~TXGBE_AUTOC_LMS_MASK;
1918 autoc |= TXGBE_AUTOC_LMS_10G;
1920 } else if ((pma_pmd_10gs == TXGBE_AUTOC_10GS_SFI) &&
1921 (link_mode == TXGBE_AUTOC_LMS_10G)) {
1922 /* Switch from 10G SFI to 1G SFI if requested */
1923 if (speed == TXGBE_LINK_SPEED_1GB_FULL &&
1924 pma_pmd_1g == TXGBE_AUTOC_1G_SFI) {
1925 autoc &= ~TXGBE_AUTOC_LMS_MASK;
1926 if (autoneg || hw->phy.type == txgbe_phy_qsfp_intel)
1927 autoc |= TXGBE_AUTOC_LMS_1G_AN;
1929 autoc |= TXGBE_AUTOC_LMS_1G_LINK_NO_AN;
1933 if (autoc == current_autoc)
1936 autoc &= ~TXGBE_AUTOC_SPEED_MASK;
1937 autoc |= TXGBE_AUTOC_SPEED(speed);
1938 autoc |= (autoneg ? TXGBE_AUTOC_AUTONEG : 0);
1941 hw->mac.autoc_write(hw, autoc);
1943 /* Only poll for autoneg to complete if specified to do so */
1944 if (autoneg_wait_to_complete) {
1945 if (link_mode == TXGBE_AUTOC_LMS_KX4_KX_KR ||
1946 link_mode == TXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
1947 link_mode == TXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
1948 links_reg = 0; /*Just in case Autoneg time=0*/
1949 for (i = 0; i < TXGBE_AUTO_NEG_TIME; i++) {
1950 links_reg = rd32(hw, TXGBE_PORTSTAT);
1951 if (links_reg & TXGBE_PORTSTAT_UP)
1955 if (!(links_reg & TXGBE_PORTSTAT_UP)) {
1956 status = TXGBE_ERR_AUTONEG_NOT_COMPLETE;
1957 DEBUGOUT("Autoneg did not complete.\n");
1962 /* Add delay to filter out noises during initial link setup */
1969 * txgbe_setup_copper_link_raptor - Set the PHY autoneg advertised field
1970 * @hw: pointer to hardware structure
1971 * @speed: new link speed
1972 * @autoneg_wait_to_complete: true if waiting is needed to complete
1974 * Restarts link on PHY and MAC based on settings passed in.
1976 static s32 txgbe_setup_copper_link_raptor(struct txgbe_hw *hw,
1978 bool autoneg_wait_to_complete)
1982 DEBUGFUNC("txgbe_setup_copper_link_raptor");
1984 /* Setup the PHY according to input speed */
1985 status = hw->phy.setup_link_speed(hw, speed,
1986 autoneg_wait_to_complete);
1988 txgbe_start_mac_link_raptor(hw, autoneg_wait_to_complete);
1994 txgbe_check_flash_load(struct txgbe_hw *hw, u32 check_bit)
1999 /* if there's flash existing */
2000 if (!(rd32(hw, TXGBE_SPISTAT) & TXGBE_SPISTAT_BPFLASH)) {
2001 /* wait hw load flash done */
2002 for (i = 0; i < 10; i++) {
2003 reg = rd32(hw, TXGBE_ILDRSTAT);
2004 if (!(reg & check_bit)) {
2011 err = TXGBE_ERR_FLASH_LOADING_FAILED;
2017 txgbe_reset_misc(struct txgbe_hw *hw)
2022 wr32(hw, TXGBE_ISBADDRL, hw->isb_dma & 0x00000000FFFFFFFF);
2023 wr32(hw, TXGBE_ISBADDRH, hw->isb_dma >> 32);
2025 value = rd32_epcs(hw, SR_XS_PCS_CTRL2);
2026 if ((value & 0x3) != SR_PCS_CTRL2_TYPE_SEL_X)
2027 hw->link_status = TXGBE_LINK_STATUS_NONE;
2029 /* receive packets that size > 2048 */
2030 wr32m(hw, TXGBE_MACRXCFG,
2031 TXGBE_MACRXCFG_JUMBO, TXGBE_MACRXCFG_JUMBO);
2033 wr32m(hw, TXGBE_FRMSZ, TXGBE_FRMSZ_MAX_MASK,
2034 TXGBE_FRMSZ_MAX(TXGBE_FRAME_SIZE_DFT));
2036 /* clear counters on read */
2037 wr32m(hw, TXGBE_MACCNTCTL,
2038 TXGBE_MACCNTCTL_RC, TXGBE_MACCNTCTL_RC);
2040 wr32m(hw, TXGBE_RXFCCFG,
2041 TXGBE_RXFCCFG_FC, TXGBE_RXFCCFG_FC);
2042 wr32m(hw, TXGBE_TXFCCFG,
2043 TXGBE_TXFCCFG_FC, TXGBE_TXFCCFG_FC);
2045 wr32m(hw, TXGBE_MACRXFLT,
2046 TXGBE_MACRXFLT_PROMISC, TXGBE_MACRXFLT_PROMISC);
2048 wr32m(hw, TXGBE_RSTSTAT,
2049 TXGBE_RSTSTAT_TMRINIT_MASK, TXGBE_RSTSTAT_TMRINIT(30));
2051 /* errata 4: initialize mng flex tbl and wakeup flex tbl*/
2052 wr32(hw, TXGBE_MNGFLEXSEL, 0);
2053 for (i = 0; i < 16; i++) {
2054 wr32(hw, TXGBE_MNGFLEXDWL(i), 0);
2055 wr32(hw, TXGBE_MNGFLEXDWH(i), 0);
2056 wr32(hw, TXGBE_MNGFLEXMSK(i), 0);
2058 wr32(hw, TXGBE_LANFLEXSEL, 0);
2059 for (i = 0; i < 16; i++) {
2060 wr32(hw, TXGBE_LANFLEXDWL(i), 0);
2061 wr32(hw, TXGBE_LANFLEXDWH(i), 0);
2062 wr32(hw, TXGBE_LANFLEXMSK(i), 0);
2065 /* set pause frame dst mac addr */
2066 wr32(hw, TXGBE_RXPBPFCDMACL, 0xC2000001);
2067 wr32(hw, TXGBE_RXPBPFCDMACH, 0x0180);
2069 hw->mac.init_thermal_sensor_thresh(hw);
2071 /* enable mac transmitter */
2072 wr32m(hw, TXGBE_MACTXCFG, TXGBE_MACTXCFG_TXE, TXGBE_MACTXCFG_TXE);
2074 for (i = 0; i < 4; i++)
2075 wr32m(hw, TXGBE_IVAR(i), 0x80808080, 0);
2079 * txgbe_reset_hw - Perform hardware reset
2080 * @hw: pointer to hardware structure
2082 * Resets the hardware by resetting the transmit and receive units, masks
2083 * and clears all interrupts, perform a PHY reset, and perform a link (MAC)
2086 s32 txgbe_reset_hw(struct txgbe_hw *hw)
2091 DEBUGFUNC("txgbe_reset_hw");
2093 /* Call adapter stop to disable tx/rx and clear interrupts */
2094 status = hw->mac.stop_hw(hw);
2098 /* flush pending Tx transactions */
2099 txgbe_clear_tx_pending(hw);
2101 /* Identify PHY and related function pointers */
2102 status = hw->phy.init(hw);
2103 if (status == TXGBE_ERR_SFP_NOT_SUPPORTED)
2106 /* Setup SFP module if there is one present. */
2107 if (hw->phy.sfp_setup_needed) {
2108 status = hw->mac.setup_sfp(hw);
2109 hw->phy.sfp_setup_needed = false;
2111 if (status == TXGBE_ERR_SFP_NOT_SUPPORTED)
2115 if (!hw->phy.reset_disable)
2118 /* remember AUTOC from before we reset */
2119 autoc = hw->mac.autoc_read(hw);
2123 * Issue global reset to the MAC. Needs to be SW reset if link is up.
2124 * If link reset is used when link is up, it might reset the PHY when
2125 * mng is using it. If link is down or the flag to force full link
2126 * reset is set, then perform link reset.
2128 if (txgbe_mng_present(hw)) {
2129 txgbe_hic_reset(hw);
2131 wr32(hw, TXGBE_RST, TXGBE_RST_LAN(hw->bus.lan_id));
2136 txgbe_reset_misc(hw);
2138 if (hw->bus.lan_id == 0) {
2139 status = txgbe_check_flash_load(hw,
2140 TXGBE_ILDRSTAT_SWRST_LAN0);
2142 status = txgbe_check_flash_load(hw,
2143 TXGBE_ILDRSTAT_SWRST_LAN1);
2151 * Double resets are required for recovery from certain error
2152 * conditions. Between resets, it is necessary to stall to
2153 * allow time for any pending HW events to complete.
2155 if (hw->mac.flags & TXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
2156 hw->mac.flags &= ~TXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
2161 * Store the original AUTOC/AUTOC2 values if they have not been
2162 * stored off yet. Otherwise restore the stored original
2163 * values since the reset operation sets back to defaults.
2165 if (!hw->mac.orig_link_settings_stored) {
2166 hw->mac.orig_autoc = hw->mac.autoc_read(hw);
2167 hw->mac.autoc_write(hw, hw->mac.orig_autoc);
2168 hw->mac.orig_link_settings_stored = true;
2170 hw->mac.orig_autoc = autoc;
2173 /* Store the permanent mac address */
2174 hw->mac.get_mac_addr(hw, hw->mac.perm_addr);
2177 * Store MAC address from RAR0, clear receive address registers, and
2178 * clear the multicast table. Also reset num_rar_entries to 128,
2179 * since we modify this value when programming the SAN MAC address.
2181 hw->mac.num_rar_entries = 128;
2182 hw->mac.init_rx_addrs(hw);
2184 /* Store the permanent SAN mac address */
2185 hw->mac.get_san_mac_addr(hw, hw->mac.san_addr);
2187 /* Add the SAN MAC address to the RAR only if it's a valid address */
2188 if (txgbe_validate_mac_addr(hw->mac.san_addr) == 0) {
2189 /* Save the SAN MAC RAR index */
2190 hw->mac.san_mac_rar_index = hw->mac.num_rar_entries - 1;
2192 hw->mac.set_rar(hw, hw->mac.san_mac_rar_index,
2193 hw->mac.san_addr, 0, true);
2195 /* clear VMDq pool/queue selection for this RAR */
2196 hw->mac.clear_vmdq(hw, hw->mac.san_mac_rar_index,
2199 /* Reserve the last RAR for the SAN MAC address */
2200 hw->mac.num_rar_entries--;
2203 /* Store the alternative WWNN/WWPN prefix */
2204 hw->mac.get_wwn_prefix(hw, &hw->mac.wwnn_prefix,
2205 &hw->mac.wwpn_prefix);
2211 * txgbe_start_hw_raptor - Prepare hardware for Tx/Rx
2212 * @hw: pointer to hardware structure
2214 * Starts the hardware using the generic start_hw function
2215 * and the generation start_hw function.
2216 * Then performs revision-specific operations, if any.
2218 s32 txgbe_start_hw_raptor(struct txgbe_hw *hw)
2222 DEBUGFUNC("txgbe_start_hw_raptor");
2224 err = txgbe_start_hw(hw);
2228 err = txgbe_start_hw_gen2(hw);
2232 /* We need to run link autotry after the driver loads */
2233 hw->mac.autotry_restart = true;
2240 * txgbe_enable_rx_dma_raptor - Enable the Rx DMA unit
2241 * @hw: pointer to hardware structure
2242 * @regval: register value to write to RXCTRL
2244 * Enables the Rx DMA unit
2246 s32 txgbe_enable_rx_dma_raptor(struct txgbe_hw *hw, u32 regval)
2248 DEBUGFUNC("txgbe_enable_rx_dma_raptor");
2251 * Workaround silicon errata when enabling the Rx datapath.
2252 * If traffic is incoming before we enable the Rx unit, it could hang
2253 * the Rx DMA unit. Therefore, make sure the security engine is
2254 * completely disabled prior to enabling the Rx unit.
2257 hw->mac.disable_sec_rx_path(hw);
2259 if (regval & TXGBE_PBRXCTL_ENA)
2260 txgbe_enable_rx(hw);
2262 txgbe_disable_rx(hw);
2264 hw->mac.enable_sec_rx_path(hw);
2270 * txgbe_verify_lesm_fw_enabled_raptor - Checks LESM FW module state.
2271 * @hw: pointer to hardware structure
2273 * Returns true if the LESM FW module is present and enabled. Otherwise
2274 * returns false. Smart Speed must be disabled if LESM FW module is enabled.
2276 bool txgbe_verify_lesm_fw_enabled_raptor(struct txgbe_hw *hw)
2278 bool lesm_enabled = false;
2279 u16 fw_offset, fw_lesm_param_offset, fw_lesm_state;
2282 DEBUGFUNC("txgbe_verify_lesm_fw_enabled_raptor");
2284 /* get the offset to the Firmware Module block */
2285 status = hw->rom.read16(hw, TXGBE_FW_PTR, &fw_offset);
2287 if (status != 0 || fw_offset == 0 || fw_offset == 0xFFFF)
2290 /* get the offset to the LESM Parameters block */
2291 status = hw->rom.read16(hw, (fw_offset +
2292 TXGBE_FW_LESM_PARAMETERS_PTR),
2293 &fw_lesm_param_offset);
2296 fw_lesm_param_offset == 0 || fw_lesm_param_offset == 0xFFFF)
2299 /* get the LESM state word */
2300 status = hw->rom.read16(hw, (fw_lesm_param_offset +
2301 TXGBE_FW_LESM_STATE_1),
2304 if (status == 0 && (fw_lesm_state & TXGBE_FW_LESM_STATE_ENABLED))
2305 lesm_enabled = true;
2308 lesm_enabled = false;
2309 return lesm_enabled;
2313 * txgbe_reset_pipeline_raptor - perform pipeline reset
2315 * @hw: pointer to hardware structure
2317 * Reset pipeline by asserting Restart_AN together with LMS change to ensure
2318 * full pipeline reset. This function assumes the SW/FW lock is held.
2320 s32 txgbe_reset_pipeline_raptor(struct txgbe_hw *hw)
2325 autoc = hw->mac.autoc_read(hw);
2327 /* Enable link if disabled in NVM */
2328 if (autoc & TXGBE_AUTOC_LINK_DIA_MASK)
2329 autoc &= ~TXGBE_AUTOC_LINK_DIA_MASK;
2331 autoc |= TXGBE_AUTOC_AN_RESTART;
2332 /* Write AUTOC register with toggled LMS[2] bit and Restart_AN */
2333 hw->mac.autoc_write(hw, autoc ^ TXGBE_AUTOC_LMS_AN);
2335 /* Write AUTOC register with original LMS field and Restart_AN */
2336 hw->mac.autoc_write(hw, autoc);