1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2015-2020
5 #include "txgbe_type.h"
7 #include "txgbe_eeprom.h"
11 #define TXGBE_RAPTOR_MAX_TX_QUEUES 128
12 #define TXGBE_RAPTOR_MAX_RX_QUEUES 128
13 #define TXGBE_RAPTOR_RAR_ENTRIES 128
14 #define TXGBE_RAPTOR_MC_TBL_SIZE 128
16 static s32 txgbe_setup_copper_link_raptor(struct txgbe_hw *hw,
18 bool autoneg_wait_to_complete);
20 static s32 txgbe_mta_vector(struct txgbe_hw *hw, u8 *mc_addr);
21 static s32 txgbe_get_san_mac_addr_offset(struct txgbe_hw *hw,
25 * txgbe_init_hw - Generic hardware initialization
26 * @hw: pointer to hardware structure
28 * Initialize the hardware by resetting the hardware, filling the bus info
29 * structure and media type, clears all on chip counters, initializes receive
30 * address registers, multicast table, VLAN filter table, calls routine to set
31 * up link and flow control settings, and leaves transmit and receive units
32 * disabled and uninitialized
34 s32 txgbe_init_hw(struct txgbe_hw *hw)
38 DEBUGFUNC("txgbe_init_hw");
40 /* Reset the hardware */
41 status = hw->mac.reset_hw(hw);
42 if (status == 0 || status == TXGBE_ERR_SFP_NOT_PRESENT) {
44 status = hw->mac.start_hw(hw);
48 DEBUGOUT("Failed to initialize HW, STATUS = %d\n", status);
54 * txgbe_get_mac_addr - Generic get MAC address
55 * @hw: pointer to hardware structure
56 * @mac_addr: Adapter MAC address
58 * Reads the adapter's MAC address from first Receive Address Register (RAR0)
59 * A reset of the adapter must be performed prior to calling this function
60 * in order for the MAC address to have been loaded from the EEPROM into RAR0
62 s32 txgbe_get_mac_addr(struct txgbe_hw *hw, u8 *mac_addr)
68 DEBUGFUNC("txgbe_get_mac_addr");
70 wr32(hw, TXGBE_ETHADDRIDX, 0);
71 rar_high = rd32(hw, TXGBE_ETHADDRH);
72 rar_low = rd32(hw, TXGBE_ETHADDRL);
74 for (i = 0; i < 2; i++)
75 mac_addr[i] = (u8)(rar_high >> (1 - i) * 8);
77 for (i = 0; i < 4; i++)
78 mac_addr[i + 2] = (u8)(rar_low >> (3 - i) * 8);
84 * txgbe_set_lan_id_multi_port - Set LAN id for PCIe multiple port devices
85 * @hw: pointer to the HW structure
87 * Determines the LAN function id by reading memory-mapped registers and swaps
88 * the port value if requested, and set MAC instance for devices.
90 void txgbe_set_lan_id_multi_port(struct txgbe_hw *hw)
92 struct txgbe_bus_info *bus = &hw->bus;
95 DEBUGFUNC("txgbe_set_lan_id_multi_port_pcie");
97 reg = rd32(hw, TXGBE_PORTSTAT);
98 bus->lan_id = TXGBE_PORTSTAT_ID(reg);
100 /* check for single port */
101 reg = rd32(hw, TXGBE_PWR);
102 if (TXGBE_PWR_LANID(reg) == TXGBE_PWR_LANID_SWAP)
105 bus->func = bus->lan_id;
109 * txgbe_validate_mac_addr - Validate MAC address
110 * @mac_addr: pointer to MAC address.
112 * Tests a MAC address to ensure it is a valid Individual Address.
114 s32 txgbe_validate_mac_addr(u8 *mac_addr)
118 DEBUGFUNC("txgbe_validate_mac_addr");
120 /* Make sure it is not a multicast address */
121 if (TXGBE_IS_MULTICAST(mac_addr)) {
122 status = TXGBE_ERR_INVALID_MAC_ADDR;
123 /* Not a broadcast address */
124 } else if (TXGBE_IS_BROADCAST(mac_addr)) {
125 status = TXGBE_ERR_INVALID_MAC_ADDR;
126 /* Reject the zero address */
127 } else if (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 &&
128 mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0) {
129 status = TXGBE_ERR_INVALID_MAC_ADDR;
135 * txgbe_set_rar - Set Rx address register
136 * @hw: pointer to hardware structure
137 * @index: Receive address register to write
138 * @addr: Address to put into receive address register
139 * @vmdq: VMDq "set" or "pool" index
140 * @enable_addr: set flag that address is active
142 * Puts an ethernet address into a receive address register.
144 s32 txgbe_set_rar(struct txgbe_hw *hw, u32 index, u8 *addr, u32 vmdq,
147 u32 rar_low, rar_high;
148 u32 rar_entries = hw->mac.num_rar_entries;
150 DEBUGFUNC("txgbe_set_rar");
152 /* Make sure we are using a valid rar index range */
153 if (index >= rar_entries) {
154 DEBUGOUT("RAR index %d is out of range.\n", index);
155 return TXGBE_ERR_INVALID_ARGUMENT;
158 /* setup VMDq pool selection before this RAR gets enabled */
159 hw->mac.set_vmdq(hw, index, vmdq);
162 * HW expects these in little endian so we reverse the byte
163 * order from network order (big endian) to little endian
165 rar_low = TXGBE_ETHADDRL_AD0(addr[5]) |
166 TXGBE_ETHADDRL_AD1(addr[4]) |
167 TXGBE_ETHADDRL_AD2(addr[3]) |
168 TXGBE_ETHADDRL_AD3(addr[2]);
170 * Some parts put the VMDq setting in the extra RAH bits,
171 * so save everything except the lower 16 bits that hold part
172 * of the address and the address valid bit.
174 rar_high = rd32(hw, TXGBE_ETHADDRH);
175 rar_high &= ~TXGBE_ETHADDRH_AD_MASK;
176 rar_high |= (TXGBE_ETHADDRH_AD4(addr[1]) |
177 TXGBE_ETHADDRH_AD5(addr[0]));
179 rar_high &= ~TXGBE_ETHADDRH_VLD;
180 if (enable_addr != 0)
181 rar_high |= TXGBE_ETHADDRH_VLD;
183 wr32(hw, TXGBE_ETHADDRIDX, index);
184 wr32(hw, TXGBE_ETHADDRL, rar_low);
185 wr32(hw, TXGBE_ETHADDRH, rar_high);
191 * txgbe_clear_rar - Remove Rx address register
192 * @hw: pointer to hardware structure
193 * @index: Receive address register to write
195 * Clears an ethernet address from a receive address register.
197 s32 txgbe_clear_rar(struct txgbe_hw *hw, u32 index)
200 u32 rar_entries = hw->mac.num_rar_entries;
202 DEBUGFUNC("txgbe_clear_rar");
204 /* Make sure we are using a valid rar index range */
205 if (index >= rar_entries) {
206 DEBUGOUT("RAR index %d is out of range.\n", index);
207 return TXGBE_ERR_INVALID_ARGUMENT;
211 * Some parts put the VMDq setting in the extra RAH bits,
212 * so save everything except the lower 16 bits that hold part
213 * of the address and the address valid bit.
215 wr32(hw, TXGBE_ETHADDRIDX, index);
216 rar_high = rd32(hw, TXGBE_ETHADDRH);
217 rar_high &= ~(TXGBE_ETHADDRH_AD_MASK | TXGBE_ETHADDRH_VLD);
219 wr32(hw, TXGBE_ETHADDRL, 0);
220 wr32(hw, TXGBE_ETHADDRH, rar_high);
222 /* clear VMDq pool/queue selection for this RAR */
223 hw->mac.clear_vmdq(hw, index, BIT_MASK32);
229 * txgbe_init_rx_addrs - Initializes receive address filters.
230 * @hw: pointer to hardware structure
232 * Places the MAC address in receive address register 0 and clears the rest
233 * of the receive address registers. Clears the multicast table. Assumes
234 * the receiver is in reset when the routine is called.
236 s32 txgbe_init_rx_addrs(struct txgbe_hw *hw)
240 u32 rar_entries = hw->mac.num_rar_entries;
242 DEBUGFUNC("txgbe_init_rx_addrs");
245 * If the current mac address is valid, assume it is a software override
246 * to the permanent address.
247 * Otherwise, use the permanent address from the eeprom.
249 if (txgbe_validate_mac_addr(hw->mac.addr) ==
250 TXGBE_ERR_INVALID_MAC_ADDR) {
251 /* Get the MAC address from the RAR0 for later reference */
252 hw->mac.get_mac_addr(hw, hw->mac.addr);
254 DEBUGOUT(" Keeping Current RAR0 Addr =%.2X %.2X %.2X ",
255 hw->mac.addr[0], hw->mac.addr[1],
257 DEBUGOUT("%.2X %.2X %.2X\n", hw->mac.addr[3],
258 hw->mac.addr[4], hw->mac.addr[5]);
260 /* Setup the receive address. */
261 DEBUGOUT("Overriding MAC Address in RAR[0]\n");
262 DEBUGOUT(" New MAC Addr =%.2X %.2X %.2X ",
263 hw->mac.addr[0], hw->mac.addr[1],
265 DEBUGOUT("%.2X %.2X %.2X\n", hw->mac.addr[3],
266 hw->mac.addr[4], hw->mac.addr[5]);
268 hw->mac.set_rar(hw, 0, hw->mac.addr, 0, true);
271 /* clear VMDq pool/queue selection for RAR 0 */
272 hw->mac.clear_vmdq(hw, 0, BIT_MASK32);
274 hw->addr_ctrl.overflow_promisc = 0;
276 hw->addr_ctrl.rar_used_count = 1;
278 /* Zero out the other receive addresses. */
279 DEBUGOUT("Clearing RAR[1-%d]\n", rar_entries - 1);
280 for (i = 1; i < rar_entries; i++) {
281 wr32(hw, TXGBE_ETHADDRIDX, i);
282 wr32(hw, TXGBE_ETHADDRL, 0);
283 wr32(hw, TXGBE_ETHADDRH, 0);
287 hw->addr_ctrl.mta_in_use = 0;
288 psrctl = rd32(hw, TXGBE_PSRCTL);
289 psrctl &= ~(TXGBE_PSRCTL_ADHF12_MASK | TXGBE_PSRCTL_MCHFENA);
290 psrctl |= TXGBE_PSRCTL_ADHF12(hw->mac.mc_filter_type);
291 wr32(hw, TXGBE_PSRCTL, psrctl);
293 DEBUGOUT(" Clearing MTA\n");
294 for (i = 0; i < hw->mac.mcft_size; i++)
295 wr32(hw, TXGBE_MCADDRTBL(i), 0);
297 txgbe_init_uta_tables(hw);
303 * txgbe_mta_vector - Determines bit-vector in multicast table to set
304 * @hw: pointer to hardware structure
305 * @mc_addr: the multicast address
307 * Extracts the 12 bits, from a multicast address, to determine which
308 * bit-vector to set in the multicast table. The hardware uses 12 bits, from
309 * incoming rx multicast addresses, to determine the bit-vector to check in
310 * the MTA. Which of the 4 combination, of 12-bits, the hardware uses is set
311 * by the MO field of the PSRCTRL. The MO field is set during initialization
314 static s32 txgbe_mta_vector(struct txgbe_hw *hw, u8 *mc_addr)
318 DEBUGFUNC("txgbe_mta_vector");
320 switch (hw->mac.mc_filter_type) {
321 case 0: /* use bits [47:36] of the address */
322 vector = ((mc_addr[4] >> 4) | (((u16)mc_addr[5]) << 4));
324 case 1: /* use bits [46:35] of the address */
325 vector = ((mc_addr[4] >> 3) | (((u16)mc_addr[5]) << 5));
327 case 2: /* use bits [45:34] of the address */
328 vector = ((mc_addr[4] >> 2) | (((u16)mc_addr[5]) << 6));
330 case 3: /* use bits [43:32] of the address */
331 vector = ((mc_addr[4]) | (((u16)mc_addr[5]) << 8));
333 default: /* Invalid mc_filter_type */
334 DEBUGOUT("MC filter type param set incorrectly\n");
339 /* vector can only be 12-bits or boundary will be exceeded */
345 * txgbe_set_mta - Set bit-vector in multicast table
346 * @hw: pointer to hardware structure
347 * @mc_addr: Multicast address
349 * Sets the bit-vector in the multicast table.
351 void txgbe_set_mta(struct txgbe_hw *hw, u8 *mc_addr)
357 DEBUGFUNC("txgbe_set_mta");
359 hw->addr_ctrl.mta_in_use++;
361 vector = txgbe_mta_vector(hw, mc_addr);
362 DEBUGOUT(" bit-vector = 0x%03X\n", vector);
365 * The MTA is a register array of 128 32-bit registers. It is treated
366 * like an array of 4096 bits. We want to set bit
367 * BitArray[vector_value]. So we figure out what register the bit is
368 * in, read it, OR in the new bit, then write back the new value. The
369 * register is determined by the upper 7 bits of the vector value and
370 * the bit within that register are determined by the lower 5 bits of
373 vector_reg = (vector >> 5) & 0x7F;
374 vector_bit = vector & 0x1F;
375 hw->mac.mta_shadow[vector_reg] |= (1 << vector_bit);
379 * txgbe_update_mc_addr_list - Updates MAC list of multicast addresses
380 * @hw: pointer to hardware structure
381 * @mc_addr_list: the list of new multicast addresses
382 * @mc_addr_count: number of addresses
383 * @next: iterator function to walk the multicast address list
384 * @clear: flag, when set clears the table beforehand
386 * When the clear flag is set, the given list replaces any existing list.
387 * Hashes the given addresses into the multicast table.
389 s32 txgbe_update_mc_addr_list(struct txgbe_hw *hw, u8 *mc_addr_list,
390 u32 mc_addr_count, txgbe_mc_addr_itr next,
396 DEBUGFUNC("txgbe_update_mc_addr_list");
399 * Set the new number of MC addresses that we are being requested to
402 hw->addr_ctrl.num_mc_addrs = mc_addr_count;
403 hw->addr_ctrl.mta_in_use = 0;
405 /* Clear mta_shadow */
407 DEBUGOUT(" Clearing MTA\n");
408 memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow));
411 /* Update mta_shadow */
412 for (i = 0; i < mc_addr_count; i++) {
413 DEBUGOUT(" Adding the multicast addresses:\n");
414 txgbe_set_mta(hw, next(hw, &mc_addr_list, &vmdq));
418 for (i = 0; i < hw->mac.mcft_size; i++)
419 wr32a(hw, TXGBE_MCADDRTBL(0), i,
420 hw->mac.mta_shadow[i]);
422 if (hw->addr_ctrl.mta_in_use > 0) {
423 u32 psrctl = rd32(hw, TXGBE_PSRCTL);
424 psrctl &= ~(TXGBE_PSRCTL_ADHF12_MASK | TXGBE_PSRCTL_MCHFENA);
425 psrctl |= TXGBE_PSRCTL_MCHFENA |
426 TXGBE_PSRCTL_ADHF12(hw->mac.mc_filter_type);
427 wr32(hw, TXGBE_PSRCTL, psrctl);
430 DEBUGOUT("txgbe update mc addr list complete\n");
435 * txgbe_get_san_mac_addr_offset - Get SAN MAC address offset from the EEPROM
436 * @hw: pointer to hardware structure
437 * @san_mac_offset: SAN MAC address offset
439 * This function will read the EEPROM location for the SAN MAC address
440 * pointer, and returns the value at that location. This is used in both
441 * get and set mac_addr routines.
443 static s32 txgbe_get_san_mac_addr_offset(struct txgbe_hw *hw,
448 DEBUGFUNC("txgbe_get_san_mac_addr_offset");
451 * First read the EEPROM pointer to see if the MAC addresses are
454 err = hw->rom.readw_sw(hw, TXGBE_SAN_MAC_ADDR_PTR,
457 DEBUGOUT("eeprom at offset %d failed",
458 TXGBE_SAN_MAC_ADDR_PTR);
465 * txgbe_get_san_mac_addr - SAN MAC address retrieval from the EEPROM
466 * @hw: pointer to hardware structure
467 * @san_mac_addr: SAN MAC address
469 * Reads the SAN MAC address from the EEPROM, if it's available. This is
470 * per-port, so set_lan_id() must be called before reading the addresses.
471 * set_lan_id() is called by identify_sfp(), but this cannot be relied
472 * upon for non-SFP connections, so we must call it here.
474 s32 txgbe_get_san_mac_addr(struct txgbe_hw *hw, u8 *san_mac_addr)
476 u16 san_mac_data, san_mac_offset;
480 DEBUGFUNC("txgbe_get_san_mac_addr");
483 * First read the EEPROM pointer to see if the MAC addresses are
484 * available. If they're not, no point in calling set_lan_id() here.
486 err = txgbe_get_san_mac_addr_offset(hw, &san_mac_offset);
487 if (err || san_mac_offset == 0 || san_mac_offset == 0xFFFF)
488 goto san_mac_addr_out;
490 /* apply the port offset to the address offset */
491 (hw->bus.func) ? (san_mac_offset += TXGBE_SAN_MAC_ADDR_PORT1_OFFSET) :
492 (san_mac_offset += TXGBE_SAN_MAC_ADDR_PORT0_OFFSET);
493 for (i = 0; i < 3; i++) {
494 err = hw->rom.read16(hw, san_mac_offset,
497 DEBUGOUT("eeprom read at offset %d failed",
499 goto san_mac_addr_out;
501 san_mac_addr[i * 2] = (u8)(san_mac_data);
502 san_mac_addr[i * 2 + 1] = (u8)(san_mac_data >> 8);
509 * No addresses available in this EEPROM. It's not an
510 * error though, so just wipe the local address and return.
512 for (i = 0; i < 6; i++)
513 san_mac_addr[i] = 0xFF;
518 * txgbe_set_san_mac_addr - Write the SAN MAC address to the EEPROM
519 * @hw: pointer to hardware structure
520 * @san_mac_addr: SAN MAC address
522 * Write a SAN MAC address to the EEPROM.
524 s32 txgbe_set_san_mac_addr(struct txgbe_hw *hw, u8 *san_mac_addr)
527 u16 san_mac_data, san_mac_offset;
530 DEBUGFUNC("txgbe_set_san_mac_addr");
532 /* Look for SAN mac address pointer. If not defined, return */
533 err = txgbe_get_san_mac_addr_offset(hw, &san_mac_offset);
534 if (err || san_mac_offset == 0 || san_mac_offset == 0xFFFF)
535 return TXGBE_ERR_NO_SAN_ADDR_PTR;
537 /* Apply the port offset to the address offset */
538 (hw->bus.func) ? (san_mac_offset += TXGBE_SAN_MAC_ADDR_PORT1_OFFSET) :
539 (san_mac_offset += TXGBE_SAN_MAC_ADDR_PORT0_OFFSET);
541 for (i = 0; i < 3; i++) {
542 san_mac_data = (u16)((u16)(san_mac_addr[i * 2 + 1]) << 8);
543 san_mac_data |= (u16)(san_mac_addr[i * 2]);
544 hw->rom.write16(hw, san_mac_offset, san_mac_data);
552 * txgbe_init_uta_tables - Initialize the Unicast Table Array
553 * @hw: pointer to hardware structure
555 s32 txgbe_init_uta_tables(struct txgbe_hw *hw)
559 DEBUGFUNC("txgbe_init_uta_tables");
560 DEBUGOUT(" Clearing UTA\n");
562 for (i = 0; i < 128; i++)
563 wr32(hw, TXGBE_UCADDRTBL(i), 0);
569 * txgbe_need_crosstalk_fix - Determine if we need to do cross talk fix
570 * @hw: pointer to hardware structure
572 * Contains the logic to identify if we need to verify link for the
575 static bool txgbe_need_crosstalk_fix(struct txgbe_hw *hw)
577 /* Does FW say we need the fix */
578 if (!hw->need_crosstalk_fix)
581 /* Only consider SFP+ PHYs i.e. media type fiber */
582 switch (hw->phy.media_type) {
583 case txgbe_media_type_fiber:
584 case txgbe_media_type_fiber_qsfp:
594 * txgbe_check_mac_link - Determine link and speed status
595 * @hw: pointer to hardware structure
596 * @speed: pointer to link speed
597 * @link_up: true when link is up
598 * @link_up_wait_to_complete: bool used to wait for link up or not
600 * Reads the links register to determine if link is up and the current speed
602 s32 txgbe_check_mac_link(struct txgbe_hw *hw, u32 *speed,
603 bool *link_up, bool link_up_wait_to_complete)
605 u32 links_reg, links_orig;
608 DEBUGFUNC("txgbe_check_mac_link");
610 /* If Crosstalk fix enabled do the sanity check of making sure
611 * the SFP+ cage is full.
613 if (txgbe_need_crosstalk_fix(hw)) {
616 switch (hw->mac.type) {
617 case txgbe_mac_raptor:
618 sfp_cage_full = !rd32m(hw, TXGBE_GPIODATA,
622 /* sanity check - No SFP+ devices here */
623 sfp_cage_full = false;
627 if (!sfp_cage_full) {
629 *speed = TXGBE_LINK_SPEED_UNKNOWN;
634 /* clear the old state */
635 links_orig = rd32(hw, TXGBE_PORTSTAT);
637 links_reg = rd32(hw, TXGBE_PORTSTAT);
639 if (links_orig != links_reg) {
640 DEBUGOUT("LINKS changed from %08X to %08X\n",
641 links_orig, links_reg);
644 if (link_up_wait_to_complete) {
645 for (i = 0; i < hw->mac.max_link_up_time; i++) {
646 if (!(links_reg & TXGBE_PORTSTAT_UP)) {
653 links_reg = rd32(hw, TXGBE_PORTSTAT);
656 if (links_reg & TXGBE_PORTSTAT_UP)
662 switch (links_reg & TXGBE_PORTSTAT_BW_MASK) {
663 case TXGBE_PORTSTAT_BW_10G:
664 *speed = TXGBE_LINK_SPEED_10GB_FULL;
666 case TXGBE_PORTSTAT_BW_1G:
667 *speed = TXGBE_LINK_SPEED_1GB_FULL;
669 case TXGBE_PORTSTAT_BW_100M:
670 *speed = TXGBE_LINK_SPEED_100M_FULL;
673 *speed = TXGBE_LINK_SPEED_UNKNOWN;
680 * txgbe_clear_tx_pending - Clear pending TX work from the PCIe fifo
681 * @hw: pointer to the hardware structure
683 * The MACs can experience issues if TX work is still pending
684 * when a reset occurs. This function prevents this by flushing the PCIe
685 * buffers on the system.
687 void txgbe_clear_tx_pending(struct txgbe_hw *hw)
692 * If double reset is not requested then all transactions should
693 * already be clear and as such there is no work to do
695 if (!(hw->mac.flags & TXGBE_FLAGS_DOUBLE_RESET_REQUIRED))
698 hlreg0 = rd32(hw, TXGBE_PSRCTL);
699 wr32(hw, TXGBE_PSRCTL, hlreg0 | TXGBE_PSRCTL_LBENA);
701 /* Wait for a last completion before clearing buffers */
706 * Before proceeding, make sure that the PCIe block does not have
707 * transactions pending.
709 poll = (800 * 11) / 10;
710 for (i = 0; i < poll; i++)
713 /* Flush all writes and allow 20usec for all transactions to clear */
717 /* restore previous register values */
718 wr32(hw, TXGBE_PSRCTL, hlreg0);
722 * txgbe_setup_mac_link_multispeed_fiber - Set MAC link speed
723 * @hw: pointer to hardware structure
724 * @speed: new link speed
725 * @autoneg_wait_to_complete: true when waiting for completion is needed
727 * Set the link speed in the MAC and/or PHY register and restarts link.
729 s32 txgbe_setup_mac_link_multispeed_fiber(struct txgbe_hw *hw,
731 bool autoneg_wait_to_complete)
733 u32 link_speed = TXGBE_LINK_SPEED_UNKNOWN;
734 u32 highest_link_speed = TXGBE_LINK_SPEED_UNKNOWN;
738 bool autoneg, link_up = false;
740 DEBUGFUNC("txgbe_setup_mac_link_multispeed_fiber");
742 /* Mask off requested but non-supported speeds */
743 status = hw->mac.get_link_capabilities(hw, &link_speed, &autoneg);
749 /* Try each speed one by one, highest priority first. We do this in
750 * software because 10Gb fiber doesn't support speed autonegotiation.
752 if (speed & TXGBE_LINK_SPEED_10GB_FULL) {
754 highest_link_speed = TXGBE_LINK_SPEED_10GB_FULL;
756 /* Set the module link speed */
757 switch (hw->phy.media_type) {
758 case txgbe_media_type_fiber:
759 hw->mac.set_rate_select_speed(hw,
760 TXGBE_LINK_SPEED_10GB_FULL);
762 case txgbe_media_type_fiber_qsfp:
763 /* QSFP module automatically detects MAC link speed */
766 DEBUGOUT("Unexpected media type.\n");
770 /* Allow module to change analog characteristics (1G->10G) */
773 status = hw->mac.setup_mac_link(hw,
774 TXGBE_LINK_SPEED_10GB_FULL,
775 autoneg_wait_to_complete);
779 /* Flap the Tx laser if it has not already been done */
780 hw->mac.flap_tx_laser(hw);
782 /* Wait for the controller to acquire link. Per IEEE 802.3ap,
783 * Section 73.10.2, we may have to wait up to 500ms if KR is
784 * attempted. uses the same timing for 10g SFI.
786 for (i = 0; i < 5; i++) {
787 /* Wait for the link partner to also set speed */
790 /* If we have link, just jump out */
791 status = hw->mac.check_link(hw, &link_speed,
801 if (speed & TXGBE_LINK_SPEED_1GB_FULL) {
803 if (highest_link_speed == TXGBE_LINK_SPEED_UNKNOWN)
804 highest_link_speed = TXGBE_LINK_SPEED_1GB_FULL;
806 /* Set the module link speed */
807 switch (hw->phy.media_type) {
808 case txgbe_media_type_fiber:
809 hw->mac.set_rate_select_speed(hw,
810 TXGBE_LINK_SPEED_1GB_FULL);
812 case txgbe_media_type_fiber_qsfp:
813 /* QSFP module automatically detects link speed */
816 DEBUGOUT("Unexpected media type.\n");
820 /* Allow module to change analog characteristics (10G->1G) */
823 status = hw->mac.setup_mac_link(hw,
824 TXGBE_LINK_SPEED_1GB_FULL,
825 autoneg_wait_to_complete);
829 /* Flap the Tx laser if it has not already been done */
830 hw->mac.flap_tx_laser(hw);
832 /* Wait for the link partner to also set speed */
835 /* If we have link, just jump out */
836 status = hw->mac.check_link(hw, &link_speed, &link_up, false);
844 /* We didn't get link. Configure back to the highest speed we tried,
845 * (if there was more than one). We call ourselves back with just the
846 * single highest speed that the user requested.
849 status = txgbe_setup_mac_link_multispeed_fiber(hw,
851 autoneg_wait_to_complete);
854 /* Set autoneg_advertised value based on input link speed */
855 hw->phy.autoneg_advertised = 0;
857 if (speed & TXGBE_LINK_SPEED_10GB_FULL)
858 hw->phy.autoneg_advertised |= TXGBE_LINK_SPEED_10GB_FULL;
860 if (speed & TXGBE_LINK_SPEED_1GB_FULL)
861 hw->phy.autoneg_advertised |= TXGBE_LINK_SPEED_1GB_FULL;
867 * txgbe_init_shared_code - Initialize the shared code
868 * @hw: pointer to hardware structure
870 * This will assign function pointers and assign the MAC type and PHY code.
871 * Does not touch the hardware. This function must be called prior to any
872 * other function in the shared code. The txgbe_hw structure should be
873 * memset to 0 prior to calling this function. The following fields in
874 * hw structure should be filled in prior to calling this function:
875 * hw_addr, back, device_id, vendor_id, subsystem_device_id,
876 * subsystem_vendor_id, and revision_id
878 s32 txgbe_init_shared_code(struct txgbe_hw *hw)
882 DEBUGFUNC("txgbe_init_shared_code");
887 txgbe_set_mac_type(hw);
889 txgbe_init_ops_dummy(hw);
890 switch (hw->mac.type) {
891 case txgbe_mac_raptor:
892 status = txgbe_init_ops_pf(hw);
895 status = TXGBE_ERR_DEVICE_NOT_SUPPORTED;
898 hw->mac.max_link_up_time = TXGBE_LINK_UP_TIME;
900 hw->bus.set_lan_id(hw);
906 * txgbe_set_mac_type - Sets MAC type
907 * @hw: pointer to the HW structure
909 * This function sets the mac type of the adapter based on the
910 * vendor ID and device ID stored in the hw structure.
912 s32 txgbe_set_mac_type(struct txgbe_hw *hw)
916 DEBUGFUNC("txgbe_set_mac_type");
918 if (hw->vendor_id != PCI_VENDOR_ID_WANGXUN) {
919 DEBUGOUT("Unsupported vendor id: %x", hw->vendor_id);
920 return TXGBE_ERR_DEVICE_NOT_SUPPORTED;
923 switch (hw->device_id) {
924 case TXGBE_DEV_ID_RAPTOR_KR_KX_KX4:
925 hw->phy.media_type = txgbe_media_type_backplane;
926 hw->mac.type = txgbe_mac_raptor;
928 case TXGBE_DEV_ID_RAPTOR_XAUI:
929 case TXGBE_DEV_ID_RAPTOR_SGMII:
930 hw->phy.media_type = txgbe_media_type_copper;
931 hw->mac.type = txgbe_mac_raptor;
933 case TXGBE_DEV_ID_RAPTOR_SFP:
934 case TXGBE_DEV_ID_WX1820_SFP:
935 hw->phy.media_type = txgbe_media_type_fiber;
936 hw->mac.type = txgbe_mac_raptor;
938 case TXGBE_DEV_ID_RAPTOR_QSFP:
939 hw->phy.media_type = txgbe_media_type_fiber_qsfp;
940 hw->mac.type = txgbe_mac_raptor;
942 case TXGBE_DEV_ID_RAPTOR_VF:
943 case TXGBE_DEV_ID_RAPTOR_VF_HV:
944 hw->phy.media_type = txgbe_media_type_virtual;
945 hw->mac.type = txgbe_mac_raptor_vf;
948 err = TXGBE_ERR_DEVICE_NOT_SUPPORTED;
949 DEBUGOUT("Unsupported device id: %x", hw->device_id);
953 DEBUGOUT("found mac: %d media: %d, returns: %d\n",
954 hw->mac.type, hw->phy.media_type, err);
958 void txgbe_init_mac_link_ops(struct txgbe_hw *hw)
960 struct txgbe_mac_info *mac = &hw->mac;
962 DEBUGFUNC("txgbe_init_mac_link_ops");
965 * enable the laser control functions for SFP+ fiber
966 * and MNG not enabled
968 if (hw->phy.media_type == txgbe_media_type_fiber &&
969 !txgbe_mng_enabled(hw)) {
970 mac->disable_tx_laser =
971 txgbe_disable_tx_laser_multispeed_fiber;
972 mac->enable_tx_laser =
973 txgbe_enable_tx_laser_multispeed_fiber;
975 txgbe_flap_tx_laser_multispeed_fiber;
978 if ((hw->phy.media_type == txgbe_media_type_fiber ||
979 hw->phy.media_type == txgbe_media_type_fiber_qsfp) &&
980 hw->phy.multispeed_fiber) {
981 /* Set up dual speed SFP+ support */
982 mac->setup_link = txgbe_setup_mac_link_multispeed_fiber;
983 mac->setup_mac_link = txgbe_setup_mac_link;
984 mac->set_rate_select_speed = txgbe_set_hard_rate_select_speed;
985 } else if ((hw->phy.media_type == txgbe_media_type_backplane) &&
986 (hw->phy.smart_speed == txgbe_smart_speed_auto ||
987 hw->phy.smart_speed == txgbe_smart_speed_on) &&
988 !txgbe_verify_lesm_fw_enabled_raptor(hw)) {
989 mac->setup_link = txgbe_setup_mac_link_smartspeed;
991 mac->setup_link = txgbe_setup_mac_link;
996 * txgbe_init_phy_raptor - PHY/SFP specific init
997 * @hw: pointer to hardware structure
999 * Initialize any function pointers that were not able to be
1000 * set during init_shared_code because the PHY/SFP type was
1001 * not known. Perform the SFP init if necessary.
1004 s32 txgbe_init_phy_raptor(struct txgbe_hw *hw)
1006 struct txgbe_mac_info *mac = &hw->mac;
1007 struct txgbe_phy_info *phy = &hw->phy;
1010 DEBUGFUNC("txgbe_init_phy_raptor");
1012 if (hw->device_id == TXGBE_DEV_ID_RAPTOR_QSFP) {
1013 /* Store flag indicating I2C bus access control unit. */
1014 hw->phy.qsfp_shared_i2c_bus = TRUE;
1016 /* Initialize access to QSFP+ I2C bus */
1020 /* Identify the PHY or SFP module */
1021 err = phy->identify(hw);
1022 if (err == TXGBE_ERR_SFP_NOT_SUPPORTED)
1023 goto init_phy_ops_out;
1025 /* Setup function pointers based on detected SFP module and speeds */
1026 txgbe_init_mac_link_ops(hw);
1028 /* If copper media, overwrite with copper function pointers */
1029 if (phy->media_type == txgbe_media_type_copper) {
1030 mac->setup_link = txgbe_setup_copper_link_raptor;
1031 mac->get_link_capabilities =
1032 txgbe_get_copper_link_capabilities;
1035 /* Set necessary function pointers based on PHY type */
1036 switch (hw->phy.type) {
1038 phy->setup_link = txgbe_setup_phy_link_tnx;
1039 phy->check_link = txgbe_check_phy_link_tnx;
1050 * txgbe_init_ops_pf - Inits func ptrs and MAC type
1051 * @hw: pointer to hardware structure
1053 * Initialize the function pointers and assign the MAC type.
1054 * Does not touch the hardware.
1056 s32 txgbe_init_ops_pf(struct txgbe_hw *hw)
1058 struct txgbe_bus_info *bus = &hw->bus;
1059 struct txgbe_mac_info *mac = &hw->mac;
1060 struct txgbe_phy_info *phy = &hw->phy;
1061 struct txgbe_rom_info *rom = &hw->rom;
1063 DEBUGFUNC("txgbe_init_ops_pf");
1066 bus->set_lan_id = txgbe_set_lan_id_multi_port;
1069 phy->identify = txgbe_identify_phy;
1070 phy->init = txgbe_init_phy_raptor;
1071 phy->read_reg = txgbe_read_phy_reg;
1072 phy->write_reg = txgbe_write_phy_reg;
1073 phy->read_reg_mdi = txgbe_read_phy_reg_mdi;
1074 phy->write_reg_mdi = txgbe_write_phy_reg_mdi;
1075 phy->setup_link = txgbe_setup_phy_link;
1076 phy->setup_link_speed = txgbe_setup_phy_link_speed;
1077 phy->read_i2c_byte = txgbe_read_i2c_byte;
1078 phy->write_i2c_byte = txgbe_write_i2c_byte;
1079 phy->read_i2c_eeprom = txgbe_read_i2c_eeprom;
1080 phy->write_i2c_eeprom = txgbe_write_i2c_eeprom;
1081 phy->reset = txgbe_reset_phy;
1084 mac->init_hw = txgbe_init_hw;
1085 mac->get_mac_addr = txgbe_get_mac_addr;
1086 mac->reset_hw = txgbe_reset_hw;
1087 mac->get_san_mac_addr = txgbe_get_san_mac_addr;
1088 mac->set_san_mac_addr = txgbe_set_san_mac_addr;
1089 mac->autoc_read = txgbe_autoc_read;
1090 mac->autoc_write = txgbe_autoc_write;
1092 mac->set_rar = txgbe_set_rar;
1093 mac->clear_rar = txgbe_clear_rar;
1094 mac->init_rx_addrs = txgbe_init_rx_addrs;
1095 mac->init_uta_tables = txgbe_init_uta_tables;
1097 mac->get_link_capabilities = txgbe_get_link_capabilities_raptor;
1098 mac->check_link = txgbe_check_mac_link;
1101 rom->init_params = txgbe_init_eeprom_params;
1102 rom->read16 = txgbe_ee_read16;
1103 rom->readw_buffer = txgbe_ee_readw_buffer;
1104 rom->readw_sw = txgbe_ee_readw_sw;
1105 rom->read32 = txgbe_ee_read32;
1106 rom->write16 = txgbe_ee_write16;
1107 rom->writew_buffer = txgbe_ee_writew_buffer;
1108 rom->writew_sw = txgbe_ee_writew_sw;
1109 rom->write32 = txgbe_ee_write32;
1110 rom->validate_checksum = txgbe_validate_eeprom_checksum;
1111 rom->update_checksum = txgbe_update_eeprom_checksum;
1112 rom->calc_checksum = txgbe_calc_eeprom_checksum;
1114 mac->mcft_size = TXGBE_RAPTOR_MC_TBL_SIZE;
1115 mac->num_rar_entries = TXGBE_RAPTOR_RAR_ENTRIES;
1116 mac->max_rx_queues = TXGBE_RAPTOR_MAX_RX_QUEUES;
1117 mac->max_tx_queues = TXGBE_RAPTOR_MAX_TX_QUEUES;
1123 * txgbe_get_link_capabilities_raptor - Determines link capabilities
1124 * @hw: pointer to hardware structure
1125 * @speed: pointer to link speed
1126 * @autoneg: true when autoneg or autotry is enabled
1128 * Determines the link capabilities by reading the AUTOC register.
1130 s32 txgbe_get_link_capabilities_raptor(struct txgbe_hw *hw,
1137 DEBUGFUNC("txgbe_get_link_capabilities_raptor");
1139 /* Check if 1G SFP module. */
1140 if (hw->phy.sfp_type == txgbe_sfp_type_1g_cu_core0 ||
1141 hw->phy.sfp_type == txgbe_sfp_type_1g_cu_core1 ||
1142 hw->phy.sfp_type == txgbe_sfp_type_1g_lx_core0 ||
1143 hw->phy.sfp_type == txgbe_sfp_type_1g_lx_core1 ||
1144 hw->phy.sfp_type == txgbe_sfp_type_1g_sx_core0 ||
1145 hw->phy.sfp_type == txgbe_sfp_type_1g_sx_core1) {
1146 *speed = TXGBE_LINK_SPEED_1GB_FULL;
1152 * Determine link capabilities based on the stored value of AUTOC,
1153 * which represents EEPROM defaults. If AUTOC value has not
1154 * been stored, use the current register values.
1156 if (hw->mac.orig_link_settings_stored)
1157 autoc = hw->mac.orig_autoc;
1159 autoc = hw->mac.autoc_read(hw);
1161 switch (autoc & TXGBE_AUTOC_LMS_MASK) {
1162 case TXGBE_AUTOC_LMS_1G_LINK_NO_AN:
1163 *speed = TXGBE_LINK_SPEED_1GB_FULL;
1167 case TXGBE_AUTOC_LMS_10G_LINK_NO_AN:
1168 *speed = TXGBE_LINK_SPEED_10GB_FULL;
1172 case TXGBE_AUTOC_LMS_1G_AN:
1173 *speed = TXGBE_LINK_SPEED_1GB_FULL;
1177 case TXGBE_AUTOC_LMS_10G:
1178 *speed = TXGBE_LINK_SPEED_10GB_FULL;
1182 case TXGBE_AUTOC_LMS_KX4_KX_KR:
1183 case TXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN:
1184 *speed = TXGBE_LINK_SPEED_UNKNOWN;
1185 if (autoc & TXGBE_AUTOC_KR_SUPP)
1186 *speed |= TXGBE_LINK_SPEED_10GB_FULL;
1187 if (autoc & TXGBE_AUTOC_KX4_SUPP)
1188 *speed |= TXGBE_LINK_SPEED_10GB_FULL;
1189 if (autoc & TXGBE_AUTOC_KX_SUPP)
1190 *speed |= TXGBE_LINK_SPEED_1GB_FULL;
1194 case TXGBE_AUTOC_LMS_KX4_KX_KR_SGMII:
1195 *speed = TXGBE_LINK_SPEED_100M_FULL;
1196 if (autoc & TXGBE_AUTOC_KR_SUPP)
1197 *speed |= TXGBE_LINK_SPEED_10GB_FULL;
1198 if (autoc & TXGBE_AUTOC_KX4_SUPP)
1199 *speed |= TXGBE_LINK_SPEED_10GB_FULL;
1200 if (autoc & TXGBE_AUTOC_KX_SUPP)
1201 *speed |= TXGBE_LINK_SPEED_1GB_FULL;
1205 case TXGBE_AUTOC_LMS_SGMII_1G_100M:
1206 *speed = TXGBE_LINK_SPEED_1GB_FULL |
1207 TXGBE_LINK_SPEED_100M_FULL |
1208 TXGBE_LINK_SPEED_10M_FULL;
1213 return TXGBE_ERR_LINK_SETUP;
1216 if (hw->phy.multispeed_fiber) {
1217 *speed |= TXGBE_LINK_SPEED_10GB_FULL |
1218 TXGBE_LINK_SPEED_1GB_FULL;
1220 /* QSFP must not enable full auto-negotiation
1221 * Limited autoneg is enabled at 1G
1223 if (hw->phy.media_type == txgbe_media_type_fiber_qsfp)
1233 * txgbe_start_mac_link_raptor - Setup MAC link settings
1234 * @hw: pointer to hardware structure
1235 * @autoneg_wait_to_complete: true when waiting for completion is needed
1237 * Configures link settings based on values in the txgbe_hw struct.
1238 * Restarts the link. Performs autonegotiation if needed.
1240 s32 txgbe_start_mac_link_raptor(struct txgbe_hw *hw,
1241 bool autoneg_wait_to_complete)
1244 bool got_lock = false;
1246 DEBUGFUNC("txgbe_start_mac_link_raptor");
1248 UNREFERENCED_PARAMETER(autoneg_wait_to_complete);
1250 /* reset_pipeline requires us to hold this lock as it writes to
1253 if (txgbe_verify_lesm_fw_enabled_raptor(hw)) {
1254 status = hw->mac.acquire_swfw_sync(hw, TXGBE_MNGSEM_SWPHY);
1262 txgbe_reset_pipeline_raptor(hw);
1265 hw->mac.release_swfw_sync(hw, TXGBE_MNGSEM_SWPHY);
1267 /* Add delay to filter out noises during initial link setup */
1275 * txgbe_disable_tx_laser_multispeed_fiber - Disable Tx laser
1276 * @hw: pointer to hardware structure
1278 * The base drivers may require better control over SFP+ module
1279 * PHY states. This includes selectively shutting down the Tx
1280 * laser on the PHY, effectively halting physical link.
1282 void txgbe_disable_tx_laser_multispeed_fiber(struct txgbe_hw *hw)
1284 u32 esdp_reg = rd32(hw, TXGBE_GPIODATA);
1286 /* Blocked by MNG FW so bail */
1287 if (txgbe_check_reset_blocked(hw))
1290 /* Disable Tx laser; allow 100us to go dark per spec */
1291 esdp_reg |= (TXGBE_GPIOBIT_0 | TXGBE_GPIOBIT_1);
1292 wr32(hw, TXGBE_GPIODATA, esdp_reg);
1298 * txgbe_enable_tx_laser_multispeed_fiber - Enable Tx laser
1299 * @hw: pointer to hardware structure
1301 * The base drivers may require better control over SFP+ module
1302 * PHY states. This includes selectively turning on the Tx
1303 * laser on the PHY, effectively starting physical link.
1305 void txgbe_enable_tx_laser_multispeed_fiber(struct txgbe_hw *hw)
1307 u32 esdp_reg = rd32(hw, TXGBE_GPIODATA);
1309 /* Enable Tx laser; allow 100ms to light up */
1310 esdp_reg &= ~(TXGBE_GPIOBIT_0 | TXGBE_GPIOBIT_1);
1311 wr32(hw, TXGBE_GPIODATA, esdp_reg);
1317 * txgbe_flap_tx_laser_multispeed_fiber - Flap Tx laser
1318 * @hw: pointer to hardware structure
1320 * When the driver changes the link speeds that it can support,
1321 * it sets autotry_restart to true to indicate that we need to
1322 * initiate a new autotry session with the link partner. To do
1323 * so, we set the speed then disable and re-enable the Tx laser, to
1324 * alert the link partner that it also needs to restart autotry on its
1325 * end. This is consistent with true clause 37 autoneg, which also
1326 * involves a loss of signal.
1328 void txgbe_flap_tx_laser_multispeed_fiber(struct txgbe_hw *hw)
1330 DEBUGFUNC("txgbe_flap_tx_laser_multispeed_fiber");
1332 /* Blocked by MNG FW so bail */
1333 if (txgbe_check_reset_blocked(hw))
1336 if (hw->mac.autotry_restart) {
1337 txgbe_disable_tx_laser_multispeed_fiber(hw);
1338 txgbe_enable_tx_laser_multispeed_fiber(hw);
1339 hw->mac.autotry_restart = false;
1344 * txgbe_set_hard_rate_select_speed - Set module link speed
1345 * @hw: pointer to hardware structure
1346 * @speed: link speed to set
1348 * Set module link speed via RS0/RS1 rate select pins.
1350 void txgbe_set_hard_rate_select_speed(struct txgbe_hw *hw,
1353 u32 esdp_reg = rd32(hw, TXGBE_GPIODATA);
1356 case TXGBE_LINK_SPEED_10GB_FULL:
1357 esdp_reg |= (TXGBE_GPIOBIT_4 | TXGBE_GPIOBIT_5);
1359 case TXGBE_LINK_SPEED_1GB_FULL:
1360 esdp_reg &= ~(TXGBE_GPIOBIT_4 | TXGBE_GPIOBIT_5);
1363 DEBUGOUT("Invalid fixed module speed\n");
1367 wr32(hw, TXGBE_GPIODATA, esdp_reg);
1372 * txgbe_setup_mac_link_smartspeed - Set MAC link speed using SmartSpeed
1373 * @hw: pointer to hardware structure
1374 * @speed: new link speed
1375 * @autoneg_wait_to_complete: true when waiting for completion is needed
1377 * Implements the Intel SmartSpeed algorithm.
1379 s32 txgbe_setup_mac_link_smartspeed(struct txgbe_hw *hw,
1381 bool autoneg_wait_to_complete)
1384 u32 link_speed = TXGBE_LINK_SPEED_UNKNOWN;
1386 bool link_up = false;
1387 u32 autoc_reg = rd32_epcs(hw, SR_AN_MMD_ADV_REG1);
1389 DEBUGFUNC("txgbe_setup_mac_link_smartspeed");
1391 /* Set autoneg_advertised value based on input link speed */
1392 hw->phy.autoneg_advertised = 0;
1394 if (speed & TXGBE_LINK_SPEED_10GB_FULL)
1395 hw->phy.autoneg_advertised |= TXGBE_LINK_SPEED_10GB_FULL;
1397 if (speed & TXGBE_LINK_SPEED_1GB_FULL)
1398 hw->phy.autoneg_advertised |= TXGBE_LINK_SPEED_1GB_FULL;
1400 if (speed & TXGBE_LINK_SPEED_100M_FULL)
1401 hw->phy.autoneg_advertised |= TXGBE_LINK_SPEED_100M_FULL;
1404 * Implement Intel SmartSpeed algorithm. SmartSpeed will reduce the
1405 * autoneg advertisement if link is unable to be established at the
1406 * highest negotiated rate. This can sometimes happen due to integrity
1407 * issues with the physical media connection.
1410 /* First, try to get link with full advertisement */
1411 hw->phy.smart_speed_active = false;
1412 for (j = 0; j < TXGBE_SMARTSPEED_MAX_RETRIES; j++) {
1413 status = txgbe_setup_mac_link(hw, speed,
1414 autoneg_wait_to_complete);
1419 * Wait for the controller to acquire link. Per IEEE 802.3ap,
1420 * Section 73.10.2, we may have to wait up to 500ms if KR is
1421 * attempted, or 200ms if KX/KX4/BX/BX4 is attempted, per
1422 * Table 9 in the AN MAS.
1424 for (i = 0; i < 5; i++) {
1427 /* If we have link, just jump out */
1428 status = hw->mac.check_link(hw, &link_speed, &link_up,
1439 * We didn't get link. If we advertised KR plus one of KX4/KX
1440 * (or BX4/BX), then disable KR and try again.
1442 if (((autoc_reg & TXGBE_AUTOC_KR_SUPP) == 0) ||
1443 ((autoc_reg & TXGBE_AUTOC_KX_SUPP) == 0 &&
1444 (autoc_reg & TXGBE_AUTOC_KX4_SUPP) == 0))
1447 /* Turn SmartSpeed on to disable KR support */
1448 hw->phy.smart_speed_active = true;
1449 status = txgbe_setup_mac_link(hw, speed,
1450 autoneg_wait_to_complete);
1455 * Wait for the controller to acquire link. 600ms will allow for
1456 * the AN link_fail_inhibit_timer as well for multiple cycles of
1457 * parallel detect, both 10g and 1g. This allows for the maximum
1458 * connect attempts as defined in the AN MAS table 73-7.
1460 for (i = 0; i < 6; i++) {
1463 /* If we have link, just jump out */
1464 status = hw->mac.check_link(hw, &link_speed, &link_up, false);
1472 /* We didn't get link. Turn SmartSpeed back off. */
1473 hw->phy.smart_speed_active = false;
1474 status = txgbe_setup_mac_link(hw, speed,
1475 autoneg_wait_to_complete);
1478 if (link_up && link_speed == TXGBE_LINK_SPEED_1GB_FULL)
1479 DEBUGOUT("Smartspeed has downgraded the link speed "
1480 "from the maximum advertised\n");
1485 * txgbe_setup_mac_link - Set MAC link speed
1486 * @hw: pointer to hardware structure
1487 * @speed: new link speed
1488 * @autoneg_wait_to_complete: true when waiting for completion is needed
1490 * Set the link speed in the AUTOC register and restarts link.
1492 s32 txgbe_setup_mac_link(struct txgbe_hw *hw,
1494 bool autoneg_wait_to_complete)
1496 bool autoneg = false;
1499 u64 autoc = hw->mac.autoc_read(hw);
1500 u64 pma_pmd_10gs = autoc & TXGBE_AUTOC_10GS_PMA_PMD_MASK;
1501 u64 pma_pmd_1g = autoc & TXGBE_AUTOC_1G_PMA_PMD_MASK;
1502 u64 link_mode = autoc & TXGBE_AUTOC_LMS_MASK;
1503 u64 current_autoc = autoc;
1507 u32 link_capabilities = TXGBE_LINK_SPEED_UNKNOWN;
1509 DEBUGFUNC("txgbe_setup_mac_link");
1511 /* Check to see if speed passed in is supported. */
1512 status = hw->mac.get_link_capabilities(hw,
1513 &link_capabilities, &autoneg);
1517 speed &= link_capabilities;
1518 if (speed == TXGBE_LINK_SPEED_UNKNOWN)
1519 return TXGBE_ERR_LINK_SETUP;
1521 /* Use stored value (EEPROM defaults) of AUTOC to find KR/KX4 support*/
1522 if (hw->mac.orig_link_settings_stored)
1523 orig_autoc = hw->mac.orig_autoc;
1527 link_mode = autoc & TXGBE_AUTOC_LMS_MASK;
1528 pma_pmd_1g = autoc & TXGBE_AUTOC_1G_PMA_PMD_MASK;
1530 if (link_mode == TXGBE_AUTOC_LMS_KX4_KX_KR ||
1531 link_mode == TXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
1532 link_mode == TXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
1533 /* Set KX4/KX/KR support according to speed requested */
1534 autoc &= ~(TXGBE_AUTOC_KX_SUPP |
1535 TXGBE_AUTOC_KX4_SUPP |
1536 TXGBE_AUTOC_KR_SUPP);
1537 if (speed & TXGBE_LINK_SPEED_10GB_FULL) {
1538 if (orig_autoc & TXGBE_AUTOC_KX4_SUPP)
1539 autoc |= TXGBE_AUTOC_KX4_SUPP;
1540 if ((orig_autoc & TXGBE_AUTOC_KR_SUPP) &&
1541 !hw->phy.smart_speed_active)
1542 autoc |= TXGBE_AUTOC_KR_SUPP;
1544 if (speed & TXGBE_LINK_SPEED_1GB_FULL)
1545 autoc |= TXGBE_AUTOC_KX_SUPP;
1546 } else if ((pma_pmd_1g == TXGBE_AUTOC_1G_SFI) &&
1547 (link_mode == TXGBE_AUTOC_LMS_1G_LINK_NO_AN ||
1548 link_mode == TXGBE_AUTOC_LMS_1G_AN)) {
1549 /* Switch from 1G SFI to 10G SFI if requested */
1550 if (speed == TXGBE_LINK_SPEED_10GB_FULL &&
1551 pma_pmd_10gs == TXGBE_AUTOC_10GS_SFI) {
1552 autoc &= ~TXGBE_AUTOC_LMS_MASK;
1553 autoc |= TXGBE_AUTOC_LMS_10G;
1555 } else if ((pma_pmd_10gs == TXGBE_AUTOC_10GS_SFI) &&
1556 (link_mode == TXGBE_AUTOC_LMS_10G)) {
1557 /* Switch from 10G SFI to 1G SFI if requested */
1558 if (speed == TXGBE_LINK_SPEED_1GB_FULL &&
1559 pma_pmd_1g == TXGBE_AUTOC_1G_SFI) {
1560 autoc &= ~TXGBE_AUTOC_LMS_MASK;
1561 if (autoneg || hw->phy.type == txgbe_phy_qsfp_intel)
1562 autoc |= TXGBE_AUTOC_LMS_1G_AN;
1564 autoc |= TXGBE_AUTOC_LMS_1G_LINK_NO_AN;
1568 if (autoc == current_autoc)
1571 autoc &= ~TXGBE_AUTOC_SPEED_MASK;
1572 autoc |= TXGBE_AUTOC_SPEED(speed);
1573 autoc |= (autoneg ? TXGBE_AUTOC_AUTONEG : 0);
1576 hw->mac.autoc_write(hw, autoc);
1578 /* Only poll for autoneg to complete if specified to do so */
1579 if (autoneg_wait_to_complete) {
1580 if (link_mode == TXGBE_AUTOC_LMS_KX4_KX_KR ||
1581 link_mode == TXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
1582 link_mode == TXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
1583 links_reg = 0; /*Just in case Autoneg time=0*/
1584 for (i = 0; i < TXGBE_AUTO_NEG_TIME; i++) {
1585 links_reg = rd32(hw, TXGBE_PORTSTAT);
1586 if (links_reg & TXGBE_PORTSTAT_UP)
1590 if (!(links_reg & TXGBE_PORTSTAT_UP)) {
1591 status = TXGBE_ERR_AUTONEG_NOT_COMPLETE;
1592 DEBUGOUT("Autoneg did not complete.\n");
1597 /* Add delay to filter out noises during initial link setup */
1604 * txgbe_setup_copper_link_raptor - Set the PHY autoneg advertised field
1605 * @hw: pointer to hardware structure
1606 * @speed: new link speed
1607 * @autoneg_wait_to_complete: true if waiting is needed to complete
1609 * Restarts link on PHY and MAC based on settings passed in.
1611 static s32 txgbe_setup_copper_link_raptor(struct txgbe_hw *hw,
1613 bool autoneg_wait_to_complete)
1617 DEBUGFUNC("txgbe_setup_copper_link_raptor");
1619 /* Setup the PHY according to input speed */
1620 status = hw->phy.setup_link_speed(hw, speed,
1621 autoneg_wait_to_complete);
1623 txgbe_start_mac_link_raptor(hw, autoneg_wait_to_complete);
1629 txgbe_check_flash_load(struct txgbe_hw *hw, u32 check_bit)
1634 /* if there's flash existing */
1635 if (!(rd32(hw, TXGBE_SPISTAT) & TXGBE_SPISTAT_BPFLASH)) {
1636 /* wait hw load flash done */
1637 for (i = 0; i < 10; i++) {
1638 reg = rd32(hw, TXGBE_ILDRSTAT);
1639 if (!(reg & check_bit)) {
1646 err = TXGBE_ERR_FLASH_LOADING_FAILED;
1652 * txgbe_reset_hw - Perform hardware reset
1653 * @hw: pointer to hardware structure
1655 * Resets the hardware by resetting the transmit and receive units, masks
1656 * and clears all interrupts, perform a PHY reset, and perform a link (MAC)
1659 s32 txgbe_reset_hw(struct txgbe_hw *hw)
1664 DEBUGFUNC("txgbe_reset_hw");
1666 /* Call adapter stop to disable tx/rx and clear interrupts */
1667 status = hw->mac.stop_hw(hw);
1671 /* flush pending Tx transactions */
1672 txgbe_clear_tx_pending(hw);
1674 /* Identify PHY and related function pointers */
1675 status = hw->phy.init(hw);
1676 if (status == TXGBE_ERR_SFP_NOT_SUPPORTED)
1679 /* Setup SFP module if there is one present. */
1680 if (hw->phy.sfp_setup_needed) {
1681 status = hw->mac.setup_sfp(hw);
1682 hw->phy.sfp_setup_needed = false;
1684 if (status == TXGBE_ERR_SFP_NOT_SUPPORTED)
1688 if (!hw->phy.reset_disable)
1691 /* remember AUTOC from before we reset */
1692 autoc = hw->mac.autoc_read(hw);
1696 * Issue global reset to the MAC. Needs to be SW reset if link is up.
1697 * If link reset is used when link is up, it might reset the PHY when
1698 * mng is using it. If link is down or the flag to force full link
1699 * reset is set, then perform link reset.
1701 if (txgbe_mng_present(hw)) {
1702 txgbe_hic_reset(hw);
1704 wr32(hw, TXGBE_RST, TXGBE_RST_LAN(hw->bus.lan_id));
1709 if (hw->bus.lan_id == 0) {
1710 status = txgbe_check_flash_load(hw,
1711 TXGBE_ILDRSTAT_SWRST_LAN0);
1713 status = txgbe_check_flash_load(hw,
1714 TXGBE_ILDRSTAT_SWRST_LAN1);
1722 * Double resets are required for recovery from certain error
1723 * conditions. Between resets, it is necessary to stall to
1724 * allow time for any pending HW events to complete.
1726 if (hw->mac.flags & TXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
1727 hw->mac.flags &= ~TXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
1732 * Store the original AUTOC/AUTOC2 values if they have not been
1733 * stored off yet. Otherwise restore the stored original
1734 * values since the reset operation sets back to defaults.
1736 if (!hw->mac.orig_link_settings_stored) {
1737 hw->mac.orig_autoc = hw->mac.autoc_read(hw);
1738 hw->mac.autoc_write(hw, hw->mac.orig_autoc);
1739 hw->mac.orig_link_settings_stored = true;
1741 hw->mac.orig_autoc = autoc;
1744 /* Store the permanent mac address */
1745 hw->mac.get_mac_addr(hw, hw->mac.perm_addr);
1748 * Store MAC address from RAR0, clear receive address registers, and
1749 * clear the multicast table. Also reset num_rar_entries to 128,
1750 * since we modify this value when programming the SAN MAC address.
1752 hw->mac.num_rar_entries = 128;
1753 hw->mac.init_rx_addrs(hw);
1755 /* Store the permanent SAN mac address */
1756 hw->mac.get_san_mac_addr(hw, hw->mac.san_addr);
1758 /* Add the SAN MAC address to the RAR only if it's a valid address */
1759 if (txgbe_validate_mac_addr(hw->mac.san_addr) == 0) {
1760 /* Save the SAN MAC RAR index */
1761 hw->mac.san_mac_rar_index = hw->mac.num_rar_entries - 1;
1763 hw->mac.set_rar(hw, hw->mac.san_mac_rar_index,
1764 hw->mac.san_addr, 0, true);
1766 /* clear VMDq pool/queue selection for this RAR */
1767 hw->mac.clear_vmdq(hw, hw->mac.san_mac_rar_index,
1770 /* Reserve the last RAR for the SAN MAC address */
1771 hw->mac.num_rar_entries--;
1774 /* Store the alternative WWNN/WWPN prefix */
1775 hw->mac.get_wwn_prefix(hw, &hw->mac.wwnn_prefix,
1776 &hw->mac.wwpn_prefix);
1782 * txgbe_verify_lesm_fw_enabled_raptor - Checks LESM FW module state.
1783 * @hw: pointer to hardware structure
1785 * Returns true if the LESM FW module is present and enabled. Otherwise
1786 * returns false. Smart Speed must be disabled if LESM FW module is enabled.
1788 bool txgbe_verify_lesm_fw_enabled_raptor(struct txgbe_hw *hw)
1790 bool lesm_enabled = false;
1791 u16 fw_offset, fw_lesm_param_offset, fw_lesm_state;
1794 DEBUGFUNC("txgbe_verify_lesm_fw_enabled_raptor");
1796 /* get the offset to the Firmware Module block */
1797 status = hw->rom.read16(hw, TXGBE_FW_PTR, &fw_offset);
1799 if (status != 0 || fw_offset == 0 || fw_offset == 0xFFFF)
1802 /* get the offset to the LESM Parameters block */
1803 status = hw->rom.read16(hw, (fw_offset +
1804 TXGBE_FW_LESM_PARAMETERS_PTR),
1805 &fw_lesm_param_offset);
1808 fw_lesm_param_offset == 0 || fw_lesm_param_offset == 0xFFFF)
1811 /* get the LESM state word */
1812 status = hw->rom.read16(hw, (fw_lesm_param_offset +
1813 TXGBE_FW_LESM_STATE_1),
1816 if (status == 0 && (fw_lesm_state & TXGBE_FW_LESM_STATE_ENABLED))
1817 lesm_enabled = true;
1820 lesm_enabled = false;
1821 return lesm_enabled;
1825 * txgbe_reset_pipeline_raptor - perform pipeline reset
1827 * @hw: pointer to hardware structure
1829 * Reset pipeline by asserting Restart_AN together with LMS change to ensure
1830 * full pipeline reset. This function assumes the SW/FW lock is held.
1832 s32 txgbe_reset_pipeline_raptor(struct txgbe_hw *hw)
1837 autoc = hw->mac.autoc_read(hw);
1839 /* Enable link if disabled in NVM */
1840 if (autoc & TXGBE_AUTOC_LINK_DIA_MASK)
1841 autoc &= ~TXGBE_AUTOC_LINK_DIA_MASK;
1843 autoc |= TXGBE_AUTOC_AN_RESTART;
1844 /* Write AUTOC register with toggled LMS[2] bit and Restart_AN */
1845 hw->mac.autoc_write(hw, autoc ^ TXGBE_AUTOC_LMS_AN);
1847 /* Write AUTOC register with original LMS field and Restart_AN */
1848 hw->mac.autoc_write(hw, autoc);