1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2015-2020
5 #include "txgbe_type.h"
9 #include "txgbe_eeprom.h"
10 #include "txgbe_mng.h"
13 #define TXGBE_RAPTOR_MAX_TX_QUEUES 128
14 #define TXGBE_RAPTOR_MAX_RX_QUEUES 128
15 #define TXGBE_RAPTOR_RAR_ENTRIES 128
16 #define TXGBE_RAPTOR_MC_TBL_SIZE 128
17 #define TXGBE_RAPTOR_VFT_TBL_SIZE 128
18 #define TXGBE_RAPTOR_RX_PB_SIZE 512 /*KB*/
20 static s32 txgbe_setup_copper_link_raptor(struct txgbe_hw *hw,
22 bool autoneg_wait_to_complete);
24 static s32 txgbe_mta_vector(struct txgbe_hw *hw, u8 *mc_addr);
25 static s32 txgbe_get_san_mac_addr_offset(struct txgbe_hw *hw,
29 * txgbe_device_supports_autoneg_fc - Check if device supports autonegotiation
31 * @hw: pointer to hardware structure
33 * This function returns true if the device supports flow control
34 * autonegotiation, and false if it does not.
37 bool txgbe_device_supports_autoneg_fc(struct txgbe_hw *hw)
39 bool supported = false;
43 DEBUGFUNC("txgbe_device_supports_autoneg_fc");
45 switch (hw->phy.media_type) {
46 case txgbe_media_type_fiber_qsfp:
47 case txgbe_media_type_fiber:
48 hw->mac.check_link(hw, &speed, &link_up, false);
49 /* if link is down, assume supported */
51 supported = speed == TXGBE_LINK_SPEED_1GB_FULL ?
57 case txgbe_media_type_backplane:
60 case txgbe_media_type_copper:
61 /* only some copper devices support flow control autoneg */
62 switch (hw->device_id) {
63 case TXGBE_DEV_ID_RAPTOR_XAUI:
64 case TXGBE_DEV_ID_RAPTOR_SGMII:
75 DEBUGOUT("Device %x does not support flow control autoneg",
81 * txgbe_setup_fc - Set up flow control
82 * @hw: pointer to hardware structure
84 * Called at init time to set up flow control.
86 s32 txgbe_setup_fc(struct txgbe_hw *hw)
95 DEBUGFUNC("txgbe_setup_fc");
97 /* Validate the requested mode */
98 if (hw->fc.strict_ieee && hw->fc.requested_mode == txgbe_fc_rx_pause) {
99 DEBUGOUT("txgbe_fc_rx_pause not valid in strict IEEE mode\n");
100 err = TXGBE_ERR_INVALID_LINK_SETTINGS;
105 * 10gig parts do not have a word in the EEPROM to determine the
106 * default flow control setting, so we explicitly set it to full.
108 if (hw->fc.requested_mode == txgbe_fc_default)
109 hw->fc.requested_mode = txgbe_fc_full;
112 * Set up the 1G and 10G flow control advertisement registers so the
113 * HW will be able to do fc autoneg once the cable is plugged in. If
114 * we link at 10G, the 1G advertisement is harmless and vice versa.
116 switch (hw->phy.media_type) {
117 case txgbe_media_type_backplane:
118 /* some MAC's need RMW protection on AUTOC */
119 err = hw->mac.prot_autoc_read(hw, &locked, ®_bp);
123 /* fall through - only backplane uses autoc */
124 case txgbe_media_type_fiber_qsfp:
125 case txgbe_media_type_fiber:
126 case txgbe_media_type_copper:
127 hw->phy.read_reg(hw, TXGBE_MD_AUTO_NEG_ADVT,
128 TXGBE_MD_DEV_AUTO_NEG, ®_cu);
135 * The possible values of fc.requested_mode are:
136 * 0: Flow control is completely disabled
137 * 1: Rx flow control is enabled (we can receive pause frames,
138 * but not send pause frames).
139 * 2: Tx flow control is enabled (we can send pause frames but
140 * we do not support receiving pause frames).
141 * 3: Both Rx and Tx flow control (symmetric) are enabled.
144 switch (hw->fc.requested_mode) {
146 /* Flow control completely disabled by software override. */
147 reg &= ~(SR_MII_MMD_AN_ADV_PAUSE_SYM |
148 SR_MII_MMD_AN_ADV_PAUSE_ASM);
149 if (hw->phy.media_type == txgbe_media_type_backplane)
150 reg_bp &= ~(TXGBE_AUTOC_SYM_PAUSE |
151 TXGBE_AUTOC_ASM_PAUSE);
152 else if (hw->phy.media_type == txgbe_media_type_copper)
153 reg_cu &= ~(TXGBE_TAF_SYM_PAUSE | TXGBE_TAF_ASM_PAUSE);
155 case txgbe_fc_tx_pause:
157 * Tx Flow control is enabled, and Rx Flow control is
158 * disabled by software override.
160 reg |= SR_MII_MMD_AN_ADV_PAUSE_ASM;
161 reg &= ~SR_MII_MMD_AN_ADV_PAUSE_SYM;
162 if (hw->phy.media_type == txgbe_media_type_backplane) {
163 reg_bp |= TXGBE_AUTOC_ASM_PAUSE;
164 reg_bp &= ~TXGBE_AUTOC_SYM_PAUSE;
165 } else if (hw->phy.media_type == txgbe_media_type_copper) {
166 reg_cu |= TXGBE_TAF_ASM_PAUSE;
167 reg_cu &= ~TXGBE_TAF_SYM_PAUSE;
169 reg |= SR_MII_MMD_AN_ADV_PAUSE_ASM;
170 reg_bp |= SR_AN_MMD_ADV_REG1_PAUSE_ASM;
172 case txgbe_fc_rx_pause:
174 * Rx Flow control is enabled and Tx Flow control is
175 * disabled by software override. Since there really
176 * isn't a way to advertise that we are capable of RX
177 * Pause ONLY, we will advertise that we support both
178 * symmetric and asymmetric Rx PAUSE, as such we fall
179 * through to the fc_full statement. Later, we will
180 * disable the adapter's ability to send PAUSE frames.
183 /* Flow control (both Rx and Tx) is enabled by SW override. */
184 reg |= SR_MII_MMD_AN_ADV_PAUSE_SYM |
185 SR_MII_MMD_AN_ADV_PAUSE_ASM;
186 if (hw->phy.media_type == txgbe_media_type_backplane)
187 reg_bp |= TXGBE_AUTOC_SYM_PAUSE |
188 TXGBE_AUTOC_ASM_PAUSE;
189 else if (hw->phy.media_type == txgbe_media_type_copper)
190 reg_cu |= TXGBE_TAF_SYM_PAUSE | TXGBE_TAF_ASM_PAUSE;
191 reg |= SR_MII_MMD_AN_ADV_PAUSE_SYM |
192 SR_MII_MMD_AN_ADV_PAUSE_ASM;
193 reg_bp |= SR_AN_MMD_ADV_REG1_PAUSE_SYM |
194 SR_AN_MMD_ADV_REG1_PAUSE_ASM;
197 DEBUGOUT("Flow control param set incorrectly\n");
198 err = TXGBE_ERR_CONFIG;
203 * Enable auto-negotiation between the MAC & PHY;
204 * the MAC will advertise clause 37 flow control.
206 value = rd32_epcs(hw, SR_MII_MMD_AN_ADV);
207 value = (value & ~(SR_MII_MMD_AN_ADV_PAUSE_ASM |
208 SR_MII_MMD_AN_ADV_PAUSE_SYM)) | reg;
209 wr32_epcs(hw, SR_MII_MMD_AN_ADV, value);
212 * AUTOC restart handles negotiation of 1G and 10G on backplane
213 * and copper. There is no need to set the PCS1GCTL register.
216 if (hw->phy.media_type == txgbe_media_type_backplane) {
217 value = rd32_epcs(hw, SR_AN_MMD_ADV_REG1);
218 value = (value & ~(SR_AN_MMD_ADV_REG1_PAUSE_ASM |
219 SR_AN_MMD_ADV_REG1_PAUSE_SYM)) |
221 wr32_epcs(hw, SR_AN_MMD_ADV_REG1, value);
222 } else if ((hw->phy.media_type == txgbe_media_type_copper) &&
223 (txgbe_device_supports_autoneg_fc(hw))) {
224 hw->phy.write_reg(hw, TXGBE_MD_AUTO_NEG_ADVT,
225 TXGBE_MD_DEV_AUTO_NEG, reg_cu);
228 DEBUGOUT("Set up FC; reg = 0x%08X\n", reg);
234 * txgbe_start_hw - Prepare hardware for Tx/Rx
235 * @hw: pointer to hardware structure
237 * Starts the hardware by filling the bus info structure and media type, clears
238 * all on chip counters, initializes receive address registers, multicast
239 * table, VLAN filter table, calls routine to set up link and flow control
240 * settings, and leaves transmit and receive units disabled and uninitialized
242 s32 txgbe_start_hw(struct txgbe_hw *hw)
247 DEBUGFUNC("txgbe_start_hw");
249 /* Set the media type */
250 hw->phy.media_type = hw->phy.get_media_type(hw);
252 /* Clear the VLAN filter table */
253 hw->mac.clear_vfta(hw);
255 /* Clear statistics registers */
256 hw->mac.clear_hw_cntrs(hw);
258 /* Setup flow control */
259 err = txgbe_setup_fc(hw);
260 if (err != 0 && err != TXGBE_NOT_IMPLEMENTED) {
261 DEBUGOUT("Flow control setup failed, returning %d\n", err);
265 /* Cache bit indicating need for crosstalk fix */
266 switch (hw->mac.type) {
267 case txgbe_mac_raptor:
268 hw->mac.get_device_caps(hw, &device_caps);
269 if (device_caps & TXGBE_DEVICE_CAPS_NO_CROSSTALK_WR)
270 hw->need_crosstalk_fix = false;
272 hw->need_crosstalk_fix = true;
275 hw->need_crosstalk_fix = false;
279 /* Clear adapter stopped flag */
280 hw->adapter_stopped = false;
286 * txgbe_start_hw_gen2 - Init sequence for common device family
287 * @hw: pointer to hw structure
289 * Performs the init sequence common to the second generation
292 s32 txgbe_start_hw_gen2(struct txgbe_hw *hw)
296 /* Clear the rate limiters */
297 for (i = 0; i < hw->mac.max_tx_queues; i++) {
298 wr32(hw, TXGBE_ARBPOOLIDX, i);
299 wr32(hw, TXGBE_ARBTXRATE, 0);
303 /* We need to run link autotry after the driver loads */
304 hw->mac.autotry_restart = true;
310 * txgbe_init_hw - Generic hardware initialization
311 * @hw: pointer to hardware structure
313 * Initialize the hardware by resetting the hardware, filling the bus info
314 * structure and media type, clears all on chip counters, initializes receive
315 * address registers, multicast table, VLAN filter table, calls routine to set
316 * up link and flow control settings, and leaves transmit and receive units
317 * disabled and uninitialized
319 s32 txgbe_init_hw(struct txgbe_hw *hw)
323 DEBUGFUNC("txgbe_init_hw");
325 /* Reset the hardware */
326 status = hw->mac.reset_hw(hw);
327 if (status == 0 || status == TXGBE_ERR_SFP_NOT_PRESENT) {
329 status = hw->mac.start_hw(hw);
333 DEBUGOUT("Failed to initialize HW, STATUS = %d\n", status);
339 * txgbe_clear_hw_cntrs - Generic clear hardware counters
340 * @hw: pointer to hardware structure
342 * Clears all hardware statistics counters by reading them from the hardware
343 * Statistics counters are clear on read.
345 s32 txgbe_clear_hw_cntrs(struct txgbe_hw *hw)
349 DEBUGFUNC("txgbe_clear_hw_cntrs");
352 /* don't write clear queue stats */
353 for (i = 0; i < TXGBE_MAX_QP; i++) {
354 hw->qp_last[i].rx_qp_packets = 0;
355 hw->qp_last[i].tx_qp_packets = 0;
356 hw->qp_last[i].rx_qp_bytes = 0;
357 hw->qp_last[i].tx_qp_bytes = 0;
358 hw->qp_last[i].rx_qp_mc_packets = 0;
362 for (i = 0; i < TXGBE_MAX_UP; i++) {
363 rd32(hw, TXGBE_PBRXUPXON(i));
364 rd32(hw, TXGBE_PBRXUPXOFF(i));
365 rd32(hw, TXGBE_PBTXUPXON(i));
366 rd32(hw, TXGBE_PBTXUPXOFF(i));
367 rd32(hw, TXGBE_PBTXUPOFF(i));
369 rd32(hw, TXGBE_PBRXMISS(i));
371 rd32(hw, TXGBE_PBRXLNKXON);
372 rd32(hw, TXGBE_PBRXLNKXOFF);
373 rd32(hw, TXGBE_PBTXLNKXON);
374 rd32(hw, TXGBE_PBTXLNKXOFF);
377 rd32(hw, TXGBE_DMARXPKT);
378 rd32(hw, TXGBE_DMATXPKT);
380 rd64(hw, TXGBE_DMARXOCTL);
381 rd64(hw, TXGBE_DMATXOCTL);
384 rd64(hw, TXGBE_MACRXERRCRCL);
385 rd64(hw, TXGBE_MACRXMPKTL);
386 rd64(hw, TXGBE_MACTXMPKTL);
388 rd64(hw, TXGBE_MACRXPKTL);
389 rd64(hw, TXGBE_MACTXPKTL);
390 rd64(hw, TXGBE_MACRXGBOCTL);
392 rd64(hw, TXGBE_MACRXOCTL);
393 rd32(hw, TXGBE_MACTXOCTL);
395 rd64(hw, TXGBE_MACRX1TO64L);
396 rd64(hw, TXGBE_MACRX65TO127L);
397 rd64(hw, TXGBE_MACRX128TO255L);
398 rd64(hw, TXGBE_MACRX256TO511L);
399 rd64(hw, TXGBE_MACRX512TO1023L);
400 rd64(hw, TXGBE_MACRX1024TOMAXL);
401 rd64(hw, TXGBE_MACTX1TO64L);
402 rd64(hw, TXGBE_MACTX65TO127L);
403 rd64(hw, TXGBE_MACTX128TO255L);
404 rd64(hw, TXGBE_MACTX256TO511L);
405 rd64(hw, TXGBE_MACTX512TO1023L);
406 rd64(hw, TXGBE_MACTX1024TOMAXL);
408 rd64(hw, TXGBE_MACRXERRLENL);
409 rd32(hw, TXGBE_MACRXOVERSIZE);
410 rd32(hw, TXGBE_MACRXJABBER);
413 rd32(hw, TXGBE_FCOECRC);
414 rd32(hw, TXGBE_FCOELAST);
415 rd32(hw, TXGBE_FCOERPDC);
416 rd32(hw, TXGBE_FCOEPRC);
417 rd32(hw, TXGBE_FCOEPTC);
418 rd32(hw, TXGBE_FCOEDWRC);
419 rd32(hw, TXGBE_FCOEDWTC);
421 /* Flow Director Stats */
422 rd32(hw, TXGBE_FDIRMATCH);
423 rd32(hw, TXGBE_FDIRMISS);
424 rd32(hw, TXGBE_FDIRUSED);
425 rd32(hw, TXGBE_FDIRUSED);
426 rd32(hw, TXGBE_FDIRFAIL);
427 rd32(hw, TXGBE_FDIRFAIL);
430 rd32(hw, TXGBE_LSECTX_UTPKT);
431 rd32(hw, TXGBE_LSECTX_ENCPKT);
432 rd32(hw, TXGBE_LSECTX_PROTPKT);
433 rd32(hw, TXGBE_LSECTX_ENCOCT);
434 rd32(hw, TXGBE_LSECTX_PROTOCT);
435 rd32(hw, TXGBE_LSECRX_UTPKT);
436 rd32(hw, TXGBE_LSECRX_BTPKT);
437 rd32(hw, TXGBE_LSECRX_NOSCIPKT);
438 rd32(hw, TXGBE_LSECRX_UNSCIPKT);
439 rd32(hw, TXGBE_LSECRX_DECOCT);
440 rd32(hw, TXGBE_LSECRX_VLDOCT);
441 rd32(hw, TXGBE_LSECRX_UNCHKPKT);
442 rd32(hw, TXGBE_LSECRX_DLYPKT);
443 rd32(hw, TXGBE_LSECRX_LATEPKT);
444 for (i = 0; i < 2; i++) {
445 rd32(hw, TXGBE_LSECRX_OKPKT(i));
446 rd32(hw, TXGBE_LSECRX_INVPKT(i));
447 rd32(hw, TXGBE_LSECRX_BADPKT(i));
449 rd32(hw, TXGBE_LSECRX_INVSAPKT);
450 rd32(hw, TXGBE_LSECRX_BADSAPKT);
456 * txgbe_get_mac_addr - Generic get MAC address
457 * @hw: pointer to hardware structure
458 * @mac_addr: Adapter MAC address
460 * Reads the adapter's MAC address from first Receive Address Register (RAR0)
461 * A reset of the adapter must be performed prior to calling this function
462 * in order for the MAC address to have been loaded from the EEPROM into RAR0
464 s32 txgbe_get_mac_addr(struct txgbe_hw *hw, u8 *mac_addr)
470 DEBUGFUNC("txgbe_get_mac_addr");
472 wr32(hw, TXGBE_ETHADDRIDX, 0);
473 rar_high = rd32(hw, TXGBE_ETHADDRH);
474 rar_low = rd32(hw, TXGBE_ETHADDRL);
476 for (i = 0; i < 2; i++)
477 mac_addr[i] = (u8)(rar_high >> (1 - i) * 8);
479 for (i = 0; i < 4; i++)
480 mac_addr[i + 2] = (u8)(rar_low >> (3 - i) * 8);
486 * txgbe_set_lan_id_multi_port - Set LAN id for PCIe multiple port devices
487 * @hw: pointer to the HW structure
489 * Determines the LAN function id by reading memory-mapped registers and swaps
490 * the port value if requested, and set MAC instance for devices.
492 void txgbe_set_lan_id_multi_port(struct txgbe_hw *hw)
494 struct txgbe_bus_info *bus = &hw->bus;
497 DEBUGFUNC("txgbe_set_lan_id_multi_port_pcie");
499 reg = rd32(hw, TXGBE_PORTSTAT);
500 bus->lan_id = TXGBE_PORTSTAT_ID(reg);
502 /* check for single port */
503 reg = rd32(hw, TXGBE_PWR);
504 if (TXGBE_PWR_LANID(reg) == TXGBE_PWR_LANID_SWAP)
507 bus->func = bus->lan_id;
511 * txgbe_stop_hw - Generic stop Tx/Rx units
512 * @hw: pointer to hardware structure
514 * Sets the adapter_stopped flag within txgbe_hw struct. Clears interrupts,
515 * disables transmit and receive units. The adapter_stopped flag is used by
516 * the shared code and drivers to determine if the adapter is in a stopped
517 * state and should not touch the hardware.
519 s32 txgbe_stop_hw(struct txgbe_hw *hw)
524 DEBUGFUNC("txgbe_stop_hw");
527 * Set the adapter_stopped flag so other driver functions stop touching
530 hw->adapter_stopped = true;
532 /* Disable the receive unit */
533 txgbe_disable_rx(hw);
535 /* Clear interrupt mask to stop interrupts from being generated */
536 wr32(hw, TXGBE_IENMISC, 0);
537 wr32(hw, TXGBE_IMS(0), TXGBE_IMS_MASK);
538 wr32(hw, TXGBE_IMS(1), TXGBE_IMS_MASK);
540 /* Clear any pending interrupts, flush previous writes */
541 wr32(hw, TXGBE_ICRMISC, TXGBE_ICRMISC_MASK);
542 wr32(hw, TXGBE_ICR(0), TXGBE_ICR_MASK);
543 wr32(hw, TXGBE_ICR(1), TXGBE_ICR_MASK);
545 /* Disable the transmit unit. Each queue must be disabled. */
546 for (i = 0; i < hw->mac.max_tx_queues; i++)
547 wr32(hw, TXGBE_TXCFG(i), TXGBE_TXCFG_FLUSH);
549 /* Disable the receive unit by stopping each queue */
550 for (i = 0; i < hw->mac.max_rx_queues; i++) {
551 reg_val = rd32(hw, TXGBE_RXCFG(i));
552 reg_val &= ~TXGBE_RXCFG_ENA;
553 wr32(hw, TXGBE_RXCFG(i), reg_val);
556 /* flush all queues disables */
564 * txgbe_validate_mac_addr - Validate MAC address
565 * @mac_addr: pointer to MAC address.
567 * Tests a MAC address to ensure it is a valid Individual Address.
569 s32 txgbe_validate_mac_addr(u8 *mac_addr)
573 DEBUGFUNC("txgbe_validate_mac_addr");
575 /* Make sure it is not a multicast address */
576 if (TXGBE_IS_MULTICAST(mac_addr)) {
577 status = TXGBE_ERR_INVALID_MAC_ADDR;
578 /* Not a broadcast address */
579 } else if (TXGBE_IS_BROADCAST(mac_addr)) {
580 status = TXGBE_ERR_INVALID_MAC_ADDR;
581 /* Reject the zero address */
582 } else if (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 &&
583 mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0) {
584 status = TXGBE_ERR_INVALID_MAC_ADDR;
590 * txgbe_set_rar - Set Rx address register
591 * @hw: pointer to hardware structure
592 * @index: Receive address register to write
593 * @addr: Address to put into receive address register
594 * @vmdq: VMDq "set" or "pool" index
595 * @enable_addr: set flag that address is active
597 * Puts an ethernet address into a receive address register.
599 s32 txgbe_set_rar(struct txgbe_hw *hw, u32 index, u8 *addr, u32 vmdq,
602 u32 rar_low, rar_high;
603 u32 rar_entries = hw->mac.num_rar_entries;
605 DEBUGFUNC("txgbe_set_rar");
607 /* Make sure we are using a valid rar index range */
608 if (index >= rar_entries) {
609 DEBUGOUT("RAR index %d is out of range.\n", index);
610 return TXGBE_ERR_INVALID_ARGUMENT;
613 /* setup VMDq pool selection before this RAR gets enabled */
614 hw->mac.set_vmdq(hw, index, vmdq);
617 * HW expects these in little endian so we reverse the byte
618 * order from network order (big endian) to little endian
620 rar_low = TXGBE_ETHADDRL_AD0(addr[5]) |
621 TXGBE_ETHADDRL_AD1(addr[4]) |
622 TXGBE_ETHADDRL_AD2(addr[3]) |
623 TXGBE_ETHADDRL_AD3(addr[2]);
625 * Some parts put the VMDq setting in the extra RAH bits,
626 * so save everything except the lower 16 bits that hold part
627 * of the address and the address valid bit.
629 rar_high = rd32(hw, TXGBE_ETHADDRH);
630 rar_high &= ~TXGBE_ETHADDRH_AD_MASK;
631 rar_high |= (TXGBE_ETHADDRH_AD4(addr[1]) |
632 TXGBE_ETHADDRH_AD5(addr[0]));
634 rar_high &= ~TXGBE_ETHADDRH_VLD;
635 if (enable_addr != 0)
636 rar_high |= TXGBE_ETHADDRH_VLD;
638 wr32(hw, TXGBE_ETHADDRIDX, index);
639 wr32(hw, TXGBE_ETHADDRL, rar_low);
640 wr32(hw, TXGBE_ETHADDRH, rar_high);
646 * txgbe_clear_rar - Remove Rx address register
647 * @hw: pointer to hardware structure
648 * @index: Receive address register to write
650 * Clears an ethernet address from a receive address register.
652 s32 txgbe_clear_rar(struct txgbe_hw *hw, u32 index)
655 u32 rar_entries = hw->mac.num_rar_entries;
657 DEBUGFUNC("txgbe_clear_rar");
659 /* Make sure we are using a valid rar index range */
660 if (index >= rar_entries) {
661 DEBUGOUT("RAR index %d is out of range.\n", index);
662 return TXGBE_ERR_INVALID_ARGUMENT;
666 * Some parts put the VMDq setting in the extra RAH bits,
667 * so save everything except the lower 16 bits that hold part
668 * of the address and the address valid bit.
670 wr32(hw, TXGBE_ETHADDRIDX, index);
671 rar_high = rd32(hw, TXGBE_ETHADDRH);
672 rar_high &= ~(TXGBE_ETHADDRH_AD_MASK | TXGBE_ETHADDRH_VLD);
674 wr32(hw, TXGBE_ETHADDRL, 0);
675 wr32(hw, TXGBE_ETHADDRH, rar_high);
677 /* clear VMDq pool/queue selection for this RAR */
678 hw->mac.clear_vmdq(hw, index, BIT_MASK32);
684 * txgbe_init_rx_addrs - Initializes receive address filters.
685 * @hw: pointer to hardware structure
687 * Places the MAC address in receive address register 0 and clears the rest
688 * of the receive address registers. Clears the multicast table. Assumes
689 * the receiver is in reset when the routine is called.
691 s32 txgbe_init_rx_addrs(struct txgbe_hw *hw)
695 u32 rar_entries = hw->mac.num_rar_entries;
697 DEBUGFUNC("txgbe_init_rx_addrs");
700 * If the current mac address is valid, assume it is a software override
701 * to the permanent address.
702 * Otherwise, use the permanent address from the eeprom.
704 if (txgbe_validate_mac_addr(hw->mac.addr) ==
705 TXGBE_ERR_INVALID_MAC_ADDR) {
706 /* Get the MAC address from the RAR0 for later reference */
707 hw->mac.get_mac_addr(hw, hw->mac.addr);
709 DEBUGOUT(" Keeping Current RAR0 Addr =%.2X %.2X %.2X ",
710 hw->mac.addr[0], hw->mac.addr[1],
712 DEBUGOUT("%.2X %.2X %.2X\n", hw->mac.addr[3],
713 hw->mac.addr[4], hw->mac.addr[5]);
715 /* Setup the receive address. */
716 DEBUGOUT("Overriding MAC Address in RAR[0]\n");
717 DEBUGOUT(" New MAC Addr =%.2X %.2X %.2X ",
718 hw->mac.addr[0], hw->mac.addr[1],
720 DEBUGOUT("%.2X %.2X %.2X\n", hw->mac.addr[3],
721 hw->mac.addr[4], hw->mac.addr[5]);
723 hw->mac.set_rar(hw, 0, hw->mac.addr, 0, true);
726 /* clear VMDq pool/queue selection for RAR 0 */
727 hw->mac.clear_vmdq(hw, 0, BIT_MASK32);
729 hw->addr_ctrl.overflow_promisc = 0;
731 hw->addr_ctrl.rar_used_count = 1;
733 /* Zero out the other receive addresses. */
734 DEBUGOUT("Clearing RAR[1-%d]\n", rar_entries - 1);
735 for (i = 1; i < rar_entries; i++) {
736 wr32(hw, TXGBE_ETHADDRIDX, i);
737 wr32(hw, TXGBE_ETHADDRL, 0);
738 wr32(hw, TXGBE_ETHADDRH, 0);
742 hw->addr_ctrl.mta_in_use = 0;
743 psrctl = rd32(hw, TXGBE_PSRCTL);
744 psrctl &= ~(TXGBE_PSRCTL_ADHF12_MASK | TXGBE_PSRCTL_MCHFENA);
745 psrctl |= TXGBE_PSRCTL_ADHF12(hw->mac.mc_filter_type);
746 wr32(hw, TXGBE_PSRCTL, psrctl);
748 DEBUGOUT(" Clearing MTA\n");
749 for (i = 0; i < hw->mac.mcft_size; i++)
750 wr32(hw, TXGBE_MCADDRTBL(i), 0);
752 txgbe_init_uta_tables(hw);
758 * txgbe_mta_vector - Determines bit-vector in multicast table to set
759 * @hw: pointer to hardware structure
760 * @mc_addr: the multicast address
762 * Extracts the 12 bits, from a multicast address, to determine which
763 * bit-vector to set in the multicast table. The hardware uses 12 bits, from
764 * incoming rx multicast addresses, to determine the bit-vector to check in
765 * the MTA. Which of the 4 combination, of 12-bits, the hardware uses is set
766 * by the MO field of the PSRCTRL. The MO field is set during initialization
769 static s32 txgbe_mta_vector(struct txgbe_hw *hw, u8 *mc_addr)
773 DEBUGFUNC("txgbe_mta_vector");
775 switch (hw->mac.mc_filter_type) {
776 case 0: /* use bits [47:36] of the address */
777 vector = ((mc_addr[4] >> 4) | (((u16)mc_addr[5]) << 4));
779 case 1: /* use bits [46:35] of the address */
780 vector = ((mc_addr[4] >> 3) | (((u16)mc_addr[5]) << 5));
782 case 2: /* use bits [45:34] of the address */
783 vector = ((mc_addr[4] >> 2) | (((u16)mc_addr[5]) << 6));
785 case 3: /* use bits [43:32] of the address */
786 vector = ((mc_addr[4]) | (((u16)mc_addr[5]) << 8));
788 default: /* Invalid mc_filter_type */
789 DEBUGOUT("MC filter type param set incorrectly\n");
794 /* vector can only be 12-bits or boundary will be exceeded */
800 * txgbe_set_mta - Set bit-vector in multicast table
801 * @hw: pointer to hardware structure
802 * @mc_addr: Multicast address
804 * Sets the bit-vector in the multicast table.
806 void txgbe_set_mta(struct txgbe_hw *hw, u8 *mc_addr)
812 DEBUGFUNC("txgbe_set_mta");
814 hw->addr_ctrl.mta_in_use++;
816 vector = txgbe_mta_vector(hw, mc_addr);
817 DEBUGOUT(" bit-vector = 0x%03X\n", vector);
820 * The MTA is a register array of 128 32-bit registers. It is treated
821 * like an array of 4096 bits. We want to set bit
822 * BitArray[vector_value]. So we figure out what register the bit is
823 * in, read it, OR in the new bit, then write back the new value. The
824 * register is determined by the upper 7 bits of the vector value and
825 * the bit within that register are determined by the lower 5 bits of
828 vector_reg = (vector >> 5) & 0x7F;
829 vector_bit = vector & 0x1F;
830 hw->mac.mta_shadow[vector_reg] |= (1 << vector_bit);
834 * txgbe_update_mc_addr_list - Updates MAC list of multicast addresses
835 * @hw: pointer to hardware structure
836 * @mc_addr_list: the list of new multicast addresses
837 * @mc_addr_count: number of addresses
838 * @next: iterator function to walk the multicast address list
839 * @clear: flag, when set clears the table beforehand
841 * When the clear flag is set, the given list replaces any existing list.
842 * Hashes the given addresses into the multicast table.
844 s32 txgbe_update_mc_addr_list(struct txgbe_hw *hw, u8 *mc_addr_list,
845 u32 mc_addr_count, txgbe_mc_addr_itr next,
851 DEBUGFUNC("txgbe_update_mc_addr_list");
854 * Set the new number of MC addresses that we are being requested to
857 hw->addr_ctrl.num_mc_addrs = mc_addr_count;
858 hw->addr_ctrl.mta_in_use = 0;
860 /* Clear mta_shadow */
862 DEBUGOUT(" Clearing MTA\n");
863 memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow));
866 /* Update mta_shadow */
867 for (i = 0; i < mc_addr_count; i++) {
868 DEBUGOUT(" Adding the multicast addresses:\n");
869 txgbe_set_mta(hw, next(hw, &mc_addr_list, &vmdq));
873 for (i = 0; i < hw->mac.mcft_size; i++)
874 wr32a(hw, TXGBE_MCADDRTBL(0), i,
875 hw->mac.mta_shadow[i]);
877 if (hw->addr_ctrl.mta_in_use > 0) {
878 u32 psrctl = rd32(hw, TXGBE_PSRCTL);
879 psrctl &= ~(TXGBE_PSRCTL_ADHF12_MASK | TXGBE_PSRCTL_MCHFENA);
880 psrctl |= TXGBE_PSRCTL_MCHFENA |
881 TXGBE_PSRCTL_ADHF12(hw->mac.mc_filter_type);
882 wr32(hw, TXGBE_PSRCTL, psrctl);
885 DEBUGOUT("txgbe update mc addr list complete\n");
890 * txgbe_fc_enable - Enable flow control
891 * @hw: pointer to hardware structure
893 * Enable flow control according to the current settings.
895 s32 txgbe_fc_enable(struct txgbe_hw *hw)
898 u32 mflcn_reg, fccfg_reg;
903 DEBUGFUNC("txgbe_fc_enable");
905 /* Validate the water mark configuration */
906 if (!hw->fc.pause_time) {
907 err = TXGBE_ERR_INVALID_LINK_SETTINGS;
911 /* Low water mark of zero causes XOFF floods */
912 for (i = 0; i < TXGBE_DCB_TC_MAX; i++) {
913 if ((hw->fc.current_mode & txgbe_fc_tx_pause) &&
914 hw->fc.high_water[i]) {
915 if (!hw->fc.low_water[i] ||
916 hw->fc.low_water[i] >= hw->fc.high_water[i]) {
917 DEBUGOUT("Invalid water mark configuration\n");
918 err = TXGBE_ERR_INVALID_LINK_SETTINGS;
924 /* Negotiate the fc mode to use */
925 hw->mac.fc_autoneg(hw);
927 /* Disable any previous flow control settings */
928 mflcn_reg = rd32(hw, TXGBE_RXFCCFG);
929 mflcn_reg &= ~(TXGBE_RXFCCFG_FC | TXGBE_RXFCCFG_PFC);
931 fccfg_reg = rd32(hw, TXGBE_TXFCCFG);
932 fccfg_reg &= ~(TXGBE_TXFCCFG_FC | TXGBE_TXFCCFG_PFC);
935 * The possible values of fc.current_mode are:
936 * 0: Flow control is completely disabled
937 * 1: Rx flow control is enabled (we can receive pause frames,
938 * but not send pause frames).
939 * 2: Tx flow control is enabled (we can send pause frames but
940 * we do not support receiving pause frames).
941 * 3: Both Rx and Tx flow control (symmetric) are enabled.
944 switch (hw->fc.current_mode) {
947 * Flow control is disabled by software override or autoneg.
948 * The code below will actually disable it in the HW.
951 case txgbe_fc_rx_pause:
953 * Rx Flow control is enabled and Tx Flow control is
954 * disabled by software override. Since there really
955 * isn't a way to advertise that we are capable of RX
956 * Pause ONLY, we will advertise that we support both
957 * symmetric and asymmetric Rx PAUSE. Later, we will
958 * disable the adapter's ability to send PAUSE frames.
960 mflcn_reg |= TXGBE_RXFCCFG_FC;
962 case txgbe_fc_tx_pause:
964 * Tx Flow control is enabled, and Rx Flow control is
965 * disabled by software override.
967 fccfg_reg |= TXGBE_TXFCCFG_FC;
970 /* Flow control (both Rx and Tx) is enabled by SW override. */
971 mflcn_reg |= TXGBE_RXFCCFG_FC;
972 fccfg_reg |= TXGBE_TXFCCFG_FC;
975 DEBUGOUT("Flow control param set incorrectly\n");
976 err = TXGBE_ERR_CONFIG;
980 /* Set 802.3x based flow control settings. */
981 wr32(hw, TXGBE_RXFCCFG, mflcn_reg);
982 wr32(hw, TXGBE_TXFCCFG, fccfg_reg);
984 /* Set up and enable Rx high/low water mark thresholds, enable XON. */
985 for (i = 0; i < TXGBE_DCB_TC_MAX; i++) {
986 if ((hw->fc.current_mode & txgbe_fc_tx_pause) &&
987 hw->fc.high_water[i]) {
988 fcrtl = TXGBE_FCWTRLO_TH(hw->fc.low_water[i]) |
990 fcrth = TXGBE_FCWTRHI_TH(hw->fc.high_water[i]) |
994 * In order to prevent Tx hangs when the internal Tx
995 * switch is enabled we must set the high water mark
996 * to the Rx packet buffer size - 24KB. This allows
997 * the Tx switch to function even under heavy Rx
1001 fcrth = rd32(hw, TXGBE_PBRXSIZE(i)) - 24576;
1003 wr32(hw, TXGBE_FCWTRLO(i), fcrtl);
1004 wr32(hw, TXGBE_FCWTRHI(i), fcrth);
1007 /* Configure pause time (2 TCs per register) */
1008 pause_time = TXGBE_RXFCFSH_TIME(hw->fc.pause_time);
1009 for (i = 0; i < (TXGBE_DCB_TC_MAX / 2); i++)
1010 wr32(hw, TXGBE_FCXOFFTM(i), pause_time * 0x00010001);
1012 /* Configure flow control refresh threshold value */
1013 wr32(hw, TXGBE_RXFCRFSH, hw->fc.pause_time / 2);
1020 * txgbe_negotiate_fc - Negotiate flow control
1021 * @hw: pointer to hardware structure
1022 * @adv_reg: flow control advertised settings
1023 * @lp_reg: link partner's flow control settings
1024 * @adv_sym: symmetric pause bit in advertisement
1025 * @adv_asm: asymmetric pause bit in advertisement
1026 * @lp_sym: symmetric pause bit in link partner advertisement
1027 * @lp_asm: asymmetric pause bit in link partner advertisement
1029 * Find the intersection between advertised settings and link partner's
1030 * advertised settings
1032 s32 txgbe_negotiate_fc(struct txgbe_hw *hw, u32 adv_reg, u32 lp_reg,
1033 u32 adv_sym, u32 adv_asm, u32 lp_sym, u32 lp_asm)
1035 if ((!(adv_reg)) || (!(lp_reg))) {
1036 DEBUGOUT("Local or link partner's advertised flow control "
1037 "settings are NULL. Local: %x, link partner: %x\n",
1039 return TXGBE_ERR_FC_NOT_NEGOTIATED;
1042 if ((adv_reg & adv_sym) && (lp_reg & lp_sym)) {
1044 * Now we need to check if the user selected Rx ONLY
1045 * of pause frames. In this case, we had to advertise
1046 * FULL flow control because we could not advertise RX
1047 * ONLY. Hence, we must now check to see if we need to
1048 * turn OFF the TRANSMISSION of PAUSE frames.
1050 if (hw->fc.requested_mode == txgbe_fc_full) {
1051 hw->fc.current_mode = txgbe_fc_full;
1052 DEBUGOUT("Flow Control = FULL.\n");
1054 hw->fc.current_mode = txgbe_fc_rx_pause;
1055 DEBUGOUT("Flow Control=RX PAUSE frames only\n");
1057 } else if (!(adv_reg & adv_sym) && (adv_reg & adv_asm) &&
1058 (lp_reg & lp_sym) && (lp_reg & lp_asm)) {
1059 hw->fc.current_mode = txgbe_fc_tx_pause;
1060 DEBUGOUT("Flow Control = TX PAUSE frames only.\n");
1061 } else if ((adv_reg & adv_sym) && (adv_reg & adv_asm) &&
1062 !(lp_reg & lp_sym) && (lp_reg & lp_asm)) {
1063 hw->fc.current_mode = txgbe_fc_rx_pause;
1064 DEBUGOUT("Flow Control = RX PAUSE frames only.\n");
1066 hw->fc.current_mode = txgbe_fc_none;
1067 DEBUGOUT("Flow Control = NONE.\n");
1073 * txgbe_fc_autoneg_fiber - Enable flow control on 1 gig fiber
1074 * @hw: pointer to hardware structure
1076 * Enable flow control according on 1 gig fiber.
1078 STATIC s32 txgbe_fc_autoneg_fiber(struct txgbe_hw *hw)
1080 u32 pcs_anadv_reg, pcs_lpab_reg;
1081 s32 err = TXGBE_ERR_FC_NOT_NEGOTIATED;
1084 * On multispeed fiber at 1g, bail out if
1085 * - link is up but AN did not complete, or if
1086 * - link is up and AN completed but timed out
1089 pcs_anadv_reg = rd32_epcs(hw, SR_MII_MMD_AN_ADV);
1090 pcs_lpab_reg = rd32_epcs(hw, SR_MII_MMD_LP_BABL);
1092 err = txgbe_negotiate_fc(hw, pcs_anadv_reg,
1094 SR_MII_MMD_AN_ADV_PAUSE_SYM,
1095 SR_MII_MMD_AN_ADV_PAUSE_ASM,
1096 SR_MII_MMD_AN_ADV_PAUSE_SYM,
1097 SR_MII_MMD_AN_ADV_PAUSE_ASM);
1103 * txgbe_fc_autoneg_backplane - Enable flow control IEEE clause 37
1104 * @hw: pointer to hardware structure
1106 * Enable flow control according to IEEE clause 37.
1108 STATIC s32 txgbe_fc_autoneg_backplane(struct txgbe_hw *hw)
1110 u32 anlp1_reg, autoc_reg;
1111 s32 err = TXGBE_ERR_FC_NOT_NEGOTIATED;
1114 * Read the 10g AN autoc and LP ability registers and resolve
1115 * local flow control settings accordingly
1117 autoc_reg = rd32_epcs(hw, SR_AN_MMD_ADV_REG1);
1118 anlp1_reg = rd32_epcs(hw, SR_AN_MMD_LP_ABL1);
1120 err = txgbe_negotiate_fc(hw, autoc_reg,
1122 SR_AN_MMD_ADV_REG1_PAUSE_SYM,
1123 SR_AN_MMD_ADV_REG1_PAUSE_ASM,
1124 SR_AN_MMD_ADV_REG1_PAUSE_SYM,
1125 SR_AN_MMD_ADV_REG1_PAUSE_ASM);
1131 * txgbe_fc_autoneg_copper - Enable flow control IEEE clause 37
1132 * @hw: pointer to hardware structure
1134 * Enable flow control according to IEEE clause 37.
1136 STATIC s32 txgbe_fc_autoneg_copper(struct txgbe_hw *hw)
1138 u16 technology_ability_reg = 0;
1139 u16 lp_technology_ability_reg = 0;
1141 hw->phy.read_reg(hw, TXGBE_MD_AUTO_NEG_ADVT,
1142 TXGBE_MD_DEV_AUTO_NEG,
1143 &technology_ability_reg);
1144 hw->phy.read_reg(hw, TXGBE_MD_AUTO_NEG_LP,
1145 TXGBE_MD_DEV_AUTO_NEG,
1146 &lp_technology_ability_reg);
1148 return txgbe_negotiate_fc(hw, (u32)technology_ability_reg,
1149 (u32)lp_technology_ability_reg,
1150 TXGBE_TAF_SYM_PAUSE, TXGBE_TAF_ASM_PAUSE,
1151 TXGBE_TAF_SYM_PAUSE, TXGBE_TAF_ASM_PAUSE);
1155 * txgbe_fc_autoneg - Configure flow control
1156 * @hw: pointer to hardware structure
1158 * Compares our advertised flow control capabilities to those advertised by
1159 * our link partner, and determines the proper flow control mode to use.
1161 void txgbe_fc_autoneg(struct txgbe_hw *hw)
1163 s32 err = TXGBE_ERR_FC_NOT_NEGOTIATED;
1167 DEBUGFUNC("txgbe_fc_autoneg");
1170 * AN should have completed when the cable was plugged in.
1171 * Look for reasons to bail out. Bail out if:
1172 * - FC autoneg is disabled, or if
1175 if (hw->fc.disable_fc_autoneg) {
1176 DEBUGOUT("Flow control autoneg is disabled");
1180 hw->mac.check_link(hw, &speed, &link_up, false);
1182 DEBUGOUT("The link is down");
1186 switch (hw->phy.media_type) {
1187 /* Autoneg flow control on fiber adapters */
1188 case txgbe_media_type_fiber_qsfp:
1189 case txgbe_media_type_fiber:
1190 if (speed == TXGBE_LINK_SPEED_1GB_FULL)
1191 err = txgbe_fc_autoneg_fiber(hw);
1194 /* Autoneg flow control on backplane adapters */
1195 case txgbe_media_type_backplane:
1196 err = txgbe_fc_autoneg_backplane(hw);
1199 /* Autoneg flow control on copper adapters */
1200 case txgbe_media_type_copper:
1201 if (txgbe_device_supports_autoneg_fc(hw))
1202 err = txgbe_fc_autoneg_copper(hw);
1211 hw->fc.fc_was_autonegged = true;
1213 hw->fc.fc_was_autonegged = false;
1214 hw->fc.current_mode = hw->fc.requested_mode;
1219 * txgbe_acquire_swfw_sync - Acquire SWFW semaphore
1220 * @hw: pointer to hardware structure
1221 * @mask: Mask to specify which semaphore to acquire
1223 * Acquires the SWFW semaphore through the MNGSEM register for the specified
1224 * function (CSR, PHY0, PHY1, EEPROM, Flash)
1226 s32 txgbe_acquire_swfw_sync(struct txgbe_hw *hw, u32 mask)
1229 u32 swmask = TXGBE_MNGSEM_SW(mask);
1230 u32 fwmask = TXGBE_MNGSEM_FW(mask);
1234 DEBUGFUNC("txgbe_acquire_swfw_sync");
1236 for (i = 0; i < timeout; i++) {
1238 * SW NVM semaphore bit is used for access to all
1239 * SW_FW_SYNC bits (not just NVM)
1241 if (txgbe_get_eeprom_semaphore(hw))
1242 return TXGBE_ERR_SWFW_SYNC;
1244 mngsem = rd32(hw, TXGBE_MNGSEM);
1245 if (mngsem & (fwmask | swmask)) {
1246 /* Resource is currently in use by FW or SW */
1247 txgbe_release_eeprom_semaphore(hw);
1251 wr32(hw, TXGBE_MNGSEM, mngsem);
1252 txgbe_release_eeprom_semaphore(hw);
1257 /* If time expired clear the bits holding the lock and retry */
1258 if (mngsem & (fwmask | swmask))
1259 txgbe_release_swfw_sync(hw, mngsem & (fwmask | swmask));
1262 return TXGBE_ERR_SWFW_SYNC;
1266 * txgbe_release_swfw_sync - Release SWFW semaphore
1267 * @hw: pointer to hardware structure
1268 * @mask: Mask to specify which semaphore to release
1270 * Releases the SWFW semaphore through the MNGSEM register for the specified
1271 * function (CSR, PHY0, PHY1, EEPROM, Flash)
1273 void txgbe_release_swfw_sync(struct txgbe_hw *hw, u32 mask)
1278 DEBUGFUNC("txgbe_release_swfw_sync");
1280 txgbe_get_eeprom_semaphore(hw);
1282 mngsem = rd32(hw, TXGBE_MNGSEM);
1284 wr32(hw, TXGBE_MNGSEM, mngsem);
1286 txgbe_release_eeprom_semaphore(hw);
1290 * txgbe_disable_sec_rx_path - Stops the receive data path
1291 * @hw: pointer to hardware structure
1293 * Stops the receive data path and waits for the HW to internally empty
1294 * the Rx security block
1296 s32 txgbe_disable_sec_rx_path(struct txgbe_hw *hw)
1298 #define TXGBE_MAX_SECRX_POLL 4000
1303 DEBUGFUNC("txgbe_disable_sec_rx_path");
1305 secrxreg = rd32(hw, TXGBE_SECRXCTL);
1306 secrxreg |= TXGBE_SECRXCTL_XDSA;
1307 wr32(hw, TXGBE_SECRXCTL, secrxreg);
1308 for (i = 0; i < TXGBE_MAX_SECRX_POLL; i++) {
1309 secrxreg = rd32(hw, TXGBE_SECRXSTAT);
1310 if (!(secrxreg & TXGBE_SECRXSTAT_RDY))
1311 /* Use interrupt-safe sleep just in case */
1317 /* For informational purposes only */
1318 if (i >= TXGBE_MAX_SECRX_POLL)
1319 DEBUGOUT("Rx unit being enabled before security "
1320 "path fully disabled. Continuing with init.\n");
1326 * txgbe_enable_sec_rx_path - Enables the receive data path
1327 * @hw: pointer to hardware structure
1329 * Enables the receive data path.
1331 s32 txgbe_enable_sec_rx_path(struct txgbe_hw *hw)
1335 DEBUGFUNC("txgbe_enable_sec_rx_path");
1337 secrxreg = rd32(hw, TXGBE_SECRXCTL);
1338 secrxreg &= ~TXGBE_SECRXCTL_XDSA;
1339 wr32(hw, TXGBE_SECRXCTL, secrxreg);
1346 * txgbe_disable_sec_tx_path - Stops the transmit data path
1347 * @hw: pointer to hardware structure
1349 * Stops the transmit data path and waits for the HW to internally empty
1350 * the Tx security block
1352 int txgbe_disable_sec_tx_path(struct txgbe_hw *hw)
1354 #define TXGBE_MAX_SECTX_POLL 40
1359 sectxreg = rd32(hw, TXGBE_SECTXCTL);
1360 sectxreg |= TXGBE_SECTXCTL_XDSA;
1361 wr32(hw, TXGBE_SECTXCTL, sectxreg);
1362 for (i = 0; i < TXGBE_MAX_SECTX_POLL; i++) {
1363 sectxreg = rd32(hw, TXGBE_SECTXSTAT);
1364 if (sectxreg & TXGBE_SECTXSTAT_RDY)
1366 /* Use interrupt-safe sleep just in case */
1370 /* For informational purposes only */
1371 if (i >= TXGBE_MAX_SECTX_POLL)
1372 PMD_DRV_LOG(DEBUG, "Tx unit being enabled before security "
1373 "path fully disabled. Continuing with init.");
1379 * txgbe_enable_sec_tx_path - Enables the transmit data path
1380 * @hw: pointer to hardware structure
1382 * Enables the transmit data path.
1384 int txgbe_enable_sec_tx_path(struct txgbe_hw *hw)
1388 sectxreg = rd32(hw, TXGBE_SECTXCTL);
1389 sectxreg &= ~TXGBE_SECTXCTL_XDSA;
1390 wr32(hw, TXGBE_SECTXCTL, sectxreg);
1397 * txgbe_get_san_mac_addr_offset - Get SAN MAC address offset from the EEPROM
1398 * @hw: pointer to hardware structure
1399 * @san_mac_offset: SAN MAC address offset
1401 * This function will read the EEPROM location for the SAN MAC address
1402 * pointer, and returns the value at that location. This is used in both
1403 * get and set mac_addr routines.
1405 static s32 txgbe_get_san_mac_addr_offset(struct txgbe_hw *hw,
1406 u16 *san_mac_offset)
1410 DEBUGFUNC("txgbe_get_san_mac_addr_offset");
1413 * First read the EEPROM pointer to see if the MAC addresses are
1416 err = hw->rom.readw_sw(hw, TXGBE_SAN_MAC_ADDR_PTR,
1419 DEBUGOUT("eeprom at offset %d failed",
1420 TXGBE_SAN_MAC_ADDR_PTR);
1427 * txgbe_get_san_mac_addr - SAN MAC address retrieval from the EEPROM
1428 * @hw: pointer to hardware structure
1429 * @san_mac_addr: SAN MAC address
1431 * Reads the SAN MAC address from the EEPROM, if it's available. This is
1432 * per-port, so set_lan_id() must be called before reading the addresses.
1433 * set_lan_id() is called by identify_sfp(), but this cannot be relied
1434 * upon for non-SFP connections, so we must call it here.
1436 s32 txgbe_get_san_mac_addr(struct txgbe_hw *hw, u8 *san_mac_addr)
1438 u16 san_mac_data, san_mac_offset;
1442 DEBUGFUNC("txgbe_get_san_mac_addr");
1445 * First read the EEPROM pointer to see if the MAC addresses are
1446 * available. If they're not, no point in calling set_lan_id() here.
1448 err = txgbe_get_san_mac_addr_offset(hw, &san_mac_offset);
1449 if (err || san_mac_offset == 0 || san_mac_offset == 0xFFFF)
1450 goto san_mac_addr_out;
1452 /* apply the port offset to the address offset */
1453 (hw->bus.func) ? (san_mac_offset += TXGBE_SAN_MAC_ADDR_PORT1_OFFSET) :
1454 (san_mac_offset += TXGBE_SAN_MAC_ADDR_PORT0_OFFSET);
1455 for (i = 0; i < 3; i++) {
1456 err = hw->rom.read16(hw, san_mac_offset,
1459 DEBUGOUT("eeprom read at offset %d failed",
1461 goto san_mac_addr_out;
1463 san_mac_addr[i * 2] = (u8)(san_mac_data);
1464 san_mac_addr[i * 2 + 1] = (u8)(san_mac_data >> 8);
1471 * No addresses available in this EEPROM. It's not an
1472 * error though, so just wipe the local address and return.
1474 for (i = 0; i < 6; i++)
1475 san_mac_addr[i] = 0xFF;
1480 * txgbe_set_san_mac_addr - Write the SAN MAC address to the EEPROM
1481 * @hw: pointer to hardware structure
1482 * @san_mac_addr: SAN MAC address
1484 * Write a SAN MAC address to the EEPROM.
1486 s32 txgbe_set_san_mac_addr(struct txgbe_hw *hw, u8 *san_mac_addr)
1489 u16 san_mac_data, san_mac_offset;
1492 DEBUGFUNC("txgbe_set_san_mac_addr");
1494 /* Look for SAN mac address pointer. If not defined, return */
1495 err = txgbe_get_san_mac_addr_offset(hw, &san_mac_offset);
1496 if (err || san_mac_offset == 0 || san_mac_offset == 0xFFFF)
1497 return TXGBE_ERR_NO_SAN_ADDR_PTR;
1499 /* Apply the port offset to the address offset */
1500 (hw->bus.func) ? (san_mac_offset += TXGBE_SAN_MAC_ADDR_PORT1_OFFSET) :
1501 (san_mac_offset += TXGBE_SAN_MAC_ADDR_PORT0_OFFSET);
1503 for (i = 0; i < 3; i++) {
1504 san_mac_data = (u16)((u16)(san_mac_addr[i * 2 + 1]) << 8);
1505 san_mac_data |= (u16)(san_mac_addr[i * 2]);
1506 hw->rom.write16(hw, san_mac_offset, san_mac_data);
1514 * txgbe_clear_vmdq - Disassociate a VMDq pool index from a rx address
1515 * @hw: pointer to hardware struct
1516 * @rar: receive address register index to disassociate
1517 * @vmdq: VMDq pool index to remove from the rar
1519 s32 txgbe_clear_vmdq(struct txgbe_hw *hw, u32 rar, u32 vmdq)
1521 u32 mpsar_lo, mpsar_hi;
1522 u32 rar_entries = hw->mac.num_rar_entries;
1524 DEBUGFUNC("txgbe_clear_vmdq");
1526 /* Make sure we are using a valid rar index range */
1527 if (rar >= rar_entries) {
1528 DEBUGOUT("RAR index %d is out of range.\n", rar);
1529 return TXGBE_ERR_INVALID_ARGUMENT;
1532 wr32(hw, TXGBE_ETHADDRIDX, rar);
1533 mpsar_lo = rd32(hw, TXGBE_ETHADDRASSL);
1534 mpsar_hi = rd32(hw, TXGBE_ETHADDRASSH);
1536 if (TXGBE_REMOVED(hw->hw_addr))
1539 if (!mpsar_lo && !mpsar_hi)
1542 if (vmdq == BIT_MASK32) {
1544 wr32(hw, TXGBE_ETHADDRASSL, 0);
1548 wr32(hw, TXGBE_ETHADDRASSH, 0);
1551 } else if (vmdq < 32) {
1552 mpsar_lo &= ~(1 << vmdq);
1553 wr32(hw, TXGBE_ETHADDRASSL, mpsar_lo);
1555 mpsar_hi &= ~(1 << (vmdq - 32));
1556 wr32(hw, TXGBE_ETHADDRASSH, mpsar_hi);
1559 /* was that the last pool using this rar? */
1560 if (mpsar_lo == 0 && mpsar_hi == 0 &&
1561 rar != 0 && rar != hw->mac.san_mac_rar_index)
1562 hw->mac.clear_rar(hw, rar);
1568 * txgbe_set_vmdq - Associate a VMDq pool index with a rx address
1569 * @hw: pointer to hardware struct
1570 * @rar: receive address register index to associate with a VMDq index
1571 * @vmdq: VMDq pool index
1573 s32 txgbe_set_vmdq(struct txgbe_hw *hw, u32 rar, u32 vmdq)
1576 u32 rar_entries = hw->mac.num_rar_entries;
1578 DEBUGFUNC("txgbe_set_vmdq");
1580 /* Make sure we are using a valid rar index range */
1581 if (rar >= rar_entries) {
1582 DEBUGOUT("RAR index %d is out of range.\n", rar);
1583 return TXGBE_ERR_INVALID_ARGUMENT;
1586 wr32(hw, TXGBE_ETHADDRIDX, rar);
1588 mpsar = rd32(hw, TXGBE_ETHADDRASSL);
1590 wr32(hw, TXGBE_ETHADDRASSL, mpsar);
1592 mpsar = rd32(hw, TXGBE_ETHADDRASSH);
1593 mpsar |= 1 << (vmdq - 32);
1594 wr32(hw, TXGBE_ETHADDRASSH, mpsar);
1600 * txgbe_init_uta_tables - Initialize the Unicast Table Array
1601 * @hw: pointer to hardware structure
1603 s32 txgbe_init_uta_tables(struct txgbe_hw *hw)
1607 DEBUGFUNC("txgbe_init_uta_tables");
1608 DEBUGOUT(" Clearing UTA\n");
1610 for (i = 0; i < 128; i++)
1611 wr32(hw, TXGBE_UCADDRTBL(i), 0);
1617 * txgbe_find_vlvf_slot - find the vlanid or the first empty slot
1618 * @hw: pointer to hardware structure
1619 * @vlan: VLAN id to write to VLAN filter
1620 * @vlvf_bypass: true to find vlanid only, false returns first empty slot if
1624 * return the VLVF index where this VLAN id should be placed
1627 s32 txgbe_find_vlvf_slot(struct txgbe_hw *hw, u32 vlan, bool vlvf_bypass)
1629 s32 regindex, first_empty_slot;
1632 /* short cut the special case */
1636 /* if vlvf_bypass is set we don't want to use an empty slot, we
1637 * will simply bypass the VLVF if there are no entries present in the
1638 * VLVF that contain our VLAN
1640 first_empty_slot = vlvf_bypass ? TXGBE_ERR_NO_SPACE : 0;
1642 /* add VLAN enable bit for comparison */
1643 vlan |= TXGBE_PSRVLAN_EA;
1645 /* Search for the vlan id in the VLVF entries. Save off the first empty
1646 * slot found along the way.
1648 * pre-decrement loop covering (TXGBE_NUM_POOL - 1) .. 1
1650 for (regindex = TXGBE_NUM_POOL; --regindex;) {
1651 wr32(hw, TXGBE_PSRVLANIDX, regindex);
1652 bits = rd32(hw, TXGBE_PSRVLAN);
1655 if (!first_empty_slot && !bits)
1656 first_empty_slot = regindex;
1659 /* If we are here then we didn't find the VLAN. Return first empty
1660 * slot we found during our search, else error.
1662 if (!first_empty_slot)
1663 DEBUGOUT("No space in VLVF.\n");
1665 return first_empty_slot ? first_empty_slot : TXGBE_ERR_NO_SPACE;
1669 * txgbe_set_vfta - Set VLAN filter table
1670 * @hw: pointer to hardware structure
1671 * @vlan: VLAN id to write to VLAN filter
1672 * @vind: VMDq output index that maps queue to VLAN id in VLVFB
1673 * @vlan_on: boolean flag to turn on/off VLAN
1674 * @vlvf_bypass: boolean flag indicating updating default pool is okay
1676 * Turn on/off specified VLAN in the VLAN filter table.
1678 s32 txgbe_set_vfta(struct txgbe_hw *hw, u32 vlan, u32 vind,
1679 bool vlan_on, bool vlvf_bypass)
1681 u32 regidx, vfta_delta, vfta;
1684 DEBUGFUNC("txgbe_set_vfta");
1686 if (vlan > 4095 || vind > 63)
1687 return TXGBE_ERR_PARAM;
1690 * this is a 2 part operation - first the VFTA, then the
1691 * VLVF and VLVFB if VT Mode is set
1692 * We don't write the VFTA until we know the VLVF part succeeded.
1696 * The VFTA is a bitstring made up of 128 32-bit registers
1697 * that enable the particular VLAN id, much like the MTA:
1698 * bits[11-5]: which register
1699 * bits[4-0]: which bit in the register
1702 vfta_delta = 1 << (vlan % 32);
1703 vfta = rd32(hw, TXGBE_VLANTBL(regidx));
1706 * vfta_delta represents the difference between the current value
1707 * of vfta and the value we want in the register. Since the diff
1708 * is an XOR mask we can just update the vfta using an XOR
1710 vfta_delta &= vlan_on ? ~vfta : vfta;
1714 * Call txgbe_set_vlvf to set VLVFB and VLVF
1716 err = txgbe_set_vlvf(hw, vlan, vind, vlan_on, &vfta_delta,
1725 /* Update VFTA now that we are ready for traffic */
1727 wr32(hw, TXGBE_VLANTBL(regidx), vfta);
1733 * txgbe_set_vlvf - Set VLAN Pool Filter
1734 * @hw: pointer to hardware structure
1735 * @vlan: VLAN id to write to VLAN filter
1736 * @vind: VMDq output index that maps queue to VLAN id in PSRVLANPLM
1737 * @vlan_on: boolean flag to turn on/off VLAN in PSRVLAN
1738 * @vfta_delta: pointer to the difference between the current value
1739 * of PSRVLANPLM and the desired value
1740 * @vfta: the desired value of the VFTA
1741 * @vlvf_bypass: boolean flag indicating updating default pool is okay
1743 * Turn on/off specified bit in VLVF table.
1745 s32 txgbe_set_vlvf(struct txgbe_hw *hw, u32 vlan, u32 vind,
1746 bool vlan_on, u32 *vfta_delta, u32 vfta,
1753 DEBUGFUNC("txgbe_set_vlvf");
1755 if (vlan > 4095 || vind > 63)
1756 return TXGBE_ERR_PARAM;
1758 /* If VT Mode is set
1760 * make sure the vlan is in PSRVLAN
1761 * set the vind bit in the matching PSRVLANPLM
1763 * clear the pool bit and possibly the vind
1765 portctl = rd32(hw, TXGBE_PORTCTL);
1766 if (!(portctl & TXGBE_PORTCTL_NUMVT_MASK))
1769 vlvf_index = txgbe_find_vlvf_slot(hw, vlan, vlvf_bypass);
1773 wr32(hw, TXGBE_PSRVLANIDX, vlvf_index);
1774 bits = rd32(hw, TXGBE_PSRVLANPLM(vind / 32));
1776 /* set the pool bit */
1777 bits |= 1 << (vind % 32);
1781 /* clear the pool bit */
1782 bits ^= 1 << (vind % 32);
1785 !rd32(hw, TXGBE_PSRVLANPLM(vind / 32))) {
1786 /* Clear PSRVLANPLM first, then disable PSRVLAN. Otherwise
1787 * we run the risk of stray packets leaking into
1788 * the PF via the default pool
1791 wr32(hw, TXGBE_PSRVLANPLM(vlan / 32), vfta);
1793 /* disable VLVF and clear remaining bit from pool */
1794 wr32(hw, TXGBE_PSRVLAN, 0);
1795 wr32(hw, TXGBE_PSRVLANPLM(vind / 32), 0);
1800 /* If there are still bits set in the PSRVLANPLM registers
1801 * for the VLAN ID indicated we need to see if the
1802 * caller is requesting that we clear the PSRVLANPLM entry bit.
1803 * If the caller has requested that we clear the PSRVLANPLM
1804 * entry bit but there are still pools/VFs using this VLAN
1805 * ID entry then ignore the request. We're not worried
1806 * about the case where we're turning the PSRVLANPLM VLAN ID
1807 * entry bit on, only when requested to turn it off as
1808 * there may be multiple pools and/or VFs using the
1809 * VLAN ID entry. In that case we cannot clear the
1810 * PSRVLANPLM bit until all pools/VFs using that VLAN ID have also
1811 * been cleared. This will be indicated by "bits" being
1817 /* record pool change and enable VLAN ID if not already enabled */
1818 wr32(hw, TXGBE_PSRVLANPLM(vind / 32), bits);
1819 wr32(hw, TXGBE_PSRVLAN, TXGBE_PSRVLAN_EA | vlan);
1825 * txgbe_clear_vfta - Clear VLAN filter table
1826 * @hw: pointer to hardware structure
1828 * Clears the VLAN filer table, and the VMDq index associated with the filter
1830 s32 txgbe_clear_vfta(struct txgbe_hw *hw)
1834 DEBUGFUNC("txgbe_clear_vfta");
1836 for (offset = 0; offset < hw->mac.vft_size; offset++)
1837 wr32(hw, TXGBE_VLANTBL(offset), 0);
1839 for (offset = 0; offset < TXGBE_NUM_POOL; offset++) {
1840 wr32(hw, TXGBE_PSRVLANIDX, offset);
1841 wr32(hw, TXGBE_PSRVLAN, 0);
1842 wr32(hw, TXGBE_PSRVLANPLM(0), 0);
1843 wr32(hw, TXGBE_PSRVLANPLM(1), 0);
1850 * txgbe_need_crosstalk_fix - Determine if we need to do cross talk fix
1851 * @hw: pointer to hardware structure
1853 * Contains the logic to identify if we need to verify link for the
1856 static bool txgbe_need_crosstalk_fix(struct txgbe_hw *hw)
1858 /* Does FW say we need the fix */
1859 if (!hw->need_crosstalk_fix)
1862 /* Only consider SFP+ PHYs i.e. media type fiber */
1863 switch (hw->phy.media_type) {
1864 case txgbe_media_type_fiber:
1865 case txgbe_media_type_fiber_qsfp:
1875 * txgbe_check_mac_link - Determine link and speed status
1876 * @hw: pointer to hardware structure
1877 * @speed: pointer to link speed
1878 * @link_up: true when link is up
1879 * @link_up_wait_to_complete: bool used to wait for link up or not
1881 * Reads the links register to determine if link is up and the current speed
1883 s32 txgbe_check_mac_link(struct txgbe_hw *hw, u32 *speed,
1884 bool *link_up, bool link_up_wait_to_complete)
1886 u32 links_reg, links_orig;
1889 DEBUGFUNC("txgbe_check_mac_link");
1891 /* If Crosstalk fix enabled do the sanity check of making sure
1892 * the SFP+ cage is full.
1894 if (txgbe_need_crosstalk_fix(hw)) {
1897 switch (hw->mac.type) {
1898 case txgbe_mac_raptor:
1899 sfp_cage_full = !rd32m(hw, TXGBE_GPIODATA,
1903 /* sanity check - No SFP+ devices here */
1904 sfp_cage_full = false;
1908 if (!sfp_cage_full) {
1910 *speed = TXGBE_LINK_SPEED_UNKNOWN;
1915 /* clear the old state */
1916 links_orig = rd32(hw, TXGBE_PORTSTAT);
1918 links_reg = rd32(hw, TXGBE_PORTSTAT);
1920 if (links_orig != links_reg) {
1921 DEBUGOUT("LINKS changed from %08X to %08X\n",
1922 links_orig, links_reg);
1925 if (link_up_wait_to_complete) {
1926 for (i = 0; i < hw->mac.max_link_up_time; i++) {
1927 if (!(links_reg & TXGBE_PORTSTAT_UP)) {
1934 links_reg = rd32(hw, TXGBE_PORTSTAT);
1937 if (links_reg & TXGBE_PORTSTAT_UP)
1943 switch (links_reg & TXGBE_PORTSTAT_BW_MASK) {
1944 case TXGBE_PORTSTAT_BW_10G:
1945 *speed = TXGBE_LINK_SPEED_10GB_FULL;
1947 case TXGBE_PORTSTAT_BW_1G:
1948 *speed = TXGBE_LINK_SPEED_1GB_FULL;
1950 case TXGBE_PORTSTAT_BW_100M:
1951 *speed = TXGBE_LINK_SPEED_100M_FULL;
1954 *speed = TXGBE_LINK_SPEED_UNKNOWN;
1961 * txgbe_get_wwn_prefix - Get alternative WWNN/WWPN prefix from
1963 * @hw: pointer to hardware structure
1964 * @wwnn_prefix: the alternative WWNN prefix
1965 * @wwpn_prefix: the alternative WWPN prefix
1967 * This function will read the EEPROM from the alternative SAN MAC address
1968 * block to check the support for the alternative WWNN/WWPN prefix support.
1970 s32 txgbe_get_wwn_prefix(struct txgbe_hw *hw, u16 *wwnn_prefix,
1974 u16 alt_san_mac_blk_offset;
1976 DEBUGFUNC("txgbe_get_wwn_prefix");
1978 /* clear output first */
1979 *wwnn_prefix = 0xFFFF;
1980 *wwpn_prefix = 0xFFFF;
1982 /* check if alternative SAN MAC is supported */
1983 offset = TXGBE_ALT_SAN_MAC_ADDR_BLK_PTR;
1984 if (hw->rom.readw_sw(hw, offset, &alt_san_mac_blk_offset))
1985 goto wwn_prefix_err;
1987 if (alt_san_mac_blk_offset == 0 || alt_san_mac_blk_offset == 0xFFFF)
1988 goto wwn_prefix_out;
1990 /* check capability in alternative san mac address block */
1991 offset = alt_san_mac_blk_offset + TXGBE_ALT_SAN_MAC_ADDR_CAPS_OFFSET;
1992 if (hw->rom.read16(hw, offset, &caps))
1993 goto wwn_prefix_err;
1994 if (!(caps & TXGBE_ALT_SAN_MAC_ADDR_CAPS_ALTWWN))
1995 goto wwn_prefix_out;
1997 /* get the corresponding prefix for WWNN/WWPN */
1998 offset = alt_san_mac_blk_offset + TXGBE_ALT_SAN_MAC_ADDR_WWNN_OFFSET;
1999 if (hw->rom.read16(hw, offset, wwnn_prefix))
2000 DEBUGOUT("eeprom read at offset %d failed", offset);
2002 offset = alt_san_mac_blk_offset + TXGBE_ALT_SAN_MAC_ADDR_WWPN_OFFSET;
2003 if (hw->rom.read16(hw, offset, wwpn_prefix))
2004 goto wwn_prefix_err;
2010 DEBUGOUT("eeprom read at offset %d failed", offset);
2015 * txgbe_set_mac_anti_spoofing - Enable/Disable MAC anti-spoofing
2016 * @hw: pointer to hardware structure
2017 * @enable: enable or disable switch for MAC anti-spoofing
2018 * @vf: Virtual Function pool - VF Pool to set for MAC anti-spoofing
2021 void txgbe_set_mac_anti_spoofing(struct txgbe_hw *hw, bool enable, int vf)
2023 int vf_target_reg = vf >> 3;
2024 int vf_target_shift = vf % 8;
2027 pfvfspoof = rd32(hw, TXGBE_POOLTXASMAC(vf_target_reg));
2029 pfvfspoof |= (1 << vf_target_shift);
2031 pfvfspoof &= ~(1 << vf_target_shift);
2032 wr32(hw, TXGBE_POOLTXASMAC(vf_target_reg), pfvfspoof);
2036 * txgbe_set_ethertype_anti_spoofing - Configure Ethertype anti-spoofing
2037 * @hw: pointer to hardware structure
2038 * @enable: enable or disable switch for Ethertype anti-spoofing
2039 * @vf: Virtual Function pool - VF Pool to set for Ethertype anti-spoofing
2042 void txgbe_set_ethertype_anti_spoofing(struct txgbe_hw *hw,
2043 bool enable, int vf)
2045 int vf_target_reg = vf >> 3;
2046 int vf_target_shift = vf % 8;
2049 pfvfspoof = rd32(hw, TXGBE_POOLTXASET(vf_target_reg));
2051 pfvfspoof |= (1 << vf_target_shift);
2053 pfvfspoof &= ~(1 << vf_target_shift);
2054 wr32(hw, TXGBE_POOLTXASET(vf_target_reg), pfvfspoof);
2058 * txgbe_get_device_caps - Get additional device capabilities
2059 * @hw: pointer to hardware structure
2060 * @device_caps: the EEPROM word with the extra device capabilities
2062 * This function will read the EEPROM location for the device capabilities,
2063 * and return the word through device_caps.
2065 s32 txgbe_get_device_caps(struct txgbe_hw *hw, u16 *device_caps)
2067 DEBUGFUNC("txgbe_get_device_caps");
2069 hw->rom.readw_sw(hw, TXGBE_DEVICE_CAPS, device_caps);
2075 * txgbe_set_pba - Initialize Rx packet buffer
2076 * @hw: pointer to hardware structure
2077 * @num_pb: number of packet buffers to allocate
2078 * @headroom: reserve n KB of headroom
2079 * @strategy: packet buffer allocation strategy
2081 void txgbe_set_pba(struct txgbe_hw *hw, int num_pb, u32 headroom,
2084 u32 pbsize = hw->mac.rx_pb_size;
2086 u32 rxpktsize, txpktsize, txpbthresh;
2088 UNREFERENCED_PARAMETER(hw);
2090 /* Reserve headroom */
2096 /* Divide remaining packet buffer space amongst the number of packet
2097 * buffers requested using supplied strategy.
2100 case PBA_STRATEGY_WEIGHTED:
2101 /* txgbe_dcb_pba_80_48 strategy weight first half of packet
2102 * buffer with 5/8 of the packet buffer space.
2104 rxpktsize = (pbsize * 5) / (num_pb * 4);
2105 pbsize -= rxpktsize * (num_pb / 2);
2107 for (; i < (num_pb / 2); i++)
2108 wr32(hw, TXGBE_PBRXSIZE(i), rxpktsize);
2109 /* fall through - configure remaining packet buffers */
2110 case PBA_STRATEGY_EQUAL:
2111 rxpktsize = (pbsize / (num_pb - i));
2113 for (; i < num_pb; i++)
2114 wr32(hw, TXGBE_PBRXSIZE(i), rxpktsize);
2120 /* Only support an equally distributed Tx packet buffer strategy. */
2121 txpktsize = TXGBE_PBTXSIZE_MAX / num_pb;
2122 txpbthresh = (txpktsize / 1024) - TXGBE_TXPKT_SIZE_MAX;
2123 for (i = 0; i < num_pb; i++) {
2124 wr32(hw, TXGBE_PBTXSIZE(i), txpktsize);
2125 wr32(hw, TXGBE_PBTXDMATH(i), txpbthresh);
2128 /* Clear unused TCs, if any, to zero buffer size*/
2129 for (; i < TXGBE_MAX_UP; i++) {
2130 wr32(hw, TXGBE_PBRXSIZE(i), 0);
2131 wr32(hw, TXGBE_PBTXSIZE(i), 0);
2132 wr32(hw, TXGBE_PBTXDMATH(i), 0);
2137 * txgbe_clear_tx_pending - Clear pending TX work from the PCIe fifo
2138 * @hw: pointer to the hardware structure
2140 * The MACs can experience issues if TX work is still pending
2141 * when a reset occurs. This function prevents this by flushing the PCIe
2142 * buffers on the system.
2144 void txgbe_clear_tx_pending(struct txgbe_hw *hw)
2146 u32 hlreg0, i, poll;
2149 * If double reset is not requested then all transactions should
2150 * already be clear and as such there is no work to do
2152 if (!(hw->mac.flags & TXGBE_FLAGS_DOUBLE_RESET_REQUIRED))
2155 hlreg0 = rd32(hw, TXGBE_PSRCTL);
2156 wr32(hw, TXGBE_PSRCTL, hlreg0 | TXGBE_PSRCTL_LBENA);
2158 /* Wait for a last completion before clearing buffers */
2163 * Before proceeding, make sure that the PCIe block does not have
2164 * transactions pending.
2166 poll = (800 * 11) / 10;
2167 for (i = 0; i < poll; i++)
2170 /* Flush all writes and allow 20usec for all transactions to clear */
2174 /* restore previous register values */
2175 wr32(hw, TXGBE_PSRCTL, hlreg0);
2179 * txgbe_get_thermal_sensor_data - Gathers thermal sensor data
2180 * @hw: pointer to hardware structure
2182 * Returns the thermal sensor data structure
2184 s32 txgbe_get_thermal_sensor_data(struct txgbe_hw *hw)
2186 struct txgbe_thermal_sensor_data *data = &hw->mac.thermal_sensor_data;
2190 DEBUGFUNC("txgbe_get_thermal_sensor_data");
2192 /* Only support thermal sensors attached to physical port 0 */
2193 if (hw->bus.lan_id != 0)
2194 return TXGBE_NOT_IMPLEMENTED;
2196 ts_stat = rd32(hw, TXGBE_TSSTAT);
2197 tsv = (s64)TXGBE_TSSTAT_DATA(ts_stat);
2198 tsv = tsv > 1200 ? tsv : 1200;
2199 tsv = -(48380 << 8) / 1000
2200 + tsv * (31020 << 8) / 100000
2201 - tsv * tsv * (18201 << 8) / 100000000
2202 + tsv * tsv * tsv * (81542 << 8) / 1000000000000
2203 - tsv * tsv * tsv * tsv * (16743 << 8) / 1000000000000000;
2206 data->sensor[0].temp = (s16)tsv;
2212 * txgbe_init_thermal_sensor_thresh - Inits thermal sensor thresholds
2213 * @hw: pointer to hardware structure
2215 * Inits the thermal sensor thresholds according to the NVM map
2216 * and save off the threshold and location values into mac.thermal_sensor_data
2218 s32 txgbe_init_thermal_sensor_thresh(struct txgbe_hw *hw)
2220 struct txgbe_thermal_sensor_data *data = &hw->mac.thermal_sensor_data;
2222 DEBUGFUNC("txgbe_init_thermal_sensor_thresh");
2224 memset(data, 0, sizeof(struct txgbe_thermal_sensor_data));
2226 if (hw->bus.lan_id != 0)
2227 return TXGBE_NOT_IMPLEMENTED;
2229 wr32(hw, TXGBE_TSCTRL, TXGBE_TSCTRL_EVALMD);
2230 wr32(hw, TXGBE_TSINTR,
2231 TXGBE_TSINTR_AEN | TXGBE_TSINTR_DEN);
2232 wr32(hw, TXGBE_TSEN, TXGBE_TSEN_ENA);
2235 data->sensor[0].alarm_thresh = 100;
2236 wr32(hw, TXGBE_TSATHRE, 677);
2237 data->sensor[0].dalarm_thresh = 90;
2238 wr32(hw, TXGBE_TSDTHRE, 614);
2243 void txgbe_disable_rx(struct txgbe_hw *hw)
2247 pfdtxgswc = rd32(hw, TXGBE_PSRCTL);
2248 if (pfdtxgswc & TXGBE_PSRCTL_LBENA) {
2249 pfdtxgswc &= ~TXGBE_PSRCTL_LBENA;
2250 wr32(hw, TXGBE_PSRCTL, pfdtxgswc);
2251 hw->mac.set_lben = true;
2253 hw->mac.set_lben = false;
2256 wr32m(hw, TXGBE_PBRXCTL, TXGBE_PBRXCTL_ENA, 0);
2257 wr32m(hw, TXGBE_MACRXCFG, TXGBE_MACRXCFG_ENA, 0);
2260 void txgbe_enable_rx(struct txgbe_hw *hw)
2264 wr32m(hw, TXGBE_MACRXCFG, TXGBE_MACRXCFG_ENA, TXGBE_MACRXCFG_ENA);
2265 wr32m(hw, TXGBE_PBRXCTL, TXGBE_PBRXCTL_ENA, TXGBE_PBRXCTL_ENA);
2267 if (hw->mac.set_lben) {
2268 pfdtxgswc = rd32(hw, TXGBE_PSRCTL);
2269 pfdtxgswc |= TXGBE_PSRCTL_LBENA;
2270 wr32(hw, TXGBE_PSRCTL, pfdtxgswc);
2271 hw->mac.set_lben = false;
2276 * txgbe_setup_mac_link_multispeed_fiber - Set MAC link speed
2277 * @hw: pointer to hardware structure
2278 * @speed: new link speed
2279 * @autoneg_wait_to_complete: true when waiting for completion is needed
2281 * Set the link speed in the MAC and/or PHY register and restarts link.
2283 s32 txgbe_setup_mac_link_multispeed_fiber(struct txgbe_hw *hw,
2285 bool autoneg_wait_to_complete)
2287 u32 link_speed = TXGBE_LINK_SPEED_UNKNOWN;
2288 u32 highest_link_speed = TXGBE_LINK_SPEED_UNKNOWN;
2292 bool autoneg, link_up = false;
2294 DEBUGFUNC("txgbe_setup_mac_link_multispeed_fiber");
2296 /* Mask off requested but non-supported speeds */
2297 status = hw->mac.get_link_capabilities(hw, &link_speed, &autoneg);
2301 speed &= link_speed;
2303 /* Try each speed one by one, highest priority first. We do this in
2304 * software because 10Gb fiber doesn't support speed autonegotiation.
2306 if (speed & TXGBE_LINK_SPEED_10GB_FULL) {
2308 highest_link_speed = TXGBE_LINK_SPEED_10GB_FULL;
2310 /* Set the module link speed */
2311 switch (hw->phy.media_type) {
2312 case txgbe_media_type_fiber:
2313 hw->mac.set_rate_select_speed(hw,
2314 TXGBE_LINK_SPEED_10GB_FULL);
2316 case txgbe_media_type_fiber_qsfp:
2317 /* QSFP module automatically detects MAC link speed */
2320 DEBUGOUT("Unexpected media type.\n");
2324 /* Allow module to change analog characteristics (1G->10G) */
2327 status = hw->mac.setup_mac_link(hw,
2328 TXGBE_LINK_SPEED_10GB_FULL,
2329 autoneg_wait_to_complete);
2333 /* Flap the Tx laser if it has not already been done */
2334 hw->mac.flap_tx_laser(hw);
2336 /* Wait for the controller to acquire link. Per IEEE 802.3ap,
2337 * Section 73.10.2, we may have to wait up to 500ms if KR is
2338 * attempted. uses the same timing for 10g SFI.
2340 for (i = 0; i < 5; i++) {
2341 /* Wait for the link partner to also set speed */
2344 /* If we have link, just jump out */
2345 status = hw->mac.check_link(hw, &link_speed,
2355 if (speed & TXGBE_LINK_SPEED_1GB_FULL) {
2357 if (highest_link_speed == TXGBE_LINK_SPEED_UNKNOWN)
2358 highest_link_speed = TXGBE_LINK_SPEED_1GB_FULL;
2360 /* Set the module link speed */
2361 switch (hw->phy.media_type) {
2362 case txgbe_media_type_fiber:
2363 hw->mac.set_rate_select_speed(hw,
2364 TXGBE_LINK_SPEED_1GB_FULL);
2366 case txgbe_media_type_fiber_qsfp:
2367 /* QSFP module automatically detects link speed */
2370 DEBUGOUT("Unexpected media type.\n");
2374 /* Allow module to change analog characteristics (10G->1G) */
2377 status = hw->mac.setup_mac_link(hw,
2378 TXGBE_LINK_SPEED_1GB_FULL,
2379 autoneg_wait_to_complete);
2383 /* Flap the Tx laser if it has not already been done */
2384 hw->mac.flap_tx_laser(hw);
2386 /* Wait for the link partner to also set speed */
2389 /* If we have link, just jump out */
2390 status = hw->mac.check_link(hw, &link_speed, &link_up, false);
2398 /* We didn't get link. Configure back to the highest speed we tried,
2399 * (if there was more than one). We call ourselves back with just the
2400 * single highest speed that the user requested.
2403 status = txgbe_setup_mac_link_multispeed_fiber(hw,
2405 autoneg_wait_to_complete);
2408 /* Set autoneg_advertised value based on input link speed */
2409 hw->phy.autoneg_advertised = 0;
2411 if (speed & TXGBE_LINK_SPEED_10GB_FULL)
2412 hw->phy.autoneg_advertised |= TXGBE_LINK_SPEED_10GB_FULL;
2414 if (speed & TXGBE_LINK_SPEED_1GB_FULL)
2415 hw->phy.autoneg_advertised |= TXGBE_LINK_SPEED_1GB_FULL;
2421 * txgbe_init_shared_code - Initialize the shared code
2422 * @hw: pointer to hardware structure
2424 * This will assign function pointers and assign the MAC type and PHY code.
2425 * Does not touch the hardware. This function must be called prior to any
2426 * other function in the shared code. The txgbe_hw structure should be
2427 * memset to 0 prior to calling this function. The following fields in
2428 * hw structure should be filled in prior to calling this function:
2429 * hw_addr, back, device_id, vendor_id, subsystem_device_id,
2430 * subsystem_vendor_id, and revision_id
2432 s32 txgbe_init_shared_code(struct txgbe_hw *hw)
2436 DEBUGFUNC("txgbe_init_shared_code");
2441 txgbe_set_mac_type(hw);
2443 txgbe_init_ops_dummy(hw);
2444 switch (hw->mac.type) {
2445 case txgbe_mac_raptor:
2446 status = txgbe_init_ops_pf(hw);
2449 status = TXGBE_ERR_DEVICE_NOT_SUPPORTED;
2452 hw->mac.max_link_up_time = TXGBE_LINK_UP_TIME;
2454 hw->bus.set_lan_id(hw);
2460 * txgbe_set_mac_type - Sets MAC type
2461 * @hw: pointer to the HW structure
2463 * This function sets the mac type of the adapter based on the
2464 * vendor ID and device ID stored in the hw structure.
2466 s32 txgbe_set_mac_type(struct txgbe_hw *hw)
2470 DEBUGFUNC("txgbe_set_mac_type");
2472 if (hw->vendor_id != PCI_VENDOR_ID_WANGXUN) {
2473 DEBUGOUT("Unsupported vendor id: %x", hw->vendor_id);
2474 return TXGBE_ERR_DEVICE_NOT_SUPPORTED;
2477 switch (hw->device_id) {
2478 case TXGBE_DEV_ID_RAPTOR_KR_KX_KX4:
2479 hw->phy.media_type = txgbe_media_type_backplane;
2480 hw->mac.type = txgbe_mac_raptor;
2482 case TXGBE_DEV_ID_RAPTOR_XAUI:
2483 case TXGBE_DEV_ID_RAPTOR_SGMII:
2484 hw->phy.media_type = txgbe_media_type_copper;
2485 hw->mac.type = txgbe_mac_raptor;
2487 case TXGBE_DEV_ID_RAPTOR_SFP:
2488 case TXGBE_DEV_ID_WX1820_SFP:
2489 hw->phy.media_type = txgbe_media_type_fiber;
2490 hw->mac.type = txgbe_mac_raptor;
2492 case TXGBE_DEV_ID_RAPTOR_QSFP:
2493 hw->phy.media_type = txgbe_media_type_fiber_qsfp;
2494 hw->mac.type = txgbe_mac_raptor;
2496 case TXGBE_DEV_ID_RAPTOR_VF:
2497 case TXGBE_DEV_ID_RAPTOR_VF_HV:
2498 hw->phy.media_type = txgbe_media_type_virtual;
2499 hw->mac.type = txgbe_mac_raptor_vf;
2502 err = TXGBE_ERR_DEVICE_NOT_SUPPORTED;
2503 DEBUGOUT("Unsupported device id: %x", hw->device_id);
2507 DEBUGOUT("found mac: %d media: %d, returns: %d\n",
2508 hw->mac.type, hw->phy.media_type, err);
2512 void txgbe_init_mac_link_ops(struct txgbe_hw *hw)
2514 struct txgbe_mac_info *mac = &hw->mac;
2516 DEBUGFUNC("txgbe_init_mac_link_ops");
2519 * enable the laser control functions for SFP+ fiber
2520 * and MNG not enabled
2522 if (hw->phy.media_type == txgbe_media_type_fiber &&
2523 !txgbe_mng_enabled(hw)) {
2524 mac->disable_tx_laser =
2525 txgbe_disable_tx_laser_multispeed_fiber;
2526 mac->enable_tx_laser =
2527 txgbe_enable_tx_laser_multispeed_fiber;
2528 mac->flap_tx_laser =
2529 txgbe_flap_tx_laser_multispeed_fiber;
2532 if ((hw->phy.media_type == txgbe_media_type_fiber ||
2533 hw->phy.media_type == txgbe_media_type_fiber_qsfp) &&
2534 hw->phy.multispeed_fiber) {
2535 /* Set up dual speed SFP+ support */
2536 mac->setup_link = txgbe_setup_mac_link_multispeed_fiber;
2537 mac->setup_mac_link = txgbe_setup_mac_link;
2538 mac->set_rate_select_speed = txgbe_set_hard_rate_select_speed;
2539 } else if ((hw->phy.media_type == txgbe_media_type_backplane) &&
2540 (hw->phy.smart_speed == txgbe_smart_speed_auto ||
2541 hw->phy.smart_speed == txgbe_smart_speed_on) &&
2542 !txgbe_verify_lesm_fw_enabled_raptor(hw)) {
2543 mac->setup_link = txgbe_setup_mac_link_smartspeed;
2545 mac->setup_link = txgbe_setup_mac_link;
2550 * txgbe_init_phy_raptor - PHY/SFP specific init
2551 * @hw: pointer to hardware structure
2553 * Initialize any function pointers that were not able to be
2554 * set during init_shared_code because the PHY/SFP type was
2555 * not known. Perform the SFP init if necessary.
2558 s32 txgbe_init_phy_raptor(struct txgbe_hw *hw)
2560 struct txgbe_mac_info *mac = &hw->mac;
2561 struct txgbe_phy_info *phy = &hw->phy;
2564 DEBUGFUNC("txgbe_init_phy_raptor");
2566 if (hw->device_id == TXGBE_DEV_ID_RAPTOR_QSFP) {
2567 /* Store flag indicating I2C bus access control unit. */
2568 hw->phy.qsfp_shared_i2c_bus = TRUE;
2570 /* Initialize access to QSFP+ I2C bus */
2574 /* Identify the PHY or SFP module */
2575 err = phy->identify(hw);
2576 if (err == TXGBE_ERR_SFP_NOT_SUPPORTED)
2577 goto init_phy_ops_out;
2579 /* Setup function pointers based on detected SFP module and speeds */
2580 txgbe_init_mac_link_ops(hw);
2582 /* If copper media, overwrite with copper function pointers */
2583 if (phy->media_type == txgbe_media_type_copper) {
2584 mac->setup_link = txgbe_setup_copper_link_raptor;
2585 mac->get_link_capabilities =
2586 txgbe_get_copper_link_capabilities;
2589 /* Set necessary function pointers based on PHY type */
2590 switch (hw->phy.type) {
2592 phy->setup_link = txgbe_setup_phy_link_tnx;
2593 phy->check_link = txgbe_check_phy_link_tnx;
2603 s32 txgbe_setup_sfp_modules(struct txgbe_hw *hw)
2607 DEBUGFUNC("txgbe_setup_sfp_modules");
2609 if (hw->phy.sfp_type == txgbe_sfp_type_unknown)
2612 txgbe_init_mac_link_ops(hw);
2614 /* PHY config will finish before releasing the semaphore */
2615 err = hw->mac.acquire_swfw_sync(hw, TXGBE_MNGSEM_SWPHY);
2617 return TXGBE_ERR_SWFW_SYNC;
2619 /* Release the semaphore */
2620 hw->mac.release_swfw_sync(hw, TXGBE_MNGSEM_SWPHY);
2622 /* Delay obtaining semaphore again to allow FW access
2623 * prot_autoc_write uses the semaphore too.
2625 msec_delay(hw->rom.semaphore_delay);
2628 DEBUGOUT("sfp module setup not complete\n");
2629 return TXGBE_ERR_SFP_SETUP_NOT_COMPLETE;
2636 * txgbe_prot_autoc_read_raptor - Hides MAC differences needed for AUTOC read
2637 * @hw: pointer to hardware structure
2638 * @locked: Return the if we locked for this read.
2639 * @value: Value we read from AUTOC
2641 * For this part we need to wrap read-modify-writes with a possible
2642 * FW/SW lock. It is assumed this lock will be freed with the next
2643 * prot_autoc_write_raptor().
2645 s32 txgbe_prot_autoc_read_raptor(struct txgbe_hw *hw, bool *locked, u64 *value)
2648 bool lock_state = false;
2650 /* If LESM is on then we need to hold the SW/FW semaphore. */
2651 if (txgbe_verify_lesm_fw_enabled_raptor(hw)) {
2652 err = hw->mac.acquire_swfw_sync(hw,
2653 TXGBE_MNGSEM_SWPHY);
2655 return TXGBE_ERR_SWFW_SYNC;
2661 *locked = lock_state;
2663 *value = txgbe_autoc_read(hw);
2668 * txgbe_prot_autoc_write_raptor - Hides MAC differences needed for AUTOC write
2669 * @hw: pointer to hardware structure
2670 * @autoc: value to write to AUTOC
2671 * @locked: bool to indicate whether the SW/FW lock was already taken by
2672 * previous prot_autoc_read_raptor.
2674 * This part may need to hold the SW/FW lock around all writes to
2675 * AUTOC. Likewise after a write we need to do a pipeline reset.
2677 s32 txgbe_prot_autoc_write_raptor(struct txgbe_hw *hw, bool locked, u64 autoc)
2681 /* Blocked by MNG FW so bail */
2682 if (txgbe_check_reset_blocked(hw))
2685 /* We only need to get the lock if:
2686 * - We didn't do it already (in the read part of a read-modify-write)
2687 * - LESM is enabled.
2689 if (!locked && txgbe_verify_lesm_fw_enabled_raptor(hw)) {
2690 err = hw->mac.acquire_swfw_sync(hw,
2691 TXGBE_MNGSEM_SWPHY);
2693 return TXGBE_ERR_SWFW_SYNC;
2698 txgbe_autoc_write(hw, autoc);
2699 err = txgbe_reset_pipeline_raptor(hw);
2702 /* Free the SW/FW semaphore as we either grabbed it here or
2703 * already had it when this function was called.
2706 hw->mac.release_swfw_sync(hw, TXGBE_MNGSEM_SWPHY);
2712 * txgbe_init_ops_pf - Inits func ptrs and MAC type
2713 * @hw: pointer to hardware structure
2715 * Initialize the function pointers and assign the MAC type.
2716 * Does not touch the hardware.
2718 s32 txgbe_init_ops_pf(struct txgbe_hw *hw)
2720 struct txgbe_bus_info *bus = &hw->bus;
2721 struct txgbe_mac_info *mac = &hw->mac;
2722 struct txgbe_phy_info *phy = &hw->phy;
2723 struct txgbe_rom_info *rom = &hw->rom;
2724 struct txgbe_mbx_info *mbx = &hw->mbx;
2726 DEBUGFUNC("txgbe_init_ops_pf");
2729 bus->set_lan_id = txgbe_set_lan_id_multi_port;
2732 phy->get_media_type = txgbe_get_media_type_raptor;
2733 phy->identify = txgbe_identify_phy;
2734 phy->init = txgbe_init_phy_raptor;
2735 phy->read_reg = txgbe_read_phy_reg;
2736 phy->write_reg = txgbe_write_phy_reg;
2737 phy->read_reg_mdi = txgbe_read_phy_reg_mdi;
2738 phy->write_reg_mdi = txgbe_write_phy_reg_mdi;
2739 phy->setup_link = txgbe_setup_phy_link;
2740 phy->setup_link_speed = txgbe_setup_phy_link_speed;
2741 phy->read_i2c_byte = txgbe_read_i2c_byte;
2742 phy->write_i2c_byte = txgbe_write_i2c_byte;
2743 phy->read_i2c_sff8472 = txgbe_read_i2c_sff8472;
2744 phy->read_i2c_eeprom = txgbe_read_i2c_eeprom;
2745 phy->write_i2c_eeprom = txgbe_write_i2c_eeprom;
2746 phy->identify_sfp = txgbe_identify_module;
2747 phy->read_i2c_byte_unlocked = txgbe_read_i2c_byte_unlocked;
2748 phy->write_i2c_byte_unlocked = txgbe_write_i2c_byte_unlocked;
2749 phy->reset = txgbe_reset_phy;
2752 mac->init_hw = txgbe_init_hw;
2753 mac->start_hw = txgbe_start_hw_raptor;
2754 mac->clear_hw_cntrs = txgbe_clear_hw_cntrs;
2755 mac->enable_rx_dma = txgbe_enable_rx_dma_raptor;
2756 mac->get_mac_addr = txgbe_get_mac_addr;
2757 mac->stop_hw = txgbe_stop_hw;
2758 mac->acquire_swfw_sync = txgbe_acquire_swfw_sync;
2759 mac->release_swfw_sync = txgbe_release_swfw_sync;
2760 mac->reset_hw = txgbe_reset_hw;
2762 mac->disable_sec_rx_path = txgbe_disable_sec_rx_path;
2763 mac->enable_sec_rx_path = txgbe_enable_sec_rx_path;
2764 mac->disable_sec_tx_path = txgbe_disable_sec_tx_path;
2765 mac->enable_sec_tx_path = txgbe_enable_sec_tx_path;
2766 mac->get_san_mac_addr = txgbe_get_san_mac_addr;
2767 mac->set_san_mac_addr = txgbe_set_san_mac_addr;
2768 mac->get_device_caps = txgbe_get_device_caps;
2769 mac->get_wwn_prefix = txgbe_get_wwn_prefix;
2770 mac->autoc_read = txgbe_autoc_read;
2771 mac->autoc_write = txgbe_autoc_write;
2772 mac->prot_autoc_read = txgbe_prot_autoc_read_raptor;
2773 mac->prot_autoc_write = txgbe_prot_autoc_write_raptor;
2775 /* RAR, Multicast, VLAN */
2776 mac->set_rar = txgbe_set_rar;
2777 mac->clear_rar = txgbe_clear_rar;
2778 mac->init_rx_addrs = txgbe_init_rx_addrs;
2779 mac->enable_rx = txgbe_enable_rx;
2780 mac->disable_rx = txgbe_disable_rx;
2781 mac->set_vmdq = txgbe_set_vmdq;
2782 mac->clear_vmdq = txgbe_clear_vmdq;
2783 mac->set_vfta = txgbe_set_vfta;
2784 mac->set_vlvf = txgbe_set_vlvf;
2785 mac->clear_vfta = txgbe_clear_vfta;
2786 mac->init_uta_tables = txgbe_init_uta_tables;
2787 mac->setup_sfp = txgbe_setup_sfp_modules;
2788 mac->set_mac_anti_spoofing = txgbe_set_mac_anti_spoofing;
2789 mac->set_ethertype_anti_spoofing = txgbe_set_ethertype_anti_spoofing;
2792 mac->fc_enable = txgbe_fc_enable;
2793 mac->setup_fc = txgbe_setup_fc;
2794 mac->fc_autoneg = txgbe_fc_autoneg;
2797 mac->get_link_capabilities = txgbe_get_link_capabilities_raptor;
2798 mac->check_link = txgbe_check_mac_link;
2799 mac->setup_pba = txgbe_set_pba;
2801 /* Manageability interface */
2802 mac->set_fw_drv_ver = txgbe_hic_set_drv_ver;
2803 mac->get_thermal_sensor_data = txgbe_get_thermal_sensor_data;
2804 mac->init_thermal_sensor_thresh = txgbe_init_thermal_sensor_thresh;
2806 mbx->init_params = txgbe_init_mbx_params_pf;
2807 mbx->read = txgbe_read_mbx_pf;
2808 mbx->write = txgbe_write_mbx_pf;
2809 mbx->check_for_msg = txgbe_check_for_msg_pf;
2810 mbx->check_for_ack = txgbe_check_for_ack_pf;
2811 mbx->check_for_rst = txgbe_check_for_rst_pf;
2814 rom->init_params = txgbe_init_eeprom_params;
2815 rom->read16 = txgbe_ee_read16;
2816 rom->readw_buffer = txgbe_ee_readw_buffer;
2817 rom->readw_sw = txgbe_ee_readw_sw;
2818 rom->read32 = txgbe_ee_read32;
2819 rom->write16 = txgbe_ee_write16;
2820 rom->writew_buffer = txgbe_ee_writew_buffer;
2821 rom->writew_sw = txgbe_ee_writew_sw;
2822 rom->write32 = txgbe_ee_write32;
2823 rom->validate_checksum = txgbe_validate_eeprom_checksum;
2824 rom->update_checksum = txgbe_update_eeprom_checksum;
2825 rom->calc_checksum = txgbe_calc_eeprom_checksum;
2827 mac->mcft_size = TXGBE_RAPTOR_MC_TBL_SIZE;
2828 mac->vft_size = TXGBE_RAPTOR_VFT_TBL_SIZE;
2829 mac->num_rar_entries = TXGBE_RAPTOR_RAR_ENTRIES;
2830 mac->rx_pb_size = TXGBE_RAPTOR_RX_PB_SIZE;
2831 mac->max_rx_queues = TXGBE_RAPTOR_MAX_RX_QUEUES;
2832 mac->max_tx_queues = TXGBE_RAPTOR_MAX_TX_QUEUES;
2838 * txgbe_get_link_capabilities_raptor - Determines link capabilities
2839 * @hw: pointer to hardware structure
2840 * @speed: pointer to link speed
2841 * @autoneg: true when autoneg or autotry is enabled
2843 * Determines the link capabilities by reading the AUTOC register.
2845 s32 txgbe_get_link_capabilities_raptor(struct txgbe_hw *hw,
2852 DEBUGFUNC("txgbe_get_link_capabilities_raptor");
2854 /* Check if 1G SFP module. */
2855 if (hw->phy.sfp_type == txgbe_sfp_type_1g_cu_core0 ||
2856 hw->phy.sfp_type == txgbe_sfp_type_1g_cu_core1 ||
2857 hw->phy.sfp_type == txgbe_sfp_type_1g_lx_core0 ||
2858 hw->phy.sfp_type == txgbe_sfp_type_1g_lx_core1 ||
2859 hw->phy.sfp_type == txgbe_sfp_type_1g_sx_core0 ||
2860 hw->phy.sfp_type == txgbe_sfp_type_1g_sx_core1) {
2861 *speed = TXGBE_LINK_SPEED_1GB_FULL;
2867 * Determine link capabilities based on the stored value of AUTOC,
2868 * which represents EEPROM defaults. If AUTOC value has not
2869 * been stored, use the current register values.
2871 if (hw->mac.orig_link_settings_stored)
2872 autoc = hw->mac.orig_autoc;
2874 autoc = hw->mac.autoc_read(hw);
2876 switch (autoc & TXGBE_AUTOC_LMS_MASK) {
2877 case TXGBE_AUTOC_LMS_1G_LINK_NO_AN:
2878 *speed = TXGBE_LINK_SPEED_1GB_FULL;
2882 case TXGBE_AUTOC_LMS_10G_LINK_NO_AN:
2883 *speed = TXGBE_LINK_SPEED_10GB_FULL;
2887 case TXGBE_AUTOC_LMS_1G_AN:
2888 *speed = TXGBE_LINK_SPEED_1GB_FULL;
2892 case TXGBE_AUTOC_LMS_10G:
2893 *speed = TXGBE_LINK_SPEED_10GB_FULL;
2897 case TXGBE_AUTOC_LMS_KX4_KX_KR:
2898 case TXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN:
2899 *speed = TXGBE_LINK_SPEED_UNKNOWN;
2900 if (autoc & TXGBE_AUTOC_KR_SUPP)
2901 *speed |= TXGBE_LINK_SPEED_10GB_FULL;
2902 if (autoc & TXGBE_AUTOC_KX4_SUPP)
2903 *speed |= TXGBE_LINK_SPEED_10GB_FULL;
2904 if (autoc & TXGBE_AUTOC_KX_SUPP)
2905 *speed |= TXGBE_LINK_SPEED_1GB_FULL;
2909 case TXGBE_AUTOC_LMS_KX4_KX_KR_SGMII:
2910 *speed = TXGBE_LINK_SPEED_100M_FULL;
2911 if (autoc & TXGBE_AUTOC_KR_SUPP)
2912 *speed |= TXGBE_LINK_SPEED_10GB_FULL;
2913 if (autoc & TXGBE_AUTOC_KX4_SUPP)
2914 *speed |= TXGBE_LINK_SPEED_10GB_FULL;
2915 if (autoc & TXGBE_AUTOC_KX_SUPP)
2916 *speed |= TXGBE_LINK_SPEED_1GB_FULL;
2920 case TXGBE_AUTOC_LMS_SGMII_1G_100M:
2921 *speed = TXGBE_LINK_SPEED_1GB_FULL |
2922 TXGBE_LINK_SPEED_100M_FULL |
2923 TXGBE_LINK_SPEED_10M_FULL;
2928 return TXGBE_ERR_LINK_SETUP;
2931 if (hw->phy.multispeed_fiber) {
2932 *speed |= TXGBE_LINK_SPEED_10GB_FULL |
2933 TXGBE_LINK_SPEED_1GB_FULL;
2935 /* QSFP must not enable full auto-negotiation
2936 * Limited autoneg is enabled at 1G
2938 if (hw->phy.media_type == txgbe_media_type_fiber_qsfp)
2948 * txgbe_get_media_type_raptor - Get media type
2949 * @hw: pointer to hardware structure
2951 * Returns the media type (fiber, copper, backplane)
2953 u32 txgbe_get_media_type_raptor(struct txgbe_hw *hw)
2957 DEBUGFUNC("txgbe_get_media_type_raptor");
2959 /* Detect if there is a copper PHY attached. */
2960 switch (hw->phy.type) {
2961 case txgbe_phy_cu_unknown:
2963 media_type = txgbe_media_type_copper;
2969 switch (hw->device_id) {
2970 case TXGBE_DEV_ID_RAPTOR_KR_KX_KX4:
2971 /* Default device ID is mezzanine card KX/KX4 */
2972 media_type = txgbe_media_type_backplane;
2974 case TXGBE_DEV_ID_RAPTOR_SFP:
2975 case TXGBE_DEV_ID_WX1820_SFP:
2976 media_type = txgbe_media_type_fiber;
2978 case TXGBE_DEV_ID_RAPTOR_QSFP:
2979 media_type = txgbe_media_type_fiber_qsfp;
2981 case TXGBE_DEV_ID_RAPTOR_XAUI:
2982 case TXGBE_DEV_ID_RAPTOR_SGMII:
2983 media_type = txgbe_media_type_copper;
2986 media_type = txgbe_media_type_unknown;
2994 * txgbe_start_mac_link_raptor - Setup MAC link settings
2995 * @hw: pointer to hardware structure
2996 * @autoneg_wait_to_complete: true when waiting for completion is needed
2998 * Configures link settings based on values in the txgbe_hw struct.
2999 * Restarts the link. Performs autonegotiation if needed.
3001 s32 txgbe_start_mac_link_raptor(struct txgbe_hw *hw,
3002 bool autoneg_wait_to_complete)
3005 bool got_lock = false;
3007 DEBUGFUNC("txgbe_start_mac_link_raptor");
3009 UNREFERENCED_PARAMETER(autoneg_wait_to_complete);
3011 /* reset_pipeline requires us to hold this lock as it writes to
3014 if (txgbe_verify_lesm_fw_enabled_raptor(hw)) {
3015 status = hw->mac.acquire_swfw_sync(hw, TXGBE_MNGSEM_SWPHY);
3023 txgbe_reset_pipeline_raptor(hw);
3026 hw->mac.release_swfw_sync(hw, TXGBE_MNGSEM_SWPHY);
3028 /* Add delay to filter out noises during initial link setup */
3036 * txgbe_disable_tx_laser_multispeed_fiber - Disable Tx laser
3037 * @hw: pointer to hardware structure
3039 * The base drivers may require better control over SFP+ module
3040 * PHY states. This includes selectively shutting down the Tx
3041 * laser on the PHY, effectively halting physical link.
3043 void txgbe_disable_tx_laser_multispeed_fiber(struct txgbe_hw *hw)
3045 u32 esdp_reg = rd32(hw, TXGBE_GPIODATA);
3047 /* Blocked by MNG FW so bail */
3048 if (txgbe_check_reset_blocked(hw))
3051 /* Disable Tx laser; allow 100us to go dark per spec */
3052 esdp_reg |= (TXGBE_GPIOBIT_0 | TXGBE_GPIOBIT_1);
3053 wr32(hw, TXGBE_GPIODATA, esdp_reg);
3059 * txgbe_enable_tx_laser_multispeed_fiber - Enable Tx laser
3060 * @hw: pointer to hardware structure
3062 * The base drivers may require better control over SFP+ module
3063 * PHY states. This includes selectively turning on the Tx
3064 * laser on the PHY, effectively starting physical link.
3066 void txgbe_enable_tx_laser_multispeed_fiber(struct txgbe_hw *hw)
3068 u32 esdp_reg = rd32(hw, TXGBE_GPIODATA);
3070 /* Enable Tx laser; allow 100ms to light up */
3071 esdp_reg &= ~(TXGBE_GPIOBIT_0 | TXGBE_GPIOBIT_1);
3072 wr32(hw, TXGBE_GPIODATA, esdp_reg);
3078 * txgbe_flap_tx_laser_multispeed_fiber - Flap Tx laser
3079 * @hw: pointer to hardware structure
3081 * When the driver changes the link speeds that it can support,
3082 * it sets autotry_restart to true to indicate that we need to
3083 * initiate a new autotry session with the link partner. To do
3084 * so, we set the speed then disable and re-enable the Tx laser, to
3085 * alert the link partner that it also needs to restart autotry on its
3086 * end. This is consistent with true clause 37 autoneg, which also
3087 * involves a loss of signal.
3089 void txgbe_flap_tx_laser_multispeed_fiber(struct txgbe_hw *hw)
3091 DEBUGFUNC("txgbe_flap_tx_laser_multispeed_fiber");
3093 /* Blocked by MNG FW so bail */
3094 if (txgbe_check_reset_blocked(hw))
3097 if (hw->mac.autotry_restart) {
3098 txgbe_disable_tx_laser_multispeed_fiber(hw);
3099 txgbe_enable_tx_laser_multispeed_fiber(hw);
3100 hw->mac.autotry_restart = false;
3105 * txgbe_set_hard_rate_select_speed - Set module link speed
3106 * @hw: pointer to hardware structure
3107 * @speed: link speed to set
3109 * Set module link speed via RS0/RS1 rate select pins.
3111 void txgbe_set_hard_rate_select_speed(struct txgbe_hw *hw,
3114 u32 esdp_reg = rd32(hw, TXGBE_GPIODATA);
3117 case TXGBE_LINK_SPEED_10GB_FULL:
3118 esdp_reg |= (TXGBE_GPIOBIT_4 | TXGBE_GPIOBIT_5);
3120 case TXGBE_LINK_SPEED_1GB_FULL:
3121 esdp_reg &= ~(TXGBE_GPIOBIT_4 | TXGBE_GPIOBIT_5);
3124 DEBUGOUT("Invalid fixed module speed\n");
3128 wr32(hw, TXGBE_GPIODATA, esdp_reg);
3133 * txgbe_setup_mac_link_smartspeed - Set MAC link speed using SmartSpeed
3134 * @hw: pointer to hardware structure
3135 * @speed: new link speed
3136 * @autoneg_wait_to_complete: true when waiting for completion is needed
3138 * Implements the Intel SmartSpeed algorithm.
3140 s32 txgbe_setup_mac_link_smartspeed(struct txgbe_hw *hw,
3142 bool autoneg_wait_to_complete)
3145 u32 link_speed = TXGBE_LINK_SPEED_UNKNOWN;
3147 bool link_up = false;
3148 u32 autoc_reg = rd32_epcs(hw, SR_AN_MMD_ADV_REG1);
3150 DEBUGFUNC("txgbe_setup_mac_link_smartspeed");
3152 /* Set autoneg_advertised value based on input link speed */
3153 hw->phy.autoneg_advertised = 0;
3155 if (speed & TXGBE_LINK_SPEED_10GB_FULL)
3156 hw->phy.autoneg_advertised |= TXGBE_LINK_SPEED_10GB_FULL;
3158 if (speed & TXGBE_LINK_SPEED_1GB_FULL)
3159 hw->phy.autoneg_advertised |= TXGBE_LINK_SPEED_1GB_FULL;
3161 if (speed & TXGBE_LINK_SPEED_100M_FULL)
3162 hw->phy.autoneg_advertised |= TXGBE_LINK_SPEED_100M_FULL;
3165 * Implement Intel SmartSpeed algorithm. SmartSpeed will reduce the
3166 * autoneg advertisement if link is unable to be established at the
3167 * highest negotiated rate. This can sometimes happen due to integrity
3168 * issues with the physical media connection.
3171 /* First, try to get link with full advertisement */
3172 hw->phy.smart_speed_active = false;
3173 for (j = 0; j < TXGBE_SMARTSPEED_MAX_RETRIES; j++) {
3174 status = txgbe_setup_mac_link(hw, speed,
3175 autoneg_wait_to_complete);
3180 * Wait for the controller to acquire link. Per IEEE 802.3ap,
3181 * Section 73.10.2, we may have to wait up to 500ms if KR is
3182 * attempted, or 200ms if KX/KX4/BX/BX4 is attempted, per
3183 * Table 9 in the AN MAS.
3185 for (i = 0; i < 5; i++) {
3188 /* If we have link, just jump out */
3189 status = hw->mac.check_link(hw, &link_speed, &link_up,
3200 * We didn't get link. If we advertised KR plus one of KX4/KX
3201 * (or BX4/BX), then disable KR and try again.
3203 if (((autoc_reg & TXGBE_AUTOC_KR_SUPP) == 0) ||
3204 ((autoc_reg & TXGBE_AUTOC_KX_SUPP) == 0 &&
3205 (autoc_reg & TXGBE_AUTOC_KX4_SUPP) == 0))
3208 /* Turn SmartSpeed on to disable KR support */
3209 hw->phy.smart_speed_active = true;
3210 status = txgbe_setup_mac_link(hw, speed,
3211 autoneg_wait_to_complete);
3216 * Wait for the controller to acquire link. 600ms will allow for
3217 * the AN link_fail_inhibit_timer as well for multiple cycles of
3218 * parallel detect, both 10g and 1g. This allows for the maximum
3219 * connect attempts as defined in the AN MAS table 73-7.
3221 for (i = 0; i < 6; i++) {
3224 /* If we have link, just jump out */
3225 status = hw->mac.check_link(hw, &link_speed, &link_up, false);
3233 /* We didn't get link. Turn SmartSpeed back off. */
3234 hw->phy.smart_speed_active = false;
3235 status = txgbe_setup_mac_link(hw, speed,
3236 autoneg_wait_to_complete);
3239 if (link_up && link_speed == TXGBE_LINK_SPEED_1GB_FULL)
3240 DEBUGOUT("Smartspeed has downgraded the link speed "
3241 "from the maximum advertised\n");
3246 * txgbe_setup_mac_link - Set MAC link speed
3247 * @hw: pointer to hardware structure
3248 * @speed: new link speed
3249 * @autoneg_wait_to_complete: true when waiting for completion is needed
3251 * Set the link speed in the AUTOC register and restarts link.
3253 s32 txgbe_setup_mac_link(struct txgbe_hw *hw,
3255 bool autoneg_wait_to_complete)
3257 bool autoneg = false;
3260 u64 autoc = hw->mac.autoc_read(hw);
3261 u64 pma_pmd_10gs = autoc & TXGBE_AUTOC_10GS_PMA_PMD_MASK;
3262 u64 pma_pmd_1g = autoc & TXGBE_AUTOC_1G_PMA_PMD_MASK;
3263 u64 link_mode = autoc & TXGBE_AUTOC_LMS_MASK;
3264 u64 current_autoc = autoc;
3268 u32 link_capabilities = TXGBE_LINK_SPEED_UNKNOWN;
3270 DEBUGFUNC("txgbe_setup_mac_link");
3272 /* Check to see if speed passed in is supported. */
3273 status = hw->mac.get_link_capabilities(hw,
3274 &link_capabilities, &autoneg);
3278 speed &= link_capabilities;
3279 if (speed == TXGBE_LINK_SPEED_UNKNOWN)
3280 return TXGBE_ERR_LINK_SETUP;
3282 /* Use stored value (EEPROM defaults) of AUTOC to find KR/KX4 support*/
3283 if (hw->mac.orig_link_settings_stored)
3284 orig_autoc = hw->mac.orig_autoc;
3288 link_mode = autoc & TXGBE_AUTOC_LMS_MASK;
3289 pma_pmd_1g = autoc & TXGBE_AUTOC_1G_PMA_PMD_MASK;
3291 if (link_mode == TXGBE_AUTOC_LMS_KX4_KX_KR ||
3292 link_mode == TXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
3293 link_mode == TXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
3294 /* Set KX4/KX/KR support according to speed requested */
3295 autoc &= ~(TXGBE_AUTOC_KX_SUPP |
3296 TXGBE_AUTOC_KX4_SUPP |
3297 TXGBE_AUTOC_KR_SUPP);
3298 if (speed & TXGBE_LINK_SPEED_10GB_FULL) {
3299 if (orig_autoc & TXGBE_AUTOC_KX4_SUPP)
3300 autoc |= TXGBE_AUTOC_KX4_SUPP;
3301 if ((orig_autoc & TXGBE_AUTOC_KR_SUPP) &&
3302 !hw->phy.smart_speed_active)
3303 autoc |= TXGBE_AUTOC_KR_SUPP;
3305 if (speed & TXGBE_LINK_SPEED_1GB_FULL)
3306 autoc |= TXGBE_AUTOC_KX_SUPP;
3307 } else if ((pma_pmd_1g == TXGBE_AUTOC_1G_SFI) &&
3308 (link_mode == TXGBE_AUTOC_LMS_1G_LINK_NO_AN ||
3309 link_mode == TXGBE_AUTOC_LMS_1G_AN)) {
3310 /* Switch from 1G SFI to 10G SFI if requested */
3311 if (speed == TXGBE_LINK_SPEED_10GB_FULL &&
3312 pma_pmd_10gs == TXGBE_AUTOC_10GS_SFI) {
3313 autoc &= ~TXGBE_AUTOC_LMS_MASK;
3314 autoc |= TXGBE_AUTOC_LMS_10G;
3316 } else if ((pma_pmd_10gs == TXGBE_AUTOC_10GS_SFI) &&
3317 (link_mode == TXGBE_AUTOC_LMS_10G)) {
3318 /* Switch from 10G SFI to 1G SFI if requested */
3319 if (speed == TXGBE_LINK_SPEED_1GB_FULL &&
3320 pma_pmd_1g == TXGBE_AUTOC_1G_SFI) {
3321 autoc &= ~TXGBE_AUTOC_LMS_MASK;
3322 if (autoneg || hw->phy.type == txgbe_phy_qsfp_intel)
3323 autoc |= TXGBE_AUTOC_LMS_1G_AN;
3325 autoc |= TXGBE_AUTOC_LMS_1G_LINK_NO_AN;
3329 if (autoc == current_autoc)
3332 autoc &= ~TXGBE_AUTOC_SPEED_MASK;
3333 autoc |= TXGBE_AUTOC_SPEED(speed);
3334 autoc |= (autoneg ? TXGBE_AUTOC_AUTONEG : 0);
3337 hw->mac.autoc_write(hw, autoc);
3339 /* Only poll for autoneg to complete if specified to do so */
3340 if (autoneg_wait_to_complete) {
3341 if (link_mode == TXGBE_AUTOC_LMS_KX4_KX_KR ||
3342 link_mode == TXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
3343 link_mode == TXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
3344 links_reg = 0; /*Just in case Autoneg time=0*/
3345 for (i = 0; i < TXGBE_AUTO_NEG_TIME; i++) {
3346 links_reg = rd32(hw, TXGBE_PORTSTAT);
3347 if (links_reg & TXGBE_PORTSTAT_UP)
3351 if (!(links_reg & TXGBE_PORTSTAT_UP)) {
3352 status = TXGBE_ERR_AUTONEG_NOT_COMPLETE;
3353 DEBUGOUT("Autoneg did not complete.\n");
3358 /* Add delay to filter out noises during initial link setup */
3365 * txgbe_setup_copper_link_raptor - Set the PHY autoneg advertised field
3366 * @hw: pointer to hardware structure
3367 * @speed: new link speed
3368 * @autoneg_wait_to_complete: true if waiting is needed to complete
3370 * Restarts link on PHY and MAC based on settings passed in.
3372 static s32 txgbe_setup_copper_link_raptor(struct txgbe_hw *hw,
3374 bool autoneg_wait_to_complete)
3378 DEBUGFUNC("txgbe_setup_copper_link_raptor");
3380 /* Setup the PHY according to input speed */
3381 status = hw->phy.setup_link_speed(hw, speed,
3382 autoneg_wait_to_complete);
3384 txgbe_start_mac_link_raptor(hw, autoneg_wait_to_complete);
3390 txgbe_check_flash_load(struct txgbe_hw *hw, u32 check_bit)
3395 /* if there's flash existing */
3396 if (!(rd32(hw, TXGBE_SPISTAT) & TXGBE_SPISTAT_BPFLASH)) {
3397 /* wait hw load flash done */
3398 for (i = 0; i < 10; i++) {
3399 reg = rd32(hw, TXGBE_ILDRSTAT);
3400 if (!(reg & check_bit)) {
3407 err = TXGBE_ERR_FLASH_LOADING_FAILED;
3413 txgbe_reset_misc(struct txgbe_hw *hw)
3418 wr32(hw, TXGBE_ISBADDRL, hw->isb_dma & 0x00000000FFFFFFFF);
3419 wr32(hw, TXGBE_ISBADDRH, hw->isb_dma >> 32);
3421 value = rd32_epcs(hw, SR_XS_PCS_CTRL2);
3422 if ((value & 0x3) != SR_PCS_CTRL2_TYPE_SEL_X)
3423 hw->link_status = TXGBE_LINK_STATUS_NONE;
3425 /* receive packets that size > 2048 */
3426 wr32m(hw, TXGBE_MACRXCFG,
3427 TXGBE_MACRXCFG_JUMBO, TXGBE_MACRXCFG_JUMBO);
3429 wr32m(hw, TXGBE_FRMSZ, TXGBE_FRMSZ_MAX_MASK,
3430 TXGBE_FRMSZ_MAX(TXGBE_FRAME_SIZE_DFT));
3432 /* clear counters on read */
3433 wr32m(hw, TXGBE_MACCNTCTL,
3434 TXGBE_MACCNTCTL_RC, TXGBE_MACCNTCTL_RC);
3436 wr32m(hw, TXGBE_RXFCCFG,
3437 TXGBE_RXFCCFG_FC, TXGBE_RXFCCFG_FC);
3438 wr32m(hw, TXGBE_TXFCCFG,
3439 TXGBE_TXFCCFG_FC, TXGBE_TXFCCFG_FC);
3441 wr32m(hw, TXGBE_MACRXFLT,
3442 TXGBE_MACRXFLT_PROMISC, TXGBE_MACRXFLT_PROMISC);
3444 wr32m(hw, TXGBE_RSTSTAT,
3445 TXGBE_RSTSTAT_TMRINIT_MASK, TXGBE_RSTSTAT_TMRINIT(30));
3447 /* errata 4: initialize mng flex tbl and wakeup flex tbl*/
3448 wr32(hw, TXGBE_MNGFLEXSEL, 0);
3449 for (i = 0; i < 16; i++) {
3450 wr32(hw, TXGBE_MNGFLEXDWL(i), 0);
3451 wr32(hw, TXGBE_MNGFLEXDWH(i), 0);
3452 wr32(hw, TXGBE_MNGFLEXMSK(i), 0);
3454 wr32(hw, TXGBE_LANFLEXSEL, 0);
3455 for (i = 0; i < 16; i++) {
3456 wr32(hw, TXGBE_LANFLEXDWL(i), 0);
3457 wr32(hw, TXGBE_LANFLEXDWH(i), 0);
3458 wr32(hw, TXGBE_LANFLEXMSK(i), 0);
3461 /* set pause frame dst mac addr */
3462 wr32(hw, TXGBE_RXPBPFCDMACL, 0xC2000001);
3463 wr32(hw, TXGBE_RXPBPFCDMACH, 0x0180);
3465 hw->mac.init_thermal_sensor_thresh(hw);
3467 /* enable mac transmitter */
3468 wr32m(hw, TXGBE_MACTXCFG, TXGBE_MACTXCFG_TXE, TXGBE_MACTXCFG_TXE);
3470 for (i = 0; i < 4; i++)
3471 wr32m(hw, TXGBE_IVAR(i), 0x80808080, 0);
3475 * txgbe_reset_hw - Perform hardware reset
3476 * @hw: pointer to hardware structure
3478 * Resets the hardware by resetting the transmit and receive units, masks
3479 * and clears all interrupts, perform a PHY reset, and perform a link (MAC)
3482 s32 txgbe_reset_hw(struct txgbe_hw *hw)
3487 DEBUGFUNC("txgbe_reset_hw");
3489 /* Call adapter stop to disable tx/rx and clear interrupts */
3490 status = hw->mac.stop_hw(hw);
3494 /* flush pending Tx transactions */
3495 txgbe_clear_tx_pending(hw);
3497 /* Identify PHY and related function pointers */
3498 status = hw->phy.init(hw);
3499 if (status == TXGBE_ERR_SFP_NOT_SUPPORTED)
3502 /* Setup SFP module if there is one present. */
3503 if (hw->phy.sfp_setup_needed) {
3504 status = hw->mac.setup_sfp(hw);
3505 hw->phy.sfp_setup_needed = false;
3507 if (status == TXGBE_ERR_SFP_NOT_SUPPORTED)
3511 if (!hw->phy.reset_disable)
3514 /* remember AUTOC from before we reset */
3515 autoc = hw->mac.autoc_read(hw);
3519 * Issue global reset to the MAC. Needs to be SW reset if link is up.
3520 * If link reset is used when link is up, it might reset the PHY when
3521 * mng is using it. If link is down or the flag to force full link
3522 * reset is set, then perform link reset.
3524 if (txgbe_mng_present(hw)) {
3525 txgbe_hic_reset(hw);
3527 wr32(hw, TXGBE_RST, TXGBE_RST_LAN(hw->bus.lan_id));
3532 txgbe_reset_misc(hw);
3534 if (hw->bus.lan_id == 0) {
3535 status = txgbe_check_flash_load(hw,
3536 TXGBE_ILDRSTAT_SWRST_LAN0);
3538 status = txgbe_check_flash_load(hw,
3539 TXGBE_ILDRSTAT_SWRST_LAN1);
3547 * Double resets are required for recovery from certain error
3548 * conditions. Between resets, it is necessary to stall to
3549 * allow time for any pending HW events to complete.
3551 if (hw->mac.flags & TXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
3552 hw->mac.flags &= ~TXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
3557 * Store the original AUTOC/AUTOC2 values if they have not been
3558 * stored off yet. Otherwise restore the stored original
3559 * values since the reset operation sets back to defaults.
3561 if (!hw->mac.orig_link_settings_stored) {
3562 hw->mac.orig_autoc = hw->mac.autoc_read(hw);
3563 hw->mac.autoc_write(hw, hw->mac.orig_autoc);
3564 hw->mac.orig_link_settings_stored = true;
3566 hw->mac.orig_autoc = autoc;
3569 /* Store the permanent mac address */
3570 hw->mac.get_mac_addr(hw, hw->mac.perm_addr);
3573 * Store MAC address from RAR0, clear receive address registers, and
3574 * clear the multicast table. Also reset num_rar_entries to 128,
3575 * since we modify this value when programming the SAN MAC address.
3577 hw->mac.num_rar_entries = 128;
3578 hw->mac.init_rx_addrs(hw);
3580 /* Store the permanent SAN mac address */
3581 hw->mac.get_san_mac_addr(hw, hw->mac.san_addr);
3583 /* Add the SAN MAC address to the RAR only if it's a valid address */
3584 if (txgbe_validate_mac_addr(hw->mac.san_addr) == 0) {
3585 /* Save the SAN MAC RAR index */
3586 hw->mac.san_mac_rar_index = hw->mac.num_rar_entries - 1;
3588 hw->mac.set_rar(hw, hw->mac.san_mac_rar_index,
3589 hw->mac.san_addr, 0, true);
3591 /* clear VMDq pool/queue selection for this RAR */
3592 hw->mac.clear_vmdq(hw, hw->mac.san_mac_rar_index,
3595 /* Reserve the last RAR for the SAN MAC address */
3596 hw->mac.num_rar_entries--;
3599 /* Store the alternative WWNN/WWPN prefix */
3600 hw->mac.get_wwn_prefix(hw, &hw->mac.wwnn_prefix,
3601 &hw->mac.wwpn_prefix);
3607 * txgbe_start_hw_raptor - Prepare hardware for Tx/Rx
3608 * @hw: pointer to hardware structure
3610 * Starts the hardware using the generic start_hw function
3611 * and the generation start_hw function.
3612 * Then performs revision-specific operations, if any.
3614 s32 txgbe_start_hw_raptor(struct txgbe_hw *hw)
3618 DEBUGFUNC("txgbe_start_hw_raptor");
3620 err = txgbe_start_hw(hw);
3624 err = txgbe_start_hw_gen2(hw);
3628 /* We need to run link autotry after the driver loads */
3629 hw->mac.autotry_restart = true;
3636 * txgbe_enable_rx_dma_raptor - Enable the Rx DMA unit
3637 * @hw: pointer to hardware structure
3638 * @regval: register value to write to RXCTRL
3640 * Enables the Rx DMA unit
3642 s32 txgbe_enable_rx_dma_raptor(struct txgbe_hw *hw, u32 regval)
3644 DEBUGFUNC("txgbe_enable_rx_dma_raptor");
3647 * Workaround silicon errata when enabling the Rx datapath.
3648 * If traffic is incoming before we enable the Rx unit, it could hang
3649 * the Rx DMA unit. Therefore, make sure the security engine is
3650 * completely disabled prior to enabling the Rx unit.
3653 hw->mac.disable_sec_rx_path(hw);
3655 if (regval & TXGBE_PBRXCTL_ENA)
3656 txgbe_enable_rx(hw);
3658 txgbe_disable_rx(hw);
3660 hw->mac.enable_sec_rx_path(hw);
3666 * txgbe_verify_lesm_fw_enabled_raptor - Checks LESM FW module state.
3667 * @hw: pointer to hardware structure
3669 * Returns true if the LESM FW module is present and enabled. Otherwise
3670 * returns false. Smart Speed must be disabled if LESM FW module is enabled.
3672 bool txgbe_verify_lesm_fw_enabled_raptor(struct txgbe_hw *hw)
3674 bool lesm_enabled = false;
3675 u16 fw_offset, fw_lesm_param_offset, fw_lesm_state;
3678 DEBUGFUNC("txgbe_verify_lesm_fw_enabled_raptor");
3680 /* get the offset to the Firmware Module block */
3681 status = hw->rom.read16(hw, TXGBE_FW_PTR, &fw_offset);
3683 if (status != 0 || fw_offset == 0 || fw_offset == 0xFFFF)
3686 /* get the offset to the LESM Parameters block */
3687 status = hw->rom.read16(hw, (fw_offset +
3688 TXGBE_FW_LESM_PARAMETERS_PTR),
3689 &fw_lesm_param_offset);
3692 fw_lesm_param_offset == 0 || fw_lesm_param_offset == 0xFFFF)
3695 /* get the LESM state word */
3696 status = hw->rom.read16(hw, (fw_lesm_param_offset +
3697 TXGBE_FW_LESM_STATE_1),
3700 if (status == 0 && (fw_lesm_state & TXGBE_FW_LESM_STATE_ENABLED))
3701 lesm_enabled = true;
3704 lesm_enabled = false;
3705 return lesm_enabled;
3709 * txgbe_reset_pipeline_raptor - perform pipeline reset
3711 * @hw: pointer to hardware structure
3713 * Reset pipeline by asserting Restart_AN together with LMS change to ensure
3714 * full pipeline reset. This function assumes the SW/FW lock is held.
3716 s32 txgbe_reset_pipeline_raptor(struct txgbe_hw *hw)
3721 autoc = hw->mac.autoc_read(hw);
3723 /* Enable link if disabled in NVM */
3724 if (autoc & TXGBE_AUTOC_LINK_DIA_MASK)
3725 autoc &= ~TXGBE_AUTOC_LINK_DIA_MASK;
3727 autoc |= TXGBE_AUTOC_AN_RESTART;
3728 /* Write AUTOC register with toggled LMS[2] bit and Restart_AN */
3729 hw->mac.autoc_write(hw, autoc ^ TXGBE_AUTOC_LMS_AN);
3731 /* Write AUTOC register with original LMS field and Restart_AN */
3732 hw->mac.autoc_write(hw, autoc);