1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2015-2020
5 #include "txgbe_type.h"
9 #include "txgbe_eeprom.h"
10 #include "txgbe_mng.h"
13 #define TXGBE_RAPTOR_MAX_TX_QUEUES 128
14 #define TXGBE_RAPTOR_MAX_RX_QUEUES 128
15 #define TXGBE_RAPTOR_RAR_ENTRIES 128
16 #define TXGBE_RAPTOR_MC_TBL_SIZE 128
17 #define TXGBE_RAPTOR_VFT_TBL_SIZE 128
18 #define TXGBE_RAPTOR_RX_PB_SIZE 512 /*KB*/
20 static s32 txgbe_setup_copper_link_raptor(struct txgbe_hw *hw,
22 bool autoneg_wait_to_complete);
24 static s32 txgbe_mta_vector(struct txgbe_hw *hw, u8 *mc_addr);
25 static s32 txgbe_get_san_mac_addr_offset(struct txgbe_hw *hw,
29 * txgbe_start_hw - Prepare hardware for Tx/Rx
30 * @hw: pointer to hardware structure
32 * Starts the hardware by filling the bus info structure and media type, clears
33 * all on chip counters, initializes receive address registers, multicast
34 * table, VLAN filter table, calls routine to set up link and flow control
35 * settings, and leaves transmit and receive units disabled and uninitialized
37 s32 txgbe_start_hw(struct txgbe_hw *hw)
41 DEBUGFUNC("txgbe_start_hw");
43 /* Set the media type */
44 hw->phy.media_type = hw->phy.get_media_type(hw);
46 /* Clear the VLAN filter table */
47 hw->mac.clear_vfta(hw);
49 /* Clear statistics registers */
50 hw->mac.clear_hw_cntrs(hw);
52 /* Cache bit indicating need for crosstalk fix */
53 switch (hw->mac.type) {
54 case txgbe_mac_raptor:
55 hw->mac.get_device_caps(hw, &device_caps);
56 if (device_caps & TXGBE_DEVICE_CAPS_NO_CROSSTALK_WR)
57 hw->need_crosstalk_fix = false;
59 hw->need_crosstalk_fix = true;
62 hw->need_crosstalk_fix = false;
66 /* Clear adapter stopped flag */
67 hw->adapter_stopped = false;
73 * txgbe_start_hw_gen2 - Init sequence for common device family
74 * @hw: pointer to hw structure
76 * Performs the init sequence common to the second generation
79 s32 txgbe_start_hw_gen2(struct txgbe_hw *hw)
83 /* Clear the rate limiters */
84 for (i = 0; i < hw->mac.max_tx_queues; i++) {
85 wr32(hw, TXGBE_ARBPOOLIDX, i);
86 wr32(hw, TXGBE_ARBTXRATE, 0);
90 /* We need to run link autotry after the driver loads */
91 hw->mac.autotry_restart = true;
97 * txgbe_init_hw - Generic hardware initialization
98 * @hw: pointer to hardware structure
100 * Initialize the hardware by resetting the hardware, filling the bus info
101 * structure and media type, clears all on chip counters, initializes receive
102 * address registers, multicast table, VLAN filter table, calls routine to set
103 * up link and flow control settings, and leaves transmit and receive units
104 * disabled and uninitialized
106 s32 txgbe_init_hw(struct txgbe_hw *hw)
110 DEBUGFUNC("txgbe_init_hw");
112 /* Reset the hardware */
113 status = hw->mac.reset_hw(hw);
114 if (status == 0 || status == TXGBE_ERR_SFP_NOT_PRESENT) {
116 status = hw->mac.start_hw(hw);
120 DEBUGOUT("Failed to initialize HW, STATUS = %d\n", status);
126 * txgbe_clear_hw_cntrs - Generic clear hardware counters
127 * @hw: pointer to hardware structure
129 * Clears all hardware statistics counters by reading them from the hardware
130 * Statistics counters are clear on read.
132 s32 txgbe_clear_hw_cntrs(struct txgbe_hw *hw)
136 DEBUGFUNC("txgbe_clear_hw_cntrs");
139 /* don't write clear queue stats */
140 for (i = 0; i < TXGBE_MAX_QP; i++) {
141 hw->qp_last[i].rx_qp_packets = 0;
142 hw->qp_last[i].tx_qp_packets = 0;
143 hw->qp_last[i].rx_qp_bytes = 0;
144 hw->qp_last[i].tx_qp_bytes = 0;
145 hw->qp_last[i].rx_qp_mc_packets = 0;
149 for (i = 0; i < TXGBE_MAX_UP; i++) {
150 rd32(hw, TXGBE_PBRXUPXON(i));
151 rd32(hw, TXGBE_PBRXUPXOFF(i));
152 rd32(hw, TXGBE_PBTXUPXON(i));
153 rd32(hw, TXGBE_PBTXUPXOFF(i));
154 rd32(hw, TXGBE_PBTXUPOFF(i));
156 rd32(hw, TXGBE_PBRXMISS(i));
158 rd32(hw, TXGBE_PBRXLNKXON);
159 rd32(hw, TXGBE_PBRXLNKXOFF);
160 rd32(hw, TXGBE_PBTXLNKXON);
161 rd32(hw, TXGBE_PBTXLNKXOFF);
164 rd32(hw, TXGBE_DMARXPKT);
165 rd32(hw, TXGBE_DMATXPKT);
167 rd64(hw, TXGBE_DMARXOCTL);
168 rd64(hw, TXGBE_DMATXOCTL);
171 rd64(hw, TXGBE_MACRXERRCRCL);
172 rd64(hw, TXGBE_MACRXMPKTL);
173 rd64(hw, TXGBE_MACTXMPKTL);
175 rd64(hw, TXGBE_MACRXPKTL);
176 rd64(hw, TXGBE_MACTXPKTL);
177 rd64(hw, TXGBE_MACRXGBOCTL);
179 rd64(hw, TXGBE_MACRXOCTL);
180 rd32(hw, TXGBE_MACTXOCTL);
182 rd64(hw, TXGBE_MACRX1TO64L);
183 rd64(hw, TXGBE_MACRX65TO127L);
184 rd64(hw, TXGBE_MACRX128TO255L);
185 rd64(hw, TXGBE_MACRX256TO511L);
186 rd64(hw, TXGBE_MACRX512TO1023L);
187 rd64(hw, TXGBE_MACRX1024TOMAXL);
188 rd64(hw, TXGBE_MACTX1TO64L);
189 rd64(hw, TXGBE_MACTX65TO127L);
190 rd64(hw, TXGBE_MACTX128TO255L);
191 rd64(hw, TXGBE_MACTX256TO511L);
192 rd64(hw, TXGBE_MACTX512TO1023L);
193 rd64(hw, TXGBE_MACTX1024TOMAXL);
195 rd64(hw, TXGBE_MACRXERRLENL);
196 rd32(hw, TXGBE_MACRXOVERSIZE);
197 rd32(hw, TXGBE_MACRXJABBER);
200 rd32(hw, TXGBE_FCOECRC);
201 rd32(hw, TXGBE_FCOELAST);
202 rd32(hw, TXGBE_FCOERPDC);
203 rd32(hw, TXGBE_FCOEPRC);
204 rd32(hw, TXGBE_FCOEPTC);
205 rd32(hw, TXGBE_FCOEDWRC);
206 rd32(hw, TXGBE_FCOEDWTC);
208 /* Flow Director Stats */
209 rd32(hw, TXGBE_FDIRMATCH);
210 rd32(hw, TXGBE_FDIRMISS);
211 rd32(hw, TXGBE_FDIRUSED);
212 rd32(hw, TXGBE_FDIRUSED);
213 rd32(hw, TXGBE_FDIRFAIL);
214 rd32(hw, TXGBE_FDIRFAIL);
217 rd32(hw, TXGBE_LSECTX_UTPKT);
218 rd32(hw, TXGBE_LSECTX_ENCPKT);
219 rd32(hw, TXGBE_LSECTX_PROTPKT);
220 rd32(hw, TXGBE_LSECTX_ENCOCT);
221 rd32(hw, TXGBE_LSECTX_PROTOCT);
222 rd32(hw, TXGBE_LSECRX_UTPKT);
223 rd32(hw, TXGBE_LSECRX_BTPKT);
224 rd32(hw, TXGBE_LSECRX_NOSCIPKT);
225 rd32(hw, TXGBE_LSECRX_UNSCIPKT);
226 rd32(hw, TXGBE_LSECRX_DECOCT);
227 rd32(hw, TXGBE_LSECRX_VLDOCT);
228 rd32(hw, TXGBE_LSECRX_UNCHKPKT);
229 rd32(hw, TXGBE_LSECRX_DLYPKT);
230 rd32(hw, TXGBE_LSECRX_LATEPKT);
231 for (i = 0; i < 2; i++) {
232 rd32(hw, TXGBE_LSECRX_OKPKT(i));
233 rd32(hw, TXGBE_LSECRX_INVPKT(i));
234 rd32(hw, TXGBE_LSECRX_BADPKT(i));
236 rd32(hw, TXGBE_LSECRX_INVSAPKT);
237 rd32(hw, TXGBE_LSECRX_BADSAPKT);
243 * txgbe_get_mac_addr - Generic get MAC address
244 * @hw: pointer to hardware structure
245 * @mac_addr: Adapter MAC address
247 * Reads the adapter's MAC address from first Receive Address Register (RAR0)
248 * A reset of the adapter must be performed prior to calling this function
249 * in order for the MAC address to have been loaded from the EEPROM into RAR0
251 s32 txgbe_get_mac_addr(struct txgbe_hw *hw, u8 *mac_addr)
257 DEBUGFUNC("txgbe_get_mac_addr");
259 wr32(hw, TXGBE_ETHADDRIDX, 0);
260 rar_high = rd32(hw, TXGBE_ETHADDRH);
261 rar_low = rd32(hw, TXGBE_ETHADDRL);
263 for (i = 0; i < 2; i++)
264 mac_addr[i] = (u8)(rar_high >> (1 - i) * 8);
266 for (i = 0; i < 4; i++)
267 mac_addr[i + 2] = (u8)(rar_low >> (3 - i) * 8);
273 * txgbe_set_lan_id_multi_port - Set LAN id for PCIe multiple port devices
274 * @hw: pointer to the HW structure
276 * Determines the LAN function id by reading memory-mapped registers and swaps
277 * the port value if requested, and set MAC instance for devices.
279 void txgbe_set_lan_id_multi_port(struct txgbe_hw *hw)
281 struct txgbe_bus_info *bus = &hw->bus;
284 DEBUGFUNC("txgbe_set_lan_id_multi_port_pcie");
286 reg = rd32(hw, TXGBE_PORTSTAT);
287 bus->lan_id = TXGBE_PORTSTAT_ID(reg);
289 /* check for single port */
290 reg = rd32(hw, TXGBE_PWR);
291 if (TXGBE_PWR_LANID(reg) == TXGBE_PWR_LANID_SWAP)
294 bus->func = bus->lan_id;
298 * txgbe_stop_hw - Generic stop Tx/Rx units
299 * @hw: pointer to hardware structure
301 * Sets the adapter_stopped flag within txgbe_hw struct. Clears interrupts,
302 * disables transmit and receive units. The adapter_stopped flag is used by
303 * the shared code and drivers to determine if the adapter is in a stopped
304 * state and should not touch the hardware.
306 s32 txgbe_stop_hw(struct txgbe_hw *hw)
311 DEBUGFUNC("txgbe_stop_hw");
314 * Set the adapter_stopped flag so other driver functions stop touching
317 hw->adapter_stopped = true;
319 /* Disable the receive unit */
320 txgbe_disable_rx(hw);
322 /* Clear interrupt mask to stop interrupts from being generated */
323 wr32(hw, TXGBE_IENMISC, 0);
324 wr32(hw, TXGBE_IMS(0), TXGBE_IMS_MASK);
325 wr32(hw, TXGBE_IMS(1), TXGBE_IMS_MASK);
327 /* Clear any pending interrupts, flush previous writes */
328 wr32(hw, TXGBE_ICRMISC, TXGBE_ICRMISC_MASK);
329 wr32(hw, TXGBE_ICR(0), TXGBE_ICR_MASK);
330 wr32(hw, TXGBE_ICR(1), TXGBE_ICR_MASK);
332 /* Disable the transmit unit. Each queue must be disabled. */
333 for (i = 0; i < hw->mac.max_tx_queues; i++)
334 wr32(hw, TXGBE_TXCFG(i), TXGBE_TXCFG_FLUSH);
336 /* Disable the receive unit by stopping each queue */
337 for (i = 0; i < hw->mac.max_rx_queues; i++) {
338 reg_val = rd32(hw, TXGBE_RXCFG(i));
339 reg_val &= ~TXGBE_RXCFG_ENA;
340 wr32(hw, TXGBE_RXCFG(i), reg_val);
343 /* flush all queues disables */
351 * txgbe_validate_mac_addr - Validate MAC address
352 * @mac_addr: pointer to MAC address.
354 * Tests a MAC address to ensure it is a valid Individual Address.
356 s32 txgbe_validate_mac_addr(u8 *mac_addr)
360 DEBUGFUNC("txgbe_validate_mac_addr");
362 /* Make sure it is not a multicast address */
363 if (TXGBE_IS_MULTICAST(mac_addr)) {
364 status = TXGBE_ERR_INVALID_MAC_ADDR;
365 /* Not a broadcast address */
366 } else if (TXGBE_IS_BROADCAST(mac_addr)) {
367 status = TXGBE_ERR_INVALID_MAC_ADDR;
368 /* Reject the zero address */
369 } else if (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 &&
370 mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0) {
371 status = TXGBE_ERR_INVALID_MAC_ADDR;
377 * txgbe_set_rar - Set Rx address register
378 * @hw: pointer to hardware structure
379 * @index: Receive address register to write
380 * @addr: Address to put into receive address register
381 * @vmdq: VMDq "set" or "pool" index
382 * @enable_addr: set flag that address is active
384 * Puts an ethernet address into a receive address register.
386 s32 txgbe_set_rar(struct txgbe_hw *hw, u32 index, u8 *addr, u32 vmdq,
389 u32 rar_low, rar_high;
390 u32 rar_entries = hw->mac.num_rar_entries;
392 DEBUGFUNC("txgbe_set_rar");
394 /* Make sure we are using a valid rar index range */
395 if (index >= rar_entries) {
396 DEBUGOUT("RAR index %d is out of range.\n", index);
397 return TXGBE_ERR_INVALID_ARGUMENT;
400 /* setup VMDq pool selection before this RAR gets enabled */
401 hw->mac.set_vmdq(hw, index, vmdq);
404 * HW expects these in little endian so we reverse the byte
405 * order from network order (big endian) to little endian
407 rar_low = TXGBE_ETHADDRL_AD0(addr[5]) |
408 TXGBE_ETHADDRL_AD1(addr[4]) |
409 TXGBE_ETHADDRL_AD2(addr[3]) |
410 TXGBE_ETHADDRL_AD3(addr[2]);
412 * Some parts put the VMDq setting in the extra RAH bits,
413 * so save everything except the lower 16 bits that hold part
414 * of the address and the address valid bit.
416 rar_high = rd32(hw, TXGBE_ETHADDRH);
417 rar_high &= ~TXGBE_ETHADDRH_AD_MASK;
418 rar_high |= (TXGBE_ETHADDRH_AD4(addr[1]) |
419 TXGBE_ETHADDRH_AD5(addr[0]));
421 rar_high &= ~TXGBE_ETHADDRH_VLD;
422 if (enable_addr != 0)
423 rar_high |= TXGBE_ETHADDRH_VLD;
425 wr32(hw, TXGBE_ETHADDRIDX, index);
426 wr32(hw, TXGBE_ETHADDRL, rar_low);
427 wr32(hw, TXGBE_ETHADDRH, rar_high);
433 * txgbe_clear_rar - Remove Rx address register
434 * @hw: pointer to hardware structure
435 * @index: Receive address register to write
437 * Clears an ethernet address from a receive address register.
439 s32 txgbe_clear_rar(struct txgbe_hw *hw, u32 index)
442 u32 rar_entries = hw->mac.num_rar_entries;
444 DEBUGFUNC("txgbe_clear_rar");
446 /* Make sure we are using a valid rar index range */
447 if (index >= rar_entries) {
448 DEBUGOUT("RAR index %d is out of range.\n", index);
449 return TXGBE_ERR_INVALID_ARGUMENT;
453 * Some parts put the VMDq setting in the extra RAH bits,
454 * so save everything except the lower 16 bits that hold part
455 * of the address and the address valid bit.
457 wr32(hw, TXGBE_ETHADDRIDX, index);
458 rar_high = rd32(hw, TXGBE_ETHADDRH);
459 rar_high &= ~(TXGBE_ETHADDRH_AD_MASK | TXGBE_ETHADDRH_VLD);
461 wr32(hw, TXGBE_ETHADDRL, 0);
462 wr32(hw, TXGBE_ETHADDRH, rar_high);
464 /* clear VMDq pool/queue selection for this RAR */
465 hw->mac.clear_vmdq(hw, index, BIT_MASK32);
471 * txgbe_init_rx_addrs - Initializes receive address filters.
472 * @hw: pointer to hardware structure
474 * Places the MAC address in receive address register 0 and clears the rest
475 * of the receive address registers. Clears the multicast table. Assumes
476 * the receiver is in reset when the routine is called.
478 s32 txgbe_init_rx_addrs(struct txgbe_hw *hw)
482 u32 rar_entries = hw->mac.num_rar_entries;
484 DEBUGFUNC("txgbe_init_rx_addrs");
487 * If the current mac address is valid, assume it is a software override
488 * to the permanent address.
489 * Otherwise, use the permanent address from the eeprom.
491 if (txgbe_validate_mac_addr(hw->mac.addr) ==
492 TXGBE_ERR_INVALID_MAC_ADDR) {
493 /* Get the MAC address from the RAR0 for later reference */
494 hw->mac.get_mac_addr(hw, hw->mac.addr);
496 DEBUGOUT(" Keeping Current RAR0 Addr =%.2X %.2X %.2X ",
497 hw->mac.addr[0], hw->mac.addr[1],
499 DEBUGOUT("%.2X %.2X %.2X\n", hw->mac.addr[3],
500 hw->mac.addr[4], hw->mac.addr[5]);
502 /* Setup the receive address. */
503 DEBUGOUT("Overriding MAC Address in RAR[0]\n");
504 DEBUGOUT(" New MAC Addr =%.2X %.2X %.2X ",
505 hw->mac.addr[0], hw->mac.addr[1],
507 DEBUGOUT("%.2X %.2X %.2X\n", hw->mac.addr[3],
508 hw->mac.addr[4], hw->mac.addr[5]);
510 hw->mac.set_rar(hw, 0, hw->mac.addr, 0, true);
513 /* clear VMDq pool/queue selection for RAR 0 */
514 hw->mac.clear_vmdq(hw, 0, BIT_MASK32);
516 hw->addr_ctrl.overflow_promisc = 0;
518 hw->addr_ctrl.rar_used_count = 1;
520 /* Zero out the other receive addresses. */
521 DEBUGOUT("Clearing RAR[1-%d]\n", rar_entries - 1);
522 for (i = 1; i < rar_entries; i++) {
523 wr32(hw, TXGBE_ETHADDRIDX, i);
524 wr32(hw, TXGBE_ETHADDRL, 0);
525 wr32(hw, TXGBE_ETHADDRH, 0);
529 hw->addr_ctrl.mta_in_use = 0;
530 psrctl = rd32(hw, TXGBE_PSRCTL);
531 psrctl &= ~(TXGBE_PSRCTL_ADHF12_MASK | TXGBE_PSRCTL_MCHFENA);
532 psrctl |= TXGBE_PSRCTL_ADHF12(hw->mac.mc_filter_type);
533 wr32(hw, TXGBE_PSRCTL, psrctl);
535 DEBUGOUT(" Clearing MTA\n");
536 for (i = 0; i < hw->mac.mcft_size; i++)
537 wr32(hw, TXGBE_MCADDRTBL(i), 0);
539 txgbe_init_uta_tables(hw);
545 * txgbe_mta_vector - Determines bit-vector in multicast table to set
546 * @hw: pointer to hardware structure
547 * @mc_addr: the multicast address
549 * Extracts the 12 bits, from a multicast address, to determine which
550 * bit-vector to set in the multicast table. The hardware uses 12 bits, from
551 * incoming rx multicast addresses, to determine the bit-vector to check in
552 * the MTA. Which of the 4 combination, of 12-bits, the hardware uses is set
553 * by the MO field of the PSRCTRL. The MO field is set during initialization
556 static s32 txgbe_mta_vector(struct txgbe_hw *hw, u8 *mc_addr)
560 DEBUGFUNC("txgbe_mta_vector");
562 switch (hw->mac.mc_filter_type) {
563 case 0: /* use bits [47:36] of the address */
564 vector = ((mc_addr[4] >> 4) | (((u16)mc_addr[5]) << 4));
566 case 1: /* use bits [46:35] of the address */
567 vector = ((mc_addr[4] >> 3) | (((u16)mc_addr[5]) << 5));
569 case 2: /* use bits [45:34] of the address */
570 vector = ((mc_addr[4] >> 2) | (((u16)mc_addr[5]) << 6));
572 case 3: /* use bits [43:32] of the address */
573 vector = ((mc_addr[4]) | (((u16)mc_addr[5]) << 8));
575 default: /* Invalid mc_filter_type */
576 DEBUGOUT("MC filter type param set incorrectly\n");
581 /* vector can only be 12-bits or boundary will be exceeded */
587 * txgbe_set_mta - Set bit-vector in multicast table
588 * @hw: pointer to hardware structure
589 * @mc_addr: Multicast address
591 * Sets the bit-vector in the multicast table.
593 void txgbe_set_mta(struct txgbe_hw *hw, u8 *mc_addr)
599 DEBUGFUNC("txgbe_set_mta");
601 hw->addr_ctrl.mta_in_use++;
603 vector = txgbe_mta_vector(hw, mc_addr);
604 DEBUGOUT(" bit-vector = 0x%03X\n", vector);
607 * The MTA is a register array of 128 32-bit registers. It is treated
608 * like an array of 4096 bits. We want to set bit
609 * BitArray[vector_value]. So we figure out what register the bit is
610 * in, read it, OR in the new bit, then write back the new value. The
611 * register is determined by the upper 7 bits of the vector value and
612 * the bit within that register are determined by the lower 5 bits of
615 vector_reg = (vector >> 5) & 0x7F;
616 vector_bit = vector & 0x1F;
617 hw->mac.mta_shadow[vector_reg] |= (1 << vector_bit);
621 * txgbe_update_mc_addr_list - Updates MAC list of multicast addresses
622 * @hw: pointer to hardware structure
623 * @mc_addr_list: the list of new multicast addresses
624 * @mc_addr_count: number of addresses
625 * @next: iterator function to walk the multicast address list
626 * @clear: flag, when set clears the table beforehand
628 * When the clear flag is set, the given list replaces any existing list.
629 * Hashes the given addresses into the multicast table.
631 s32 txgbe_update_mc_addr_list(struct txgbe_hw *hw, u8 *mc_addr_list,
632 u32 mc_addr_count, txgbe_mc_addr_itr next,
638 DEBUGFUNC("txgbe_update_mc_addr_list");
641 * Set the new number of MC addresses that we are being requested to
644 hw->addr_ctrl.num_mc_addrs = mc_addr_count;
645 hw->addr_ctrl.mta_in_use = 0;
647 /* Clear mta_shadow */
649 DEBUGOUT(" Clearing MTA\n");
650 memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow));
653 /* Update mta_shadow */
654 for (i = 0; i < mc_addr_count; i++) {
655 DEBUGOUT(" Adding the multicast addresses:\n");
656 txgbe_set_mta(hw, next(hw, &mc_addr_list, &vmdq));
660 for (i = 0; i < hw->mac.mcft_size; i++)
661 wr32a(hw, TXGBE_MCADDRTBL(0), i,
662 hw->mac.mta_shadow[i]);
664 if (hw->addr_ctrl.mta_in_use > 0) {
665 u32 psrctl = rd32(hw, TXGBE_PSRCTL);
666 psrctl &= ~(TXGBE_PSRCTL_ADHF12_MASK | TXGBE_PSRCTL_MCHFENA);
667 psrctl |= TXGBE_PSRCTL_MCHFENA |
668 TXGBE_PSRCTL_ADHF12(hw->mac.mc_filter_type);
669 wr32(hw, TXGBE_PSRCTL, psrctl);
672 DEBUGOUT("txgbe update mc addr list complete\n");
677 * txgbe_acquire_swfw_sync - Acquire SWFW semaphore
678 * @hw: pointer to hardware structure
679 * @mask: Mask to specify which semaphore to acquire
681 * Acquires the SWFW semaphore through the MNGSEM register for the specified
682 * function (CSR, PHY0, PHY1, EEPROM, Flash)
684 s32 txgbe_acquire_swfw_sync(struct txgbe_hw *hw, u32 mask)
687 u32 swmask = TXGBE_MNGSEM_SW(mask);
688 u32 fwmask = TXGBE_MNGSEM_FW(mask);
692 DEBUGFUNC("txgbe_acquire_swfw_sync");
694 for (i = 0; i < timeout; i++) {
696 * SW NVM semaphore bit is used for access to all
697 * SW_FW_SYNC bits (not just NVM)
699 if (txgbe_get_eeprom_semaphore(hw))
700 return TXGBE_ERR_SWFW_SYNC;
702 mngsem = rd32(hw, TXGBE_MNGSEM);
703 if (mngsem & (fwmask | swmask)) {
704 /* Resource is currently in use by FW or SW */
705 txgbe_release_eeprom_semaphore(hw);
709 wr32(hw, TXGBE_MNGSEM, mngsem);
710 txgbe_release_eeprom_semaphore(hw);
715 /* If time expired clear the bits holding the lock and retry */
716 if (mngsem & (fwmask | swmask))
717 txgbe_release_swfw_sync(hw, mngsem & (fwmask | swmask));
720 return TXGBE_ERR_SWFW_SYNC;
724 * txgbe_release_swfw_sync - Release SWFW semaphore
725 * @hw: pointer to hardware structure
726 * @mask: Mask to specify which semaphore to release
728 * Releases the SWFW semaphore through the MNGSEM register for the specified
729 * function (CSR, PHY0, PHY1, EEPROM, Flash)
731 void txgbe_release_swfw_sync(struct txgbe_hw *hw, u32 mask)
736 DEBUGFUNC("txgbe_release_swfw_sync");
738 txgbe_get_eeprom_semaphore(hw);
740 mngsem = rd32(hw, TXGBE_MNGSEM);
742 wr32(hw, TXGBE_MNGSEM, mngsem);
744 txgbe_release_eeprom_semaphore(hw);
748 * txgbe_disable_sec_rx_path - Stops the receive data path
749 * @hw: pointer to hardware structure
751 * Stops the receive data path and waits for the HW to internally empty
752 * the Rx security block
754 s32 txgbe_disable_sec_rx_path(struct txgbe_hw *hw)
756 #define TXGBE_MAX_SECRX_POLL 4000
761 DEBUGFUNC("txgbe_disable_sec_rx_path");
763 secrxreg = rd32(hw, TXGBE_SECRXCTL);
764 secrxreg |= TXGBE_SECRXCTL_XDSA;
765 wr32(hw, TXGBE_SECRXCTL, secrxreg);
766 for (i = 0; i < TXGBE_MAX_SECRX_POLL; i++) {
767 secrxreg = rd32(hw, TXGBE_SECRXSTAT);
768 if (!(secrxreg & TXGBE_SECRXSTAT_RDY))
769 /* Use interrupt-safe sleep just in case */
775 /* For informational purposes only */
776 if (i >= TXGBE_MAX_SECRX_POLL)
777 DEBUGOUT("Rx unit being enabled before security "
778 "path fully disabled. Continuing with init.\n");
784 * txgbe_enable_sec_rx_path - Enables the receive data path
785 * @hw: pointer to hardware structure
787 * Enables the receive data path.
789 s32 txgbe_enable_sec_rx_path(struct txgbe_hw *hw)
793 DEBUGFUNC("txgbe_enable_sec_rx_path");
795 secrxreg = rd32(hw, TXGBE_SECRXCTL);
796 secrxreg &= ~TXGBE_SECRXCTL_XDSA;
797 wr32(hw, TXGBE_SECRXCTL, secrxreg);
804 * txgbe_disable_sec_tx_path - Stops the transmit data path
805 * @hw: pointer to hardware structure
807 * Stops the transmit data path and waits for the HW to internally empty
808 * the Tx security block
810 int txgbe_disable_sec_tx_path(struct txgbe_hw *hw)
812 #define TXGBE_MAX_SECTX_POLL 40
817 sectxreg = rd32(hw, TXGBE_SECTXCTL);
818 sectxreg |= TXGBE_SECTXCTL_XDSA;
819 wr32(hw, TXGBE_SECTXCTL, sectxreg);
820 for (i = 0; i < TXGBE_MAX_SECTX_POLL; i++) {
821 sectxreg = rd32(hw, TXGBE_SECTXSTAT);
822 if (sectxreg & TXGBE_SECTXSTAT_RDY)
824 /* Use interrupt-safe sleep just in case */
828 /* For informational purposes only */
829 if (i >= TXGBE_MAX_SECTX_POLL)
830 PMD_DRV_LOG(DEBUG, "Tx unit being enabled before security "
831 "path fully disabled. Continuing with init.");
837 * txgbe_enable_sec_tx_path - Enables the transmit data path
838 * @hw: pointer to hardware structure
840 * Enables the transmit data path.
842 int txgbe_enable_sec_tx_path(struct txgbe_hw *hw)
846 sectxreg = rd32(hw, TXGBE_SECTXCTL);
847 sectxreg &= ~TXGBE_SECTXCTL_XDSA;
848 wr32(hw, TXGBE_SECTXCTL, sectxreg);
855 * txgbe_get_san_mac_addr_offset - Get SAN MAC address offset from the EEPROM
856 * @hw: pointer to hardware structure
857 * @san_mac_offset: SAN MAC address offset
859 * This function will read the EEPROM location for the SAN MAC address
860 * pointer, and returns the value at that location. This is used in both
861 * get and set mac_addr routines.
863 static s32 txgbe_get_san_mac_addr_offset(struct txgbe_hw *hw,
868 DEBUGFUNC("txgbe_get_san_mac_addr_offset");
871 * First read the EEPROM pointer to see if the MAC addresses are
874 err = hw->rom.readw_sw(hw, TXGBE_SAN_MAC_ADDR_PTR,
877 DEBUGOUT("eeprom at offset %d failed",
878 TXGBE_SAN_MAC_ADDR_PTR);
885 * txgbe_get_san_mac_addr - SAN MAC address retrieval from the EEPROM
886 * @hw: pointer to hardware structure
887 * @san_mac_addr: SAN MAC address
889 * Reads the SAN MAC address from the EEPROM, if it's available. This is
890 * per-port, so set_lan_id() must be called before reading the addresses.
891 * set_lan_id() is called by identify_sfp(), but this cannot be relied
892 * upon for non-SFP connections, so we must call it here.
894 s32 txgbe_get_san_mac_addr(struct txgbe_hw *hw, u8 *san_mac_addr)
896 u16 san_mac_data, san_mac_offset;
900 DEBUGFUNC("txgbe_get_san_mac_addr");
903 * First read the EEPROM pointer to see if the MAC addresses are
904 * available. If they're not, no point in calling set_lan_id() here.
906 err = txgbe_get_san_mac_addr_offset(hw, &san_mac_offset);
907 if (err || san_mac_offset == 0 || san_mac_offset == 0xFFFF)
908 goto san_mac_addr_out;
910 /* apply the port offset to the address offset */
911 (hw->bus.func) ? (san_mac_offset += TXGBE_SAN_MAC_ADDR_PORT1_OFFSET) :
912 (san_mac_offset += TXGBE_SAN_MAC_ADDR_PORT0_OFFSET);
913 for (i = 0; i < 3; i++) {
914 err = hw->rom.read16(hw, san_mac_offset,
917 DEBUGOUT("eeprom read at offset %d failed",
919 goto san_mac_addr_out;
921 san_mac_addr[i * 2] = (u8)(san_mac_data);
922 san_mac_addr[i * 2 + 1] = (u8)(san_mac_data >> 8);
929 * No addresses available in this EEPROM. It's not an
930 * error though, so just wipe the local address and return.
932 for (i = 0; i < 6; i++)
933 san_mac_addr[i] = 0xFF;
938 * txgbe_set_san_mac_addr - Write the SAN MAC address to the EEPROM
939 * @hw: pointer to hardware structure
940 * @san_mac_addr: SAN MAC address
942 * Write a SAN MAC address to the EEPROM.
944 s32 txgbe_set_san_mac_addr(struct txgbe_hw *hw, u8 *san_mac_addr)
947 u16 san_mac_data, san_mac_offset;
950 DEBUGFUNC("txgbe_set_san_mac_addr");
952 /* Look for SAN mac address pointer. If not defined, return */
953 err = txgbe_get_san_mac_addr_offset(hw, &san_mac_offset);
954 if (err || san_mac_offset == 0 || san_mac_offset == 0xFFFF)
955 return TXGBE_ERR_NO_SAN_ADDR_PTR;
957 /* Apply the port offset to the address offset */
958 (hw->bus.func) ? (san_mac_offset += TXGBE_SAN_MAC_ADDR_PORT1_OFFSET) :
959 (san_mac_offset += TXGBE_SAN_MAC_ADDR_PORT0_OFFSET);
961 for (i = 0; i < 3; i++) {
962 san_mac_data = (u16)((u16)(san_mac_addr[i * 2 + 1]) << 8);
963 san_mac_data |= (u16)(san_mac_addr[i * 2]);
964 hw->rom.write16(hw, san_mac_offset, san_mac_data);
972 * txgbe_clear_vmdq - Disassociate a VMDq pool index from a rx address
973 * @hw: pointer to hardware struct
974 * @rar: receive address register index to disassociate
975 * @vmdq: VMDq pool index to remove from the rar
977 s32 txgbe_clear_vmdq(struct txgbe_hw *hw, u32 rar, u32 vmdq)
979 u32 mpsar_lo, mpsar_hi;
980 u32 rar_entries = hw->mac.num_rar_entries;
982 DEBUGFUNC("txgbe_clear_vmdq");
984 /* Make sure we are using a valid rar index range */
985 if (rar >= rar_entries) {
986 DEBUGOUT("RAR index %d is out of range.\n", rar);
987 return TXGBE_ERR_INVALID_ARGUMENT;
990 wr32(hw, TXGBE_ETHADDRIDX, rar);
991 mpsar_lo = rd32(hw, TXGBE_ETHADDRASSL);
992 mpsar_hi = rd32(hw, TXGBE_ETHADDRASSH);
994 if (TXGBE_REMOVED(hw->hw_addr))
997 if (!mpsar_lo && !mpsar_hi)
1000 if (vmdq == BIT_MASK32) {
1002 wr32(hw, TXGBE_ETHADDRASSL, 0);
1006 wr32(hw, TXGBE_ETHADDRASSH, 0);
1009 } else if (vmdq < 32) {
1010 mpsar_lo &= ~(1 << vmdq);
1011 wr32(hw, TXGBE_ETHADDRASSL, mpsar_lo);
1013 mpsar_hi &= ~(1 << (vmdq - 32));
1014 wr32(hw, TXGBE_ETHADDRASSH, mpsar_hi);
1017 /* was that the last pool using this rar? */
1018 if (mpsar_lo == 0 && mpsar_hi == 0 &&
1019 rar != 0 && rar != hw->mac.san_mac_rar_index)
1020 hw->mac.clear_rar(hw, rar);
1026 * txgbe_set_vmdq - Associate a VMDq pool index with a rx address
1027 * @hw: pointer to hardware struct
1028 * @rar: receive address register index to associate with a VMDq index
1029 * @vmdq: VMDq pool index
1031 s32 txgbe_set_vmdq(struct txgbe_hw *hw, u32 rar, u32 vmdq)
1034 u32 rar_entries = hw->mac.num_rar_entries;
1036 DEBUGFUNC("txgbe_set_vmdq");
1038 /* Make sure we are using a valid rar index range */
1039 if (rar >= rar_entries) {
1040 DEBUGOUT("RAR index %d is out of range.\n", rar);
1041 return TXGBE_ERR_INVALID_ARGUMENT;
1044 wr32(hw, TXGBE_ETHADDRIDX, rar);
1046 mpsar = rd32(hw, TXGBE_ETHADDRASSL);
1048 wr32(hw, TXGBE_ETHADDRASSL, mpsar);
1050 mpsar = rd32(hw, TXGBE_ETHADDRASSH);
1051 mpsar |= 1 << (vmdq - 32);
1052 wr32(hw, TXGBE_ETHADDRASSH, mpsar);
1058 * txgbe_init_uta_tables - Initialize the Unicast Table Array
1059 * @hw: pointer to hardware structure
1061 s32 txgbe_init_uta_tables(struct txgbe_hw *hw)
1065 DEBUGFUNC("txgbe_init_uta_tables");
1066 DEBUGOUT(" Clearing UTA\n");
1068 for (i = 0; i < 128; i++)
1069 wr32(hw, TXGBE_UCADDRTBL(i), 0);
1075 * txgbe_find_vlvf_slot - find the vlanid or the first empty slot
1076 * @hw: pointer to hardware structure
1077 * @vlan: VLAN id to write to VLAN filter
1078 * @vlvf_bypass: true to find vlanid only, false returns first empty slot if
1082 * return the VLVF index where this VLAN id should be placed
1085 s32 txgbe_find_vlvf_slot(struct txgbe_hw *hw, u32 vlan, bool vlvf_bypass)
1087 s32 regindex, first_empty_slot;
1090 /* short cut the special case */
1094 /* if vlvf_bypass is set we don't want to use an empty slot, we
1095 * will simply bypass the VLVF if there are no entries present in the
1096 * VLVF that contain our VLAN
1098 first_empty_slot = vlvf_bypass ? TXGBE_ERR_NO_SPACE : 0;
1100 /* add VLAN enable bit for comparison */
1101 vlan |= TXGBE_PSRVLAN_EA;
1103 /* Search for the vlan id in the VLVF entries. Save off the first empty
1104 * slot found along the way.
1106 * pre-decrement loop covering (TXGBE_NUM_POOL - 1) .. 1
1108 for (regindex = TXGBE_NUM_POOL; --regindex;) {
1109 wr32(hw, TXGBE_PSRVLANIDX, regindex);
1110 bits = rd32(hw, TXGBE_PSRVLAN);
1113 if (!first_empty_slot && !bits)
1114 first_empty_slot = regindex;
1117 /* If we are here then we didn't find the VLAN. Return first empty
1118 * slot we found during our search, else error.
1120 if (!first_empty_slot)
1121 DEBUGOUT("No space in VLVF.\n");
1123 return first_empty_slot ? first_empty_slot : TXGBE_ERR_NO_SPACE;
1127 * txgbe_set_vfta - Set VLAN filter table
1128 * @hw: pointer to hardware structure
1129 * @vlan: VLAN id to write to VLAN filter
1130 * @vind: VMDq output index that maps queue to VLAN id in VLVFB
1131 * @vlan_on: boolean flag to turn on/off VLAN
1132 * @vlvf_bypass: boolean flag indicating updating default pool is okay
1134 * Turn on/off specified VLAN in the VLAN filter table.
1136 s32 txgbe_set_vfta(struct txgbe_hw *hw, u32 vlan, u32 vind,
1137 bool vlan_on, bool vlvf_bypass)
1139 u32 regidx, vfta_delta, vfta;
1142 DEBUGFUNC("txgbe_set_vfta");
1144 if (vlan > 4095 || vind > 63)
1145 return TXGBE_ERR_PARAM;
1148 * this is a 2 part operation - first the VFTA, then the
1149 * VLVF and VLVFB if VT Mode is set
1150 * We don't write the VFTA until we know the VLVF part succeeded.
1154 * The VFTA is a bitstring made up of 128 32-bit registers
1155 * that enable the particular VLAN id, much like the MTA:
1156 * bits[11-5]: which register
1157 * bits[4-0]: which bit in the register
1160 vfta_delta = 1 << (vlan % 32);
1161 vfta = rd32(hw, TXGBE_VLANTBL(regidx));
1164 * vfta_delta represents the difference between the current value
1165 * of vfta and the value we want in the register. Since the diff
1166 * is an XOR mask we can just update the vfta using an XOR
1168 vfta_delta &= vlan_on ? ~vfta : vfta;
1172 * Call txgbe_set_vlvf to set VLVFB and VLVF
1174 err = txgbe_set_vlvf(hw, vlan, vind, vlan_on, &vfta_delta,
1183 /* Update VFTA now that we are ready for traffic */
1185 wr32(hw, TXGBE_VLANTBL(regidx), vfta);
1191 * txgbe_set_vlvf - Set VLAN Pool Filter
1192 * @hw: pointer to hardware structure
1193 * @vlan: VLAN id to write to VLAN filter
1194 * @vind: VMDq output index that maps queue to VLAN id in PSRVLANPLM
1195 * @vlan_on: boolean flag to turn on/off VLAN in PSRVLAN
1196 * @vfta_delta: pointer to the difference between the current value
1197 * of PSRVLANPLM and the desired value
1198 * @vfta: the desired value of the VFTA
1199 * @vlvf_bypass: boolean flag indicating updating default pool is okay
1201 * Turn on/off specified bit in VLVF table.
1203 s32 txgbe_set_vlvf(struct txgbe_hw *hw, u32 vlan, u32 vind,
1204 bool vlan_on, u32 *vfta_delta, u32 vfta,
1211 DEBUGFUNC("txgbe_set_vlvf");
1213 if (vlan > 4095 || vind > 63)
1214 return TXGBE_ERR_PARAM;
1216 /* If VT Mode is set
1218 * make sure the vlan is in PSRVLAN
1219 * set the vind bit in the matching PSRVLANPLM
1221 * clear the pool bit and possibly the vind
1223 portctl = rd32(hw, TXGBE_PORTCTL);
1224 if (!(portctl & TXGBE_PORTCTL_NUMVT_MASK))
1227 vlvf_index = txgbe_find_vlvf_slot(hw, vlan, vlvf_bypass);
1231 wr32(hw, TXGBE_PSRVLANIDX, vlvf_index);
1232 bits = rd32(hw, TXGBE_PSRVLANPLM(vind / 32));
1234 /* set the pool bit */
1235 bits |= 1 << (vind % 32);
1239 /* clear the pool bit */
1240 bits ^= 1 << (vind % 32);
1243 !rd32(hw, TXGBE_PSRVLANPLM(vind / 32))) {
1244 /* Clear PSRVLANPLM first, then disable PSRVLAN. Otherwise
1245 * we run the risk of stray packets leaking into
1246 * the PF via the default pool
1249 wr32(hw, TXGBE_PSRVLANPLM(vlan / 32), vfta);
1251 /* disable VLVF and clear remaining bit from pool */
1252 wr32(hw, TXGBE_PSRVLAN, 0);
1253 wr32(hw, TXGBE_PSRVLANPLM(vind / 32), 0);
1258 /* If there are still bits set in the PSRVLANPLM registers
1259 * for the VLAN ID indicated we need to see if the
1260 * caller is requesting that we clear the PSRVLANPLM entry bit.
1261 * If the caller has requested that we clear the PSRVLANPLM
1262 * entry bit but there are still pools/VFs using this VLAN
1263 * ID entry then ignore the request. We're not worried
1264 * about the case where we're turning the PSRVLANPLM VLAN ID
1265 * entry bit on, only when requested to turn it off as
1266 * there may be multiple pools and/or VFs using the
1267 * VLAN ID entry. In that case we cannot clear the
1268 * PSRVLANPLM bit until all pools/VFs using that VLAN ID have also
1269 * been cleared. This will be indicated by "bits" being
1275 /* record pool change and enable VLAN ID if not already enabled */
1276 wr32(hw, TXGBE_PSRVLANPLM(vind / 32), bits);
1277 wr32(hw, TXGBE_PSRVLAN, TXGBE_PSRVLAN_EA | vlan);
1283 * txgbe_clear_vfta - Clear VLAN filter table
1284 * @hw: pointer to hardware structure
1286 * Clears the VLAN filer table, and the VMDq index associated with the filter
1288 s32 txgbe_clear_vfta(struct txgbe_hw *hw)
1292 DEBUGFUNC("txgbe_clear_vfta");
1294 for (offset = 0; offset < hw->mac.vft_size; offset++)
1295 wr32(hw, TXGBE_VLANTBL(offset), 0);
1297 for (offset = 0; offset < TXGBE_NUM_POOL; offset++) {
1298 wr32(hw, TXGBE_PSRVLANIDX, offset);
1299 wr32(hw, TXGBE_PSRVLAN, 0);
1300 wr32(hw, TXGBE_PSRVLANPLM(0), 0);
1301 wr32(hw, TXGBE_PSRVLANPLM(1), 0);
1308 * txgbe_need_crosstalk_fix - Determine if we need to do cross talk fix
1309 * @hw: pointer to hardware structure
1311 * Contains the logic to identify if we need to verify link for the
1314 static bool txgbe_need_crosstalk_fix(struct txgbe_hw *hw)
1316 /* Does FW say we need the fix */
1317 if (!hw->need_crosstalk_fix)
1320 /* Only consider SFP+ PHYs i.e. media type fiber */
1321 switch (hw->phy.media_type) {
1322 case txgbe_media_type_fiber:
1323 case txgbe_media_type_fiber_qsfp:
1333 * txgbe_check_mac_link - Determine link and speed status
1334 * @hw: pointer to hardware structure
1335 * @speed: pointer to link speed
1336 * @link_up: true when link is up
1337 * @link_up_wait_to_complete: bool used to wait for link up or not
1339 * Reads the links register to determine if link is up and the current speed
1341 s32 txgbe_check_mac_link(struct txgbe_hw *hw, u32 *speed,
1342 bool *link_up, bool link_up_wait_to_complete)
1344 u32 links_reg, links_orig;
1347 DEBUGFUNC("txgbe_check_mac_link");
1349 /* If Crosstalk fix enabled do the sanity check of making sure
1350 * the SFP+ cage is full.
1352 if (txgbe_need_crosstalk_fix(hw)) {
1355 switch (hw->mac.type) {
1356 case txgbe_mac_raptor:
1357 sfp_cage_full = !rd32m(hw, TXGBE_GPIODATA,
1361 /* sanity check - No SFP+ devices here */
1362 sfp_cage_full = false;
1366 if (!sfp_cage_full) {
1368 *speed = TXGBE_LINK_SPEED_UNKNOWN;
1373 /* clear the old state */
1374 links_orig = rd32(hw, TXGBE_PORTSTAT);
1376 links_reg = rd32(hw, TXGBE_PORTSTAT);
1378 if (links_orig != links_reg) {
1379 DEBUGOUT("LINKS changed from %08X to %08X\n",
1380 links_orig, links_reg);
1383 if (link_up_wait_to_complete) {
1384 for (i = 0; i < hw->mac.max_link_up_time; i++) {
1385 if (!(links_reg & TXGBE_PORTSTAT_UP)) {
1392 links_reg = rd32(hw, TXGBE_PORTSTAT);
1395 if (links_reg & TXGBE_PORTSTAT_UP)
1401 switch (links_reg & TXGBE_PORTSTAT_BW_MASK) {
1402 case TXGBE_PORTSTAT_BW_10G:
1403 *speed = TXGBE_LINK_SPEED_10GB_FULL;
1405 case TXGBE_PORTSTAT_BW_1G:
1406 *speed = TXGBE_LINK_SPEED_1GB_FULL;
1408 case TXGBE_PORTSTAT_BW_100M:
1409 *speed = TXGBE_LINK_SPEED_100M_FULL;
1412 *speed = TXGBE_LINK_SPEED_UNKNOWN;
1419 * txgbe_get_wwn_prefix - Get alternative WWNN/WWPN prefix from
1421 * @hw: pointer to hardware structure
1422 * @wwnn_prefix: the alternative WWNN prefix
1423 * @wwpn_prefix: the alternative WWPN prefix
1425 * This function will read the EEPROM from the alternative SAN MAC address
1426 * block to check the support for the alternative WWNN/WWPN prefix support.
1428 s32 txgbe_get_wwn_prefix(struct txgbe_hw *hw, u16 *wwnn_prefix,
1432 u16 alt_san_mac_blk_offset;
1434 DEBUGFUNC("txgbe_get_wwn_prefix");
1436 /* clear output first */
1437 *wwnn_prefix = 0xFFFF;
1438 *wwpn_prefix = 0xFFFF;
1440 /* check if alternative SAN MAC is supported */
1441 offset = TXGBE_ALT_SAN_MAC_ADDR_BLK_PTR;
1442 if (hw->rom.readw_sw(hw, offset, &alt_san_mac_blk_offset))
1443 goto wwn_prefix_err;
1445 if (alt_san_mac_blk_offset == 0 || alt_san_mac_blk_offset == 0xFFFF)
1446 goto wwn_prefix_out;
1448 /* check capability in alternative san mac address block */
1449 offset = alt_san_mac_blk_offset + TXGBE_ALT_SAN_MAC_ADDR_CAPS_OFFSET;
1450 if (hw->rom.read16(hw, offset, &caps))
1451 goto wwn_prefix_err;
1452 if (!(caps & TXGBE_ALT_SAN_MAC_ADDR_CAPS_ALTWWN))
1453 goto wwn_prefix_out;
1455 /* get the corresponding prefix for WWNN/WWPN */
1456 offset = alt_san_mac_blk_offset + TXGBE_ALT_SAN_MAC_ADDR_WWNN_OFFSET;
1457 if (hw->rom.read16(hw, offset, wwnn_prefix))
1458 DEBUGOUT("eeprom read at offset %d failed", offset);
1460 offset = alt_san_mac_blk_offset + TXGBE_ALT_SAN_MAC_ADDR_WWPN_OFFSET;
1461 if (hw->rom.read16(hw, offset, wwpn_prefix))
1462 goto wwn_prefix_err;
1468 DEBUGOUT("eeprom read at offset %d failed", offset);
1473 * txgbe_set_mac_anti_spoofing - Enable/Disable MAC anti-spoofing
1474 * @hw: pointer to hardware structure
1475 * @enable: enable or disable switch for MAC anti-spoofing
1476 * @vf: Virtual Function pool - VF Pool to set for MAC anti-spoofing
1479 void txgbe_set_mac_anti_spoofing(struct txgbe_hw *hw, bool enable, int vf)
1481 int vf_target_reg = vf >> 3;
1482 int vf_target_shift = vf % 8;
1485 pfvfspoof = rd32(hw, TXGBE_POOLTXASMAC(vf_target_reg));
1487 pfvfspoof |= (1 << vf_target_shift);
1489 pfvfspoof &= ~(1 << vf_target_shift);
1490 wr32(hw, TXGBE_POOLTXASMAC(vf_target_reg), pfvfspoof);
1494 * txgbe_set_ethertype_anti_spoofing - Configure Ethertype anti-spoofing
1495 * @hw: pointer to hardware structure
1496 * @enable: enable or disable switch for Ethertype anti-spoofing
1497 * @vf: Virtual Function pool - VF Pool to set for Ethertype anti-spoofing
1500 void txgbe_set_ethertype_anti_spoofing(struct txgbe_hw *hw,
1501 bool enable, int vf)
1503 int vf_target_reg = vf >> 3;
1504 int vf_target_shift = vf % 8;
1507 pfvfspoof = rd32(hw, TXGBE_POOLTXASET(vf_target_reg));
1509 pfvfspoof |= (1 << vf_target_shift);
1511 pfvfspoof &= ~(1 << vf_target_shift);
1512 wr32(hw, TXGBE_POOLTXASET(vf_target_reg), pfvfspoof);
1516 * txgbe_get_device_caps - Get additional device capabilities
1517 * @hw: pointer to hardware structure
1518 * @device_caps: the EEPROM word with the extra device capabilities
1520 * This function will read the EEPROM location for the device capabilities,
1521 * and return the word through device_caps.
1523 s32 txgbe_get_device_caps(struct txgbe_hw *hw, u16 *device_caps)
1525 DEBUGFUNC("txgbe_get_device_caps");
1527 hw->rom.readw_sw(hw, TXGBE_DEVICE_CAPS, device_caps);
1533 * txgbe_set_pba - Initialize Rx packet buffer
1534 * @hw: pointer to hardware structure
1535 * @num_pb: number of packet buffers to allocate
1536 * @headroom: reserve n KB of headroom
1537 * @strategy: packet buffer allocation strategy
1539 void txgbe_set_pba(struct txgbe_hw *hw, int num_pb, u32 headroom,
1542 u32 pbsize = hw->mac.rx_pb_size;
1544 u32 rxpktsize, txpktsize, txpbthresh;
1546 UNREFERENCED_PARAMETER(hw);
1548 /* Reserve headroom */
1554 /* Divide remaining packet buffer space amongst the number of packet
1555 * buffers requested using supplied strategy.
1558 case PBA_STRATEGY_WEIGHTED:
1559 /* txgbe_dcb_pba_80_48 strategy weight first half of packet
1560 * buffer with 5/8 of the packet buffer space.
1562 rxpktsize = (pbsize * 5) / (num_pb * 4);
1563 pbsize -= rxpktsize * (num_pb / 2);
1565 for (; i < (num_pb / 2); i++)
1566 wr32(hw, TXGBE_PBRXSIZE(i), rxpktsize);
1567 /* fall through - configure remaining packet buffers */
1568 case PBA_STRATEGY_EQUAL:
1569 rxpktsize = (pbsize / (num_pb - i));
1571 for (; i < num_pb; i++)
1572 wr32(hw, TXGBE_PBRXSIZE(i), rxpktsize);
1578 /* Only support an equally distributed Tx packet buffer strategy. */
1579 txpktsize = TXGBE_PBTXSIZE_MAX / num_pb;
1580 txpbthresh = (txpktsize / 1024) - TXGBE_TXPKT_SIZE_MAX;
1581 for (i = 0; i < num_pb; i++) {
1582 wr32(hw, TXGBE_PBTXSIZE(i), txpktsize);
1583 wr32(hw, TXGBE_PBTXDMATH(i), txpbthresh);
1586 /* Clear unused TCs, if any, to zero buffer size*/
1587 for (; i < TXGBE_MAX_UP; i++) {
1588 wr32(hw, TXGBE_PBRXSIZE(i), 0);
1589 wr32(hw, TXGBE_PBTXSIZE(i), 0);
1590 wr32(hw, TXGBE_PBTXDMATH(i), 0);
1595 * txgbe_clear_tx_pending - Clear pending TX work from the PCIe fifo
1596 * @hw: pointer to the hardware structure
1598 * The MACs can experience issues if TX work is still pending
1599 * when a reset occurs. This function prevents this by flushing the PCIe
1600 * buffers on the system.
1602 void txgbe_clear_tx_pending(struct txgbe_hw *hw)
1604 u32 hlreg0, i, poll;
1607 * If double reset is not requested then all transactions should
1608 * already be clear and as such there is no work to do
1610 if (!(hw->mac.flags & TXGBE_FLAGS_DOUBLE_RESET_REQUIRED))
1613 hlreg0 = rd32(hw, TXGBE_PSRCTL);
1614 wr32(hw, TXGBE_PSRCTL, hlreg0 | TXGBE_PSRCTL_LBENA);
1616 /* Wait for a last completion before clearing buffers */
1621 * Before proceeding, make sure that the PCIe block does not have
1622 * transactions pending.
1624 poll = (800 * 11) / 10;
1625 for (i = 0; i < poll; i++)
1628 /* Flush all writes and allow 20usec for all transactions to clear */
1632 /* restore previous register values */
1633 wr32(hw, TXGBE_PSRCTL, hlreg0);
1637 * txgbe_get_thermal_sensor_data - Gathers thermal sensor data
1638 * @hw: pointer to hardware structure
1640 * Returns the thermal sensor data structure
1642 s32 txgbe_get_thermal_sensor_data(struct txgbe_hw *hw)
1644 struct txgbe_thermal_sensor_data *data = &hw->mac.thermal_sensor_data;
1648 DEBUGFUNC("txgbe_get_thermal_sensor_data");
1650 /* Only support thermal sensors attached to physical port 0 */
1651 if (hw->bus.lan_id != 0)
1652 return TXGBE_NOT_IMPLEMENTED;
1654 ts_stat = rd32(hw, TXGBE_TSSTAT);
1655 tsv = (s64)TXGBE_TSSTAT_DATA(ts_stat);
1656 tsv = tsv > 1200 ? tsv : 1200;
1657 tsv = -(48380 << 8) / 1000
1658 + tsv * (31020 << 8) / 100000
1659 - tsv * tsv * (18201 << 8) / 100000000
1660 + tsv * tsv * tsv * (81542 << 8) / 1000000000000
1661 - tsv * tsv * tsv * tsv * (16743 << 8) / 1000000000000000;
1664 data->sensor[0].temp = (s16)tsv;
1670 * txgbe_init_thermal_sensor_thresh - Inits thermal sensor thresholds
1671 * @hw: pointer to hardware structure
1673 * Inits the thermal sensor thresholds according to the NVM map
1674 * and save off the threshold and location values into mac.thermal_sensor_data
1676 s32 txgbe_init_thermal_sensor_thresh(struct txgbe_hw *hw)
1678 struct txgbe_thermal_sensor_data *data = &hw->mac.thermal_sensor_data;
1680 DEBUGFUNC("txgbe_init_thermal_sensor_thresh");
1682 memset(data, 0, sizeof(struct txgbe_thermal_sensor_data));
1684 if (hw->bus.lan_id != 0)
1685 return TXGBE_NOT_IMPLEMENTED;
1687 wr32(hw, TXGBE_TSCTRL, TXGBE_TSCTRL_EVALMD);
1688 wr32(hw, TXGBE_TSINTR,
1689 TXGBE_TSINTR_AEN | TXGBE_TSINTR_DEN);
1690 wr32(hw, TXGBE_TSEN, TXGBE_TSEN_ENA);
1693 data->sensor[0].alarm_thresh = 100;
1694 wr32(hw, TXGBE_TSATHRE, 677);
1695 data->sensor[0].dalarm_thresh = 90;
1696 wr32(hw, TXGBE_TSDTHRE, 614);
1701 void txgbe_disable_rx(struct txgbe_hw *hw)
1705 pfdtxgswc = rd32(hw, TXGBE_PSRCTL);
1706 if (pfdtxgswc & TXGBE_PSRCTL_LBENA) {
1707 pfdtxgswc &= ~TXGBE_PSRCTL_LBENA;
1708 wr32(hw, TXGBE_PSRCTL, pfdtxgswc);
1709 hw->mac.set_lben = true;
1711 hw->mac.set_lben = false;
1714 wr32m(hw, TXGBE_PBRXCTL, TXGBE_PBRXCTL_ENA, 0);
1715 wr32m(hw, TXGBE_MACRXCFG, TXGBE_MACRXCFG_ENA, 0);
1718 void txgbe_enable_rx(struct txgbe_hw *hw)
1722 wr32m(hw, TXGBE_MACRXCFG, TXGBE_MACRXCFG_ENA, TXGBE_MACRXCFG_ENA);
1723 wr32m(hw, TXGBE_PBRXCTL, TXGBE_PBRXCTL_ENA, TXGBE_PBRXCTL_ENA);
1725 if (hw->mac.set_lben) {
1726 pfdtxgswc = rd32(hw, TXGBE_PSRCTL);
1727 pfdtxgswc |= TXGBE_PSRCTL_LBENA;
1728 wr32(hw, TXGBE_PSRCTL, pfdtxgswc);
1729 hw->mac.set_lben = false;
1734 * txgbe_setup_mac_link_multispeed_fiber - Set MAC link speed
1735 * @hw: pointer to hardware structure
1736 * @speed: new link speed
1737 * @autoneg_wait_to_complete: true when waiting for completion is needed
1739 * Set the link speed in the MAC and/or PHY register and restarts link.
1741 s32 txgbe_setup_mac_link_multispeed_fiber(struct txgbe_hw *hw,
1743 bool autoneg_wait_to_complete)
1745 u32 link_speed = TXGBE_LINK_SPEED_UNKNOWN;
1746 u32 highest_link_speed = TXGBE_LINK_SPEED_UNKNOWN;
1750 bool autoneg, link_up = false;
1752 DEBUGFUNC("txgbe_setup_mac_link_multispeed_fiber");
1754 /* Mask off requested but non-supported speeds */
1755 status = hw->mac.get_link_capabilities(hw, &link_speed, &autoneg);
1759 speed &= link_speed;
1761 /* Try each speed one by one, highest priority first. We do this in
1762 * software because 10Gb fiber doesn't support speed autonegotiation.
1764 if (speed & TXGBE_LINK_SPEED_10GB_FULL) {
1766 highest_link_speed = TXGBE_LINK_SPEED_10GB_FULL;
1768 /* Set the module link speed */
1769 switch (hw->phy.media_type) {
1770 case txgbe_media_type_fiber:
1771 hw->mac.set_rate_select_speed(hw,
1772 TXGBE_LINK_SPEED_10GB_FULL);
1774 case txgbe_media_type_fiber_qsfp:
1775 /* QSFP module automatically detects MAC link speed */
1778 DEBUGOUT("Unexpected media type.\n");
1782 /* Allow module to change analog characteristics (1G->10G) */
1785 status = hw->mac.setup_mac_link(hw,
1786 TXGBE_LINK_SPEED_10GB_FULL,
1787 autoneg_wait_to_complete);
1791 /* Flap the Tx laser if it has not already been done */
1792 hw->mac.flap_tx_laser(hw);
1794 /* Wait for the controller to acquire link. Per IEEE 802.3ap,
1795 * Section 73.10.2, we may have to wait up to 500ms if KR is
1796 * attempted. uses the same timing for 10g SFI.
1798 for (i = 0; i < 5; i++) {
1799 /* Wait for the link partner to also set speed */
1802 /* If we have link, just jump out */
1803 status = hw->mac.check_link(hw, &link_speed,
1813 if (speed & TXGBE_LINK_SPEED_1GB_FULL) {
1815 if (highest_link_speed == TXGBE_LINK_SPEED_UNKNOWN)
1816 highest_link_speed = TXGBE_LINK_SPEED_1GB_FULL;
1818 /* Set the module link speed */
1819 switch (hw->phy.media_type) {
1820 case txgbe_media_type_fiber:
1821 hw->mac.set_rate_select_speed(hw,
1822 TXGBE_LINK_SPEED_1GB_FULL);
1824 case txgbe_media_type_fiber_qsfp:
1825 /* QSFP module automatically detects link speed */
1828 DEBUGOUT("Unexpected media type.\n");
1832 /* Allow module to change analog characteristics (10G->1G) */
1835 status = hw->mac.setup_mac_link(hw,
1836 TXGBE_LINK_SPEED_1GB_FULL,
1837 autoneg_wait_to_complete);
1841 /* Flap the Tx laser if it has not already been done */
1842 hw->mac.flap_tx_laser(hw);
1844 /* Wait for the link partner to also set speed */
1847 /* If we have link, just jump out */
1848 status = hw->mac.check_link(hw, &link_speed, &link_up, false);
1856 /* We didn't get link. Configure back to the highest speed we tried,
1857 * (if there was more than one). We call ourselves back with just the
1858 * single highest speed that the user requested.
1861 status = txgbe_setup_mac_link_multispeed_fiber(hw,
1863 autoneg_wait_to_complete);
1866 /* Set autoneg_advertised value based on input link speed */
1867 hw->phy.autoneg_advertised = 0;
1869 if (speed & TXGBE_LINK_SPEED_10GB_FULL)
1870 hw->phy.autoneg_advertised |= TXGBE_LINK_SPEED_10GB_FULL;
1872 if (speed & TXGBE_LINK_SPEED_1GB_FULL)
1873 hw->phy.autoneg_advertised |= TXGBE_LINK_SPEED_1GB_FULL;
1879 * txgbe_init_shared_code - Initialize the shared code
1880 * @hw: pointer to hardware structure
1882 * This will assign function pointers and assign the MAC type and PHY code.
1883 * Does not touch the hardware. This function must be called prior to any
1884 * other function in the shared code. The txgbe_hw structure should be
1885 * memset to 0 prior to calling this function. The following fields in
1886 * hw structure should be filled in prior to calling this function:
1887 * hw_addr, back, device_id, vendor_id, subsystem_device_id,
1888 * subsystem_vendor_id, and revision_id
1890 s32 txgbe_init_shared_code(struct txgbe_hw *hw)
1894 DEBUGFUNC("txgbe_init_shared_code");
1899 txgbe_set_mac_type(hw);
1901 txgbe_init_ops_dummy(hw);
1902 switch (hw->mac.type) {
1903 case txgbe_mac_raptor:
1904 status = txgbe_init_ops_pf(hw);
1907 status = TXGBE_ERR_DEVICE_NOT_SUPPORTED;
1910 hw->mac.max_link_up_time = TXGBE_LINK_UP_TIME;
1912 hw->bus.set_lan_id(hw);
1918 * txgbe_set_mac_type - Sets MAC type
1919 * @hw: pointer to the HW structure
1921 * This function sets the mac type of the adapter based on the
1922 * vendor ID and device ID stored in the hw structure.
1924 s32 txgbe_set_mac_type(struct txgbe_hw *hw)
1928 DEBUGFUNC("txgbe_set_mac_type");
1930 if (hw->vendor_id != PCI_VENDOR_ID_WANGXUN) {
1931 DEBUGOUT("Unsupported vendor id: %x", hw->vendor_id);
1932 return TXGBE_ERR_DEVICE_NOT_SUPPORTED;
1935 switch (hw->device_id) {
1936 case TXGBE_DEV_ID_RAPTOR_KR_KX_KX4:
1937 hw->phy.media_type = txgbe_media_type_backplane;
1938 hw->mac.type = txgbe_mac_raptor;
1940 case TXGBE_DEV_ID_RAPTOR_XAUI:
1941 case TXGBE_DEV_ID_RAPTOR_SGMII:
1942 hw->phy.media_type = txgbe_media_type_copper;
1943 hw->mac.type = txgbe_mac_raptor;
1945 case TXGBE_DEV_ID_RAPTOR_SFP:
1946 case TXGBE_DEV_ID_WX1820_SFP:
1947 hw->phy.media_type = txgbe_media_type_fiber;
1948 hw->mac.type = txgbe_mac_raptor;
1950 case TXGBE_DEV_ID_RAPTOR_QSFP:
1951 hw->phy.media_type = txgbe_media_type_fiber_qsfp;
1952 hw->mac.type = txgbe_mac_raptor;
1954 case TXGBE_DEV_ID_RAPTOR_VF:
1955 case TXGBE_DEV_ID_RAPTOR_VF_HV:
1956 hw->phy.media_type = txgbe_media_type_virtual;
1957 hw->mac.type = txgbe_mac_raptor_vf;
1960 err = TXGBE_ERR_DEVICE_NOT_SUPPORTED;
1961 DEBUGOUT("Unsupported device id: %x", hw->device_id);
1965 DEBUGOUT("found mac: %d media: %d, returns: %d\n",
1966 hw->mac.type, hw->phy.media_type, err);
1970 void txgbe_init_mac_link_ops(struct txgbe_hw *hw)
1972 struct txgbe_mac_info *mac = &hw->mac;
1974 DEBUGFUNC("txgbe_init_mac_link_ops");
1977 * enable the laser control functions for SFP+ fiber
1978 * and MNG not enabled
1980 if (hw->phy.media_type == txgbe_media_type_fiber &&
1981 !txgbe_mng_enabled(hw)) {
1982 mac->disable_tx_laser =
1983 txgbe_disable_tx_laser_multispeed_fiber;
1984 mac->enable_tx_laser =
1985 txgbe_enable_tx_laser_multispeed_fiber;
1986 mac->flap_tx_laser =
1987 txgbe_flap_tx_laser_multispeed_fiber;
1990 if ((hw->phy.media_type == txgbe_media_type_fiber ||
1991 hw->phy.media_type == txgbe_media_type_fiber_qsfp) &&
1992 hw->phy.multispeed_fiber) {
1993 /* Set up dual speed SFP+ support */
1994 mac->setup_link = txgbe_setup_mac_link_multispeed_fiber;
1995 mac->setup_mac_link = txgbe_setup_mac_link;
1996 mac->set_rate_select_speed = txgbe_set_hard_rate_select_speed;
1997 } else if ((hw->phy.media_type == txgbe_media_type_backplane) &&
1998 (hw->phy.smart_speed == txgbe_smart_speed_auto ||
1999 hw->phy.smart_speed == txgbe_smart_speed_on) &&
2000 !txgbe_verify_lesm_fw_enabled_raptor(hw)) {
2001 mac->setup_link = txgbe_setup_mac_link_smartspeed;
2003 mac->setup_link = txgbe_setup_mac_link;
2008 * txgbe_init_phy_raptor - PHY/SFP specific init
2009 * @hw: pointer to hardware structure
2011 * Initialize any function pointers that were not able to be
2012 * set during init_shared_code because the PHY/SFP type was
2013 * not known. Perform the SFP init if necessary.
2016 s32 txgbe_init_phy_raptor(struct txgbe_hw *hw)
2018 struct txgbe_mac_info *mac = &hw->mac;
2019 struct txgbe_phy_info *phy = &hw->phy;
2022 DEBUGFUNC("txgbe_init_phy_raptor");
2024 if (hw->device_id == TXGBE_DEV_ID_RAPTOR_QSFP) {
2025 /* Store flag indicating I2C bus access control unit. */
2026 hw->phy.qsfp_shared_i2c_bus = TRUE;
2028 /* Initialize access to QSFP+ I2C bus */
2032 /* Identify the PHY or SFP module */
2033 err = phy->identify(hw);
2034 if (err == TXGBE_ERR_SFP_NOT_SUPPORTED)
2035 goto init_phy_ops_out;
2037 /* Setup function pointers based on detected SFP module and speeds */
2038 txgbe_init_mac_link_ops(hw);
2040 /* If copper media, overwrite with copper function pointers */
2041 if (phy->media_type == txgbe_media_type_copper) {
2042 mac->setup_link = txgbe_setup_copper_link_raptor;
2043 mac->get_link_capabilities =
2044 txgbe_get_copper_link_capabilities;
2047 /* Set necessary function pointers based on PHY type */
2048 switch (hw->phy.type) {
2050 phy->setup_link = txgbe_setup_phy_link_tnx;
2051 phy->check_link = txgbe_check_phy_link_tnx;
2061 s32 txgbe_setup_sfp_modules(struct txgbe_hw *hw)
2065 DEBUGFUNC("txgbe_setup_sfp_modules");
2067 if (hw->phy.sfp_type == txgbe_sfp_type_unknown)
2070 txgbe_init_mac_link_ops(hw);
2072 /* PHY config will finish before releasing the semaphore */
2073 err = hw->mac.acquire_swfw_sync(hw, TXGBE_MNGSEM_SWPHY);
2075 return TXGBE_ERR_SWFW_SYNC;
2077 /* Release the semaphore */
2078 hw->mac.release_swfw_sync(hw, TXGBE_MNGSEM_SWPHY);
2080 /* Delay obtaining semaphore again to allow FW access
2081 * prot_autoc_write uses the semaphore too.
2083 msec_delay(hw->rom.semaphore_delay);
2086 DEBUGOUT("sfp module setup not complete\n");
2087 return TXGBE_ERR_SFP_SETUP_NOT_COMPLETE;
2094 * txgbe_init_ops_pf - Inits func ptrs and MAC type
2095 * @hw: pointer to hardware structure
2097 * Initialize the function pointers and assign the MAC type.
2098 * Does not touch the hardware.
2100 s32 txgbe_init_ops_pf(struct txgbe_hw *hw)
2102 struct txgbe_bus_info *bus = &hw->bus;
2103 struct txgbe_mac_info *mac = &hw->mac;
2104 struct txgbe_phy_info *phy = &hw->phy;
2105 struct txgbe_rom_info *rom = &hw->rom;
2106 struct txgbe_mbx_info *mbx = &hw->mbx;
2108 DEBUGFUNC("txgbe_init_ops_pf");
2111 bus->set_lan_id = txgbe_set_lan_id_multi_port;
2114 phy->get_media_type = txgbe_get_media_type_raptor;
2115 phy->identify = txgbe_identify_phy;
2116 phy->init = txgbe_init_phy_raptor;
2117 phy->read_reg = txgbe_read_phy_reg;
2118 phy->write_reg = txgbe_write_phy_reg;
2119 phy->read_reg_mdi = txgbe_read_phy_reg_mdi;
2120 phy->write_reg_mdi = txgbe_write_phy_reg_mdi;
2121 phy->setup_link = txgbe_setup_phy_link;
2122 phy->setup_link_speed = txgbe_setup_phy_link_speed;
2123 phy->read_i2c_byte = txgbe_read_i2c_byte;
2124 phy->write_i2c_byte = txgbe_write_i2c_byte;
2125 phy->read_i2c_eeprom = txgbe_read_i2c_eeprom;
2126 phy->write_i2c_eeprom = txgbe_write_i2c_eeprom;
2127 phy->reset = txgbe_reset_phy;
2130 mac->init_hw = txgbe_init_hw;
2131 mac->start_hw = txgbe_start_hw_raptor;
2132 mac->clear_hw_cntrs = txgbe_clear_hw_cntrs;
2133 mac->enable_rx_dma = txgbe_enable_rx_dma_raptor;
2134 mac->get_mac_addr = txgbe_get_mac_addr;
2135 mac->stop_hw = txgbe_stop_hw;
2136 mac->acquire_swfw_sync = txgbe_acquire_swfw_sync;
2137 mac->release_swfw_sync = txgbe_release_swfw_sync;
2138 mac->reset_hw = txgbe_reset_hw;
2140 mac->disable_sec_rx_path = txgbe_disable_sec_rx_path;
2141 mac->enable_sec_rx_path = txgbe_enable_sec_rx_path;
2142 mac->disable_sec_tx_path = txgbe_disable_sec_tx_path;
2143 mac->enable_sec_tx_path = txgbe_enable_sec_tx_path;
2144 mac->get_san_mac_addr = txgbe_get_san_mac_addr;
2145 mac->set_san_mac_addr = txgbe_set_san_mac_addr;
2146 mac->get_device_caps = txgbe_get_device_caps;
2147 mac->get_wwn_prefix = txgbe_get_wwn_prefix;
2148 mac->autoc_read = txgbe_autoc_read;
2149 mac->autoc_write = txgbe_autoc_write;
2151 /* RAR, Multicast, VLAN */
2152 mac->set_rar = txgbe_set_rar;
2153 mac->clear_rar = txgbe_clear_rar;
2154 mac->init_rx_addrs = txgbe_init_rx_addrs;
2155 mac->enable_rx = txgbe_enable_rx;
2156 mac->disable_rx = txgbe_disable_rx;
2157 mac->set_vmdq = txgbe_set_vmdq;
2158 mac->clear_vmdq = txgbe_clear_vmdq;
2159 mac->set_vfta = txgbe_set_vfta;
2160 mac->set_vlvf = txgbe_set_vlvf;
2161 mac->clear_vfta = txgbe_clear_vfta;
2162 mac->init_uta_tables = txgbe_init_uta_tables;
2163 mac->setup_sfp = txgbe_setup_sfp_modules;
2164 mac->set_mac_anti_spoofing = txgbe_set_mac_anti_spoofing;
2165 mac->set_ethertype_anti_spoofing = txgbe_set_ethertype_anti_spoofing;
2168 mac->get_link_capabilities = txgbe_get_link_capabilities_raptor;
2169 mac->check_link = txgbe_check_mac_link;
2170 mac->setup_pba = txgbe_set_pba;
2172 /* Manageability interface */
2173 mac->set_fw_drv_ver = txgbe_hic_set_drv_ver;
2174 mac->get_thermal_sensor_data = txgbe_get_thermal_sensor_data;
2175 mac->init_thermal_sensor_thresh = txgbe_init_thermal_sensor_thresh;
2177 mbx->init_params = txgbe_init_mbx_params_pf;
2178 mbx->read = txgbe_read_mbx_pf;
2179 mbx->write = txgbe_write_mbx_pf;
2180 mbx->check_for_msg = txgbe_check_for_msg_pf;
2181 mbx->check_for_ack = txgbe_check_for_ack_pf;
2182 mbx->check_for_rst = txgbe_check_for_rst_pf;
2185 rom->init_params = txgbe_init_eeprom_params;
2186 rom->read16 = txgbe_ee_read16;
2187 rom->readw_buffer = txgbe_ee_readw_buffer;
2188 rom->readw_sw = txgbe_ee_readw_sw;
2189 rom->read32 = txgbe_ee_read32;
2190 rom->write16 = txgbe_ee_write16;
2191 rom->writew_buffer = txgbe_ee_writew_buffer;
2192 rom->writew_sw = txgbe_ee_writew_sw;
2193 rom->write32 = txgbe_ee_write32;
2194 rom->validate_checksum = txgbe_validate_eeprom_checksum;
2195 rom->update_checksum = txgbe_update_eeprom_checksum;
2196 rom->calc_checksum = txgbe_calc_eeprom_checksum;
2198 mac->mcft_size = TXGBE_RAPTOR_MC_TBL_SIZE;
2199 mac->vft_size = TXGBE_RAPTOR_VFT_TBL_SIZE;
2200 mac->num_rar_entries = TXGBE_RAPTOR_RAR_ENTRIES;
2201 mac->rx_pb_size = TXGBE_RAPTOR_RX_PB_SIZE;
2202 mac->max_rx_queues = TXGBE_RAPTOR_MAX_RX_QUEUES;
2203 mac->max_tx_queues = TXGBE_RAPTOR_MAX_TX_QUEUES;
2209 * txgbe_get_link_capabilities_raptor - Determines link capabilities
2210 * @hw: pointer to hardware structure
2211 * @speed: pointer to link speed
2212 * @autoneg: true when autoneg or autotry is enabled
2214 * Determines the link capabilities by reading the AUTOC register.
2216 s32 txgbe_get_link_capabilities_raptor(struct txgbe_hw *hw,
2223 DEBUGFUNC("txgbe_get_link_capabilities_raptor");
2225 /* Check if 1G SFP module. */
2226 if (hw->phy.sfp_type == txgbe_sfp_type_1g_cu_core0 ||
2227 hw->phy.sfp_type == txgbe_sfp_type_1g_cu_core1 ||
2228 hw->phy.sfp_type == txgbe_sfp_type_1g_lx_core0 ||
2229 hw->phy.sfp_type == txgbe_sfp_type_1g_lx_core1 ||
2230 hw->phy.sfp_type == txgbe_sfp_type_1g_sx_core0 ||
2231 hw->phy.sfp_type == txgbe_sfp_type_1g_sx_core1) {
2232 *speed = TXGBE_LINK_SPEED_1GB_FULL;
2238 * Determine link capabilities based on the stored value of AUTOC,
2239 * which represents EEPROM defaults. If AUTOC value has not
2240 * been stored, use the current register values.
2242 if (hw->mac.orig_link_settings_stored)
2243 autoc = hw->mac.orig_autoc;
2245 autoc = hw->mac.autoc_read(hw);
2247 switch (autoc & TXGBE_AUTOC_LMS_MASK) {
2248 case TXGBE_AUTOC_LMS_1G_LINK_NO_AN:
2249 *speed = TXGBE_LINK_SPEED_1GB_FULL;
2253 case TXGBE_AUTOC_LMS_10G_LINK_NO_AN:
2254 *speed = TXGBE_LINK_SPEED_10GB_FULL;
2258 case TXGBE_AUTOC_LMS_1G_AN:
2259 *speed = TXGBE_LINK_SPEED_1GB_FULL;
2263 case TXGBE_AUTOC_LMS_10G:
2264 *speed = TXGBE_LINK_SPEED_10GB_FULL;
2268 case TXGBE_AUTOC_LMS_KX4_KX_KR:
2269 case TXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN:
2270 *speed = TXGBE_LINK_SPEED_UNKNOWN;
2271 if (autoc & TXGBE_AUTOC_KR_SUPP)
2272 *speed |= TXGBE_LINK_SPEED_10GB_FULL;
2273 if (autoc & TXGBE_AUTOC_KX4_SUPP)
2274 *speed |= TXGBE_LINK_SPEED_10GB_FULL;
2275 if (autoc & TXGBE_AUTOC_KX_SUPP)
2276 *speed |= TXGBE_LINK_SPEED_1GB_FULL;
2280 case TXGBE_AUTOC_LMS_KX4_KX_KR_SGMII:
2281 *speed = TXGBE_LINK_SPEED_100M_FULL;
2282 if (autoc & TXGBE_AUTOC_KR_SUPP)
2283 *speed |= TXGBE_LINK_SPEED_10GB_FULL;
2284 if (autoc & TXGBE_AUTOC_KX4_SUPP)
2285 *speed |= TXGBE_LINK_SPEED_10GB_FULL;
2286 if (autoc & TXGBE_AUTOC_KX_SUPP)
2287 *speed |= TXGBE_LINK_SPEED_1GB_FULL;
2291 case TXGBE_AUTOC_LMS_SGMII_1G_100M:
2292 *speed = TXGBE_LINK_SPEED_1GB_FULL |
2293 TXGBE_LINK_SPEED_100M_FULL |
2294 TXGBE_LINK_SPEED_10M_FULL;
2299 return TXGBE_ERR_LINK_SETUP;
2302 if (hw->phy.multispeed_fiber) {
2303 *speed |= TXGBE_LINK_SPEED_10GB_FULL |
2304 TXGBE_LINK_SPEED_1GB_FULL;
2306 /* QSFP must not enable full auto-negotiation
2307 * Limited autoneg is enabled at 1G
2309 if (hw->phy.media_type == txgbe_media_type_fiber_qsfp)
2319 * txgbe_get_media_type_raptor - Get media type
2320 * @hw: pointer to hardware structure
2322 * Returns the media type (fiber, copper, backplane)
2324 u32 txgbe_get_media_type_raptor(struct txgbe_hw *hw)
2328 DEBUGFUNC("txgbe_get_media_type_raptor");
2330 /* Detect if there is a copper PHY attached. */
2331 switch (hw->phy.type) {
2332 case txgbe_phy_cu_unknown:
2334 media_type = txgbe_media_type_copper;
2340 switch (hw->device_id) {
2341 case TXGBE_DEV_ID_RAPTOR_KR_KX_KX4:
2342 /* Default device ID is mezzanine card KX/KX4 */
2343 media_type = txgbe_media_type_backplane;
2345 case TXGBE_DEV_ID_RAPTOR_SFP:
2346 case TXGBE_DEV_ID_WX1820_SFP:
2347 media_type = txgbe_media_type_fiber;
2349 case TXGBE_DEV_ID_RAPTOR_QSFP:
2350 media_type = txgbe_media_type_fiber_qsfp;
2352 case TXGBE_DEV_ID_RAPTOR_XAUI:
2353 case TXGBE_DEV_ID_RAPTOR_SGMII:
2354 media_type = txgbe_media_type_copper;
2357 media_type = txgbe_media_type_unknown;
2365 * txgbe_start_mac_link_raptor - Setup MAC link settings
2366 * @hw: pointer to hardware structure
2367 * @autoneg_wait_to_complete: true when waiting for completion is needed
2369 * Configures link settings based on values in the txgbe_hw struct.
2370 * Restarts the link. Performs autonegotiation if needed.
2372 s32 txgbe_start_mac_link_raptor(struct txgbe_hw *hw,
2373 bool autoneg_wait_to_complete)
2376 bool got_lock = false;
2378 DEBUGFUNC("txgbe_start_mac_link_raptor");
2380 UNREFERENCED_PARAMETER(autoneg_wait_to_complete);
2382 /* reset_pipeline requires us to hold this lock as it writes to
2385 if (txgbe_verify_lesm_fw_enabled_raptor(hw)) {
2386 status = hw->mac.acquire_swfw_sync(hw, TXGBE_MNGSEM_SWPHY);
2394 txgbe_reset_pipeline_raptor(hw);
2397 hw->mac.release_swfw_sync(hw, TXGBE_MNGSEM_SWPHY);
2399 /* Add delay to filter out noises during initial link setup */
2407 * txgbe_disable_tx_laser_multispeed_fiber - Disable Tx laser
2408 * @hw: pointer to hardware structure
2410 * The base drivers may require better control over SFP+ module
2411 * PHY states. This includes selectively shutting down the Tx
2412 * laser on the PHY, effectively halting physical link.
2414 void txgbe_disable_tx_laser_multispeed_fiber(struct txgbe_hw *hw)
2416 u32 esdp_reg = rd32(hw, TXGBE_GPIODATA);
2418 /* Blocked by MNG FW so bail */
2419 if (txgbe_check_reset_blocked(hw))
2422 /* Disable Tx laser; allow 100us to go dark per spec */
2423 esdp_reg |= (TXGBE_GPIOBIT_0 | TXGBE_GPIOBIT_1);
2424 wr32(hw, TXGBE_GPIODATA, esdp_reg);
2430 * txgbe_enable_tx_laser_multispeed_fiber - Enable Tx laser
2431 * @hw: pointer to hardware structure
2433 * The base drivers may require better control over SFP+ module
2434 * PHY states. This includes selectively turning on the Tx
2435 * laser on the PHY, effectively starting physical link.
2437 void txgbe_enable_tx_laser_multispeed_fiber(struct txgbe_hw *hw)
2439 u32 esdp_reg = rd32(hw, TXGBE_GPIODATA);
2441 /* Enable Tx laser; allow 100ms to light up */
2442 esdp_reg &= ~(TXGBE_GPIOBIT_0 | TXGBE_GPIOBIT_1);
2443 wr32(hw, TXGBE_GPIODATA, esdp_reg);
2449 * txgbe_flap_tx_laser_multispeed_fiber - Flap Tx laser
2450 * @hw: pointer to hardware structure
2452 * When the driver changes the link speeds that it can support,
2453 * it sets autotry_restart to true to indicate that we need to
2454 * initiate a new autotry session with the link partner. To do
2455 * so, we set the speed then disable and re-enable the Tx laser, to
2456 * alert the link partner that it also needs to restart autotry on its
2457 * end. This is consistent with true clause 37 autoneg, which also
2458 * involves a loss of signal.
2460 void txgbe_flap_tx_laser_multispeed_fiber(struct txgbe_hw *hw)
2462 DEBUGFUNC("txgbe_flap_tx_laser_multispeed_fiber");
2464 /* Blocked by MNG FW so bail */
2465 if (txgbe_check_reset_blocked(hw))
2468 if (hw->mac.autotry_restart) {
2469 txgbe_disable_tx_laser_multispeed_fiber(hw);
2470 txgbe_enable_tx_laser_multispeed_fiber(hw);
2471 hw->mac.autotry_restart = false;
2476 * txgbe_set_hard_rate_select_speed - Set module link speed
2477 * @hw: pointer to hardware structure
2478 * @speed: link speed to set
2480 * Set module link speed via RS0/RS1 rate select pins.
2482 void txgbe_set_hard_rate_select_speed(struct txgbe_hw *hw,
2485 u32 esdp_reg = rd32(hw, TXGBE_GPIODATA);
2488 case TXGBE_LINK_SPEED_10GB_FULL:
2489 esdp_reg |= (TXGBE_GPIOBIT_4 | TXGBE_GPIOBIT_5);
2491 case TXGBE_LINK_SPEED_1GB_FULL:
2492 esdp_reg &= ~(TXGBE_GPIOBIT_4 | TXGBE_GPIOBIT_5);
2495 DEBUGOUT("Invalid fixed module speed\n");
2499 wr32(hw, TXGBE_GPIODATA, esdp_reg);
2504 * txgbe_setup_mac_link_smartspeed - Set MAC link speed using SmartSpeed
2505 * @hw: pointer to hardware structure
2506 * @speed: new link speed
2507 * @autoneg_wait_to_complete: true when waiting for completion is needed
2509 * Implements the Intel SmartSpeed algorithm.
2511 s32 txgbe_setup_mac_link_smartspeed(struct txgbe_hw *hw,
2513 bool autoneg_wait_to_complete)
2516 u32 link_speed = TXGBE_LINK_SPEED_UNKNOWN;
2518 bool link_up = false;
2519 u32 autoc_reg = rd32_epcs(hw, SR_AN_MMD_ADV_REG1);
2521 DEBUGFUNC("txgbe_setup_mac_link_smartspeed");
2523 /* Set autoneg_advertised value based on input link speed */
2524 hw->phy.autoneg_advertised = 0;
2526 if (speed & TXGBE_LINK_SPEED_10GB_FULL)
2527 hw->phy.autoneg_advertised |= TXGBE_LINK_SPEED_10GB_FULL;
2529 if (speed & TXGBE_LINK_SPEED_1GB_FULL)
2530 hw->phy.autoneg_advertised |= TXGBE_LINK_SPEED_1GB_FULL;
2532 if (speed & TXGBE_LINK_SPEED_100M_FULL)
2533 hw->phy.autoneg_advertised |= TXGBE_LINK_SPEED_100M_FULL;
2536 * Implement Intel SmartSpeed algorithm. SmartSpeed will reduce the
2537 * autoneg advertisement if link is unable to be established at the
2538 * highest negotiated rate. This can sometimes happen due to integrity
2539 * issues with the physical media connection.
2542 /* First, try to get link with full advertisement */
2543 hw->phy.smart_speed_active = false;
2544 for (j = 0; j < TXGBE_SMARTSPEED_MAX_RETRIES; j++) {
2545 status = txgbe_setup_mac_link(hw, speed,
2546 autoneg_wait_to_complete);
2551 * Wait for the controller to acquire link. Per IEEE 802.3ap,
2552 * Section 73.10.2, we may have to wait up to 500ms if KR is
2553 * attempted, or 200ms if KX/KX4/BX/BX4 is attempted, per
2554 * Table 9 in the AN MAS.
2556 for (i = 0; i < 5; i++) {
2559 /* If we have link, just jump out */
2560 status = hw->mac.check_link(hw, &link_speed, &link_up,
2571 * We didn't get link. If we advertised KR plus one of KX4/KX
2572 * (or BX4/BX), then disable KR and try again.
2574 if (((autoc_reg & TXGBE_AUTOC_KR_SUPP) == 0) ||
2575 ((autoc_reg & TXGBE_AUTOC_KX_SUPP) == 0 &&
2576 (autoc_reg & TXGBE_AUTOC_KX4_SUPP) == 0))
2579 /* Turn SmartSpeed on to disable KR support */
2580 hw->phy.smart_speed_active = true;
2581 status = txgbe_setup_mac_link(hw, speed,
2582 autoneg_wait_to_complete);
2587 * Wait for the controller to acquire link. 600ms will allow for
2588 * the AN link_fail_inhibit_timer as well for multiple cycles of
2589 * parallel detect, both 10g and 1g. This allows for the maximum
2590 * connect attempts as defined in the AN MAS table 73-7.
2592 for (i = 0; i < 6; i++) {
2595 /* If we have link, just jump out */
2596 status = hw->mac.check_link(hw, &link_speed, &link_up, false);
2604 /* We didn't get link. Turn SmartSpeed back off. */
2605 hw->phy.smart_speed_active = false;
2606 status = txgbe_setup_mac_link(hw, speed,
2607 autoneg_wait_to_complete);
2610 if (link_up && link_speed == TXGBE_LINK_SPEED_1GB_FULL)
2611 DEBUGOUT("Smartspeed has downgraded the link speed "
2612 "from the maximum advertised\n");
2617 * txgbe_setup_mac_link - Set MAC link speed
2618 * @hw: pointer to hardware structure
2619 * @speed: new link speed
2620 * @autoneg_wait_to_complete: true when waiting for completion is needed
2622 * Set the link speed in the AUTOC register and restarts link.
2624 s32 txgbe_setup_mac_link(struct txgbe_hw *hw,
2626 bool autoneg_wait_to_complete)
2628 bool autoneg = false;
2631 u64 autoc = hw->mac.autoc_read(hw);
2632 u64 pma_pmd_10gs = autoc & TXGBE_AUTOC_10GS_PMA_PMD_MASK;
2633 u64 pma_pmd_1g = autoc & TXGBE_AUTOC_1G_PMA_PMD_MASK;
2634 u64 link_mode = autoc & TXGBE_AUTOC_LMS_MASK;
2635 u64 current_autoc = autoc;
2639 u32 link_capabilities = TXGBE_LINK_SPEED_UNKNOWN;
2641 DEBUGFUNC("txgbe_setup_mac_link");
2643 /* Check to see if speed passed in is supported. */
2644 status = hw->mac.get_link_capabilities(hw,
2645 &link_capabilities, &autoneg);
2649 speed &= link_capabilities;
2650 if (speed == TXGBE_LINK_SPEED_UNKNOWN)
2651 return TXGBE_ERR_LINK_SETUP;
2653 /* Use stored value (EEPROM defaults) of AUTOC to find KR/KX4 support*/
2654 if (hw->mac.orig_link_settings_stored)
2655 orig_autoc = hw->mac.orig_autoc;
2659 link_mode = autoc & TXGBE_AUTOC_LMS_MASK;
2660 pma_pmd_1g = autoc & TXGBE_AUTOC_1G_PMA_PMD_MASK;
2662 if (link_mode == TXGBE_AUTOC_LMS_KX4_KX_KR ||
2663 link_mode == TXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
2664 link_mode == TXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
2665 /* Set KX4/KX/KR support according to speed requested */
2666 autoc &= ~(TXGBE_AUTOC_KX_SUPP |
2667 TXGBE_AUTOC_KX4_SUPP |
2668 TXGBE_AUTOC_KR_SUPP);
2669 if (speed & TXGBE_LINK_SPEED_10GB_FULL) {
2670 if (orig_autoc & TXGBE_AUTOC_KX4_SUPP)
2671 autoc |= TXGBE_AUTOC_KX4_SUPP;
2672 if ((orig_autoc & TXGBE_AUTOC_KR_SUPP) &&
2673 !hw->phy.smart_speed_active)
2674 autoc |= TXGBE_AUTOC_KR_SUPP;
2676 if (speed & TXGBE_LINK_SPEED_1GB_FULL)
2677 autoc |= TXGBE_AUTOC_KX_SUPP;
2678 } else if ((pma_pmd_1g == TXGBE_AUTOC_1G_SFI) &&
2679 (link_mode == TXGBE_AUTOC_LMS_1G_LINK_NO_AN ||
2680 link_mode == TXGBE_AUTOC_LMS_1G_AN)) {
2681 /* Switch from 1G SFI to 10G SFI if requested */
2682 if (speed == TXGBE_LINK_SPEED_10GB_FULL &&
2683 pma_pmd_10gs == TXGBE_AUTOC_10GS_SFI) {
2684 autoc &= ~TXGBE_AUTOC_LMS_MASK;
2685 autoc |= TXGBE_AUTOC_LMS_10G;
2687 } else if ((pma_pmd_10gs == TXGBE_AUTOC_10GS_SFI) &&
2688 (link_mode == TXGBE_AUTOC_LMS_10G)) {
2689 /* Switch from 10G SFI to 1G SFI if requested */
2690 if (speed == TXGBE_LINK_SPEED_1GB_FULL &&
2691 pma_pmd_1g == TXGBE_AUTOC_1G_SFI) {
2692 autoc &= ~TXGBE_AUTOC_LMS_MASK;
2693 if (autoneg || hw->phy.type == txgbe_phy_qsfp_intel)
2694 autoc |= TXGBE_AUTOC_LMS_1G_AN;
2696 autoc |= TXGBE_AUTOC_LMS_1G_LINK_NO_AN;
2700 if (autoc == current_autoc)
2703 autoc &= ~TXGBE_AUTOC_SPEED_MASK;
2704 autoc |= TXGBE_AUTOC_SPEED(speed);
2705 autoc |= (autoneg ? TXGBE_AUTOC_AUTONEG : 0);
2708 hw->mac.autoc_write(hw, autoc);
2710 /* Only poll for autoneg to complete if specified to do so */
2711 if (autoneg_wait_to_complete) {
2712 if (link_mode == TXGBE_AUTOC_LMS_KX4_KX_KR ||
2713 link_mode == TXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
2714 link_mode == TXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
2715 links_reg = 0; /*Just in case Autoneg time=0*/
2716 for (i = 0; i < TXGBE_AUTO_NEG_TIME; i++) {
2717 links_reg = rd32(hw, TXGBE_PORTSTAT);
2718 if (links_reg & TXGBE_PORTSTAT_UP)
2722 if (!(links_reg & TXGBE_PORTSTAT_UP)) {
2723 status = TXGBE_ERR_AUTONEG_NOT_COMPLETE;
2724 DEBUGOUT("Autoneg did not complete.\n");
2729 /* Add delay to filter out noises during initial link setup */
2736 * txgbe_setup_copper_link_raptor - Set the PHY autoneg advertised field
2737 * @hw: pointer to hardware structure
2738 * @speed: new link speed
2739 * @autoneg_wait_to_complete: true if waiting is needed to complete
2741 * Restarts link on PHY and MAC based on settings passed in.
2743 static s32 txgbe_setup_copper_link_raptor(struct txgbe_hw *hw,
2745 bool autoneg_wait_to_complete)
2749 DEBUGFUNC("txgbe_setup_copper_link_raptor");
2751 /* Setup the PHY according to input speed */
2752 status = hw->phy.setup_link_speed(hw, speed,
2753 autoneg_wait_to_complete);
2755 txgbe_start_mac_link_raptor(hw, autoneg_wait_to_complete);
2761 txgbe_check_flash_load(struct txgbe_hw *hw, u32 check_bit)
2766 /* if there's flash existing */
2767 if (!(rd32(hw, TXGBE_SPISTAT) & TXGBE_SPISTAT_BPFLASH)) {
2768 /* wait hw load flash done */
2769 for (i = 0; i < 10; i++) {
2770 reg = rd32(hw, TXGBE_ILDRSTAT);
2771 if (!(reg & check_bit)) {
2778 err = TXGBE_ERR_FLASH_LOADING_FAILED;
2784 txgbe_reset_misc(struct txgbe_hw *hw)
2789 wr32(hw, TXGBE_ISBADDRL, hw->isb_dma & 0x00000000FFFFFFFF);
2790 wr32(hw, TXGBE_ISBADDRH, hw->isb_dma >> 32);
2792 value = rd32_epcs(hw, SR_XS_PCS_CTRL2);
2793 if ((value & 0x3) != SR_PCS_CTRL2_TYPE_SEL_X)
2794 hw->link_status = TXGBE_LINK_STATUS_NONE;
2796 /* receive packets that size > 2048 */
2797 wr32m(hw, TXGBE_MACRXCFG,
2798 TXGBE_MACRXCFG_JUMBO, TXGBE_MACRXCFG_JUMBO);
2800 wr32m(hw, TXGBE_FRMSZ, TXGBE_FRMSZ_MAX_MASK,
2801 TXGBE_FRMSZ_MAX(TXGBE_FRAME_SIZE_DFT));
2803 /* clear counters on read */
2804 wr32m(hw, TXGBE_MACCNTCTL,
2805 TXGBE_MACCNTCTL_RC, TXGBE_MACCNTCTL_RC);
2807 wr32m(hw, TXGBE_RXFCCFG,
2808 TXGBE_RXFCCFG_FC, TXGBE_RXFCCFG_FC);
2809 wr32m(hw, TXGBE_TXFCCFG,
2810 TXGBE_TXFCCFG_FC, TXGBE_TXFCCFG_FC);
2812 wr32m(hw, TXGBE_MACRXFLT,
2813 TXGBE_MACRXFLT_PROMISC, TXGBE_MACRXFLT_PROMISC);
2815 wr32m(hw, TXGBE_RSTSTAT,
2816 TXGBE_RSTSTAT_TMRINIT_MASK, TXGBE_RSTSTAT_TMRINIT(30));
2818 /* errata 4: initialize mng flex tbl and wakeup flex tbl*/
2819 wr32(hw, TXGBE_MNGFLEXSEL, 0);
2820 for (i = 0; i < 16; i++) {
2821 wr32(hw, TXGBE_MNGFLEXDWL(i), 0);
2822 wr32(hw, TXGBE_MNGFLEXDWH(i), 0);
2823 wr32(hw, TXGBE_MNGFLEXMSK(i), 0);
2825 wr32(hw, TXGBE_LANFLEXSEL, 0);
2826 for (i = 0; i < 16; i++) {
2827 wr32(hw, TXGBE_LANFLEXDWL(i), 0);
2828 wr32(hw, TXGBE_LANFLEXDWH(i), 0);
2829 wr32(hw, TXGBE_LANFLEXMSK(i), 0);
2832 /* set pause frame dst mac addr */
2833 wr32(hw, TXGBE_RXPBPFCDMACL, 0xC2000001);
2834 wr32(hw, TXGBE_RXPBPFCDMACH, 0x0180);
2836 hw->mac.init_thermal_sensor_thresh(hw);
2838 /* enable mac transmitter */
2839 wr32m(hw, TXGBE_MACTXCFG, TXGBE_MACTXCFG_TXE, TXGBE_MACTXCFG_TXE);
2841 for (i = 0; i < 4; i++)
2842 wr32m(hw, TXGBE_IVAR(i), 0x80808080, 0);
2846 * txgbe_reset_hw - Perform hardware reset
2847 * @hw: pointer to hardware structure
2849 * Resets the hardware by resetting the transmit and receive units, masks
2850 * and clears all interrupts, perform a PHY reset, and perform a link (MAC)
2853 s32 txgbe_reset_hw(struct txgbe_hw *hw)
2858 DEBUGFUNC("txgbe_reset_hw");
2860 /* Call adapter stop to disable tx/rx and clear interrupts */
2861 status = hw->mac.stop_hw(hw);
2865 /* flush pending Tx transactions */
2866 txgbe_clear_tx_pending(hw);
2868 /* Identify PHY and related function pointers */
2869 status = hw->phy.init(hw);
2870 if (status == TXGBE_ERR_SFP_NOT_SUPPORTED)
2873 /* Setup SFP module if there is one present. */
2874 if (hw->phy.sfp_setup_needed) {
2875 status = hw->mac.setup_sfp(hw);
2876 hw->phy.sfp_setup_needed = false;
2878 if (status == TXGBE_ERR_SFP_NOT_SUPPORTED)
2882 if (!hw->phy.reset_disable)
2885 /* remember AUTOC from before we reset */
2886 autoc = hw->mac.autoc_read(hw);
2890 * Issue global reset to the MAC. Needs to be SW reset if link is up.
2891 * If link reset is used when link is up, it might reset the PHY when
2892 * mng is using it. If link is down or the flag to force full link
2893 * reset is set, then perform link reset.
2895 if (txgbe_mng_present(hw)) {
2896 txgbe_hic_reset(hw);
2898 wr32(hw, TXGBE_RST, TXGBE_RST_LAN(hw->bus.lan_id));
2903 txgbe_reset_misc(hw);
2905 if (hw->bus.lan_id == 0) {
2906 status = txgbe_check_flash_load(hw,
2907 TXGBE_ILDRSTAT_SWRST_LAN0);
2909 status = txgbe_check_flash_load(hw,
2910 TXGBE_ILDRSTAT_SWRST_LAN1);
2918 * Double resets are required for recovery from certain error
2919 * conditions. Between resets, it is necessary to stall to
2920 * allow time for any pending HW events to complete.
2922 if (hw->mac.flags & TXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
2923 hw->mac.flags &= ~TXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
2928 * Store the original AUTOC/AUTOC2 values if they have not been
2929 * stored off yet. Otherwise restore the stored original
2930 * values since the reset operation sets back to defaults.
2932 if (!hw->mac.orig_link_settings_stored) {
2933 hw->mac.orig_autoc = hw->mac.autoc_read(hw);
2934 hw->mac.autoc_write(hw, hw->mac.orig_autoc);
2935 hw->mac.orig_link_settings_stored = true;
2937 hw->mac.orig_autoc = autoc;
2940 /* Store the permanent mac address */
2941 hw->mac.get_mac_addr(hw, hw->mac.perm_addr);
2944 * Store MAC address from RAR0, clear receive address registers, and
2945 * clear the multicast table. Also reset num_rar_entries to 128,
2946 * since we modify this value when programming the SAN MAC address.
2948 hw->mac.num_rar_entries = 128;
2949 hw->mac.init_rx_addrs(hw);
2951 /* Store the permanent SAN mac address */
2952 hw->mac.get_san_mac_addr(hw, hw->mac.san_addr);
2954 /* Add the SAN MAC address to the RAR only if it's a valid address */
2955 if (txgbe_validate_mac_addr(hw->mac.san_addr) == 0) {
2956 /* Save the SAN MAC RAR index */
2957 hw->mac.san_mac_rar_index = hw->mac.num_rar_entries - 1;
2959 hw->mac.set_rar(hw, hw->mac.san_mac_rar_index,
2960 hw->mac.san_addr, 0, true);
2962 /* clear VMDq pool/queue selection for this RAR */
2963 hw->mac.clear_vmdq(hw, hw->mac.san_mac_rar_index,
2966 /* Reserve the last RAR for the SAN MAC address */
2967 hw->mac.num_rar_entries--;
2970 /* Store the alternative WWNN/WWPN prefix */
2971 hw->mac.get_wwn_prefix(hw, &hw->mac.wwnn_prefix,
2972 &hw->mac.wwpn_prefix);
2978 * txgbe_start_hw_raptor - Prepare hardware for Tx/Rx
2979 * @hw: pointer to hardware structure
2981 * Starts the hardware using the generic start_hw function
2982 * and the generation start_hw function.
2983 * Then performs revision-specific operations, if any.
2985 s32 txgbe_start_hw_raptor(struct txgbe_hw *hw)
2989 DEBUGFUNC("txgbe_start_hw_raptor");
2991 err = txgbe_start_hw(hw);
2995 err = txgbe_start_hw_gen2(hw);
2999 /* We need to run link autotry after the driver loads */
3000 hw->mac.autotry_restart = true;
3007 * txgbe_enable_rx_dma_raptor - Enable the Rx DMA unit
3008 * @hw: pointer to hardware structure
3009 * @regval: register value to write to RXCTRL
3011 * Enables the Rx DMA unit
3013 s32 txgbe_enable_rx_dma_raptor(struct txgbe_hw *hw, u32 regval)
3015 DEBUGFUNC("txgbe_enable_rx_dma_raptor");
3018 * Workaround silicon errata when enabling the Rx datapath.
3019 * If traffic is incoming before we enable the Rx unit, it could hang
3020 * the Rx DMA unit. Therefore, make sure the security engine is
3021 * completely disabled prior to enabling the Rx unit.
3024 hw->mac.disable_sec_rx_path(hw);
3026 if (regval & TXGBE_PBRXCTL_ENA)
3027 txgbe_enable_rx(hw);
3029 txgbe_disable_rx(hw);
3031 hw->mac.enable_sec_rx_path(hw);
3037 * txgbe_verify_lesm_fw_enabled_raptor - Checks LESM FW module state.
3038 * @hw: pointer to hardware structure
3040 * Returns true if the LESM FW module is present and enabled. Otherwise
3041 * returns false. Smart Speed must be disabled if LESM FW module is enabled.
3043 bool txgbe_verify_lesm_fw_enabled_raptor(struct txgbe_hw *hw)
3045 bool lesm_enabled = false;
3046 u16 fw_offset, fw_lesm_param_offset, fw_lesm_state;
3049 DEBUGFUNC("txgbe_verify_lesm_fw_enabled_raptor");
3051 /* get the offset to the Firmware Module block */
3052 status = hw->rom.read16(hw, TXGBE_FW_PTR, &fw_offset);
3054 if (status != 0 || fw_offset == 0 || fw_offset == 0xFFFF)
3057 /* get the offset to the LESM Parameters block */
3058 status = hw->rom.read16(hw, (fw_offset +
3059 TXGBE_FW_LESM_PARAMETERS_PTR),
3060 &fw_lesm_param_offset);
3063 fw_lesm_param_offset == 0 || fw_lesm_param_offset == 0xFFFF)
3066 /* get the LESM state word */
3067 status = hw->rom.read16(hw, (fw_lesm_param_offset +
3068 TXGBE_FW_LESM_STATE_1),
3071 if (status == 0 && (fw_lesm_state & TXGBE_FW_LESM_STATE_ENABLED))
3072 lesm_enabled = true;
3075 lesm_enabled = false;
3076 return lesm_enabled;
3080 * txgbe_reset_pipeline_raptor - perform pipeline reset
3082 * @hw: pointer to hardware structure
3084 * Reset pipeline by asserting Restart_AN together with LMS change to ensure
3085 * full pipeline reset. This function assumes the SW/FW lock is held.
3087 s32 txgbe_reset_pipeline_raptor(struct txgbe_hw *hw)
3092 autoc = hw->mac.autoc_read(hw);
3094 /* Enable link if disabled in NVM */
3095 if (autoc & TXGBE_AUTOC_LINK_DIA_MASK)
3096 autoc &= ~TXGBE_AUTOC_LINK_DIA_MASK;
3098 autoc |= TXGBE_AUTOC_AN_RESTART;
3099 /* Write AUTOC register with toggled LMS[2] bit and Restart_AN */
3100 hw->mac.autoc_write(hw, autoc ^ TXGBE_AUTOC_LMS_AN);
3102 /* Write AUTOC register with original LMS field and Restart_AN */
3103 hw->mac.autoc_write(hw, autoc);