1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2015-2020
5 #include "txgbe_type.h"
8 #include "txgbe_eeprom.h"
12 #define TXGBE_RAPTOR_MAX_TX_QUEUES 128
13 #define TXGBE_RAPTOR_MAX_RX_QUEUES 128
14 #define TXGBE_RAPTOR_RAR_ENTRIES 128
15 #define TXGBE_RAPTOR_MC_TBL_SIZE 128
16 #define TXGBE_RAPTOR_VFT_TBL_SIZE 128
18 static s32 txgbe_setup_copper_link_raptor(struct txgbe_hw *hw,
20 bool autoneg_wait_to_complete);
22 static s32 txgbe_mta_vector(struct txgbe_hw *hw, u8 *mc_addr);
23 static s32 txgbe_get_san_mac_addr_offset(struct txgbe_hw *hw,
27 * txgbe_start_hw - Prepare hardware for Tx/Rx
28 * @hw: pointer to hardware structure
30 * Starts the hardware by filling the bus info structure and media type, clears
31 * all on chip counters, initializes receive address registers, multicast
32 * table, VLAN filter table, calls routine to set up link and flow control
33 * settings, and leaves transmit and receive units disabled and uninitialized
35 s32 txgbe_start_hw(struct txgbe_hw *hw)
39 DEBUGFUNC("txgbe_start_hw");
41 /* Set the media type */
42 hw->phy.media_type = hw->phy.get_media_type(hw);
44 /* Clear the VLAN filter table */
45 hw->mac.clear_vfta(hw);
47 /* Clear statistics registers */
48 hw->mac.clear_hw_cntrs(hw);
50 /* Cache bit indicating need for crosstalk fix */
51 switch (hw->mac.type) {
52 case txgbe_mac_raptor:
53 hw->mac.get_device_caps(hw, &device_caps);
54 if (device_caps & TXGBE_DEVICE_CAPS_NO_CROSSTALK_WR)
55 hw->need_crosstalk_fix = false;
57 hw->need_crosstalk_fix = true;
60 hw->need_crosstalk_fix = false;
64 /* Clear adapter stopped flag */
65 hw->adapter_stopped = false;
71 * txgbe_start_hw_gen2 - Init sequence for common device family
72 * @hw: pointer to hw structure
74 * Performs the init sequence common to the second generation
77 s32 txgbe_start_hw_gen2(struct txgbe_hw *hw)
81 /* Clear the rate limiters */
82 for (i = 0; i < hw->mac.max_tx_queues; i++) {
83 wr32(hw, TXGBE_ARBPOOLIDX, i);
84 wr32(hw, TXGBE_ARBTXRATE, 0);
88 /* We need to run link autotry after the driver loads */
89 hw->mac.autotry_restart = true;
95 * txgbe_init_hw - Generic hardware initialization
96 * @hw: pointer to hardware structure
98 * Initialize the hardware by resetting the hardware, filling the bus info
99 * structure and media type, clears all on chip counters, initializes receive
100 * address registers, multicast table, VLAN filter table, calls routine to set
101 * up link and flow control settings, and leaves transmit and receive units
102 * disabled and uninitialized
104 s32 txgbe_init_hw(struct txgbe_hw *hw)
108 DEBUGFUNC("txgbe_init_hw");
110 /* Reset the hardware */
111 status = hw->mac.reset_hw(hw);
112 if (status == 0 || status == TXGBE_ERR_SFP_NOT_PRESENT) {
114 status = hw->mac.start_hw(hw);
118 DEBUGOUT("Failed to initialize HW, STATUS = %d\n", status);
124 * txgbe_clear_hw_cntrs - Generic clear hardware counters
125 * @hw: pointer to hardware structure
127 * Clears all hardware statistics counters by reading them from the hardware
128 * Statistics counters are clear on read.
130 s32 txgbe_clear_hw_cntrs(struct txgbe_hw *hw)
134 DEBUGFUNC("txgbe_clear_hw_cntrs");
137 /* don't write clear queue stats */
138 for (i = 0; i < TXGBE_MAX_QP; i++) {
139 hw->qp_last[i].rx_qp_packets = 0;
140 hw->qp_last[i].tx_qp_packets = 0;
141 hw->qp_last[i].rx_qp_bytes = 0;
142 hw->qp_last[i].tx_qp_bytes = 0;
143 hw->qp_last[i].rx_qp_mc_packets = 0;
147 for (i = 0; i < TXGBE_MAX_UP; i++) {
148 rd32(hw, TXGBE_PBRXUPXON(i));
149 rd32(hw, TXGBE_PBRXUPXOFF(i));
150 rd32(hw, TXGBE_PBTXUPXON(i));
151 rd32(hw, TXGBE_PBTXUPXOFF(i));
152 rd32(hw, TXGBE_PBTXUPOFF(i));
154 rd32(hw, TXGBE_PBRXMISS(i));
156 rd32(hw, TXGBE_PBRXLNKXON);
157 rd32(hw, TXGBE_PBRXLNKXOFF);
158 rd32(hw, TXGBE_PBTXLNKXON);
159 rd32(hw, TXGBE_PBTXLNKXOFF);
162 rd32(hw, TXGBE_DMARXPKT);
163 rd32(hw, TXGBE_DMATXPKT);
165 rd64(hw, TXGBE_DMARXOCTL);
166 rd64(hw, TXGBE_DMATXOCTL);
169 rd64(hw, TXGBE_MACRXERRCRCL);
170 rd64(hw, TXGBE_MACRXMPKTL);
171 rd64(hw, TXGBE_MACTXMPKTL);
173 rd64(hw, TXGBE_MACRXPKTL);
174 rd64(hw, TXGBE_MACTXPKTL);
175 rd64(hw, TXGBE_MACRXGBOCTL);
177 rd64(hw, TXGBE_MACRXOCTL);
178 rd32(hw, TXGBE_MACTXOCTL);
180 rd64(hw, TXGBE_MACRX1TO64L);
181 rd64(hw, TXGBE_MACRX65TO127L);
182 rd64(hw, TXGBE_MACRX128TO255L);
183 rd64(hw, TXGBE_MACRX256TO511L);
184 rd64(hw, TXGBE_MACRX512TO1023L);
185 rd64(hw, TXGBE_MACRX1024TOMAXL);
186 rd64(hw, TXGBE_MACTX1TO64L);
187 rd64(hw, TXGBE_MACTX65TO127L);
188 rd64(hw, TXGBE_MACTX128TO255L);
189 rd64(hw, TXGBE_MACTX256TO511L);
190 rd64(hw, TXGBE_MACTX512TO1023L);
191 rd64(hw, TXGBE_MACTX1024TOMAXL);
193 rd64(hw, TXGBE_MACRXERRLENL);
194 rd32(hw, TXGBE_MACRXOVERSIZE);
195 rd32(hw, TXGBE_MACRXJABBER);
198 rd32(hw, TXGBE_FCOECRC);
199 rd32(hw, TXGBE_FCOELAST);
200 rd32(hw, TXGBE_FCOERPDC);
201 rd32(hw, TXGBE_FCOEPRC);
202 rd32(hw, TXGBE_FCOEPTC);
203 rd32(hw, TXGBE_FCOEDWRC);
204 rd32(hw, TXGBE_FCOEDWTC);
206 /* Flow Director Stats */
207 rd32(hw, TXGBE_FDIRMATCH);
208 rd32(hw, TXGBE_FDIRMISS);
209 rd32(hw, TXGBE_FDIRUSED);
210 rd32(hw, TXGBE_FDIRUSED);
211 rd32(hw, TXGBE_FDIRFAIL);
212 rd32(hw, TXGBE_FDIRFAIL);
215 rd32(hw, TXGBE_LSECTX_UTPKT);
216 rd32(hw, TXGBE_LSECTX_ENCPKT);
217 rd32(hw, TXGBE_LSECTX_PROTPKT);
218 rd32(hw, TXGBE_LSECTX_ENCOCT);
219 rd32(hw, TXGBE_LSECTX_PROTOCT);
220 rd32(hw, TXGBE_LSECRX_UTPKT);
221 rd32(hw, TXGBE_LSECRX_BTPKT);
222 rd32(hw, TXGBE_LSECRX_NOSCIPKT);
223 rd32(hw, TXGBE_LSECRX_UNSCIPKT);
224 rd32(hw, TXGBE_LSECRX_DECOCT);
225 rd32(hw, TXGBE_LSECRX_VLDOCT);
226 rd32(hw, TXGBE_LSECRX_UNCHKPKT);
227 rd32(hw, TXGBE_LSECRX_DLYPKT);
228 rd32(hw, TXGBE_LSECRX_LATEPKT);
229 for (i = 0; i < 2; i++) {
230 rd32(hw, TXGBE_LSECRX_OKPKT(i));
231 rd32(hw, TXGBE_LSECRX_INVPKT(i));
232 rd32(hw, TXGBE_LSECRX_BADPKT(i));
234 rd32(hw, TXGBE_LSECRX_INVSAPKT);
235 rd32(hw, TXGBE_LSECRX_BADSAPKT);
241 * txgbe_get_mac_addr - Generic get MAC address
242 * @hw: pointer to hardware structure
243 * @mac_addr: Adapter MAC address
245 * Reads the adapter's MAC address from first Receive Address Register (RAR0)
246 * A reset of the adapter must be performed prior to calling this function
247 * in order for the MAC address to have been loaded from the EEPROM into RAR0
249 s32 txgbe_get_mac_addr(struct txgbe_hw *hw, u8 *mac_addr)
255 DEBUGFUNC("txgbe_get_mac_addr");
257 wr32(hw, TXGBE_ETHADDRIDX, 0);
258 rar_high = rd32(hw, TXGBE_ETHADDRH);
259 rar_low = rd32(hw, TXGBE_ETHADDRL);
261 for (i = 0; i < 2; i++)
262 mac_addr[i] = (u8)(rar_high >> (1 - i) * 8);
264 for (i = 0; i < 4; i++)
265 mac_addr[i + 2] = (u8)(rar_low >> (3 - i) * 8);
271 * txgbe_set_lan_id_multi_port - Set LAN id for PCIe multiple port devices
272 * @hw: pointer to the HW structure
274 * Determines the LAN function id by reading memory-mapped registers and swaps
275 * the port value if requested, and set MAC instance for devices.
277 void txgbe_set_lan_id_multi_port(struct txgbe_hw *hw)
279 struct txgbe_bus_info *bus = &hw->bus;
282 DEBUGFUNC("txgbe_set_lan_id_multi_port_pcie");
284 reg = rd32(hw, TXGBE_PORTSTAT);
285 bus->lan_id = TXGBE_PORTSTAT_ID(reg);
287 /* check for single port */
288 reg = rd32(hw, TXGBE_PWR);
289 if (TXGBE_PWR_LANID(reg) == TXGBE_PWR_LANID_SWAP)
292 bus->func = bus->lan_id;
296 * txgbe_stop_hw - Generic stop Tx/Rx units
297 * @hw: pointer to hardware structure
299 * Sets the adapter_stopped flag within txgbe_hw struct. Clears interrupts,
300 * disables transmit and receive units. The adapter_stopped flag is used by
301 * the shared code and drivers to determine if the adapter is in a stopped
302 * state and should not touch the hardware.
304 s32 txgbe_stop_hw(struct txgbe_hw *hw)
309 DEBUGFUNC("txgbe_stop_hw");
312 * Set the adapter_stopped flag so other driver functions stop touching
315 hw->adapter_stopped = true;
317 /* Disable the receive unit */
318 txgbe_disable_rx(hw);
320 /* Clear interrupt mask to stop interrupts from being generated */
321 wr32(hw, TXGBE_IENMISC, 0);
322 wr32(hw, TXGBE_IMS(0), TXGBE_IMS_MASK);
323 wr32(hw, TXGBE_IMS(1), TXGBE_IMS_MASK);
325 /* Clear any pending interrupts, flush previous writes */
326 wr32(hw, TXGBE_ICRMISC, TXGBE_ICRMISC_MASK);
327 wr32(hw, TXGBE_ICR(0), TXGBE_ICR_MASK);
328 wr32(hw, TXGBE_ICR(1), TXGBE_ICR_MASK);
330 /* Disable the transmit unit. Each queue must be disabled. */
331 for (i = 0; i < hw->mac.max_tx_queues; i++)
332 wr32(hw, TXGBE_TXCFG(i), TXGBE_TXCFG_FLUSH);
334 /* Disable the receive unit by stopping each queue */
335 for (i = 0; i < hw->mac.max_rx_queues; i++) {
336 reg_val = rd32(hw, TXGBE_RXCFG(i));
337 reg_val &= ~TXGBE_RXCFG_ENA;
338 wr32(hw, TXGBE_RXCFG(i), reg_val);
341 /* flush all queues disables */
349 * txgbe_validate_mac_addr - Validate MAC address
350 * @mac_addr: pointer to MAC address.
352 * Tests a MAC address to ensure it is a valid Individual Address.
354 s32 txgbe_validate_mac_addr(u8 *mac_addr)
358 DEBUGFUNC("txgbe_validate_mac_addr");
360 /* Make sure it is not a multicast address */
361 if (TXGBE_IS_MULTICAST(mac_addr)) {
362 status = TXGBE_ERR_INVALID_MAC_ADDR;
363 /* Not a broadcast address */
364 } else if (TXGBE_IS_BROADCAST(mac_addr)) {
365 status = TXGBE_ERR_INVALID_MAC_ADDR;
366 /* Reject the zero address */
367 } else if (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 &&
368 mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0) {
369 status = TXGBE_ERR_INVALID_MAC_ADDR;
375 * txgbe_set_rar - Set Rx address register
376 * @hw: pointer to hardware structure
377 * @index: Receive address register to write
378 * @addr: Address to put into receive address register
379 * @vmdq: VMDq "set" or "pool" index
380 * @enable_addr: set flag that address is active
382 * Puts an ethernet address into a receive address register.
384 s32 txgbe_set_rar(struct txgbe_hw *hw, u32 index, u8 *addr, u32 vmdq,
387 u32 rar_low, rar_high;
388 u32 rar_entries = hw->mac.num_rar_entries;
390 DEBUGFUNC("txgbe_set_rar");
392 /* Make sure we are using a valid rar index range */
393 if (index >= rar_entries) {
394 DEBUGOUT("RAR index %d is out of range.\n", index);
395 return TXGBE_ERR_INVALID_ARGUMENT;
398 /* setup VMDq pool selection before this RAR gets enabled */
399 hw->mac.set_vmdq(hw, index, vmdq);
402 * HW expects these in little endian so we reverse the byte
403 * order from network order (big endian) to little endian
405 rar_low = TXGBE_ETHADDRL_AD0(addr[5]) |
406 TXGBE_ETHADDRL_AD1(addr[4]) |
407 TXGBE_ETHADDRL_AD2(addr[3]) |
408 TXGBE_ETHADDRL_AD3(addr[2]);
410 * Some parts put the VMDq setting in the extra RAH bits,
411 * so save everything except the lower 16 bits that hold part
412 * of the address and the address valid bit.
414 rar_high = rd32(hw, TXGBE_ETHADDRH);
415 rar_high &= ~TXGBE_ETHADDRH_AD_MASK;
416 rar_high |= (TXGBE_ETHADDRH_AD4(addr[1]) |
417 TXGBE_ETHADDRH_AD5(addr[0]));
419 rar_high &= ~TXGBE_ETHADDRH_VLD;
420 if (enable_addr != 0)
421 rar_high |= TXGBE_ETHADDRH_VLD;
423 wr32(hw, TXGBE_ETHADDRIDX, index);
424 wr32(hw, TXGBE_ETHADDRL, rar_low);
425 wr32(hw, TXGBE_ETHADDRH, rar_high);
431 * txgbe_clear_rar - Remove Rx address register
432 * @hw: pointer to hardware structure
433 * @index: Receive address register to write
435 * Clears an ethernet address from a receive address register.
437 s32 txgbe_clear_rar(struct txgbe_hw *hw, u32 index)
440 u32 rar_entries = hw->mac.num_rar_entries;
442 DEBUGFUNC("txgbe_clear_rar");
444 /* Make sure we are using a valid rar index range */
445 if (index >= rar_entries) {
446 DEBUGOUT("RAR index %d is out of range.\n", index);
447 return TXGBE_ERR_INVALID_ARGUMENT;
451 * Some parts put the VMDq setting in the extra RAH bits,
452 * so save everything except the lower 16 bits that hold part
453 * of the address and the address valid bit.
455 wr32(hw, TXGBE_ETHADDRIDX, index);
456 rar_high = rd32(hw, TXGBE_ETHADDRH);
457 rar_high &= ~(TXGBE_ETHADDRH_AD_MASK | TXGBE_ETHADDRH_VLD);
459 wr32(hw, TXGBE_ETHADDRL, 0);
460 wr32(hw, TXGBE_ETHADDRH, rar_high);
462 /* clear VMDq pool/queue selection for this RAR */
463 hw->mac.clear_vmdq(hw, index, BIT_MASK32);
469 * txgbe_init_rx_addrs - Initializes receive address filters.
470 * @hw: pointer to hardware structure
472 * Places the MAC address in receive address register 0 and clears the rest
473 * of the receive address registers. Clears the multicast table. Assumes
474 * the receiver is in reset when the routine is called.
476 s32 txgbe_init_rx_addrs(struct txgbe_hw *hw)
480 u32 rar_entries = hw->mac.num_rar_entries;
482 DEBUGFUNC("txgbe_init_rx_addrs");
485 * If the current mac address is valid, assume it is a software override
486 * to the permanent address.
487 * Otherwise, use the permanent address from the eeprom.
489 if (txgbe_validate_mac_addr(hw->mac.addr) ==
490 TXGBE_ERR_INVALID_MAC_ADDR) {
491 /* Get the MAC address from the RAR0 for later reference */
492 hw->mac.get_mac_addr(hw, hw->mac.addr);
494 DEBUGOUT(" Keeping Current RAR0 Addr =%.2X %.2X %.2X ",
495 hw->mac.addr[0], hw->mac.addr[1],
497 DEBUGOUT("%.2X %.2X %.2X\n", hw->mac.addr[3],
498 hw->mac.addr[4], hw->mac.addr[5]);
500 /* Setup the receive address. */
501 DEBUGOUT("Overriding MAC Address in RAR[0]\n");
502 DEBUGOUT(" New MAC Addr =%.2X %.2X %.2X ",
503 hw->mac.addr[0], hw->mac.addr[1],
505 DEBUGOUT("%.2X %.2X %.2X\n", hw->mac.addr[3],
506 hw->mac.addr[4], hw->mac.addr[5]);
508 hw->mac.set_rar(hw, 0, hw->mac.addr, 0, true);
511 /* clear VMDq pool/queue selection for RAR 0 */
512 hw->mac.clear_vmdq(hw, 0, BIT_MASK32);
514 hw->addr_ctrl.overflow_promisc = 0;
516 hw->addr_ctrl.rar_used_count = 1;
518 /* Zero out the other receive addresses. */
519 DEBUGOUT("Clearing RAR[1-%d]\n", rar_entries - 1);
520 for (i = 1; i < rar_entries; i++) {
521 wr32(hw, TXGBE_ETHADDRIDX, i);
522 wr32(hw, TXGBE_ETHADDRL, 0);
523 wr32(hw, TXGBE_ETHADDRH, 0);
527 hw->addr_ctrl.mta_in_use = 0;
528 psrctl = rd32(hw, TXGBE_PSRCTL);
529 psrctl &= ~(TXGBE_PSRCTL_ADHF12_MASK | TXGBE_PSRCTL_MCHFENA);
530 psrctl |= TXGBE_PSRCTL_ADHF12(hw->mac.mc_filter_type);
531 wr32(hw, TXGBE_PSRCTL, psrctl);
533 DEBUGOUT(" Clearing MTA\n");
534 for (i = 0; i < hw->mac.mcft_size; i++)
535 wr32(hw, TXGBE_MCADDRTBL(i), 0);
537 txgbe_init_uta_tables(hw);
543 * txgbe_mta_vector - Determines bit-vector in multicast table to set
544 * @hw: pointer to hardware structure
545 * @mc_addr: the multicast address
547 * Extracts the 12 bits, from a multicast address, to determine which
548 * bit-vector to set in the multicast table. The hardware uses 12 bits, from
549 * incoming rx multicast addresses, to determine the bit-vector to check in
550 * the MTA. Which of the 4 combination, of 12-bits, the hardware uses is set
551 * by the MO field of the PSRCTRL. The MO field is set during initialization
554 static s32 txgbe_mta_vector(struct txgbe_hw *hw, u8 *mc_addr)
558 DEBUGFUNC("txgbe_mta_vector");
560 switch (hw->mac.mc_filter_type) {
561 case 0: /* use bits [47:36] of the address */
562 vector = ((mc_addr[4] >> 4) | (((u16)mc_addr[5]) << 4));
564 case 1: /* use bits [46:35] of the address */
565 vector = ((mc_addr[4] >> 3) | (((u16)mc_addr[5]) << 5));
567 case 2: /* use bits [45:34] of the address */
568 vector = ((mc_addr[4] >> 2) | (((u16)mc_addr[5]) << 6));
570 case 3: /* use bits [43:32] of the address */
571 vector = ((mc_addr[4]) | (((u16)mc_addr[5]) << 8));
573 default: /* Invalid mc_filter_type */
574 DEBUGOUT("MC filter type param set incorrectly\n");
579 /* vector can only be 12-bits or boundary will be exceeded */
585 * txgbe_set_mta - Set bit-vector in multicast table
586 * @hw: pointer to hardware structure
587 * @mc_addr: Multicast address
589 * Sets the bit-vector in the multicast table.
591 void txgbe_set_mta(struct txgbe_hw *hw, u8 *mc_addr)
597 DEBUGFUNC("txgbe_set_mta");
599 hw->addr_ctrl.mta_in_use++;
601 vector = txgbe_mta_vector(hw, mc_addr);
602 DEBUGOUT(" bit-vector = 0x%03X\n", vector);
605 * The MTA is a register array of 128 32-bit registers. It is treated
606 * like an array of 4096 bits. We want to set bit
607 * BitArray[vector_value]. So we figure out what register the bit is
608 * in, read it, OR in the new bit, then write back the new value. The
609 * register is determined by the upper 7 bits of the vector value and
610 * the bit within that register are determined by the lower 5 bits of
613 vector_reg = (vector >> 5) & 0x7F;
614 vector_bit = vector & 0x1F;
615 hw->mac.mta_shadow[vector_reg] |= (1 << vector_bit);
619 * txgbe_update_mc_addr_list - Updates MAC list of multicast addresses
620 * @hw: pointer to hardware structure
621 * @mc_addr_list: the list of new multicast addresses
622 * @mc_addr_count: number of addresses
623 * @next: iterator function to walk the multicast address list
624 * @clear: flag, when set clears the table beforehand
626 * When the clear flag is set, the given list replaces any existing list.
627 * Hashes the given addresses into the multicast table.
629 s32 txgbe_update_mc_addr_list(struct txgbe_hw *hw, u8 *mc_addr_list,
630 u32 mc_addr_count, txgbe_mc_addr_itr next,
636 DEBUGFUNC("txgbe_update_mc_addr_list");
639 * Set the new number of MC addresses that we are being requested to
642 hw->addr_ctrl.num_mc_addrs = mc_addr_count;
643 hw->addr_ctrl.mta_in_use = 0;
645 /* Clear mta_shadow */
647 DEBUGOUT(" Clearing MTA\n");
648 memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow));
651 /* Update mta_shadow */
652 for (i = 0; i < mc_addr_count; i++) {
653 DEBUGOUT(" Adding the multicast addresses:\n");
654 txgbe_set_mta(hw, next(hw, &mc_addr_list, &vmdq));
658 for (i = 0; i < hw->mac.mcft_size; i++)
659 wr32a(hw, TXGBE_MCADDRTBL(0), i,
660 hw->mac.mta_shadow[i]);
662 if (hw->addr_ctrl.mta_in_use > 0) {
663 u32 psrctl = rd32(hw, TXGBE_PSRCTL);
664 psrctl &= ~(TXGBE_PSRCTL_ADHF12_MASK | TXGBE_PSRCTL_MCHFENA);
665 psrctl |= TXGBE_PSRCTL_MCHFENA |
666 TXGBE_PSRCTL_ADHF12(hw->mac.mc_filter_type);
667 wr32(hw, TXGBE_PSRCTL, psrctl);
670 DEBUGOUT("txgbe update mc addr list complete\n");
675 * txgbe_acquire_swfw_sync - Acquire SWFW semaphore
676 * @hw: pointer to hardware structure
677 * @mask: Mask to specify which semaphore to acquire
679 * Acquires the SWFW semaphore through the MNGSEM register for the specified
680 * function (CSR, PHY0, PHY1, EEPROM, Flash)
682 s32 txgbe_acquire_swfw_sync(struct txgbe_hw *hw, u32 mask)
685 u32 swmask = TXGBE_MNGSEM_SW(mask);
686 u32 fwmask = TXGBE_MNGSEM_FW(mask);
690 DEBUGFUNC("txgbe_acquire_swfw_sync");
692 for (i = 0; i < timeout; i++) {
694 * SW NVM semaphore bit is used for access to all
695 * SW_FW_SYNC bits (not just NVM)
697 if (txgbe_get_eeprom_semaphore(hw))
698 return TXGBE_ERR_SWFW_SYNC;
700 mngsem = rd32(hw, TXGBE_MNGSEM);
701 if (mngsem & (fwmask | swmask)) {
702 /* Resource is currently in use by FW or SW */
703 txgbe_release_eeprom_semaphore(hw);
707 wr32(hw, TXGBE_MNGSEM, mngsem);
708 txgbe_release_eeprom_semaphore(hw);
713 /* If time expired clear the bits holding the lock and retry */
714 if (mngsem & (fwmask | swmask))
715 txgbe_release_swfw_sync(hw, mngsem & (fwmask | swmask));
718 return TXGBE_ERR_SWFW_SYNC;
722 * txgbe_release_swfw_sync - Release SWFW semaphore
723 * @hw: pointer to hardware structure
724 * @mask: Mask to specify which semaphore to release
726 * Releases the SWFW semaphore through the MNGSEM register for the specified
727 * function (CSR, PHY0, PHY1, EEPROM, Flash)
729 void txgbe_release_swfw_sync(struct txgbe_hw *hw, u32 mask)
734 DEBUGFUNC("txgbe_release_swfw_sync");
736 txgbe_get_eeprom_semaphore(hw);
738 mngsem = rd32(hw, TXGBE_MNGSEM);
740 wr32(hw, TXGBE_MNGSEM, mngsem);
742 txgbe_release_eeprom_semaphore(hw);
746 * txgbe_disable_sec_rx_path - Stops the receive data path
747 * @hw: pointer to hardware structure
749 * Stops the receive data path and waits for the HW to internally empty
750 * the Rx security block
752 s32 txgbe_disable_sec_rx_path(struct txgbe_hw *hw)
754 #define TXGBE_MAX_SECRX_POLL 4000
759 DEBUGFUNC("txgbe_disable_sec_rx_path");
761 secrxreg = rd32(hw, TXGBE_SECRXCTL);
762 secrxreg |= TXGBE_SECRXCTL_XDSA;
763 wr32(hw, TXGBE_SECRXCTL, secrxreg);
764 for (i = 0; i < TXGBE_MAX_SECRX_POLL; i++) {
765 secrxreg = rd32(hw, TXGBE_SECRXSTAT);
766 if (!(secrxreg & TXGBE_SECRXSTAT_RDY))
767 /* Use interrupt-safe sleep just in case */
773 /* For informational purposes only */
774 if (i >= TXGBE_MAX_SECRX_POLL)
775 DEBUGOUT("Rx unit being enabled before security "
776 "path fully disabled. Continuing with init.\n");
782 * txgbe_enable_sec_rx_path - Enables the receive data path
783 * @hw: pointer to hardware structure
785 * Enables the receive data path.
787 s32 txgbe_enable_sec_rx_path(struct txgbe_hw *hw)
791 DEBUGFUNC("txgbe_enable_sec_rx_path");
793 secrxreg = rd32(hw, TXGBE_SECRXCTL);
794 secrxreg &= ~TXGBE_SECRXCTL_XDSA;
795 wr32(hw, TXGBE_SECRXCTL, secrxreg);
802 * txgbe_disable_sec_tx_path - Stops the transmit data path
803 * @hw: pointer to hardware structure
805 * Stops the transmit data path and waits for the HW to internally empty
806 * the Tx security block
808 int txgbe_disable_sec_tx_path(struct txgbe_hw *hw)
810 #define TXGBE_MAX_SECTX_POLL 40
815 sectxreg = rd32(hw, TXGBE_SECTXCTL);
816 sectxreg |= TXGBE_SECTXCTL_XDSA;
817 wr32(hw, TXGBE_SECTXCTL, sectxreg);
818 for (i = 0; i < TXGBE_MAX_SECTX_POLL; i++) {
819 sectxreg = rd32(hw, TXGBE_SECTXSTAT);
820 if (sectxreg & TXGBE_SECTXSTAT_RDY)
822 /* Use interrupt-safe sleep just in case */
826 /* For informational purposes only */
827 if (i >= TXGBE_MAX_SECTX_POLL)
828 PMD_DRV_LOG(DEBUG, "Tx unit being enabled before security "
829 "path fully disabled. Continuing with init.");
835 * txgbe_enable_sec_tx_path - Enables the transmit data path
836 * @hw: pointer to hardware structure
838 * Enables the transmit data path.
840 int txgbe_enable_sec_tx_path(struct txgbe_hw *hw)
844 sectxreg = rd32(hw, TXGBE_SECTXCTL);
845 sectxreg &= ~TXGBE_SECTXCTL_XDSA;
846 wr32(hw, TXGBE_SECTXCTL, sectxreg);
853 * txgbe_get_san_mac_addr_offset - Get SAN MAC address offset from the EEPROM
854 * @hw: pointer to hardware structure
855 * @san_mac_offset: SAN MAC address offset
857 * This function will read the EEPROM location for the SAN MAC address
858 * pointer, and returns the value at that location. This is used in both
859 * get and set mac_addr routines.
861 static s32 txgbe_get_san_mac_addr_offset(struct txgbe_hw *hw,
866 DEBUGFUNC("txgbe_get_san_mac_addr_offset");
869 * First read the EEPROM pointer to see if the MAC addresses are
872 err = hw->rom.readw_sw(hw, TXGBE_SAN_MAC_ADDR_PTR,
875 DEBUGOUT("eeprom at offset %d failed",
876 TXGBE_SAN_MAC_ADDR_PTR);
883 * txgbe_get_san_mac_addr - SAN MAC address retrieval from the EEPROM
884 * @hw: pointer to hardware structure
885 * @san_mac_addr: SAN MAC address
887 * Reads the SAN MAC address from the EEPROM, if it's available. This is
888 * per-port, so set_lan_id() must be called before reading the addresses.
889 * set_lan_id() is called by identify_sfp(), but this cannot be relied
890 * upon for non-SFP connections, so we must call it here.
892 s32 txgbe_get_san_mac_addr(struct txgbe_hw *hw, u8 *san_mac_addr)
894 u16 san_mac_data, san_mac_offset;
898 DEBUGFUNC("txgbe_get_san_mac_addr");
901 * First read the EEPROM pointer to see if the MAC addresses are
902 * available. If they're not, no point in calling set_lan_id() here.
904 err = txgbe_get_san_mac_addr_offset(hw, &san_mac_offset);
905 if (err || san_mac_offset == 0 || san_mac_offset == 0xFFFF)
906 goto san_mac_addr_out;
908 /* apply the port offset to the address offset */
909 (hw->bus.func) ? (san_mac_offset += TXGBE_SAN_MAC_ADDR_PORT1_OFFSET) :
910 (san_mac_offset += TXGBE_SAN_MAC_ADDR_PORT0_OFFSET);
911 for (i = 0; i < 3; i++) {
912 err = hw->rom.read16(hw, san_mac_offset,
915 DEBUGOUT("eeprom read at offset %d failed",
917 goto san_mac_addr_out;
919 san_mac_addr[i * 2] = (u8)(san_mac_data);
920 san_mac_addr[i * 2 + 1] = (u8)(san_mac_data >> 8);
927 * No addresses available in this EEPROM. It's not an
928 * error though, so just wipe the local address and return.
930 for (i = 0; i < 6; i++)
931 san_mac_addr[i] = 0xFF;
936 * txgbe_set_san_mac_addr - Write the SAN MAC address to the EEPROM
937 * @hw: pointer to hardware structure
938 * @san_mac_addr: SAN MAC address
940 * Write a SAN MAC address to the EEPROM.
942 s32 txgbe_set_san_mac_addr(struct txgbe_hw *hw, u8 *san_mac_addr)
945 u16 san_mac_data, san_mac_offset;
948 DEBUGFUNC("txgbe_set_san_mac_addr");
950 /* Look for SAN mac address pointer. If not defined, return */
951 err = txgbe_get_san_mac_addr_offset(hw, &san_mac_offset);
952 if (err || san_mac_offset == 0 || san_mac_offset == 0xFFFF)
953 return TXGBE_ERR_NO_SAN_ADDR_PTR;
955 /* Apply the port offset to the address offset */
956 (hw->bus.func) ? (san_mac_offset += TXGBE_SAN_MAC_ADDR_PORT1_OFFSET) :
957 (san_mac_offset += TXGBE_SAN_MAC_ADDR_PORT0_OFFSET);
959 for (i = 0; i < 3; i++) {
960 san_mac_data = (u16)((u16)(san_mac_addr[i * 2 + 1]) << 8);
961 san_mac_data |= (u16)(san_mac_addr[i * 2]);
962 hw->rom.write16(hw, san_mac_offset, san_mac_data);
970 * txgbe_init_uta_tables - Initialize the Unicast Table Array
971 * @hw: pointer to hardware structure
973 s32 txgbe_init_uta_tables(struct txgbe_hw *hw)
977 DEBUGFUNC("txgbe_init_uta_tables");
978 DEBUGOUT(" Clearing UTA\n");
980 for (i = 0; i < 128; i++)
981 wr32(hw, TXGBE_UCADDRTBL(i), 0);
987 * txgbe_clear_vfta - Clear VLAN filter table
988 * @hw: pointer to hardware structure
990 * Clears the VLAN filer table, and the VMDq index associated with the filter
992 s32 txgbe_clear_vfta(struct txgbe_hw *hw)
996 DEBUGFUNC("txgbe_clear_vfta");
998 for (offset = 0; offset < hw->mac.vft_size; offset++)
999 wr32(hw, TXGBE_VLANTBL(offset), 0);
1001 for (offset = 0; offset < TXGBE_NUM_POOL; offset++) {
1002 wr32(hw, TXGBE_PSRVLANIDX, offset);
1003 wr32(hw, TXGBE_PSRVLAN, 0);
1004 wr32(hw, TXGBE_PSRVLANPLM(0), 0);
1005 wr32(hw, TXGBE_PSRVLANPLM(1), 0);
1012 * txgbe_need_crosstalk_fix - Determine if we need to do cross talk fix
1013 * @hw: pointer to hardware structure
1015 * Contains the logic to identify if we need to verify link for the
1018 static bool txgbe_need_crosstalk_fix(struct txgbe_hw *hw)
1020 /* Does FW say we need the fix */
1021 if (!hw->need_crosstalk_fix)
1024 /* Only consider SFP+ PHYs i.e. media type fiber */
1025 switch (hw->phy.media_type) {
1026 case txgbe_media_type_fiber:
1027 case txgbe_media_type_fiber_qsfp:
1037 * txgbe_check_mac_link - Determine link and speed status
1038 * @hw: pointer to hardware structure
1039 * @speed: pointer to link speed
1040 * @link_up: true when link is up
1041 * @link_up_wait_to_complete: bool used to wait for link up or not
1043 * Reads the links register to determine if link is up and the current speed
1045 s32 txgbe_check_mac_link(struct txgbe_hw *hw, u32 *speed,
1046 bool *link_up, bool link_up_wait_to_complete)
1048 u32 links_reg, links_orig;
1051 DEBUGFUNC("txgbe_check_mac_link");
1053 /* If Crosstalk fix enabled do the sanity check of making sure
1054 * the SFP+ cage is full.
1056 if (txgbe_need_crosstalk_fix(hw)) {
1059 switch (hw->mac.type) {
1060 case txgbe_mac_raptor:
1061 sfp_cage_full = !rd32m(hw, TXGBE_GPIODATA,
1065 /* sanity check - No SFP+ devices here */
1066 sfp_cage_full = false;
1070 if (!sfp_cage_full) {
1072 *speed = TXGBE_LINK_SPEED_UNKNOWN;
1077 /* clear the old state */
1078 links_orig = rd32(hw, TXGBE_PORTSTAT);
1080 links_reg = rd32(hw, TXGBE_PORTSTAT);
1082 if (links_orig != links_reg) {
1083 DEBUGOUT("LINKS changed from %08X to %08X\n",
1084 links_orig, links_reg);
1087 if (link_up_wait_to_complete) {
1088 for (i = 0; i < hw->mac.max_link_up_time; i++) {
1089 if (!(links_reg & TXGBE_PORTSTAT_UP)) {
1096 links_reg = rd32(hw, TXGBE_PORTSTAT);
1099 if (links_reg & TXGBE_PORTSTAT_UP)
1105 switch (links_reg & TXGBE_PORTSTAT_BW_MASK) {
1106 case TXGBE_PORTSTAT_BW_10G:
1107 *speed = TXGBE_LINK_SPEED_10GB_FULL;
1109 case TXGBE_PORTSTAT_BW_1G:
1110 *speed = TXGBE_LINK_SPEED_1GB_FULL;
1112 case TXGBE_PORTSTAT_BW_100M:
1113 *speed = TXGBE_LINK_SPEED_100M_FULL;
1116 *speed = TXGBE_LINK_SPEED_UNKNOWN;
1123 * txgbe_get_wwn_prefix - Get alternative WWNN/WWPN prefix from
1125 * @hw: pointer to hardware structure
1126 * @wwnn_prefix: the alternative WWNN prefix
1127 * @wwpn_prefix: the alternative WWPN prefix
1129 * This function will read the EEPROM from the alternative SAN MAC address
1130 * block to check the support for the alternative WWNN/WWPN prefix support.
1132 s32 txgbe_get_wwn_prefix(struct txgbe_hw *hw, u16 *wwnn_prefix,
1136 u16 alt_san_mac_blk_offset;
1138 DEBUGFUNC("txgbe_get_wwn_prefix");
1140 /* clear output first */
1141 *wwnn_prefix = 0xFFFF;
1142 *wwpn_prefix = 0xFFFF;
1144 /* check if alternative SAN MAC is supported */
1145 offset = TXGBE_ALT_SAN_MAC_ADDR_BLK_PTR;
1146 if (hw->rom.readw_sw(hw, offset, &alt_san_mac_blk_offset))
1147 goto wwn_prefix_err;
1149 if (alt_san_mac_blk_offset == 0 || alt_san_mac_blk_offset == 0xFFFF)
1150 goto wwn_prefix_out;
1152 /* check capability in alternative san mac address block */
1153 offset = alt_san_mac_blk_offset + TXGBE_ALT_SAN_MAC_ADDR_CAPS_OFFSET;
1154 if (hw->rom.read16(hw, offset, &caps))
1155 goto wwn_prefix_err;
1156 if (!(caps & TXGBE_ALT_SAN_MAC_ADDR_CAPS_ALTWWN))
1157 goto wwn_prefix_out;
1159 /* get the corresponding prefix for WWNN/WWPN */
1160 offset = alt_san_mac_blk_offset + TXGBE_ALT_SAN_MAC_ADDR_WWNN_OFFSET;
1161 if (hw->rom.read16(hw, offset, wwnn_prefix))
1162 DEBUGOUT("eeprom read at offset %d failed", offset);
1164 offset = alt_san_mac_blk_offset + TXGBE_ALT_SAN_MAC_ADDR_WWPN_OFFSET;
1165 if (hw->rom.read16(hw, offset, wwpn_prefix))
1166 goto wwn_prefix_err;
1172 DEBUGOUT("eeprom read at offset %d failed", offset);
1177 * txgbe_get_device_caps - Get additional device capabilities
1178 * @hw: pointer to hardware structure
1179 * @device_caps: the EEPROM word with the extra device capabilities
1181 * This function will read the EEPROM location for the device capabilities,
1182 * and return the word through device_caps.
1184 s32 txgbe_get_device_caps(struct txgbe_hw *hw, u16 *device_caps)
1186 DEBUGFUNC("txgbe_get_device_caps");
1188 hw->rom.readw_sw(hw, TXGBE_DEVICE_CAPS, device_caps);
1194 * txgbe_clear_tx_pending - Clear pending TX work from the PCIe fifo
1195 * @hw: pointer to the hardware structure
1197 * The MACs can experience issues if TX work is still pending
1198 * when a reset occurs. This function prevents this by flushing the PCIe
1199 * buffers on the system.
1201 void txgbe_clear_tx_pending(struct txgbe_hw *hw)
1203 u32 hlreg0, i, poll;
1206 * If double reset is not requested then all transactions should
1207 * already be clear and as such there is no work to do
1209 if (!(hw->mac.flags & TXGBE_FLAGS_DOUBLE_RESET_REQUIRED))
1212 hlreg0 = rd32(hw, TXGBE_PSRCTL);
1213 wr32(hw, TXGBE_PSRCTL, hlreg0 | TXGBE_PSRCTL_LBENA);
1215 /* Wait for a last completion before clearing buffers */
1220 * Before proceeding, make sure that the PCIe block does not have
1221 * transactions pending.
1223 poll = (800 * 11) / 10;
1224 for (i = 0; i < poll; i++)
1227 /* Flush all writes and allow 20usec for all transactions to clear */
1231 /* restore previous register values */
1232 wr32(hw, TXGBE_PSRCTL, hlreg0);
1236 * txgbe_get_thermal_sensor_data - Gathers thermal sensor data
1237 * @hw: pointer to hardware structure
1239 * Returns the thermal sensor data structure
1241 s32 txgbe_get_thermal_sensor_data(struct txgbe_hw *hw)
1243 struct txgbe_thermal_sensor_data *data = &hw->mac.thermal_sensor_data;
1247 DEBUGFUNC("txgbe_get_thermal_sensor_data");
1249 /* Only support thermal sensors attached to physical port 0 */
1250 if (hw->bus.lan_id != 0)
1251 return TXGBE_NOT_IMPLEMENTED;
1253 ts_stat = rd32(hw, TXGBE_TSSTAT);
1254 tsv = (s64)TXGBE_TSSTAT_DATA(ts_stat);
1255 tsv = tsv > 1200 ? tsv : 1200;
1256 tsv = -(48380 << 8) / 1000
1257 + tsv * (31020 << 8) / 100000
1258 - tsv * tsv * (18201 << 8) / 100000000
1259 + tsv * tsv * tsv * (81542 << 8) / 1000000000000
1260 - tsv * tsv * tsv * tsv * (16743 << 8) / 1000000000000000;
1263 data->sensor[0].temp = (s16)tsv;
1269 * txgbe_init_thermal_sensor_thresh - Inits thermal sensor thresholds
1270 * @hw: pointer to hardware structure
1272 * Inits the thermal sensor thresholds according to the NVM map
1273 * and save off the threshold and location values into mac.thermal_sensor_data
1275 s32 txgbe_init_thermal_sensor_thresh(struct txgbe_hw *hw)
1277 struct txgbe_thermal_sensor_data *data = &hw->mac.thermal_sensor_data;
1279 DEBUGFUNC("txgbe_init_thermal_sensor_thresh");
1281 memset(data, 0, sizeof(struct txgbe_thermal_sensor_data));
1283 if (hw->bus.lan_id != 0)
1284 return TXGBE_NOT_IMPLEMENTED;
1286 wr32(hw, TXGBE_TSCTRL, TXGBE_TSCTRL_EVALMD);
1287 wr32(hw, TXGBE_TSINTR,
1288 TXGBE_TSINTR_AEN | TXGBE_TSINTR_DEN);
1289 wr32(hw, TXGBE_TSEN, TXGBE_TSEN_ENA);
1292 data->sensor[0].alarm_thresh = 100;
1293 wr32(hw, TXGBE_TSATHRE, 677);
1294 data->sensor[0].dalarm_thresh = 90;
1295 wr32(hw, TXGBE_TSDTHRE, 614);
1300 void txgbe_disable_rx(struct txgbe_hw *hw)
1304 pfdtxgswc = rd32(hw, TXGBE_PSRCTL);
1305 if (pfdtxgswc & TXGBE_PSRCTL_LBENA) {
1306 pfdtxgswc &= ~TXGBE_PSRCTL_LBENA;
1307 wr32(hw, TXGBE_PSRCTL, pfdtxgswc);
1308 hw->mac.set_lben = true;
1310 hw->mac.set_lben = false;
1313 wr32m(hw, TXGBE_PBRXCTL, TXGBE_PBRXCTL_ENA, 0);
1314 wr32m(hw, TXGBE_MACRXCFG, TXGBE_MACRXCFG_ENA, 0);
1317 void txgbe_enable_rx(struct txgbe_hw *hw)
1321 wr32m(hw, TXGBE_MACRXCFG, TXGBE_MACRXCFG_ENA, TXGBE_MACRXCFG_ENA);
1322 wr32m(hw, TXGBE_PBRXCTL, TXGBE_PBRXCTL_ENA, TXGBE_PBRXCTL_ENA);
1324 if (hw->mac.set_lben) {
1325 pfdtxgswc = rd32(hw, TXGBE_PSRCTL);
1326 pfdtxgswc |= TXGBE_PSRCTL_LBENA;
1327 wr32(hw, TXGBE_PSRCTL, pfdtxgswc);
1328 hw->mac.set_lben = false;
1333 * txgbe_setup_mac_link_multispeed_fiber - Set MAC link speed
1334 * @hw: pointer to hardware structure
1335 * @speed: new link speed
1336 * @autoneg_wait_to_complete: true when waiting for completion is needed
1338 * Set the link speed in the MAC and/or PHY register and restarts link.
1340 s32 txgbe_setup_mac_link_multispeed_fiber(struct txgbe_hw *hw,
1342 bool autoneg_wait_to_complete)
1344 u32 link_speed = TXGBE_LINK_SPEED_UNKNOWN;
1345 u32 highest_link_speed = TXGBE_LINK_SPEED_UNKNOWN;
1349 bool autoneg, link_up = false;
1351 DEBUGFUNC("txgbe_setup_mac_link_multispeed_fiber");
1353 /* Mask off requested but non-supported speeds */
1354 status = hw->mac.get_link_capabilities(hw, &link_speed, &autoneg);
1358 speed &= link_speed;
1360 /* Try each speed one by one, highest priority first. We do this in
1361 * software because 10Gb fiber doesn't support speed autonegotiation.
1363 if (speed & TXGBE_LINK_SPEED_10GB_FULL) {
1365 highest_link_speed = TXGBE_LINK_SPEED_10GB_FULL;
1367 /* Set the module link speed */
1368 switch (hw->phy.media_type) {
1369 case txgbe_media_type_fiber:
1370 hw->mac.set_rate_select_speed(hw,
1371 TXGBE_LINK_SPEED_10GB_FULL);
1373 case txgbe_media_type_fiber_qsfp:
1374 /* QSFP module automatically detects MAC link speed */
1377 DEBUGOUT("Unexpected media type.\n");
1381 /* Allow module to change analog characteristics (1G->10G) */
1384 status = hw->mac.setup_mac_link(hw,
1385 TXGBE_LINK_SPEED_10GB_FULL,
1386 autoneg_wait_to_complete);
1390 /* Flap the Tx laser if it has not already been done */
1391 hw->mac.flap_tx_laser(hw);
1393 /* Wait for the controller to acquire link. Per IEEE 802.3ap,
1394 * Section 73.10.2, we may have to wait up to 500ms if KR is
1395 * attempted. uses the same timing for 10g SFI.
1397 for (i = 0; i < 5; i++) {
1398 /* Wait for the link partner to also set speed */
1401 /* If we have link, just jump out */
1402 status = hw->mac.check_link(hw, &link_speed,
1412 if (speed & TXGBE_LINK_SPEED_1GB_FULL) {
1414 if (highest_link_speed == TXGBE_LINK_SPEED_UNKNOWN)
1415 highest_link_speed = TXGBE_LINK_SPEED_1GB_FULL;
1417 /* Set the module link speed */
1418 switch (hw->phy.media_type) {
1419 case txgbe_media_type_fiber:
1420 hw->mac.set_rate_select_speed(hw,
1421 TXGBE_LINK_SPEED_1GB_FULL);
1423 case txgbe_media_type_fiber_qsfp:
1424 /* QSFP module automatically detects link speed */
1427 DEBUGOUT("Unexpected media type.\n");
1431 /* Allow module to change analog characteristics (10G->1G) */
1434 status = hw->mac.setup_mac_link(hw,
1435 TXGBE_LINK_SPEED_1GB_FULL,
1436 autoneg_wait_to_complete);
1440 /* Flap the Tx laser if it has not already been done */
1441 hw->mac.flap_tx_laser(hw);
1443 /* Wait for the link partner to also set speed */
1446 /* If we have link, just jump out */
1447 status = hw->mac.check_link(hw, &link_speed, &link_up, false);
1455 /* We didn't get link. Configure back to the highest speed we tried,
1456 * (if there was more than one). We call ourselves back with just the
1457 * single highest speed that the user requested.
1460 status = txgbe_setup_mac_link_multispeed_fiber(hw,
1462 autoneg_wait_to_complete);
1465 /* Set autoneg_advertised value based on input link speed */
1466 hw->phy.autoneg_advertised = 0;
1468 if (speed & TXGBE_LINK_SPEED_10GB_FULL)
1469 hw->phy.autoneg_advertised |= TXGBE_LINK_SPEED_10GB_FULL;
1471 if (speed & TXGBE_LINK_SPEED_1GB_FULL)
1472 hw->phy.autoneg_advertised |= TXGBE_LINK_SPEED_1GB_FULL;
1478 * txgbe_init_shared_code - Initialize the shared code
1479 * @hw: pointer to hardware structure
1481 * This will assign function pointers and assign the MAC type and PHY code.
1482 * Does not touch the hardware. This function must be called prior to any
1483 * other function in the shared code. The txgbe_hw structure should be
1484 * memset to 0 prior to calling this function. The following fields in
1485 * hw structure should be filled in prior to calling this function:
1486 * hw_addr, back, device_id, vendor_id, subsystem_device_id,
1487 * subsystem_vendor_id, and revision_id
1489 s32 txgbe_init_shared_code(struct txgbe_hw *hw)
1493 DEBUGFUNC("txgbe_init_shared_code");
1498 txgbe_set_mac_type(hw);
1500 txgbe_init_ops_dummy(hw);
1501 switch (hw->mac.type) {
1502 case txgbe_mac_raptor:
1503 status = txgbe_init_ops_pf(hw);
1506 status = TXGBE_ERR_DEVICE_NOT_SUPPORTED;
1509 hw->mac.max_link_up_time = TXGBE_LINK_UP_TIME;
1511 hw->bus.set_lan_id(hw);
1517 * txgbe_set_mac_type - Sets MAC type
1518 * @hw: pointer to the HW structure
1520 * This function sets the mac type of the adapter based on the
1521 * vendor ID and device ID stored in the hw structure.
1523 s32 txgbe_set_mac_type(struct txgbe_hw *hw)
1527 DEBUGFUNC("txgbe_set_mac_type");
1529 if (hw->vendor_id != PCI_VENDOR_ID_WANGXUN) {
1530 DEBUGOUT("Unsupported vendor id: %x", hw->vendor_id);
1531 return TXGBE_ERR_DEVICE_NOT_SUPPORTED;
1534 switch (hw->device_id) {
1535 case TXGBE_DEV_ID_RAPTOR_KR_KX_KX4:
1536 hw->phy.media_type = txgbe_media_type_backplane;
1537 hw->mac.type = txgbe_mac_raptor;
1539 case TXGBE_DEV_ID_RAPTOR_XAUI:
1540 case TXGBE_DEV_ID_RAPTOR_SGMII:
1541 hw->phy.media_type = txgbe_media_type_copper;
1542 hw->mac.type = txgbe_mac_raptor;
1544 case TXGBE_DEV_ID_RAPTOR_SFP:
1545 case TXGBE_DEV_ID_WX1820_SFP:
1546 hw->phy.media_type = txgbe_media_type_fiber;
1547 hw->mac.type = txgbe_mac_raptor;
1549 case TXGBE_DEV_ID_RAPTOR_QSFP:
1550 hw->phy.media_type = txgbe_media_type_fiber_qsfp;
1551 hw->mac.type = txgbe_mac_raptor;
1553 case TXGBE_DEV_ID_RAPTOR_VF:
1554 case TXGBE_DEV_ID_RAPTOR_VF_HV:
1555 hw->phy.media_type = txgbe_media_type_virtual;
1556 hw->mac.type = txgbe_mac_raptor_vf;
1559 err = TXGBE_ERR_DEVICE_NOT_SUPPORTED;
1560 DEBUGOUT("Unsupported device id: %x", hw->device_id);
1564 DEBUGOUT("found mac: %d media: %d, returns: %d\n",
1565 hw->mac.type, hw->phy.media_type, err);
1569 void txgbe_init_mac_link_ops(struct txgbe_hw *hw)
1571 struct txgbe_mac_info *mac = &hw->mac;
1573 DEBUGFUNC("txgbe_init_mac_link_ops");
1576 * enable the laser control functions for SFP+ fiber
1577 * and MNG not enabled
1579 if (hw->phy.media_type == txgbe_media_type_fiber &&
1580 !txgbe_mng_enabled(hw)) {
1581 mac->disable_tx_laser =
1582 txgbe_disable_tx_laser_multispeed_fiber;
1583 mac->enable_tx_laser =
1584 txgbe_enable_tx_laser_multispeed_fiber;
1585 mac->flap_tx_laser =
1586 txgbe_flap_tx_laser_multispeed_fiber;
1589 if ((hw->phy.media_type == txgbe_media_type_fiber ||
1590 hw->phy.media_type == txgbe_media_type_fiber_qsfp) &&
1591 hw->phy.multispeed_fiber) {
1592 /* Set up dual speed SFP+ support */
1593 mac->setup_link = txgbe_setup_mac_link_multispeed_fiber;
1594 mac->setup_mac_link = txgbe_setup_mac_link;
1595 mac->set_rate_select_speed = txgbe_set_hard_rate_select_speed;
1596 } else if ((hw->phy.media_type == txgbe_media_type_backplane) &&
1597 (hw->phy.smart_speed == txgbe_smart_speed_auto ||
1598 hw->phy.smart_speed == txgbe_smart_speed_on) &&
1599 !txgbe_verify_lesm_fw_enabled_raptor(hw)) {
1600 mac->setup_link = txgbe_setup_mac_link_smartspeed;
1602 mac->setup_link = txgbe_setup_mac_link;
1607 * txgbe_init_phy_raptor - PHY/SFP specific init
1608 * @hw: pointer to hardware structure
1610 * Initialize any function pointers that were not able to be
1611 * set during init_shared_code because the PHY/SFP type was
1612 * not known. Perform the SFP init if necessary.
1615 s32 txgbe_init_phy_raptor(struct txgbe_hw *hw)
1617 struct txgbe_mac_info *mac = &hw->mac;
1618 struct txgbe_phy_info *phy = &hw->phy;
1621 DEBUGFUNC("txgbe_init_phy_raptor");
1623 if (hw->device_id == TXGBE_DEV_ID_RAPTOR_QSFP) {
1624 /* Store flag indicating I2C bus access control unit. */
1625 hw->phy.qsfp_shared_i2c_bus = TRUE;
1627 /* Initialize access to QSFP+ I2C bus */
1631 /* Identify the PHY or SFP module */
1632 err = phy->identify(hw);
1633 if (err == TXGBE_ERR_SFP_NOT_SUPPORTED)
1634 goto init_phy_ops_out;
1636 /* Setup function pointers based on detected SFP module and speeds */
1637 txgbe_init_mac_link_ops(hw);
1639 /* If copper media, overwrite with copper function pointers */
1640 if (phy->media_type == txgbe_media_type_copper) {
1641 mac->setup_link = txgbe_setup_copper_link_raptor;
1642 mac->get_link_capabilities =
1643 txgbe_get_copper_link_capabilities;
1646 /* Set necessary function pointers based on PHY type */
1647 switch (hw->phy.type) {
1649 phy->setup_link = txgbe_setup_phy_link_tnx;
1650 phy->check_link = txgbe_check_phy_link_tnx;
1660 s32 txgbe_setup_sfp_modules(struct txgbe_hw *hw)
1664 DEBUGFUNC("txgbe_setup_sfp_modules");
1666 if (hw->phy.sfp_type == txgbe_sfp_type_unknown)
1669 txgbe_init_mac_link_ops(hw);
1671 /* PHY config will finish before releasing the semaphore */
1672 err = hw->mac.acquire_swfw_sync(hw, TXGBE_MNGSEM_SWPHY);
1674 return TXGBE_ERR_SWFW_SYNC;
1676 /* Release the semaphore */
1677 hw->mac.release_swfw_sync(hw, TXGBE_MNGSEM_SWPHY);
1679 /* Delay obtaining semaphore again to allow FW access
1680 * prot_autoc_write uses the semaphore too.
1682 msec_delay(hw->rom.semaphore_delay);
1685 DEBUGOUT("sfp module setup not complete\n");
1686 return TXGBE_ERR_SFP_SETUP_NOT_COMPLETE;
1693 * txgbe_init_ops_pf - Inits func ptrs and MAC type
1694 * @hw: pointer to hardware structure
1696 * Initialize the function pointers and assign the MAC type.
1697 * Does not touch the hardware.
1699 s32 txgbe_init_ops_pf(struct txgbe_hw *hw)
1701 struct txgbe_bus_info *bus = &hw->bus;
1702 struct txgbe_mac_info *mac = &hw->mac;
1703 struct txgbe_phy_info *phy = &hw->phy;
1704 struct txgbe_rom_info *rom = &hw->rom;
1705 struct txgbe_mbx_info *mbx = &hw->mbx;
1707 DEBUGFUNC("txgbe_init_ops_pf");
1710 bus->set_lan_id = txgbe_set_lan_id_multi_port;
1713 phy->get_media_type = txgbe_get_media_type_raptor;
1714 phy->identify = txgbe_identify_phy;
1715 phy->init = txgbe_init_phy_raptor;
1716 phy->read_reg = txgbe_read_phy_reg;
1717 phy->write_reg = txgbe_write_phy_reg;
1718 phy->read_reg_mdi = txgbe_read_phy_reg_mdi;
1719 phy->write_reg_mdi = txgbe_write_phy_reg_mdi;
1720 phy->setup_link = txgbe_setup_phy_link;
1721 phy->setup_link_speed = txgbe_setup_phy_link_speed;
1722 phy->read_i2c_byte = txgbe_read_i2c_byte;
1723 phy->write_i2c_byte = txgbe_write_i2c_byte;
1724 phy->read_i2c_eeprom = txgbe_read_i2c_eeprom;
1725 phy->write_i2c_eeprom = txgbe_write_i2c_eeprom;
1726 phy->reset = txgbe_reset_phy;
1729 mac->init_hw = txgbe_init_hw;
1730 mac->start_hw = txgbe_start_hw_raptor;
1731 mac->clear_hw_cntrs = txgbe_clear_hw_cntrs;
1732 mac->enable_rx_dma = txgbe_enable_rx_dma_raptor;
1733 mac->get_mac_addr = txgbe_get_mac_addr;
1734 mac->stop_hw = txgbe_stop_hw;
1735 mac->acquire_swfw_sync = txgbe_acquire_swfw_sync;
1736 mac->release_swfw_sync = txgbe_release_swfw_sync;
1737 mac->reset_hw = txgbe_reset_hw;
1739 mac->disable_sec_rx_path = txgbe_disable_sec_rx_path;
1740 mac->enable_sec_rx_path = txgbe_enable_sec_rx_path;
1741 mac->disable_sec_tx_path = txgbe_disable_sec_tx_path;
1742 mac->enable_sec_tx_path = txgbe_enable_sec_tx_path;
1743 mac->get_san_mac_addr = txgbe_get_san_mac_addr;
1744 mac->set_san_mac_addr = txgbe_set_san_mac_addr;
1745 mac->get_device_caps = txgbe_get_device_caps;
1746 mac->get_wwn_prefix = txgbe_get_wwn_prefix;
1747 mac->autoc_read = txgbe_autoc_read;
1748 mac->autoc_write = txgbe_autoc_write;
1750 mac->set_rar = txgbe_set_rar;
1751 mac->clear_rar = txgbe_clear_rar;
1752 mac->init_rx_addrs = txgbe_init_rx_addrs;
1753 mac->enable_rx = txgbe_enable_rx;
1754 mac->disable_rx = txgbe_disable_rx;
1755 mac->clear_vfta = txgbe_clear_vfta;
1756 mac->init_uta_tables = txgbe_init_uta_tables;
1757 mac->setup_sfp = txgbe_setup_sfp_modules;
1759 mac->get_link_capabilities = txgbe_get_link_capabilities_raptor;
1760 mac->check_link = txgbe_check_mac_link;
1762 /* Manageability interface */
1763 mac->set_fw_drv_ver = txgbe_hic_set_drv_ver;
1764 mac->get_thermal_sensor_data = txgbe_get_thermal_sensor_data;
1765 mac->init_thermal_sensor_thresh = txgbe_init_thermal_sensor_thresh;
1767 mbx->init_params = txgbe_init_mbx_params_pf;
1770 rom->init_params = txgbe_init_eeprom_params;
1771 rom->read16 = txgbe_ee_read16;
1772 rom->readw_buffer = txgbe_ee_readw_buffer;
1773 rom->readw_sw = txgbe_ee_readw_sw;
1774 rom->read32 = txgbe_ee_read32;
1775 rom->write16 = txgbe_ee_write16;
1776 rom->writew_buffer = txgbe_ee_writew_buffer;
1777 rom->writew_sw = txgbe_ee_writew_sw;
1778 rom->write32 = txgbe_ee_write32;
1779 rom->validate_checksum = txgbe_validate_eeprom_checksum;
1780 rom->update_checksum = txgbe_update_eeprom_checksum;
1781 rom->calc_checksum = txgbe_calc_eeprom_checksum;
1783 mac->mcft_size = TXGBE_RAPTOR_MC_TBL_SIZE;
1784 mac->vft_size = TXGBE_RAPTOR_VFT_TBL_SIZE;
1785 mac->num_rar_entries = TXGBE_RAPTOR_RAR_ENTRIES;
1786 mac->max_rx_queues = TXGBE_RAPTOR_MAX_RX_QUEUES;
1787 mac->max_tx_queues = TXGBE_RAPTOR_MAX_TX_QUEUES;
1793 * txgbe_get_link_capabilities_raptor - Determines link capabilities
1794 * @hw: pointer to hardware structure
1795 * @speed: pointer to link speed
1796 * @autoneg: true when autoneg or autotry is enabled
1798 * Determines the link capabilities by reading the AUTOC register.
1800 s32 txgbe_get_link_capabilities_raptor(struct txgbe_hw *hw,
1807 DEBUGFUNC("txgbe_get_link_capabilities_raptor");
1809 /* Check if 1G SFP module. */
1810 if (hw->phy.sfp_type == txgbe_sfp_type_1g_cu_core0 ||
1811 hw->phy.sfp_type == txgbe_sfp_type_1g_cu_core1 ||
1812 hw->phy.sfp_type == txgbe_sfp_type_1g_lx_core0 ||
1813 hw->phy.sfp_type == txgbe_sfp_type_1g_lx_core1 ||
1814 hw->phy.sfp_type == txgbe_sfp_type_1g_sx_core0 ||
1815 hw->phy.sfp_type == txgbe_sfp_type_1g_sx_core1) {
1816 *speed = TXGBE_LINK_SPEED_1GB_FULL;
1822 * Determine link capabilities based on the stored value of AUTOC,
1823 * which represents EEPROM defaults. If AUTOC value has not
1824 * been stored, use the current register values.
1826 if (hw->mac.orig_link_settings_stored)
1827 autoc = hw->mac.orig_autoc;
1829 autoc = hw->mac.autoc_read(hw);
1831 switch (autoc & TXGBE_AUTOC_LMS_MASK) {
1832 case TXGBE_AUTOC_LMS_1G_LINK_NO_AN:
1833 *speed = TXGBE_LINK_SPEED_1GB_FULL;
1837 case TXGBE_AUTOC_LMS_10G_LINK_NO_AN:
1838 *speed = TXGBE_LINK_SPEED_10GB_FULL;
1842 case TXGBE_AUTOC_LMS_1G_AN:
1843 *speed = TXGBE_LINK_SPEED_1GB_FULL;
1847 case TXGBE_AUTOC_LMS_10G:
1848 *speed = TXGBE_LINK_SPEED_10GB_FULL;
1852 case TXGBE_AUTOC_LMS_KX4_KX_KR:
1853 case TXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN:
1854 *speed = TXGBE_LINK_SPEED_UNKNOWN;
1855 if (autoc & TXGBE_AUTOC_KR_SUPP)
1856 *speed |= TXGBE_LINK_SPEED_10GB_FULL;
1857 if (autoc & TXGBE_AUTOC_KX4_SUPP)
1858 *speed |= TXGBE_LINK_SPEED_10GB_FULL;
1859 if (autoc & TXGBE_AUTOC_KX_SUPP)
1860 *speed |= TXGBE_LINK_SPEED_1GB_FULL;
1864 case TXGBE_AUTOC_LMS_KX4_KX_KR_SGMII:
1865 *speed = TXGBE_LINK_SPEED_100M_FULL;
1866 if (autoc & TXGBE_AUTOC_KR_SUPP)
1867 *speed |= TXGBE_LINK_SPEED_10GB_FULL;
1868 if (autoc & TXGBE_AUTOC_KX4_SUPP)
1869 *speed |= TXGBE_LINK_SPEED_10GB_FULL;
1870 if (autoc & TXGBE_AUTOC_KX_SUPP)
1871 *speed |= TXGBE_LINK_SPEED_1GB_FULL;
1875 case TXGBE_AUTOC_LMS_SGMII_1G_100M:
1876 *speed = TXGBE_LINK_SPEED_1GB_FULL |
1877 TXGBE_LINK_SPEED_100M_FULL |
1878 TXGBE_LINK_SPEED_10M_FULL;
1883 return TXGBE_ERR_LINK_SETUP;
1886 if (hw->phy.multispeed_fiber) {
1887 *speed |= TXGBE_LINK_SPEED_10GB_FULL |
1888 TXGBE_LINK_SPEED_1GB_FULL;
1890 /* QSFP must not enable full auto-negotiation
1891 * Limited autoneg is enabled at 1G
1893 if (hw->phy.media_type == txgbe_media_type_fiber_qsfp)
1903 * txgbe_get_media_type_raptor - Get media type
1904 * @hw: pointer to hardware structure
1906 * Returns the media type (fiber, copper, backplane)
1908 u32 txgbe_get_media_type_raptor(struct txgbe_hw *hw)
1912 DEBUGFUNC("txgbe_get_media_type_raptor");
1914 /* Detect if there is a copper PHY attached. */
1915 switch (hw->phy.type) {
1916 case txgbe_phy_cu_unknown:
1918 media_type = txgbe_media_type_copper;
1924 switch (hw->device_id) {
1925 case TXGBE_DEV_ID_RAPTOR_KR_KX_KX4:
1926 /* Default device ID is mezzanine card KX/KX4 */
1927 media_type = txgbe_media_type_backplane;
1929 case TXGBE_DEV_ID_RAPTOR_SFP:
1930 case TXGBE_DEV_ID_WX1820_SFP:
1931 media_type = txgbe_media_type_fiber;
1933 case TXGBE_DEV_ID_RAPTOR_QSFP:
1934 media_type = txgbe_media_type_fiber_qsfp;
1936 case TXGBE_DEV_ID_RAPTOR_XAUI:
1937 case TXGBE_DEV_ID_RAPTOR_SGMII:
1938 media_type = txgbe_media_type_copper;
1941 media_type = txgbe_media_type_unknown;
1949 * txgbe_start_mac_link_raptor - Setup MAC link settings
1950 * @hw: pointer to hardware structure
1951 * @autoneg_wait_to_complete: true when waiting for completion is needed
1953 * Configures link settings based on values in the txgbe_hw struct.
1954 * Restarts the link. Performs autonegotiation if needed.
1956 s32 txgbe_start_mac_link_raptor(struct txgbe_hw *hw,
1957 bool autoneg_wait_to_complete)
1960 bool got_lock = false;
1962 DEBUGFUNC("txgbe_start_mac_link_raptor");
1964 UNREFERENCED_PARAMETER(autoneg_wait_to_complete);
1966 /* reset_pipeline requires us to hold this lock as it writes to
1969 if (txgbe_verify_lesm_fw_enabled_raptor(hw)) {
1970 status = hw->mac.acquire_swfw_sync(hw, TXGBE_MNGSEM_SWPHY);
1978 txgbe_reset_pipeline_raptor(hw);
1981 hw->mac.release_swfw_sync(hw, TXGBE_MNGSEM_SWPHY);
1983 /* Add delay to filter out noises during initial link setup */
1991 * txgbe_disable_tx_laser_multispeed_fiber - Disable Tx laser
1992 * @hw: pointer to hardware structure
1994 * The base drivers may require better control over SFP+ module
1995 * PHY states. This includes selectively shutting down the Tx
1996 * laser on the PHY, effectively halting physical link.
1998 void txgbe_disable_tx_laser_multispeed_fiber(struct txgbe_hw *hw)
2000 u32 esdp_reg = rd32(hw, TXGBE_GPIODATA);
2002 /* Blocked by MNG FW so bail */
2003 if (txgbe_check_reset_blocked(hw))
2006 /* Disable Tx laser; allow 100us to go dark per spec */
2007 esdp_reg |= (TXGBE_GPIOBIT_0 | TXGBE_GPIOBIT_1);
2008 wr32(hw, TXGBE_GPIODATA, esdp_reg);
2014 * txgbe_enable_tx_laser_multispeed_fiber - Enable Tx laser
2015 * @hw: pointer to hardware structure
2017 * The base drivers may require better control over SFP+ module
2018 * PHY states. This includes selectively turning on the Tx
2019 * laser on the PHY, effectively starting physical link.
2021 void txgbe_enable_tx_laser_multispeed_fiber(struct txgbe_hw *hw)
2023 u32 esdp_reg = rd32(hw, TXGBE_GPIODATA);
2025 /* Enable Tx laser; allow 100ms to light up */
2026 esdp_reg &= ~(TXGBE_GPIOBIT_0 | TXGBE_GPIOBIT_1);
2027 wr32(hw, TXGBE_GPIODATA, esdp_reg);
2033 * txgbe_flap_tx_laser_multispeed_fiber - Flap Tx laser
2034 * @hw: pointer to hardware structure
2036 * When the driver changes the link speeds that it can support,
2037 * it sets autotry_restart to true to indicate that we need to
2038 * initiate a new autotry session with the link partner. To do
2039 * so, we set the speed then disable and re-enable the Tx laser, to
2040 * alert the link partner that it also needs to restart autotry on its
2041 * end. This is consistent with true clause 37 autoneg, which also
2042 * involves a loss of signal.
2044 void txgbe_flap_tx_laser_multispeed_fiber(struct txgbe_hw *hw)
2046 DEBUGFUNC("txgbe_flap_tx_laser_multispeed_fiber");
2048 /* Blocked by MNG FW so bail */
2049 if (txgbe_check_reset_blocked(hw))
2052 if (hw->mac.autotry_restart) {
2053 txgbe_disable_tx_laser_multispeed_fiber(hw);
2054 txgbe_enable_tx_laser_multispeed_fiber(hw);
2055 hw->mac.autotry_restart = false;
2060 * txgbe_set_hard_rate_select_speed - Set module link speed
2061 * @hw: pointer to hardware structure
2062 * @speed: link speed to set
2064 * Set module link speed via RS0/RS1 rate select pins.
2066 void txgbe_set_hard_rate_select_speed(struct txgbe_hw *hw,
2069 u32 esdp_reg = rd32(hw, TXGBE_GPIODATA);
2072 case TXGBE_LINK_SPEED_10GB_FULL:
2073 esdp_reg |= (TXGBE_GPIOBIT_4 | TXGBE_GPIOBIT_5);
2075 case TXGBE_LINK_SPEED_1GB_FULL:
2076 esdp_reg &= ~(TXGBE_GPIOBIT_4 | TXGBE_GPIOBIT_5);
2079 DEBUGOUT("Invalid fixed module speed\n");
2083 wr32(hw, TXGBE_GPIODATA, esdp_reg);
2088 * txgbe_setup_mac_link_smartspeed - Set MAC link speed using SmartSpeed
2089 * @hw: pointer to hardware structure
2090 * @speed: new link speed
2091 * @autoneg_wait_to_complete: true when waiting for completion is needed
2093 * Implements the Intel SmartSpeed algorithm.
2095 s32 txgbe_setup_mac_link_smartspeed(struct txgbe_hw *hw,
2097 bool autoneg_wait_to_complete)
2100 u32 link_speed = TXGBE_LINK_SPEED_UNKNOWN;
2102 bool link_up = false;
2103 u32 autoc_reg = rd32_epcs(hw, SR_AN_MMD_ADV_REG1);
2105 DEBUGFUNC("txgbe_setup_mac_link_smartspeed");
2107 /* Set autoneg_advertised value based on input link speed */
2108 hw->phy.autoneg_advertised = 0;
2110 if (speed & TXGBE_LINK_SPEED_10GB_FULL)
2111 hw->phy.autoneg_advertised |= TXGBE_LINK_SPEED_10GB_FULL;
2113 if (speed & TXGBE_LINK_SPEED_1GB_FULL)
2114 hw->phy.autoneg_advertised |= TXGBE_LINK_SPEED_1GB_FULL;
2116 if (speed & TXGBE_LINK_SPEED_100M_FULL)
2117 hw->phy.autoneg_advertised |= TXGBE_LINK_SPEED_100M_FULL;
2120 * Implement Intel SmartSpeed algorithm. SmartSpeed will reduce the
2121 * autoneg advertisement if link is unable to be established at the
2122 * highest negotiated rate. This can sometimes happen due to integrity
2123 * issues with the physical media connection.
2126 /* First, try to get link with full advertisement */
2127 hw->phy.smart_speed_active = false;
2128 for (j = 0; j < TXGBE_SMARTSPEED_MAX_RETRIES; j++) {
2129 status = txgbe_setup_mac_link(hw, speed,
2130 autoneg_wait_to_complete);
2135 * Wait for the controller to acquire link. Per IEEE 802.3ap,
2136 * Section 73.10.2, we may have to wait up to 500ms if KR is
2137 * attempted, or 200ms if KX/KX4/BX/BX4 is attempted, per
2138 * Table 9 in the AN MAS.
2140 for (i = 0; i < 5; i++) {
2143 /* If we have link, just jump out */
2144 status = hw->mac.check_link(hw, &link_speed, &link_up,
2155 * We didn't get link. If we advertised KR plus one of KX4/KX
2156 * (or BX4/BX), then disable KR and try again.
2158 if (((autoc_reg & TXGBE_AUTOC_KR_SUPP) == 0) ||
2159 ((autoc_reg & TXGBE_AUTOC_KX_SUPP) == 0 &&
2160 (autoc_reg & TXGBE_AUTOC_KX4_SUPP) == 0))
2163 /* Turn SmartSpeed on to disable KR support */
2164 hw->phy.smart_speed_active = true;
2165 status = txgbe_setup_mac_link(hw, speed,
2166 autoneg_wait_to_complete);
2171 * Wait for the controller to acquire link. 600ms will allow for
2172 * the AN link_fail_inhibit_timer as well for multiple cycles of
2173 * parallel detect, both 10g and 1g. This allows for the maximum
2174 * connect attempts as defined in the AN MAS table 73-7.
2176 for (i = 0; i < 6; i++) {
2179 /* If we have link, just jump out */
2180 status = hw->mac.check_link(hw, &link_speed, &link_up, false);
2188 /* We didn't get link. Turn SmartSpeed back off. */
2189 hw->phy.smart_speed_active = false;
2190 status = txgbe_setup_mac_link(hw, speed,
2191 autoneg_wait_to_complete);
2194 if (link_up && link_speed == TXGBE_LINK_SPEED_1GB_FULL)
2195 DEBUGOUT("Smartspeed has downgraded the link speed "
2196 "from the maximum advertised\n");
2201 * txgbe_setup_mac_link - Set MAC link speed
2202 * @hw: pointer to hardware structure
2203 * @speed: new link speed
2204 * @autoneg_wait_to_complete: true when waiting for completion is needed
2206 * Set the link speed in the AUTOC register and restarts link.
2208 s32 txgbe_setup_mac_link(struct txgbe_hw *hw,
2210 bool autoneg_wait_to_complete)
2212 bool autoneg = false;
2215 u64 autoc = hw->mac.autoc_read(hw);
2216 u64 pma_pmd_10gs = autoc & TXGBE_AUTOC_10GS_PMA_PMD_MASK;
2217 u64 pma_pmd_1g = autoc & TXGBE_AUTOC_1G_PMA_PMD_MASK;
2218 u64 link_mode = autoc & TXGBE_AUTOC_LMS_MASK;
2219 u64 current_autoc = autoc;
2223 u32 link_capabilities = TXGBE_LINK_SPEED_UNKNOWN;
2225 DEBUGFUNC("txgbe_setup_mac_link");
2227 /* Check to see if speed passed in is supported. */
2228 status = hw->mac.get_link_capabilities(hw,
2229 &link_capabilities, &autoneg);
2233 speed &= link_capabilities;
2234 if (speed == TXGBE_LINK_SPEED_UNKNOWN)
2235 return TXGBE_ERR_LINK_SETUP;
2237 /* Use stored value (EEPROM defaults) of AUTOC to find KR/KX4 support*/
2238 if (hw->mac.orig_link_settings_stored)
2239 orig_autoc = hw->mac.orig_autoc;
2243 link_mode = autoc & TXGBE_AUTOC_LMS_MASK;
2244 pma_pmd_1g = autoc & TXGBE_AUTOC_1G_PMA_PMD_MASK;
2246 if (link_mode == TXGBE_AUTOC_LMS_KX4_KX_KR ||
2247 link_mode == TXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
2248 link_mode == TXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
2249 /* Set KX4/KX/KR support according to speed requested */
2250 autoc &= ~(TXGBE_AUTOC_KX_SUPP |
2251 TXGBE_AUTOC_KX4_SUPP |
2252 TXGBE_AUTOC_KR_SUPP);
2253 if (speed & TXGBE_LINK_SPEED_10GB_FULL) {
2254 if (orig_autoc & TXGBE_AUTOC_KX4_SUPP)
2255 autoc |= TXGBE_AUTOC_KX4_SUPP;
2256 if ((orig_autoc & TXGBE_AUTOC_KR_SUPP) &&
2257 !hw->phy.smart_speed_active)
2258 autoc |= TXGBE_AUTOC_KR_SUPP;
2260 if (speed & TXGBE_LINK_SPEED_1GB_FULL)
2261 autoc |= TXGBE_AUTOC_KX_SUPP;
2262 } else if ((pma_pmd_1g == TXGBE_AUTOC_1G_SFI) &&
2263 (link_mode == TXGBE_AUTOC_LMS_1G_LINK_NO_AN ||
2264 link_mode == TXGBE_AUTOC_LMS_1G_AN)) {
2265 /* Switch from 1G SFI to 10G SFI if requested */
2266 if (speed == TXGBE_LINK_SPEED_10GB_FULL &&
2267 pma_pmd_10gs == TXGBE_AUTOC_10GS_SFI) {
2268 autoc &= ~TXGBE_AUTOC_LMS_MASK;
2269 autoc |= TXGBE_AUTOC_LMS_10G;
2271 } else if ((pma_pmd_10gs == TXGBE_AUTOC_10GS_SFI) &&
2272 (link_mode == TXGBE_AUTOC_LMS_10G)) {
2273 /* Switch from 10G SFI to 1G SFI if requested */
2274 if (speed == TXGBE_LINK_SPEED_1GB_FULL &&
2275 pma_pmd_1g == TXGBE_AUTOC_1G_SFI) {
2276 autoc &= ~TXGBE_AUTOC_LMS_MASK;
2277 if (autoneg || hw->phy.type == txgbe_phy_qsfp_intel)
2278 autoc |= TXGBE_AUTOC_LMS_1G_AN;
2280 autoc |= TXGBE_AUTOC_LMS_1G_LINK_NO_AN;
2284 if (autoc == current_autoc)
2287 autoc &= ~TXGBE_AUTOC_SPEED_MASK;
2288 autoc |= TXGBE_AUTOC_SPEED(speed);
2289 autoc |= (autoneg ? TXGBE_AUTOC_AUTONEG : 0);
2292 hw->mac.autoc_write(hw, autoc);
2294 /* Only poll for autoneg to complete if specified to do so */
2295 if (autoneg_wait_to_complete) {
2296 if (link_mode == TXGBE_AUTOC_LMS_KX4_KX_KR ||
2297 link_mode == TXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
2298 link_mode == TXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
2299 links_reg = 0; /*Just in case Autoneg time=0*/
2300 for (i = 0; i < TXGBE_AUTO_NEG_TIME; i++) {
2301 links_reg = rd32(hw, TXGBE_PORTSTAT);
2302 if (links_reg & TXGBE_PORTSTAT_UP)
2306 if (!(links_reg & TXGBE_PORTSTAT_UP)) {
2307 status = TXGBE_ERR_AUTONEG_NOT_COMPLETE;
2308 DEBUGOUT("Autoneg did not complete.\n");
2313 /* Add delay to filter out noises during initial link setup */
2320 * txgbe_setup_copper_link_raptor - Set the PHY autoneg advertised field
2321 * @hw: pointer to hardware structure
2322 * @speed: new link speed
2323 * @autoneg_wait_to_complete: true if waiting is needed to complete
2325 * Restarts link on PHY and MAC based on settings passed in.
2327 static s32 txgbe_setup_copper_link_raptor(struct txgbe_hw *hw,
2329 bool autoneg_wait_to_complete)
2333 DEBUGFUNC("txgbe_setup_copper_link_raptor");
2335 /* Setup the PHY according to input speed */
2336 status = hw->phy.setup_link_speed(hw, speed,
2337 autoneg_wait_to_complete);
2339 txgbe_start_mac_link_raptor(hw, autoneg_wait_to_complete);
2345 txgbe_check_flash_load(struct txgbe_hw *hw, u32 check_bit)
2350 /* if there's flash existing */
2351 if (!(rd32(hw, TXGBE_SPISTAT) & TXGBE_SPISTAT_BPFLASH)) {
2352 /* wait hw load flash done */
2353 for (i = 0; i < 10; i++) {
2354 reg = rd32(hw, TXGBE_ILDRSTAT);
2355 if (!(reg & check_bit)) {
2362 err = TXGBE_ERR_FLASH_LOADING_FAILED;
2368 txgbe_reset_misc(struct txgbe_hw *hw)
2373 wr32(hw, TXGBE_ISBADDRL, hw->isb_dma & 0x00000000FFFFFFFF);
2374 wr32(hw, TXGBE_ISBADDRH, hw->isb_dma >> 32);
2376 value = rd32_epcs(hw, SR_XS_PCS_CTRL2);
2377 if ((value & 0x3) != SR_PCS_CTRL2_TYPE_SEL_X)
2378 hw->link_status = TXGBE_LINK_STATUS_NONE;
2380 /* receive packets that size > 2048 */
2381 wr32m(hw, TXGBE_MACRXCFG,
2382 TXGBE_MACRXCFG_JUMBO, TXGBE_MACRXCFG_JUMBO);
2384 wr32m(hw, TXGBE_FRMSZ, TXGBE_FRMSZ_MAX_MASK,
2385 TXGBE_FRMSZ_MAX(TXGBE_FRAME_SIZE_DFT));
2387 /* clear counters on read */
2388 wr32m(hw, TXGBE_MACCNTCTL,
2389 TXGBE_MACCNTCTL_RC, TXGBE_MACCNTCTL_RC);
2391 wr32m(hw, TXGBE_RXFCCFG,
2392 TXGBE_RXFCCFG_FC, TXGBE_RXFCCFG_FC);
2393 wr32m(hw, TXGBE_TXFCCFG,
2394 TXGBE_TXFCCFG_FC, TXGBE_TXFCCFG_FC);
2396 wr32m(hw, TXGBE_MACRXFLT,
2397 TXGBE_MACRXFLT_PROMISC, TXGBE_MACRXFLT_PROMISC);
2399 wr32m(hw, TXGBE_RSTSTAT,
2400 TXGBE_RSTSTAT_TMRINIT_MASK, TXGBE_RSTSTAT_TMRINIT(30));
2402 /* errata 4: initialize mng flex tbl and wakeup flex tbl*/
2403 wr32(hw, TXGBE_MNGFLEXSEL, 0);
2404 for (i = 0; i < 16; i++) {
2405 wr32(hw, TXGBE_MNGFLEXDWL(i), 0);
2406 wr32(hw, TXGBE_MNGFLEXDWH(i), 0);
2407 wr32(hw, TXGBE_MNGFLEXMSK(i), 0);
2409 wr32(hw, TXGBE_LANFLEXSEL, 0);
2410 for (i = 0; i < 16; i++) {
2411 wr32(hw, TXGBE_LANFLEXDWL(i), 0);
2412 wr32(hw, TXGBE_LANFLEXDWH(i), 0);
2413 wr32(hw, TXGBE_LANFLEXMSK(i), 0);
2416 /* set pause frame dst mac addr */
2417 wr32(hw, TXGBE_RXPBPFCDMACL, 0xC2000001);
2418 wr32(hw, TXGBE_RXPBPFCDMACH, 0x0180);
2420 hw->mac.init_thermal_sensor_thresh(hw);
2422 /* enable mac transmitter */
2423 wr32m(hw, TXGBE_MACTXCFG, TXGBE_MACTXCFG_TXE, TXGBE_MACTXCFG_TXE);
2425 for (i = 0; i < 4; i++)
2426 wr32m(hw, TXGBE_IVAR(i), 0x80808080, 0);
2430 * txgbe_reset_hw - Perform hardware reset
2431 * @hw: pointer to hardware structure
2433 * Resets the hardware by resetting the transmit and receive units, masks
2434 * and clears all interrupts, perform a PHY reset, and perform a link (MAC)
2437 s32 txgbe_reset_hw(struct txgbe_hw *hw)
2442 DEBUGFUNC("txgbe_reset_hw");
2444 /* Call adapter stop to disable tx/rx and clear interrupts */
2445 status = hw->mac.stop_hw(hw);
2449 /* flush pending Tx transactions */
2450 txgbe_clear_tx_pending(hw);
2452 /* Identify PHY and related function pointers */
2453 status = hw->phy.init(hw);
2454 if (status == TXGBE_ERR_SFP_NOT_SUPPORTED)
2457 /* Setup SFP module if there is one present. */
2458 if (hw->phy.sfp_setup_needed) {
2459 status = hw->mac.setup_sfp(hw);
2460 hw->phy.sfp_setup_needed = false;
2462 if (status == TXGBE_ERR_SFP_NOT_SUPPORTED)
2466 if (!hw->phy.reset_disable)
2469 /* remember AUTOC from before we reset */
2470 autoc = hw->mac.autoc_read(hw);
2474 * Issue global reset to the MAC. Needs to be SW reset if link is up.
2475 * If link reset is used when link is up, it might reset the PHY when
2476 * mng is using it. If link is down or the flag to force full link
2477 * reset is set, then perform link reset.
2479 if (txgbe_mng_present(hw)) {
2480 txgbe_hic_reset(hw);
2482 wr32(hw, TXGBE_RST, TXGBE_RST_LAN(hw->bus.lan_id));
2487 txgbe_reset_misc(hw);
2489 if (hw->bus.lan_id == 0) {
2490 status = txgbe_check_flash_load(hw,
2491 TXGBE_ILDRSTAT_SWRST_LAN0);
2493 status = txgbe_check_flash_load(hw,
2494 TXGBE_ILDRSTAT_SWRST_LAN1);
2502 * Double resets are required for recovery from certain error
2503 * conditions. Between resets, it is necessary to stall to
2504 * allow time for any pending HW events to complete.
2506 if (hw->mac.flags & TXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
2507 hw->mac.flags &= ~TXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
2512 * Store the original AUTOC/AUTOC2 values if they have not been
2513 * stored off yet. Otherwise restore the stored original
2514 * values since the reset operation sets back to defaults.
2516 if (!hw->mac.orig_link_settings_stored) {
2517 hw->mac.orig_autoc = hw->mac.autoc_read(hw);
2518 hw->mac.autoc_write(hw, hw->mac.orig_autoc);
2519 hw->mac.orig_link_settings_stored = true;
2521 hw->mac.orig_autoc = autoc;
2524 /* Store the permanent mac address */
2525 hw->mac.get_mac_addr(hw, hw->mac.perm_addr);
2528 * Store MAC address from RAR0, clear receive address registers, and
2529 * clear the multicast table. Also reset num_rar_entries to 128,
2530 * since we modify this value when programming the SAN MAC address.
2532 hw->mac.num_rar_entries = 128;
2533 hw->mac.init_rx_addrs(hw);
2535 /* Store the permanent SAN mac address */
2536 hw->mac.get_san_mac_addr(hw, hw->mac.san_addr);
2538 /* Add the SAN MAC address to the RAR only if it's a valid address */
2539 if (txgbe_validate_mac_addr(hw->mac.san_addr) == 0) {
2540 /* Save the SAN MAC RAR index */
2541 hw->mac.san_mac_rar_index = hw->mac.num_rar_entries - 1;
2543 hw->mac.set_rar(hw, hw->mac.san_mac_rar_index,
2544 hw->mac.san_addr, 0, true);
2546 /* clear VMDq pool/queue selection for this RAR */
2547 hw->mac.clear_vmdq(hw, hw->mac.san_mac_rar_index,
2550 /* Reserve the last RAR for the SAN MAC address */
2551 hw->mac.num_rar_entries--;
2554 /* Store the alternative WWNN/WWPN prefix */
2555 hw->mac.get_wwn_prefix(hw, &hw->mac.wwnn_prefix,
2556 &hw->mac.wwpn_prefix);
2562 * txgbe_start_hw_raptor - Prepare hardware for Tx/Rx
2563 * @hw: pointer to hardware structure
2565 * Starts the hardware using the generic start_hw function
2566 * and the generation start_hw function.
2567 * Then performs revision-specific operations, if any.
2569 s32 txgbe_start_hw_raptor(struct txgbe_hw *hw)
2573 DEBUGFUNC("txgbe_start_hw_raptor");
2575 err = txgbe_start_hw(hw);
2579 err = txgbe_start_hw_gen2(hw);
2583 /* We need to run link autotry after the driver loads */
2584 hw->mac.autotry_restart = true;
2591 * txgbe_enable_rx_dma_raptor - Enable the Rx DMA unit
2592 * @hw: pointer to hardware structure
2593 * @regval: register value to write to RXCTRL
2595 * Enables the Rx DMA unit
2597 s32 txgbe_enable_rx_dma_raptor(struct txgbe_hw *hw, u32 regval)
2599 DEBUGFUNC("txgbe_enable_rx_dma_raptor");
2602 * Workaround silicon errata when enabling the Rx datapath.
2603 * If traffic is incoming before we enable the Rx unit, it could hang
2604 * the Rx DMA unit. Therefore, make sure the security engine is
2605 * completely disabled prior to enabling the Rx unit.
2608 hw->mac.disable_sec_rx_path(hw);
2610 if (regval & TXGBE_PBRXCTL_ENA)
2611 txgbe_enable_rx(hw);
2613 txgbe_disable_rx(hw);
2615 hw->mac.enable_sec_rx_path(hw);
2621 * txgbe_verify_lesm_fw_enabled_raptor - Checks LESM FW module state.
2622 * @hw: pointer to hardware structure
2624 * Returns true if the LESM FW module is present and enabled. Otherwise
2625 * returns false. Smart Speed must be disabled if LESM FW module is enabled.
2627 bool txgbe_verify_lesm_fw_enabled_raptor(struct txgbe_hw *hw)
2629 bool lesm_enabled = false;
2630 u16 fw_offset, fw_lesm_param_offset, fw_lesm_state;
2633 DEBUGFUNC("txgbe_verify_lesm_fw_enabled_raptor");
2635 /* get the offset to the Firmware Module block */
2636 status = hw->rom.read16(hw, TXGBE_FW_PTR, &fw_offset);
2638 if (status != 0 || fw_offset == 0 || fw_offset == 0xFFFF)
2641 /* get the offset to the LESM Parameters block */
2642 status = hw->rom.read16(hw, (fw_offset +
2643 TXGBE_FW_LESM_PARAMETERS_PTR),
2644 &fw_lesm_param_offset);
2647 fw_lesm_param_offset == 0 || fw_lesm_param_offset == 0xFFFF)
2650 /* get the LESM state word */
2651 status = hw->rom.read16(hw, (fw_lesm_param_offset +
2652 TXGBE_FW_LESM_STATE_1),
2655 if (status == 0 && (fw_lesm_state & TXGBE_FW_LESM_STATE_ENABLED))
2656 lesm_enabled = true;
2659 lesm_enabled = false;
2660 return lesm_enabled;
2664 * txgbe_reset_pipeline_raptor - perform pipeline reset
2666 * @hw: pointer to hardware structure
2668 * Reset pipeline by asserting Restart_AN together with LMS change to ensure
2669 * full pipeline reset. This function assumes the SW/FW lock is held.
2671 s32 txgbe_reset_pipeline_raptor(struct txgbe_hw *hw)
2676 autoc = hw->mac.autoc_read(hw);
2678 /* Enable link if disabled in NVM */
2679 if (autoc & TXGBE_AUTOC_LINK_DIA_MASK)
2680 autoc &= ~TXGBE_AUTOC_LINK_DIA_MASK;
2682 autoc |= TXGBE_AUTOC_AN_RESTART;
2683 /* Write AUTOC register with toggled LMS[2] bit and Restart_AN */
2684 hw->mac.autoc_write(hw, autoc ^ TXGBE_AUTOC_LMS_AN);
2686 /* Write AUTOC register with original LMS field and Restart_AN */
2687 hw->mac.autoc_write(hw, autoc);