1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2015-2020 Beijing WangXun Technology Co., Ltd.
3 * Copyright(c) 2010-2017 Intel Corporation
9 #include "txgbe_type.h"
12 #define TXGBE_PMMBX_QSIZE 64 /* Num of dwords in range */
13 #define TXGBE_PMMBX_BSIZE (TXGBE_PMMBX_QSIZE * 4)
14 #define TXGBE_PMMBX_DATA_SIZE (TXGBE_PMMBX_BSIZE - FW_NVM_DATA_OFFSET * 4)
15 #define TXGBE_HI_COMMAND_TIMEOUT 5000 /* Process HI command limit */
16 #define TXGBE_HI_FLASH_ERASE_TIMEOUT 5000 /* Process Erase command limit */
17 #define TXGBE_HI_FLASH_UPDATE_TIMEOUT 5000 /* Process Update command limit */
18 #define TXGBE_HI_FLASH_VERIFY_TIMEOUT 60000 /* Process Apply command limit */
19 #define TXGBE_HI_PHY_MGMT_REQ_TIMEOUT 2000 /* Wait up to 2 seconds */
22 #define FW_CEM_HDR_LEN 0x4
23 #define FW_CEM_CMD_DRIVER_INFO 0xDD
24 #define FW_CEM_CMD_DRIVER_INFO_LEN 0x5
25 #define FW_CEM_CMD_RESERVED 0X0
26 #define FW_CEM_UNUSED_VER 0x0
27 #define FW_CEM_MAX_RETRIES 3
28 #define FW_CEM_RESP_STATUS_SUCCESS 0x1
29 #define FW_READ_SHADOW_RAM_CMD 0x31
30 #define FW_READ_SHADOW_RAM_LEN 0x6
31 #define FW_WRITE_SHADOW_RAM_CMD 0x33
32 #define FW_WRITE_SHADOW_RAM_LEN 0xA /* 8 plus 1 WORD to write */
33 #define FW_SHADOW_RAM_DUMP_CMD 0x36
34 #define FW_SHADOW_RAM_DUMP_LEN 0
35 #define FW_DEFAULT_CHECKSUM 0xFF /* checksum always 0xFF */
36 #define FW_NVM_DATA_OFFSET 3
37 #define FW_MAX_READ_BUFFER_SIZE 244
38 #define FW_DISABLE_RXEN_CMD 0xDE
39 #define FW_DISABLE_RXEN_LEN 0x1
40 #define FW_PHY_MGMT_REQ_CMD 0x20
41 #define FW_RESET_CMD 0xDF
42 #define FW_RESET_LEN 0x2
43 #define FW_SETUP_MAC_LINK_CMD 0xE0
44 #define FW_SETUP_MAC_LINK_LEN 0x2
45 #define FW_FLASH_UPGRADE_START_CMD 0xE3
46 #define FW_FLASH_UPGRADE_START_LEN 0x1
47 #define FW_FLASH_UPGRADE_WRITE_CMD 0xE4
48 #define FW_FLASH_UPGRADE_VERIFY_CMD 0xE5
49 #define FW_FLASH_UPGRADE_VERIFY_LEN 0x4
50 #define FW_PHY_ACT_DATA_COUNT 4
51 #define FW_PHY_TOKEN_DELAY 5 /* milliseconds */
52 #define FW_PHY_TOKEN_WAIT 5 /* seconds */
53 #define FW_PHY_TOKEN_RETRIES ((FW_PHY_TOKEN_WAIT * 1000) / FW_PHY_TOKEN_DELAY)
55 /* Host Interface Command Structures */
56 struct txgbe_hic_hdr {
66 struct txgbe_hic_hdr2_req {
73 struct txgbe_hic_hdr2_rsp {
76 u8 buf_lenh_status; /* 7-5: high bits of buf_len, 4-0: status */
80 union txgbe_hic_hdr2 {
81 struct txgbe_hic_hdr2_req req;
82 struct txgbe_hic_hdr2_rsp rsp;
85 struct txgbe_hic_drv_info {
86 struct txgbe_hic_hdr hdr;
92 u8 pad; /* end spacing to ensure length is mult. of dword */
93 u16 pad2; /* end spacing to ensure length is mult. of dword2 */
96 /* These need to be dword aligned */
97 struct txgbe_hic_read_shadow_ram {
98 union txgbe_hic_hdr2 hdr;
106 struct txgbe_hic_write_shadow_ram {
107 union txgbe_hic_hdr2 hdr;
115 struct txgbe_hic_disable_rxen {
116 struct txgbe_hic_hdr hdr;
122 struct txgbe_hic_reset {
123 struct txgbe_hic_hdr hdr;
128 struct txgbe_hic_phy_cfg {
129 struct txgbe_hic_hdr hdr;
135 enum txgbe_module_id {
136 TXGBE_MODULE_EEPROM = 0,
137 TXGBE_MODULE_FIRMWARE,
138 TXGBE_MODULE_HARDWARE,
142 struct txgbe_hic_upg_start {
143 struct txgbe_hic_hdr hdr;
149 struct txgbe_hic_upg_write {
150 struct txgbe_hic_hdr hdr;
157 enum txgbe_upg_flag {
158 TXGBE_RESET_NONE = 0,
159 TXGBE_RESET_FIRMWARE,
164 struct txgbe_hic_upg_verify {
165 struct txgbe_hic_hdr hdr;
169 s32 txgbe_hic_sr_read(struct txgbe_hw *hw, u32 addr, u8 *buf, int len);
170 s32 txgbe_hic_sr_write(struct txgbe_hw *hw, u32 addr, u8 *buf, int len);
172 s32 txgbe_hic_set_drv_ver(struct txgbe_hw *hw, u8 maj, u8 min, u8 build,
173 u8 ver, u16 len, const char *str);
174 s32 txgbe_hic_reset(struct txgbe_hw *hw);
175 bool txgbe_mng_present(struct txgbe_hw *hw);
176 bool txgbe_mng_enabled(struct txgbe_hw *hw);
177 #endif /* _TXGBE_MNG_H_ */