1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2015-2020
6 #include "txgbe_eeprom.h"
10 static void txgbe_i2c_start(struct txgbe_hw *hw);
11 static void txgbe_i2c_stop(struct txgbe_hw *hw);
12 static s32 txgbe_handle_bp_flow(u32 link_mode, struct txgbe_hw *hw);
13 static void txgbe_get_bp_ability(struct txgbe_backplane_ability *ability,
14 u32 link_partner, struct txgbe_hw *hw);
15 static s32 txgbe_check_bp_ability(struct txgbe_backplane_ability *local_ability,
16 struct txgbe_backplane_ability *lp_ability, struct txgbe_hw *hw);
17 static void txgbe_clear_bp_intr(u32 bit, u32 bit_high, struct txgbe_hw *hw);
18 static s32 txgbe_enable_kr_training(struct txgbe_hw *hw);
19 static s32 txgbe_disable_kr_training(struct txgbe_hw *hw, s32 post, s32 mode);
20 static s32 txgbe_check_kr_training(struct txgbe_hw *hw);
21 static void txgbe_read_phy_lane_tx_eq(u16 lane, struct txgbe_hw *hw,
23 static s32 txgbe_set_link_to_sfi(struct txgbe_hw *hw, u32 speed);
26 * txgbe_identify_extphy - Identify a single address for a PHY
27 * @hw: pointer to hardware structure
28 * @phy_addr: PHY address to probe
30 * Returns true if PHY found
32 static bool txgbe_identify_extphy(struct txgbe_hw *hw)
36 if (!txgbe_validate_phy_addr(hw, phy_addr)) {
37 DEBUGOUT("Unable to validate PHY address 0x%04X\n",
42 if (txgbe_get_phy_id(hw))
45 hw->phy.type = txgbe_get_phy_type_from_id(hw->phy.id);
46 if (hw->phy.type == txgbe_phy_unknown) {
48 hw->phy.read_reg(hw, TXGBE_MD_PHY_EXT_ABILITY,
52 if (ext_ability & (TXGBE_MD_PHY_10GBASET_ABILITY |
53 TXGBE_MD_PHY_1000BASET_ABILITY))
54 hw->phy.type = txgbe_phy_cu_unknown;
56 hw->phy.type = txgbe_phy_generic;
63 * txgbe_read_phy_if - Read TXGBE_ETHPHYIF register
64 * @hw: pointer to hardware structure
66 * Read TXGBE_ETHPHYIF register and save field values,
67 * and check for valid field values.
69 static s32 txgbe_read_phy_if(struct txgbe_hw *hw)
71 hw->phy.media_type = hw->phy.get_media_type(hw);
73 /* Save NW management interface connected on board. This is used
74 * to determine internal PHY mode.
76 hw->phy.nw_mng_if_sel = rd32(hw, TXGBE_ETHPHYIF);
78 /* If MDIO is connected to external PHY, then set PHY address. */
79 if (hw->phy.nw_mng_if_sel & TXGBE_ETHPHYIF_MDIO_ACT)
80 hw->phy.addr = TXGBE_ETHPHYIF_MDIO_BASE(hw->phy.nw_mng_if_sel);
82 if (!hw->phy.phy_semaphore_mask) {
84 hw->phy.phy_semaphore_mask = TXGBE_MNGSEM_SWPHY;
86 hw->phy.phy_semaphore_mask = TXGBE_MNGSEM_SWPHY;
93 * txgbe_identify_phy - Get physical layer module
94 * @hw: pointer to hardware structure
96 * Determines the physical layer module found on the current adapter.
98 s32 txgbe_identify_phy(struct txgbe_hw *hw)
100 s32 err = TXGBE_ERR_PHY_ADDR_INVALID;
102 DEBUGFUNC("txgbe_identify_phy");
104 txgbe_read_phy_if(hw);
106 if (hw->phy.type != txgbe_phy_unknown)
109 /* Raptor 10GBASE-T requires an external PHY */
110 if (hw->phy.media_type == txgbe_media_type_copper) {
111 err = txgbe_identify_extphy(hw);
112 } else if (hw->phy.media_type == txgbe_media_type_fiber) {
113 err = txgbe_identify_module(hw);
115 hw->phy.type = txgbe_phy_none;
119 /* Return error if SFP module has been detected but is not supported */
120 if (hw->phy.type == txgbe_phy_sfp_unsupported)
121 return TXGBE_ERR_SFP_NOT_SUPPORTED;
127 * txgbe_check_reset_blocked - check status of MNG FW veto bit
128 * @hw: pointer to the hardware structure
130 * This function checks the STAT.MNGVETO bit to see if there are
131 * any constraints on link from manageability. For MAC's that don't
132 * have this bit just return faluse since the link can not be blocked
135 s32 txgbe_check_reset_blocked(struct txgbe_hw *hw)
139 DEBUGFUNC("txgbe_check_reset_blocked");
141 mmngc = rd32(hw, TXGBE_STAT);
142 if (mmngc & TXGBE_STAT_MNGVETO) {
143 DEBUGOUT("MNG_VETO bit detected.\n");
151 * txgbe_validate_phy_addr - Determines phy address is valid
152 * @hw: pointer to hardware structure
153 * @phy_addr: PHY address
156 bool txgbe_validate_phy_addr(struct txgbe_hw *hw, u32 phy_addr)
161 DEBUGFUNC("txgbe_validate_phy_addr");
163 hw->phy.addr = phy_addr;
164 hw->phy.read_reg(hw, TXGBE_MD_PHY_ID_HIGH,
165 TXGBE_MD_DEV_PMA_PMD, &phy_id);
167 if (phy_id != 0xFFFF && phy_id != 0x0)
170 DEBUGOUT("PHY ID HIGH is 0x%04X\n", phy_id);
176 * txgbe_get_phy_id - Get the phy type
177 * @hw: pointer to hardware structure
180 s32 txgbe_get_phy_id(struct txgbe_hw *hw)
186 DEBUGFUNC("txgbe_get_phy_id");
188 err = hw->phy.read_reg(hw, TXGBE_MD_PHY_ID_HIGH,
189 TXGBE_MD_DEV_PMA_PMD,
193 hw->phy.id = (u32)(phy_id_high << 16);
194 err = hw->phy.read_reg(hw, TXGBE_MD_PHY_ID_LOW,
195 TXGBE_MD_DEV_PMA_PMD,
197 hw->phy.id |= (u32)(phy_id_low & TXGBE_PHY_REVISION_MASK);
198 hw->phy.revision = (u32)(phy_id_low & ~TXGBE_PHY_REVISION_MASK);
200 DEBUGOUT("PHY_ID_HIGH 0x%04X, PHY_ID_LOW 0x%04X\n",
201 phy_id_high, phy_id_low);
207 * txgbe_get_phy_type_from_id - Get the phy type
208 * @phy_id: PHY ID information
211 enum txgbe_phy_type txgbe_get_phy_type_from_id(u32 phy_id)
213 enum txgbe_phy_type phy_type;
215 DEBUGFUNC("txgbe_get_phy_type_from_id");
218 case TXGBE_PHYID_TN1010:
219 phy_type = txgbe_phy_tn;
221 case TXGBE_PHYID_QT2022:
222 phy_type = txgbe_phy_qt;
224 case TXGBE_PHYID_ATH:
225 phy_type = txgbe_phy_nl;
227 case TXGBE_PHYID_MTD3310:
228 phy_type = txgbe_phy_cu_mtd;
231 phy_type = txgbe_phy_unknown;
239 txgbe_reset_extphy(struct txgbe_hw *hw)
244 err = hw->phy.read_reg(hw, TXGBE_MD_PORT_CTRL,
245 TXGBE_MD_DEV_GENERAL, &ctrl);
248 ctrl |= TXGBE_MD_PORT_CTRL_RESET;
249 err = hw->phy.write_reg(hw, TXGBE_MD_PORT_CTRL,
250 TXGBE_MD_DEV_GENERAL, ctrl);
255 * Poll for reset bit to self-clear indicating reset is complete.
256 * Some PHYs could take up to 3 seconds to complete and need about
257 * 1.7 usec delay after the reset is complete.
259 for (i = 0; i < 30; i++) {
261 err = hw->phy.read_reg(hw, TXGBE_MD_PORT_CTRL,
262 TXGBE_MD_DEV_GENERAL, &ctrl);
266 if (!(ctrl & TXGBE_MD_PORT_CTRL_RESET)) {
272 if (ctrl & TXGBE_MD_PORT_CTRL_RESET) {
273 err = TXGBE_ERR_RESET_FAILED;
274 DEBUGOUT("PHY reset polling failed to complete.\n");
281 * txgbe_reset_phy - Performs a PHY reset
282 * @hw: pointer to hardware structure
284 s32 txgbe_reset_phy(struct txgbe_hw *hw)
288 DEBUGFUNC("txgbe_reset_phy");
290 if (hw->phy.type == txgbe_phy_unknown)
291 err = txgbe_identify_phy(hw);
293 if (err != 0 || hw->phy.type == txgbe_phy_none)
296 /* Don't reset PHY if it's shut down due to overtemp. */
297 if (hw->phy.check_overtemp(hw) == TXGBE_ERR_OVERTEMP)
300 /* Blocked by MNG FW so bail */
301 if (txgbe_check_reset_blocked(hw))
304 switch (hw->phy.type) {
305 case txgbe_phy_cu_mtd:
306 err = txgbe_reset_extphy(hw);
316 * txgbe_read_phy_mdi - Reads a value from a specified PHY register without
318 * @hw: pointer to hardware structure
319 * @reg_addr: 32 bit address of PHY register to read
320 * @device_type: 5 bit device type
321 * @phy_data: Pointer to read data from PHY register
323 s32 txgbe_read_phy_reg_mdi(struct txgbe_hw *hw, u32 reg_addr, u32 device_type,
328 /* Setup and write the address cycle command */
329 command = TXGBE_MDIOSCA_REG(reg_addr) |
330 TXGBE_MDIOSCA_DEV(device_type) |
331 TXGBE_MDIOSCA_PORT(hw->phy.addr);
332 wr32(hw, TXGBE_MDIOSCA, command);
334 command = TXGBE_MDIOSCD_CMD_READ |
336 wr32(hw, TXGBE_MDIOSCD, command);
339 * Check every 10 usec to see if the address cycle completed.
340 * The MDI Command bit will clear when the operation is
343 if (!po32m(hw, TXGBE_MDIOSCD, TXGBE_MDIOSCD_BUSY,
344 0, NULL, 100, 100)) {
345 DEBUGOUT("PHY address command did not complete\n");
346 return TXGBE_ERR_PHY;
349 data = rd32(hw, TXGBE_MDIOSCD);
350 *phy_data = (u16)TXGBD_MDIOSCD_DAT(data);
356 * txgbe_read_phy_reg - Reads a value from a specified PHY register
357 * using the SWFW lock - this function is needed in most cases
358 * @hw: pointer to hardware structure
359 * @reg_addr: 32 bit address of PHY register to read
360 * @device_type: 5 bit device type
361 * @phy_data: Pointer to read data from PHY register
363 s32 txgbe_read_phy_reg(struct txgbe_hw *hw, u32 reg_addr,
364 u32 device_type, u16 *phy_data)
367 u32 gssr = hw->phy.phy_semaphore_mask;
369 DEBUGFUNC("txgbe_read_phy_reg");
371 if (hw->mac.acquire_swfw_sync(hw, gssr))
372 return TXGBE_ERR_SWFW_SYNC;
374 err = hw->phy.read_reg_mdi(hw, reg_addr, device_type, phy_data);
376 hw->mac.release_swfw_sync(hw, gssr);
382 * txgbe_write_phy_reg_mdi - Writes a value to specified PHY register
384 * @hw: pointer to hardware structure
385 * @reg_addr: 32 bit PHY register to write
386 * @device_type: 5 bit device type
387 * @phy_data: Data to write to the PHY register
389 s32 txgbe_write_phy_reg_mdi(struct txgbe_hw *hw, u32 reg_addr,
390 u32 device_type, u16 phy_data)
395 command = TXGBE_MDIOSCA_REG(reg_addr) |
396 TXGBE_MDIOSCA_DEV(device_type) |
397 TXGBE_MDIOSCA_PORT(hw->phy.addr);
398 wr32(hw, TXGBE_MDIOSCA, command);
400 command = TXGBE_MDIOSCD_CMD_WRITE |
401 TXGBE_MDIOSCD_DAT(phy_data) |
403 wr32(hw, TXGBE_MDIOSCD, command);
405 /* wait for completion */
406 if (!po32m(hw, TXGBE_MDIOSCD, TXGBE_MDIOSCD_BUSY,
407 0, NULL, 100, 100)) {
408 TLOG_DEBUG("PHY write cmd didn't complete\n");
416 * txgbe_write_phy_reg - Writes a value to specified PHY register
417 * using SWFW lock- this function is needed in most cases
418 * @hw: pointer to hardware structure
419 * @reg_addr: 32 bit PHY register to write
420 * @device_type: 5 bit device type
421 * @phy_data: Data to write to the PHY register
423 s32 txgbe_write_phy_reg(struct txgbe_hw *hw, u32 reg_addr,
424 u32 device_type, u16 phy_data)
427 u32 gssr = hw->phy.phy_semaphore_mask;
429 DEBUGFUNC("txgbe_write_phy_reg");
431 if (hw->mac.acquire_swfw_sync(hw, gssr))
432 err = TXGBE_ERR_SWFW_SYNC;
434 err = hw->phy.write_reg_mdi(hw, reg_addr, device_type,
436 hw->mac.release_swfw_sync(hw, gssr);
442 * txgbe_setup_phy_link - Set and restart auto-neg
443 * @hw: pointer to hardware structure
445 * Restart auto-negotiation and PHY and waits for completion.
447 s32 txgbe_setup_phy_link(struct txgbe_hw *hw)
450 u16 autoneg_reg = TXGBE_MII_AUTONEG_REG;
451 bool autoneg = false;
454 DEBUGFUNC("txgbe_setup_phy_link");
456 txgbe_get_copper_link_capabilities(hw, &speed, &autoneg);
458 /* Set or unset auto-negotiation 10G advertisement */
459 hw->phy.read_reg(hw, TXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
460 TXGBE_MD_DEV_AUTO_NEG,
463 autoneg_reg &= ~TXGBE_MII_10GBASE_T_ADVERTISE;
464 if ((hw->phy.autoneg_advertised & TXGBE_LINK_SPEED_10GB_FULL) &&
465 (speed & TXGBE_LINK_SPEED_10GB_FULL))
466 autoneg_reg |= TXGBE_MII_10GBASE_T_ADVERTISE;
468 hw->phy.write_reg(hw, TXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
469 TXGBE_MD_DEV_AUTO_NEG,
472 hw->phy.read_reg(hw, TXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
473 TXGBE_MD_DEV_AUTO_NEG,
476 /* Set or unset auto-negotiation 5G advertisement */
477 autoneg_reg &= ~TXGBE_MII_5GBASE_T_ADVERTISE;
478 if ((hw->phy.autoneg_advertised & TXGBE_LINK_SPEED_5GB_FULL) &&
479 (speed & TXGBE_LINK_SPEED_5GB_FULL))
480 autoneg_reg |= TXGBE_MII_5GBASE_T_ADVERTISE;
482 /* Set or unset auto-negotiation 2.5G advertisement */
483 autoneg_reg &= ~TXGBE_MII_2_5GBASE_T_ADVERTISE;
484 if ((hw->phy.autoneg_advertised &
485 TXGBE_LINK_SPEED_2_5GB_FULL) &&
486 (speed & TXGBE_LINK_SPEED_2_5GB_FULL))
487 autoneg_reg |= TXGBE_MII_2_5GBASE_T_ADVERTISE;
488 /* Set or unset auto-negotiation 1G advertisement */
489 autoneg_reg &= ~TXGBE_MII_1GBASE_T_ADVERTISE;
490 if ((hw->phy.autoneg_advertised & TXGBE_LINK_SPEED_1GB_FULL) &&
491 (speed & TXGBE_LINK_SPEED_1GB_FULL))
492 autoneg_reg |= TXGBE_MII_1GBASE_T_ADVERTISE;
494 hw->phy.write_reg(hw, TXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
495 TXGBE_MD_DEV_AUTO_NEG,
498 /* Set or unset auto-negotiation 100M advertisement */
499 hw->phy.read_reg(hw, TXGBE_MII_AUTONEG_ADVERTISE_REG,
500 TXGBE_MD_DEV_AUTO_NEG,
503 autoneg_reg &= ~(TXGBE_MII_100BASE_T_ADVERTISE |
504 TXGBE_MII_100BASE_T_ADVERTISE_HALF);
505 if ((hw->phy.autoneg_advertised & TXGBE_LINK_SPEED_100M_FULL) &&
506 (speed & TXGBE_LINK_SPEED_100M_FULL))
507 autoneg_reg |= TXGBE_MII_100BASE_T_ADVERTISE;
509 hw->phy.write_reg(hw, TXGBE_MII_AUTONEG_ADVERTISE_REG,
510 TXGBE_MD_DEV_AUTO_NEG,
513 /* Blocked by MNG FW so don't reset PHY */
514 if (txgbe_check_reset_blocked(hw))
517 /* Restart PHY auto-negotiation. */
518 hw->phy.read_reg(hw, TXGBE_MD_AUTO_NEG_CONTROL,
519 TXGBE_MD_DEV_AUTO_NEG, &autoneg_reg);
521 autoneg_reg |= TXGBE_MII_RESTART;
523 hw->phy.write_reg(hw, TXGBE_MD_AUTO_NEG_CONTROL,
524 TXGBE_MD_DEV_AUTO_NEG, autoneg_reg);
530 * txgbe_setup_phy_link_speed - Sets the auto advertised capabilities
531 * @hw: pointer to hardware structure
532 * @speed: new link speed
533 * @autoneg_wait_to_complete: unused
535 s32 txgbe_setup_phy_link_speed(struct txgbe_hw *hw,
537 bool autoneg_wait_to_complete)
539 UNREFERENCED_PARAMETER(autoneg_wait_to_complete);
541 DEBUGFUNC("txgbe_setup_phy_link_speed");
544 * Clear autoneg_advertised and set new values based on input link
547 hw->phy.autoneg_advertised = 0;
549 if (speed & TXGBE_LINK_SPEED_10GB_FULL)
550 hw->phy.autoneg_advertised |= TXGBE_LINK_SPEED_10GB_FULL;
552 if (speed & TXGBE_LINK_SPEED_5GB_FULL)
553 hw->phy.autoneg_advertised |= TXGBE_LINK_SPEED_5GB_FULL;
555 if (speed & TXGBE_LINK_SPEED_2_5GB_FULL)
556 hw->phy.autoneg_advertised |= TXGBE_LINK_SPEED_2_5GB_FULL;
558 if (speed & TXGBE_LINK_SPEED_1GB_FULL)
559 hw->phy.autoneg_advertised |= TXGBE_LINK_SPEED_1GB_FULL;
561 if (speed & TXGBE_LINK_SPEED_100M_FULL)
562 hw->phy.autoneg_advertised |= TXGBE_LINK_SPEED_100M_FULL;
564 if (speed & TXGBE_LINK_SPEED_10M_FULL)
565 hw->phy.autoneg_advertised |= TXGBE_LINK_SPEED_10M_FULL;
567 /* Setup link based on the new speed settings */
568 hw->phy.setup_link(hw);
573 s32 txgbe_get_phy_fw_version(struct txgbe_hw *hw, u32 *fw_version)
575 u16 eeprom_verh, eeprom_verl;
577 hw->rom.readw_sw(hw, TXGBE_EEPROM_VERSION_H, &eeprom_verh);
578 hw->rom.readw_sw(hw, TXGBE_EEPROM_VERSION_L, &eeprom_verl);
580 *fw_version = (eeprom_verh << 16) | eeprom_verl;
586 * txgbe_get_copper_speeds_supported - Get copper link speeds from phy
587 * @hw: pointer to hardware structure
589 * Determines the supported link capabilities by reading the PHY auto
590 * negotiation register.
592 static s32 txgbe_get_copper_speeds_supported(struct txgbe_hw *hw)
597 err = hw->phy.read_reg(hw, TXGBE_MD_PHY_SPEED_ABILITY,
598 TXGBE_MD_DEV_PMA_PMD,
603 if (speed_ability & TXGBE_MD_PHY_SPEED_10G)
604 hw->phy.speeds_supported |= TXGBE_LINK_SPEED_10GB_FULL;
605 if (speed_ability & TXGBE_MD_PHY_SPEED_1G)
606 hw->phy.speeds_supported |= TXGBE_LINK_SPEED_1GB_FULL;
607 if (speed_ability & TXGBE_MD_PHY_SPEED_100M)
608 hw->phy.speeds_supported |= TXGBE_LINK_SPEED_100M_FULL;
614 * txgbe_get_copper_link_capabilities - Determines link capabilities
615 * @hw: pointer to hardware structure
616 * @speed: pointer to link speed
617 * @autoneg: boolean auto-negotiation value
619 s32 txgbe_get_copper_link_capabilities(struct txgbe_hw *hw,
625 DEBUGFUNC("txgbe_get_copper_link_capabilities");
628 if (!hw->phy.speeds_supported)
629 err = txgbe_get_copper_speeds_supported(hw);
631 *speed = hw->phy.speeds_supported;
636 * txgbe_check_phy_link_tnx - Determine link and speed status
637 * @hw: pointer to hardware structure
638 * @speed: current link speed
639 * @link_up: true is link is up, false otherwise
641 * Reads the VS1 register to determine if link is up and the current speed for
644 s32 txgbe_check_phy_link_tnx(struct txgbe_hw *hw, u32 *speed,
649 u32 max_time_out = 10;
654 DEBUGFUNC("txgbe_check_phy_link_tnx");
656 /* Initialize speed and link to default case */
658 *speed = TXGBE_LINK_SPEED_10GB_FULL;
661 * Check current speed and link status of the PHY register.
662 * This is a vendor specific register and may have to
663 * be changed for other copper PHYs.
665 for (time_out = 0; time_out < max_time_out; time_out++) {
667 err = hw->phy.read_reg(hw,
668 TXGBE_MD_VENDOR_SPECIFIC_1_STATUS,
669 TXGBE_MD_DEV_VENDOR_1,
671 phy_link = phy_data & TXGBE_MD_VENDOR_SPECIFIC_1_LINK_STATUS;
672 phy_speed = phy_data &
673 TXGBE_MD_VENDOR_SPECIFIC_1_SPEED_STATUS;
674 if (phy_link == TXGBE_MD_VENDOR_SPECIFIC_1_LINK_STATUS) {
677 TXGBE_MD_VENDOR_SPECIFIC_1_SPEED_STATUS)
678 *speed = TXGBE_LINK_SPEED_1GB_FULL;
687 * txgbe_setup_phy_link_tnx - Set and restart auto-neg
688 * @hw: pointer to hardware structure
690 * Restart auto-negotiation and PHY and waits for completion.
692 s32 txgbe_setup_phy_link_tnx(struct txgbe_hw *hw)
695 u16 autoneg_reg = TXGBE_MII_AUTONEG_REG;
696 bool autoneg = false;
699 DEBUGFUNC("txgbe_setup_phy_link_tnx");
701 txgbe_get_copper_link_capabilities(hw, &speed, &autoneg);
703 if (speed & TXGBE_LINK_SPEED_10GB_FULL) {
704 /* Set or unset auto-negotiation 10G advertisement */
705 hw->phy.read_reg(hw, TXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
706 TXGBE_MD_DEV_AUTO_NEG,
709 autoneg_reg &= ~TXGBE_MII_10GBASE_T_ADVERTISE;
710 if (hw->phy.autoneg_advertised & TXGBE_LINK_SPEED_10GB_FULL)
711 autoneg_reg |= TXGBE_MII_10GBASE_T_ADVERTISE;
713 hw->phy.write_reg(hw, TXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
714 TXGBE_MD_DEV_AUTO_NEG,
718 if (speed & TXGBE_LINK_SPEED_1GB_FULL) {
719 /* Set or unset auto-negotiation 1G advertisement */
720 hw->phy.read_reg(hw, TXGBE_MII_AUTONEG_XNP_TX_REG,
721 TXGBE_MD_DEV_AUTO_NEG,
724 autoneg_reg &= ~TXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
725 if (hw->phy.autoneg_advertised & TXGBE_LINK_SPEED_1GB_FULL)
726 autoneg_reg |= TXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
728 hw->phy.write_reg(hw, TXGBE_MII_AUTONEG_XNP_TX_REG,
729 TXGBE_MD_DEV_AUTO_NEG,
733 if (speed & TXGBE_LINK_SPEED_100M_FULL) {
734 /* Set or unset auto-negotiation 100M advertisement */
735 hw->phy.read_reg(hw, TXGBE_MII_AUTONEG_ADVERTISE_REG,
736 TXGBE_MD_DEV_AUTO_NEG,
739 autoneg_reg &= ~TXGBE_MII_100BASE_T_ADVERTISE;
740 if (hw->phy.autoneg_advertised & TXGBE_LINK_SPEED_100M_FULL)
741 autoneg_reg |= TXGBE_MII_100BASE_T_ADVERTISE;
743 hw->phy.write_reg(hw, TXGBE_MII_AUTONEG_ADVERTISE_REG,
744 TXGBE_MD_DEV_AUTO_NEG,
748 /* Blocked by MNG FW so don't reset PHY */
749 if (txgbe_check_reset_blocked(hw))
752 /* Restart PHY auto-negotiation. */
753 hw->phy.read_reg(hw, TXGBE_MD_AUTO_NEG_CONTROL,
754 TXGBE_MD_DEV_AUTO_NEG, &autoneg_reg);
756 autoneg_reg |= TXGBE_MII_RESTART;
758 hw->phy.write_reg(hw, TXGBE_MD_AUTO_NEG_CONTROL,
759 TXGBE_MD_DEV_AUTO_NEG, autoneg_reg);
765 * txgbe_identify_module - Identifies module type
766 * @hw: pointer to hardware structure
768 * Determines HW type and calls appropriate function.
770 s32 txgbe_identify_module(struct txgbe_hw *hw)
772 s32 err = TXGBE_ERR_SFP_NOT_PRESENT;
774 DEBUGFUNC("txgbe_identify_module");
776 switch (hw->phy.media_type) {
777 case txgbe_media_type_fiber:
778 err = txgbe_identify_sfp_module(hw);
781 case txgbe_media_type_fiber_qsfp:
782 err = txgbe_identify_qsfp_module(hw);
786 hw->phy.sfp_type = txgbe_sfp_type_not_present;
787 err = TXGBE_ERR_SFP_NOT_PRESENT;
795 * txgbe_identify_sfp_module - Identifies SFP modules
796 * @hw: pointer to hardware structure
798 * Searches for and identifies the SFP module and assigns appropriate PHY type.
800 s32 txgbe_identify_sfp_module(struct txgbe_hw *hw)
802 s32 err = TXGBE_ERR_PHY_ADDR_INVALID;
804 enum txgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
806 u8 comp_codes_1g = 0;
807 u8 comp_codes_10g = 0;
808 u8 oui_bytes[3] = {0, 0, 0};
813 DEBUGFUNC("txgbe_identify_sfp_module");
815 if (hw->phy.media_type != txgbe_media_type_fiber) {
816 hw->phy.sfp_type = txgbe_sfp_type_not_present;
817 return TXGBE_ERR_SFP_NOT_PRESENT;
820 err = hw->phy.read_i2c_eeprom(hw, TXGBE_SFF_IDENTIFIER,
824 hw->phy.sfp_type = txgbe_sfp_type_not_present;
825 if (hw->phy.type != txgbe_phy_nl) {
827 hw->phy.type = txgbe_phy_unknown;
829 return TXGBE_ERR_SFP_NOT_PRESENT;
832 if (identifier != TXGBE_SFF_IDENTIFIER_SFP) {
833 hw->phy.type = txgbe_phy_sfp_unsupported;
834 return TXGBE_ERR_SFP_NOT_SUPPORTED;
837 err = hw->phy.read_i2c_eeprom(hw, TXGBE_SFF_1GBE_COMP_CODES,
842 err = hw->phy.read_i2c_eeprom(hw, TXGBE_SFF_10GBE_COMP_CODES,
847 err = hw->phy.read_i2c_eeprom(hw, TXGBE_SFF_CABLE_TECHNOLOGY,
857 * 3 SFP_DA_CORE0 - chip-specific
858 * 4 SFP_DA_CORE1 - chip-specific
859 * 5 SFP_SR/LR_CORE0 - chip-specific
860 * 6 SFP_SR/LR_CORE1 - chip-specific
861 * 7 SFP_act_lmt_DA_CORE0 - chip-specific
862 * 8 SFP_act_lmt_DA_CORE1 - chip-specific
863 * 9 SFP_1g_cu_CORE0 - chip-specific
864 * 10 SFP_1g_cu_CORE1 - chip-specific
865 * 11 SFP_1g_sx_CORE0 - chip-specific
866 * 12 SFP_1g_sx_CORE1 - chip-specific
868 if (cable_tech & TXGBE_SFF_CABLE_DA_PASSIVE) {
869 if (hw->bus.lan_id == 0)
870 hw->phy.sfp_type = txgbe_sfp_type_da_cu_core0;
872 hw->phy.sfp_type = txgbe_sfp_type_da_cu_core1;
873 } else if (cable_tech & TXGBE_SFF_CABLE_DA_ACTIVE) {
874 err = hw->phy.read_i2c_eeprom(hw,
875 TXGBE_SFF_CABLE_SPEC_COMP, &cable_spec);
878 if (cable_spec & TXGBE_SFF_DA_SPEC_ACTIVE_LIMITING) {
879 hw->phy.sfp_type = (hw->bus.lan_id == 0
880 ? txgbe_sfp_type_da_act_lmt_core0
881 : txgbe_sfp_type_da_act_lmt_core1);
883 hw->phy.sfp_type = txgbe_sfp_type_unknown;
885 } else if (comp_codes_10g &
886 (TXGBE_SFF_10GBASESR_CAPABLE |
887 TXGBE_SFF_10GBASELR_CAPABLE)) {
888 hw->phy.sfp_type = (hw->bus.lan_id == 0
889 ? txgbe_sfp_type_srlr_core0
890 : txgbe_sfp_type_srlr_core1);
891 } else if (comp_codes_1g & TXGBE_SFF_1GBASET_CAPABLE) {
892 hw->phy.sfp_type = (hw->bus.lan_id == 0
893 ? txgbe_sfp_type_1g_cu_core0
894 : txgbe_sfp_type_1g_cu_core1);
895 } else if (comp_codes_1g & TXGBE_SFF_1GBASESX_CAPABLE) {
896 hw->phy.sfp_type = (hw->bus.lan_id == 0
897 ? txgbe_sfp_type_1g_sx_core0
898 : txgbe_sfp_type_1g_sx_core1);
899 } else if (comp_codes_1g & TXGBE_SFF_1GBASELX_CAPABLE) {
900 hw->phy.sfp_type = (hw->bus.lan_id == 0
901 ? txgbe_sfp_type_1g_lx_core0
902 : txgbe_sfp_type_1g_lx_core1);
904 hw->phy.sfp_type = txgbe_sfp_type_unknown;
907 if (hw->phy.sfp_type != stored_sfp_type)
908 hw->phy.sfp_setup_needed = true;
910 /* Determine if the SFP+ PHY is dual speed or not. */
911 hw->phy.multispeed_fiber = false;
912 if (((comp_codes_1g & TXGBE_SFF_1GBASESX_CAPABLE) &&
913 (comp_codes_10g & TXGBE_SFF_10GBASESR_CAPABLE)) ||
914 ((comp_codes_1g & TXGBE_SFF_1GBASELX_CAPABLE) &&
915 (comp_codes_10g & TXGBE_SFF_10GBASELR_CAPABLE)))
916 hw->phy.multispeed_fiber = true;
918 /* Determine PHY vendor */
919 if (hw->phy.type != txgbe_phy_nl) {
920 hw->phy.id = identifier;
921 err = hw->phy.read_i2c_eeprom(hw,
922 TXGBE_SFF_VENDOR_OUI_BYTE0, &oui_bytes[0]);
926 err = hw->phy.read_i2c_eeprom(hw,
927 TXGBE_SFF_VENDOR_OUI_BYTE1, &oui_bytes[1]);
931 err = hw->phy.read_i2c_eeprom(hw,
932 TXGBE_SFF_VENDOR_OUI_BYTE2, &oui_bytes[2]);
936 vendor_oui = ((u32)oui_bytes[0] << 24) |
937 ((u32)oui_bytes[1] << 16) |
938 ((u32)oui_bytes[2] << 8);
939 switch (vendor_oui) {
940 case TXGBE_SFF_VENDOR_OUI_TYCO:
941 if (cable_tech & TXGBE_SFF_CABLE_DA_PASSIVE)
942 hw->phy.type = txgbe_phy_sfp_tyco_passive;
944 case TXGBE_SFF_VENDOR_OUI_FTL:
945 if (cable_tech & TXGBE_SFF_CABLE_DA_ACTIVE)
946 hw->phy.type = txgbe_phy_sfp_ftl_active;
948 hw->phy.type = txgbe_phy_sfp_ftl;
950 case TXGBE_SFF_VENDOR_OUI_AVAGO:
951 hw->phy.type = txgbe_phy_sfp_avago;
953 case TXGBE_SFF_VENDOR_OUI_INTEL:
954 hw->phy.type = txgbe_phy_sfp_intel;
957 if (cable_tech & TXGBE_SFF_CABLE_DA_PASSIVE)
958 hw->phy.type = txgbe_phy_sfp_unknown_passive;
959 else if (cable_tech & TXGBE_SFF_CABLE_DA_ACTIVE)
960 hw->phy.type = txgbe_phy_sfp_unknown_active;
962 hw->phy.type = txgbe_phy_sfp_unknown;
967 /* Allow any DA cable vendor */
968 if (cable_tech & (TXGBE_SFF_CABLE_DA_PASSIVE |
969 TXGBE_SFF_CABLE_DA_ACTIVE)) {
973 /* Verify supported 1G SFP modules */
974 if (comp_codes_10g == 0 &&
975 !(hw->phy.sfp_type == txgbe_sfp_type_1g_cu_core1 ||
976 hw->phy.sfp_type == txgbe_sfp_type_1g_cu_core0 ||
977 hw->phy.sfp_type == txgbe_sfp_type_1g_lx_core0 ||
978 hw->phy.sfp_type == txgbe_sfp_type_1g_lx_core1 ||
979 hw->phy.sfp_type == txgbe_sfp_type_1g_sx_core0 ||
980 hw->phy.sfp_type == txgbe_sfp_type_1g_sx_core1)) {
981 hw->phy.type = txgbe_phy_sfp_unsupported;
982 return TXGBE_ERR_SFP_NOT_SUPPORTED;
985 hw->mac.get_device_caps(hw, &enforce_sfp);
986 if (!(enforce_sfp & TXGBE_DEVICE_CAPS_ALLOW_ANY_SFP) &&
987 !hw->allow_unsupported_sfp &&
988 !(hw->phy.sfp_type == txgbe_sfp_type_1g_cu_core0 ||
989 hw->phy.sfp_type == txgbe_sfp_type_1g_cu_core1 ||
990 hw->phy.sfp_type == txgbe_sfp_type_1g_lx_core0 ||
991 hw->phy.sfp_type == txgbe_sfp_type_1g_lx_core1 ||
992 hw->phy.sfp_type == txgbe_sfp_type_1g_sx_core0 ||
993 hw->phy.sfp_type == txgbe_sfp_type_1g_sx_core1)) {
994 DEBUGOUT("SFP+ module not supported\n");
995 hw->phy.type = txgbe_phy_sfp_unsupported;
996 return TXGBE_ERR_SFP_NOT_SUPPORTED;
1003 * txgbe_identify_qsfp_module - Identifies QSFP modules
1004 * @hw: pointer to hardware structure
1006 * Searches for and identifies the QSFP module and assigns appropriate PHY type
1008 s32 txgbe_identify_qsfp_module(struct txgbe_hw *hw)
1010 s32 err = TXGBE_ERR_PHY_ADDR_INVALID;
1012 enum txgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
1014 u8 comp_codes_1g = 0;
1015 u8 comp_codes_10g = 0;
1016 u8 oui_bytes[3] = {0, 0, 0};
1017 u16 enforce_sfp = 0;
1019 u8 cable_length = 0;
1021 bool active_cable = false;
1023 DEBUGFUNC("txgbe_identify_qsfp_module");
1025 if (hw->phy.media_type != txgbe_media_type_fiber_qsfp) {
1026 hw->phy.sfp_type = txgbe_sfp_type_not_present;
1027 err = TXGBE_ERR_SFP_NOT_PRESENT;
1031 err = hw->phy.read_i2c_eeprom(hw, TXGBE_SFF_IDENTIFIER,
1035 hw->phy.sfp_type = txgbe_sfp_type_not_present;
1037 hw->phy.type = txgbe_phy_unknown;
1038 return TXGBE_ERR_SFP_NOT_PRESENT;
1040 if (identifier != TXGBE_SFF_IDENTIFIER_QSFP_PLUS) {
1041 hw->phy.type = txgbe_phy_sfp_unsupported;
1042 err = TXGBE_ERR_SFP_NOT_SUPPORTED;
1046 hw->phy.id = identifier;
1048 err = hw->phy.read_i2c_eeprom(hw, TXGBE_SFF_QSFP_10GBE_COMP,
1054 err = hw->phy.read_i2c_eeprom(hw, TXGBE_SFF_QSFP_1GBE_COMP,
1060 if (comp_codes_10g & TXGBE_SFF_QSFP_DA_PASSIVE_CABLE) {
1061 hw->phy.type = txgbe_phy_qsfp_unknown_passive;
1062 if (hw->bus.lan_id == 0)
1063 hw->phy.sfp_type = txgbe_sfp_type_da_cu_core0;
1065 hw->phy.sfp_type = txgbe_sfp_type_da_cu_core1;
1066 } else if (comp_codes_10g & (TXGBE_SFF_10GBASESR_CAPABLE |
1067 TXGBE_SFF_10GBASELR_CAPABLE)) {
1068 if (hw->bus.lan_id == 0)
1069 hw->phy.sfp_type = txgbe_sfp_type_srlr_core0;
1071 hw->phy.sfp_type = txgbe_sfp_type_srlr_core1;
1073 if (comp_codes_10g & TXGBE_SFF_QSFP_DA_ACTIVE_CABLE)
1074 active_cable = true;
1076 if (!active_cable) {
1077 hw->phy.read_i2c_eeprom(hw,
1078 TXGBE_SFF_QSFP_CONNECTOR,
1081 hw->phy.read_i2c_eeprom(hw,
1082 TXGBE_SFF_QSFP_CABLE_LENGTH,
1085 hw->phy.read_i2c_eeprom(hw,
1086 TXGBE_SFF_QSFP_DEVICE_TECH,
1090 TXGBE_SFF_QSFP_CONNECTOR_NOT_SEPARABLE &&
1092 ((device_tech >> 4) ==
1093 TXGBE_SFF_QSFP_TRANSMITTER_850NM_VCSEL))
1094 active_cable = true;
1098 hw->phy.type = txgbe_phy_qsfp_unknown_active;
1099 if (hw->bus.lan_id == 0)
1101 txgbe_sfp_type_da_act_lmt_core0;
1104 txgbe_sfp_type_da_act_lmt_core1;
1106 /* unsupported module type */
1107 hw->phy.type = txgbe_phy_sfp_unsupported;
1108 err = TXGBE_ERR_SFP_NOT_SUPPORTED;
1113 if (hw->phy.sfp_type != stored_sfp_type)
1114 hw->phy.sfp_setup_needed = true;
1116 /* Determine if the QSFP+ PHY is dual speed or not. */
1117 hw->phy.multispeed_fiber = false;
1118 if (((comp_codes_1g & TXGBE_SFF_1GBASESX_CAPABLE) &&
1119 (comp_codes_10g & TXGBE_SFF_10GBASESR_CAPABLE)) ||
1120 ((comp_codes_1g & TXGBE_SFF_1GBASELX_CAPABLE) &&
1121 (comp_codes_10g & TXGBE_SFF_10GBASELR_CAPABLE)))
1122 hw->phy.multispeed_fiber = true;
1124 /* Determine PHY vendor for optical modules */
1125 if (comp_codes_10g & (TXGBE_SFF_10GBASESR_CAPABLE |
1126 TXGBE_SFF_10GBASELR_CAPABLE)) {
1127 err = hw->phy.read_i2c_eeprom(hw,
1128 TXGBE_SFF_QSFP_VENDOR_OUI_BYTE0,
1134 err = hw->phy.read_i2c_eeprom(hw,
1135 TXGBE_SFF_QSFP_VENDOR_OUI_BYTE1,
1141 err = hw->phy.read_i2c_eeprom(hw,
1142 TXGBE_SFF_QSFP_VENDOR_OUI_BYTE2,
1149 ((oui_bytes[0] << 24) |
1150 (oui_bytes[1] << 16) |
1151 (oui_bytes[2] << 8));
1153 if (vendor_oui == TXGBE_SFF_VENDOR_OUI_INTEL)
1154 hw->phy.type = txgbe_phy_qsfp_intel;
1156 hw->phy.type = txgbe_phy_qsfp_unknown;
1158 hw->mac.get_device_caps(hw, &enforce_sfp);
1159 if (!(enforce_sfp & TXGBE_DEVICE_CAPS_ALLOW_ANY_SFP)) {
1160 /* Make sure we're a supported PHY type */
1161 if (hw->phy.type == txgbe_phy_qsfp_intel) {
1164 if (hw->allow_unsupported_sfp) {
1165 DEBUGOUT("WARNING: Wangxun (R) Network Connections are quality tested using Wangxun (R) Ethernet Optics. "
1166 "Using untested modules is not supported and may cause unstable operation or damage to the module or the adapter. "
1167 "Wangxun Corporation is not responsible for any harm caused by using untested modules.\n");
1170 DEBUGOUT("QSFP module not supported\n");
1172 txgbe_phy_sfp_unsupported;
1173 err = TXGBE_ERR_SFP_NOT_SUPPORTED;
1186 * txgbe_read_i2c_eeprom - Reads 8 bit EEPROM word over I2C interface
1187 * @hw: pointer to hardware structure
1188 * @byte_offset: EEPROM byte offset to read
1189 * @eeprom_data: value read
1191 * Performs byte read operation to SFP module's EEPROM over I2C interface.
1193 s32 txgbe_read_i2c_eeprom(struct txgbe_hw *hw, u8 byte_offset,
1196 DEBUGFUNC("txgbe_read_i2c_eeprom");
1198 return hw->phy.read_i2c_byte(hw, byte_offset,
1199 TXGBE_I2C_EEPROM_DEV_ADDR,
1204 * txgbe_read_i2c_sff8472 - Reads 8 bit word over I2C interface
1205 * @hw: pointer to hardware structure
1206 * @byte_offset: byte offset at address 0xA2
1207 * @sff8472_data: value read
1209 * Performs byte read operation to SFP module's SFF-8472 data over I2C
1211 s32 txgbe_read_i2c_sff8472(struct txgbe_hw *hw, u8 byte_offset,
1214 return hw->phy.read_i2c_byte(hw, byte_offset,
1215 TXGBE_I2C_EEPROM_DEV_ADDR2,
1220 * txgbe_write_i2c_eeprom - Writes 8 bit EEPROM word over I2C interface
1221 * @hw: pointer to hardware structure
1222 * @byte_offset: EEPROM byte offset to write
1223 * @eeprom_data: value to write
1225 * Performs byte write operation to SFP module's EEPROM over I2C interface.
1227 s32 txgbe_write_i2c_eeprom(struct txgbe_hw *hw, u8 byte_offset,
1230 DEBUGFUNC("txgbe_write_i2c_eeprom");
1232 return hw->phy.write_i2c_byte(hw, byte_offset,
1233 TXGBE_I2C_EEPROM_DEV_ADDR,
1238 * txgbe_read_i2c_byte_unlocked - Reads 8 bit word over I2C
1239 * @hw: pointer to hardware structure
1240 * @byte_offset: byte offset to read
1241 * @dev_addr: address to read from
1244 * Performs byte read operation to SFP module's EEPROM over I2C interface at
1245 * a specified device address.
1247 s32 txgbe_read_i2c_byte_unlocked(struct txgbe_hw *hw, u8 byte_offset,
1248 u8 dev_addr, u8 *data)
1250 UNREFERENCED_PARAMETER(dev_addr);
1252 DEBUGFUNC("txgbe_read_i2c_byte");
1254 txgbe_i2c_start(hw);
1257 if (!po32m(hw, TXGBE_I2CICR, TXGBE_I2CICR_TXEMPTY,
1258 TXGBE_I2CICR_TXEMPTY, NULL, 100, 100)) {
1259 return -TERR_TIMEOUT;
1263 wr32(hw, TXGBE_I2CDATA,
1264 byte_offset | TXGBE_I2CDATA_STOP);
1265 wr32(hw, TXGBE_I2CDATA, TXGBE_I2CDATA_READ);
1267 /* wait for read complete */
1268 if (!po32m(hw, TXGBE_I2CICR, TXGBE_I2CICR_RXFULL,
1269 TXGBE_I2CICR_RXFULL, NULL, 100, 100)) {
1270 return -TERR_TIMEOUT;
1275 *data = 0xFF & rd32(hw, TXGBE_I2CDATA);
1281 * txgbe_read_i2c_byte - Reads 8 bit word over I2C
1282 * @hw: pointer to hardware structure
1283 * @byte_offset: byte offset to read
1284 * @dev_addr: address to read from
1287 * Performs byte read operation to SFP module's EEPROM over I2C interface at
1288 * a specified device address.
1290 s32 txgbe_read_i2c_byte(struct txgbe_hw *hw, u8 byte_offset,
1291 u8 dev_addr, u8 *data)
1293 u32 swfw_mask = hw->phy.phy_semaphore_mask;
1296 if (hw->mac.acquire_swfw_sync(hw, swfw_mask))
1297 return TXGBE_ERR_SWFW_SYNC;
1298 err = txgbe_read_i2c_byte_unlocked(hw, byte_offset, dev_addr, data);
1299 hw->mac.release_swfw_sync(hw, swfw_mask);
1304 * txgbe_write_i2c_byte_unlocked - Writes 8 bit word over I2C
1305 * @hw: pointer to hardware structure
1306 * @byte_offset: byte offset to write
1307 * @dev_addr: address to write to
1308 * @data: value to write
1310 * Performs byte write operation to SFP module's EEPROM over I2C interface at
1311 * a specified device address.
1313 s32 txgbe_write_i2c_byte_unlocked(struct txgbe_hw *hw, u8 byte_offset,
1314 u8 dev_addr, u8 data)
1316 UNREFERENCED_PARAMETER(dev_addr);
1318 DEBUGFUNC("txgbe_write_i2c_byte");
1320 txgbe_i2c_start(hw);
1323 if (!po32m(hw, TXGBE_I2CICR, TXGBE_I2CICR_TXEMPTY,
1324 TXGBE_I2CICR_TXEMPTY, NULL, 100, 100)) {
1325 return -TERR_TIMEOUT;
1328 wr32(hw, TXGBE_I2CDATA, byte_offset | TXGBE_I2CDATA_STOP);
1329 wr32(hw, TXGBE_I2CDATA, data | TXGBE_I2CDATA_WRITE);
1331 /* wait for write complete */
1332 if (!po32m(hw, TXGBE_I2CICR, TXGBE_I2CICR_RXFULL,
1333 TXGBE_I2CICR_RXFULL, NULL, 100, 100)) {
1334 return -TERR_TIMEOUT;
1342 * txgbe_write_i2c_byte - Writes 8 bit word over I2C
1343 * @hw: pointer to hardware structure
1344 * @byte_offset: byte offset to write
1345 * @dev_addr: address to write to
1346 * @data: value to write
1348 * Performs byte write operation to SFP module's EEPROM over I2C interface at
1349 * a specified device address.
1351 s32 txgbe_write_i2c_byte(struct txgbe_hw *hw, u8 byte_offset,
1352 u8 dev_addr, u8 data)
1354 u32 swfw_mask = hw->phy.phy_semaphore_mask;
1357 if (hw->mac.acquire_swfw_sync(hw, swfw_mask))
1358 return TXGBE_ERR_SWFW_SYNC;
1359 err = txgbe_write_i2c_byte_unlocked(hw, byte_offset, dev_addr, data);
1360 hw->mac.release_swfw_sync(hw, swfw_mask);
1366 * txgbe_i2c_start - Sets I2C start condition
1367 * @hw: pointer to hardware structure
1369 * Sets I2C start condition (High -> Low on SDA while SCL is High)
1371 static void txgbe_i2c_start(struct txgbe_hw *hw)
1373 DEBUGFUNC("txgbe_i2c_start");
1375 wr32(hw, TXGBE_I2CENA, 0);
1377 wr32(hw, TXGBE_I2CCON,
1378 (TXGBE_I2CCON_MENA |
1379 TXGBE_I2CCON_SPEED(1) |
1380 TXGBE_I2CCON_RESTART |
1381 TXGBE_I2CCON_SDIA));
1382 wr32(hw, TXGBE_I2CTAR, TXGBE_I2C_SLAVEADDR);
1383 wr32(hw, TXGBE_I2CSSSCLHCNT, 600);
1384 wr32(hw, TXGBE_I2CSSSCLLCNT, 600);
1385 wr32(hw, TXGBE_I2CRXTL, 0); /* 1byte for rx full signal */
1386 wr32(hw, TXGBE_I2CTXTL, 4);
1387 wr32(hw, TXGBE_I2CSCLTMOUT, 0xFFFFFF);
1388 wr32(hw, TXGBE_I2CSDATMOUT, 0xFFFFFF);
1390 wr32(hw, TXGBE_I2CICM, 0);
1391 wr32(hw, TXGBE_I2CENA, 1);
1395 * txgbe_i2c_stop - Sets I2C stop condition
1396 * @hw: pointer to hardware structure
1398 * Sets I2C stop condition (Low -> High on SDA while SCL is High)
1400 static void txgbe_i2c_stop(struct txgbe_hw *hw)
1402 DEBUGFUNC("txgbe_i2c_stop");
1404 /* wait for completion */
1405 if (!po32m(hw, TXGBE_I2CSTAT, TXGBE_I2CSTAT_MST,
1406 0, NULL, 100, 100)) {
1407 DEBUGFUNC("i2c stop timeout.");
1410 wr32(hw, TXGBE_I2CENA, 0);
1414 txgbe_set_sgmii_an37_ability(struct txgbe_hw *hw)
1418 wr32_epcs(hw, VR_XS_OR_PCS_MMD_DIGI_CTL1, 0x3002);
1419 wr32_epcs(hw, SR_MII_MMD_AN_CTL, 0x0105);
1420 wr32_epcs(hw, SR_MII_MMD_DIGI_CTL, 0x0200);
1421 value = rd32_epcs(hw, SR_MII_MMD_CTL);
1422 value = (value & ~0x1200) | (0x1 << 12) | (0x1 << 9);
1423 wr32_epcs(hw, SR_MII_MMD_CTL, value);
1427 txgbe_set_link_to_kr(struct txgbe_hw *hw, bool autoneg)
1433 /* 1. Wait xpcs power-up good */
1434 for (i = 0; i < 100; i++) {
1435 if ((rd32_epcs(hw, VR_XS_OR_PCS_MMD_DIGI_STATUS) &
1436 VR_XS_OR_PCS_MMD_DIGI_STATUS_PSEQ_MASK) ==
1437 VR_XS_OR_PCS_MMD_DIGI_STATUS_PSEQ_POWER_GOOD)
1442 err = TXGBE_ERR_XPCS_POWER_UP_FAILED;
1445 BP_LOG("It is set to kr.\n");
1447 wr32_epcs(hw, VR_AN_INTR_MSK, 0x7);
1448 wr32_epcs(hw, TXGBE_PHY_TX_POWER_ST_CTL, 0x00FC);
1449 wr32_epcs(hw, TXGBE_PHY_RX_POWER_ST_CTL, 0x00FC);
1452 /* 2. Disable xpcs AN-73 */
1453 wr32_epcs(hw, SR_AN_CTRL,
1454 SR_AN_CTRL_AN_EN | SR_AN_CTRL_EXT_NP);
1456 wr32_epcs(hw, VR_AN_KR_MODE_CL, VR_AN_KR_MODE_CL_PDET);
1458 if (!(hw->devarg.auto_neg == 1)) {
1459 wr32_epcs(hw, SR_AN_CTRL, 0);
1460 wr32_epcs(hw, VR_AN_KR_MODE_CL, 0);
1462 if (hw->devarg.present == 1) {
1463 value = rd32_epcs(hw, TXGBE_PHY_TX_EQ_CTL1);
1464 value |= TXGBE_PHY_TX_EQ_CTL1_DEF;
1465 wr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL1, value);
1467 if (hw->devarg.poll == 1) {
1468 wr32_epcs(hw, VR_PMA_KRTR_TIMER_CTRL0,
1469 VR_PMA_KRTR_TIMER_MAX_WAIT);
1470 wr32_epcs(hw, VR_PMA_KRTR_TIMER_CTRL2, 0xA697);
1473 /* 3. Set VR_XS_PMA_Gen5_12G_MPLLA_CTRL3 Register
1474 * Bit[10:0](MPLLA_BANDWIDTH) = 11'd123 (default: 11'd16)
1476 wr32_epcs(hw, TXGBE_PHY_MPLLA_CTL3,
1477 TXGBE_PHY_MPLLA_CTL3_MULTIPLIER_BW_10GBASER_KR);
1479 /* 4. Set VR_XS_PMA_Gen5_12G_MISC_CTRL0 Register
1480 * Bit[12:8](RX_VREF_CTRL) = 5'hF (default: 5'h11)
1482 wr32_epcs(hw, TXGBE_PHY_MISC_CTL0, 0xCF00);
1484 /* 5. Set VR_XS_PMA_Gen5_12G_RX_EQ_CTRL0 Register
1485 * Bit[15:8](VGA1/2_GAIN_0) = 8'h77
1486 * Bit[7:5](CTLE_POLE_0) = 3'h2
1487 * Bit[4:0](CTLE_BOOST_0) = 4'hA
1489 wr32_epcs(hw, TXGBE_PHY_RX_EQ_CTL0, 0x774A);
1491 /* 6. Set VR_MII_Gen5_12G_RX_GENCTRL3 Register
1492 * Bit[2:0](LOS_TRSHLD_0) = 3'h4 (default: 3)
1494 wr32_epcs(hw, TXGBE_PHY_RX_GEN_CTL3, 0x0004);
1496 /* 7. Initialize the mode by setting VR XS or PCS MMD Digital
1497 * Control1 Register Bit[15](VR_RST)
1499 wr32_epcs(hw, VR_XS_OR_PCS_MMD_DIGI_CTL1, 0xA000);
1501 /* Wait phy initialization done */
1502 for (i = 0; i < 100; i++) {
1504 VR_XS_OR_PCS_MMD_DIGI_CTL1) &
1505 VR_XS_OR_PCS_MMD_DIGI_CTL1_VR_RST) == 0)
1510 err = TXGBE_ERR_PHY_INIT_NOT_DONE;
1514 wr32_epcs(hw, VR_AN_KR_MODE_CL, 0x1);
1521 txgbe_set_link_to_kx4(struct txgbe_hw *hw, bool autoneg)
1527 /* Check link status, if already set, skip setting it again */
1528 if (hw->link_status == TXGBE_LINK_STATUS_KX4)
1531 BP_LOG("It is set to kx4.\n");
1532 wr32_epcs(hw, TXGBE_PHY_TX_POWER_ST_CTL, 0);
1533 wr32_epcs(hw, TXGBE_PHY_RX_POWER_ST_CTL, 0);
1535 /* 1. Wait xpcs power-up good */
1536 for (i = 0; i < 100; i++) {
1537 if ((rd32_epcs(hw, VR_XS_OR_PCS_MMD_DIGI_STATUS) &
1538 VR_XS_OR_PCS_MMD_DIGI_STATUS_PSEQ_MASK) ==
1539 VR_XS_OR_PCS_MMD_DIGI_STATUS_PSEQ_POWER_GOOD)
1544 err = TXGBE_ERR_XPCS_POWER_UP_FAILED;
1548 wr32m(hw, TXGBE_MACTXCFG, TXGBE_MACTXCFG_TXE,
1549 ~TXGBE_MACTXCFG_TXE);
1551 /* 2. Disable xpcs AN-73 */
1553 wr32_epcs(hw, SR_AN_CTRL, 0x0);
1555 wr32_epcs(hw, SR_AN_CTRL, 0x3000);
1557 /* Disable PHY MPLLA for eth mode change(after ECO) */
1558 wr32_ephy(hw, 0x4, 0x250A);
1562 /* Set the eth change_mode bit first in mis_rst register
1563 * for corresponding LAN port
1565 wr32(hw, TXGBE_RST, TXGBE_RST_ETH(hw->bus.lan_id));
1567 /* Set SR PCS Control2 Register Bits[1:0] = 2'b01
1568 * PCS_TYPE_SEL: non KR
1570 wr32_epcs(hw, SR_XS_PCS_CTRL2,
1571 SR_PCS_CTRL2_TYPE_SEL_X);
1573 /* Set SR PMA MMD Control1 Register Bit[13] = 1'b1
1576 wr32_epcs(hw, SR_PMA_CTRL1,
1577 SR_PMA_CTRL1_SS13_KX4);
1579 value = (0xf5f0 & ~0x7F0) | (0x5 << 8) | (0x7 << 5) | 0xF0;
1580 wr32_epcs(hw, TXGBE_PHY_TX_GENCTRL1, value);
1582 if ((hw->subsystem_device_id & 0xFF) == TXGBE_DEV_ID_MAC_XAUI)
1583 wr32_epcs(hw, TXGBE_PHY_MISC_CTL0, 0xCF00);
1585 wr32_epcs(hw, TXGBE_PHY_MISC_CTL0, 0x4F00);
1587 for (i = 0; i < 4; i++) {
1589 value = (0x45 & ~0xFFFF) | (0x7 << 12) |
1592 value = (0xff06 & ~0xFFFF) | (0x7 << 12) |
1594 wr32_epcs(hw, TXGBE_PHY_RX_EQ_CTL0 + i, value);
1597 value = 0x0 & ~0x7777;
1598 wr32_epcs(hw, TXGBE_PHY_RX_EQ_ATT_LVL0, value);
1600 wr32_epcs(hw, TXGBE_PHY_DFE_TAP_CTL0, 0x0);
1602 value = (0x6db & ~0xFFF) | (0x1 << 9) | (0x1 << 6) | (0x1 << 3) | 0x1;
1603 wr32_epcs(hw, TXGBE_PHY_RX_GEN_CTL3, value);
1605 /* Set VR XS, PMA, or MII Gen5 12G PHY MPLLA
1606 * Control 0 Register Bit[7:0] = 8'd40 //MPLLA_MULTIPLIER
1608 wr32_epcs(hw, TXGBE_PHY_MPLLA_CTL0,
1609 TXGBE_PHY_MPLLA_CTL0_MULTIPLIER_OTHER);
1611 /* Set VR XS, PMA or MII Gen5 12G PHY MPLLA
1612 * Control 3 Register Bit[10:0] = 11'd86 //MPLLA_BANDWIDTH
1614 wr32_epcs(hw, TXGBE_PHY_MPLLA_CTL3,
1615 TXGBE_PHY_MPLLA_CTL3_MULTIPLIER_BW_OTHER);
1617 /* Set VR XS, PMA, or MII Gen5 12G PHY VCO
1618 * Calibration Load 0 Register Bit[12:0] = 13'd1360 //VCO_LD_VAL_0
1620 wr32_epcs(hw, TXGBE_PHY_VCO_CAL_LD0,
1621 TXGBE_PHY_VCO_CAL_LD0_OTHER);
1623 /* Set VR XS, PMA, or MII Gen5 12G PHY VCO
1624 * Calibration Load 1 Register Bit[12:0] = 13'd1360 //VCO_LD_VAL_1
1626 wr32_epcs(hw, TXGBE_PHY_VCO_CAL_LD1,
1627 TXGBE_PHY_VCO_CAL_LD0_OTHER);
1629 /* Set VR XS, PMA, or MII Gen5 12G PHY VCO
1630 * Calibration Load 2 Register Bit[12:0] = 13'd1360 //VCO_LD_VAL_2
1632 wr32_epcs(hw, TXGBE_PHY_VCO_CAL_LD2,
1633 TXGBE_PHY_VCO_CAL_LD0_OTHER);
1634 /* Set VR XS, PMA, or MII Gen5 12G PHY VCO
1635 * Calibration Load 3 Register Bit[12:0] = 13'd1360 //VCO_LD_VAL_3
1637 wr32_epcs(hw, TXGBE_PHY_VCO_CAL_LD3,
1638 TXGBE_PHY_VCO_CAL_LD0_OTHER);
1639 /* Set VR XS, PMA, or MII Gen5 12G PHY VCO
1640 * Calibration Reference 0 Register Bit[5:0] = 6'd34 //VCO_REF_LD_0/1
1642 wr32_epcs(hw, TXGBE_PHY_VCO_CAL_REF0, 0x2222);
1644 /* Set VR XS, PMA, or MII Gen5 12G PHY VCO
1645 * Calibration Reference 1 Register Bit[5:0] = 6'd34 //VCO_REF_LD_2/3
1647 wr32_epcs(hw, TXGBE_PHY_VCO_CAL_REF1, 0x2222);
1649 /* Set VR XS, PMA, or MII Gen5 12G PHY AFE-DFE
1650 * Enable Register Bit[7:0] = 8'd0 //AFE_EN_0/3_1, DFE_EN_0/3_1
1652 wr32_epcs(hw, TXGBE_PHY_AFE_DFE_ENABLE, 0x0);
1654 /* Set VR XS, PMA, or MII Gen5 12G PHY Rx
1655 * Equalization Control 4 Register Bit[3:0] = 4'd0 //CONT_ADAPT_0/3_1
1657 wr32_epcs(hw, TXGBE_PHY_RX_EQ_CTL, 0x00F0);
1659 /* Set VR XS, PMA, or MII Gen5 12G PHY Tx Rate
1660 * Control Register Bit[14:12], Bit[10:8], Bit[6:4], Bit[2:0],
1661 * all rates to 3'b010 //TX0/1/2/3_RATE
1663 wr32_epcs(hw, TXGBE_PHY_TX_RATE_CTL, 0x2222);
1665 /* Set VR XS, PMA, or MII Gen5 12G PHY Rx Rate
1666 * Control Register Bit[13:12], Bit[9:8], Bit[5:4], Bit[1:0],
1667 * all rates to 2'b10 //RX0/1/2/3_RATE
1669 wr32_epcs(hw, TXGBE_PHY_RX_RATE_CTL, 0x2222);
1671 /* Set VR XS, PMA, or MII Gen5 12G PHY Tx General
1672 * Control 2 Register Bit[15:8] = 2'b01 //TX0/1/2/3_WIDTH: 10bits
1674 wr32_epcs(hw, TXGBE_PHY_TX_GEN_CTL2, 0x5500);
1676 /* Set VR XS, PMA, or MII Gen5 12G PHY Rx General
1677 * Control 2 Register Bit[15:8] = 2'b01 //RX0/1/2/3_WIDTH: 10bits
1679 wr32_epcs(hw, TXGBE_PHY_RX_GEN_CTL2, 0x5500);
1681 /* Set VR XS, PMA, or MII Gen5 12G PHY MPLLA Control
1682 * 2 Register Bit[10:8] = 3'b010
1683 * MPLLA_DIV16P5_CLK_EN=0, MPLLA_DIV10_CLK_EN=1, MPLLA_DIV8_CLK_EN=0
1685 wr32_epcs(hw, TXGBE_PHY_MPLLA_CTL2,
1686 TXGBE_PHY_MPLLA_CTL2_DIV_CLK_EN_10);
1688 wr32_epcs(hw, 0x1f0000, 0x0);
1689 wr32_epcs(hw, 0x1f8001, 0x0);
1690 wr32_epcs(hw, SR_MII_MMD_DIGI_CTL, 0x0);
1692 /* 10. Initialize the mode by setting VR XS or PCS MMD Digital Control1
1693 * Register Bit[15](VR_RST)
1695 wr32_epcs(hw, VR_XS_OR_PCS_MMD_DIGI_CTL1, 0xA000);
1697 /* Wait phy initialization done */
1698 for (i = 0; i < 100; i++) {
1699 if ((rd32_epcs(hw, VR_XS_OR_PCS_MMD_DIGI_CTL1) &
1700 VR_XS_OR_PCS_MMD_DIGI_CTL1_VR_RST) == 0)
1705 /* If success, set link status */
1706 hw->link_status = TXGBE_LINK_STATUS_KX4;
1709 err = TXGBE_ERR_PHY_INIT_NOT_DONE;
1713 if (hw->fw_version <= TXGBE_FW_N_TXEQ) {
1714 value = (0x1804 & ~0x3F3F);
1715 wr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL0, value);
1717 value = (0x50 & ~0x7F) | 40 | (1 << 6);
1718 wr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL1, value);
1725 txgbe_set_link_to_kx(struct txgbe_hw *hw,
1734 /* Check link status, if already set, skip setting it again */
1735 if (hw->link_status == TXGBE_LINK_STATUS_KX)
1738 BP_LOG("It is set to kx. speed =0x%x\n", speed);
1739 wr32_epcs(hw, TXGBE_PHY_TX_POWER_ST_CTL, 0x00FC);
1740 wr32_epcs(hw, TXGBE_PHY_RX_POWER_ST_CTL, 0x00FC);
1742 /* 1. Wait xpcs power-up good */
1743 for (i = 0; i < 100; i++) {
1744 if ((rd32_epcs(hw, VR_XS_OR_PCS_MMD_DIGI_STATUS) &
1745 VR_XS_OR_PCS_MMD_DIGI_STATUS_PSEQ_MASK) ==
1746 VR_XS_OR_PCS_MMD_DIGI_STATUS_PSEQ_POWER_GOOD)
1751 err = TXGBE_ERR_XPCS_POWER_UP_FAILED;
1755 wr32m(hw, TXGBE_MACTXCFG, TXGBE_MACTXCFG_TXE,
1756 ~TXGBE_MACTXCFG_TXE);
1758 /* 2. Disable xpcs AN-73 */
1760 wr32_epcs(hw, SR_AN_CTRL, 0x0);
1762 wr32_epcs(hw, SR_AN_CTRL, 0x3000);
1764 /* Disable PHY MPLLA for eth mode change(after ECO) */
1765 wr32_ephy(hw, 0x4, 0x240A);
1769 /* Set the eth change_mode bit first in mis_rst register
1770 * for corresponding LAN port
1772 wr32(hw, TXGBE_RST, TXGBE_RST_ETH(hw->bus.lan_id));
1774 /* Set SR PCS Control2 Register Bits[1:0] = 2'b01
1775 * PCS_TYPE_SEL: non KR
1777 wr32_epcs(hw, SR_XS_PCS_CTRL2,
1778 SR_PCS_CTRL2_TYPE_SEL_X);
1780 /* Set SR PMA MMD Control1 Register Bit[13] = 1'b0
1783 wr32_epcs(hw, SR_PMA_CTRL1,
1784 SR_PMA_CTRL1_SS13_KX);
1786 /* Set SR MII MMD Control Register to corresponding speed: {Bit[6],
1787 * Bit[13]}=[2'b00,2'b01,2'b10]->[10M,100M,1G]
1789 if (speed == TXGBE_LINK_SPEED_100M_FULL)
1791 else if (speed == TXGBE_LINK_SPEED_1GB_FULL)
1793 else if (speed == TXGBE_LINK_SPEED_10M_FULL)
1795 wr32_epcs(hw, SR_MII_MMD_CTL,
1798 value = (0xf5f0 & ~0x710) | (0x5 << 8) | 0x10;
1799 wr32_epcs(hw, TXGBE_PHY_TX_GENCTRL1, value);
1801 if (hw->devarg.sgmii == 1)
1802 wr32_epcs(hw, TXGBE_PHY_MISC_CTL0, 0x4F00);
1804 wr32_epcs(hw, TXGBE_PHY_MISC_CTL0, 0xCF00);
1806 for (i = 0; i < 4; i++) {
1810 value = (0x45 & ~0xFFFF) | (0x7 << 12) |
1813 wr32_epcs(hw, TXGBE_PHY_RX_EQ_CTL0 + i, value);
1817 wr32_epcs(hw, TXGBE_PHY_RX_EQ_ATT_LVL0, value);
1819 wr32_epcs(hw, TXGBE_PHY_DFE_TAP_CTL0, 0x0);
1821 value = (0x6db & ~0x7) | 0x4;
1822 wr32_epcs(hw, TXGBE_PHY_RX_GEN_CTL3, value);
1824 /* Set VR XS, PMA, or MII Gen5 12G PHY MPLLA Control
1825 * 0 Register Bit[7:0] = 8'd32 //MPLLA_MULTIPLIER
1827 wr32_epcs(hw, TXGBE_PHY_MPLLA_CTL0,
1828 TXGBE_PHY_MPLLA_CTL0_MULTIPLIER_1GBASEX_KX);
1830 /* Set VR XS, PMA or MII Gen5 12G PHY MPLLA Control
1831 * 3 Register Bit[10:0] = 11'd70 //MPLLA_BANDWIDTH
1833 wr32_epcs(hw, TXGBE_PHY_MPLLA_CTL3,
1834 TXGBE_PHY_MPLLA_CTL3_MULTIPLIER_BW_1GBASEX_KX);
1836 /* Set VR XS, PMA, or MII Gen5 12G PHY VCO
1837 * Calibration Load 0 Register Bit[12:0] = 13'd1344 //VCO_LD_VAL_0
1839 wr32_epcs(hw, TXGBE_PHY_VCO_CAL_LD0,
1840 TXGBE_PHY_VCO_CAL_LD0_1GBASEX_KX);
1842 wr32_epcs(hw, TXGBE_PHY_VCO_CAL_LD1, 0x549);
1843 wr32_epcs(hw, TXGBE_PHY_VCO_CAL_LD2, 0x549);
1844 wr32_epcs(hw, TXGBE_PHY_VCO_CAL_LD3, 0x549);
1846 /* Set VR XS, PMA, or MII Gen5 12G PHY VCO
1847 * Calibration Reference 0 Register Bit[5:0] = 6'd42 //VCO_REF_LD_0
1849 wr32_epcs(hw, TXGBE_PHY_VCO_CAL_REF0,
1850 TXGBE_PHY_VCO_CAL_REF0_LD0_1GBASEX_KX);
1852 wr32_epcs(hw, TXGBE_PHY_VCO_CAL_REF1, 0x2929);
1854 /* Set VR XS, PMA, or MII Gen5 12G PHY AFE-DFE
1855 * Enable Register Bit[4], Bit[0] = 1'b0 //AFE_EN_0, DFE_EN_0
1857 wr32_epcs(hw, TXGBE_PHY_AFE_DFE_ENABLE,
1859 /* Set VR XS, PMA, or MII Gen5 12G PHY Rx
1860 * Equalization Control 4 Register Bit[0] = 1'b0 //CONT_ADAPT_0
1862 wr32_epcs(hw, TXGBE_PHY_RX_EQ_CTL,
1864 /* Set VR XS, PMA, or MII Gen5 12G PHY Tx Rate
1865 * Control Register Bit[2:0] = 3'b011 //TX0_RATE
1867 wr32_epcs(hw, TXGBE_PHY_TX_RATE_CTL,
1868 TXGBE_PHY_TX_RATE_CTL_TX0_RATE_1GBASEX_KX);
1870 /* Set VR XS, PMA, or MII Gen5 12G PHY Rx Rate
1871 * Control Register Bit[2:0] = 3'b011 //RX0_RATE
1873 wr32_epcs(hw, TXGBE_PHY_RX_RATE_CTL,
1874 TXGBE_PHY_RX_RATE_CTL_RX0_RATE_1GBASEX_KX);
1876 /* Set VR XS, PMA, or MII Gen5 12G PHY Tx General
1877 * Control 2 Register Bit[9:8] = 2'b01 //TX0_WIDTH: 10bits
1879 wr32_epcs(hw, TXGBE_PHY_TX_GEN_CTL2,
1880 TXGBE_PHY_TX_GEN_CTL2_TX0_WIDTH_OTHER);
1881 /* Set VR XS, PMA, or MII Gen5 12G PHY Rx General
1882 * Control 2 Register Bit[9:8] = 2'b01 //RX0_WIDTH: 10bits
1884 wr32_epcs(hw, TXGBE_PHY_RX_GEN_CTL2,
1885 TXGBE_PHY_RX_GEN_CTL2_RX0_WIDTH_OTHER);
1886 /* Set VR XS, PMA, or MII Gen5 12G PHY MPLLA Control
1887 * 2 Register Bit[10:8] = 3'b010 //MPLLA_DIV16P5_CLK_EN=0,
1888 * MPLLA_DIV10_CLK_EN=1, MPLLA_DIV8_CLK_EN=0
1890 wr32_epcs(hw, TXGBE_PHY_MPLLA_CTL2,
1891 TXGBE_PHY_MPLLA_CTL2_DIV_CLK_EN_10);
1893 /* VR MII MMD AN Control Register Bit[8] = 1'b1 //MII_CTRL
1894 * Set to 8bit MII (required in 10M/100M SGMII)
1896 wr32_epcs(hw, SR_MII_MMD_AN_CTL,
1899 /* 10. Initialize the mode by setting VR XS or PCS MMD Digital Control1
1900 * Register Bit[15](VR_RST)
1902 wr32_epcs(hw, VR_XS_OR_PCS_MMD_DIGI_CTL1, 0xA000);
1904 /* Wait phy initialization done */
1905 for (i = 0; i < 100; i++) {
1906 if ((rd32_epcs(hw, VR_XS_OR_PCS_MMD_DIGI_CTL1) &
1907 VR_XS_OR_PCS_MMD_DIGI_CTL1_VR_RST) == 0)
1912 /* If success, set link status */
1913 hw->link_status = TXGBE_LINK_STATUS_KX;
1916 err = TXGBE_ERR_PHY_INIT_NOT_DONE;
1920 if (hw->fw_version <= TXGBE_FW_N_TXEQ) {
1921 value = (0x1804 & ~0x3F3F) | (24 << 8) | 4;
1922 wr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL0, value);
1924 value = (0x50 & ~0x7F) | 16 | (1 << 6);
1925 wr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL1, value);
1932 txgbe_set_link_to_sfi(struct txgbe_hw *hw,
1939 /* Set the module link speed */
1940 hw->mac.set_rate_select_speed(hw, speed);
1941 /* 1. Wait xpcs power-up good */
1942 for (i = 0; i < 100; i++) {
1943 if ((rd32_epcs(hw, VR_XS_OR_PCS_MMD_DIGI_STATUS) &
1944 VR_XS_OR_PCS_MMD_DIGI_STATUS_PSEQ_MASK) ==
1945 VR_XS_OR_PCS_MMD_DIGI_STATUS_PSEQ_POWER_GOOD)
1950 err = TXGBE_ERR_XPCS_POWER_UP_FAILED;
1954 wr32m(hw, TXGBE_MACTXCFG, TXGBE_MACTXCFG_TXE,
1955 ~TXGBE_MACTXCFG_TXE);
1957 /* 2. Disable xpcs AN-73 */
1958 wr32_epcs(hw, SR_AN_CTRL, 0x0);
1960 /* Disable PHY MPLLA for eth mode change(after ECO) */
1961 wr32_ephy(hw, 0x4, 0x243A);
1964 /* Set the eth change_mode bit first in mis_rst register
1965 * for corresponding LAN port
1967 wr32(hw, TXGBE_RST, TXGBE_RST_ETH(hw->bus.lan_id));
1969 if (speed == TXGBE_LINK_SPEED_10GB_FULL) {
1970 /* Set SR PCS Control2 Register Bits[1:0] = 2'b00
1973 wr32_epcs(hw, SR_XS_PCS_CTRL2, 0);
1974 value = rd32_epcs(hw, SR_PMA_CTRL1);
1975 value = value | 0x2000;
1976 wr32_epcs(hw, SR_PMA_CTRL1, value);
1977 /* Set VR_XS_PMA_Gen5_12G_MPLLA_CTRL0 Register Bit[7:0] = 8'd33
1980 wr32_epcs(hw, TXGBE_PHY_MPLLA_CTL0, 0x0021);
1981 /* 3. Set VR_XS_PMA_Gen5_12G_MPLLA_CTRL3 Register
1982 * Bit[10:0](MPLLA_BANDWIDTH) = 11'd0
1984 wr32_epcs(hw, TXGBE_PHY_MPLLA_CTL3, 0);
1985 value = rd32_epcs(hw, TXGBE_PHY_TX_GENCTRL1);
1986 value = (value & ~0x700) | 0x500;
1987 wr32_epcs(hw, TXGBE_PHY_TX_GENCTRL1, value);
1988 /* 4. Set VR_XS_PMA_Gen5_12G_MISC_CTRL0 Register
1989 * Bit[12:8](RX_VREF_CTRL) = 5'hF
1991 wr32_epcs(hw, TXGBE_PHY_MISC_CTL0, 0xCF00);
1992 /* Set VR_XS_PMA_Gen5_12G_VCO_CAL_LD0 Register
1993 * Bit[12:0] = 13'd1353 //VCO_LD_VAL_0
1995 wr32_epcs(hw, TXGBE_PHY_VCO_CAL_LD0, 0x0549);
1996 /* Set VR_XS_PMA_Gen5_12G_VCO_CAL_REF0 Register
1997 * Bit[5:0] = 6'd41 //VCO_REF_LD_0
1999 wr32_epcs(hw, TXGBE_PHY_VCO_CAL_REF0, 0x0029);
2000 /* Set VR_XS_PMA_Gen5_12G_TX_RATE_CTRL Register
2001 * Bit[2:0] = 3'b000 //TX0_RATE
2003 wr32_epcs(hw, TXGBE_PHY_TX_RATE_CTL, 0);
2004 /* Set VR_XS_PMA_Gen5_12G_RX_RATE_CTRL Register
2005 * Bit[2:0] = 3'b000 //RX0_RATE
2007 wr32_epcs(hw, TXGBE_PHY_RX_RATE_CTL, 0);
2008 /* Set VR_XS_PMA_Gen5_12G_TX_GENCTRL2 Register Bit[9:8] = 2'b11
2011 wr32_epcs(hw, TXGBE_PHY_TX_GEN_CTL2, 0x0300);
2012 /* Set VR_XS_PMA_Gen5_12G_RX_GENCTRL2 Register Bit[9:8] = 2'b11
2015 wr32_epcs(hw, TXGBE_PHY_RX_GEN_CTL2, 0x0300);
2016 /* Set VR_XS_PMA_Gen5_12G_MPLLA_CTRL2 Register
2017 * Bit[10:8] = 3'b110
2018 * MPLLA_DIV16P5_CLK_EN=1
2019 * MPLLA_DIV10_CLK_EN=1
2020 * MPLLA_DIV8_CLK_EN=0
2022 wr32_epcs(hw, TXGBE_PHY_MPLLA_CTL2, 0x0600);
2024 if (hw->phy.sfp_type == txgbe_sfp_type_da_cu_core0 ||
2025 hw->phy.sfp_type == txgbe_sfp_type_da_cu_core1) {
2026 /* 7. Set VR_XS_PMA_Gen5_12G_RX_EQ_CTRL0 Register
2027 * Bit[15:8](VGA1/2_GAIN_0) = 8'h77
2028 * Bit[7:5](CTLE_POLE_0) = 3'h2
2029 * Bit[4:0](CTLE_BOOST_0) = 4'hF
2031 wr32_epcs(hw, TXGBE_PHY_RX_EQ_CTL0, 0x774F);
2034 /* 7. Set VR_XS_PMA_Gen5_12G_RX_EQ_CTRL0 Register
2035 * Bit[15:8](VGA1/2_GAIN_0) = 8'h00
2036 * Bit[7:5](CTLE_POLE_0) = 3'h2
2037 * Bit[4:0](CTLE_BOOST_0) = 4'hA
2039 value = rd32_epcs(hw, TXGBE_PHY_RX_EQ_CTL0);
2040 value = (value & ~0xFFFF) | (2 << 5) | 0x05;
2041 wr32_epcs(hw, TXGBE_PHY_RX_EQ_CTL0, value);
2043 value = rd32_epcs(hw, TXGBE_PHY_RX_EQ_ATT_LVL0);
2044 value = (value & ~0x7) | 0x0;
2045 wr32_epcs(hw, TXGBE_PHY_RX_EQ_ATT_LVL0, value);
2047 if (hw->phy.sfp_type == txgbe_sfp_type_da_cu_core0 ||
2048 hw->phy.sfp_type == txgbe_sfp_type_da_cu_core1) {
2049 /* 8. Set VR_XS_PMA_Gen5_12G_DFE_TAP_CTRL0 Register
2050 * Bit[7:0](DFE_TAP1_0) = 8'd20
2052 wr32_epcs(hw, TXGBE_PHY_DFE_TAP_CTL0, 0x0014);
2053 value = rd32_epcs(hw, TXGBE_PHY_AFE_DFE_ENABLE);
2054 value = (value & ~0x11) | 0x11;
2055 wr32_epcs(hw, TXGBE_PHY_AFE_DFE_ENABLE, value);
2057 /* 8. Set VR_XS_PMA_Gen5_12G_DFE_TAP_CTRL0 Register
2058 * Bit[7:0](DFE_TAP1_0) = 8'd20
2060 wr32_epcs(hw, TXGBE_PHY_DFE_TAP_CTL0, 0xBE);
2061 /* 9. Set VR_MII_Gen5_12G_AFE_DFE_EN_CTRL Register
2062 * Bit[4](DFE_EN_0) = 1'b0, Bit[0](AFE_EN_0) = 1'b0
2064 value = rd32_epcs(hw, TXGBE_PHY_AFE_DFE_ENABLE);
2065 value = (value & ~0x11) | 0x0;
2066 wr32_epcs(hw, TXGBE_PHY_AFE_DFE_ENABLE, value);
2068 value = rd32_epcs(hw, TXGBE_PHY_RX_EQ_CTL);
2069 value = value & ~0x1;
2070 wr32_epcs(hw, TXGBE_PHY_RX_EQ_CTL, value);
2072 /* Set SR PCS Control2 Register Bits[1:0] = 2'b00
2075 wr32_epcs(hw, SR_XS_PCS_CTRL2, 0x1);
2076 /* Set SR PMA MMD Control1 Register Bit[13] = 1'b0
2079 wr32_epcs(hw, SR_PMA_CTRL1, 0x0000);
2080 /* Set SR MII MMD Control Register to corresponding speed */
2081 wr32_epcs(hw, SR_MII_MMD_CTL, 0x0140);
2083 value = rd32_epcs(hw, TXGBE_PHY_TX_GENCTRL1);
2084 value = (value & ~0x710) | 0x500;
2085 wr32_epcs(hw, TXGBE_PHY_TX_GENCTRL1, value);
2086 /* 4. Set VR_XS_PMA_Gen5_12G_MISC_CTRL0 Register
2087 * Bit[12:8](RX_VREF_CTRL) = 5'hF
2089 wr32_epcs(hw, TXGBE_PHY_MISC_CTL0, 0xCF00);
2091 if (hw->phy.sfp_type == txgbe_sfp_type_da_cu_core0 ||
2092 hw->phy.sfp_type == txgbe_sfp_type_da_cu_core1) {
2093 wr32_epcs(hw, TXGBE_PHY_RX_EQ_CTL0, 0x774F);
2095 /* 7. Set VR_XS_PMA_Gen5_12G_RX_EQ_CTRL0 Register
2096 * Bit[15:8](VGA1/2_GAIN_0) = 8'h00
2097 * Bit[7:5](CTLE_POLE_0) = 3'h2
2098 * Bit[4:0](CTLE_BOOST_0) = 4'hA
2100 value = rd32_epcs(hw, TXGBE_PHY_RX_EQ_CTL0);
2101 value = (value & ~0xFFFF) | 0x7706;
2102 wr32_epcs(hw, TXGBE_PHY_RX_EQ_CTL0, value);
2104 value = rd32_epcs(hw, TXGBE_PHY_RX_EQ_ATT_LVL0);
2105 value = (value & ~0x7) | 0x0;
2106 wr32_epcs(hw, TXGBE_PHY_RX_EQ_ATT_LVL0, value);
2107 /* 8. Set VR_XS_PMA_Gen5_12G_DFE_TAP_CTRL0 Register
2108 * Bit[7:0](DFE_TAP1_0) = 8'd00
2110 wr32_epcs(hw, TXGBE_PHY_DFE_TAP_CTL0, 0x0);
2111 /* 9. Set VR_MII_Gen5_12G_AFE_DFE_EN_CTRL Register
2112 * Bit[4](DFE_EN_0) = 1'b0, Bit[0](AFE_EN_0) = 1'b0
2114 value = rd32_epcs(hw, TXGBE_PHY_RX_GEN_CTL3);
2115 value = (value & ~0x7) | 0x4;
2116 wr32_epcs(hw, TXGBE_PHY_RX_GEN_CTL3, value);
2117 wr32_epcs(hw, TXGBE_PHY_MPLLA_CTL0, 0x0020);
2118 wr32_epcs(hw, TXGBE_PHY_MPLLA_CTL3, 0x0046);
2119 wr32_epcs(hw, TXGBE_PHY_VCO_CAL_LD0, 0x0540);
2120 wr32_epcs(hw, TXGBE_PHY_VCO_CAL_REF0, 0x002A);
2121 wr32_epcs(hw, TXGBE_PHY_AFE_DFE_ENABLE, 0x0);
2122 wr32_epcs(hw, TXGBE_PHY_RX_EQ_CTL, 0x0010);
2123 wr32_epcs(hw, TXGBE_PHY_TX_RATE_CTL, 0x0003);
2124 wr32_epcs(hw, TXGBE_PHY_RX_RATE_CTL, 0x0003);
2125 wr32_epcs(hw, TXGBE_PHY_TX_GEN_CTL2, 0x0100);
2126 wr32_epcs(hw, TXGBE_PHY_RX_GEN_CTL2, 0x0100);
2127 wr32_epcs(hw, TXGBE_PHY_MPLLA_CTL2, 0x0200);
2128 wr32_epcs(hw, SR_MII_MMD_AN_CTL, 0x0100);
2130 /* 10. Initialize the mode by setting VR XS or PCS MMD Digital Control1
2131 * Register Bit[15](VR_RST)
2133 wr32_epcs(hw, VR_XS_OR_PCS_MMD_DIGI_CTL1, 0xA000);
2135 /* Wait phy initialization done */
2136 for (i = 0; i < 100; i++) {
2137 if ((rd32_epcs(hw, VR_XS_OR_PCS_MMD_DIGI_CTL1) &
2138 VR_XS_OR_PCS_MMD_DIGI_CTL1_VR_RST) == 0)
2143 err = TXGBE_ERR_PHY_INIT_NOT_DONE;
2147 if (hw->fw_version <= TXGBE_FW_N_TXEQ) {
2148 value = rd32_epcs(hw, TXGBE_PHY_TX_EQ_CTL0);
2149 value = (value & ~0x3F3F) | (24 << 8) | 4;
2150 wr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL0, value);
2152 value = rd32_epcs(hw, TXGBE_PHY_TX_EQ_CTL1);
2153 value = (value & ~0x7F) | 16 | (1 << 6);
2154 wr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL1, value);
2161 * txgbe_autoc_read - Hides MAC differences needed for AUTOC read
2162 * @hw: pointer to hardware structure
2164 u64 txgbe_autoc_read(struct txgbe_hw *hw)
2171 u8 type = hw->subsystem_device_id & 0xFF;
2173 autoc = hw->mac.autoc;
2175 if (hw->phy.multispeed_fiber) {
2176 autoc |= TXGBE_AUTOC_LMS_10G;
2177 } else if (type == TXGBE_DEV_ID_SFP) {
2178 autoc |= TXGBE_AUTOC_LMS_10G;
2179 autoc |= TXGBE_AUTOC_10GS_SFI;
2180 } else if (type == TXGBE_DEV_ID_QSFP) {
2182 } else if (type == TXGBE_DEV_ID_XAUI || type == TXGBE_DEV_ID_SFI_XAUI) {
2183 autoc |= TXGBE_AUTOC_LMS_10G_LINK_NO_AN;
2184 autoc |= TXGBE_AUTOC_10G_XAUI;
2185 hw->phy.link_mode = TXGBE_PHYSICAL_LAYER_10GBASE_T;
2186 } else if (type == TXGBE_DEV_ID_SGMII) {
2187 autoc |= TXGBE_AUTOC_LMS_SGMII_1G_100M;
2188 hw->phy.link_mode = TXGBE_PHYSICAL_LAYER_1000BASE_T |
2189 TXGBE_PHYSICAL_LAYER_100BASE_TX;
2190 } else if (type == TXGBE_DEV_ID_MAC_XAUI) {
2191 autoc |= TXGBE_AUTOC_LMS_10G_LINK_NO_AN;
2192 hw->phy.link_mode = TXGBE_PHYSICAL_LAYER_10GBASE_KX4;
2193 } else if (type == TXGBE_DEV_ID_MAC_SGMII) {
2194 autoc |= TXGBE_AUTOC_LMS_1G_LINK_NO_AN;
2195 hw->phy.link_mode = TXGBE_PHYSICAL_LAYER_1000BASE_KX;
2198 if (type != TXGBE_DEV_ID_KR_KX_KX4)
2201 sr_pcs_ctl = rd32_epcs(hw, SR_XS_PCS_CTRL2);
2202 sr_pma_ctl1 = rd32_epcs(hw, SR_PMA_CTRL1);
2203 sr_an_ctl = rd32_epcs(hw, SR_AN_CTRL);
2204 sr_an_adv_reg2 = rd32_epcs(hw, SR_AN_MMD_ADV_REG2);
2206 if ((sr_pcs_ctl & SR_PCS_CTRL2_TYPE_SEL) == SR_PCS_CTRL2_TYPE_SEL_X &&
2207 (sr_pma_ctl1 & SR_PMA_CTRL1_SS13) == SR_PMA_CTRL1_SS13_KX &&
2208 (sr_an_ctl & SR_AN_CTRL_AN_EN) == 0) {
2209 /* 1G or KX - no backplane auto-negotiation */
2210 autoc |= TXGBE_AUTOC_LMS_1G_LINK_NO_AN |
2212 hw->phy.link_mode = TXGBE_PHYSICAL_LAYER_1000BASE_KX;
2213 } else if ((sr_pcs_ctl & SR_PCS_CTRL2_TYPE_SEL) ==
2214 SR_PCS_CTRL2_TYPE_SEL_X &&
2215 (sr_pma_ctl1 & SR_PMA_CTRL1_SS13) == SR_PMA_CTRL1_SS13_KX4 &&
2216 (sr_an_ctl & SR_AN_CTRL_AN_EN) == 0) {
2217 autoc |= TXGBE_AUTOC_LMS_10G |
2218 TXGBE_AUTOC_10G_KX4;
2219 hw->phy.link_mode = TXGBE_PHYSICAL_LAYER_10GBASE_KX4;
2220 } else if ((sr_pcs_ctl & SR_PCS_CTRL2_TYPE_SEL) ==
2221 SR_PCS_CTRL2_TYPE_SEL_R &&
2222 (sr_an_ctl & SR_AN_CTRL_AN_EN) == 0) {
2223 /* 10 GbE serial link (KR -no backplane auto-negotiation) */
2224 autoc |= TXGBE_AUTOC_LMS_10G |
2225 TXGBE_AUTOC_10GS_KR;
2226 hw->phy.link_mode = TXGBE_PHYSICAL_LAYER_10GBASE_KR;
2227 } else if ((sr_an_ctl & SR_AN_CTRL_AN_EN)) {
2228 /* KX/KX4/KR backplane auto-negotiation enable */
2229 if (sr_an_adv_reg2 & SR_AN_MMD_ADV_REG2_BP_TYPE_KR)
2230 autoc |= TXGBE_AUTOC_KR_SUPP;
2231 if (sr_an_adv_reg2 & SR_AN_MMD_ADV_REG2_BP_TYPE_KX4)
2232 autoc |= TXGBE_AUTOC_KX4_SUPP;
2233 if (sr_an_adv_reg2 & SR_AN_MMD_ADV_REG2_BP_TYPE_KX)
2234 autoc |= TXGBE_AUTOC_KX_SUPP;
2235 autoc |= TXGBE_AUTOC_LMS_KX4_KX_KR;
2236 hw->phy.link_mode = TXGBE_PHYSICAL_LAYER_10GBASE_KR |
2237 TXGBE_PHYSICAL_LAYER_10GBASE_KX4 |
2238 TXGBE_PHYSICAL_LAYER_1000BASE_KX;
2245 * txgbe_autoc_write - Hides MAC differences needed for AUTOC write
2246 * @hw: pointer to hardware structure
2247 * @autoc: value to write to AUTOC
2249 void txgbe_autoc_write(struct txgbe_hw *hw, u64 autoc)
2254 u8 device_type = hw->subsystem_device_id & 0xFF;
2256 speed = TXGBD_AUTOC_SPEED(autoc);
2257 autoc &= ~TXGBE_AUTOC_SPEED_MASK;
2258 autoneg = (autoc & TXGBE_AUTOC_AUTONEG ? true : false);
2259 autoc &= ~TXGBE_AUTOC_AUTONEG;
2261 if (device_type == TXGBE_DEV_ID_KR_KX_KX4) {
2263 switch (hw->phy.link_mode) {
2264 case TXGBE_PHYSICAL_LAYER_10GBASE_KR:
2265 txgbe_set_link_to_kr(hw, autoneg);
2267 case TXGBE_PHYSICAL_LAYER_10GBASE_KX4:
2268 txgbe_set_link_to_kx4(hw, autoneg);
2270 case TXGBE_PHYSICAL_LAYER_1000BASE_KX:
2271 txgbe_set_link_to_kx(hw, speed, autoneg);
2277 txgbe_set_link_to_kr(hw, !autoneg);
2279 } else if (device_type == TXGBE_DEV_ID_XAUI ||
2280 device_type == TXGBE_DEV_ID_SGMII ||
2281 device_type == TXGBE_DEV_ID_MAC_XAUI ||
2282 device_type == TXGBE_DEV_ID_MAC_SGMII ||
2283 (device_type == TXGBE_DEV_ID_SFI_XAUI &&
2284 hw->phy.media_type == txgbe_media_type_copper)) {
2285 if (speed == TXGBE_LINK_SPEED_10GB_FULL) {
2286 txgbe_set_link_to_kx4(hw, 0);
2288 txgbe_set_link_to_kx(hw, speed, 0);
2289 if (hw->devarg.auto_neg == 1)
2290 txgbe_set_sgmii_an37_ability(hw);
2292 } else if (hw->phy.media_type == txgbe_media_type_fiber) {
2293 txgbe_set_link_to_sfi(hw, speed);
2296 if (speed == TXGBE_LINK_SPEED_10GB_FULL)
2297 mactxcfg = TXGBE_MACTXCFG_SPEED_10G;
2298 else if (speed == TXGBE_LINK_SPEED_1GB_FULL)
2299 mactxcfg = TXGBE_MACTXCFG_SPEED_1G;
2301 /* enable mac transmitter */
2302 wr32m(hw, TXGBE_MACTXCFG,
2303 TXGBE_MACTXCFG_SPEED_MASK | TXGBE_MACTXCFG_TXE,
2304 mactxcfg | TXGBE_MACTXCFG_TXE);
2308 * txgbe_kr_handle - Handle the interrupt of auto-negotiation
2309 * @hw: pointer to hardware structure
2311 s32 txgbe_kr_handle(struct txgbe_hw *hw)
2316 DEBUGFUNC("txgbe_kr_handle");
2318 value = rd32_epcs(hw, VR_AN_INTR);
2319 BP_LOG("AN INTERRUPT!! value: 0x%x\n", value);
2320 if (!(value & VR_AN_INTR_PG_RCV)) {
2321 wr32_epcs(hw, VR_AN_INTR, 0);
2325 status = txgbe_handle_bp_flow(0, hw);
2331 * txgbe_handle_bp_flow - Handle backplane AN73 flow
2332 * @hw: pointer to hardware structure
2333 * @link_mode: local AN73 link mode
2335 static s32 txgbe_handle_bp_flow(u32 link_mode, struct txgbe_hw *hw)
2337 u32 value, i, lp_reg, ld_reg;
2339 struct txgbe_backplane_ability local_ability, lp_ability;
2341 DEBUGFUNC("txgbe_handle_bp_flow");
2343 local_ability.current_link_mode = link_mode;
2345 /* 1. Get the local AN73 Base Page Ability */
2346 BP_LOG("<1>. Get the local AN73 Base Page Ability ...\n");
2347 txgbe_get_bp_ability(&local_ability, 0, hw);
2349 /* 2. Check and clear the AN73 Interrupt Status */
2350 BP_LOG("<2>. Check the AN73 Interrupt Status ...\n");
2351 txgbe_clear_bp_intr(2, 0, hw);
2353 /* 3.1. Get the link partner AN73 Base Page Ability */
2354 BP_LOG("<3.1>. Get the link partner AN73 Base Page Ability ...\n");
2355 txgbe_get_bp_ability(&lp_ability, 1, hw);
2357 /* 3.2. Check the AN73 Link Ability with Link Partner */
2358 BP_LOG("<3.2>. Check the AN73 Link Ability with Link Partner ...\n");
2359 BP_LOG(" Local Link Ability: 0x%x\n", local_ability.link_ability);
2360 BP_LOG(" Link Partner Link Ability: 0x%x\n", lp_ability.link_ability);
2362 status = txgbe_check_bp_ability(&local_ability, &lp_ability, hw);
2364 wr32_epcs(hw, SR_AN_CTRL, 0);
2365 wr32_epcs(hw, VR_AN_KR_MODE_CL, 0);
2367 /* 3.3. Check the FEC and KR Training for KR mode */
2368 BP_LOG("<3.3>. Check the FEC for KR mode ...\n");
2369 if ((local_ability.fec_ability & lp_ability.fec_ability) == 0x03) {
2370 BP_LOG("Enable the Backplane KR FEC ...\n");
2371 wr32_epcs(hw, SR_PMA_KR_FEC_CTRL, SR_PMA_KR_FEC_CTRL_EN);
2373 BP_LOG("Backplane KR FEC is disabled.\n");
2376 printf("Enter training.\n");
2377 /* CL72 KR training on */
2378 for (i = 0; i < 2; i++) {
2379 /* 3.4. Check the CL72 KR Training for KR mode */
2380 BP_LOG("<3.4>. Check the CL72 KR Training for KR mode ...\n");
2381 BP_LOG("==================%d==================\n", i);
2382 status = txgbe_enable_kr_training(hw);
2383 BP_LOG("Check the Clause 72 KR Training status ...\n");
2384 status |= txgbe_check_kr_training(hw);
2386 lp_reg = rd32_epcs(hw, SR_PMA_KR_LP_CESTS);
2387 lp_reg &= SR_PMA_KR_LP_CESTS_RR;
2388 BP_LOG("SR PMA MMD 10GBASE-KR LP Coefficient Status Register: 0x%x\n",
2390 ld_reg = rd32_epcs(hw, SR_PMA_KR_LD_CESTS);
2391 ld_reg &= SR_PMA_KR_LD_CESTS_RR;
2392 BP_LOG("SR PMA MMD 10GBASE-KR LD Coefficient Status Register: 0x%x\n",
2394 if (hw->devarg.poll == 0 && status != 0)
2395 lp_reg = SR_PMA_KR_LP_CESTS_RR;
2397 if (lp_reg & ld_reg) {
2398 BP_LOG("==================out==================\n");
2399 status = txgbe_disable_kr_training(hw, 0, 0);
2400 wr32_epcs(hw, SR_AN_CTRL, 0);
2401 txgbe_clear_bp_intr(2, 0, hw);
2402 txgbe_clear_bp_intr(1, 0, hw);
2403 txgbe_clear_bp_intr(0, 0, hw);
2404 for (i = 0; i < 10; i++) {
2405 value = rd32_epcs(hw, SR_XS_PCS_KR_STS1);
2406 if (value & SR_XS_PCS_KR_STS1_PLU) {
2407 BP_LOG("\nINT_AN_INT_CMPLT =1, AN73 Done Success.\n");
2408 wr32_epcs(hw, SR_AN_CTRL, 0);
2414 txgbe_set_link_to_kr(hw, 0);
2419 status |= txgbe_disable_kr_training(hw, 0, 0);
2422 txgbe_clear_bp_intr(2, 0, hw);
2423 txgbe_clear_bp_intr(1, 0, hw);
2424 txgbe_clear_bp_intr(0, 0, hw);
2430 * txgbe_get_bp_ability
2431 * @hw: pointer to hardware structure
2432 * @ability: pointer to blackplane ability structure
2434 * 1: Get Link Partner Base Page
2435 * 2: Get Link Partner Next Page
2436 * (only get NXP Ability Register 1 at the moment)
2437 * 0: Get Local Device Base Page
2439 static void txgbe_get_bp_ability(struct txgbe_backplane_ability *ability,
2440 u32 link_partner, struct txgbe_hw *hw)
2444 DEBUGFUNC("txgbe_get_bp_ability");
2446 /* Link Partner Base Page */
2447 if (link_partner == 1) {
2448 /* Read the link partner AN73 Base Page Ability Registers */
2449 BP_LOG("Read the link partner AN73 Base Page Ability Registers...\n");
2450 value = rd32_epcs(hw, SR_AN_MMD_LP_ABL1);
2451 BP_LOG("SR AN MMD LP Base Page Ability Register 1: 0x%x\n",
2453 ability->next_page = SR_MMD_LP_ABL1_ADV_NP(value);
2454 BP_LOG(" Next Page (bit15): %d\n", ability->next_page);
2456 value = rd32_epcs(hw, SR_AN_MMD_LP_ABL2);
2457 BP_LOG("SR AN MMD LP Base Page Ability Register 2: 0x%x\n",
2459 ability->link_ability =
2460 value & SR_AN_MMD_LP_ABL2_BP_TYPE_KR_KX4_KX;
2461 BP_LOG(" Link Ability (bit[15:0]): 0x%x\n",
2462 ability->link_ability);
2463 BP_LOG(" (0x20- KX_ONLY, 0x40- KX4_ONLY, 0x60- KX4_KX\n");
2464 BP_LOG(" 0x80- KR_ONLY, 0xA0- KR_KX, 0xC0- KR_KX4, 0xE0- KR_KX4_KX)\n");
2466 value = rd32_epcs(hw, SR_AN_MMD_LP_ABL3);
2467 BP_LOG("SR AN MMD LP Base Page Ability Register 3: 0x%x\n",
2469 BP_LOG(" FEC Request (bit15): %d\n", ((value >> 15) & 0x01));
2470 BP_LOG(" FEC Enable (bit14): %d\n", ((value >> 14) & 0x01));
2471 ability->fec_ability = SR_AN_MMD_LP_ABL3_FCE(value);
2472 } else if (link_partner == 2) {
2473 /* Read the link partner AN73 Next Page Ability Registers */
2474 BP_LOG("\nRead the link partner AN73 Next Page Ability Registers...\n");
2475 value = rd32_epcs(hw, SR_AN_LP_XNP_ABL1);
2476 BP_LOG(" SR AN MMD LP XNP Ability Register 1: 0x%x\n", value);
2477 ability->next_page = SR_AN_LP_XNP_ABL1_NP(value);
2478 BP_LOG(" Next Page (bit15): %d\n", ability->next_page);
2480 /* Read the local AN73 Base Page Ability Registers */
2481 BP_LOG("Read the local AN73 Base Page Ability Registers...\n");
2482 value = rd32_epcs(hw, SR_AN_MMD_ADV_REG1);
2483 BP_LOG("SR AN MMD Advertisement Register 1: 0x%x\n", value);
2484 ability->next_page = SR_AN_MMD_ADV_REG1_NP(value);
2485 BP_LOG(" Next Page (bit15): %d\n", ability->next_page);
2487 value = rd32_epcs(hw, SR_AN_MMD_ADV_REG2);
2488 BP_LOG("SR AN MMD Advertisement Register 2: 0x%x\n", value);
2489 ability->link_ability =
2490 value & SR_AN_MMD_ADV_REG2_BP_TYPE_KR_KX4_KX;
2491 BP_LOG(" Link Ability (bit[15:0]): 0x%x\n",
2492 ability->link_ability);
2493 BP_LOG(" (0x20- KX_ONLY, 0x40- KX4_ONLY, 0x60- KX4_KX\n");
2494 BP_LOG(" 0x80- KR_ONLY, 0xA0- KR_KX, 0xC0- KR_KX4, 0xE0- KR_KX4_KX)\n");
2496 value = rd32_epcs(hw, SR_AN_MMD_ADV_REG3);
2497 BP_LOG("SR AN MMD Advertisement Register 3: 0x%x\n", value);
2498 BP_LOG(" FEC Request (bit15): %d\n", ((value >> 15) & 0x01));
2499 BP_LOG(" FEC Enable (bit14): %d\n", ((value >> 14) & 0x01));
2500 ability->fec_ability = SR_AN_MMD_ADV_REG3_FCE(value);
2507 * txgbe_check_bp_ability
2508 * @hw: pointer to hardware structure
2509 * @ability: pointer to blackplane ability structure
2511 static s32 txgbe_check_bp_ability(struct txgbe_backplane_ability *local_ability,
2512 struct txgbe_backplane_ability *lp_ability, struct txgbe_hw *hw)
2517 DEBUGFUNC("txgbe_check_bp_ability");
2519 com_link_abi = local_ability->link_ability & lp_ability->link_ability;
2520 BP_LOG("com_link_abi = 0x%x, local_ability = 0x%x, lp_ability = 0x%x\n",
2521 com_link_abi, local_ability->link_ability,
2522 lp_ability->link_ability);
2524 if (!com_link_abi) {
2525 BP_LOG("The Link Partner does not support any compatible speed mode.\n");
2527 } else if (com_link_abi & BP_TYPE_KR) {
2528 if (local_ability->current_link_mode) {
2529 BP_LOG("Link mode is not matched with Link Partner: [LINK_KR].\n");
2530 BP_LOG("Set the local link mode to [LINK_KR] ...\n");
2531 txgbe_set_link_to_kr(hw, 0);
2534 BP_LOG("Link mode is matched with Link Partner: [LINK_KR].\n");
2537 } else if (com_link_abi & BP_TYPE_KX4) {
2538 if (local_ability->current_link_mode == 0x10) {
2539 BP_LOG("Link mode is matched with Link Partner: [LINK_KX4].\n");
2542 BP_LOG("Link mode is not matched with Link Partner: [LINK_KX4].\n");
2543 BP_LOG("Set the local link mode to [LINK_KX4] ...\n");
2544 txgbe_set_link_to_kx4(hw, 1);
2547 } else if (com_link_abi & BP_TYPE_KX) {
2548 if (local_ability->current_link_mode == 0x1) {
2549 BP_LOG("Link mode is matched with Link Partner: [LINK_KX].\n");
2552 BP_LOG("Link mode is not matched with Link Partner: [LINK_KX].\n");
2553 BP_LOG("Set the local link mode to [LINK_KX] ...\n");
2554 txgbe_set_link_to_kx(hw, 1, 1);
2563 * txgbe_clear_bp_intr
2564 * @hw: pointer to hardware structure
2565 * @index: the bit will be cleared
2567 * index_high = 0: Only the index bit will be cleared
2568 * index_high != 0: the [index_high, index] range will be cleared
2570 static void txgbe_clear_bp_intr(u32 bit, u32 bit_high, struct txgbe_hw *hw)
2572 u32 rdata = 0, wdata, i;
2574 DEBUGFUNC("txgbe_clear_bp_intr");
2576 rdata = rd32_epcs(hw, VR_AN_INTR);
2577 BP_LOG("[Before clear]Read VR AN MMD Interrupt Register: 0x%x\n",
2579 BP_LOG("Interrupt: 0- AN_INT_CMPLT, 1- AN_INC_LINK, 2- AN_PG_RCV\n\n");
2583 for (i = bit; i <= bit_high; i++)
2586 wdata &= ~(1 << bit);
2589 wr32_epcs(hw, VR_AN_INTR, wdata);
2591 rdata = rd32_epcs(hw, VR_AN_INTR);
2592 BP_LOG("[After clear]Read VR AN MMD Interrupt Register: 0x%x\n", rdata);
2595 static s32 txgbe_enable_kr_training(struct txgbe_hw *hw)
2600 DEBUGFUNC("txgbe_enable_kr_training");
2602 BP_LOG("Enable Clause 72 KR Training ...\n");
2604 if (CL72_KRTR_PRBS_MODE_EN != 0xFFFF) {
2605 /* Set PRBS Timer Duration Control to maximum 6.7ms in
2606 * VR_PMA_KRTR_PRBS_CTRL2 Register
2608 value = CL72_KRTR_PRBS_MODE_EN;
2609 wr32_epcs(hw, VR_PMA_KRTR_PRBS_CTRL2, value);
2610 /* Set PRBS Timer Duration Control to maximum 6.7ms in
2611 * VR_PMA_KRTR_PRBS_CTRL1 Register
2613 wr32_epcs(hw, VR_PMA_KRTR_PRBS_CTRL1,
2614 VR_PMA_KRTR_PRBS_TIME_LMT);
2615 /* Enable PRBS Mode to determine KR Training Status by setting
2616 * Bit 0 of VR_PMA_KRTR_PRBS_CTRL0 Register
2618 value = VR_PMA_KRTR_PRBS_MODE_EN;
2620 #ifdef CL72_KRTR_PRBS31_EN
2621 /* Enable PRBS Mode to determine KR Training Status by setting
2622 * Bit 1 of VR_PMA_KRTR_PRBS_CTRL0 Register
2624 value = VR_PMA_KRTR_PRBS31_EN;
2626 wr32_epcs(hw, VR_PMA_KRTR_PRBS_CTRL0, value);
2627 /* Read PHY Lane0 TX EQ before Clause 72 KR Training. */
2628 txgbe_read_phy_lane_tx_eq(0, hw, 0, 0);
2630 /* Enable the Clause 72 start-up protocol
2631 * by setting Bit 1 of SR_PMA_KR_PMD_CTRL Register.
2632 * Restart the Clause 72 start-up protocol
2633 * by setting Bit 0 of SR_PMA_KR_PMD_CTRL Register.
2635 wr32_epcs(hw, SR_PMA_KR_PMD_CTRL,
2636 SR_PMA_KR_PMD_CTRL_EN_TR | SR_PMA_KR_PMD_CTRL_RS_TR);
2641 static s32 txgbe_disable_kr_training(struct txgbe_hw *hw, s32 post, s32 mode)
2645 DEBUGFUNC("txgbe_disable_kr_training");
2647 BP_LOG("Disable Clause 72 KR Training ...\n");
2648 /* Read PHY Lane0 TX EQ before Clause 72 KR Training. */
2649 txgbe_read_phy_lane_tx_eq(0, hw, post, mode);
2651 wr32_epcs(hw, SR_PMA_KR_PMD_CTRL, SR_PMA_KR_PMD_CTRL_RS_TR);
2656 static s32 txgbe_check_kr_training(struct txgbe_hw *hw)
2661 int times = hw->devarg.poll ? 35 : 20;
2663 DEBUGFUNC("txgbe_check_kr_training");
2665 for (i = 0; i < times; i++) {
2666 value = rd32_epcs(hw, SR_PMA_KR_LP_CEU);
2667 BP_LOG("SR PMA MMD 10GBASE-KR LP Coefficient Update Register: 0x%x\n",
2669 value = rd32_epcs(hw, SR_PMA_KR_LP_CESTS);
2670 BP_LOG("SR PMA MMD 10GBASE-KR LP Coefficient Status Register: 0x%x\n",
2672 value = rd32_epcs(hw, SR_PMA_KR_LD_CEU);
2673 BP_LOG("SR PMA MMD 10GBASE-KR LD Coefficient Update: 0x%x\n",
2675 value = rd32_epcs(hw, SR_PMA_KR_LD_CESTS);
2676 BP_LOG("SR PMA MMD 10GBASE-KR LD Coefficient Status: 0x%x\n",
2678 value = rd32_epcs(hw, SR_PMA_KR_PMD_STS);
2679 BP_LOG("SR PMA MMD 10GBASE-KR Status Register: 0x%x\n", value);
2680 BP_LOG(" Training Failure (bit3): %d\n",
2681 ((value >> 3) & 0x01));
2682 BP_LOG(" Start-Up Protocol Status (bit2): %d\n",
2683 ((value >> 2) & 0x01));
2684 BP_LOG(" Frame Lock (bit1): %d\n",
2685 ((value >> 1) & 0x01));
2686 BP_LOG(" Receiver Status (bit0): %d\n",
2687 ((value >> 0) & 0x01));
2689 test = rd32_epcs(hw, SR_PMA_KR_LP_CESTS);
2690 if (test & SR_PMA_KR_LP_CESTS_RR) {
2691 BP_LOG("TEST Coefficient Status Register: 0x%x\n",
2696 if (value & SR_PMA_KR_PMD_STS_TR_FAIL) {
2697 BP_LOG("Training is completed with failure.\n");
2698 txgbe_read_phy_lane_tx_eq(0, hw, 0, 0);
2702 if (value & SR_PMA_KR_PMD_STS_RCV) {
2703 BP_LOG("Receiver trained and ready to receive data.\n");
2704 txgbe_read_phy_lane_tx_eq(0, hw, 0, 0);
2711 BP_LOG("ERROR: Check Clause 72 KR Training Complete Timeout.\n");
2715 static void txgbe_read_phy_lane_tx_eq(u16 lane, struct txgbe_hw *hw,
2720 u32 tx_main_cursor, tx_pre_cursor, tx_post_cursor, lmain;
2722 DEBUGFUNC("txgbe_read_phy_lane_tx_eq");
2724 addr = TXGBE_PHY_LANE0_TX_EQ_CTL1 | (lane << 8);
2725 value = rd32_ephy(hw, addr);
2726 BP_LOG("PHY LANE TX EQ Read Value: %x\n", lane);
2727 tx_main_cursor = TXGBE_PHY_LANE0_TX_EQ_CTL1_MAIN(value);
2728 BP_LOG("TX_MAIN_CURSOR: %x\n", tx_main_cursor);
2729 UNREFERENCED_PARAMETER(tx_main_cursor);
2731 addr = TXGBE_PHY_LANE0_TX_EQ_CTL2 | (lane << 8);
2732 value = rd32_ephy(hw, addr);
2733 tx_pre_cursor = value & TXGBE_PHY_LANE0_TX_EQ_CTL2_PRE;
2734 tx_post_cursor = TXGBE_PHY_LANE0_TX_EQ_CTL2_POST(value);
2735 BP_LOG("TX_PRE_CURSOR: %x\n", tx_pre_cursor);
2736 BP_LOG("TX_POST_CURSOR: %x\n", tx_post_cursor);
2739 lmain = 160 - tx_pre_cursor - tx_post_cursor;
2744 tx_post_cursor = post;
2746 wr32_epcs(hw, TXGBE_PHY_EQ_INIT_CTL1, tx_post_cursor);
2747 wr32_epcs(hw, TXGBE_PHY_EQ_INIT_CTL0,
2748 tx_pre_cursor | (lmain << 8));
2749 value = rd32_epcs(hw, TXGBE_PHY_TX_EQ_CTL1);
2750 value &= ~TXGBE_PHY_TX_EQ_CTL1_DEF;
2751 wr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL1, value);