1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2015-2020 Beijing WangXun Technology Co., Ltd.
3 * Copyright(c) 2010-2017 Intel Corporation
7 #include "txgbe_eeprom.h"
11 static void txgbe_i2c_start(struct txgbe_hw *hw, u8 dev_addr);
12 static void txgbe_i2c_stop(struct txgbe_hw *hw);
13 static s32 txgbe_handle_bp_flow(u32 link_mode, struct txgbe_hw *hw);
14 static void txgbe_get_bp_ability(struct txgbe_backplane_ability *ability,
15 u32 link_partner, struct txgbe_hw *hw);
16 static s32 txgbe_check_bp_ability(struct txgbe_backplane_ability *local_ability,
17 struct txgbe_backplane_ability *lp_ability, struct txgbe_hw *hw);
18 static void txgbe_clear_bp_intr(u32 bit, u32 bit_high, struct txgbe_hw *hw);
19 static s32 txgbe_enable_kr_training(struct txgbe_hw *hw);
20 static s32 txgbe_disable_kr_training(struct txgbe_hw *hw, s32 post, s32 mode);
21 static s32 txgbe_check_kr_training(struct txgbe_hw *hw);
22 static void txgbe_read_phy_lane_tx_eq(u16 lane, struct txgbe_hw *hw,
24 static s32 txgbe_set_link_to_sfi(struct txgbe_hw *hw, u32 speed);
27 * txgbe_identify_extphy - Identify a single address for a PHY
28 * @hw: pointer to hardware structure
29 * @phy_addr: PHY address to probe
31 * Returns true if PHY found
33 static bool txgbe_identify_extphy(struct txgbe_hw *hw)
37 if (!txgbe_validate_phy_addr(hw, phy_addr)) {
38 DEBUGOUT("Unable to validate PHY address 0x%04X\n",
43 if (txgbe_get_phy_id(hw))
46 hw->phy.type = txgbe_get_phy_type_from_id(hw->phy.id);
47 if (hw->phy.type == txgbe_phy_unknown) {
49 hw->phy.read_reg(hw, TXGBE_MD_PHY_EXT_ABILITY,
53 if (ext_ability & (TXGBE_MD_PHY_10GBASET_ABILITY |
54 TXGBE_MD_PHY_1000BASET_ABILITY))
55 hw->phy.type = txgbe_phy_cu_unknown;
57 hw->phy.type = txgbe_phy_generic;
64 * txgbe_read_phy_if - Read TXGBE_ETHPHYIF register
65 * @hw: pointer to hardware structure
67 * Read TXGBE_ETHPHYIF register and save field values,
68 * and check for valid field values.
70 static s32 txgbe_read_phy_if(struct txgbe_hw *hw)
72 hw->phy.media_type = hw->phy.get_media_type(hw);
74 /* Save NW management interface connected on board. This is used
75 * to determine internal PHY mode.
77 hw->phy.nw_mng_if_sel = rd32(hw, TXGBE_ETHPHYIF);
79 /* If MDIO is connected to external PHY, then set PHY address. */
80 if (hw->phy.nw_mng_if_sel & TXGBE_ETHPHYIF_MDIO_ACT)
81 hw->phy.addr = TXGBE_ETHPHYIF_MDIO_BASE(hw->phy.nw_mng_if_sel);
83 if (!hw->phy.phy_semaphore_mask) {
85 hw->phy.phy_semaphore_mask = TXGBE_MNGSEM_SWPHY;
87 hw->phy.phy_semaphore_mask = TXGBE_MNGSEM_SWPHY;
94 * txgbe_identify_phy - Get physical layer module
95 * @hw: pointer to hardware structure
97 * Determines the physical layer module found on the current adapter.
99 s32 txgbe_identify_phy(struct txgbe_hw *hw)
101 s32 err = TXGBE_ERR_PHY_ADDR_INVALID;
103 DEBUGFUNC("txgbe_identify_phy");
105 txgbe_read_phy_if(hw);
107 if (hw->phy.type != txgbe_phy_unknown)
110 /* Raptor 10GBASE-T requires an external PHY */
111 if (hw->phy.media_type == txgbe_media_type_copper) {
112 err = txgbe_identify_extphy(hw);
113 } else if (hw->phy.media_type == txgbe_media_type_fiber) {
114 err = txgbe_identify_module(hw);
116 hw->phy.type = txgbe_phy_none;
120 /* Return error if SFP module has been detected but is not supported */
121 if (hw->phy.type == txgbe_phy_sfp_unsupported)
122 return TXGBE_ERR_SFP_NOT_SUPPORTED;
128 * txgbe_check_reset_blocked - check status of MNG FW veto bit
129 * @hw: pointer to the hardware structure
131 * This function checks the STAT.MNGVETO bit to see if there are
132 * any constraints on link from manageability. For MAC's that don't
133 * have this bit just return faluse since the link can not be blocked
136 s32 txgbe_check_reset_blocked(struct txgbe_hw *hw)
140 DEBUGFUNC("txgbe_check_reset_blocked");
142 mmngc = rd32(hw, TXGBE_STAT);
143 if (mmngc & TXGBE_STAT_MNGVETO) {
144 DEBUGOUT("MNG_VETO bit detected.\n");
152 * txgbe_validate_phy_addr - Determines phy address is valid
153 * @hw: pointer to hardware structure
154 * @phy_addr: PHY address
157 bool txgbe_validate_phy_addr(struct txgbe_hw *hw, u32 phy_addr)
162 DEBUGFUNC("txgbe_validate_phy_addr");
164 hw->phy.addr = phy_addr;
165 hw->phy.read_reg(hw, TXGBE_MD_PHY_ID_HIGH,
166 TXGBE_MD_DEV_PMA_PMD, &phy_id);
168 if (phy_id != 0xFFFF && phy_id != 0x0)
171 DEBUGOUT("PHY ID HIGH is 0x%04X\n", phy_id);
177 * txgbe_get_phy_id - Get the phy type
178 * @hw: pointer to hardware structure
181 s32 txgbe_get_phy_id(struct txgbe_hw *hw)
187 DEBUGFUNC("txgbe_get_phy_id");
189 err = hw->phy.read_reg(hw, TXGBE_MD_PHY_ID_HIGH,
190 TXGBE_MD_DEV_PMA_PMD,
194 hw->phy.id = (u32)(phy_id_high << 16);
195 err = hw->phy.read_reg(hw, TXGBE_MD_PHY_ID_LOW,
196 TXGBE_MD_DEV_PMA_PMD,
198 hw->phy.id |= (u32)(phy_id_low & TXGBE_PHY_REVISION_MASK);
199 hw->phy.revision = (u32)(phy_id_low & ~TXGBE_PHY_REVISION_MASK);
201 DEBUGOUT("PHY_ID_HIGH 0x%04X, PHY_ID_LOW 0x%04X\n",
202 phy_id_high, phy_id_low);
208 * txgbe_get_phy_type_from_id - Get the phy type
209 * @phy_id: PHY ID information
212 enum txgbe_phy_type txgbe_get_phy_type_from_id(u32 phy_id)
214 enum txgbe_phy_type phy_type;
216 DEBUGFUNC("txgbe_get_phy_type_from_id");
219 case TXGBE_PHYID_TN1010:
220 phy_type = txgbe_phy_tn;
222 case TXGBE_PHYID_QT2022:
223 phy_type = txgbe_phy_qt;
225 case TXGBE_PHYID_ATH:
226 phy_type = txgbe_phy_nl;
228 case TXGBE_PHYID_MTD3310:
229 phy_type = txgbe_phy_cu_mtd;
232 phy_type = txgbe_phy_unknown;
240 txgbe_reset_extphy(struct txgbe_hw *hw)
245 err = hw->phy.read_reg(hw, TXGBE_MD_PORT_CTRL,
246 TXGBE_MD_DEV_GENERAL, &ctrl);
249 ctrl |= TXGBE_MD_PORT_CTRL_RESET;
250 err = hw->phy.write_reg(hw, TXGBE_MD_PORT_CTRL,
251 TXGBE_MD_DEV_GENERAL, ctrl);
256 * Poll for reset bit to self-clear indicating reset is complete.
257 * Some PHYs could take up to 3 seconds to complete and need about
258 * 1.7 usec delay after the reset is complete.
260 for (i = 0; i < 30; i++) {
262 err = hw->phy.read_reg(hw, TXGBE_MD_PORT_CTRL,
263 TXGBE_MD_DEV_GENERAL, &ctrl);
267 if (!(ctrl & TXGBE_MD_PORT_CTRL_RESET)) {
273 if (ctrl & TXGBE_MD_PORT_CTRL_RESET) {
274 err = TXGBE_ERR_RESET_FAILED;
275 DEBUGOUT("PHY reset polling failed to complete.\n");
282 * txgbe_reset_phy - Performs a PHY reset
283 * @hw: pointer to hardware structure
285 s32 txgbe_reset_phy(struct txgbe_hw *hw)
289 DEBUGFUNC("txgbe_reset_phy");
291 if (hw->phy.type == txgbe_phy_unknown)
292 err = txgbe_identify_phy(hw);
294 if (err != 0 || hw->phy.type == txgbe_phy_none)
297 /* Don't reset PHY if it's shut down due to overtemp. */
298 if (hw->phy.check_overtemp(hw) == TXGBE_ERR_OVERTEMP)
301 /* Blocked by MNG FW so bail */
302 if (txgbe_check_reset_blocked(hw))
305 switch (hw->phy.type) {
306 case txgbe_phy_cu_mtd:
307 err = txgbe_reset_extphy(hw);
317 * txgbe_read_phy_mdi - Reads a value from a specified PHY register without
319 * @hw: pointer to hardware structure
320 * @reg_addr: 32 bit address of PHY register to read
321 * @device_type: 5 bit device type
322 * @phy_data: Pointer to read data from PHY register
324 s32 txgbe_read_phy_reg_mdi(struct txgbe_hw *hw, u32 reg_addr, u32 device_type,
329 /* Setup and write the address cycle command */
330 command = TXGBE_MDIOSCA_REG(reg_addr) |
331 TXGBE_MDIOSCA_DEV(device_type) |
332 TXGBE_MDIOSCA_PORT(hw->phy.addr);
333 wr32(hw, TXGBE_MDIOSCA, command);
335 command = TXGBE_MDIOSCD_CMD_READ |
337 wr32(hw, TXGBE_MDIOSCD, command);
340 * Check every 10 usec to see if the address cycle completed.
341 * The MDI Command bit will clear when the operation is
344 if (!po32m(hw, TXGBE_MDIOSCD, TXGBE_MDIOSCD_BUSY,
345 0, NULL, 100, 100)) {
346 DEBUGOUT("PHY address command did not complete\n");
347 return TXGBE_ERR_PHY;
350 data = rd32(hw, TXGBE_MDIOSCD);
351 *phy_data = (u16)TXGBD_MDIOSCD_DAT(data);
357 * txgbe_read_phy_reg - Reads a value from a specified PHY register
358 * using the SWFW lock - this function is needed in most cases
359 * @hw: pointer to hardware structure
360 * @reg_addr: 32 bit address of PHY register to read
361 * @device_type: 5 bit device type
362 * @phy_data: Pointer to read data from PHY register
364 s32 txgbe_read_phy_reg(struct txgbe_hw *hw, u32 reg_addr,
365 u32 device_type, u16 *phy_data)
368 u32 gssr = hw->phy.phy_semaphore_mask;
370 DEBUGFUNC("txgbe_read_phy_reg");
372 if (hw->mac.acquire_swfw_sync(hw, gssr))
373 return TXGBE_ERR_SWFW_SYNC;
375 err = hw->phy.read_reg_mdi(hw, reg_addr, device_type, phy_data);
377 hw->mac.release_swfw_sync(hw, gssr);
383 * txgbe_write_phy_reg_mdi - Writes a value to specified PHY register
385 * @hw: pointer to hardware structure
386 * @reg_addr: 32 bit PHY register to write
387 * @device_type: 5 bit device type
388 * @phy_data: Data to write to the PHY register
390 s32 txgbe_write_phy_reg_mdi(struct txgbe_hw *hw, u32 reg_addr,
391 u32 device_type, u16 phy_data)
396 command = TXGBE_MDIOSCA_REG(reg_addr) |
397 TXGBE_MDIOSCA_DEV(device_type) |
398 TXGBE_MDIOSCA_PORT(hw->phy.addr);
399 wr32(hw, TXGBE_MDIOSCA, command);
401 command = TXGBE_MDIOSCD_CMD_WRITE |
402 TXGBE_MDIOSCD_DAT(phy_data) |
404 wr32(hw, TXGBE_MDIOSCD, command);
406 /* wait for completion */
407 if (!po32m(hw, TXGBE_MDIOSCD, TXGBE_MDIOSCD_BUSY,
408 0, NULL, 100, 100)) {
409 TLOG_DEBUG("PHY write cmd didn't complete\n");
417 * txgbe_write_phy_reg - Writes a value to specified PHY register
418 * using SWFW lock- this function is needed in most cases
419 * @hw: pointer to hardware structure
420 * @reg_addr: 32 bit PHY register to write
421 * @device_type: 5 bit device type
422 * @phy_data: Data to write to the PHY register
424 s32 txgbe_write_phy_reg(struct txgbe_hw *hw, u32 reg_addr,
425 u32 device_type, u16 phy_data)
428 u32 gssr = hw->phy.phy_semaphore_mask;
430 DEBUGFUNC("txgbe_write_phy_reg");
432 if (hw->mac.acquire_swfw_sync(hw, gssr))
433 err = TXGBE_ERR_SWFW_SYNC;
435 err = hw->phy.write_reg_mdi(hw, reg_addr, device_type,
437 hw->mac.release_swfw_sync(hw, gssr);
443 * txgbe_setup_phy_link - Set and restart auto-neg
444 * @hw: pointer to hardware structure
446 * Restart auto-negotiation and PHY and waits for completion.
448 s32 txgbe_setup_phy_link(struct txgbe_hw *hw)
451 u16 autoneg_reg = TXGBE_MII_AUTONEG_REG;
452 bool autoneg = false;
455 DEBUGFUNC("txgbe_setup_phy_link");
457 txgbe_get_copper_link_capabilities(hw, &speed, &autoneg);
459 /* Set or unset auto-negotiation 10G advertisement */
460 hw->phy.read_reg(hw, TXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
461 TXGBE_MD_DEV_AUTO_NEG,
464 autoneg_reg &= ~TXGBE_MII_10GBASE_T_ADVERTISE;
465 if ((hw->phy.autoneg_advertised & TXGBE_LINK_SPEED_10GB_FULL) &&
466 (speed & TXGBE_LINK_SPEED_10GB_FULL))
467 autoneg_reg |= TXGBE_MII_10GBASE_T_ADVERTISE;
469 hw->phy.write_reg(hw, TXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
470 TXGBE_MD_DEV_AUTO_NEG,
473 hw->phy.read_reg(hw, TXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
474 TXGBE_MD_DEV_AUTO_NEG,
477 /* Set or unset auto-negotiation 5G advertisement */
478 autoneg_reg &= ~TXGBE_MII_5GBASE_T_ADVERTISE;
479 if ((hw->phy.autoneg_advertised & TXGBE_LINK_SPEED_5GB_FULL) &&
480 (speed & TXGBE_LINK_SPEED_5GB_FULL))
481 autoneg_reg |= TXGBE_MII_5GBASE_T_ADVERTISE;
483 /* Set or unset auto-negotiation 2.5G advertisement */
484 autoneg_reg &= ~TXGBE_MII_2_5GBASE_T_ADVERTISE;
485 if ((hw->phy.autoneg_advertised &
486 TXGBE_LINK_SPEED_2_5GB_FULL) &&
487 (speed & TXGBE_LINK_SPEED_2_5GB_FULL))
488 autoneg_reg |= TXGBE_MII_2_5GBASE_T_ADVERTISE;
489 /* Set or unset auto-negotiation 1G advertisement */
490 autoneg_reg &= ~TXGBE_MII_1GBASE_T_ADVERTISE;
491 if ((hw->phy.autoneg_advertised & TXGBE_LINK_SPEED_1GB_FULL) &&
492 (speed & TXGBE_LINK_SPEED_1GB_FULL))
493 autoneg_reg |= TXGBE_MII_1GBASE_T_ADVERTISE;
495 hw->phy.write_reg(hw, TXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
496 TXGBE_MD_DEV_AUTO_NEG,
499 /* Set or unset auto-negotiation 100M advertisement */
500 hw->phy.read_reg(hw, TXGBE_MII_AUTONEG_ADVERTISE_REG,
501 TXGBE_MD_DEV_AUTO_NEG,
504 autoneg_reg &= ~(TXGBE_MII_100BASE_T_ADVERTISE |
505 TXGBE_MII_100BASE_T_ADVERTISE_HALF);
506 if ((hw->phy.autoneg_advertised & TXGBE_LINK_SPEED_100M_FULL) &&
507 (speed & TXGBE_LINK_SPEED_100M_FULL))
508 autoneg_reg |= TXGBE_MII_100BASE_T_ADVERTISE;
510 hw->phy.write_reg(hw, TXGBE_MII_AUTONEG_ADVERTISE_REG,
511 TXGBE_MD_DEV_AUTO_NEG,
514 /* Blocked by MNG FW so don't reset PHY */
515 if (txgbe_check_reset_blocked(hw))
518 /* Restart PHY auto-negotiation. */
519 hw->phy.read_reg(hw, TXGBE_MD_AUTO_NEG_CONTROL,
520 TXGBE_MD_DEV_AUTO_NEG, &autoneg_reg);
522 autoneg_reg |= TXGBE_MII_RESTART;
524 hw->phy.write_reg(hw, TXGBE_MD_AUTO_NEG_CONTROL,
525 TXGBE_MD_DEV_AUTO_NEG, autoneg_reg);
531 * txgbe_setup_phy_link_speed - Sets the auto advertised capabilities
532 * @hw: pointer to hardware structure
533 * @speed: new link speed
534 * @autoneg_wait_to_complete: unused
536 s32 txgbe_setup_phy_link_speed(struct txgbe_hw *hw,
538 bool autoneg_wait_to_complete)
540 UNREFERENCED_PARAMETER(autoneg_wait_to_complete);
542 DEBUGFUNC("txgbe_setup_phy_link_speed");
545 * Clear autoneg_advertised and set new values based on input link
548 hw->phy.autoneg_advertised = 0;
550 if (speed & TXGBE_LINK_SPEED_10GB_FULL)
551 hw->phy.autoneg_advertised |= TXGBE_LINK_SPEED_10GB_FULL;
553 if (speed & TXGBE_LINK_SPEED_5GB_FULL)
554 hw->phy.autoneg_advertised |= TXGBE_LINK_SPEED_5GB_FULL;
556 if (speed & TXGBE_LINK_SPEED_2_5GB_FULL)
557 hw->phy.autoneg_advertised |= TXGBE_LINK_SPEED_2_5GB_FULL;
559 if (speed & TXGBE_LINK_SPEED_1GB_FULL)
560 hw->phy.autoneg_advertised |= TXGBE_LINK_SPEED_1GB_FULL;
562 if (speed & TXGBE_LINK_SPEED_100M_FULL)
563 hw->phy.autoneg_advertised |= TXGBE_LINK_SPEED_100M_FULL;
565 if (speed & TXGBE_LINK_SPEED_10M_FULL)
566 hw->phy.autoneg_advertised |= TXGBE_LINK_SPEED_10M_FULL;
568 /* Setup link based on the new speed settings */
569 hw->phy.setup_link(hw);
574 s32 txgbe_get_phy_fw_version(struct txgbe_hw *hw, u32 *fw_version)
576 u16 eeprom_verh, eeprom_verl;
578 hw->rom.readw_sw(hw, TXGBE_EEPROM_VERSION_H, &eeprom_verh);
579 hw->rom.readw_sw(hw, TXGBE_EEPROM_VERSION_L, &eeprom_verl);
581 *fw_version = (eeprom_verh << 16) | eeprom_verl;
587 * txgbe_get_copper_speeds_supported - Get copper link speeds from phy
588 * @hw: pointer to hardware structure
590 * Determines the supported link capabilities by reading the PHY auto
591 * negotiation register.
593 static s32 txgbe_get_copper_speeds_supported(struct txgbe_hw *hw)
598 err = hw->phy.read_reg(hw, TXGBE_MD_PHY_SPEED_ABILITY,
599 TXGBE_MD_DEV_PMA_PMD,
604 if (speed_ability & TXGBE_MD_PHY_SPEED_10G)
605 hw->phy.speeds_supported |= TXGBE_LINK_SPEED_10GB_FULL;
606 if (speed_ability & TXGBE_MD_PHY_SPEED_1G)
607 hw->phy.speeds_supported |= TXGBE_LINK_SPEED_1GB_FULL;
608 if (speed_ability & TXGBE_MD_PHY_SPEED_100M)
609 hw->phy.speeds_supported |= TXGBE_LINK_SPEED_100M_FULL;
615 * txgbe_get_copper_link_capabilities - Determines link capabilities
616 * @hw: pointer to hardware structure
617 * @speed: pointer to link speed
618 * @autoneg: boolean auto-negotiation value
620 s32 txgbe_get_copper_link_capabilities(struct txgbe_hw *hw,
626 DEBUGFUNC("txgbe_get_copper_link_capabilities");
629 if (!hw->phy.speeds_supported)
630 err = txgbe_get_copper_speeds_supported(hw);
632 *speed = hw->phy.speeds_supported;
637 * txgbe_check_phy_link_tnx - Determine link and speed status
638 * @hw: pointer to hardware structure
639 * @speed: current link speed
640 * @link_up: true is link is up, false otherwise
642 * Reads the VS1 register to determine if link is up and the current speed for
645 s32 txgbe_check_phy_link_tnx(struct txgbe_hw *hw, u32 *speed,
650 u32 max_time_out = 10;
655 DEBUGFUNC("txgbe_check_phy_link_tnx");
657 /* Initialize speed and link to default case */
659 *speed = TXGBE_LINK_SPEED_10GB_FULL;
662 * Check current speed and link status of the PHY register.
663 * This is a vendor specific register and may have to
664 * be changed for other copper PHYs.
666 for (time_out = 0; time_out < max_time_out; time_out++) {
668 err = hw->phy.read_reg(hw,
669 TXGBE_MD_VENDOR_SPECIFIC_1_STATUS,
670 TXGBE_MD_DEV_VENDOR_1,
672 phy_link = phy_data & TXGBE_MD_VENDOR_SPECIFIC_1_LINK_STATUS;
673 phy_speed = phy_data &
674 TXGBE_MD_VENDOR_SPECIFIC_1_SPEED_STATUS;
675 if (phy_link == TXGBE_MD_VENDOR_SPECIFIC_1_LINK_STATUS) {
678 TXGBE_MD_VENDOR_SPECIFIC_1_SPEED_STATUS)
679 *speed = TXGBE_LINK_SPEED_1GB_FULL;
688 * txgbe_setup_phy_link_tnx - Set and restart auto-neg
689 * @hw: pointer to hardware structure
691 * Restart auto-negotiation and PHY and waits for completion.
693 s32 txgbe_setup_phy_link_tnx(struct txgbe_hw *hw)
696 u16 autoneg_reg = TXGBE_MII_AUTONEG_REG;
697 bool autoneg = false;
700 DEBUGFUNC("txgbe_setup_phy_link_tnx");
702 txgbe_get_copper_link_capabilities(hw, &speed, &autoneg);
704 if (speed & TXGBE_LINK_SPEED_10GB_FULL) {
705 /* Set or unset auto-negotiation 10G advertisement */
706 hw->phy.read_reg(hw, TXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
707 TXGBE_MD_DEV_AUTO_NEG,
710 autoneg_reg &= ~TXGBE_MII_10GBASE_T_ADVERTISE;
711 if (hw->phy.autoneg_advertised & TXGBE_LINK_SPEED_10GB_FULL)
712 autoneg_reg |= TXGBE_MII_10GBASE_T_ADVERTISE;
714 hw->phy.write_reg(hw, TXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
715 TXGBE_MD_DEV_AUTO_NEG,
719 if (speed & TXGBE_LINK_SPEED_1GB_FULL) {
720 /* Set or unset auto-negotiation 1G advertisement */
721 hw->phy.read_reg(hw, TXGBE_MII_AUTONEG_XNP_TX_REG,
722 TXGBE_MD_DEV_AUTO_NEG,
725 autoneg_reg &= ~TXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
726 if (hw->phy.autoneg_advertised & TXGBE_LINK_SPEED_1GB_FULL)
727 autoneg_reg |= TXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
729 hw->phy.write_reg(hw, TXGBE_MII_AUTONEG_XNP_TX_REG,
730 TXGBE_MD_DEV_AUTO_NEG,
734 if (speed & TXGBE_LINK_SPEED_100M_FULL) {
735 /* Set or unset auto-negotiation 100M advertisement */
736 hw->phy.read_reg(hw, TXGBE_MII_AUTONEG_ADVERTISE_REG,
737 TXGBE_MD_DEV_AUTO_NEG,
740 autoneg_reg &= ~TXGBE_MII_100BASE_T_ADVERTISE;
741 if (hw->phy.autoneg_advertised & TXGBE_LINK_SPEED_100M_FULL)
742 autoneg_reg |= TXGBE_MII_100BASE_T_ADVERTISE;
744 hw->phy.write_reg(hw, TXGBE_MII_AUTONEG_ADVERTISE_REG,
745 TXGBE_MD_DEV_AUTO_NEG,
749 /* Blocked by MNG FW so don't reset PHY */
750 if (txgbe_check_reset_blocked(hw))
753 /* Restart PHY auto-negotiation. */
754 hw->phy.read_reg(hw, TXGBE_MD_AUTO_NEG_CONTROL,
755 TXGBE_MD_DEV_AUTO_NEG, &autoneg_reg);
757 autoneg_reg |= TXGBE_MII_RESTART;
759 hw->phy.write_reg(hw, TXGBE_MD_AUTO_NEG_CONTROL,
760 TXGBE_MD_DEV_AUTO_NEG, autoneg_reg);
766 * txgbe_identify_module - Identifies module type
767 * @hw: pointer to hardware structure
769 * Determines HW type and calls appropriate function.
771 s32 txgbe_identify_module(struct txgbe_hw *hw)
773 s32 err = TXGBE_ERR_SFP_NOT_PRESENT;
775 DEBUGFUNC("txgbe_identify_module");
777 switch (hw->phy.media_type) {
778 case txgbe_media_type_fiber:
779 err = txgbe_identify_sfp_module(hw);
782 case txgbe_media_type_fiber_qsfp:
783 err = txgbe_identify_qsfp_module(hw);
787 hw->phy.sfp_type = txgbe_sfp_type_not_present;
788 err = TXGBE_ERR_SFP_NOT_PRESENT;
796 * txgbe_identify_sfp_module - Identifies SFP modules
797 * @hw: pointer to hardware structure
799 * Searches for and identifies the SFP module and assigns appropriate PHY type.
801 s32 txgbe_identify_sfp_module(struct txgbe_hw *hw)
803 s32 err = TXGBE_ERR_PHY_ADDR_INVALID;
805 enum txgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
807 u8 comp_codes_1g = 0;
808 u8 comp_codes_10g = 0;
809 u8 oui_bytes[3] = {0, 0, 0};
814 DEBUGFUNC("txgbe_identify_sfp_module");
816 if (hw->phy.media_type != txgbe_media_type_fiber) {
817 hw->phy.sfp_type = txgbe_sfp_type_not_present;
818 return TXGBE_ERR_SFP_NOT_PRESENT;
821 err = hw->phy.read_i2c_eeprom(hw, TXGBE_SFF_IDENTIFIER,
825 hw->phy.sfp_type = txgbe_sfp_type_not_present;
826 if (hw->phy.type != txgbe_phy_nl) {
828 hw->phy.type = txgbe_phy_unknown;
830 return TXGBE_ERR_SFP_NOT_PRESENT;
833 if (identifier != TXGBE_SFF_IDENTIFIER_SFP) {
834 hw->phy.type = txgbe_phy_sfp_unsupported;
835 return TXGBE_ERR_SFP_NOT_SUPPORTED;
838 err = hw->phy.read_i2c_eeprom(hw, TXGBE_SFF_1GBE_COMP_CODES,
843 err = hw->phy.read_i2c_eeprom(hw, TXGBE_SFF_10GBE_COMP_CODES,
848 err = hw->phy.read_i2c_eeprom(hw, TXGBE_SFF_CABLE_TECHNOLOGY,
858 * 3 SFP_DA_CORE0 - chip-specific
859 * 4 SFP_DA_CORE1 - chip-specific
860 * 5 SFP_SR/LR_CORE0 - chip-specific
861 * 6 SFP_SR/LR_CORE1 - chip-specific
862 * 7 SFP_act_lmt_DA_CORE0 - chip-specific
863 * 8 SFP_act_lmt_DA_CORE1 - chip-specific
864 * 9 SFP_1g_cu_CORE0 - chip-specific
865 * 10 SFP_1g_cu_CORE1 - chip-specific
866 * 11 SFP_1g_sx_CORE0 - chip-specific
867 * 12 SFP_1g_sx_CORE1 - chip-specific
869 if (cable_tech & TXGBE_SFF_CABLE_DA_PASSIVE) {
870 if (hw->bus.lan_id == 0)
871 hw->phy.sfp_type = txgbe_sfp_type_da_cu_core0;
873 hw->phy.sfp_type = txgbe_sfp_type_da_cu_core1;
874 } else if (cable_tech & TXGBE_SFF_CABLE_DA_ACTIVE) {
875 err = hw->phy.read_i2c_eeprom(hw,
876 TXGBE_SFF_CABLE_SPEC_COMP, &cable_spec);
879 if (cable_spec & TXGBE_SFF_DA_SPEC_ACTIVE_LIMITING) {
880 hw->phy.sfp_type = (hw->bus.lan_id == 0
881 ? txgbe_sfp_type_da_act_lmt_core0
882 : txgbe_sfp_type_da_act_lmt_core1);
884 hw->phy.sfp_type = txgbe_sfp_type_unknown;
886 } else if (comp_codes_10g &
887 (TXGBE_SFF_10GBASESR_CAPABLE |
888 TXGBE_SFF_10GBASELR_CAPABLE)) {
889 hw->phy.sfp_type = (hw->bus.lan_id == 0
890 ? txgbe_sfp_type_srlr_core0
891 : txgbe_sfp_type_srlr_core1);
892 } else if (comp_codes_1g & TXGBE_SFF_1GBASET_CAPABLE) {
893 hw->phy.sfp_type = (hw->bus.lan_id == 0
894 ? txgbe_sfp_type_1g_cu_core0
895 : txgbe_sfp_type_1g_cu_core1);
896 } else if (comp_codes_1g & TXGBE_SFF_1GBASESX_CAPABLE) {
897 hw->phy.sfp_type = (hw->bus.lan_id == 0
898 ? txgbe_sfp_type_1g_sx_core0
899 : txgbe_sfp_type_1g_sx_core1);
900 } else if (comp_codes_1g & TXGBE_SFF_1GBASELX_CAPABLE) {
901 hw->phy.sfp_type = (hw->bus.lan_id == 0
902 ? txgbe_sfp_type_1g_lx_core0
903 : txgbe_sfp_type_1g_lx_core1);
905 hw->phy.sfp_type = txgbe_sfp_type_unknown;
908 if (hw->phy.sfp_type != stored_sfp_type)
909 hw->phy.sfp_setup_needed = true;
911 /* Determine if the SFP+ PHY is dual speed or not. */
912 hw->phy.multispeed_fiber = false;
913 if (((comp_codes_1g & TXGBE_SFF_1GBASESX_CAPABLE) &&
914 (comp_codes_10g & TXGBE_SFF_10GBASESR_CAPABLE)) ||
915 ((comp_codes_1g & TXGBE_SFF_1GBASELX_CAPABLE) &&
916 (comp_codes_10g & TXGBE_SFF_10GBASELR_CAPABLE)))
917 hw->phy.multispeed_fiber = true;
919 /* Determine PHY vendor */
920 if (hw->phy.type != txgbe_phy_nl) {
921 hw->phy.id = identifier;
922 err = hw->phy.read_i2c_eeprom(hw,
923 TXGBE_SFF_VENDOR_OUI_BYTE0, &oui_bytes[0]);
927 err = hw->phy.read_i2c_eeprom(hw,
928 TXGBE_SFF_VENDOR_OUI_BYTE1, &oui_bytes[1]);
932 err = hw->phy.read_i2c_eeprom(hw,
933 TXGBE_SFF_VENDOR_OUI_BYTE2, &oui_bytes[2]);
937 vendor_oui = ((u32)oui_bytes[0] << 24) |
938 ((u32)oui_bytes[1] << 16) |
939 ((u32)oui_bytes[2] << 8);
940 switch (vendor_oui) {
941 case TXGBE_SFF_VENDOR_OUI_TYCO:
942 if (cable_tech & TXGBE_SFF_CABLE_DA_PASSIVE)
943 hw->phy.type = txgbe_phy_sfp_tyco_passive;
945 case TXGBE_SFF_VENDOR_OUI_FTL:
946 if (cable_tech & TXGBE_SFF_CABLE_DA_ACTIVE)
947 hw->phy.type = txgbe_phy_sfp_ftl_active;
949 hw->phy.type = txgbe_phy_sfp_ftl;
951 case TXGBE_SFF_VENDOR_OUI_AVAGO:
952 hw->phy.type = txgbe_phy_sfp_avago;
954 case TXGBE_SFF_VENDOR_OUI_INTEL:
955 hw->phy.type = txgbe_phy_sfp_intel;
958 if (cable_tech & TXGBE_SFF_CABLE_DA_PASSIVE)
959 hw->phy.type = txgbe_phy_sfp_unknown_passive;
960 else if (cable_tech & TXGBE_SFF_CABLE_DA_ACTIVE)
961 hw->phy.type = txgbe_phy_sfp_unknown_active;
963 hw->phy.type = txgbe_phy_sfp_unknown;
968 /* Allow any DA cable vendor */
969 if (cable_tech & (TXGBE_SFF_CABLE_DA_PASSIVE |
970 TXGBE_SFF_CABLE_DA_ACTIVE)) {
974 /* Verify supported 1G SFP modules */
975 if (comp_codes_10g == 0 &&
976 !(hw->phy.sfp_type == txgbe_sfp_type_1g_cu_core1 ||
977 hw->phy.sfp_type == txgbe_sfp_type_1g_cu_core0 ||
978 hw->phy.sfp_type == txgbe_sfp_type_1g_lx_core0 ||
979 hw->phy.sfp_type == txgbe_sfp_type_1g_lx_core1 ||
980 hw->phy.sfp_type == txgbe_sfp_type_1g_sx_core0 ||
981 hw->phy.sfp_type == txgbe_sfp_type_1g_sx_core1)) {
982 hw->phy.type = txgbe_phy_sfp_unsupported;
983 return TXGBE_ERR_SFP_NOT_SUPPORTED;
986 hw->mac.get_device_caps(hw, &enforce_sfp);
987 if (!(enforce_sfp & TXGBE_DEVICE_CAPS_ALLOW_ANY_SFP) &&
988 !hw->allow_unsupported_sfp &&
989 !(hw->phy.sfp_type == txgbe_sfp_type_1g_cu_core0 ||
990 hw->phy.sfp_type == txgbe_sfp_type_1g_cu_core1 ||
991 hw->phy.sfp_type == txgbe_sfp_type_1g_lx_core0 ||
992 hw->phy.sfp_type == txgbe_sfp_type_1g_lx_core1 ||
993 hw->phy.sfp_type == txgbe_sfp_type_1g_sx_core0 ||
994 hw->phy.sfp_type == txgbe_sfp_type_1g_sx_core1)) {
995 DEBUGOUT("SFP+ module not supported\n");
996 hw->phy.type = txgbe_phy_sfp_unsupported;
997 return TXGBE_ERR_SFP_NOT_SUPPORTED;
1004 * txgbe_identify_qsfp_module - Identifies QSFP modules
1005 * @hw: pointer to hardware structure
1007 * Searches for and identifies the QSFP module and assigns appropriate PHY type
1009 s32 txgbe_identify_qsfp_module(struct txgbe_hw *hw)
1011 s32 err = TXGBE_ERR_PHY_ADDR_INVALID;
1013 enum txgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
1015 u8 comp_codes_1g = 0;
1016 u8 comp_codes_10g = 0;
1017 u8 oui_bytes[3] = {0, 0, 0};
1018 u16 enforce_sfp = 0;
1020 u8 cable_length = 0;
1022 bool active_cable = false;
1024 DEBUGFUNC("txgbe_identify_qsfp_module");
1026 if (hw->phy.media_type != txgbe_media_type_fiber_qsfp) {
1027 hw->phy.sfp_type = txgbe_sfp_type_not_present;
1028 err = TXGBE_ERR_SFP_NOT_PRESENT;
1032 err = hw->phy.read_i2c_eeprom(hw, TXGBE_SFF_IDENTIFIER,
1036 hw->phy.sfp_type = txgbe_sfp_type_not_present;
1038 hw->phy.type = txgbe_phy_unknown;
1039 return TXGBE_ERR_SFP_NOT_PRESENT;
1041 if (identifier != TXGBE_SFF_IDENTIFIER_QSFP_PLUS) {
1042 hw->phy.type = txgbe_phy_sfp_unsupported;
1043 err = TXGBE_ERR_SFP_NOT_SUPPORTED;
1047 hw->phy.id = identifier;
1049 err = hw->phy.read_i2c_eeprom(hw, TXGBE_SFF_QSFP_10GBE_COMP,
1055 err = hw->phy.read_i2c_eeprom(hw, TXGBE_SFF_QSFP_1GBE_COMP,
1061 if (comp_codes_10g & TXGBE_SFF_QSFP_DA_PASSIVE_CABLE) {
1062 hw->phy.type = txgbe_phy_qsfp_unknown_passive;
1063 if (hw->bus.lan_id == 0)
1064 hw->phy.sfp_type = txgbe_sfp_type_da_cu_core0;
1066 hw->phy.sfp_type = txgbe_sfp_type_da_cu_core1;
1067 } else if (comp_codes_10g & (TXGBE_SFF_10GBASESR_CAPABLE |
1068 TXGBE_SFF_10GBASELR_CAPABLE)) {
1069 if (hw->bus.lan_id == 0)
1070 hw->phy.sfp_type = txgbe_sfp_type_srlr_core0;
1072 hw->phy.sfp_type = txgbe_sfp_type_srlr_core1;
1074 if (comp_codes_10g & TXGBE_SFF_QSFP_DA_ACTIVE_CABLE)
1075 active_cable = true;
1077 if (!active_cable) {
1078 hw->phy.read_i2c_eeprom(hw,
1079 TXGBE_SFF_QSFP_CONNECTOR,
1082 hw->phy.read_i2c_eeprom(hw,
1083 TXGBE_SFF_QSFP_CABLE_LENGTH,
1086 hw->phy.read_i2c_eeprom(hw,
1087 TXGBE_SFF_QSFP_DEVICE_TECH,
1091 TXGBE_SFF_QSFP_CONNECTOR_NOT_SEPARABLE &&
1093 ((device_tech >> 4) ==
1094 TXGBE_SFF_QSFP_TRANSMITTER_850NM_VCSEL))
1095 active_cable = true;
1099 hw->phy.type = txgbe_phy_qsfp_unknown_active;
1100 if (hw->bus.lan_id == 0)
1102 txgbe_sfp_type_da_act_lmt_core0;
1105 txgbe_sfp_type_da_act_lmt_core1;
1107 /* unsupported module type */
1108 hw->phy.type = txgbe_phy_sfp_unsupported;
1109 err = TXGBE_ERR_SFP_NOT_SUPPORTED;
1114 if (hw->phy.sfp_type != stored_sfp_type)
1115 hw->phy.sfp_setup_needed = true;
1117 /* Determine if the QSFP+ PHY is dual speed or not. */
1118 hw->phy.multispeed_fiber = false;
1119 if (((comp_codes_1g & TXGBE_SFF_1GBASESX_CAPABLE) &&
1120 (comp_codes_10g & TXGBE_SFF_10GBASESR_CAPABLE)) ||
1121 ((comp_codes_1g & TXGBE_SFF_1GBASELX_CAPABLE) &&
1122 (comp_codes_10g & TXGBE_SFF_10GBASELR_CAPABLE)))
1123 hw->phy.multispeed_fiber = true;
1125 /* Determine PHY vendor for optical modules */
1126 if (comp_codes_10g & (TXGBE_SFF_10GBASESR_CAPABLE |
1127 TXGBE_SFF_10GBASELR_CAPABLE)) {
1128 err = hw->phy.read_i2c_eeprom(hw,
1129 TXGBE_SFF_QSFP_VENDOR_OUI_BYTE0,
1135 err = hw->phy.read_i2c_eeprom(hw,
1136 TXGBE_SFF_QSFP_VENDOR_OUI_BYTE1,
1142 err = hw->phy.read_i2c_eeprom(hw,
1143 TXGBE_SFF_QSFP_VENDOR_OUI_BYTE2,
1150 ((oui_bytes[0] << 24) |
1151 (oui_bytes[1] << 16) |
1152 (oui_bytes[2] << 8));
1154 if (vendor_oui == TXGBE_SFF_VENDOR_OUI_INTEL)
1155 hw->phy.type = txgbe_phy_qsfp_intel;
1157 hw->phy.type = txgbe_phy_qsfp_unknown;
1159 hw->mac.get_device_caps(hw, &enforce_sfp);
1160 if (!(enforce_sfp & TXGBE_DEVICE_CAPS_ALLOW_ANY_SFP)) {
1161 /* Make sure we're a supported PHY type */
1162 if (hw->phy.type == txgbe_phy_qsfp_intel) {
1165 if (hw->allow_unsupported_sfp) {
1166 DEBUGOUT("WARNING: Wangxun (R) Network Connections are quality tested using Wangxun (R) Ethernet Optics. "
1167 "Using untested modules is not supported and may cause unstable operation or damage to the module or the adapter. "
1168 "Wangxun Corporation is not responsible for any harm caused by using untested modules.\n");
1171 DEBUGOUT("QSFP module not supported\n");
1173 txgbe_phy_sfp_unsupported;
1174 err = TXGBE_ERR_SFP_NOT_SUPPORTED;
1187 * txgbe_read_i2c_eeprom - Reads 8 bit EEPROM word over I2C interface
1188 * @hw: pointer to hardware structure
1189 * @byte_offset: EEPROM byte offset to read
1190 * @eeprom_data: value read
1192 * Performs byte read operation to SFP module's EEPROM over I2C interface.
1194 s32 txgbe_read_i2c_eeprom(struct txgbe_hw *hw, u8 byte_offset,
1197 DEBUGFUNC("txgbe_read_i2c_eeprom");
1199 return hw->phy.read_i2c_byte(hw, byte_offset,
1200 TXGBE_I2C_EEPROM_DEV_ADDR,
1205 * txgbe_read_i2c_sff8472 - Reads 8 bit word over I2C interface
1206 * @hw: pointer to hardware structure
1207 * @byte_offset: byte offset at address 0xA2
1208 * @sff8472_data: value read
1210 * Performs byte read operation to SFP module's SFF-8472 data over I2C
1212 s32 txgbe_read_i2c_sff8472(struct txgbe_hw *hw, u8 byte_offset,
1215 return hw->phy.read_i2c_byte(hw, byte_offset,
1216 TXGBE_I2C_EEPROM_DEV_ADDR2,
1221 * txgbe_write_i2c_eeprom - Writes 8 bit EEPROM word over I2C interface
1222 * @hw: pointer to hardware structure
1223 * @byte_offset: EEPROM byte offset to write
1224 * @eeprom_data: value to write
1226 * Performs byte write operation to SFP module's EEPROM over I2C interface.
1228 s32 txgbe_write_i2c_eeprom(struct txgbe_hw *hw, u8 byte_offset,
1231 DEBUGFUNC("txgbe_write_i2c_eeprom");
1233 return hw->phy.write_i2c_byte(hw, byte_offset,
1234 TXGBE_I2C_EEPROM_DEV_ADDR,
1239 * txgbe_read_i2c_byte_unlocked - Reads 8 bit word over I2C
1240 * @hw: pointer to hardware structure
1241 * @byte_offset: byte offset to read
1242 * @dev_addr: address to read from
1245 * Performs byte read operation to SFP module's EEPROM over I2C interface at
1246 * a specified device address.
1248 s32 txgbe_read_i2c_byte_unlocked(struct txgbe_hw *hw, u8 byte_offset,
1249 u8 dev_addr, u8 *data)
1251 DEBUGFUNC("txgbe_read_i2c_byte");
1253 txgbe_i2c_start(hw, dev_addr);
1256 if (!po32m(hw, TXGBE_I2CICR, TXGBE_I2CICR_TXEMPTY,
1257 TXGBE_I2CICR_TXEMPTY, NULL, 100, 100)) {
1258 return -TERR_TIMEOUT;
1262 wr32(hw, TXGBE_I2CDATA,
1263 byte_offset | TXGBE_I2CDATA_STOP);
1264 wr32(hw, TXGBE_I2CDATA, TXGBE_I2CDATA_READ);
1266 /* wait for read complete */
1267 if (!po32m(hw, TXGBE_I2CICR, TXGBE_I2CICR_RXFULL,
1268 TXGBE_I2CICR_RXFULL, NULL, 100, 100)) {
1269 return -TERR_TIMEOUT;
1274 *data = 0xFF & rd32(hw, TXGBE_I2CDATA);
1280 * txgbe_read_i2c_byte - Reads 8 bit word over I2C
1281 * @hw: pointer to hardware structure
1282 * @byte_offset: byte offset to read
1283 * @dev_addr: address to read from
1286 * Performs byte read operation to SFP module's EEPROM over I2C interface at
1287 * a specified device address.
1289 s32 txgbe_read_i2c_byte(struct txgbe_hw *hw, u8 byte_offset,
1290 u8 dev_addr, u8 *data)
1292 u32 swfw_mask = hw->phy.phy_semaphore_mask;
1295 if (hw->mac.acquire_swfw_sync(hw, swfw_mask))
1296 return TXGBE_ERR_SWFW_SYNC;
1297 err = txgbe_read_i2c_byte_unlocked(hw, byte_offset, dev_addr, data);
1298 hw->mac.release_swfw_sync(hw, swfw_mask);
1303 * txgbe_write_i2c_byte_unlocked - Writes 8 bit word over I2C
1304 * @hw: pointer to hardware structure
1305 * @byte_offset: byte offset to write
1306 * @dev_addr: address to write to
1307 * @data: value to write
1309 * Performs byte write operation to SFP module's EEPROM over I2C interface at
1310 * a specified device address.
1312 s32 txgbe_write_i2c_byte_unlocked(struct txgbe_hw *hw, u8 byte_offset,
1313 u8 dev_addr, u8 data)
1315 DEBUGFUNC("txgbe_write_i2c_byte");
1317 txgbe_i2c_start(hw, dev_addr);
1320 if (!po32m(hw, TXGBE_I2CICR, TXGBE_I2CICR_TXEMPTY,
1321 TXGBE_I2CICR_TXEMPTY, NULL, 100, 100)) {
1322 return -TERR_TIMEOUT;
1325 wr32(hw, TXGBE_I2CDATA, byte_offset | TXGBE_I2CDATA_STOP);
1326 wr32(hw, TXGBE_I2CDATA, data | TXGBE_I2CDATA_WRITE);
1328 /* wait for write complete */
1329 if (!po32m(hw, TXGBE_I2CICR, TXGBE_I2CICR_RXFULL,
1330 TXGBE_I2CICR_RXFULL, NULL, 100, 100)) {
1331 return -TERR_TIMEOUT;
1339 * txgbe_write_i2c_byte - Writes 8 bit word over I2C
1340 * @hw: pointer to hardware structure
1341 * @byte_offset: byte offset to write
1342 * @dev_addr: address to write to
1343 * @data: value to write
1345 * Performs byte write operation to SFP module's EEPROM over I2C interface at
1346 * a specified device address.
1348 s32 txgbe_write_i2c_byte(struct txgbe_hw *hw, u8 byte_offset,
1349 u8 dev_addr, u8 data)
1351 u32 swfw_mask = hw->phy.phy_semaphore_mask;
1354 if (hw->mac.acquire_swfw_sync(hw, swfw_mask))
1355 return TXGBE_ERR_SWFW_SYNC;
1356 err = txgbe_write_i2c_byte_unlocked(hw, byte_offset, dev_addr, data);
1357 hw->mac.release_swfw_sync(hw, swfw_mask);
1363 * txgbe_i2c_start - Sets I2C start condition
1364 * @hw: pointer to hardware structure
1366 * Sets I2C start condition (High -> Low on SDA while SCL is High)
1368 static void txgbe_i2c_start(struct txgbe_hw *hw, u8 dev_addr)
1370 DEBUGFUNC("txgbe_i2c_start");
1372 wr32(hw, TXGBE_I2CENA, 0);
1374 wr32(hw, TXGBE_I2CCON,
1375 (TXGBE_I2CCON_MENA |
1376 TXGBE_I2CCON_SPEED(1) |
1377 TXGBE_I2CCON_RESTART |
1378 TXGBE_I2CCON_SDIA));
1379 wr32(hw, TXGBE_I2CTAR, dev_addr >> 1);
1380 wr32(hw, TXGBE_I2CSSSCLHCNT, 200);
1381 wr32(hw, TXGBE_I2CSSSCLLCNT, 200);
1382 wr32(hw, TXGBE_I2CRXTL, 0); /* 1byte for rx full signal */
1383 wr32(hw, TXGBE_I2CTXTL, 4);
1384 wr32(hw, TXGBE_I2CSCLTMOUT, 0xFFFFFF);
1385 wr32(hw, TXGBE_I2CSDATMOUT, 0xFFFFFF);
1387 wr32(hw, TXGBE_I2CICM, 0);
1388 wr32(hw, TXGBE_I2CENA, 1);
1392 * txgbe_i2c_stop - Sets I2C stop condition
1393 * @hw: pointer to hardware structure
1395 * Sets I2C stop condition (Low -> High on SDA while SCL is High)
1397 static void txgbe_i2c_stop(struct txgbe_hw *hw)
1399 DEBUGFUNC("txgbe_i2c_stop");
1401 /* wait for completion */
1402 if (!po32m(hw, TXGBE_I2CSTAT, TXGBE_I2CSTAT_MST,
1403 0, NULL, 100, 100)) {
1404 DEBUGFUNC("i2c stop timeout.");
1407 wr32(hw, TXGBE_I2CENA, 0);
1411 txgbe_set_sgmii_an37_ability(struct txgbe_hw *hw)
1415 wr32_epcs(hw, VR_XS_OR_PCS_MMD_DIGI_CTL1, 0x3002);
1416 wr32_epcs(hw, SR_MII_MMD_AN_CTL, 0x0105);
1417 wr32_epcs(hw, SR_MII_MMD_DIGI_CTL, 0x0200);
1418 value = rd32_epcs(hw, SR_MII_MMD_CTL);
1419 value = (value & ~0x1200) | (0x1 << 12) | (0x1 << 9);
1420 wr32_epcs(hw, SR_MII_MMD_CTL, value);
1424 txgbe_set_link_to_kr(struct txgbe_hw *hw, bool autoneg)
1430 /* 1. Wait xpcs power-up good */
1431 for (i = 0; i < 100; i++) {
1432 if ((rd32_epcs(hw, VR_XS_OR_PCS_MMD_DIGI_STATUS) &
1433 VR_XS_OR_PCS_MMD_DIGI_STATUS_PSEQ_MASK) ==
1434 VR_XS_OR_PCS_MMD_DIGI_STATUS_PSEQ_POWER_GOOD)
1439 err = TXGBE_ERR_XPCS_POWER_UP_FAILED;
1442 BP_LOG("It is set to kr.\n");
1444 wr32_epcs(hw, VR_AN_INTR_MSK, 0x7);
1445 wr32_epcs(hw, TXGBE_PHY_TX_POWER_ST_CTL, 0x00FC);
1446 wr32_epcs(hw, TXGBE_PHY_RX_POWER_ST_CTL, 0x00FC);
1449 /* 2. Disable xpcs AN-73 */
1450 wr32_epcs(hw, SR_AN_CTRL,
1451 SR_AN_CTRL_AN_EN | SR_AN_CTRL_EXT_NP);
1453 wr32_epcs(hw, VR_AN_KR_MODE_CL, VR_AN_KR_MODE_CL_PDET);
1455 if (!(hw->devarg.auto_neg == 1)) {
1456 wr32_epcs(hw, SR_AN_CTRL, 0);
1457 wr32_epcs(hw, VR_AN_KR_MODE_CL, 0);
1459 if (hw->devarg.present == 1) {
1460 value = rd32_epcs(hw, TXGBE_PHY_TX_EQ_CTL1);
1461 value |= TXGBE_PHY_TX_EQ_CTL1_DEF;
1462 wr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL1, value);
1464 if (hw->devarg.poll == 1) {
1465 wr32_epcs(hw, VR_PMA_KRTR_TIMER_CTRL0,
1466 VR_PMA_KRTR_TIMER_MAX_WAIT);
1467 wr32_epcs(hw, VR_PMA_KRTR_TIMER_CTRL2, 0xA697);
1470 /* 3. Set VR_XS_PMA_Gen5_12G_MPLLA_CTRL3 Register
1471 * Bit[10:0](MPLLA_BANDWIDTH) = 11'd123 (default: 11'd16)
1473 wr32_epcs(hw, TXGBE_PHY_MPLLA_CTL3,
1474 TXGBE_PHY_MPLLA_CTL3_MULTIPLIER_BW_10GBASER_KR);
1476 /* 4. Set VR_XS_PMA_Gen5_12G_MISC_CTRL0 Register
1477 * Bit[12:8](RX_VREF_CTRL) = 5'hF (default: 5'h11)
1479 wr32_epcs(hw, TXGBE_PHY_MISC_CTL0, 0xCF00);
1481 /* 5. Set VR_XS_PMA_Gen5_12G_RX_EQ_CTRL0 Register
1482 * Bit[15:8](VGA1/2_GAIN_0) = 8'h77
1483 * Bit[7:5](CTLE_POLE_0) = 3'h2
1484 * Bit[4:0](CTLE_BOOST_0) = 4'hA
1486 wr32_epcs(hw, TXGBE_PHY_RX_EQ_CTL0, 0x774A);
1488 /* 6. Set VR_MII_Gen5_12G_RX_GENCTRL3 Register
1489 * Bit[2:0](LOS_TRSHLD_0) = 3'h4 (default: 3)
1491 wr32_epcs(hw, TXGBE_PHY_RX_GEN_CTL3, 0x0004);
1493 /* 7. Initialize the mode by setting VR XS or PCS MMD Digital
1494 * Control1 Register Bit[15](VR_RST)
1496 wr32_epcs(hw, VR_XS_OR_PCS_MMD_DIGI_CTL1, 0xA000);
1498 /* Wait phy initialization done */
1499 for (i = 0; i < 100; i++) {
1501 VR_XS_OR_PCS_MMD_DIGI_CTL1) &
1502 VR_XS_OR_PCS_MMD_DIGI_CTL1_VR_RST) == 0)
1507 err = TXGBE_ERR_PHY_INIT_NOT_DONE;
1511 wr32_epcs(hw, VR_AN_KR_MODE_CL, 0x1);
1514 if (hw->phy.ffe_set == TXGBE_BP_M_KR) {
1515 value = (0x1804 & ~0x3F3F);
1516 value |= hw->phy.ffe_main << 8 | hw->phy.ffe_pre;
1517 wr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL0, value);
1519 value = (0x50 & ~0x7F) | (1 << 6) | hw->phy.ffe_post;
1520 wr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL1, value);
1527 txgbe_set_link_to_kx4(struct txgbe_hw *hw, bool autoneg)
1533 /* Check link status, if already set, skip setting it again */
1534 if (hw->link_status == TXGBE_LINK_STATUS_KX4)
1537 BP_LOG("It is set to kx4.\n");
1538 wr32_epcs(hw, TXGBE_PHY_TX_POWER_ST_CTL, 0);
1539 wr32_epcs(hw, TXGBE_PHY_RX_POWER_ST_CTL, 0);
1541 /* 1. Wait xpcs power-up good */
1542 for (i = 0; i < 100; i++) {
1543 if ((rd32_epcs(hw, VR_XS_OR_PCS_MMD_DIGI_STATUS) &
1544 VR_XS_OR_PCS_MMD_DIGI_STATUS_PSEQ_MASK) ==
1545 VR_XS_OR_PCS_MMD_DIGI_STATUS_PSEQ_POWER_GOOD)
1550 err = TXGBE_ERR_XPCS_POWER_UP_FAILED;
1554 wr32m(hw, TXGBE_MACTXCFG, TXGBE_MACTXCFG_TXE,
1555 ~TXGBE_MACTXCFG_TXE);
1557 /* 2. Disable xpcs AN-73 */
1559 wr32_epcs(hw, SR_AN_CTRL, 0x0);
1561 wr32_epcs(hw, SR_AN_CTRL, 0x3000);
1563 /* Disable PHY MPLLA for eth mode change(after ECO) */
1564 wr32_ephy(hw, 0x4, 0x250A);
1568 /* Set the eth change_mode bit first in mis_rst register
1569 * for corresponding LAN port
1571 wr32(hw, TXGBE_RST, TXGBE_RST_ETH(hw->bus.lan_id));
1573 /* Set SR PCS Control2 Register Bits[1:0] = 2'b01
1574 * PCS_TYPE_SEL: non KR
1576 wr32_epcs(hw, SR_XS_PCS_CTRL2,
1577 SR_PCS_CTRL2_TYPE_SEL_X);
1579 /* Set SR PMA MMD Control1 Register Bit[13] = 1'b1
1582 wr32_epcs(hw, SR_PMA_CTRL1,
1583 SR_PMA_CTRL1_SS13_KX4);
1585 value = (0xf5f0 & ~0x7F0) | (0x5 << 8) | (0x7 << 5) | 0xF0;
1586 wr32_epcs(hw, TXGBE_PHY_TX_GENCTRL1, value);
1588 if ((hw->subsystem_device_id & 0xFF) == TXGBE_DEV_ID_MAC_XAUI)
1589 wr32_epcs(hw, TXGBE_PHY_MISC_CTL0, 0xCF00);
1591 wr32_epcs(hw, TXGBE_PHY_MISC_CTL0, 0x4F00);
1593 for (i = 0; i < 4; i++) {
1595 value = (0x45 & ~0xFFFF) | (0x7 << 12) |
1598 value = (0xff06 & ~0xFFFF) | (0x7 << 12) |
1600 wr32_epcs(hw, TXGBE_PHY_RX_EQ_CTL0 + i, value);
1603 value = 0x0 & ~0x7777;
1604 wr32_epcs(hw, TXGBE_PHY_RX_EQ_ATT_LVL0, value);
1606 wr32_epcs(hw, TXGBE_PHY_DFE_TAP_CTL0, 0x0);
1608 value = (0x6db & ~0xFFF) | (0x1 << 9) | (0x1 << 6) | (0x1 << 3) | 0x1;
1609 wr32_epcs(hw, TXGBE_PHY_RX_GEN_CTL3, value);
1611 /* Set VR XS, PMA, or MII Gen5 12G PHY MPLLA
1612 * Control 0 Register Bit[7:0] = 8'd40 //MPLLA_MULTIPLIER
1614 wr32_epcs(hw, TXGBE_PHY_MPLLA_CTL0,
1615 TXGBE_PHY_MPLLA_CTL0_MULTIPLIER_OTHER);
1617 /* Set VR XS, PMA or MII Gen5 12G PHY MPLLA
1618 * Control 3 Register Bit[10:0] = 11'd86 //MPLLA_BANDWIDTH
1620 wr32_epcs(hw, TXGBE_PHY_MPLLA_CTL3,
1621 TXGBE_PHY_MPLLA_CTL3_MULTIPLIER_BW_OTHER);
1623 /* Set VR XS, PMA, or MII Gen5 12G PHY VCO
1624 * Calibration Load 0 Register Bit[12:0] = 13'd1360 //VCO_LD_VAL_0
1626 wr32_epcs(hw, TXGBE_PHY_VCO_CAL_LD0,
1627 TXGBE_PHY_VCO_CAL_LD0_OTHER);
1629 /* Set VR XS, PMA, or MII Gen5 12G PHY VCO
1630 * Calibration Load 1 Register Bit[12:0] = 13'd1360 //VCO_LD_VAL_1
1632 wr32_epcs(hw, TXGBE_PHY_VCO_CAL_LD1,
1633 TXGBE_PHY_VCO_CAL_LD0_OTHER);
1635 /* Set VR XS, PMA, or MII Gen5 12G PHY VCO
1636 * Calibration Load 2 Register Bit[12:0] = 13'd1360 //VCO_LD_VAL_2
1638 wr32_epcs(hw, TXGBE_PHY_VCO_CAL_LD2,
1639 TXGBE_PHY_VCO_CAL_LD0_OTHER);
1640 /* Set VR XS, PMA, or MII Gen5 12G PHY VCO
1641 * Calibration Load 3 Register Bit[12:0] = 13'd1360 //VCO_LD_VAL_3
1643 wr32_epcs(hw, TXGBE_PHY_VCO_CAL_LD3,
1644 TXGBE_PHY_VCO_CAL_LD0_OTHER);
1645 /* Set VR XS, PMA, or MII Gen5 12G PHY VCO
1646 * Calibration Reference 0 Register Bit[5:0] = 6'd34 //VCO_REF_LD_0/1
1648 wr32_epcs(hw, TXGBE_PHY_VCO_CAL_REF0, 0x2222);
1650 /* Set VR XS, PMA, or MII Gen5 12G PHY VCO
1651 * Calibration Reference 1 Register Bit[5:0] = 6'd34 //VCO_REF_LD_2/3
1653 wr32_epcs(hw, TXGBE_PHY_VCO_CAL_REF1, 0x2222);
1655 /* Set VR XS, PMA, or MII Gen5 12G PHY AFE-DFE
1656 * Enable Register Bit[7:0] = 8'd0 //AFE_EN_0/3_1, DFE_EN_0/3_1
1658 wr32_epcs(hw, TXGBE_PHY_AFE_DFE_ENABLE, 0x0);
1660 /* Set VR XS, PMA, or MII Gen5 12G PHY Rx
1661 * Equalization Control 4 Register Bit[3:0] = 4'd0 //CONT_ADAPT_0/3_1
1663 wr32_epcs(hw, TXGBE_PHY_RX_EQ_CTL, 0x00F0);
1665 /* Set VR XS, PMA, or MII Gen5 12G PHY Tx Rate
1666 * Control Register Bit[14:12], Bit[10:8], Bit[6:4], Bit[2:0],
1667 * all rates to 3'b010 //TX0/1/2/3_RATE
1669 wr32_epcs(hw, TXGBE_PHY_TX_RATE_CTL, 0x2222);
1671 /* Set VR XS, PMA, or MII Gen5 12G PHY Rx Rate
1672 * Control Register Bit[13:12], Bit[9:8], Bit[5:4], Bit[1:0],
1673 * all rates to 2'b10 //RX0/1/2/3_RATE
1675 wr32_epcs(hw, TXGBE_PHY_RX_RATE_CTL, 0x2222);
1677 /* Set VR XS, PMA, or MII Gen5 12G PHY Tx General
1678 * Control 2 Register Bit[15:8] = 2'b01 //TX0/1/2/3_WIDTH: 10bits
1680 wr32_epcs(hw, TXGBE_PHY_TX_GEN_CTL2, 0x5500);
1682 /* Set VR XS, PMA, or MII Gen5 12G PHY Rx General
1683 * Control 2 Register Bit[15:8] = 2'b01 //RX0/1/2/3_WIDTH: 10bits
1685 wr32_epcs(hw, TXGBE_PHY_RX_GEN_CTL2, 0x5500);
1687 /* Set VR XS, PMA, or MII Gen5 12G PHY MPLLA Control
1688 * 2 Register Bit[10:8] = 3'b010
1689 * MPLLA_DIV16P5_CLK_EN=0, MPLLA_DIV10_CLK_EN=1, MPLLA_DIV8_CLK_EN=0
1691 wr32_epcs(hw, TXGBE_PHY_MPLLA_CTL2,
1692 TXGBE_PHY_MPLLA_CTL2_DIV_CLK_EN_10);
1694 wr32_epcs(hw, 0x1f0000, 0x0);
1695 wr32_epcs(hw, 0x1f8001, 0x0);
1696 wr32_epcs(hw, SR_MII_MMD_DIGI_CTL, 0x0);
1698 /* 10. Initialize the mode by setting VR XS or PCS MMD Digital Control1
1699 * Register Bit[15](VR_RST)
1701 wr32_epcs(hw, VR_XS_OR_PCS_MMD_DIGI_CTL1, 0xA000);
1703 /* Wait phy initialization done */
1704 for (i = 0; i < 100; i++) {
1705 if ((rd32_epcs(hw, VR_XS_OR_PCS_MMD_DIGI_CTL1) &
1706 VR_XS_OR_PCS_MMD_DIGI_CTL1_VR_RST) == 0)
1711 /* If success, set link status */
1712 hw->link_status = TXGBE_LINK_STATUS_KX4;
1715 err = TXGBE_ERR_PHY_INIT_NOT_DONE;
1719 if (hw->phy.ffe_set == TXGBE_BP_M_KX4) {
1720 value = (0x1804 & ~0x3F3F);
1721 value |= hw->phy.ffe_main << 8 | hw->phy.ffe_pre;
1722 wr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL0, value);
1724 value = (0x50 & ~0x7F) | (1 << 6) | hw->phy.ffe_post;
1725 wr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL1, value);
1726 } else if (hw->fw_version <= TXGBE_FW_N_TXEQ) {
1727 value = (0x1804 & ~0x3F3F);
1728 wr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL0, value);
1730 value = (0x50 & ~0x7F) | 40 | (1 << 6);
1731 wr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL1, value);
1738 txgbe_set_link_to_kx(struct txgbe_hw *hw,
1747 /* Check link status, if already set, skip setting it again */
1748 if (hw->link_status == TXGBE_LINK_STATUS_KX)
1751 BP_LOG("It is set to kx. speed =0x%x\n", speed);
1752 wr32_epcs(hw, TXGBE_PHY_TX_POWER_ST_CTL, 0x00FC);
1753 wr32_epcs(hw, TXGBE_PHY_RX_POWER_ST_CTL, 0x00FC);
1755 /* 1. Wait xpcs power-up good */
1756 for (i = 0; i < 100; i++) {
1757 if ((rd32_epcs(hw, VR_XS_OR_PCS_MMD_DIGI_STATUS) &
1758 VR_XS_OR_PCS_MMD_DIGI_STATUS_PSEQ_MASK) ==
1759 VR_XS_OR_PCS_MMD_DIGI_STATUS_PSEQ_POWER_GOOD)
1764 err = TXGBE_ERR_XPCS_POWER_UP_FAILED;
1768 wr32m(hw, TXGBE_MACTXCFG, TXGBE_MACTXCFG_TXE,
1769 ~TXGBE_MACTXCFG_TXE);
1771 /* 2. Disable xpcs AN-73 */
1773 wr32_epcs(hw, SR_AN_CTRL, 0x0);
1775 wr32_epcs(hw, SR_AN_CTRL, 0x3000);
1777 /* Disable PHY MPLLA for eth mode change(after ECO) */
1778 wr32_ephy(hw, 0x4, 0x240A);
1782 /* Set the eth change_mode bit first in mis_rst register
1783 * for corresponding LAN port
1785 wr32(hw, TXGBE_RST, TXGBE_RST_ETH(hw->bus.lan_id));
1787 /* Set SR PCS Control2 Register Bits[1:0] = 2'b01
1788 * PCS_TYPE_SEL: non KR
1790 wr32_epcs(hw, SR_XS_PCS_CTRL2,
1791 SR_PCS_CTRL2_TYPE_SEL_X);
1793 /* Set SR PMA MMD Control1 Register Bit[13] = 1'b0
1796 wr32_epcs(hw, SR_PMA_CTRL1,
1797 SR_PMA_CTRL1_SS13_KX);
1799 /* Set SR MII MMD Control Register to corresponding speed: {Bit[6],
1800 * Bit[13]}=[2'b00,2'b01,2'b10]->[10M,100M,1G]
1802 if (speed == TXGBE_LINK_SPEED_100M_FULL)
1804 else if (speed == TXGBE_LINK_SPEED_1GB_FULL)
1806 else if (speed == TXGBE_LINK_SPEED_10M_FULL)
1808 wr32_epcs(hw, SR_MII_MMD_CTL,
1811 value = (0xf5f0 & ~0x710) | (0x5 << 8) | 0x10;
1812 wr32_epcs(hw, TXGBE_PHY_TX_GENCTRL1, value);
1814 if (hw->devarg.sgmii == 1)
1815 wr32_epcs(hw, TXGBE_PHY_MISC_CTL0, 0x4F00);
1817 wr32_epcs(hw, TXGBE_PHY_MISC_CTL0, 0xCF00);
1819 for (i = 0; i < 4; i++) {
1823 value = (0x45 & ~0xFFFF) | (0x7 << 12) |
1826 wr32_epcs(hw, TXGBE_PHY_RX_EQ_CTL0 + i, value);
1830 wr32_epcs(hw, TXGBE_PHY_RX_EQ_ATT_LVL0, value);
1832 wr32_epcs(hw, TXGBE_PHY_DFE_TAP_CTL0, 0x0);
1834 value = (0x6db & ~0x7) | 0x4;
1835 wr32_epcs(hw, TXGBE_PHY_RX_GEN_CTL3, value);
1837 /* Set VR XS, PMA, or MII Gen5 12G PHY MPLLA Control
1838 * 0 Register Bit[7:0] = 8'd32 //MPLLA_MULTIPLIER
1840 wr32_epcs(hw, TXGBE_PHY_MPLLA_CTL0,
1841 TXGBE_PHY_MPLLA_CTL0_MULTIPLIER_1GBASEX_KX);
1843 /* Set VR XS, PMA or MII Gen5 12G PHY MPLLA Control
1844 * 3 Register Bit[10:0] = 11'd70 //MPLLA_BANDWIDTH
1846 wr32_epcs(hw, TXGBE_PHY_MPLLA_CTL3,
1847 TXGBE_PHY_MPLLA_CTL3_MULTIPLIER_BW_1GBASEX_KX);
1849 /* Set VR XS, PMA, or MII Gen5 12G PHY VCO
1850 * Calibration Load 0 Register Bit[12:0] = 13'd1344 //VCO_LD_VAL_0
1852 wr32_epcs(hw, TXGBE_PHY_VCO_CAL_LD0,
1853 TXGBE_PHY_VCO_CAL_LD0_1GBASEX_KX);
1855 wr32_epcs(hw, TXGBE_PHY_VCO_CAL_LD1, 0x549);
1856 wr32_epcs(hw, TXGBE_PHY_VCO_CAL_LD2, 0x549);
1857 wr32_epcs(hw, TXGBE_PHY_VCO_CAL_LD3, 0x549);
1859 /* Set VR XS, PMA, or MII Gen5 12G PHY VCO
1860 * Calibration Reference 0 Register Bit[5:0] = 6'd42 //VCO_REF_LD_0
1862 wr32_epcs(hw, TXGBE_PHY_VCO_CAL_REF0,
1863 TXGBE_PHY_VCO_CAL_REF0_LD0_1GBASEX_KX);
1865 wr32_epcs(hw, TXGBE_PHY_VCO_CAL_REF1, 0x2929);
1867 /* Set VR XS, PMA, or MII Gen5 12G PHY AFE-DFE
1868 * Enable Register Bit[4], Bit[0] = 1'b0 //AFE_EN_0, DFE_EN_0
1870 wr32_epcs(hw, TXGBE_PHY_AFE_DFE_ENABLE,
1872 /* Set VR XS, PMA, or MII Gen5 12G PHY Rx
1873 * Equalization Control 4 Register Bit[0] = 1'b0 //CONT_ADAPT_0
1875 wr32_epcs(hw, TXGBE_PHY_RX_EQ_CTL,
1877 /* Set VR XS, PMA, or MII Gen5 12G PHY Tx Rate
1878 * Control Register Bit[2:0] = 3'b011 //TX0_RATE
1880 wr32_epcs(hw, TXGBE_PHY_TX_RATE_CTL,
1881 TXGBE_PHY_TX_RATE_CTL_TX0_RATE_1GBASEX_KX);
1883 /* Set VR XS, PMA, or MII Gen5 12G PHY Rx Rate
1884 * Control Register Bit[2:0] = 3'b011 //RX0_RATE
1886 wr32_epcs(hw, TXGBE_PHY_RX_RATE_CTL,
1887 TXGBE_PHY_RX_RATE_CTL_RX0_RATE_1GBASEX_KX);
1889 /* Set VR XS, PMA, or MII Gen5 12G PHY Tx General
1890 * Control 2 Register Bit[9:8] = 2'b01 //TX0_WIDTH: 10bits
1892 wr32_epcs(hw, TXGBE_PHY_TX_GEN_CTL2,
1893 TXGBE_PHY_TX_GEN_CTL2_TX0_WIDTH_OTHER);
1894 /* Set VR XS, PMA, or MII Gen5 12G PHY Rx General
1895 * Control 2 Register Bit[9:8] = 2'b01 //RX0_WIDTH: 10bits
1897 wr32_epcs(hw, TXGBE_PHY_RX_GEN_CTL2,
1898 TXGBE_PHY_RX_GEN_CTL2_RX0_WIDTH_OTHER);
1899 /* Set VR XS, PMA, or MII Gen5 12G PHY MPLLA Control
1900 * 2 Register Bit[10:8] = 3'b010 //MPLLA_DIV16P5_CLK_EN=0,
1901 * MPLLA_DIV10_CLK_EN=1, MPLLA_DIV8_CLK_EN=0
1903 wr32_epcs(hw, TXGBE_PHY_MPLLA_CTL2,
1904 TXGBE_PHY_MPLLA_CTL2_DIV_CLK_EN_10);
1906 /* VR MII MMD AN Control Register Bit[8] = 1'b1 //MII_CTRL
1907 * Set to 8bit MII (required in 10M/100M SGMII)
1909 wr32_epcs(hw, SR_MII_MMD_AN_CTL,
1912 /* 10. Initialize the mode by setting VR XS or PCS MMD Digital Control1
1913 * Register Bit[15](VR_RST)
1915 wr32_epcs(hw, VR_XS_OR_PCS_MMD_DIGI_CTL1, 0xA000);
1917 /* Wait phy initialization done */
1918 for (i = 0; i < 100; i++) {
1919 if ((rd32_epcs(hw, VR_XS_OR_PCS_MMD_DIGI_CTL1) &
1920 VR_XS_OR_PCS_MMD_DIGI_CTL1_VR_RST) == 0)
1925 /* If success, set link status */
1926 hw->link_status = TXGBE_LINK_STATUS_KX;
1929 err = TXGBE_ERR_PHY_INIT_NOT_DONE;
1933 if (hw->phy.ffe_set == TXGBE_BP_M_KX) {
1934 value = rd32_epcs(hw, TXGBE_PHY_TX_EQ_CTL0) & ~0x3F3F;
1935 value |= hw->phy.ffe_main << 8 | hw->phy.ffe_pre;
1936 wr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL0, value);
1938 value = rd32_epcs(hw, TXGBE_PHY_TX_EQ_CTL0) & ~0x7F;
1939 value |= hw->phy.ffe_post | (1 << 6);
1940 wr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL1, value);
1941 } else if (hw->fw_version <= TXGBE_FW_N_TXEQ) {
1942 value = (0x1804 & ~0x3F3F) | (24 << 8) | 4;
1943 wr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL0, value);
1945 value = (0x50 & ~0x7F) | 16 | (1 << 6);
1946 wr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL1, value);
1953 txgbe_set_link_to_sfi(struct txgbe_hw *hw,
1960 /* Set the module link speed */
1961 hw->mac.set_rate_select_speed(hw, speed);
1962 /* 1. Wait xpcs power-up good */
1963 for (i = 0; i < 100; i++) {
1964 if ((rd32_epcs(hw, VR_XS_OR_PCS_MMD_DIGI_STATUS) &
1965 VR_XS_OR_PCS_MMD_DIGI_STATUS_PSEQ_MASK) ==
1966 VR_XS_OR_PCS_MMD_DIGI_STATUS_PSEQ_POWER_GOOD)
1971 err = TXGBE_ERR_XPCS_POWER_UP_FAILED;
1975 wr32m(hw, TXGBE_MACTXCFG, TXGBE_MACTXCFG_TXE,
1976 ~TXGBE_MACTXCFG_TXE);
1978 /* 2. Disable xpcs AN-73 */
1979 wr32_epcs(hw, SR_AN_CTRL, 0x0);
1981 /* Disable PHY MPLLA for eth mode change(after ECO) */
1982 wr32_ephy(hw, 0x4, 0x243A);
1985 /* Set the eth change_mode bit first in mis_rst register
1986 * for corresponding LAN port
1988 wr32(hw, TXGBE_RST, TXGBE_RST_ETH(hw->bus.lan_id));
1990 if (speed == TXGBE_LINK_SPEED_10GB_FULL) {
1991 /* Set SR PCS Control2 Register Bits[1:0] = 2'b00
1994 wr32_epcs(hw, SR_XS_PCS_CTRL2, 0);
1995 value = rd32_epcs(hw, SR_PMA_CTRL1);
1996 value = value | 0x2000;
1997 wr32_epcs(hw, SR_PMA_CTRL1, value);
1998 /* Set VR_XS_PMA_Gen5_12G_MPLLA_CTRL0 Register Bit[7:0] = 8'd33
2001 wr32_epcs(hw, TXGBE_PHY_MPLLA_CTL0, 0x0021);
2002 /* 3. Set VR_XS_PMA_Gen5_12G_MPLLA_CTRL3 Register
2003 * Bit[10:0](MPLLA_BANDWIDTH) = 11'd0
2005 wr32_epcs(hw, TXGBE_PHY_MPLLA_CTL3, 0);
2006 value = rd32_epcs(hw, TXGBE_PHY_TX_GENCTRL1);
2007 value = (value & ~0x700) | 0x500;
2008 wr32_epcs(hw, TXGBE_PHY_TX_GENCTRL1, value);
2009 /* 4. Set VR_XS_PMA_Gen5_12G_MISC_CTRL0 Register
2010 * Bit[12:8](RX_VREF_CTRL) = 5'hF
2012 wr32_epcs(hw, TXGBE_PHY_MISC_CTL0, 0xCF00);
2013 /* Set VR_XS_PMA_Gen5_12G_VCO_CAL_LD0 Register
2014 * Bit[12:0] = 13'd1353 //VCO_LD_VAL_0
2016 wr32_epcs(hw, TXGBE_PHY_VCO_CAL_LD0, 0x0549);
2017 /* Set VR_XS_PMA_Gen5_12G_VCO_CAL_REF0 Register
2018 * Bit[5:0] = 6'd41 //VCO_REF_LD_0
2020 wr32_epcs(hw, TXGBE_PHY_VCO_CAL_REF0, 0x0029);
2021 /* Set VR_XS_PMA_Gen5_12G_TX_RATE_CTRL Register
2022 * Bit[2:0] = 3'b000 //TX0_RATE
2024 wr32_epcs(hw, TXGBE_PHY_TX_RATE_CTL, 0);
2025 /* Set VR_XS_PMA_Gen5_12G_RX_RATE_CTRL Register
2026 * Bit[2:0] = 3'b000 //RX0_RATE
2028 wr32_epcs(hw, TXGBE_PHY_RX_RATE_CTL, 0);
2029 /* Set VR_XS_PMA_Gen5_12G_TX_GENCTRL2 Register Bit[9:8] = 2'b11
2032 wr32_epcs(hw, TXGBE_PHY_TX_GEN_CTL2, 0x0300);
2033 /* Set VR_XS_PMA_Gen5_12G_RX_GENCTRL2 Register Bit[9:8] = 2'b11
2036 wr32_epcs(hw, TXGBE_PHY_RX_GEN_CTL2, 0x0300);
2037 /* Set VR_XS_PMA_Gen5_12G_MPLLA_CTRL2 Register
2038 * Bit[10:8] = 3'b110
2039 * MPLLA_DIV16P5_CLK_EN=1
2040 * MPLLA_DIV10_CLK_EN=1
2041 * MPLLA_DIV8_CLK_EN=0
2043 wr32_epcs(hw, TXGBE_PHY_MPLLA_CTL2, 0x0600);
2045 if (hw->phy.sfp_type == txgbe_sfp_type_da_cu_core0 ||
2046 hw->phy.sfp_type == txgbe_sfp_type_da_cu_core1) {
2047 /* 7. Set VR_XS_PMA_Gen5_12G_RX_EQ_CTRL0 Register
2048 * Bit[15:8](VGA1/2_GAIN_0) = 8'h77
2049 * Bit[7:5](CTLE_POLE_0) = 3'h2
2050 * Bit[4:0](CTLE_BOOST_0) = 4'hF
2052 wr32_epcs(hw, TXGBE_PHY_RX_EQ_CTL0, 0x774F);
2055 /* 7. Set VR_XS_PMA_Gen5_12G_RX_EQ_CTRL0 Register
2056 * Bit[15:8](VGA1/2_GAIN_0) = 8'h00
2057 * Bit[7:5](CTLE_POLE_0) = 3'h2
2058 * Bit[4:0](CTLE_BOOST_0) = 4'hA
2060 value = rd32_epcs(hw, TXGBE_PHY_RX_EQ_CTL0);
2061 value = (value & ~0xFFFF) | (2 << 5) | 0x05;
2062 wr32_epcs(hw, TXGBE_PHY_RX_EQ_CTL0, value);
2064 value = rd32_epcs(hw, TXGBE_PHY_RX_EQ_ATT_LVL0);
2065 value = (value & ~0x7) | 0x0;
2066 wr32_epcs(hw, TXGBE_PHY_RX_EQ_ATT_LVL0, value);
2068 if (hw->phy.sfp_type == txgbe_sfp_type_da_cu_core0 ||
2069 hw->phy.sfp_type == txgbe_sfp_type_da_cu_core1) {
2070 /* 8. Set VR_XS_PMA_Gen5_12G_DFE_TAP_CTRL0 Register
2071 * Bit[7:0](DFE_TAP1_0) = 8'd20
2073 wr32_epcs(hw, TXGBE_PHY_DFE_TAP_CTL0, 0x0014);
2074 value = rd32_epcs(hw, TXGBE_PHY_AFE_DFE_ENABLE);
2075 value = (value & ~0x11) | 0x11;
2076 wr32_epcs(hw, TXGBE_PHY_AFE_DFE_ENABLE, value);
2078 /* 8. Set VR_XS_PMA_Gen5_12G_DFE_TAP_CTRL0 Register
2079 * Bit[7:0](DFE_TAP1_0) = 8'd20
2081 wr32_epcs(hw, TXGBE_PHY_DFE_TAP_CTL0, 0xBE);
2082 /* 9. Set VR_MII_Gen5_12G_AFE_DFE_EN_CTRL Register
2083 * Bit[4](DFE_EN_0) = 1'b0, Bit[0](AFE_EN_0) = 1'b0
2085 value = rd32_epcs(hw, TXGBE_PHY_AFE_DFE_ENABLE);
2086 value = (value & ~0x11) | 0x0;
2087 wr32_epcs(hw, TXGBE_PHY_AFE_DFE_ENABLE, value);
2089 value = rd32_epcs(hw, TXGBE_PHY_RX_EQ_CTL);
2090 value = value & ~0x1;
2091 wr32_epcs(hw, TXGBE_PHY_RX_EQ_CTL, value);
2093 /* Set SR PCS Control2 Register Bits[1:0] = 2'b00
2096 wr32_epcs(hw, SR_XS_PCS_CTRL2, 0x1);
2097 /* Set SR PMA MMD Control1 Register Bit[13] = 1'b0
2100 wr32_epcs(hw, SR_PMA_CTRL1, 0x0000);
2101 /* Set SR MII MMD Control Register to corresponding speed */
2102 wr32_epcs(hw, SR_MII_MMD_CTL, 0x0140);
2104 value = rd32_epcs(hw, TXGBE_PHY_TX_GENCTRL1);
2105 value = (value & ~0x710) | 0x500;
2106 wr32_epcs(hw, TXGBE_PHY_TX_GENCTRL1, value);
2107 /* 4. Set VR_XS_PMA_Gen5_12G_MISC_CTRL0 Register
2108 * Bit[12:8](RX_VREF_CTRL) = 5'hF
2110 wr32_epcs(hw, TXGBE_PHY_MISC_CTL0, 0xCF00);
2112 if (hw->phy.sfp_type == txgbe_sfp_type_da_cu_core0 ||
2113 hw->phy.sfp_type == txgbe_sfp_type_da_cu_core1) {
2114 wr32_epcs(hw, TXGBE_PHY_RX_EQ_CTL0, 0x774F);
2116 /* 7. Set VR_XS_PMA_Gen5_12G_RX_EQ_CTRL0 Register
2117 * Bit[15:8](VGA1/2_GAIN_0) = 8'h00
2118 * Bit[7:5](CTLE_POLE_0) = 3'h2
2119 * Bit[4:0](CTLE_BOOST_0) = 4'hA
2121 value = rd32_epcs(hw, TXGBE_PHY_RX_EQ_CTL0);
2122 value = (value & ~0xFFFF) | 0x7706;
2123 wr32_epcs(hw, TXGBE_PHY_RX_EQ_CTL0, value);
2125 value = rd32_epcs(hw, TXGBE_PHY_RX_EQ_ATT_LVL0);
2126 value = (value & ~0x7) | 0x0;
2127 wr32_epcs(hw, TXGBE_PHY_RX_EQ_ATT_LVL0, value);
2128 /* 8. Set VR_XS_PMA_Gen5_12G_DFE_TAP_CTRL0 Register
2129 * Bit[7:0](DFE_TAP1_0) = 8'd00
2131 wr32_epcs(hw, TXGBE_PHY_DFE_TAP_CTL0, 0x0);
2132 /* 9. Set VR_MII_Gen5_12G_AFE_DFE_EN_CTRL Register
2133 * Bit[4](DFE_EN_0) = 1'b0, Bit[0](AFE_EN_0) = 1'b0
2135 value = rd32_epcs(hw, TXGBE_PHY_RX_GEN_CTL3);
2136 value = (value & ~0x7) | 0x4;
2137 wr32_epcs(hw, TXGBE_PHY_RX_GEN_CTL3, value);
2138 wr32_epcs(hw, TXGBE_PHY_MPLLA_CTL0, 0x0020);
2139 wr32_epcs(hw, TXGBE_PHY_MPLLA_CTL3, 0x0046);
2140 wr32_epcs(hw, TXGBE_PHY_VCO_CAL_LD0, 0x0540);
2141 wr32_epcs(hw, TXGBE_PHY_VCO_CAL_REF0, 0x002A);
2142 wr32_epcs(hw, TXGBE_PHY_AFE_DFE_ENABLE, 0x0);
2143 wr32_epcs(hw, TXGBE_PHY_RX_EQ_CTL, 0x0010);
2144 wr32_epcs(hw, TXGBE_PHY_TX_RATE_CTL, 0x0003);
2145 wr32_epcs(hw, TXGBE_PHY_RX_RATE_CTL, 0x0003);
2146 wr32_epcs(hw, TXGBE_PHY_TX_GEN_CTL2, 0x0100);
2147 wr32_epcs(hw, TXGBE_PHY_RX_GEN_CTL2, 0x0100);
2148 wr32_epcs(hw, TXGBE_PHY_MPLLA_CTL2, 0x0200);
2149 wr32_epcs(hw, SR_MII_MMD_AN_CTL, 0x0100);
2151 /* 10. Initialize the mode by setting VR XS or PCS MMD Digital Control1
2152 * Register Bit[15](VR_RST)
2154 wr32_epcs(hw, VR_XS_OR_PCS_MMD_DIGI_CTL1, 0xA000);
2156 /* Wait phy initialization done */
2157 for (i = 0; i < 100; i++) {
2158 if ((rd32_epcs(hw, VR_XS_OR_PCS_MMD_DIGI_CTL1) &
2159 VR_XS_OR_PCS_MMD_DIGI_CTL1_VR_RST) == 0)
2164 err = TXGBE_ERR_PHY_INIT_NOT_DONE;
2168 if (hw->phy.ffe_set == TXGBE_BP_M_SFI) {
2169 value = rd32_epcs(hw, TXGBE_PHY_TX_EQ_CTL0) & ~0x3F3F;
2170 value |= hw->phy.ffe_main << 8 | hw->phy.ffe_pre;
2171 wr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL0, value);
2173 value = rd32_epcs(hw, TXGBE_PHY_TX_EQ_CTL0) & ~0x7F;
2174 value |= hw->phy.ffe_post | (1 << 6);
2175 wr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL1, value);
2176 } else if (hw->fw_version <= TXGBE_FW_N_TXEQ) {
2177 value = rd32_epcs(hw, TXGBE_PHY_TX_EQ_CTL0);
2178 value = (value & ~0x3F3F) | (24 << 8) | 4;
2179 wr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL0, value);
2181 value = rd32_epcs(hw, TXGBE_PHY_TX_EQ_CTL1);
2182 value = (value & ~0x7F) | 16 | (1 << 6);
2183 wr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL1, value);
2190 * txgbe_autoc_read - Hides MAC differences needed for AUTOC read
2191 * @hw: pointer to hardware structure
2193 u64 txgbe_autoc_read(struct txgbe_hw *hw)
2200 u8 type = hw->subsystem_device_id & 0xFF;
2202 autoc = hw->mac.autoc;
2204 if (hw->phy.multispeed_fiber) {
2205 autoc |= TXGBE_AUTOC_LMS_10G;
2206 } else if (type == TXGBE_DEV_ID_SFP) {
2207 autoc |= TXGBE_AUTOC_LMS_10G;
2208 autoc |= TXGBE_AUTOC_10GS_SFI;
2209 } else if (type == TXGBE_DEV_ID_QSFP) {
2211 } else if (type == TXGBE_DEV_ID_XAUI || type == TXGBE_DEV_ID_SFI_XAUI) {
2212 autoc |= TXGBE_AUTOC_LMS_10G_LINK_NO_AN;
2213 autoc |= TXGBE_AUTOC_10G_XAUI;
2214 hw->phy.link_mode = TXGBE_PHYSICAL_LAYER_10GBASE_T;
2215 } else if (type == TXGBE_DEV_ID_SGMII) {
2216 autoc |= TXGBE_AUTOC_LMS_SGMII_1G_100M;
2217 hw->phy.link_mode = TXGBE_PHYSICAL_LAYER_1000BASE_T |
2218 TXGBE_PHYSICAL_LAYER_100BASE_TX;
2219 } else if (type == TXGBE_DEV_ID_MAC_XAUI) {
2220 autoc |= TXGBE_AUTOC_LMS_10G_LINK_NO_AN;
2221 hw->phy.link_mode = TXGBE_PHYSICAL_LAYER_10GBASE_KX4;
2222 } else if (type == TXGBE_DEV_ID_MAC_SGMII) {
2223 autoc |= TXGBE_AUTOC_LMS_1G_LINK_NO_AN;
2224 hw->phy.link_mode = TXGBE_PHYSICAL_LAYER_1000BASE_KX;
2227 if (type != TXGBE_DEV_ID_KR_KX_KX4)
2230 sr_pcs_ctl = rd32_epcs(hw, SR_XS_PCS_CTRL2);
2231 sr_pma_ctl1 = rd32_epcs(hw, SR_PMA_CTRL1);
2232 sr_an_ctl = rd32_epcs(hw, SR_AN_CTRL);
2233 sr_an_adv_reg2 = rd32_epcs(hw, SR_AN_MMD_ADV_REG2);
2235 if ((sr_pcs_ctl & SR_PCS_CTRL2_TYPE_SEL) == SR_PCS_CTRL2_TYPE_SEL_X &&
2236 (sr_pma_ctl1 & SR_PMA_CTRL1_SS13) == SR_PMA_CTRL1_SS13_KX &&
2237 (sr_an_ctl & SR_AN_CTRL_AN_EN) == 0) {
2238 /* 1G or KX - no backplane auto-negotiation */
2239 autoc |= TXGBE_AUTOC_LMS_1G_LINK_NO_AN |
2241 hw->phy.link_mode = TXGBE_PHYSICAL_LAYER_1000BASE_KX;
2242 } else if ((sr_pcs_ctl & SR_PCS_CTRL2_TYPE_SEL) ==
2243 SR_PCS_CTRL2_TYPE_SEL_X &&
2244 (sr_pma_ctl1 & SR_PMA_CTRL1_SS13) == SR_PMA_CTRL1_SS13_KX4 &&
2245 (sr_an_ctl & SR_AN_CTRL_AN_EN) == 0) {
2246 autoc |= TXGBE_AUTOC_LMS_10G |
2247 TXGBE_AUTOC_10G_KX4;
2248 hw->phy.link_mode = TXGBE_PHYSICAL_LAYER_10GBASE_KX4;
2249 } else if ((sr_pcs_ctl & SR_PCS_CTRL2_TYPE_SEL) ==
2250 SR_PCS_CTRL2_TYPE_SEL_R &&
2251 (sr_an_ctl & SR_AN_CTRL_AN_EN) == 0) {
2252 /* 10 GbE serial link (KR -no backplane auto-negotiation) */
2253 autoc |= TXGBE_AUTOC_LMS_10G |
2254 TXGBE_AUTOC_10GS_KR;
2255 hw->phy.link_mode = TXGBE_PHYSICAL_LAYER_10GBASE_KR;
2256 } else if ((sr_an_ctl & SR_AN_CTRL_AN_EN)) {
2257 /* KX/KX4/KR backplane auto-negotiation enable */
2258 if (sr_an_adv_reg2 & SR_AN_MMD_ADV_REG2_BP_TYPE_KR)
2259 autoc |= TXGBE_AUTOC_KR_SUPP;
2260 if (sr_an_adv_reg2 & SR_AN_MMD_ADV_REG2_BP_TYPE_KX4)
2261 autoc |= TXGBE_AUTOC_KX4_SUPP;
2262 if (sr_an_adv_reg2 & SR_AN_MMD_ADV_REG2_BP_TYPE_KX)
2263 autoc |= TXGBE_AUTOC_KX_SUPP;
2264 autoc |= TXGBE_AUTOC_LMS_KX4_KX_KR;
2265 hw->phy.link_mode = TXGBE_PHYSICAL_LAYER_10GBASE_KR |
2266 TXGBE_PHYSICAL_LAYER_10GBASE_KX4 |
2267 TXGBE_PHYSICAL_LAYER_1000BASE_KX;
2274 * txgbe_autoc_write - Hides MAC differences needed for AUTOC write
2275 * @hw: pointer to hardware structure
2276 * @autoc: value to write to AUTOC
2278 void txgbe_autoc_write(struct txgbe_hw *hw, u64 autoc)
2283 u8 device_type = hw->subsystem_device_id & 0xFF;
2285 speed = TXGBD_AUTOC_SPEED(autoc);
2286 autoc &= ~TXGBE_AUTOC_SPEED_MASK;
2287 autoneg = (autoc & TXGBE_AUTOC_AUTONEG ? true : false);
2288 autoc &= ~TXGBE_AUTOC_AUTONEG;
2290 if (device_type == TXGBE_DEV_ID_KR_KX_KX4) {
2292 switch (hw->phy.link_mode) {
2293 case TXGBE_PHYSICAL_LAYER_10GBASE_KR:
2294 txgbe_set_link_to_kr(hw, autoneg);
2296 case TXGBE_PHYSICAL_LAYER_10GBASE_KX4:
2297 txgbe_set_link_to_kx4(hw, autoneg);
2299 case TXGBE_PHYSICAL_LAYER_1000BASE_KX:
2300 txgbe_set_link_to_kx(hw, speed, autoneg);
2306 txgbe_set_link_to_kr(hw, !autoneg);
2308 } else if (device_type == TXGBE_DEV_ID_XAUI ||
2309 device_type == TXGBE_DEV_ID_SGMII ||
2310 device_type == TXGBE_DEV_ID_MAC_XAUI ||
2311 device_type == TXGBE_DEV_ID_MAC_SGMII ||
2312 (device_type == TXGBE_DEV_ID_SFI_XAUI &&
2313 hw->phy.media_type == txgbe_media_type_copper)) {
2314 if (speed == TXGBE_LINK_SPEED_10GB_FULL) {
2315 txgbe_set_link_to_kx4(hw, 0);
2317 txgbe_set_link_to_kx(hw, speed, 0);
2318 if (hw->devarg.auto_neg == 1)
2319 txgbe_set_sgmii_an37_ability(hw);
2321 } else if (hw->phy.media_type == txgbe_media_type_fiber) {
2322 txgbe_set_link_to_sfi(hw, speed);
2325 if (speed == TXGBE_LINK_SPEED_10GB_FULL)
2326 mactxcfg = TXGBE_MACTXCFG_SPEED_10G;
2327 else if (speed == TXGBE_LINK_SPEED_1GB_FULL)
2328 mactxcfg = TXGBE_MACTXCFG_SPEED_1G;
2330 /* enable mac transmitter */
2331 wr32m(hw, TXGBE_MACTXCFG,
2332 TXGBE_MACTXCFG_SPEED_MASK | TXGBE_MACTXCFG_TXE,
2333 mactxcfg | TXGBE_MACTXCFG_TXE);
2336 void txgbe_bp_down_event(struct txgbe_hw *hw)
2338 if (!(hw->devarg.auto_neg == 1))
2341 BP_LOG("restart phy power.\n");
2342 wr32_epcs(hw, VR_AN_KR_MODE_CL, 0);
2343 wr32_epcs(hw, SR_AN_CTRL, 0);
2344 wr32_epcs(hw, VR_AN_INTR_MSK, 0);
2347 txgbe_set_link_to_kr(hw, 0);
2350 void txgbe_bp_mode_set(struct txgbe_hw *hw)
2352 if (hw->phy.ffe_set == TXGBE_BP_M_SFI)
2353 hw->subsystem_device_id = TXGBE_DEV_ID_WX1820_SFP;
2354 else if (hw->phy.ffe_set == TXGBE_BP_M_KR)
2355 hw->subsystem_device_id = TXGBE_DEV_ID_WX1820_KR_KX_KX4;
2356 else if (hw->phy.ffe_set == TXGBE_BP_M_KX4)
2357 hw->subsystem_device_id = TXGBE_DEV_ID_WX1820_MAC_XAUI;
2358 else if (hw->phy.ffe_set == TXGBE_BP_M_KX)
2359 hw->subsystem_device_id = TXGBE_DEV_ID_WX1820_MAC_SGMII;
2362 void txgbe_set_phy_temp(struct txgbe_hw *hw)
2366 if (hw->phy.ffe_set == TXGBE_BP_M_SFI) {
2367 BP_LOG("Set SFI TX_EQ MAIN:%d PRE:%d POST:%d\n",
2368 hw->phy.ffe_main, hw->phy.ffe_pre, hw->phy.ffe_post);
2370 value = rd32_epcs(hw, TXGBE_PHY_TX_EQ_CTL0);
2371 value = (value & ~0x3F3F) | (hw->phy.ffe_main << 8) |
2373 wr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL0, value);
2375 value = rd32_epcs(hw, TXGBE_PHY_TX_EQ_CTL1);
2376 value = (value & ~0x7F) | hw->phy.ffe_post | (1 << 6);
2377 wr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL1, value);
2380 if (hw->phy.ffe_set == TXGBE_BP_M_KR) {
2381 BP_LOG("Set KR TX_EQ MAIN:%d PRE:%d POST:%d\n",
2382 hw->phy.ffe_main, hw->phy.ffe_pre, hw->phy.ffe_post);
2383 value = (0x1804 & ~0x3F3F);
2384 value |= hw->phy.ffe_main << 8 | hw->phy.ffe_pre;
2385 wr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL0, value);
2387 value = (0x50 & ~0x7F) | (1 << 6) | hw->phy.ffe_post;
2388 wr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL1, value);
2389 wr32_epcs(hw, 0x18035, 0x00FF);
2390 wr32_epcs(hw, 0x18055, 0x00FF);
2393 if (hw->phy.ffe_set == TXGBE_BP_M_KX) {
2394 BP_LOG("Set KX TX_EQ MAIN:%d PRE:%d POST:%d\n",
2395 hw->phy.ffe_main, hw->phy.ffe_pre, hw->phy.ffe_post);
2396 value = rd32_epcs(hw, TXGBE_PHY_TX_EQ_CTL0);
2397 value = (value & ~0x3F3F) | (hw->phy.ffe_main << 8) |
2399 wr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL0, value);
2401 value = rd32_epcs(hw, TXGBE_PHY_TX_EQ_CTL1);
2402 value = (value & ~0x7F) | hw->phy.ffe_post | (1 << 6);
2403 wr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL1, value);
2405 wr32_epcs(hw, 0x18035, 0x00FF);
2406 wr32_epcs(hw, 0x18055, 0x00FF);
2411 * txgbe_kr_handle - Handle the interrupt of auto-negotiation
2412 * @hw: pointer to hardware structure
2414 s32 txgbe_kr_handle(struct txgbe_hw *hw)
2419 DEBUGFUNC("txgbe_kr_handle");
2421 value = rd32_epcs(hw, VR_AN_INTR);
2422 BP_LOG("AN INTERRUPT!! value: 0x%x\n", value);
2423 if (!(value & VR_AN_INTR_PG_RCV)) {
2424 wr32_epcs(hw, VR_AN_INTR, 0);
2428 status = txgbe_handle_bp_flow(0, hw);
2434 * txgbe_handle_bp_flow - Handle backplane AN73 flow
2435 * @hw: pointer to hardware structure
2436 * @link_mode: local AN73 link mode
2438 static s32 txgbe_handle_bp_flow(u32 link_mode, struct txgbe_hw *hw)
2440 u32 value, i, lp_reg, ld_reg;
2442 struct txgbe_backplane_ability local_ability, lp_ability;
2444 DEBUGFUNC("txgbe_handle_bp_flow");
2446 local_ability.current_link_mode = link_mode;
2448 /* 1. Get the local AN73 Base Page Ability */
2449 BP_LOG("<1>. Get the local AN73 Base Page Ability ...\n");
2450 txgbe_get_bp_ability(&local_ability, 0, hw);
2452 /* 2. Check and clear the AN73 Interrupt Status */
2453 BP_LOG("<2>. Check the AN73 Interrupt Status ...\n");
2454 txgbe_clear_bp_intr(2, 0, hw);
2456 /* 3.1. Get the link partner AN73 Base Page Ability */
2457 BP_LOG("<3.1>. Get the link partner AN73 Base Page Ability ...\n");
2458 txgbe_get_bp_ability(&lp_ability, 1, hw);
2460 /* 3.2. Check the AN73 Link Ability with Link Partner */
2461 BP_LOG("<3.2>. Check the AN73 Link Ability with Link Partner ...\n");
2462 BP_LOG(" Local Link Ability: 0x%x\n", local_ability.link_ability);
2463 BP_LOG(" Link Partner Link Ability: 0x%x\n", lp_ability.link_ability);
2465 status = txgbe_check_bp_ability(&local_ability, &lp_ability, hw);
2467 wr32_epcs(hw, SR_AN_CTRL, 0);
2468 wr32_epcs(hw, VR_AN_KR_MODE_CL, 0);
2470 /* 3.3. Check the FEC and KR Training for KR mode */
2471 BP_LOG("<3.3>. Check the FEC for KR mode ...\n");
2472 if ((local_ability.fec_ability & lp_ability.fec_ability) == 0x03) {
2473 BP_LOG("Enable the Backplane KR FEC ...\n");
2474 wr32_epcs(hw, SR_PMA_KR_FEC_CTRL, SR_PMA_KR_FEC_CTRL_EN);
2476 BP_LOG("Backplane KR FEC is disabled.\n");
2479 printf("Enter training.\n");
2480 /* CL72 KR training on */
2481 for (i = 0; i < 2; i++) {
2482 /* 3.4. Check the CL72 KR Training for KR mode */
2483 BP_LOG("<3.4>. Check the CL72 KR Training for KR mode ...\n");
2484 BP_LOG("==================%d==================\n", i);
2485 status = txgbe_enable_kr_training(hw);
2486 BP_LOG("Check the Clause 72 KR Training status ...\n");
2487 status |= txgbe_check_kr_training(hw);
2489 lp_reg = rd32_epcs(hw, SR_PMA_KR_LP_CESTS);
2490 lp_reg &= SR_PMA_KR_LP_CESTS_RR;
2491 BP_LOG("SR PMA MMD 10GBASE-KR LP Coefficient Status Register: 0x%x\n",
2493 ld_reg = rd32_epcs(hw, SR_PMA_KR_LD_CESTS);
2494 ld_reg &= SR_PMA_KR_LD_CESTS_RR;
2495 BP_LOG("SR PMA MMD 10GBASE-KR LD Coefficient Status Register: 0x%x\n",
2497 if (hw->devarg.poll == 0 && status != 0)
2498 lp_reg = SR_PMA_KR_LP_CESTS_RR;
2500 if (lp_reg & ld_reg) {
2501 BP_LOG("==================out==================\n");
2502 status = txgbe_disable_kr_training(hw, 0, 0);
2503 wr32_epcs(hw, SR_AN_CTRL, 0);
2504 txgbe_clear_bp_intr(2, 0, hw);
2505 txgbe_clear_bp_intr(1, 0, hw);
2506 txgbe_clear_bp_intr(0, 0, hw);
2507 for (i = 0; i < 10; i++) {
2508 value = rd32_epcs(hw, SR_XS_PCS_KR_STS1);
2509 if (value & SR_XS_PCS_KR_STS1_PLU) {
2510 BP_LOG("\nINT_AN_INT_CMPLT =1, AN73 Done Success.\n");
2511 wr32_epcs(hw, SR_AN_CTRL, 0);
2517 txgbe_set_link_to_kr(hw, 0);
2522 status |= txgbe_disable_kr_training(hw, 0, 0);
2525 txgbe_clear_bp_intr(2, 0, hw);
2526 txgbe_clear_bp_intr(1, 0, hw);
2527 txgbe_clear_bp_intr(0, 0, hw);
2533 * txgbe_get_bp_ability
2534 * @hw: pointer to hardware structure
2535 * @ability: pointer to blackplane ability structure
2537 * 1: Get Link Partner Base Page
2538 * 2: Get Link Partner Next Page
2539 * (only get NXP Ability Register 1 at the moment)
2540 * 0: Get Local Device Base Page
2542 static void txgbe_get_bp_ability(struct txgbe_backplane_ability *ability,
2543 u32 link_partner, struct txgbe_hw *hw)
2547 DEBUGFUNC("txgbe_get_bp_ability");
2549 /* Link Partner Base Page */
2550 if (link_partner == 1) {
2551 /* Read the link partner AN73 Base Page Ability Registers */
2552 BP_LOG("Read the link partner AN73 Base Page Ability Registers...\n");
2553 value = rd32_epcs(hw, SR_AN_MMD_LP_ABL1);
2554 BP_LOG("SR AN MMD LP Base Page Ability Register 1: 0x%x\n",
2556 ability->next_page = SR_MMD_LP_ABL1_ADV_NP(value);
2557 BP_LOG(" Next Page (bit15): %d\n", ability->next_page);
2559 value = rd32_epcs(hw, SR_AN_MMD_LP_ABL2);
2560 BP_LOG("SR AN MMD LP Base Page Ability Register 2: 0x%x\n",
2562 ability->link_ability =
2563 value & SR_AN_MMD_LP_ABL2_BP_TYPE_KR_KX4_KX;
2564 BP_LOG(" Link Ability (bit[15:0]): 0x%x\n",
2565 ability->link_ability);
2566 BP_LOG(" (0x20- KX_ONLY, 0x40- KX4_ONLY, 0x60- KX4_KX\n");
2567 BP_LOG(" 0x80- KR_ONLY, 0xA0- KR_KX, 0xC0- KR_KX4, 0xE0- KR_KX4_KX)\n");
2569 value = rd32_epcs(hw, SR_AN_MMD_LP_ABL3);
2570 BP_LOG("SR AN MMD LP Base Page Ability Register 3: 0x%x\n",
2572 BP_LOG(" FEC Request (bit15): %d\n", ((value >> 15) & 0x01));
2573 BP_LOG(" FEC Enable (bit14): %d\n", ((value >> 14) & 0x01));
2574 ability->fec_ability = SR_AN_MMD_LP_ABL3_FCE(value);
2575 } else if (link_partner == 2) {
2576 /* Read the link partner AN73 Next Page Ability Registers */
2577 BP_LOG("\nRead the link partner AN73 Next Page Ability Registers...\n");
2578 value = rd32_epcs(hw, SR_AN_LP_XNP_ABL1);
2579 BP_LOG(" SR AN MMD LP XNP Ability Register 1: 0x%x\n", value);
2580 ability->next_page = SR_AN_LP_XNP_ABL1_NP(value);
2581 BP_LOG(" Next Page (bit15): %d\n", ability->next_page);
2583 /* Read the local AN73 Base Page Ability Registers */
2584 BP_LOG("Read the local AN73 Base Page Ability Registers...\n");
2585 value = rd32_epcs(hw, SR_AN_MMD_ADV_REG1);
2586 BP_LOG("SR AN MMD Advertisement Register 1: 0x%x\n", value);
2587 ability->next_page = SR_AN_MMD_ADV_REG1_NP(value);
2588 BP_LOG(" Next Page (bit15): %d\n", ability->next_page);
2590 value = rd32_epcs(hw, SR_AN_MMD_ADV_REG2);
2591 BP_LOG("SR AN MMD Advertisement Register 2: 0x%x\n", value);
2592 ability->link_ability =
2593 value & SR_AN_MMD_ADV_REG2_BP_TYPE_KR_KX4_KX;
2594 BP_LOG(" Link Ability (bit[15:0]): 0x%x\n",
2595 ability->link_ability);
2596 BP_LOG(" (0x20- KX_ONLY, 0x40- KX4_ONLY, 0x60- KX4_KX\n");
2597 BP_LOG(" 0x80- KR_ONLY, 0xA0- KR_KX, 0xC0- KR_KX4, 0xE0- KR_KX4_KX)\n");
2599 value = rd32_epcs(hw, SR_AN_MMD_ADV_REG3);
2600 BP_LOG("SR AN MMD Advertisement Register 3: 0x%x\n", value);
2601 BP_LOG(" FEC Request (bit15): %d\n", ((value >> 15) & 0x01));
2602 BP_LOG(" FEC Enable (bit14): %d\n", ((value >> 14) & 0x01));
2603 ability->fec_ability = SR_AN_MMD_ADV_REG3_FCE(value);
2610 * txgbe_check_bp_ability
2611 * @hw: pointer to hardware structure
2612 * @ability: pointer to blackplane ability structure
2614 static s32 txgbe_check_bp_ability(struct txgbe_backplane_ability *local_ability,
2615 struct txgbe_backplane_ability *lp_ability, struct txgbe_hw *hw)
2620 DEBUGFUNC("txgbe_check_bp_ability");
2622 com_link_abi = local_ability->link_ability & lp_ability->link_ability;
2623 BP_LOG("com_link_abi = 0x%x, local_ability = 0x%x, lp_ability = 0x%x\n",
2624 com_link_abi, local_ability->link_ability,
2625 lp_ability->link_ability);
2627 if (!com_link_abi) {
2628 BP_LOG("The Link Partner does not support any compatible speed mode.\n");
2630 } else if (com_link_abi & BP_TYPE_KR) {
2631 if (local_ability->current_link_mode) {
2632 BP_LOG("Link mode is not matched with Link Partner: [LINK_KR].\n");
2633 BP_LOG("Set the local link mode to [LINK_KR] ...\n");
2634 txgbe_set_link_to_kr(hw, 0);
2637 BP_LOG("Link mode is matched with Link Partner: [LINK_KR].\n");
2640 } else if (com_link_abi & BP_TYPE_KX4) {
2641 if (local_ability->current_link_mode == 0x10) {
2642 BP_LOG("Link mode is matched with Link Partner: [LINK_KX4].\n");
2645 BP_LOG("Link mode is not matched with Link Partner: [LINK_KX4].\n");
2646 BP_LOG("Set the local link mode to [LINK_KX4] ...\n");
2647 txgbe_set_link_to_kx4(hw, 1);
2650 } else if (com_link_abi & BP_TYPE_KX) {
2651 if (local_ability->current_link_mode == 0x1) {
2652 BP_LOG("Link mode is matched with Link Partner: [LINK_KX].\n");
2655 BP_LOG("Link mode is not matched with Link Partner: [LINK_KX].\n");
2656 BP_LOG("Set the local link mode to [LINK_KX] ...\n");
2657 txgbe_set_link_to_kx(hw, 1, 1);
2666 * txgbe_clear_bp_intr
2667 * @hw: pointer to hardware structure
2668 * @index: the bit will be cleared
2670 * index_high = 0: Only the index bit will be cleared
2671 * index_high != 0: the [index_high, index] range will be cleared
2673 static void txgbe_clear_bp_intr(u32 bit, u32 bit_high, struct txgbe_hw *hw)
2675 u32 rdata = 0, wdata, i;
2677 DEBUGFUNC("txgbe_clear_bp_intr");
2679 rdata = rd32_epcs(hw, VR_AN_INTR);
2680 BP_LOG("[Before clear]Read VR AN MMD Interrupt Register: 0x%x\n",
2682 BP_LOG("Interrupt: 0- AN_INT_CMPLT, 1- AN_INC_LINK, 2- AN_PG_RCV\n\n");
2686 for (i = bit; i <= bit_high; i++)
2689 wdata &= ~(1 << bit);
2692 wr32_epcs(hw, VR_AN_INTR, wdata);
2694 rdata = rd32_epcs(hw, VR_AN_INTR);
2695 BP_LOG("[After clear]Read VR AN MMD Interrupt Register: 0x%x\n", rdata);
2698 static s32 txgbe_enable_kr_training(struct txgbe_hw *hw)
2703 DEBUGFUNC("txgbe_enable_kr_training");
2705 BP_LOG("Enable Clause 72 KR Training ...\n");
2707 if (CL72_KRTR_PRBS_MODE_EN != 0xFFFF) {
2708 /* Set PRBS Timer Duration Control to maximum 6.7ms in
2709 * VR_PMA_KRTR_PRBS_CTRL2 Register
2711 value = CL72_KRTR_PRBS_MODE_EN;
2712 wr32_epcs(hw, VR_PMA_KRTR_PRBS_CTRL2, value);
2713 /* Set PRBS Timer Duration Control to maximum 6.7ms in
2714 * VR_PMA_KRTR_PRBS_CTRL1 Register
2716 wr32_epcs(hw, VR_PMA_KRTR_PRBS_CTRL1,
2717 VR_PMA_KRTR_PRBS_TIME_LMT);
2718 /* Enable PRBS Mode to determine KR Training Status by setting
2719 * Bit 0 of VR_PMA_KRTR_PRBS_CTRL0 Register
2721 value = VR_PMA_KRTR_PRBS_MODE_EN;
2723 #ifdef CL72_KRTR_PRBS31_EN
2724 /* Enable PRBS Mode to determine KR Training Status by setting
2725 * Bit 1 of VR_PMA_KRTR_PRBS_CTRL0 Register
2727 value = VR_PMA_KRTR_PRBS31_EN;
2729 wr32_epcs(hw, VR_PMA_KRTR_PRBS_CTRL0, value);
2730 /* Read PHY Lane0 TX EQ before Clause 72 KR Training. */
2731 txgbe_read_phy_lane_tx_eq(0, hw, 0, 0);
2733 /* Enable the Clause 72 start-up protocol
2734 * by setting Bit 1 of SR_PMA_KR_PMD_CTRL Register.
2735 * Restart the Clause 72 start-up protocol
2736 * by setting Bit 0 of SR_PMA_KR_PMD_CTRL Register.
2738 wr32_epcs(hw, SR_PMA_KR_PMD_CTRL,
2739 SR_PMA_KR_PMD_CTRL_EN_TR | SR_PMA_KR_PMD_CTRL_RS_TR);
2744 static s32 txgbe_disable_kr_training(struct txgbe_hw *hw, s32 post, s32 mode)
2748 DEBUGFUNC("txgbe_disable_kr_training");
2750 BP_LOG("Disable Clause 72 KR Training ...\n");
2751 /* Read PHY Lane0 TX EQ before Clause 72 KR Training. */
2752 txgbe_read_phy_lane_tx_eq(0, hw, post, mode);
2754 wr32_epcs(hw, SR_PMA_KR_PMD_CTRL, SR_PMA_KR_PMD_CTRL_RS_TR);
2759 static s32 txgbe_check_kr_training(struct txgbe_hw *hw)
2764 int times = hw->devarg.poll ? 35 : 20;
2766 DEBUGFUNC("txgbe_check_kr_training");
2768 for (i = 0; i < times; i++) {
2769 value = rd32_epcs(hw, SR_PMA_KR_LP_CEU);
2770 BP_LOG("SR PMA MMD 10GBASE-KR LP Coefficient Update Register: 0x%x\n",
2772 value = rd32_epcs(hw, SR_PMA_KR_LP_CESTS);
2773 BP_LOG("SR PMA MMD 10GBASE-KR LP Coefficient Status Register: 0x%x\n",
2775 value = rd32_epcs(hw, SR_PMA_KR_LD_CEU);
2776 BP_LOG("SR PMA MMD 10GBASE-KR LD Coefficient Update: 0x%x\n",
2778 value = rd32_epcs(hw, SR_PMA_KR_LD_CESTS);
2779 BP_LOG("SR PMA MMD 10GBASE-KR LD Coefficient Status: 0x%x\n",
2781 value = rd32_epcs(hw, SR_PMA_KR_PMD_STS);
2782 BP_LOG("SR PMA MMD 10GBASE-KR Status Register: 0x%x\n", value);
2783 BP_LOG(" Training Failure (bit3): %d\n",
2784 ((value >> 3) & 0x01));
2785 BP_LOG(" Start-Up Protocol Status (bit2): %d\n",
2786 ((value >> 2) & 0x01));
2787 BP_LOG(" Frame Lock (bit1): %d\n",
2788 ((value >> 1) & 0x01));
2789 BP_LOG(" Receiver Status (bit0): %d\n",
2790 ((value >> 0) & 0x01));
2792 test = rd32_epcs(hw, SR_PMA_KR_LP_CESTS);
2793 if (test & SR_PMA_KR_LP_CESTS_RR) {
2794 BP_LOG("TEST Coefficient Status Register: 0x%x\n",
2799 if (value & SR_PMA_KR_PMD_STS_TR_FAIL) {
2800 BP_LOG("Training is completed with failure.\n");
2801 txgbe_read_phy_lane_tx_eq(0, hw, 0, 0);
2805 if (value & SR_PMA_KR_PMD_STS_RCV) {
2806 BP_LOG("Receiver trained and ready to receive data.\n");
2807 txgbe_read_phy_lane_tx_eq(0, hw, 0, 0);
2814 BP_LOG("ERROR: Check Clause 72 KR Training Complete Timeout.\n");
2818 static void txgbe_read_phy_lane_tx_eq(u16 lane, struct txgbe_hw *hw,
2823 u32 tx_main_cursor, tx_pre_cursor, tx_post_cursor, lmain;
2825 DEBUGFUNC("txgbe_read_phy_lane_tx_eq");
2827 addr = TXGBE_PHY_LANE0_TX_EQ_CTL1 | (lane << 8);
2828 value = rd32_ephy(hw, addr);
2829 BP_LOG("PHY LANE TX EQ Read Value: %x\n", lane);
2830 tx_main_cursor = TXGBE_PHY_LANE0_TX_EQ_CTL1_MAIN(value);
2831 BP_LOG("TX_MAIN_CURSOR: %x\n", tx_main_cursor);
2832 UNREFERENCED_PARAMETER(tx_main_cursor);
2834 addr = TXGBE_PHY_LANE0_TX_EQ_CTL2 | (lane << 8);
2835 value = rd32_ephy(hw, addr);
2836 tx_pre_cursor = value & TXGBE_PHY_LANE0_TX_EQ_CTL2_PRE;
2837 tx_post_cursor = TXGBE_PHY_LANE0_TX_EQ_CTL2_POST(value);
2838 BP_LOG("TX_PRE_CURSOR: %x\n", tx_pre_cursor);
2839 BP_LOG("TX_POST_CURSOR: %x\n", tx_post_cursor);
2842 lmain = 160 - tx_pre_cursor - tx_post_cursor;
2847 tx_post_cursor = post;
2849 wr32_epcs(hw, TXGBE_PHY_EQ_INIT_CTL1, tx_post_cursor);
2850 wr32_epcs(hw, TXGBE_PHY_EQ_INIT_CTL0,
2851 tx_pre_cursor | (lmain << 8));
2852 value = rd32_epcs(hw, TXGBE_PHY_TX_EQ_CTL1);
2853 value &= ~TXGBE_PHY_TX_EQ_CTL1_DEF;
2854 wr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL1, value);