1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2015-2020
6 #include "txgbe_eeprom.h"
10 static void txgbe_i2c_start(struct txgbe_hw *hw);
11 static void txgbe_i2c_stop(struct txgbe_hw *hw);
14 * txgbe_identify_extphy - Identify a single address for a PHY
15 * @hw: pointer to hardware structure
16 * @phy_addr: PHY address to probe
18 * Returns true if PHY found
20 static bool txgbe_identify_extphy(struct txgbe_hw *hw)
24 if (!txgbe_validate_phy_addr(hw, phy_addr)) {
25 DEBUGOUT("Unable to validate PHY address 0x%04X\n",
30 if (txgbe_get_phy_id(hw))
33 hw->phy.type = txgbe_get_phy_type_from_id(hw->phy.id);
34 if (hw->phy.type == txgbe_phy_unknown) {
36 hw->phy.read_reg(hw, TXGBE_MD_PHY_EXT_ABILITY,
40 if (ext_ability & (TXGBE_MD_PHY_10GBASET_ABILITY |
41 TXGBE_MD_PHY_1000BASET_ABILITY))
42 hw->phy.type = txgbe_phy_cu_unknown;
44 hw->phy.type = txgbe_phy_generic;
51 * txgbe_read_phy_if - Read TXGBE_ETHPHYIF register
52 * @hw: pointer to hardware structure
54 * Read TXGBE_ETHPHYIF register and save field values,
55 * and check for valid field values.
57 static s32 txgbe_read_phy_if(struct txgbe_hw *hw)
59 hw->phy.media_type = hw->phy.get_media_type(hw);
61 /* Save NW management interface connected on board. This is used
62 * to determine internal PHY mode.
64 hw->phy.nw_mng_if_sel = rd32(hw, TXGBE_ETHPHYIF);
66 /* If MDIO is connected to external PHY, then set PHY address. */
67 if (hw->phy.nw_mng_if_sel & TXGBE_ETHPHYIF_MDIO_ACT)
68 hw->phy.addr = TXGBE_ETHPHYIF_MDIO_BASE(hw->phy.nw_mng_if_sel);
70 if (!hw->phy.phy_semaphore_mask) {
72 hw->phy.phy_semaphore_mask = TXGBE_MNGSEM_SWPHY;
74 hw->phy.phy_semaphore_mask = TXGBE_MNGSEM_SWPHY;
81 * txgbe_identify_phy - Get physical layer module
82 * @hw: pointer to hardware structure
84 * Determines the physical layer module found on the current adapter.
86 s32 txgbe_identify_phy(struct txgbe_hw *hw)
88 s32 err = TXGBE_ERR_PHY_ADDR_INVALID;
90 DEBUGFUNC("txgbe_identify_phy");
92 txgbe_read_phy_if(hw);
94 if (hw->phy.type != txgbe_phy_unknown)
97 /* Raptor 10GBASE-T requires an external PHY */
98 if (hw->phy.media_type == txgbe_media_type_copper) {
99 err = txgbe_identify_extphy(hw);
100 } else if (hw->phy.media_type == txgbe_media_type_fiber) {
101 err = txgbe_identify_module(hw);
103 hw->phy.type = txgbe_phy_none;
107 /* Return error if SFP module has been detected but is not supported */
108 if (hw->phy.type == txgbe_phy_sfp_unsupported)
109 return TXGBE_ERR_SFP_NOT_SUPPORTED;
115 * txgbe_check_reset_blocked - check status of MNG FW veto bit
116 * @hw: pointer to the hardware structure
118 * This function checks the STAT.MNGVETO bit to see if there are
119 * any constraints on link from manageability. For MAC's that don't
120 * have this bit just return faluse since the link can not be blocked
123 s32 txgbe_check_reset_blocked(struct txgbe_hw *hw)
127 DEBUGFUNC("txgbe_check_reset_blocked");
129 mmngc = rd32(hw, TXGBE_STAT);
130 if (mmngc & TXGBE_STAT_MNGVETO) {
131 DEBUGOUT("MNG_VETO bit detected.\n");
139 * txgbe_validate_phy_addr - Determines phy address is valid
140 * @hw: pointer to hardware structure
141 * @phy_addr: PHY address
144 bool txgbe_validate_phy_addr(struct txgbe_hw *hw, u32 phy_addr)
149 DEBUGFUNC("txgbe_validate_phy_addr");
151 hw->phy.addr = phy_addr;
152 hw->phy.read_reg(hw, TXGBE_MD_PHY_ID_HIGH,
153 TXGBE_MD_DEV_PMA_PMD, &phy_id);
155 if (phy_id != 0xFFFF && phy_id != 0x0)
158 DEBUGOUT("PHY ID HIGH is 0x%04X\n", phy_id);
164 * txgbe_get_phy_id - Get the phy type
165 * @hw: pointer to hardware structure
168 s32 txgbe_get_phy_id(struct txgbe_hw *hw)
174 DEBUGFUNC("txgbe_get_phy_id");
176 err = hw->phy.read_reg(hw, TXGBE_MD_PHY_ID_HIGH,
177 TXGBE_MD_DEV_PMA_PMD,
181 hw->phy.id = (u32)(phy_id_high << 16);
182 err = hw->phy.read_reg(hw, TXGBE_MD_PHY_ID_LOW,
183 TXGBE_MD_DEV_PMA_PMD,
185 hw->phy.id |= (u32)(phy_id_low & TXGBE_PHY_REVISION_MASK);
186 hw->phy.revision = (u32)(phy_id_low & ~TXGBE_PHY_REVISION_MASK);
188 DEBUGOUT("PHY_ID_HIGH 0x%04X, PHY_ID_LOW 0x%04X\n",
189 phy_id_high, phy_id_low);
195 * txgbe_get_phy_type_from_id - Get the phy type
196 * @phy_id: PHY ID information
199 enum txgbe_phy_type txgbe_get_phy_type_from_id(u32 phy_id)
201 enum txgbe_phy_type phy_type;
203 DEBUGFUNC("txgbe_get_phy_type_from_id");
206 case TXGBE_PHYID_TN1010:
207 phy_type = txgbe_phy_tn;
209 case TXGBE_PHYID_QT2022:
210 phy_type = txgbe_phy_qt;
212 case TXGBE_PHYID_ATH:
213 phy_type = txgbe_phy_nl;
215 case TXGBE_PHYID_MTD3310:
216 phy_type = txgbe_phy_cu_mtd;
219 phy_type = txgbe_phy_unknown;
227 txgbe_reset_extphy(struct txgbe_hw *hw)
232 err = hw->phy.read_reg(hw, TXGBE_MD_PORT_CTRL,
233 TXGBE_MD_DEV_GENERAL, &ctrl);
236 ctrl |= TXGBE_MD_PORT_CTRL_RESET;
237 err = hw->phy.write_reg(hw, TXGBE_MD_PORT_CTRL,
238 TXGBE_MD_DEV_GENERAL, ctrl);
243 * Poll for reset bit to self-clear indicating reset is complete.
244 * Some PHYs could take up to 3 seconds to complete and need about
245 * 1.7 usec delay after the reset is complete.
247 for (i = 0; i < 30; i++) {
249 err = hw->phy.read_reg(hw, TXGBE_MD_PORT_CTRL,
250 TXGBE_MD_DEV_GENERAL, &ctrl);
254 if (!(ctrl & TXGBE_MD_PORT_CTRL_RESET)) {
260 if (ctrl & TXGBE_MD_PORT_CTRL_RESET) {
261 err = TXGBE_ERR_RESET_FAILED;
262 DEBUGOUT("PHY reset polling failed to complete.\n");
269 * txgbe_reset_phy - Performs a PHY reset
270 * @hw: pointer to hardware structure
272 s32 txgbe_reset_phy(struct txgbe_hw *hw)
276 DEBUGFUNC("txgbe_reset_phy");
278 if (hw->phy.type == txgbe_phy_unknown)
279 err = txgbe_identify_phy(hw);
281 if (err != 0 || hw->phy.type == txgbe_phy_none)
284 /* Don't reset PHY if it's shut down due to overtemp. */
285 if (hw->phy.check_overtemp(hw) == TXGBE_ERR_OVERTEMP)
288 /* Blocked by MNG FW so bail */
289 if (txgbe_check_reset_blocked(hw))
292 switch (hw->phy.type) {
293 case txgbe_phy_cu_mtd:
294 err = txgbe_reset_extphy(hw);
304 * txgbe_read_phy_mdi - Reads a value from a specified PHY register without
306 * @hw: pointer to hardware structure
307 * @reg_addr: 32 bit address of PHY register to read
308 * @device_type: 5 bit device type
309 * @phy_data: Pointer to read data from PHY register
311 s32 txgbe_read_phy_reg_mdi(struct txgbe_hw *hw, u32 reg_addr, u32 device_type,
316 /* Setup and write the address cycle command */
317 command = TXGBE_MDIOSCA_REG(reg_addr) |
318 TXGBE_MDIOSCA_DEV(device_type) |
319 TXGBE_MDIOSCA_PORT(hw->phy.addr);
320 wr32(hw, TXGBE_MDIOSCA, command);
322 command = TXGBE_MDIOSCD_CMD_READ |
324 wr32(hw, TXGBE_MDIOSCD, command);
327 * Check every 10 usec to see if the address cycle completed.
328 * The MDI Command bit will clear when the operation is
331 if (!po32m(hw, TXGBE_MDIOSCD, TXGBE_MDIOSCD_BUSY,
332 0, NULL, 100, 100)) {
333 DEBUGOUT("PHY address command did not complete\n");
334 return TXGBE_ERR_PHY;
337 data = rd32(hw, TXGBE_MDIOSCD);
338 *phy_data = (u16)TXGBD_MDIOSCD_DAT(data);
344 * txgbe_read_phy_reg - Reads a value from a specified PHY register
345 * using the SWFW lock - this function is needed in most cases
346 * @hw: pointer to hardware structure
347 * @reg_addr: 32 bit address of PHY register to read
348 * @device_type: 5 bit device type
349 * @phy_data: Pointer to read data from PHY register
351 s32 txgbe_read_phy_reg(struct txgbe_hw *hw, u32 reg_addr,
352 u32 device_type, u16 *phy_data)
355 u32 gssr = hw->phy.phy_semaphore_mask;
357 DEBUGFUNC("txgbe_read_phy_reg");
359 if (hw->mac.acquire_swfw_sync(hw, gssr))
360 return TXGBE_ERR_SWFW_SYNC;
362 err = hw->phy.read_reg_mdi(hw, reg_addr, device_type, phy_data);
364 hw->mac.release_swfw_sync(hw, gssr);
370 * txgbe_write_phy_reg_mdi - Writes a value to specified PHY register
372 * @hw: pointer to hardware structure
373 * @reg_addr: 32 bit PHY register to write
374 * @device_type: 5 bit device type
375 * @phy_data: Data to write to the PHY register
377 s32 txgbe_write_phy_reg_mdi(struct txgbe_hw *hw, u32 reg_addr,
378 u32 device_type, u16 phy_data)
383 command = TXGBE_MDIOSCA_REG(reg_addr) |
384 TXGBE_MDIOSCA_DEV(device_type) |
385 TXGBE_MDIOSCA_PORT(hw->phy.addr);
386 wr32(hw, TXGBE_MDIOSCA, command);
388 command = TXGBE_MDIOSCD_CMD_WRITE |
389 TXGBE_MDIOSCD_DAT(phy_data) |
391 wr32(hw, TXGBE_MDIOSCD, command);
393 /* wait for completion */
394 if (!po32m(hw, TXGBE_MDIOSCD, TXGBE_MDIOSCD_BUSY,
395 0, NULL, 100, 100)) {
396 TLOG_DEBUG("PHY write cmd didn't complete\n");
404 * txgbe_write_phy_reg - Writes a value to specified PHY register
405 * using SWFW lock- this function is needed in most cases
406 * @hw: pointer to hardware structure
407 * @reg_addr: 32 bit PHY register to write
408 * @device_type: 5 bit device type
409 * @phy_data: Data to write to the PHY register
411 s32 txgbe_write_phy_reg(struct txgbe_hw *hw, u32 reg_addr,
412 u32 device_type, u16 phy_data)
415 u32 gssr = hw->phy.phy_semaphore_mask;
417 DEBUGFUNC("txgbe_write_phy_reg");
419 if (hw->mac.acquire_swfw_sync(hw, gssr))
420 err = TXGBE_ERR_SWFW_SYNC;
422 err = hw->phy.write_reg_mdi(hw, reg_addr, device_type,
424 hw->mac.release_swfw_sync(hw, gssr);
429 * txgbe_identify_module - Identifies module type
430 * @hw: pointer to hardware structure
432 * Determines HW type and calls appropriate function.
434 s32 txgbe_identify_module(struct txgbe_hw *hw)
436 s32 err = TXGBE_ERR_SFP_NOT_PRESENT;
438 DEBUGFUNC("txgbe_identify_module");
440 switch (hw->phy.media_type) {
441 case txgbe_media_type_fiber:
442 err = txgbe_identify_sfp_module(hw);
445 case txgbe_media_type_fiber_qsfp:
446 err = txgbe_identify_qsfp_module(hw);
450 hw->phy.sfp_type = txgbe_sfp_type_not_present;
451 err = TXGBE_ERR_SFP_NOT_PRESENT;
459 * txgbe_identify_sfp_module - Identifies SFP modules
460 * @hw: pointer to hardware structure
462 * Searches for and identifies the SFP module and assigns appropriate PHY type.
464 s32 txgbe_identify_sfp_module(struct txgbe_hw *hw)
466 s32 err = TXGBE_ERR_PHY_ADDR_INVALID;
468 enum txgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
470 u8 comp_codes_1g = 0;
471 u8 comp_codes_10g = 0;
472 u8 oui_bytes[3] = {0, 0, 0};
477 DEBUGFUNC("txgbe_identify_sfp_module");
479 if (hw->phy.media_type != txgbe_media_type_fiber) {
480 hw->phy.sfp_type = txgbe_sfp_type_not_present;
481 return TXGBE_ERR_SFP_NOT_PRESENT;
484 err = hw->phy.read_i2c_eeprom(hw, TXGBE_SFF_IDENTIFIER,
488 hw->phy.sfp_type = txgbe_sfp_type_not_present;
489 if (hw->phy.type != txgbe_phy_nl) {
491 hw->phy.type = txgbe_phy_unknown;
493 return TXGBE_ERR_SFP_NOT_PRESENT;
496 if (identifier != TXGBE_SFF_IDENTIFIER_SFP) {
497 hw->phy.type = txgbe_phy_sfp_unsupported;
498 return TXGBE_ERR_SFP_NOT_SUPPORTED;
501 err = hw->phy.read_i2c_eeprom(hw, TXGBE_SFF_1GBE_COMP_CODES,
506 err = hw->phy.read_i2c_eeprom(hw, TXGBE_SFF_10GBE_COMP_CODES,
511 err = hw->phy.read_i2c_eeprom(hw, TXGBE_SFF_CABLE_TECHNOLOGY,
521 * 3 SFP_DA_CORE0 - chip-specific
522 * 4 SFP_DA_CORE1 - chip-specific
523 * 5 SFP_SR/LR_CORE0 - chip-specific
524 * 6 SFP_SR/LR_CORE1 - chip-specific
525 * 7 SFP_act_lmt_DA_CORE0 - chip-specific
526 * 8 SFP_act_lmt_DA_CORE1 - chip-specific
527 * 9 SFP_1g_cu_CORE0 - chip-specific
528 * 10 SFP_1g_cu_CORE1 - chip-specific
529 * 11 SFP_1g_sx_CORE0 - chip-specific
530 * 12 SFP_1g_sx_CORE1 - chip-specific
532 if (cable_tech & TXGBE_SFF_CABLE_DA_PASSIVE) {
533 if (hw->bus.lan_id == 0)
534 hw->phy.sfp_type = txgbe_sfp_type_da_cu_core0;
536 hw->phy.sfp_type = txgbe_sfp_type_da_cu_core1;
537 } else if (cable_tech & TXGBE_SFF_CABLE_DA_ACTIVE) {
538 err = hw->phy.read_i2c_eeprom(hw,
539 TXGBE_SFF_CABLE_SPEC_COMP, &cable_spec);
542 if (cable_spec & TXGBE_SFF_DA_SPEC_ACTIVE_LIMITING) {
543 hw->phy.sfp_type = (hw->bus.lan_id == 0
544 ? txgbe_sfp_type_da_act_lmt_core0
545 : txgbe_sfp_type_da_act_lmt_core1);
547 hw->phy.sfp_type = txgbe_sfp_type_unknown;
549 } else if (comp_codes_10g &
550 (TXGBE_SFF_10GBASESR_CAPABLE |
551 TXGBE_SFF_10GBASELR_CAPABLE)) {
552 hw->phy.sfp_type = (hw->bus.lan_id == 0
553 ? txgbe_sfp_type_srlr_core0
554 : txgbe_sfp_type_srlr_core1);
555 } else if (comp_codes_1g & TXGBE_SFF_1GBASET_CAPABLE) {
556 hw->phy.sfp_type = (hw->bus.lan_id == 0
557 ? txgbe_sfp_type_1g_cu_core0
558 : txgbe_sfp_type_1g_cu_core1);
559 } else if (comp_codes_1g & TXGBE_SFF_1GBASESX_CAPABLE) {
560 hw->phy.sfp_type = (hw->bus.lan_id == 0
561 ? txgbe_sfp_type_1g_sx_core0
562 : txgbe_sfp_type_1g_sx_core1);
563 } else if (comp_codes_1g & TXGBE_SFF_1GBASELX_CAPABLE) {
564 hw->phy.sfp_type = (hw->bus.lan_id == 0
565 ? txgbe_sfp_type_1g_lx_core0
566 : txgbe_sfp_type_1g_lx_core1);
568 hw->phy.sfp_type = txgbe_sfp_type_unknown;
571 if (hw->phy.sfp_type != stored_sfp_type)
572 hw->phy.sfp_setup_needed = true;
574 /* Determine if the SFP+ PHY is dual speed or not. */
575 hw->phy.multispeed_fiber = false;
576 if (((comp_codes_1g & TXGBE_SFF_1GBASESX_CAPABLE) &&
577 (comp_codes_10g & TXGBE_SFF_10GBASESR_CAPABLE)) ||
578 ((comp_codes_1g & TXGBE_SFF_1GBASELX_CAPABLE) &&
579 (comp_codes_10g & TXGBE_SFF_10GBASELR_CAPABLE)))
580 hw->phy.multispeed_fiber = true;
582 /* Determine PHY vendor */
583 if (hw->phy.type != txgbe_phy_nl) {
584 hw->phy.id = identifier;
585 err = hw->phy.read_i2c_eeprom(hw,
586 TXGBE_SFF_VENDOR_OUI_BYTE0, &oui_bytes[0]);
590 err = hw->phy.read_i2c_eeprom(hw,
591 TXGBE_SFF_VENDOR_OUI_BYTE1, &oui_bytes[1]);
595 err = hw->phy.read_i2c_eeprom(hw,
596 TXGBE_SFF_VENDOR_OUI_BYTE2, &oui_bytes[2]);
600 vendor_oui = ((u32)oui_bytes[0] << 24) |
601 ((u32)oui_bytes[1] << 16) |
602 ((u32)oui_bytes[2] << 8);
603 switch (vendor_oui) {
604 case TXGBE_SFF_VENDOR_OUI_TYCO:
605 if (cable_tech & TXGBE_SFF_CABLE_DA_PASSIVE)
606 hw->phy.type = txgbe_phy_sfp_tyco_passive;
608 case TXGBE_SFF_VENDOR_OUI_FTL:
609 if (cable_tech & TXGBE_SFF_CABLE_DA_ACTIVE)
610 hw->phy.type = txgbe_phy_sfp_ftl_active;
612 hw->phy.type = txgbe_phy_sfp_ftl;
614 case TXGBE_SFF_VENDOR_OUI_AVAGO:
615 hw->phy.type = txgbe_phy_sfp_avago;
617 case TXGBE_SFF_VENDOR_OUI_INTEL:
618 hw->phy.type = txgbe_phy_sfp_intel;
621 if (cable_tech & TXGBE_SFF_CABLE_DA_PASSIVE)
622 hw->phy.type = txgbe_phy_sfp_unknown_passive;
623 else if (cable_tech & TXGBE_SFF_CABLE_DA_ACTIVE)
624 hw->phy.type = txgbe_phy_sfp_unknown_active;
626 hw->phy.type = txgbe_phy_sfp_unknown;
631 /* Allow any DA cable vendor */
632 if (cable_tech & (TXGBE_SFF_CABLE_DA_PASSIVE |
633 TXGBE_SFF_CABLE_DA_ACTIVE)) {
637 /* Verify supported 1G SFP modules */
638 if (comp_codes_10g == 0 &&
639 !(hw->phy.sfp_type == txgbe_sfp_type_1g_cu_core1 ||
640 hw->phy.sfp_type == txgbe_sfp_type_1g_cu_core0 ||
641 hw->phy.sfp_type == txgbe_sfp_type_1g_lx_core0 ||
642 hw->phy.sfp_type == txgbe_sfp_type_1g_lx_core1 ||
643 hw->phy.sfp_type == txgbe_sfp_type_1g_sx_core0 ||
644 hw->phy.sfp_type == txgbe_sfp_type_1g_sx_core1)) {
645 hw->phy.type = txgbe_phy_sfp_unsupported;
646 return TXGBE_ERR_SFP_NOT_SUPPORTED;
649 hw->mac.get_device_caps(hw, &enforce_sfp);
650 if (!(enforce_sfp & TXGBE_DEVICE_CAPS_ALLOW_ANY_SFP) &&
651 !hw->allow_unsupported_sfp &&
652 !(hw->phy.sfp_type == txgbe_sfp_type_1g_cu_core0 ||
653 hw->phy.sfp_type == txgbe_sfp_type_1g_cu_core1 ||
654 hw->phy.sfp_type == txgbe_sfp_type_1g_lx_core0 ||
655 hw->phy.sfp_type == txgbe_sfp_type_1g_lx_core1 ||
656 hw->phy.sfp_type == txgbe_sfp_type_1g_sx_core0 ||
657 hw->phy.sfp_type == txgbe_sfp_type_1g_sx_core1)) {
658 DEBUGOUT("SFP+ module not supported\n");
659 hw->phy.type = txgbe_phy_sfp_unsupported;
660 return TXGBE_ERR_SFP_NOT_SUPPORTED;
667 * txgbe_identify_qsfp_module - Identifies QSFP modules
668 * @hw: pointer to hardware structure
670 * Searches for and identifies the QSFP module and assigns appropriate PHY type
672 s32 txgbe_identify_qsfp_module(struct txgbe_hw *hw)
674 s32 err = TXGBE_ERR_PHY_ADDR_INVALID;
676 enum txgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
678 u8 comp_codes_1g = 0;
679 u8 comp_codes_10g = 0;
680 u8 oui_bytes[3] = {0, 0, 0};
685 bool active_cable = false;
687 DEBUGFUNC("txgbe_identify_qsfp_module");
689 if (hw->phy.media_type != txgbe_media_type_fiber_qsfp) {
690 hw->phy.sfp_type = txgbe_sfp_type_not_present;
691 err = TXGBE_ERR_SFP_NOT_PRESENT;
695 err = hw->phy.read_i2c_eeprom(hw, TXGBE_SFF_IDENTIFIER,
699 hw->phy.sfp_type = txgbe_sfp_type_not_present;
701 hw->phy.type = txgbe_phy_unknown;
702 return TXGBE_ERR_SFP_NOT_PRESENT;
704 if (identifier != TXGBE_SFF_IDENTIFIER_QSFP_PLUS) {
705 hw->phy.type = txgbe_phy_sfp_unsupported;
706 err = TXGBE_ERR_SFP_NOT_SUPPORTED;
710 hw->phy.id = identifier;
712 err = hw->phy.read_i2c_eeprom(hw, TXGBE_SFF_QSFP_10GBE_COMP,
718 err = hw->phy.read_i2c_eeprom(hw, TXGBE_SFF_QSFP_1GBE_COMP,
724 if (comp_codes_10g & TXGBE_SFF_QSFP_DA_PASSIVE_CABLE) {
725 hw->phy.type = txgbe_phy_qsfp_unknown_passive;
726 if (hw->bus.lan_id == 0)
727 hw->phy.sfp_type = txgbe_sfp_type_da_cu_core0;
729 hw->phy.sfp_type = txgbe_sfp_type_da_cu_core1;
730 } else if (comp_codes_10g & (TXGBE_SFF_10GBASESR_CAPABLE |
731 TXGBE_SFF_10GBASELR_CAPABLE)) {
732 if (hw->bus.lan_id == 0)
733 hw->phy.sfp_type = txgbe_sfp_type_srlr_core0;
735 hw->phy.sfp_type = txgbe_sfp_type_srlr_core1;
737 if (comp_codes_10g & TXGBE_SFF_QSFP_DA_ACTIVE_CABLE)
741 hw->phy.read_i2c_eeprom(hw,
742 TXGBE_SFF_QSFP_CONNECTOR,
745 hw->phy.read_i2c_eeprom(hw,
746 TXGBE_SFF_QSFP_CABLE_LENGTH,
749 hw->phy.read_i2c_eeprom(hw,
750 TXGBE_SFF_QSFP_DEVICE_TECH,
754 TXGBE_SFF_QSFP_CONNECTOR_NOT_SEPARABLE &&
756 ((device_tech >> 4) ==
757 TXGBE_SFF_QSFP_TRANSMITTER_850NM_VCSEL))
762 hw->phy.type = txgbe_phy_qsfp_unknown_active;
763 if (hw->bus.lan_id == 0)
765 txgbe_sfp_type_da_act_lmt_core0;
768 txgbe_sfp_type_da_act_lmt_core1;
770 /* unsupported module type */
771 hw->phy.type = txgbe_phy_sfp_unsupported;
772 err = TXGBE_ERR_SFP_NOT_SUPPORTED;
777 if (hw->phy.sfp_type != stored_sfp_type)
778 hw->phy.sfp_setup_needed = true;
780 /* Determine if the QSFP+ PHY is dual speed or not. */
781 hw->phy.multispeed_fiber = false;
782 if (((comp_codes_1g & TXGBE_SFF_1GBASESX_CAPABLE) &&
783 (comp_codes_10g & TXGBE_SFF_10GBASESR_CAPABLE)) ||
784 ((comp_codes_1g & TXGBE_SFF_1GBASELX_CAPABLE) &&
785 (comp_codes_10g & TXGBE_SFF_10GBASELR_CAPABLE)))
786 hw->phy.multispeed_fiber = true;
788 /* Determine PHY vendor for optical modules */
789 if (comp_codes_10g & (TXGBE_SFF_10GBASESR_CAPABLE |
790 TXGBE_SFF_10GBASELR_CAPABLE)) {
791 err = hw->phy.read_i2c_eeprom(hw,
792 TXGBE_SFF_QSFP_VENDOR_OUI_BYTE0,
798 err = hw->phy.read_i2c_eeprom(hw,
799 TXGBE_SFF_QSFP_VENDOR_OUI_BYTE1,
805 err = hw->phy.read_i2c_eeprom(hw,
806 TXGBE_SFF_QSFP_VENDOR_OUI_BYTE2,
813 ((oui_bytes[0] << 24) |
814 (oui_bytes[1] << 16) |
815 (oui_bytes[2] << 8));
817 if (vendor_oui == TXGBE_SFF_VENDOR_OUI_INTEL)
818 hw->phy.type = txgbe_phy_qsfp_intel;
820 hw->phy.type = txgbe_phy_qsfp_unknown;
822 hw->mac.get_device_caps(hw, &enforce_sfp);
823 if (!(enforce_sfp & TXGBE_DEVICE_CAPS_ALLOW_ANY_SFP)) {
824 /* Make sure we're a supported PHY type */
825 if (hw->phy.type == txgbe_phy_qsfp_intel) {
828 if (hw->allow_unsupported_sfp) {
829 DEBUGOUT("WARNING: Wangxun (R) Network Connections are quality tested using Wangxun (R) Ethernet Optics. "
830 "Using untested modules is not supported and may cause unstable operation or damage to the module or the adapter. "
831 "Wangxun Corporation is not responsible for any harm caused by using untested modules.\n");
834 DEBUGOUT("QSFP module not supported\n");
836 txgbe_phy_sfp_unsupported;
837 err = TXGBE_ERR_SFP_NOT_SUPPORTED;
850 * txgbe_read_i2c_eeprom - Reads 8 bit EEPROM word over I2C interface
851 * @hw: pointer to hardware structure
852 * @byte_offset: EEPROM byte offset to read
853 * @eeprom_data: value read
855 * Performs byte read operation to SFP module's EEPROM over I2C interface.
857 s32 txgbe_read_i2c_eeprom(struct txgbe_hw *hw, u8 byte_offset,
860 DEBUGFUNC("txgbe_read_i2c_eeprom");
862 return hw->phy.read_i2c_byte(hw, byte_offset,
863 TXGBE_I2C_EEPROM_DEV_ADDR,
868 * txgbe_write_i2c_eeprom - Writes 8 bit EEPROM word over I2C interface
869 * @hw: pointer to hardware structure
870 * @byte_offset: EEPROM byte offset to write
871 * @eeprom_data: value to write
873 * Performs byte write operation to SFP module's EEPROM over I2C interface.
875 s32 txgbe_write_i2c_eeprom(struct txgbe_hw *hw, u8 byte_offset,
878 DEBUGFUNC("txgbe_write_i2c_eeprom");
880 return hw->phy.write_i2c_byte(hw, byte_offset,
881 TXGBE_I2C_EEPROM_DEV_ADDR,
886 * txgbe_read_i2c_byte_unlocked - Reads 8 bit word over I2C
887 * @hw: pointer to hardware structure
888 * @byte_offset: byte offset to read
889 * @dev_addr: address to read from
892 * Performs byte read operation to SFP module's EEPROM over I2C interface at
893 * a specified device address.
895 s32 txgbe_read_i2c_byte_unlocked(struct txgbe_hw *hw, u8 byte_offset,
896 u8 dev_addr, u8 *data)
898 UNREFERENCED_PARAMETER(dev_addr);
900 DEBUGFUNC("txgbe_read_i2c_byte");
905 if (!po32m(hw, TXGBE_I2CICR, TXGBE_I2CICR_TXEMPTY,
906 TXGBE_I2CICR_TXEMPTY, NULL, 100, 100)) {
907 return -TERR_TIMEOUT;
911 wr32(hw, TXGBE_I2CDATA,
912 byte_offset | TXGBE_I2CDATA_STOP);
913 wr32(hw, TXGBE_I2CDATA, TXGBE_I2CDATA_READ);
915 /* wait for read complete */
916 if (!po32m(hw, TXGBE_I2CICR, TXGBE_I2CICR_RXFULL,
917 TXGBE_I2CICR_RXFULL, NULL, 100, 100)) {
918 return -TERR_TIMEOUT;
923 *data = 0xFF & rd32(hw, TXGBE_I2CDATA);
929 * txgbe_read_i2c_byte - Reads 8 bit word over I2C
930 * @hw: pointer to hardware structure
931 * @byte_offset: byte offset to read
932 * @dev_addr: address to read from
935 * Performs byte read operation to SFP module's EEPROM over I2C interface at
936 * a specified device address.
938 s32 txgbe_read_i2c_byte(struct txgbe_hw *hw, u8 byte_offset,
939 u8 dev_addr, u8 *data)
941 u32 swfw_mask = hw->phy.phy_semaphore_mask;
944 if (hw->mac.acquire_swfw_sync(hw, swfw_mask))
945 return TXGBE_ERR_SWFW_SYNC;
946 err = txgbe_read_i2c_byte_unlocked(hw, byte_offset, dev_addr, data);
947 hw->mac.release_swfw_sync(hw, swfw_mask);
952 * txgbe_write_i2c_byte_unlocked - Writes 8 bit word over I2C
953 * @hw: pointer to hardware structure
954 * @byte_offset: byte offset to write
955 * @dev_addr: address to write to
956 * @data: value to write
958 * Performs byte write operation to SFP module's EEPROM over I2C interface at
959 * a specified device address.
961 s32 txgbe_write_i2c_byte_unlocked(struct txgbe_hw *hw, u8 byte_offset,
962 u8 dev_addr, u8 data)
964 UNREFERENCED_PARAMETER(dev_addr);
966 DEBUGFUNC("txgbe_write_i2c_byte");
971 if (!po32m(hw, TXGBE_I2CICR, TXGBE_I2CICR_TXEMPTY,
972 TXGBE_I2CICR_TXEMPTY, NULL, 100, 100)) {
973 return -TERR_TIMEOUT;
976 wr32(hw, TXGBE_I2CDATA, byte_offset | TXGBE_I2CDATA_STOP);
977 wr32(hw, TXGBE_I2CDATA, data | TXGBE_I2CDATA_WRITE);
979 /* wait for write complete */
980 if (!po32m(hw, TXGBE_I2CICR, TXGBE_I2CICR_RXFULL,
981 TXGBE_I2CICR_RXFULL, NULL, 100, 100)) {
982 return -TERR_TIMEOUT;
990 * txgbe_write_i2c_byte - Writes 8 bit word over I2C
991 * @hw: pointer to hardware structure
992 * @byte_offset: byte offset to write
993 * @dev_addr: address to write to
994 * @data: value to write
996 * Performs byte write operation to SFP module's EEPROM over I2C interface at
997 * a specified device address.
999 s32 txgbe_write_i2c_byte(struct txgbe_hw *hw, u8 byte_offset,
1000 u8 dev_addr, u8 data)
1002 u32 swfw_mask = hw->phy.phy_semaphore_mask;
1005 if (hw->mac.acquire_swfw_sync(hw, swfw_mask))
1006 return TXGBE_ERR_SWFW_SYNC;
1007 err = txgbe_write_i2c_byte_unlocked(hw, byte_offset, dev_addr, data);
1008 hw->mac.release_swfw_sync(hw, swfw_mask);
1014 * txgbe_i2c_start - Sets I2C start condition
1015 * @hw: pointer to hardware structure
1017 * Sets I2C start condition (High -> Low on SDA while SCL is High)
1019 static void txgbe_i2c_start(struct txgbe_hw *hw)
1021 DEBUGFUNC("txgbe_i2c_start");
1023 wr32(hw, TXGBE_I2CENA, 0);
1025 wr32(hw, TXGBE_I2CCON,
1026 (TXGBE_I2CCON_MENA |
1027 TXGBE_I2CCON_SPEED(1) |
1028 TXGBE_I2CCON_RESTART |
1029 TXGBE_I2CCON_SDIA));
1030 wr32(hw, TXGBE_I2CTAR, TXGBE_I2C_SLAVEADDR);
1031 wr32(hw, TXGBE_I2CSSSCLHCNT, 600);
1032 wr32(hw, TXGBE_I2CSSSCLLCNT, 600);
1033 wr32(hw, TXGBE_I2CRXTL, 0); /* 1byte for rx full signal */
1034 wr32(hw, TXGBE_I2CTXTL, 4);
1035 wr32(hw, TXGBE_I2CSCLTMOUT, 0xFFFFFF);
1036 wr32(hw, TXGBE_I2CSDATMOUT, 0xFFFFFF);
1038 wr32(hw, TXGBE_I2CICM, 0);
1039 wr32(hw, TXGBE_I2CENA, 1);
1043 * txgbe_i2c_stop - Sets I2C stop condition
1044 * @hw: pointer to hardware structure
1046 * Sets I2C stop condition (Low -> High on SDA while SCL is High)
1048 static void txgbe_i2c_stop(struct txgbe_hw *hw)
1050 DEBUGFUNC("txgbe_i2c_stop");
1052 /* wait for completion */
1053 if (!po32m(hw, TXGBE_I2CSTAT, TXGBE_I2CSTAT_MST,
1054 0, NULL, 100, 100)) {
1055 DEBUGFUNC("i2c stop timeout.");
1058 wr32(hw, TXGBE_I2CENA, 0);