1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2015-2020
6 #include "txgbe_eeprom.h"
10 static void txgbe_i2c_start(struct txgbe_hw *hw);
11 static void txgbe_i2c_stop(struct txgbe_hw *hw);
14 * txgbe_identify_extphy - Identify a single address for a PHY
15 * @hw: pointer to hardware structure
16 * @phy_addr: PHY address to probe
18 * Returns true if PHY found
20 static bool txgbe_identify_extphy(struct txgbe_hw *hw)
24 if (!txgbe_validate_phy_addr(hw, phy_addr)) {
25 DEBUGOUT("Unable to validate PHY address 0x%04X\n",
30 if (txgbe_get_phy_id(hw))
33 hw->phy.type = txgbe_get_phy_type_from_id(hw->phy.id);
34 if (hw->phy.type == txgbe_phy_unknown) {
36 hw->phy.read_reg(hw, TXGBE_MD_PHY_EXT_ABILITY,
40 if (ext_ability & (TXGBE_MD_PHY_10GBASET_ABILITY |
41 TXGBE_MD_PHY_1000BASET_ABILITY))
42 hw->phy.type = txgbe_phy_cu_unknown;
44 hw->phy.type = txgbe_phy_generic;
51 * txgbe_read_phy_if - Read TXGBE_ETHPHYIF register
52 * @hw: pointer to hardware structure
54 * Read TXGBE_ETHPHYIF register and save field values,
55 * and check for valid field values.
57 static s32 txgbe_read_phy_if(struct txgbe_hw *hw)
59 hw->phy.media_type = hw->phy.get_media_type(hw);
61 /* Save NW management interface connected on board. This is used
62 * to determine internal PHY mode.
64 hw->phy.nw_mng_if_sel = rd32(hw, TXGBE_ETHPHYIF);
66 /* If MDIO is connected to external PHY, then set PHY address. */
67 if (hw->phy.nw_mng_if_sel & TXGBE_ETHPHYIF_MDIO_ACT)
68 hw->phy.addr = TXGBE_ETHPHYIF_MDIO_BASE(hw->phy.nw_mng_if_sel);
70 if (!hw->phy.phy_semaphore_mask) {
72 hw->phy.phy_semaphore_mask = TXGBE_MNGSEM_SWPHY;
74 hw->phy.phy_semaphore_mask = TXGBE_MNGSEM_SWPHY;
81 * txgbe_identify_phy - Get physical layer module
82 * @hw: pointer to hardware structure
84 * Determines the physical layer module found on the current adapter.
86 s32 txgbe_identify_phy(struct txgbe_hw *hw)
88 s32 err = TXGBE_ERR_PHY_ADDR_INVALID;
90 DEBUGFUNC("txgbe_identify_phy");
92 txgbe_read_phy_if(hw);
94 if (hw->phy.type != txgbe_phy_unknown)
97 /* Raptor 10GBASE-T requires an external PHY */
98 if (hw->phy.media_type == txgbe_media_type_copper) {
99 err = txgbe_identify_extphy(hw);
100 } else if (hw->phy.media_type == txgbe_media_type_fiber) {
101 err = txgbe_identify_module(hw);
103 hw->phy.type = txgbe_phy_none;
107 /* Return error if SFP module has been detected but is not supported */
108 if (hw->phy.type == txgbe_phy_sfp_unsupported)
109 return TXGBE_ERR_SFP_NOT_SUPPORTED;
115 * txgbe_check_reset_blocked - check status of MNG FW veto bit
116 * @hw: pointer to the hardware structure
118 * This function checks the STAT.MNGVETO bit to see if there are
119 * any constraints on link from manageability. For MAC's that don't
120 * have this bit just return faluse since the link can not be blocked
123 s32 txgbe_check_reset_blocked(struct txgbe_hw *hw)
127 DEBUGFUNC("txgbe_check_reset_blocked");
129 mmngc = rd32(hw, TXGBE_STAT);
130 if (mmngc & TXGBE_STAT_MNGVETO) {
131 DEBUGOUT("MNG_VETO bit detected.\n");
139 * txgbe_validate_phy_addr - Determines phy address is valid
140 * @hw: pointer to hardware structure
141 * @phy_addr: PHY address
144 bool txgbe_validate_phy_addr(struct txgbe_hw *hw, u32 phy_addr)
149 DEBUGFUNC("txgbe_validate_phy_addr");
151 hw->phy.addr = phy_addr;
152 hw->phy.read_reg(hw, TXGBE_MD_PHY_ID_HIGH,
153 TXGBE_MD_DEV_PMA_PMD, &phy_id);
155 if (phy_id != 0xFFFF && phy_id != 0x0)
158 DEBUGOUT("PHY ID HIGH is 0x%04X\n", phy_id);
164 * txgbe_get_phy_id - Get the phy type
165 * @hw: pointer to hardware structure
168 s32 txgbe_get_phy_id(struct txgbe_hw *hw)
174 DEBUGFUNC("txgbe_get_phy_id");
176 err = hw->phy.read_reg(hw, TXGBE_MD_PHY_ID_HIGH,
177 TXGBE_MD_DEV_PMA_PMD,
181 hw->phy.id = (u32)(phy_id_high << 16);
182 err = hw->phy.read_reg(hw, TXGBE_MD_PHY_ID_LOW,
183 TXGBE_MD_DEV_PMA_PMD,
185 hw->phy.id |= (u32)(phy_id_low & TXGBE_PHY_REVISION_MASK);
186 hw->phy.revision = (u32)(phy_id_low & ~TXGBE_PHY_REVISION_MASK);
188 DEBUGOUT("PHY_ID_HIGH 0x%04X, PHY_ID_LOW 0x%04X\n",
189 phy_id_high, phy_id_low);
195 * txgbe_get_phy_type_from_id - Get the phy type
196 * @phy_id: PHY ID information
199 enum txgbe_phy_type txgbe_get_phy_type_from_id(u32 phy_id)
201 enum txgbe_phy_type phy_type;
203 DEBUGFUNC("txgbe_get_phy_type_from_id");
206 case TXGBE_PHYID_TN1010:
207 phy_type = txgbe_phy_tn;
209 case TXGBE_PHYID_QT2022:
210 phy_type = txgbe_phy_qt;
212 case TXGBE_PHYID_ATH:
213 phy_type = txgbe_phy_nl;
215 case TXGBE_PHYID_MTD3310:
216 phy_type = txgbe_phy_cu_mtd;
219 phy_type = txgbe_phy_unknown;
227 txgbe_reset_extphy(struct txgbe_hw *hw)
232 err = hw->phy.read_reg(hw, TXGBE_MD_PORT_CTRL,
233 TXGBE_MD_DEV_GENERAL, &ctrl);
236 ctrl |= TXGBE_MD_PORT_CTRL_RESET;
237 err = hw->phy.write_reg(hw, TXGBE_MD_PORT_CTRL,
238 TXGBE_MD_DEV_GENERAL, ctrl);
243 * Poll for reset bit to self-clear indicating reset is complete.
244 * Some PHYs could take up to 3 seconds to complete and need about
245 * 1.7 usec delay after the reset is complete.
247 for (i = 0; i < 30; i++) {
249 err = hw->phy.read_reg(hw, TXGBE_MD_PORT_CTRL,
250 TXGBE_MD_DEV_GENERAL, &ctrl);
254 if (!(ctrl & TXGBE_MD_PORT_CTRL_RESET)) {
260 if (ctrl & TXGBE_MD_PORT_CTRL_RESET) {
261 err = TXGBE_ERR_RESET_FAILED;
262 DEBUGOUT("PHY reset polling failed to complete.\n");
269 * txgbe_reset_phy - Performs a PHY reset
270 * @hw: pointer to hardware structure
272 s32 txgbe_reset_phy(struct txgbe_hw *hw)
276 DEBUGFUNC("txgbe_reset_phy");
278 if (hw->phy.type == txgbe_phy_unknown)
279 err = txgbe_identify_phy(hw);
281 if (err != 0 || hw->phy.type == txgbe_phy_none)
284 /* Don't reset PHY if it's shut down due to overtemp. */
285 if (hw->phy.check_overtemp(hw) == TXGBE_ERR_OVERTEMP)
288 /* Blocked by MNG FW so bail */
289 if (txgbe_check_reset_blocked(hw))
292 switch (hw->phy.type) {
293 case txgbe_phy_cu_mtd:
294 err = txgbe_reset_extphy(hw);
304 * txgbe_read_phy_mdi - Reads a value from a specified PHY register without
306 * @hw: pointer to hardware structure
307 * @reg_addr: 32 bit address of PHY register to read
308 * @device_type: 5 bit device type
309 * @phy_data: Pointer to read data from PHY register
311 s32 txgbe_read_phy_reg_mdi(struct txgbe_hw *hw, u32 reg_addr, u32 device_type,
316 /* Setup and write the address cycle command */
317 command = TXGBE_MDIOSCA_REG(reg_addr) |
318 TXGBE_MDIOSCA_DEV(device_type) |
319 TXGBE_MDIOSCA_PORT(hw->phy.addr);
320 wr32(hw, TXGBE_MDIOSCA, command);
322 command = TXGBE_MDIOSCD_CMD_READ |
324 wr32(hw, TXGBE_MDIOSCD, command);
327 * Check every 10 usec to see if the address cycle completed.
328 * The MDI Command bit will clear when the operation is
331 if (!po32m(hw, TXGBE_MDIOSCD, TXGBE_MDIOSCD_BUSY,
332 0, NULL, 100, 100)) {
333 DEBUGOUT("PHY address command did not complete\n");
334 return TXGBE_ERR_PHY;
337 data = rd32(hw, TXGBE_MDIOSCD);
338 *phy_data = (u16)TXGBD_MDIOSCD_DAT(data);
344 * txgbe_read_phy_reg - Reads a value from a specified PHY register
345 * using the SWFW lock - this function is needed in most cases
346 * @hw: pointer to hardware structure
347 * @reg_addr: 32 bit address of PHY register to read
348 * @device_type: 5 bit device type
349 * @phy_data: Pointer to read data from PHY register
351 s32 txgbe_read_phy_reg(struct txgbe_hw *hw, u32 reg_addr,
352 u32 device_type, u16 *phy_data)
355 u32 gssr = hw->phy.phy_semaphore_mask;
357 DEBUGFUNC("txgbe_read_phy_reg");
359 if (hw->mac.acquire_swfw_sync(hw, gssr))
360 return TXGBE_ERR_SWFW_SYNC;
362 err = hw->phy.read_reg_mdi(hw, reg_addr, device_type, phy_data);
364 hw->mac.release_swfw_sync(hw, gssr);
370 * txgbe_write_phy_reg_mdi - Writes a value to specified PHY register
372 * @hw: pointer to hardware structure
373 * @reg_addr: 32 bit PHY register to write
374 * @device_type: 5 bit device type
375 * @phy_data: Data to write to the PHY register
377 s32 txgbe_write_phy_reg_mdi(struct txgbe_hw *hw, u32 reg_addr,
378 u32 device_type, u16 phy_data)
383 command = TXGBE_MDIOSCA_REG(reg_addr) |
384 TXGBE_MDIOSCA_DEV(device_type) |
385 TXGBE_MDIOSCA_PORT(hw->phy.addr);
386 wr32(hw, TXGBE_MDIOSCA, command);
388 command = TXGBE_MDIOSCD_CMD_WRITE |
389 TXGBE_MDIOSCD_DAT(phy_data) |
391 wr32(hw, TXGBE_MDIOSCD, command);
393 /* wait for completion */
394 if (!po32m(hw, TXGBE_MDIOSCD, TXGBE_MDIOSCD_BUSY,
395 0, NULL, 100, 100)) {
396 TLOG_DEBUG("PHY write cmd didn't complete\n");
404 * txgbe_write_phy_reg - Writes a value to specified PHY register
405 * using SWFW lock- this function is needed in most cases
406 * @hw: pointer to hardware structure
407 * @reg_addr: 32 bit PHY register to write
408 * @device_type: 5 bit device type
409 * @phy_data: Data to write to the PHY register
411 s32 txgbe_write_phy_reg(struct txgbe_hw *hw, u32 reg_addr,
412 u32 device_type, u16 phy_data)
415 u32 gssr = hw->phy.phy_semaphore_mask;
417 DEBUGFUNC("txgbe_write_phy_reg");
419 if (hw->mac.acquire_swfw_sync(hw, gssr))
420 err = TXGBE_ERR_SWFW_SYNC;
422 err = hw->phy.write_reg_mdi(hw, reg_addr, device_type,
424 hw->mac.release_swfw_sync(hw, gssr);
430 * txgbe_setup_phy_link - Set and restart auto-neg
431 * @hw: pointer to hardware structure
433 * Restart auto-negotiation and PHY and waits for completion.
435 s32 txgbe_setup_phy_link(struct txgbe_hw *hw)
438 u16 autoneg_reg = TXGBE_MII_AUTONEG_REG;
439 bool autoneg = false;
442 DEBUGFUNC("txgbe_setup_phy_link");
444 txgbe_get_copper_link_capabilities(hw, &speed, &autoneg);
446 /* Set or unset auto-negotiation 10G advertisement */
447 hw->phy.read_reg(hw, TXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
448 TXGBE_MD_DEV_AUTO_NEG,
451 autoneg_reg &= ~TXGBE_MII_10GBASE_T_ADVERTISE;
452 if ((hw->phy.autoneg_advertised & TXGBE_LINK_SPEED_10GB_FULL) &&
453 (speed & TXGBE_LINK_SPEED_10GB_FULL))
454 autoneg_reg |= TXGBE_MII_10GBASE_T_ADVERTISE;
456 hw->phy.write_reg(hw, TXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
457 TXGBE_MD_DEV_AUTO_NEG,
460 hw->phy.read_reg(hw, TXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
461 TXGBE_MD_DEV_AUTO_NEG,
464 /* Set or unset auto-negotiation 5G advertisement */
465 autoneg_reg &= ~TXGBE_MII_5GBASE_T_ADVERTISE;
466 if ((hw->phy.autoneg_advertised & TXGBE_LINK_SPEED_5GB_FULL) &&
467 (speed & TXGBE_LINK_SPEED_5GB_FULL))
468 autoneg_reg |= TXGBE_MII_5GBASE_T_ADVERTISE;
470 /* Set or unset auto-negotiation 2.5G advertisement */
471 autoneg_reg &= ~TXGBE_MII_2_5GBASE_T_ADVERTISE;
472 if ((hw->phy.autoneg_advertised &
473 TXGBE_LINK_SPEED_2_5GB_FULL) &&
474 (speed & TXGBE_LINK_SPEED_2_5GB_FULL))
475 autoneg_reg |= TXGBE_MII_2_5GBASE_T_ADVERTISE;
476 /* Set or unset auto-negotiation 1G advertisement */
477 autoneg_reg &= ~TXGBE_MII_1GBASE_T_ADVERTISE;
478 if ((hw->phy.autoneg_advertised & TXGBE_LINK_SPEED_1GB_FULL) &&
479 (speed & TXGBE_LINK_SPEED_1GB_FULL))
480 autoneg_reg |= TXGBE_MII_1GBASE_T_ADVERTISE;
482 hw->phy.write_reg(hw, TXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
483 TXGBE_MD_DEV_AUTO_NEG,
486 /* Set or unset auto-negotiation 100M advertisement */
487 hw->phy.read_reg(hw, TXGBE_MII_AUTONEG_ADVERTISE_REG,
488 TXGBE_MD_DEV_AUTO_NEG,
491 autoneg_reg &= ~(TXGBE_MII_100BASE_T_ADVERTISE |
492 TXGBE_MII_100BASE_T_ADVERTISE_HALF);
493 if ((hw->phy.autoneg_advertised & TXGBE_LINK_SPEED_100M_FULL) &&
494 (speed & TXGBE_LINK_SPEED_100M_FULL))
495 autoneg_reg |= TXGBE_MII_100BASE_T_ADVERTISE;
497 hw->phy.write_reg(hw, TXGBE_MII_AUTONEG_ADVERTISE_REG,
498 TXGBE_MD_DEV_AUTO_NEG,
501 /* Blocked by MNG FW so don't reset PHY */
502 if (txgbe_check_reset_blocked(hw))
505 /* Restart PHY auto-negotiation. */
506 hw->phy.read_reg(hw, TXGBE_MD_AUTO_NEG_CONTROL,
507 TXGBE_MD_DEV_AUTO_NEG, &autoneg_reg);
509 autoneg_reg |= TXGBE_MII_RESTART;
511 hw->phy.write_reg(hw, TXGBE_MD_AUTO_NEG_CONTROL,
512 TXGBE_MD_DEV_AUTO_NEG, autoneg_reg);
518 * txgbe_setup_phy_link_speed - Sets the auto advertised capabilities
519 * @hw: pointer to hardware structure
520 * @speed: new link speed
521 * @autoneg_wait_to_complete: unused
523 s32 txgbe_setup_phy_link_speed(struct txgbe_hw *hw,
525 bool autoneg_wait_to_complete)
527 UNREFERENCED_PARAMETER(autoneg_wait_to_complete);
529 DEBUGFUNC("txgbe_setup_phy_link_speed");
532 * Clear autoneg_advertised and set new values based on input link
535 hw->phy.autoneg_advertised = 0;
537 if (speed & TXGBE_LINK_SPEED_10GB_FULL)
538 hw->phy.autoneg_advertised |= TXGBE_LINK_SPEED_10GB_FULL;
540 if (speed & TXGBE_LINK_SPEED_5GB_FULL)
541 hw->phy.autoneg_advertised |= TXGBE_LINK_SPEED_5GB_FULL;
543 if (speed & TXGBE_LINK_SPEED_2_5GB_FULL)
544 hw->phy.autoneg_advertised |= TXGBE_LINK_SPEED_2_5GB_FULL;
546 if (speed & TXGBE_LINK_SPEED_1GB_FULL)
547 hw->phy.autoneg_advertised |= TXGBE_LINK_SPEED_1GB_FULL;
549 if (speed & TXGBE_LINK_SPEED_100M_FULL)
550 hw->phy.autoneg_advertised |= TXGBE_LINK_SPEED_100M_FULL;
552 if (speed & TXGBE_LINK_SPEED_10M_FULL)
553 hw->phy.autoneg_advertised |= TXGBE_LINK_SPEED_10M_FULL;
555 /* Setup link based on the new speed settings */
556 hw->phy.setup_link(hw);
562 * txgbe_get_copper_speeds_supported - Get copper link speeds from phy
563 * @hw: pointer to hardware structure
565 * Determines the supported link capabilities by reading the PHY auto
566 * negotiation register.
568 static s32 txgbe_get_copper_speeds_supported(struct txgbe_hw *hw)
573 err = hw->phy.read_reg(hw, TXGBE_MD_PHY_SPEED_ABILITY,
574 TXGBE_MD_DEV_PMA_PMD,
579 if (speed_ability & TXGBE_MD_PHY_SPEED_10G)
580 hw->phy.speeds_supported |= TXGBE_LINK_SPEED_10GB_FULL;
581 if (speed_ability & TXGBE_MD_PHY_SPEED_1G)
582 hw->phy.speeds_supported |= TXGBE_LINK_SPEED_1GB_FULL;
583 if (speed_ability & TXGBE_MD_PHY_SPEED_100M)
584 hw->phy.speeds_supported |= TXGBE_LINK_SPEED_100M_FULL;
590 * txgbe_get_copper_link_capabilities - Determines link capabilities
591 * @hw: pointer to hardware structure
592 * @speed: pointer to link speed
593 * @autoneg: boolean auto-negotiation value
595 s32 txgbe_get_copper_link_capabilities(struct txgbe_hw *hw,
601 DEBUGFUNC("txgbe_get_copper_link_capabilities");
604 if (!hw->phy.speeds_supported)
605 err = txgbe_get_copper_speeds_supported(hw);
607 *speed = hw->phy.speeds_supported;
612 * txgbe_check_phy_link_tnx - Determine link and speed status
613 * @hw: pointer to hardware structure
614 * @speed: current link speed
615 * @link_up: true is link is up, false otherwise
617 * Reads the VS1 register to determine if link is up and the current speed for
620 s32 txgbe_check_phy_link_tnx(struct txgbe_hw *hw, u32 *speed,
625 u32 max_time_out = 10;
630 DEBUGFUNC("txgbe_check_phy_link_tnx");
632 /* Initialize speed and link to default case */
634 *speed = TXGBE_LINK_SPEED_10GB_FULL;
637 * Check current speed and link status of the PHY register.
638 * This is a vendor specific register and may have to
639 * be changed for other copper PHYs.
641 for (time_out = 0; time_out < max_time_out; time_out++) {
643 err = hw->phy.read_reg(hw,
644 TXGBE_MD_VENDOR_SPECIFIC_1_STATUS,
645 TXGBE_MD_DEV_VENDOR_1,
647 phy_link = phy_data & TXGBE_MD_VENDOR_SPECIFIC_1_LINK_STATUS;
648 phy_speed = phy_data &
649 TXGBE_MD_VENDOR_SPECIFIC_1_SPEED_STATUS;
650 if (phy_link == TXGBE_MD_VENDOR_SPECIFIC_1_LINK_STATUS) {
653 TXGBE_MD_VENDOR_SPECIFIC_1_SPEED_STATUS)
654 *speed = TXGBE_LINK_SPEED_1GB_FULL;
663 * txgbe_setup_phy_link_tnx - Set and restart auto-neg
664 * @hw: pointer to hardware structure
666 * Restart auto-negotiation and PHY and waits for completion.
668 s32 txgbe_setup_phy_link_tnx(struct txgbe_hw *hw)
671 u16 autoneg_reg = TXGBE_MII_AUTONEG_REG;
672 bool autoneg = false;
675 DEBUGFUNC("txgbe_setup_phy_link_tnx");
677 txgbe_get_copper_link_capabilities(hw, &speed, &autoneg);
679 if (speed & TXGBE_LINK_SPEED_10GB_FULL) {
680 /* Set or unset auto-negotiation 10G advertisement */
681 hw->phy.read_reg(hw, TXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
682 TXGBE_MD_DEV_AUTO_NEG,
685 autoneg_reg &= ~TXGBE_MII_10GBASE_T_ADVERTISE;
686 if (hw->phy.autoneg_advertised & TXGBE_LINK_SPEED_10GB_FULL)
687 autoneg_reg |= TXGBE_MII_10GBASE_T_ADVERTISE;
689 hw->phy.write_reg(hw, TXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
690 TXGBE_MD_DEV_AUTO_NEG,
694 if (speed & TXGBE_LINK_SPEED_1GB_FULL) {
695 /* Set or unset auto-negotiation 1G advertisement */
696 hw->phy.read_reg(hw, TXGBE_MII_AUTONEG_XNP_TX_REG,
697 TXGBE_MD_DEV_AUTO_NEG,
700 autoneg_reg &= ~TXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
701 if (hw->phy.autoneg_advertised & TXGBE_LINK_SPEED_1GB_FULL)
702 autoneg_reg |= TXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
704 hw->phy.write_reg(hw, TXGBE_MII_AUTONEG_XNP_TX_REG,
705 TXGBE_MD_DEV_AUTO_NEG,
709 if (speed & TXGBE_LINK_SPEED_100M_FULL) {
710 /* Set or unset auto-negotiation 100M advertisement */
711 hw->phy.read_reg(hw, TXGBE_MII_AUTONEG_ADVERTISE_REG,
712 TXGBE_MD_DEV_AUTO_NEG,
715 autoneg_reg &= ~TXGBE_MII_100BASE_T_ADVERTISE;
716 if (hw->phy.autoneg_advertised & TXGBE_LINK_SPEED_100M_FULL)
717 autoneg_reg |= TXGBE_MII_100BASE_T_ADVERTISE;
719 hw->phy.write_reg(hw, TXGBE_MII_AUTONEG_ADVERTISE_REG,
720 TXGBE_MD_DEV_AUTO_NEG,
724 /* Blocked by MNG FW so don't reset PHY */
725 if (txgbe_check_reset_blocked(hw))
728 /* Restart PHY auto-negotiation. */
729 hw->phy.read_reg(hw, TXGBE_MD_AUTO_NEG_CONTROL,
730 TXGBE_MD_DEV_AUTO_NEG, &autoneg_reg);
732 autoneg_reg |= TXGBE_MII_RESTART;
734 hw->phy.write_reg(hw, TXGBE_MD_AUTO_NEG_CONTROL,
735 TXGBE_MD_DEV_AUTO_NEG, autoneg_reg);
741 * txgbe_identify_module - Identifies module type
742 * @hw: pointer to hardware structure
744 * Determines HW type and calls appropriate function.
746 s32 txgbe_identify_module(struct txgbe_hw *hw)
748 s32 err = TXGBE_ERR_SFP_NOT_PRESENT;
750 DEBUGFUNC("txgbe_identify_module");
752 switch (hw->phy.media_type) {
753 case txgbe_media_type_fiber:
754 err = txgbe_identify_sfp_module(hw);
757 case txgbe_media_type_fiber_qsfp:
758 err = txgbe_identify_qsfp_module(hw);
762 hw->phy.sfp_type = txgbe_sfp_type_not_present;
763 err = TXGBE_ERR_SFP_NOT_PRESENT;
771 * txgbe_identify_sfp_module - Identifies SFP modules
772 * @hw: pointer to hardware structure
774 * Searches for and identifies the SFP module and assigns appropriate PHY type.
776 s32 txgbe_identify_sfp_module(struct txgbe_hw *hw)
778 s32 err = TXGBE_ERR_PHY_ADDR_INVALID;
780 enum txgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
782 u8 comp_codes_1g = 0;
783 u8 comp_codes_10g = 0;
784 u8 oui_bytes[3] = {0, 0, 0};
789 DEBUGFUNC("txgbe_identify_sfp_module");
791 if (hw->phy.media_type != txgbe_media_type_fiber) {
792 hw->phy.sfp_type = txgbe_sfp_type_not_present;
793 return TXGBE_ERR_SFP_NOT_PRESENT;
796 err = hw->phy.read_i2c_eeprom(hw, TXGBE_SFF_IDENTIFIER,
800 hw->phy.sfp_type = txgbe_sfp_type_not_present;
801 if (hw->phy.type != txgbe_phy_nl) {
803 hw->phy.type = txgbe_phy_unknown;
805 return TXGBE_ERR_SFP_NOT_PRESENT;
808 if (identifier != TXGBE_SFF_IDENTIFIER_SFP) {
809 hw->phy.type = txgbe_phy_sfp_unsupported;
810 return TXGBE_ERR_SFP_NOT_SUPPORTED;
813 err = hw->phy.read_i2c_eeprom(hw, TXGBE_SFF_1GBE_COMP_CODES,
818 err = hw->phy.read_i2c_eeprom(hw, TXGBE_SFF_10GBE_COMP_CODES,
823 err = hw->phy.read_i2c_eeprom(hw, TXGBE_SFF_CABLE_TECHNOLOGY,
833 * 3 SFP_DA_CORE0 - chip-specific
834 * 4 SFP_DA_CORE1 - chip-specific
835 * 5 SFP_SR/LR_CORE0 - chip-specific
836 * 6 SFP_SR/LR_CORE1 - chip-specific
837 * 7 SFP_act_lmt_DA_CORE0 - chip-specific
838 * 8 SFP_act_lmt_DA_CORE1 - chip-specific
839 * 9 SFP_1g_cu_CORE0 - chip-specific
840 * 10 SFP_1g_cu_CORE1 - chip-specific
841 * 11 SFP_1g_sx_CORE0 - chip-specific
842 * 12 SFP_1g_sx_CORE1 - chip-specific
844 if (cable_tech & TXGBE_SFF_CABLE_DA_PASSIVE) {
845 if (hw->bus.lan_id == 0)
846 hw->phy.sfp_type = txgbe_sfp_type_da_cu_core0;
848 hw->phy.sfp_type = txgbe_sfp_type_da_cu_core1;
849 } else if (cable_tech & TXGBE_SFF_CABLE_DA_ACTIVE) {
850 err = hw->phy.read_i2c_eeprom(hw,
851 TXGBE_SFF_CABLE_SPEC_COMP, &cable_spec);
854 if (cable_spec & TXGBE_SFF_DA_SPEC_ACTIVE_LIMITING) {
855 hw->phy.sfp_type = (hw->bus.lan_id == 0
856 ? txgbe_sfp_type_da_act_lmt_core0
857 : txgbe_sfp_type_da_act_lmt_core1);
859 hw->phy.sfp_type = txgbe_sfp_type_unknown;
861 } else if (comp_codes_10g &
862 (TXGBE_SFF_10GBASESR_CAPABLE |
863 TXGBE_SFF_10GBASELR_CAPABLE)) {
864 hw->phy.sfp_type = (hw->bus.lan_id == 0
865 ? txgbe_sfp_type_srlr_core0
866 : txgbe_sfp_type_srlr_core1);
867 } else if (comp_codes_1g & TXGBE_SFF_1GBASET_CAPABLE) {
868 hw->phy.sfp_type = (hw->bus.lan_id == 0
869 ? txgbe_sfp_type_1g_cu_core0
870 : txgbe_sfp_type_1g_cu_core1);
871 } else if (comp_codes_1g & TXGBE_SFF_1GBASESX_CAPABLE) {
872 hw->phy.sfp_type = (hw->bus.lan_id == 0
873 ? txgbe_sfp_type_1g_sx_core0
874 : txgbe_sfp_type_1g_sx_core1);
875 } else if (comp_codes_1g & TXGBE_SFF_1GBASELX_CAPABLE) {
876 hw->phy.sfp_type = (hw->bus.lan_id == 0
877 ? txgbe_sfp_type_1g_lx_core0
878 : txgbe_sfp_type_1g_lx_core1);
880 hw->phy.sfp_type = txgbe_sfp_type_unknown;
883 if (hw->phy.sfp_type != stored_sfp_type)
884 hw->phy.sfp_setup_needed = true;
886 /* Determine if the SFP+ PHY is dual speed or not. */
887 hw->phy.multispeed_fiber = false;
888 if (((comp_codes_1g & TXGBE_SFF_1GBASESX_CAPABLE) &&
889 (comp_codes_10g & TXGBE_SFF_10GBASESR_CAPABLE)) ||
890 ((comp_codes_1g & TXGBE_SFF_1GBASELX_CAPABLE) &&
891 (comp_codes_10g & TXGBE_SFF_10GBASELR_CAPABLE)))
892 hw->phy.multispeed_fiber = true;
894 /* Determine PHY vendor */
895 if (hw->phy.type != txgbe_phy_nl) {
896 hw->phy.id = identifier;
897 err = hw->phy.read_i2c_eeprom(hw,
898 TXGBE_SFF_VENDOR_OUI_BYTE0, &oui_bytes[0]);
902 err = hw->phy.read_i2c_eeprom(hw,
903 TXGBE_SFF_VENDOR_OUI_BYTE1, &oui_bytes[1]);
907 err = hw->phy.read_i2c_eeprom(hw,
908 TXGBE_SFF_VENDOR_OUI_BYTE2, &oui_bytes[2]);
912 vendor_oui = ((u32)oui_bytes[0] << 24) |
913 ((u32)oui_bytes[1] << 16) |
914 ((u32)oui_bytes[2] << 8);
915 switch (vendor_oui) {
916 case TXGBE_SFF_VENDOR_OUI_TYCO:
917 if (cable_tech & TXGBE_SFF_CABLE_DA_PASSIVE)
918 hw->phy.type = txgbe_phy_sfp_tyco_passive;
920 case TXGBE_SFF_VENDOR_OUI_FTL:
921 if (cable_tech & TXGBE_SFF_CABLE_DA_ACTIVE)
922 hw->phy.type = txgbe_phy_sfp_ftl_active;
924 hw->phy.type = txgbe_phy_sfp_ftl;
926 case TXGBE_SFF_VENDOR_OUI_AVAGO:
927 hw->phy.type = txgbe_phy_sfp_avago;
929 case TXGBE_SFF_VENDOR_OUI_INTEL:
930 hw->phy.type = txgbe_phy_sfp_intel;
933 if (cable_tech & TXGBE_SFF_CABLE_DA_PASSIVE)
934 hw->phy.type = txgbe_phy_sfp_unknown_passive;
935 else if (cable_tech & TXGBE_SFF_CABLE_DA_ACTIVE)
936 hw->phy.type = txgbe_phy_sfp_unknown_active;
938 hw->phy.type = txgbe_phy_sfp_unknown;
943 /* Allow any DA cable vendor */
944 if (cable_tech & (TXGBE_SFF_CABLE_DA_PASSIVE |
945 TXGBE_SFF_CABLE_DA_ACTIVE)) {
949 /* Verify supported 1G SFP modules */
950 if (comp_codes_10g == 0 &&
951 !(hw->phy.sfp_type == txgbe_sfp_type_1g_cu_core1 ||
952 hw->phy.sfp_type == txgbe_sfp_type_1g_cu_core0 ||
953 hw->phy.sfp_type == txgbe_sfp_type_1g_lx_core0 ||
954 hw->phy.sfp_type == txgbe_sfp_type_1g_lx_core1 ||
955 hw->phy.sfp_type == txgbe_sfp_type_1g_sx_core0 ||
956 hw->phy.sfp_type == txgbe_sfp_type_1g_sx_core1)) {
957 hw->phy.type = txgbe_phy_sfp_unsupported;
958 return TXGBE_ERR_SFP_NOT_SUPPORTED;
961 hw->mac.get_device_caps(hw, &enforce_sfp);
962 if (!(enforce_sfp & TXGBE_DEVICE_CAPS_ALLOW_ANY_SFP) &&
963 !hw->allow_unsupported_sfp &&
964 !(hw->phy.sfp_type == txgbe_sfp_type_1g_cu_core0 ||
965 hw->phy.sfp_type == txgbe_sfp_type_1g_cu_core1 ||
966 hw->phy.sfp_type == txgbe_sfp_type_1g_lx_core0 ||
967 hw->phy.sfp_type == txgbe_sfp_type_1g_lx_core1 ||
968 hw->phy.sfp_type == txgbe_sfp_type_1g_sx_core0 ||
969 hw->phy.sfp_type == txgbe_sfp_type_1g_sx_core1)) {
970 DEBUGOUT("SFP+ module not supported\n");
971 hw->phy.type = txgbe_phy_sfp_unsupported;
972 return TXGBE_ERR_SFP_NOT_SUPPORTED;
979 * txgbe_identify_qsfp_module - Identifies QSFP modules
980 * @hw: pointer to hardware structure
982 * Searches for and identifies the QSFP module and assigns appropriate PHY type
984 s32 txgbe_identify_qsfp_module(struct txgbe_hw *hw)
986 s32 err = TXGBE_ERR_PHY_ADDR_INVALID;
988 enum txgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
990 u8 comp_codes_1g = 0;
991 u8 comp_codes_10g = 0;
992 u8 oui_bytes[3] = {0, 0, 0};
997 bool active_cable = false;
999 DEBUGFUNC("txgbe_identify_qsfp_module");
1001 if (hw->phy.media_type != txgbe_media_type_fiber_qsfp) {
1002 hw->phy.sfp_type = txgbe_sfp_type_not_present;
1003 err = TXGBE_ERR_SFP_NOT_PRESENT;
1007 err = hw->phy.read_i2c_eeprom(hw, TXGBE_SFF_IDENTIFIER,
1011 hw->phy.sfp_type = txgbe_sfp_type_not_present;
1013 hw->phy.type = txgbe_phy_unknown;
1014 return TXGBE_ERR_SFP_NOT_PRESENT;
1016 if (identifier != TXGBE_SFF_IDENTIFIER_QSFP_PLUS) {
1017 hw->phy.type = txgbe_phy_sfp_unsupported;
1018 err = TXGBE_ERR_SFP_NOT_SUPPORTED;
1022 hw->phy.id = identifier;
1024 err = hw->phy.read_i2c_eeprom(hw, TXGBE_SFF_QSFP_10GBE_COMP,
1030 err = hw->phy.read_i2c_eeprom(hw, TXGBE_SFF_QSFP_1GBE_COMP,
1036 if (comp_codes_10g & TXGBE_SFF_QSFP_DA_PASSIVE_CABLE) {
1037 hw->phy.type = txgbe_phy_qsfp_unknown_passive;
1038 if (hw->bus.lan_id == 0)
1039 hw->phy.sfp_type = txgbe_sfp_type_da_cu_core0;
1041 hw->phy.sfp_type = txgbe_sfp_type_da_cu_core1;
1042 } else if (comp_codes_10g & (TXGBE_SFF_10GBASESR_CAPABLE |
1043 TXGBE_SFF_10GBASELR_CAPABLE)) {
1044 if (hw->bus.lan_id == 0)
1045 hw->phy.sfp_type = txgbe_sfp_type_srlr_core0;
1047 hw->phy.sfp_type = txgbe_sfp_type_srlr_core1;
1049 if (comp_codes_10g & TXGBE_SFF_QSFP_DA_ACTIVE_CABLE)
1050 active_cable = true;
1052 if (!active_cable) {
1053 hw->phy.read_i2c_eeprom(hw,
1054 TXGBE_SFF_QSFP_CONNECTOR,
1057 hw->phy.read_i2c_eeprom(hw,
1058 TXGBE_SFF_QSFP_CABLE_LENGTH,
1061 hw->phy.read_i2c_eeprom(hw,
1062 TXGBE_SFF_QSFP_DEVICE_TECH,
1066 TXGBE_SFF_QSFP_CONNECTOR_NOT_SEPARABLE &&
1068 ((device_tech >> 4) ==
1069 TXGBE_SFF_QSFP_TRANSMITTER_850NM_VCSEL))
1070 active_cable = true;
1074 hw->phy.type = txgbe_phy_qsfp_unknown_active;
1075 if (hw->bus.lan_id == 0)
1077 txgbe_sfp_type_da_act_lmt_core0;
1080 txgbe_sfp_type_da_act_lmt_core1;
1082 /* unsupported module type */
1083 hw->phy.type = txgbe_phy_sfp_unsupported;
1084 err = TXGBE_ERR_SFP_NOT_SUPPORTED;
1089 if (hw->phy.sfp_type != stored_sfp_type)
1090 hw->phy.sfp_setup_needed = true;
1092 /* Determine if the QSFP+ PHY is dual speed or not. */
1093 hw->phy.multispeed_fiber = false;
1094 if (((comp_codes_1g & TXGBE_SFF_1GBASESX_CAPABLE) &&
1095 (comp_codes_10g & TXGBE_SFF_10GBASESR_CAPABLE)) ||
1096 ((comp_codes_1g & TXGBE_SFF_1GBASELX_CAPABLE) &&
1097 (comp_codes_10g & TXGBE_SFF_10GBASELR_CAPABLE)))
1098 hw->phy.multispeed_fiber = true;
1100 /* Determine PHY vendor for optical modules */
1101 if (comp_codes_10g & (TXGBE_SFF_10GBASESR_CAPABLE |
1102 TXGBE_SFF_10GBASELR_CAPABLE)) {
1103 err = hw->phy.read_i2c_eeprom(hw,
1104 TXGBE_SFF_QSFP_VENDOR_OUI_BYTE0,
1110 err = hw->phy.read_i2c_eeprom(hw,
1111 TXGBE_SFF_QSFP_VENDOR_OUI_BYTE1,
1117 err = hw->phy.read_i2c_eeprom(hw,
1118 TXGBE_SFF_QSFP_VENDOR_OUI_BYTE2,
1125 ((oui_bytes[0] << 24) |
1126 (oui_bytes[1] << 16) |
1127 (oui_bytes[2] << 8));
1129 if (vendor_oui == TXGBE_SFF_VENDOR_OUI_INTEL)
1130 hw->phy.type = txgbe_phy_qsfp_intel;
1132 hw->phy.type = txgbe_phy_qsfp_unknown;
1134 hw->mac.get_device_caps(hw, &enforce_sfp);
1135 if (!(enforce_sfp & TXGBE_DEVICE_CAPS_ALLOW_ANY_SFP)) {
1136 /* Make sure we're a supported PHY type */
1137 if (hw->phy.type == txgbe_phy_qsfp_intel) {
1140 if (hw->allow_unsupported_sfp) {
1141 DEBUGOUT("WARNING: Wangxun (R) Network Connections are quality tested using Wangxun (R) Ethernet Optics. "
1142 "Using untested modules is not supported and may cause unstable operation or damage to the module or the adapter. "
1143 "Wangxun Corporation is not responsible for any harm caused by using untested modules.\n");
1146 DEBUGOUT("QSFP module not supported\n");
1148 txgbe_phy_sfp_unsupported;
1149 err = TXGBE_ERR_SFP_NOT_SUPPORTED;
1162 * txgbe_read_i2c_eeprom - Reads 8 bit EEPROM word over I2C interface
1163 * @hw: pointer to hardware structure
1164 * @byte_offset: EEPROM byte offset to read
1165 * @eeprom_data: value read
1167 * Performs byte read operation to SFP module's EEPROM over I2C interface.
1169 s32 txgbe_read_i2c_eeprom(struct txgbe_hw *hw, u8 byte_offset,
1172 DEBUGFUNC("txgbe_read_i2c_eeprom");
1174 return hw->phy.read_i2c_byte(hw, byte_offset,
1175 TXGBE_I2C_EEPROM_DEV_ADDR,
1180 * txgbe_write_i2c_eeprom - Writes 8 bit EEPROM word over I2C interface
1181 * @hw: pointer to hardware structure
1182 * @byte_offset: EEPROM byte offset to write
1183 * @eeprom_data: value to write
1185 * Performs byte write operation to SFP module's EEPROM over I2C interface.
1187 s32 txgbe_write_i2c_eeprom(struct txgbe_hw *hw, u8 byte_offset,
1190 DEBUGFUNC("txgbe_write_i2c_eeprom");
1192 return hw->phy.write_i2c_byte(hw, byte_offset,
1193 TXGBE_I2C_EEPROM_DEV_ADDR,
1198 * txgbe_read_i2c_byte_unlocked - Reads 8 bit word over I2C
1199 * @hw: pointer to hardware structure
1200 * @byte_offset: byte offset to read
1201 * @dev_addr: address to read from
1204 * Performs byte read operation to SFP module's EEPROM over I2C interface at
1205 * a specified device address.
1207 s32 txgbe_read_i2c_byte_unlocked(struct txgbe_hw *hw, u8 byte_offset,
1208 u8 dev_addr, u8 *data)
1210 UNREFERENCED_PARAMETER(dev_addr);
1212 DEBUGFUNC("txgbe_read_i2c_byte");
1214 txgbe_i2c_start(hw);
1217 if (!po32m(hw, TXGBE_I2CICR, TXGBE_I2CICR_TXEMPTY,
1218 TXGBE_I2CICR_TXEMPTY, NULL, 100, 100)) {
1219 return -TERR_TIMEOUT;
1223 wr32(hw, TXGBE_I2CDATA,
1224 byte_offset | TXGBE_I2CDATA_STOP);
1225 wr32(hw, TXGBE_I2CDATA, TXGBE_I2CDATA_READ);
1227 /* wait for read complete */
1228 if (!po32m(hw, TXGBE_I2CICR, TXGBE_I2CICR_RXFULL,
1229 TXGBE_I2CICR_RXFULL, NULL, 100, 100)) {
1230 return -TERR_TIMEOUT;
1235 *data = 0xFF & rd32(hw, TXGBE_I2CDATA);
1241 * txgbe_read_i2c_byte - Reads 8 bit word over I2C
1242 * @hw: pointer to hardware structure
1243 * @byte_offset: byte offset to read
1244 * @dev_addr: address to read from
1247 * Performs byte read operation to SFP module's EEPROM over I2C interface at
1248 * a specified device address.
1250 s32 txgbe_read_i2c_byte(struct txgbe_hw *hw, u8 byte_offset,
1251 u8 dev_addr, u8 *data)
1253 u32 swfw_mask = hw->phy.phy_semaphore_mask;
1256 if (hw->mac.acquire_swfw_sync(hw, swfw_mask))
1257 return TXGBE_ERR_SWFW_SYNC;
1258 err = txgbe_read_i2c_byte_unlocked(hw, byte_offset, dev_addr, data);
1259 hw->mac.release_swfw_sync(hw, swfw_mask);
1264 * txgbe_write_i2c_byte_unlocked - Writes 8 bit word over I2C
1265 * @hw: pointer to hardware structure
1266 * @byte_offset: byte offset to write
1267 * @dev_addr: address to write to
1268 * @data: value to write
1270 * Performs byte write operation to SFP module's EEPROM over I2C interface at
1271 * a specified device address.
1273 s32 txgbe_write_i2c_byte_unlocked(struct txgbe_hw *hw, u8 byte_offset,
1274 u8 dev_addr, u8 data)
1276 UNREFERENCED_PARAMETER(dev_addr);
1278 DEBUGFUNC("txgbe_write_i2c_byte");
1280 txgbe_i2c_start(hw);
1283 if (!po32m(hw, TXGBE_I2CICR, TXGBE_I2CICR_TXEMPTY,
1284 TXGBE_I2CICR_TXEMPTY, NULL, 100, 100)) {
1285 return -TERR_TIMEOUT;
1288 wr32(hw, TXGBE_I2CDATA, byte_offset | TXGBE_I2CDATA_STOP);
1289 wr32(hw, TXGBE_I2CDATA, data | TXGBE_I2CDATA_WRITE);
1291 /* wait for write complete */
1292 if (!po32m(hw, TXGBE_I2CICR, TXGBE_I2CICR_RXFULL,
1293 TXGBE_I2CICR_RXFULL, NULL, 100, 100)) {
1294 return -TERR_TIMEOUT;
1302 * txgbe_write_i2c_byte - Writes 8 bit word over I2C
1303 * @hw: pointer to hardware structure
1304 * @byte_offset: byte offset to write
1305 * @dev_addr: address to write to
1306 * @data: value to write
1308 * Performs byte write operation to SFP module's EEPROM over I2C interface at
1309 * a specified device address.
1311 s32 txgbe_write_i2c_byte(struct txgbe_hw *hw, u8 byte_offset,
1312 u8 dev_addr, u8 data)
1314 u32 swfw_mask = hw->phy.phy_semaphore_mask;
1317 if (hw->mac.acquire_swfw_sync(hw, swfw_mask))
1318 return TXGBE_ERR_SWFW_SYNC;
1319 err = txgbe_write_i2c_byte_unlocked(hw, byte_offset, dev_addr, data);
1320 hw->mac.release_swfw_sync(hw, swfw_mask);
1326 * txgbe_i2c_start - Sets I2C start condition
1327 * @hw: pointer to hardware structure
1329 * Sets I2C start condition (High -> Low on SDA while SCL is High)
1331 static void txgbe_i2c_start(struct txgbe_hw *hw)
1333 DEBUGFUNC("txgbe_i2c_start");
1335 wr32(hw, TXGBE_I2CENA, 0);
1337 wr32(hw, TXGBE_I2CCON,
1338 (TXGBE_I2CCON_MENA |
1339 TXGBE_I2CCON_SPEED(1) |
1340 TXGBE_I2CCON_RESTART |
1341 TXGBE_I2CCON_SDIA));
1342 wr32(hw, TXGBE_I2CTAR, TXGBE_I2C_SLAVEADDR);
1343 wr32(hw, TXGBE_I2CSSSCLHCNT, 600);
1344 wr32(hw, TXGBE_I2CSSSCLLCNT, 600);
1345 wr32(hw, TXGBE_I2CRXTL, 0); /* 1byte for rx full signal */
1346 wr32(hw, TXGBE_I2CTXTL, 4);
1347 wr32(hw, TXGBE_I2CSCLTMOUT, 0xFFFFFF);
1348 wr32(hw, TXGBE_I2CSDATMOUT, 0xFFFFFF);
1350 wr32(hw, TXGBE_I2CICM, 0);
1351 wr32(hw, TXGBE_I2CENA, 1);
1355 * txgbe_i2c_stop - Sets I2C stop condition
1356 * @hw: pointer to hardware structure
1358 * Sets I2C stop condition (Low -> High on SDA while SCL is High)
1360 static void txgbe_i2c_stop(struct txgbe_hw *hw)
1362 DEBUGFUNC("txgbe_i2c_stop");
1364 /* wait for completion */
1365 if (!po32m(hw, TXGBE_I2CSTAT, TXGBE_I2CSTAT_MST,
1366 0, NULL, 100, 100)) {
1367 DEBUGFUNC("i2c stop timeout.");
1370 wr32(hw, TXGBE_I2CENA, 0);
1374 txgbe_set_sgmii_an37_ability(struct txgbe_hw *hw)
1378 wr32_epcs(hw, VR_XS_OR_PCS_MMD_DIGI_CTL1, 0x3002);
1379 wr32_epcs(hw, SR_MII_MMD_AN_CTL, 0x0105);
1380 wr32_epcs(hw, SR_MII_MMD_DIGI_CTL, 0x0200);
1381 value = rd32_epcs(hw, SR_MII_MMD_CTL);
1382 value = (value & ~0x1200) | (0x1 << 12) | (0x1 << 9);
1383 wr32_epcs(hw, SR_MII_MMD_CTL, value);
1388 txgbe_set_link_to_kr(struct txgbe_hw *hw, bool autoneg)
1393 /* 1. Wait xpcs power-up good */
1394 for (i = 0; i < 100; i++) {
1395 if ((rd32_epcs(hw, VR_XS_OR_PCS_MMD_DIGI_STATUS) &
1396 VR_XS_OR_PCS_MMD_DIGI_STATUS_PSEQ_MASK) ==
1397 VR_XS_OR_PCS_MMD_DIGI_STATUS_PSEQ_POWER_GOOD)
1402 err = TXGBE_ERR_XPCS_POWER_UP_FAILED;
1407 /* 2. Disable xpcs AN-73 */
1408 wr32_epcs(hw, SR_AN_CTRL, 0x0);
1409 /* Disable PHY MPLLA for eth mode change(after ECO) */
1410 wr32_ephy(hw, 0x4, 0x243A);
1413 /* Set the eth change_mode bit first in mis_rst register
1414 * for corresponding LAN port
1416 wr32(hw, TXGBE_RST, TXGBE_RST_ETH(hw->bus.lan_id));
1418 /* 3. Set VR_XS_PMA_Gen5_12G_MPLLA_CTRL3 Register
1419 * Bit[10:0](MPLLA_BANDWIDTH) = 11'd123 (default: 11'd16)
1421 wr32_epcs(hw, TXGBE_PHY_MPLLA_CTL3,
1422 TXGBE_PHY_MPLLA_CTL3_MULTIPLIER_BW_10GBASER_KR);
1424 /* 4. Set VR_XS_PMA_Gen5_12G_MISC_CTRL0 Register
1425 * Bit[12:8](RX_VREF_CTRL) = 5'hF (default: 5'h11)
1427 wr32_epcs(hw, TXGBE_PHY_MISC_CTL0, 0xCF00);
1429 /* 5. Set VR_XS_PMA_Gen5_12G_RX_EQ_CTRL0 Register
1430 * Bit[15:8](VGA1/2_GAIN_0) = 8'h77
1431 * Bit[7:5](CTLE_POLE_0) = 3'h2
1432 * Bit[4:0](CTLE_BOOST_0) = 4'hA
1434 wr32_epcs(hw, TXGBE_PHY_RX_EQ_CTL0, 0x774A);
1436 /* 6. Set VR_MII_Gen5_12G_RX_GENCTRL3 Register
1437 * Bit[2:0](LOS_TRSHLD_0) = 3'h4 (default: 3)
1439 wr32_epcs(hw, TXGBE_PHY_RX_GEN_CTL3, 0x0004);
1441 /* 7. Initialize the mode by setting VR XS or PCS MMD Digital
1442 * Control1 Register Bit[15](VR_RST)
1444 wr32_epcs(hw, VR_XS_OR_PCS_MMD_DIGI_CTL1, 0xA000);
1446 /* Wait phy initialization done */
1447 for (i = 0; i < 100; i++) {
1449 VR_XS_OR_PCS_MMD_DIGI_CTL1) &
1450 VR_XS_OR_PCS_MMD_DIGI_CTL1_VR_RST) == 0)
1455 err = TXGBE_ERR_PHY_INIT_NOT_DONE;
1459 wr32_epcs(hw, VR_AN_KR_MODE_CL, 0x1);
1466 txgbe_set_link_to_kx4(struct txgbe_hw *hw, bool autoneg)
1472 /* Check link status, if already set, skip setting it again */
1473 if (hw->link_status == TXGBE_LINK_STATUS_KX4)
1476 /* 1. Wait xpcs power-up good */
1477 for (i = 0; i < 100; i++) {
1478 if ((rd32_epcs(hw, VR_XS_OR_PCS_MMD_DIGI_STATUS) &
1479 VR_XS_OR_PCS_MMD_DIGI_STATUS_PSEQ_MASK) ==
1480 VR_XS_OR_PCS_MMD_DIGI_STATUS_PSEQ_POWER_GOOD)
1485 err = TXGBE_ERR_XPCS_POWER_UP_FAILED;
1489 wr32m(hw, TXGBE_MACTXCFG, TXGBE_MACTXCFG_TXE,
1490 ~TXGBE_MACTXCFG_TXE);
1492 /* 2. Disable xpcs AN-73 */
1494 wr32_epcs(hw, SR_AN_CTRL, 0x0);
1496 wr32_epcs(hw, SR_AN_CTRL, 0x3000);
1498 /* Disable PHY MPLLA for eth mode change(after ECO) */
1499 wr32_ephy(hw, 0x4, 0x250A);
1503 /* Set the eth change_mode bit first in mis_rst register
1504 * for corresponding LAN port
1506 wr32(hw, TXGBE_RST, TXGBE_RST_ETH(hw->bus.lan_id));
1508 /* Set SR PCS Control2 Register Bits[1:0] = 2'b01
1509 * PCS_TYPE_SEL: non KR
1511 wr32_epcs(hw, SR_XS_PCS_CTRL2,
1512 SR_PCS_CTRL2_TYPE_SEL_X);
1514 /* Set SR PMA MMD Control1 Register Bit[13] = 1'b1
1517 wr32_epcs(hw, SR_PMA_CTRL1,
1518 SR_PMA_CTRL1_SS13_KX4);
1520 value = (0xf5f0 & ~0x7F0) | (0x5 << 8) | (0x7 << 5) | 0x10;
1521 wr32_epcs(hw, TXGBE_PHY_TX_GENCTRL1, value);
1523 wr32_epcs(hw, TXGBE_PHY_MISC_CTL0, 0x4F00);
1525 value = (0x1804 & ~0x3F3F);
1526 wr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL0, value);
1528 value = (0x50 & ~0x7F) | 40 | (1 << 6);
1529 wr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL1, value);
1531 for (i = 0; i < 4; i++) {
1533 value = (0x45 & ~0xFFFF) | (0x7 << 12) |
1536 value = (0xff06 & ~0xFFFF) | (0x7 << 12) |
1538 wr32_epcs(hw, TXGBE_PHY_RX_EQ_CTL0 + i, value);
1541 value = 0x0 & ~0x7777;
1542 wr32_epcs(hw, TXGBE_PHY_RX_EQ_ATT_LVL0, value);
1544 wr32_epcs(hw, TXGBE_PHY_DFE_TAP_CTL0, 0x0);
1546 value = (0x6db & ~0xFFF) | (0x1 << 9) | (0x1 << 6) | (0x1 << 3) | 0x1;
1547 wr32_epcs(hw, TXGBE_PHY_RX_GEN_CTL3, value);
1549 /* Set VR XS, PMA, or MII Gen5 12G PHY MPLLA
1550 * Control 0 Register Bit[7:0] = 8'd40 //MPLLA_MULTIPLIER
1552 wr32_epcs(hw, TXGBE_PHY_MPLLA_CTL0,
1553 TXGBE_PHY_MPLLA_CTL0_MULTIPLIER_OTHER);
1555 /* Set VR XS, PMA or MII Gen5 12G PHY MPLLA
1556 * Control 3 Register Bit[10:0] = 11'd86 //MPLLA_BANDWIDTH
1558 wr32_epcs(hw, TXGBE_PHY_MPLLA_CTL3,
1559 TXGBE_PHY_MPLLA_CTL3_MULTIPLIER_BW_OTHER);
1561 /* Set VR XS, PMA, or MII Gen5 12G PHY VCO
1562 * Calibration Load 0 Register Bit[12:0] = 13'd1360 //VCO_LD_VAL_0
1564 wr32_epcs(hw, TXGBE_PHY_VCO_CAL_LD0,
1565 TXGBE_PHY_VCO_CAL_LD0_OTHER);
1567 /* Set VR XS, PMA, or MII Gen5 12G PHY VCO
1568 * Calibration Load 1 Register Bit[12:0] = 13'd1360 //VCO_LD_VAL_1
1570 wr32_epcs(hw, TXGBE_PHY_VCO_CAL_LD1,
1571 TXGBE_PHY_VCO_CAL_LD0_OTHER);
1573 /* Set VR XS, PMA, or MII Gen5 12G PHY VCO
1574 * Calibration Load 2 Register Bit[12:0] = 13'd1360 //VCO_LD_VAL_2
1576 wr32_epcs(hw, TXGBE_PHY_VCO_CAL_LD2,
1577 TXGBE_PHY_VCO_CAL_LD0_OTHER);
1578 /* Set VR XS, PMA, or MII Gen5 12G PHY VCO
1579 * Calibration Load 3 Register Bit[12:0] = 13'd1360 //VCO_LD_VAL_3
1581 wr32_epcs(hw, TXGBE_PHY_VCO_CAL_LD3,
1582 TXGBE_PHY_VCO_CAL_LD0_OTHER);
1583 /* Set VR XS, PMA, or MII Gen5 12G PHY VCO
1584 * Calibration Reference 0 Register Bit[5:0] = 6'd34 //VCO_REF_LD_0/1
1586 wr32_epcs(hw, TXGBE_PHY_VCO_CAL_REF0, 0x2222);
1588 /* Set VR XS, PMA, or MII Gen5 12G PHY VCO
1589 * Calibration Reference 1 Register Bit[5:0] = 6'd34 //VCO_REF_LD_2/3
1591 wr32_epcs(hw, TXGBE_PHY_VCO_CAL_REF1, 0x2222);
1593 /* Set VR XS, PMA, or MII Gen5 12G PHY AFE-DFE
1594 * Enable Register Bit[7:0] = 8'd0 //AFE_EN_0/3_1, DFE_EN_0/3_1
1596 wr32_epcs(hw, TXGBE_PHY_AFE_DFE_ENABLE, 0x0);
1598 /* Set VR XS, PMA, or MII Gen5 12G PHY Rx
1599 * Equalization Control 4 Register Bit[3:0] = 4'd0 //CONT_ADAPT_0/3_1
1601 wr32_epcs(hw, TXGBE_PHY_RX_EQ_CTL, 0x00F0);
1603 /* Set VR XS, PMA, or MII Gen5 12G PHY Tx Rate
1604 * Control Register Bit[14:12], Bit[10:8], Bit[6:4], Bit[2:0],
1605 * all rates to 3'b010 //TX0/1/2/3_RATE
1607 wr32_epcs(hw, TXGBE_PHY_TX_RATE_CTL, 0x2222);
1609 /* Set VR XS, PMA, or MII Gen5 12G PHY Rx Rate
1610 * Control Register Bit[13:12], Bit[9:8], Bit[5:4], Bit[1:0],
1611 * all rates to 2'b10 //RX0/1/2/3_RATE
1613 wr32_epcs(hw, TXGBE_PHY_RX_RATE_CTL, 0x2222);
1615 /* Set VR XS, PMA, or MII Gen5 12G PHY Tx General
1616 * Control 2 Register Bit[15:8] = 2'b01 //TX0/1/2/3_WIDTH: 10bits
1618 wr32_epcs(hw, TXGBE_PHY_TX_GEN_CTL2, 0x5500);
1620 /* Set VR XS, PMA, or MII Gen5 12G PHY Rx General
1621 * Control 2 Register Bit[15:8] = 2'b01 //RX0/1/2/3_WIDTH: 10bits
1623 wr32_epcs(hw, TXGBE_PHY_RX_GEN_CTL2, 0x5500);
1625 /* Set VR XS, PMA, or MII Gen5 12G PHY MPLLA Control
1626 * 2 Register Bit[10:8] = 3'b010
1627 * MPLLA_DIV16P5_CLK_EN=0, MPLLA_DIV10_CLK_EN=1, MPLLA_DIV8_CLK_EN=0
1629 wr32_epcs(hw, TXGBE_PHY_MPLLA_CTL2,
1630 TXGBE_PHY_MPLLA_CTL2_DIV_CLK_EN_10);
1632 wr32_epcs(hw, 0x1f0000, 0x0);
1633 wr32_epcs(hw, 0x1f8001, 0x0);
1634 wr32_epcs(hw, SR_MII_MMD_DIGI_CTL, 0x0);
1636 /* 10. Initialize the mode by setting VR XS or PCS MMD Digital Control1
1637 * Register Bit[15](VR_RST)
1639 wr32_epcs(hw, VR_XS_OR_PCS_MMD_DIGI_CTL1, 0xA000);
1641 /* Wait phy initialization done */
1642 for (i = 0; i < 100; i++) {
1643 if ((rd32_epcs(hw, VR_XS_OR_PCS_MMD_DIGI_CTL1) &
1644 VR_XS_OR_PCS_MMD_DIGI_CTL1_VR_RST) == 0)
1649 /* If success, set link status */
1650 hw->link_status = TXGBE_LINK_STATUS_KX4;
1653 err = TXGBE_ERR_PHY_INIT_NOT_DONE;
1662 txgbe_set_link_to_kx(struct txgbe_hw *hw,
1671 /* Check link status, if already set, skip setting it again */
1672 if (hw->link_status == TXGBE_LINK_STATUS_KX)
1675 /* 1. Wait xpcs power-up good */
1676 for (i = 0; i < 100; i++) {
1677 if ((rd32_epcs(hw, VR_XS_OR_PCS_MMD_DIGI_STATUS) &
1678 VR_XS_OR_PCS_MMD_DIGI_STATUS_PSEQ_MASK) ==
1679 VR_XS_OR_PCS_MMD_DIGI_STATUS_PSEQ_POWER_GOOD)
1684 err = TXGBE_ERR_XPCS_POWER_UP_FAILED;
1688 wr32m(hw, TXGBE_MACTXCFG, TXGBE_MACTXCFG_TXE,
1689 ~TXGBE_MACTXCFG_TXE);
1691 /* 2. Disable xpcs AN-73 */
1693 wr32_epcs(hw, SR_AN_CTRL, 0x0);
1695 wr32_epcs(hw, SR_AN_CTRL, 0x3000);
1697 /* Disable PHY MPLLA for eth mode change(after ECO) */
1698 wr32_ephy(hw, 0x4, 0x240A);
1702 /* Set the eth change_mode bit first in mis_rst register
1703 * for corresponding LAN port
1705 wr32(hw, TXGBE_RST, TXGBE_RST_ETH(hw->bus.lan_id));
1707 /* Set SR PCS Control2 Register Bits[1:0] = 2'b01
1708 * PCS_TYPE_SEL: non KR
1710 wr32_epcs(hw, SR_XS_PCS_CTRL2,
1711 SR_PCS_CTRL2_TYPE_SEL_X);
1713 /* Set SR PMA MMD Control1 Register Bit[13] = 1'b0
1716 wr32_epcs(hw, SR_PMA_CTRL1,
1717 SR_PMA_CTRL1_SS13_KX);
1719 /* Set SR MII MMD Control Register to corresponding speed: {Bit[6],
1720 * Bit[13]}=[2'b00,2'b01,2'b10]->[10M,100M,1G]
1722 if (speed == TXGBE_LINK_SPEED_100M_FULL)
1724 else if (speed == TXGBE_LINK_SPEED_1GB_FULL)
1726 else if (speed == TXGBE_LINK_SPEED_10M_FULL)
1728 wr32_epcs(hw, SR_MII_MMD_CTL,
1731 value = (0xf5f0 & ~0x710) | (0x5 << 8);
1732 wr32_epcs(hw, TXGBE_PHY_TX_GENCTRL1, value);
1734 wr32_epcs(hw, TXGBE_PHY_MISC_CTL0, 0x4F00);
1736 value = (0x1804 & ~0x3F3F) | (24 << 8) | 4;
1737 wr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL0, value);
1739 value = (0x50 & ~0x7F) | 16 | (1 << 6);
1740 wr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL1, value);
1742 for (i = 0; i < 4; i++) {
1746 value = (0x45 & ~0xFFFF) | (0x7 << 12) |
1749 wr32_epcs(hw, TXGBE_PHY_RX_EQ_CTL0 + i, value);
1753 wr32_epcs(hw, TXGBE_PHY_RX_EQ_ATT_LVL0, value);
1755 wr32_epcs(hw, TXGBE_PHY_DFE_TAP_CTL0, 0x0);
1757 value = (0x6db & ~0x7) | 0x4;
1758 wr32_epcs(hw, TXGBE_PHY_RX_GEN_CTL3, value);
1760 /* Set VR XS, PMA, or MII Gen5 12G PHY MPLLA Control
1761 * 0 Register Bit[7:0] = 8'd32 //MPLLA_MULTIPLIER
1763 wr32_epcs(hw, TXGBE_PHY_MPLLA_CTL0,
1764 TXGBE_PHY_MPLLA_CTL0_MULTIPLIER_1GBASEX_KX);
1766 /* Set VR XS, PMA or MII Gen5 12G PHY MPLLA Control
1767 * 3 Register Bit[10:0] = 11'd70 //MPLLA_BANDWIDTH
1769 wr32_epcs(hw, TXGBE_PHY_MPLLA_CTL3,
1770 TXGBE_PHY_MPLLA_CTL3_MULTIPLIER_BW_1GBASEX_KX);
1772 /* Set VR XS, PMA, or MII Gen5 12G PHY VCO
1773 * Calibration Load 0 Register Bit[12:0] = 13'd1344 //VCO_LD_VAL_0
1775 wr32_epcs(hw, TXGBE_PHY_VCO_CAL_LD0,
1776 TXGBE_PHY_VCO_CAL_LD0_1GBASEX_KX);
1778 wr32_epcs(hw, TXGBE_PHY_VCO_CAL_LD1, 0x549);
1779 wr32_epcs(hw, TXGBE_PHY_VCO_CAL_LD2, 0x549);
1780 wr32_epcs(hw, TXGBE_PHY_VCO_CAL_LD3, 0x549);
1782 /* Set VR XS, PMA, or MII Gen5 12G PHY VCO
1783 * Calibration Reference 0 Register Bit[5:0] = 6'd42 //VCO_REF_LD_0
1785 wr32_epcs(hw, TXGBE_PHY_VCO_CAL_REF0,
1786 TXGBE_PHY_VCO_CAL_REF0_LD0_1GBASEX_KX);
1788 wr32_epcs(hw, TXGBE_PHY_VCO_CAL_REF1, 0x2929);
1790 /* Set VR XS, PMA, or MII Gen5 12G PHY AFE-DFE
1791 * Enable Register Bit[4], Bit[0] = 1'b0 //AFE_EN_0, DFE_EN_0
1793 wr32_epcs(hw, TXGBE_PHY_AFE_DFE_ENABLE,
1795 /* Set VR XS, PMA, or MII Gen5 12G PHY Rx
1796 * Equalization Control 4 Register Bit[0] = 1'b0 //CONT_ADAPT_0
1798 wr32_epcs(hw, TXGBE_PHY_RX_EQ_CTL,
1800 /* Set VR XS, PMA, or MII Gen5 12G PHY Tx Rate
1801 * Control Register Bit[2:0] = 3'b011 //TX0_RATE
1803 wr32_epcs(hw, TXGBE_PHY_TX_RATE_CTL,
1804 TXGBE_PHY_TX_RATE_CTL_TX0_RATE_1GBASEX_KX);
1806 /* Set VR XS, PMA, or MII Gen5 12G PHY Rx Rate
1807 * Control Register Bit[2:0] = 3'b011 //RX0_RATE
1809 wr32_epcs(hw, TXGBE_PHY_RX_RATE_CTL,
1810 TXGBE_PHY_RX_RATE_CTL_RX0_RATE_1GBASEX_KX);
1812 /* Set VR XS, PMA, or MII Gen5 12G PHY Tx General
1813 * Control 2 Register Bit[9:8] = 2'b01 //TX0_WIDTH: 10bits
1815 wr32_epcs(hw, TXGBE_PHY_TX_GEN_CTL2,
1816 TXGBE_PHY_TX_GEN_CTL2_TX0_WIDTH_OTHER);
1817 /* Set VR XS, PMA, or MII Gen5 12G PHY Rx General
1818 * Control 2 Register Bit[9:8] = 2'b01 //RX0_WIDTH: 10bits
1820 wr32_epcs(hw, TXGBE_PHY_RX_GEN_CTL2,
1821 TXGBE_PHY_RX_GEN_CTL2_RX0_WIDTH_OTHER);
1822 /* Set VR XS, PMA, or MII Gen5 12G PHY MPLLA Control
1823 * 2 Register Bit[10:8] = 3'b010 //MPLLA_DIV16P5_CLK_EN=0,
1824 * MPLLA_DIV10_CLK_EN=1, MPLLA_DIV8_CLK_EN=0
1826 wr32_epcs(hw, TXGBE_PHY_MPLLA_CTL2,
1827 TXGBE_PHY_MPLLA_CTL2_DIV_CLK_EN_10);
1829 /* VR MII MMD AN Control Register Bit[8] = 1'b1 //MII_CTRL
1830 * Set to 8bit MII (required in 10M/100M SGMII)
1832 wr32_epcs(hw, SR_MII_MMD_AN_CTL,
1835 /* 10. Initialize the mode by setting VR XS or PCS MMD Digital Control1
1836 * Register Bit[15](VR_RST)
1838 wr32_epcs(hw, VR_XS_OR_PCS_MMD_DIGI_CTL1, 0xA000);
1840 /* Wait phy initialization done */
1841 for (i = 0; i < 100; i++) {
1842 if ((rd32_epcs(hw, VR_XS_OR_PCS_MMD_DIGI_CTL1) &
1843 VR_XS_OR_PCS_MMD_DIGI_CTL1_VR_RST) == 0)
1848 /* If success, set link status */
1849 hw->link_status = TXGBE_LINK_STATUS_KX;
1852 err = TXGBE_ERR_PHY_INIT_NOT_DONE;
1861 txgbe_set_link_to_sfi(struct txgbe_hw *hw,
1868 /* Set the module link speed */
1869 hw->mac.set_rate_select_speed(hw, speed);
1870 /* 1. Wait xpcs power-up good */
1871 for (i = 0; i < 100; i++) {
1872 if ((rd32_epcs(hw, VR_XS_OR_PCS_MMD_DIGI_STATUS) &
1873 VR_XS_OR_PCS_MMD_DIGI_STATUS_PSEQ_MASK) ==
1874 VR_XS_OR_PCS_MMD_DIGI_STATUS_PSEQ_POWER_GOOD)
1879 err = TXGBE_ERR_XPCS_POWER_UP_FAILED;
1883 wr32m(hw, TXGBE_MACTXCFG, TXGBE_MACTXCFG_TXE,
1884 ~TXGBE_MACTXCFG_TXE);
1886 /* 2. Disable xpcs AN-73 */
1887 wr32_epcs(hw, SR_AN_CTRL, 0x0);
1889 /* Disable PHY MPLLA for eth mode change(after ECO) */
1890 wr32_ephy(hw, 0x4, 0x243A);
1893 /* Set the eth change_mode bit first in mis_rst register
1894 * for corresponding LAN port
1896 wr32(hw, TXGBE_RST, TXGBE_RST_ETH(hw->bus.lan_id));
1898 if (speed == TXGBE_LINK_SPEED_10GB_FULL) {
1899 /* Set SR PCS Control2 Register Bits[1:0] = 2'b00
1902 wr32_epcs(hw, SR_XS_PCS_CTRL2, 0);
1903 value = rd32_epcs(hw, SR_PMA_CTRL1);
1904 value = value | 0x2000;
1905 wr32_epcs(hw, SR_PMA_CTRL1, value);
1906 /* Set VR_XS_PMA_Gen5_12G_MPLLA_CTRL0 Register Bit[7:0] = 8'd33
1909 wr32_epcs(hw, TXGBE_PHY_MPLLA_CTL0, 0x0021);
1910 /* 3. Set VR_XS_PMA_Gen5_12G_MPLLA_CTRL3 Register
1911 * Bit[10:0](MPLLA_BANDWIDTH) = 11'd0
1913 wr32_epcs(hw, TXGBE_PHY_MPLLA_CTL3, 0);
1914 value = rd32_epcs(hw, TXGBE_PHY_TX_GENCTRL1);
1915 value = (value & ~0x700) | 0x500;
1916 wr32_epcs(hw, TXGBE_PHY_TX_GENCTRL1, value);
1917 /* 4. Set VR_XS_PMA_Gen5_12G_MISC_CTRL0 Register
1918 * Bit[12:8](RX_VREF_CTRL) = 5'hF
1920 wr32_epcs(hw, TXGBE_PHY_MISC_CTL0, 0xCF00);
1921 /* Set VR_XS_PMA_Gen5_12G_VCO_CAL_LD0 Register
1922 * Bit[12:0] = 13'd1353 //VCO_LD_VAL_0
1924 wr32_epcs(hw, TXGBE_PHY_VCO_CAL_LD0, 0x0549);
1925 /* Set VR_XS_PMA_Gen5_12G_VCO_CAL_REF0 Register
1926 * Bit[5:0] = 6'd41 //VCO_REF_LD_0
1928 wr32_epcs(hw, TXGBE_PHY_VCO_CAL_REF0, 0x0029);
1929 /* Set VR_XS_PMA_Gen5_12G_TX_RATE_CTRL Register
1930 * Bit[2:0] = 3'b000 //TX0_RATE
1932 wr32_epcs(hw, TXGBE_PHY_TX_RATE_CTL, 0);
1933 /* Set VR_XS_PMA_Gen5_12G_RX_RATE_CTRL Register
1934 * Bit[2:0] = 3'b000 //RX0_RATE
1936 wr32_epcs(hw, TXGBE_PHY_RX_RATE_CTL, 0);
1937 /* Set VR_XS_PMA_Gen5_12G_TX_GENCTRL2 Register Bit[9:8] = 2'b11
1940 wr32_epcs(hw, TXGBE_PHY_TX_GEN_CTL2, 0x0300);
1941 /* Set VR_XS_PMA_Gen5_12G_RX_GENCTRL2 Register Bit[9:8] = 2'b11
1944 wr32_epcs(hw, TXGBE_PHY_RX_GEN_CTL2, 0x0300);
1945 /* Set VR_XS_PMA_Gen5_12G_MPLLA_CTRL2 Register
1946 * Bit[10:8] = 3'b110
1947 * MPLLA_DIV16P5_CLK_EN=1
1948 * MPLLA_DIV10_CLK_EN=1
1949 * MPLLA_DIV8_CLK_EN=0
1951 wr32_epcs(hw, TXGBE_PHY_MPLLA_CTL2, 0x0600);
1952 /* 5. Set VR_XS_PMA_Gen5_12G_TX_EQ_CTRL0 Register
1953 * Bit[13:8](TX_EQ_MAIN) = 6'd30, Bit[5:0](TX_EQ_PRE) = 6'd4
1955 value = rd32_epcs(hw, TXGBE_PHY_TX_EQ_CTL0);
1956 value = (value & ~0x3F3F) | (24 << 8) | 4;
1957 wr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL0, value);
1958 /* 6. Set VR_XS_PMA_Gen5_12G_TX_EQ_CTRL1 Register
1959 * Bit[6](TX_EQ_OVR_RIDE) = 1'b1, Bit[5:0](TX_EQ_POST) = 6'd36
1961 value = rd32_epcs(hw, TXGBE_PHY_TX_EQ_CTL1);
1962 value = (value & ~0x7F) | 16 | (1 << 6);
1963 wr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL1, value);
1964 if (hw->phy.sfp_type == txgbe_sfp_type_da_cu_core0 ||
1965 hw->phy.sfp_type == txgbe_sfp_type_da_cu_core1) {
1966 /* 7. Set VR_XS_PMA_Gen5_12G_RX_EQ_CTRL0 Register
1967 * Bit[15:8](VGA1/2_GAIN_0) = 8'h77
1968 * Bit[7:5](CTLE_POLE_0) = 3'h2
1969 * Bit[4:0](CTLE_BOOST_0) = 4'hF
1971 wr32_epcs(hw, TXGBE_PHY_RX_EQ_CTL0, 0x774F);
1974 /* 7. Set VR_XS_PMA_Gen5_12G_RX_EQ_CTRL0 Register
1975 * Bit[15:8](VGA1/2_GAIN_0) = 8'h00
1976 * Bit[7:5](CTLE_POLE_0) = 3'h2
1977 * Bit[4:0](CTLE_BOOST_0) = 4'hA
1979 value = rd32_epcs(hw, TXGBE_PHY_RX_EQ_CTL0);
1980 value = (value & ~0xFFFF) | (2 << 5) | 0x05;
1981 wr32_epcs(hw, TXGBE_PHY_RX_EQ_CTL0, value);
1983 value = rd32_epcs(hw, TXGBE_PHY_RX_EQ_ATT_LVL0);
1984 value = (value & ~0x7) | 0x0;
1985 wr32_epcs(hw, TXGBE_PHY_RX_EQ_ATT_LVL0, value);
1987 if (hw->phy.sfp_type == txgbe_sfp_type_da_cu_core0 ||
1988 hw->phy.sfp_type == txgbe_sfp_type_da_cu_core1) {
1989 /* 8. Set VR_XS_PMA_Gen5_12G_DFE_TAP_CTRL0 Register
1990 * Bit[7:0](DFE_TAP1_0) = 8'd20
1992 wr32_epcs(hw, TXGBE_PHY_DFE_TAP_CTL0, 0x0014);
1993 value = rd32_epcs(hw, TXGBE_PHY_AFE_DFE_ENABLE);
1994 value = (value & ~0x11) | 0x11;
1995 wr32_epcs(hw, TXGBE_PHY_AFE_DFE_ENABLE, value);
1997 /* 8. Set VR_XS_PMA_Gen5_12G_DFE_TAP_CTRL0 Register
1998 * Bit[7:0](DFE_TAP1_0) = 8'd20
2000 wr32_epcs(hw, TXGBE_PHY_DFE_TAP_CTL0, 0xBE);
2001 /* 9. Set VR_MII_Gen5_12G_AFE_DFE_EN_CTRL Register
2002 * Bit[4](DFE_EN_0) = 1'b0, Bit[0](AFE_EN_0) = 1'b0
2004 value = rd32_epcs(hw, TXGBE_PHY_AFE_DFE_ENABLE);
2005 value = (value & ~0x11) | 0x0;
2006 wr32_epcs(hw, TXGBE_PHY_AFE_DFE_ENABLE, value);
2008 value = rd32_epcs(hw, TXGBE_PHY_RX_EQ_CTL);
2009 value = value & ~0x1;
2010 wr32_epcs(hw, TXGBE_PHY_RX_EQ_CTL, value);
2012 /* Set SR PCS Control2 Register Bits[1:0] = 2'b00
2015 wr32_epcs(hw, SR_XS_PCS_CTRL2, 0x1);
2016 /* Set SR PMA MMD Control1 Register Bit[13] = 1'b0
2019 wr32_epcs(hw, SR_PMA_CTRL1, 0x0000);
2020 /* Set SR MII MMD Control Register to corresponding speed */
2021 wr32_epcs(hw, SR_MII_MMD_CTL, 0x0140);
2023 value = rd32_epcs(hw, TXGBE_PHY_TX_GENCTRL1);
2024 value = (value & ~0x710) | 0x500;
2025 wr32_epcs(hw, TXGBE_PHY_TX_GENCTRL1, value);
2026 /* 4. Set VR_XS_PMA_Gen5_12G_MISC_CTRL0 Register
2027 * Bit[12:8](RX_VREF_CTRL) = 5'hF
2029 wr32_epcs(hw, TXGBE_PHY_MISC_CTL0, 0xCF00);
2030 /* 5. Set VR_XS_PMA_Gen5_12G_TX_EQ_CTRL0 Register
2031 * Bit[13:8](TX_EQ_MAIN) = 6'd30, Bit[5:0](TX_EQ_PRE) = 6'd4
2033 value = rd32_epcs(hw, TXGBE_PHY_TX_EQ_CTL0);
2034 value = (value & ~0x3F3F) | (24 << 8) | 4;
2035 wr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL0, value);
2036 /* 6. Set VR_XS_PMA_Gen5_12G_TX_EQ_CTRL1 Register Bit[6]
2037 * (TX_EQ_OVR_RIDE) = 1'b1, Bit[5:0](TX_EQ_POST) = 6'd36
2039 value = rd32_epcs(hw, TXGBE_PHY_TX_EQ_CTL1);
2040 value = (value & ~0x7F) | 16 | (1 << 6);
2041 wr32_epcs(hw, TXGBE_PHY_TX_EQ_CTL1, value);
2042 if (hw->phy.sfp_type == txgbe_sfp_type_da_cu_core0 ||
2043 hw->phy.sfp_type == txgbe_sfp_type_da_cu_core1) {
2044 wr32_epcs(hw, TXGBE_PHY_RX_EQ_CTL0, 0x774F);
2046 /* 7. Set VR_XS_PMA_Gen5_12G_RX_EQ_CTRL0 Register
2047 * Bit[15:8](VGA1/2_GAIN_0) = 8'h00
2048 * Bit[7:5](CTLE_POLE_0) = 3'h2
2049 * Bit[4:0](CTLE_BOOST_0) = 4'hA
2051 value = rd32_epcs(hw, TXGBE_PHY_RX_EQ_CTL0);
2052 value = (value & ~0xFFFF) | 0x7706;
2053 wr32_epcs(hw, TXGBE_PHY_RX_EQ_CTL0, value);
2055 value = rd32_epcs(hw, TXGBE_PHY_RX_EQ_ATT_LVL0);
2056 value = (value & ~0x7) | 0x0;
2057 wr32_epcs(hw, TXGBE_PHY_RX_EQ_ATT_LVL0, value);
2058 /* 8. Set VR_XS_PMA_Gen5_12G_DFE_TAP_CTRL0 Register
2059 * Bit[7:0](DFE_TAP1_0) = 8'd00
2061 wr32_epcs(hw, TXGBE_PHY_DFE_TAP_CTL0, 0x0);
2062 /* 9. Set VR_MII_Gen5_12G_AFE_DFE_EN_CTRL Register
2063 * Bit[4](DFE_EN_0) = 1'b0, Bit[0](AFE_EN_0) = 1'b0
2065 value = rd32_epcs(hw, TXGBE_PHY_RX_GEN_CTL3);
2066 value = (value & ~0x7) | 0x4;
2067 wr32_epcs(hw, TXGBE_PHY_RX_GEN_CTL3, value);
2068 wr32_epcs(hw, TXGBE_PHY_MPLLA_CTL0, 0x0020);
2069 wr32_epcs(hw, TXGBE_PHY_MPLLA_CTL3, 0x0046);
2070 wr32_epcs(hw, TXGBE_PHY_VCO_CAL_LD0, 0x0540);
2071 wr32_epcs(hw, TXGBE_PHY_VCO_CAL_REF0, 0x002A);
2072 wr32_epcs(hw, TXGBE_PHY_AFE_DFE_ENABLE, 0x0);
2073 wr32_epcs(hw, TXGBE_PHY_RX_EQ_CTL, 0x0010);
2074 wr32_epcs(hw, TXGBE_PHY_TX_RATE_CTL, 0x0003);
2075 wr32_epcs(hw, TXGBE_PHY_RX_RATE_CTL, 0x0003);
2076 wr32_epcs(hw, TXGBE_PHY_TX_GEN_CTL2, 0x0100);
2077 wr32_epcs(hw, TXGBE_PHY_RX_GEN_CTL2, 0x0100);
2078 wr32_epcs(hw, TXGBE_PHY_MPLLA_CTL2, 0x0200);
2079 wr32_epcs(hw, SR_MII_MMD_AN_CTL, 0x0100);
2081 /* 10. Initialize the mode by setting VR XS or PCS MMD Digital Control1
2082 * Register Bit[15](VR_RST)
2084 wr32_epcs(hw, VR_XS_OR_PCS_MMD_DIGI_CTL1, 0xA000);
2086 /* Wait phy initialization done */
2087 for (i = 0; i < 100; i++) {
2088 if ((rd32_epcs(hw, VR_XS_OR_PCS_MMD_DIGI_CTL1) &
2089 VR_XS_OR_PCS_MMD_DIGI_CTL1_VR_RST) == 0)
2094 err = TXGBE_ERR_PHY_INIT_NOT_DONE;
2103 * txgbe_autoc_read - Hides MAC differences needed for AUTOC read
2104 * @hw: pointer to hardware structure
2106 u64 txgbe_autoc_read(struct txgbe_hw *hw)
2114 if (hw->phy.multispeed_fiber) {
2115 autoc |= TXGBE_AUTOC_LMS_10G;
2116 } else if (hw->device_id == TXGBE_DEV_ID_RAPTOR_SFP ||
2117 hw->device_id == TXGBE_DEV_ID_WX1820_SFP) {
2118 autoc |= TXGBE_AUTOC_LMS_10G |
2119 TXGBE_AUTOC_10GS_SFI;
2120 } else if (hw->device_id == TXGBE_DEV_ID_RAPTOR_QSFP) {
2122 } else if (hw->device_id == TXGBE_DEV_ID_RAPTOR_XAUI) {
2123 autoc |= TXGBE_AUTOC_LMS_10G_LINK_NO_AN |
2124 TXGBE_AUTOC_10G_XAUI;
2125 hw->phy.link_mode = TXGBE_PHYSICAL_LAYER_10GBASE_T;
2126 } else if (hw->device_id == TXGBE_DEV_ID_RAPTOR_SGMII) {
2127 autoc |= TXGBE_AUTOC_LMS_SGMII_1G_100M;
2128 hw->phy.link_mode = TXGBE_PHYSICAL_LAYER_1000BASE_T |
2129 TXGBE_PHYSICAL_LAYER_100BASE_TX;
2132 if (hw->device_id != TXGBE_DEV_ID_RAPTOR_SGMII)
2135 sr_pcs_ctl = rd32_epcs(hw, SR_XS_PCS_CTRL2);
2136 sr_pma_ctl1 = rd32_epcs(hw, SR_PMA_CTRL1);
2137 sr_an_ctl = rd32_epcs(hw, SR_AN_CTRL);
2138 sr_an_adv_reg2 = rd32_epcs(hw, SR_AN_MMD_ADV_REG2);
2140 if ((sr_pcs_ctl & SR_PCS_CTRL2_TYPE_SEL) == SR_PCS_CTRL2_TYPE_SEL_X &&
2141 (sr_pma_ctl1 & SR_PMA_CTRL1_SS13) == SR_PMA_CTRL1_SS13_KX &&
2142 (sr_an_ctl & SR_AN_CTRL_AN_EN) == 0) {
2143 /* 1G or KX - no backplane auto-negotiation */
2144 autoc |= TXGBE_AUTOC_LMS_1G_LINK_NO_AN |
2146 hw->phy.link_mode = TXGBE_PHYSICAL_LAYER_1000BASE_KX;
2147 } else if ((sr_pcs_ctl & SR_PCS_CTRL2_TYPE_SEL) ==
2148 SR_PCS_CTRL2_TYPE_SEL_X &&
2149 (sr_pma_ctl1 & SR_PMA_CTRL1_SS13) == SR_PMA_CTRL1_SS13_KX4 &&
2150 (sr_an_ctl & SR_AN_CTRL_AN_EN) == 0) {
2151 autoc |= TXGBE_AUTOC_LMS_10G |
2152 TXGBE_AUTOC_10G_KX4;
2153 hw->phy.link_mode = TXGBE_PHYSICAL_LAYER_10GBASE_KX4;
2154 } else if ((sr_pcs_ctl & SR_PCS_CTRL2_TYPE_SEL) ==
2155 SR_PCS_CTRL2_TYPE_SEL_R &&
2156 (sr_an_ctl & SR_AN_CTRL_AN_EN) == 0) {
2157 /* 10 GbE serial link (KR -no backplane auto-negotiation) */
2158 autoc |= TXGBE_AUTOC_LMS_10G |
2159 TXGBE_AUTOC_10GS_KR;
2160 hw->phy.link_mode = TXGBE_PHYSICAL_LAYER_10GBASE_KR;
2161 } else if ((sr_an_ctl & SR_AN_CTRL_AN_EN)) {
2162 /* KX/KX4/KR backplane auto-negotiation enable */
2163 if (sr_an_adv_reg2 & SR_AN_MMD_ADV_REG2_BP_TYPE_KR)
2164 autoc |= TXGBE_AUTOC_10G_KR;
2165 if (sr_an_adv_reg2 & SR_AN_MMD_ADV_REG2_BP_TYPE_KX4)
2166 autoc |= TXGBE_AUTOC_10G_KX4;
2167 if (sr_an_adv_reg2 & SR_AN_MMD_ADV_REG2_BP_TYPE_KX)
2168 autoc |= TXGBE_AUTOC_1G_KX;
2169 autoc |= TXGBE_AUTOC_LMS_KX4_KX_KR;
2170 hw->phy.link_mode = TXGBE_PHYSICAL_LAYER_10GBASE_KR |
2171 TXGBE_PHYSICAL_LAYER_10GBASE_KX4 |
2172 TXGBE_PHYSICAL_LAYER_1000BASE_KX;
2179 * txgbe_autoc_write - Hides MAC differences needed for AUTOC write
2180 * @hw: pointer to hardware structure
2181 * @autoc: value to write to AUTOC
2183 void txgbe_autoc_write(struct txgbe_hw *hw, u64 autoc)
2189 speed = TXGBE_AUTOC_SPEED(autoc);
2190 autoc &= ~TXGBE_AUTOC_SPEED_MASK;
2191 autoneg = (autoc & TXGBE_AUTOC_AUTONEG ? true : false);
2192 autoc &= ~TXGBE_AUTOC_AUTONEG;
2194 if (hw->device_id == TXGBE_DEV_ID_RAPTOR_KR_KX_KX4) {
2196 switch (hw->phy.link_mode) {
2197 case TXGBE_PHYSICAL_LAYER_10GBASE_KR:
2198 txgbe_set_link_to_kr(hw, autoneg);
2200 case TXGBE_PHYSICAL_LAYER_10GBASE_KX4:
2201 txgbe_set_link_to_kx4(hw, autoneg);
2203 case TXGBE_PHYSICAL_LAYER_1000BASE_KX:
2204 txgbe_set_link_to_kx(hw, speed, autoneg);
2210 } else if (hw->device_id == TXGBE_DEV_ID_RAPTOR_XAUI ||
2211 hw->device_id == TXGBE_DEV_ID_RAPTOR_SGMII) {
2212 if (speed == TXGBE_LINK_SPEED_10GB_FULL) {
2213 txgbe_set_link_to_kx4(hw, autoneg);
2215 txgbe_set_link_to_kx(hw, speed, 0);
2216 txgbe_set_sgmii_an37_ability(hw);
2218 } else if (hw->device_id == TXGBE_DEV_ID_RAPTOR_SFP ||
2219 hw->device_id == TXGBE_DEV_ID_WX1820_SFP) {
2220 txgbe_set_link_to_sfi(hw, speed);
2223 if (speed == TXGBE_LINK_SPEED_10GB_FULL)
2224 mactxcfg = TXGBE_MACTXCFG_SPEED_10G;
2225 else if (speed == TXGBE_LINK_SPEED_1GB_FULL)
2226 mactxcfg = TXGBE_MACTXCFG_SPEED_1G;
2228 /* enable mac transmitter */
2229 wr32m(hw, TXGBE_MACTXCFG, TXGBE_MACTXCFG_SPEED_MASK, mactxcfg);