1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2015-2020 Beijing WangXun Technology Co., Ltd.
3 * Copyright(c) 2010-2017 Intel Corporation
9 #include "txgbe_type.h"
11 #define TXGBE_SFP_DETECT_RETRIES 10
12 #define TXGBE_MD_COMMAND_TIMEOUT 100 /* PHY Timeout for 1 GB mode */
15 /* ETH PHY Registers */
16 #define SR_XS_PCS_MMD_STATUS1 0x030001
17 #define SR_XS_PCS_CTRL2 0x030007
18 #define SR_PCS_CTRL2_TYPE_SEL MS16(0, 0x3)
19 #define SR_PCS_CTRL2_TYPE_SEL_R LS16(0, 0, 0x3)
20 #define SR_PCS_CTRL2_TYPE_SEL_X LS16(1, 0, 0x3)
21 #define SR_PCS_CTRL2_TYPE_SEL_W LS16(2, 0, 0x3)
22 #define SR_XS_PCS_KR_STS1 0x030020
23 #define SR_XS_PCS_KR_STS1_PLU MS16(12, 0x1)
24 #define SR_PMA_CTRL1 0x010000
25 #define SR_PMA_CTRL1_SS13 MS16(13, 0x1)
26 #define SR_PMA_CTRL1_SS13_KX LS16(0, 13, 0x1)
27 #define SR_PMA_CTRL1_SS13_KX4 LS16(1, 13, 0x1)
28 #define SR_PMA_CTRL1_LB MS16(0, 0x1)
29 #define SR_PMA_KR_PMD_CTRL 0x010096
30 #define SR_PMA_KR_PMD_CTRL_EN_TR MS16(1, 0x1)
31 #define SR_PMA_KR_PMD_CTRL_RS_TR MS16(0, 0x1)
32 #define SR_PMA_KR_PMD_STS 0x010097
33 #define SR_PMA_KR_PMD_STS_TR_FAIL MS16(3, 0x1)
34 #define SR_PMA_KR_PMD_STS_RCV MS16(0, 0x1)
35 #define SR_PMA_KR_LP_CEU 0x010098
36 #define SR_PMA_KR_LP_CESTS 0x010099
37 #define SR_PMA_KR_LP_CESTS_RR MS16(15, 0x1)
38 #define SR_PMA_KR_LD_CEU 0x01009A
39 #define SR_PMA_KR_LD_CESTS 0x01009B
40 #define SR_PMA_KR_LD_CESTS_RR MS16(15, 0x1)
41 #define SR_PMA_KR_FEC_CTRL 0x0100AB
42 #define SR_PMA_KR_FEC_CTRL_EN MS16(0, 0x1)
43 #define SR_MII_MMD_CTL 0x1F0000
44 #define SR_MII_MMD_CTL_AN_EN 0x1000
45 #define SR_MII_MMD_CTL_RESTART_AN 0x0200
46 #define SR_MII_MMD_DIGI_CTL 0x1F8000
47 #define SR_MII_MMD_AN_CTL 0x1F8001
48 #define SR_MII_MMD_AN_ADV 0x1F0004
49 #define SR_MII_MMD_AN_ADV_PAUSE(v) ((0x3 & (v)) << 7)
50 #define SR_MII_MMD_AN_ADV_PAUSE_ASM 0x80
51 #define SR_MII_MMD_AN_ADV_PAUSE_SYM 0x100
52 #define SR_MII_MMD_LP_BABL 0x1F0005
54 #define BP_TYPE_KX 0x20
55 #define BP_TYPE_KX4 0x40
56 #define BP_TYPE_KX4_KX 0x60
57 #define BP_TYPE_KR 0x80
58 #define BP_TYPE_KR_KX 0xA0
59 #define BP_TYPE_KR_KX4 0xC0
60 #define BP_TYPE_KR_KX4_KX 0xE0
62 #define SR_AN_CTRL 0x070000
63 #define SR_AN_CTRL_RSTRT_AN MS16(9, 0x1)
64 #define SR_AN_CTRL_AN_EN MS16(12, 0x1)
65 #define SR_AN_CTRL_EXT_NP MS16(13, 0x1)
66 #define SR_AN_MMD_ADV_REG1 0x070010
67 #define SR_AN_MMD_ADV_REG1_PAUSE(v) ((0x3 & (v)) << 10)
68 #define SR_AN_MMD_ADV_REG1_PAUSE_SYM 0x400
69 #define SR_AN_MMD_ADV_REG1_PAUSE_ASM 0x800
70 #define SR_AN_MMD_ADV_REG1_NP(v) RS16(v, 15, 0x1)
71 #define SR_AN_MMD_ADV_REG2 0x070011
72 #define SR_AN_MMD_ADV_REG2_BP_TYPE_KX4 BP_TYPE_KX4
73 #define SR_AN_MMD_ADV_REG2_BP_TYPE_KX BP_TYPE_KX
74 #define SR_AN_MMD_ADV_REG2_BP_TYPE_KR BP_TYPE_KR
75 #define SR_AN_MMD_ADV_REG2_BP_TYPE_KX4_KX BP_TYPE_KX4_KX
76 #define SR_AN_MMD_ADV_REG2_BP_TYPE_KR_KX BP_TYPE_KR_KX
77 #define SR_AN_MMD_ADV_REG2_BP_TYPE_KR_KX4 BP_TYPE_KR_KX4
78 #define SR_AN_MMD_ADV_REG2_BP_TYPE_KR_KX4_KX BP_TYPE_KR_KX4_KX
79 #define SR_AN_MMD_ADV_REG2_BP_TYPE_MASK 0xFFFF
80 #define SR_AN_MMD_ADV_REG3 0x070012
81 #define SR_AN_MMD_ADV_REG3_FCE(v) RS16(v, 14, 0x3)
82 #define SR_AN_MMD_LP_ABL1 0x070013
83 #define SR_MMD_LP_ABL1_ADV_NP(v) RS16(v, 15, 0x1)
84 #define SR_AN_MMD_LP_ABL2 0x070014
85 #define SR_AN_MMD_LP_ABL2_BP_TYPE_KX4 BP_TYPE_KX4
86 #define SR_AN_MMD_LP_ABL2_BP_TYPE_KX BP_TYPE_KX
87 #define SR_AN_MMD_LP_ABL2_BP_TYPE_KR BP_TYPE_KR
88 #define SR_AN_MMD_LP_ABL2_BP_TYPE_KX4_KX BP_TYPE_KX4_KX
89 #define SR_AN_MMD_LP_ABL2_BP_TYPE_KR_KX BP_TYPE_KR_KX
90 #define SR_AN_MMD_LP_ABL2_BP_TYPE_KR_KX4 BP_TYPE_KR_KX4
91 #define SR_AN_MMD_LP_ABL2_BP_TYPE_KR_KX4_KX BP_TYPE_KR_KX4_KX
92 #define SR_AN_MMD_LP_ABL2_BP_TYPE_MASK 0xFFFF
93 #define SR_AN_MMD_LP_ABL3 0x070015
94 #define SR_AN_MMD_LP_ABL3_FCE(v) RS16(v, 14, 0x3)
95 #define SR_AN_XNP_TX1 0x070016
96 #define SR_AN_XNP_TX1_NP MS16(15, 0x1)
97 #define SR_AN_LP_XNP_ABL1 0x070019
98 #define SR_AN_LP_XNP_ABL1_NP(v) RS16(v, 15, 0x1)
100 #define VR_AN_INTR_MSK 0x078001
101 #define VR_AN_INTR_CMPLT_IE MS16(0, 0x1)
102 #define VR_AN_INTR_LINK_IE MS16(1, 0x1)
103 #define VR_AN_INTR_PG_RCV_IE MS16(2, 0x1)
104 #define VR_AN_INTR 0x078002
105 #define VR_AN_INTR_CMPLT MS16(0, 0x1)
106 #define VR_AN_INTR_LINK MS16(1, 0x1)
107 #define VR_AN_INTR_PG_RCV MS16(2, 0x1)
108 #define VR_AN_KR_MODE_CL 0x078003
109 #define VR_AN_KR_MODE_CL_PDET MS16(0, 0x1)
110 #define VR_XS_OR_PCS_MMD_DIGI_CTL1 0x038000
111 #define VR_XS_OR_PCS_MMD_DIGI_CTL1_ENABLE 0x1000
112 #define VR_XS_OR_PCS_MMD_DIGI_CTL1_VR_RST 0x8000
113 #define VR_XS_OR_PCS_MMD_DIGI_CTL2 0x038001
114 #define VR_XS_OR_PCS_MMD_DIGI_STATUS 0x038010
115 #define VR_XS_OR_PCS_MMD_DIGI_STATUS_PSEQ_MASK 0x1C
116 #define VR_XS_OR_PCS_MMD_DIGI_STATUS_PSEQ_POWER_GOOD 0x10
117 #define VR_PMA_KRTR_PRBS_CTRL0 0x018003
118 #define VR_PMA_KRTR_PRBS31_EN MS16(1, 0x1)
119 #define VR_PMA_KRTR_PRBS_MODE_EN MS16(0, 0x1)
120 #define VR_PMA_KRTR_PRBS_CTRL1 0x018004
121 #define VR_PMA_KRTR_PRBS_TIME_LMT MS16(0, 0xFFFF)
122 #define VR_PMA_KRTR_PRBS_CTRL2 0x018005
123 #define VR_PMA_KRTR_PRBS_ERR_LIM MS16(0, 0x2FFF)
124 #define VR_PMA_KRTR_TIMER_CTRL0 0x018006
125 #define VR_PMA_KRTR_TIMER_MAX_WAIT MS16(0, 0xFFFF)
126 #define VR_PMA_KRTR_TIMER_CTRL2 0x018008
128 #define TXGBE_PHY_MPLLA_CTL0 0x018071
129 #define TXGBE_PHY_MPLLA_CTL3 0x018077
130 #define TXGBE_PHY_MISC_CTL0 0x018090
131 #define TXGBE_PHY_VCO_CAL_LD0 0x018092
132 #define TXGBE_PHY_VCO_CAL_LD1 0x018093
133 #define TXGBE_PHY_VCO_CAL_LD2 0x018094
134 #define TXGBE_PHY_VCO_CAL_LD3 0x018095
135 #define TXGBE_PHY_VCO_CAL_REF0 0x018096
136 #define TXGBE_PHY_VCO_CAL_REF1 0x018097
137 #define TXGBE_PHY_RX_AD_ACK 0x018098
138 #define TXGBE_PHY_AFE_DFE_ENABLE 0x01805D
139 #define TXGBE_PHY_DFE_TAP_CTL0 0x01805E
140 #define TXGBE_PHY_RX_EQ_ATT_LVL0 0x018057
141 #define TXGBE_PHY_RX_EQ_CTL0 0x018058
142 #define TXGBE_PHY_RX_EQ_CTL 0x01805C
143 #define TXGBE_PHY_TX_EQ_CTL0 0x018036
144 #define TXGBE_PHY_TX_EQ_CTL1 0x018037
145 #define TXGBE_PHY_TX_EQ_CTL1_DEF MS16(7, 0x1)
146 #define TXGBE_PHY_TX_RATE_CTL 0x018034
147 #define TXGBE_PHY_RX_RATE_CTL 0x018054
148 #define TXGBE_PHY_TX_GEN_CTL2 0x018032
149 #define TXGBE_PHY_RX_GEN_CTL2 0x018052
150 #define TXGBE_PHY_RX_GEN_CTL3 0x018053
151 #define TXGBE_PHY_MPLLA_CTL2 0x018073
152 #define TXGBE_PHY_RX_POWER_ST_CTL 0x018055
153 #define TXGBE_PHY_TX_POWER_ST_CTL 0x018035
154 #define TXGBE_PHY_TX_GENCTRL1 0x018031
155 #define TXGBE_PHY_EQ_INIT_CTL0 0x01803A
156 #define TXGBE_PHY_EQ_INIT_CTL1 0x01803B
158 #define TXGBE_PHY_MPLLA_CTL0_MULTIPLIER_1GBASEX_KX 32
159 #define TXGBE_PHY_MPLLA_CTL0_MULTIPLIER_10GBASER_KR 33
160 #define TXGBE_PHY_MPLLA_CTL0_MULTIPLIER_OTHER 40
161 #define TXGBE_PHY_MPLLA_CTL0_MULTIPLIER_MASK 0xFF
162 #define TXGBE_PHY_MPLLA_CTL3_MULTIPLIER_BW_1GBASEX_KX 0x56
163 #define TXGBE_PHY_MPLLA_CTL3_MULTIPLIER_BW_10GBASER_KR 0x7B
164 #define TXGBE_PHY_MPLLA_CTL3_MULTIPLIER_BW_OTHER 0x56
165 #define TXGBE_PHY_MPLLA_CTL3_MULTIPLIER_BW_MASK 0x7FF
166 #define TXGBE_PHY_MISC_CTL0_TX2RX_LB_EN_0 0x1
167 #define TXGBE_PHY_MISC_CTL0_TX2RX_LB_EN_3_1 0xE
168 #define TXGBE_PHY_MISC_CTL0_RX_VREF_CTRL 0x1F00
169 #define TXGBE_PHY_VCO_CAL_LD0_1GBASEX_KX 1344
170 #define TXGBE_PHY_VCO_CAL_LD0_10GBASER_KR 1353
171 #define TXGBE_PHY_VCO_CAL_LD0_OTHER 1360
172 #define TXGBE_PHY_VCO_CAL_LD0_MASK 0x1000
173 #define TXGBE_PHY_VCO_CAL_REF0_LD0_1GBASEX_KX 42
174 #define TXGBE_PHY_VCO_CAL_REF0_LD0_10GBASER_KR 41
175 #define TXGBE_PHY_VCO_CAL_REF0_LD0_OTHER 34
176 #define TXGBE_PHY_VCO_CAL_REF0_LD0_MASK 0x3F
177 #define TXGBE_PHY_AFE_DFE_ENABLE_DFE_EN0 0x10
178 #define TXGBE_PHY_AFE_DFE_ENABLE_AFE_EN0 0x1
179 #define TXGBE_PHY_AFE_DFE_ENABLE_MASK 0xFF
180 #define TXGBE_PHY_RX_EQ_CTL_CONT_ADAPT0 0x1
181 #define TXGBE_PHY_RX_EQ_CTL_CONT_ADAPT_MASK 0xF
182 #define TXGBE_PHY_TX_RATE_CTL_TX0_RATE_10GBASER_KR 0x0
183 #define TXGBE_PHY_TX_RATE_CTL_TX0_RATE_RXAUI 0x1
184 #define TXGBE_PHY_TX_RATE_CTL_TX0_RATE_1GBASEX_KX 0x3
185 #define TXGBE_PHY_TX_RATE_CTL_TX0_RATE_OTHER 0x2
186 #define TXGBE_PHY_TX_RATE_CTL_TX1_RATE_OTHER 0x20
187 #define TXGBE_PHY_TX_RATE_CTL_TX2_RATE_OTHER 0x200
188 #define TXGBE_PHY_TX_RATE_CTL_TX3_RATE_OTHER 0x2000
189 #define TXGBE_PHY_TX_RATE_CTL_TX0_RATE_MASK 0x7
190 #define TXGBE_PHY_TX_RATE_CTL_TX1_RATE_MASK 0x70
191 #define TXGBE_PHY_TX_RATE_CTL_TX2_RATE_MASK 0x700
192 #define TXGBE_PHY_TX_RATE_CTL_TX3_RATE_MASK 0x7000
193 #define TXGBE_PHY_RX_RATE_CTL_RX0_RATE_10GBASER_KR 0x0
194 #define TXGBE_PHY_RX_RATE_CTL_RX0_RATE_RXAUI 0x1
195 #define TXGBE_PHY_RX_RATE_CTL_RX0_RATE_1GBASEX_KX 0x3
196 #define TXGBE_PHY_RX_RATE_CTL_RX0_RATE_OTHER 0x2
197 #define TXGBE_PHY_RX_RATE_CTL_RX1_RATE_OTHER 0x20
198 #define TXGBE_PHY_RX_RATE_CTL_RX2_RATE_OTHER 0x200
199 #define TXGBE_PHY_RX_RATE_CTL_RX3_RATE_OTHER 0x2000
200 #define TXGBE_PHY_RX_RATE_CTL_RX0_RATE_MASK 0x7
201 #define TXGBE_PHY_RX_RATE_CTL_RX1_RATE_MASK 0x70
202 #define TXGBE_PHY_RX_RATE_CTL_RX2_RATE_MASK 0x700
203 #define TXGBE_PHY_RX_RATE_CTL_RX3_RATE_MASK 0x7000
204 #define TXGBE_PHY_TX_GEN_CTL2_TX0_WIDTH_10GBASER_KR 0x200
205 #define TXGBE_PHY_TX_GEN_CTL2_TX0_WIDTH_10GBASER_KR_RXAUI 0x300
206 #define TXGBE_PHY_TX_GEN_CTL2_TX0_WIDTH_OTHER 0x100
207 #define TXGBE_PHY_TX_GEN_CTL2_TX0_WIDTH_MASK 0x300
208 #define TXGBE_PHY_TX_GEN_CTL2_TX1_WIDTH_OTHER 0x400
209 #define TXGBE_PHY_TX_GEN_CTL2_TX1_WIDTH_MASK 0xC00
210 #define TXGBE_PHY_TX_GEN_CTL2_TX2_WIDTH_OTHER 0x1000
211 #define TXGBE_PHY_TX_GEN_CTL2_TX2_WIDTH_MASK 0x3000
212 #define TXGBE_PHY_TX_GEN_CTL2_TX3_WIDTH_OTHER 0x4000
213 #define TXGBE_PHY_TX_GEN_CTL2_TX3_WIDTH_MASK 0xC000
214 #define TXGBE_PHY_RX_GEN_CTL2_RX0_WIDTH_10GBASER_KR 0x200
215 #define TXGBE_PHY_RX_GEN_CTL2_RX0_WIDTH_10GBASER_KR_RXAUI 0x300
216 #define TXGBE_PHY_RX_GEN_CTL2_RX0_WIDTH_OTHER 0x100
217 #define TXGBE_PHY_RX_GEN_CTL2_RX0_WIDTH_MASK 0x300
218 #define TXGBE_PHY_RX_GEN_CTL2_RX1_WIDTH_OTHER 0x400
219 #define TXGBE_PHY_RX_GEN_CTL2_RX1_WIDTH_MASK 0xC00
220 #define TXGBE_PHY_RX_GEN_CTL2_RX2_WIDTH_OTHER 0x1000
221 #define TXGBE_PHY_RX_GEN_CTL2_RX2_WIDTH_MASK 0x3000
222 #define TXGBE_PHY_RX_GEN_CTL2_RX3_WIDTH_OTHER 0x4000
223 #define TXGBE_PHY_RX_GEN_CTL2_RX3_WIDTH_MASK 0xC000
224 #define TXGBE_PHY_MPLLA_CTL2_DIV_CLK_EN_8 0x100
225 #define TXGBE_PHY_MPLLA_CTL2_DIV_CLK_EN_10 0x200
226 #define TXGBE_PHY_MPLLA_CTL2_DIV_CLK_EN_16P5 0x400
227 #define TXGBE_PHY_MPLLA_CTL2_DIV_CLK_EN_MASK 0x700
228 #define TXGBE_PHY_LANE0_TX_EQ_CTL1 0x100E
229 #define TXGBE_PHY_LANE0_TX_EQ_CTL1_MAIN(v) RS16(v, 6, 0x3F)
230 #define TXGBE_PHY_LANE0_TX_EQ_CTL2 0x100F
231 #define TXGBE_PHY_LANE0_TX_EQ_CTL2_PRE MS16(0, 0x3F)
232 #define TXGBE_PHY_LANE0_TX_EQ_CTL2_POST(v) RS16(v, 6, 0x3F)
234 /******************************************************************************
236 ******************************************************************************/
237 /* SFP IDs: format of OUI is 0x[byte0][byte1][byte2][00] */
238 #define TXGBE_SFF_VENDOR_OUI_TYCO 0x00407600
239 #define TXGBE_SFF_VENDOR_OUI_FTL 0x00906500
240 #define TXGBE_SFF_VENDOR_OUI_AVAGO 0x00176A00
241 #define TXGBE_SFF_VENDOR_OUI_INTEL 0x001B2100
243 /* EEPROM (dev_addr = 0xA0) */
244 #define TXGBE_I2C_EEPROM_DEV_ADDR 0xA0
245 #define TXGBE_SFF_IDENTIFIER 0x00
246 #define TXGBE_SFF_IDENTIFIER_SFP 0x03
247 #define TXGBE_SFF_VENDOR_OUI_BYTE0 0x25
248 #define TXGBE_SFF_VENDOR_OUI_BYTE1 0x26
249 #define TXGBE_SFF_VENDOR_OUI_BYTE2 0x27
250 #define TXGBE_SFF_1GBE_COMP_CODES 0x06
251 #define TXGBE_SFF_10GBE_COMP_CODES 0x03
252 #define TXGBE_SFF_CABLE_TECHNOLOGY 0x08
253 #define TXGBE_SFF_CABLE_DA_PASSIVE 0x4
254 #define TXGBE_SFF_CABLE_DA_ACTIVE 0x8
255 #define TXGBE_SFF_CABLE_SPEC_COMP 0x3C
256 #define TXGBE_SFF_SFF_8472_SWAP 0x5C
257 #define TXGBE_SFF_SFF_8472_COMP 0x5E
258 #define TXGBE_SFF_SFF_8472_OSCB 0x6E
259 #define TXGBE_SFF_SFF_8472_ESCB 0x76
261 #define TXGBE_SFF_IDENTIFIER_QSFP_PLUS 0x0D
262 #define TXGBE_SFF_QSFP_VENDOR_OUI_BYTE0 0xA5
263 #define TXGBE_SFF_QSFP_VENDOR_OUI_BYTE1 0xA6
264 #define TXGBE_SFF_QSFP_VENDOR_OUI_BYTE2 0xA7
265 #define TXGBE_SFF_QSFP_CONNECTOR 0x82
266 #define TXGBE_SFF_QSFP_10GBE_COMP 0x83
267 #define TXGBE_SFF_QSFP_1GBE_COMP 0x86
268 #define TXGBE_SFF_QSFP_CABLE_LENGTH 0x92
269 #define TXGBE_SFF_QSFP_DEVICE_TECH 0x93
272 #define TXGBE_SFF_DA_SPEC_ACTIVE_LIMITING 0x4
273 #define TXGBE_SFF_1GBASESX_CAPABLE 0x1
274 #define TXGBE_SFF_1GBASELX_CAPABLE 0x2
275 #define TXGBE_SFF_1GBASET_CAPABLE 0x8
276 #define TXGBE_SFF_10GBASESR_CAPABLE 0x10
277 #define TXGBE_SFF_10GBASELR_CAPABLE 0x20
278 #define TXGBE_SFF_SOFT_RS_SELECT_MASK 0x8
279 #define TXGBE_SFF_SOFT_RS_SELECT_10G 0x8
280 #define TXGBE_SFF_SOFT_RS_SELECT_1G 0x0
281 #define TXGBE_SFF_ADDRESSING_MODE 0x4
282 #define TXGBE_SFF_QSFP_DA_ACTIVE_CABLE 0x1
283 #define TXGBE_SFF_QSFP_DA_PASSIVE_CABLE 0x8
284 #define TXGBE_SFF_QSFP_CONNECTOR_NOT_SEPARABLE 0x23
285 #define TXGBE_SFF_QSFP_TRANSMITTER_850NM_VCSEL 0x0
286 #define TXGBE_I2C_EEPROM_READ_MASK 0x100
287 #define TXGBE_I2C_EEPROM_STATUS_MASK 0x3
288 #define TXGBE_I2C_EEPROM_STATUS_NO_OPERATION 0x0
289 #define TXGBE_I2C_EEPROM_STATUS_PASS 0x1
290 #define TXGBE_I2C_EEPROM_STATUS_FAIL 0x2
291 #define TXGBE_I2C_EEPROM_STATUS_IN_PROGRESS 0x3
293 /* EEPROM for SFF-8472 (dev_addr = 0xA2) */
294 #define TXGBE_I2C_EEPROM_DEV_ADDR2 0xA2
296 /* SFP+ SFF-8472 Compliance */
297 #define TXGBE_SFF_SFF_8472_UNSUP 0x00
299 /******************************************************************************
300 * PHY MDIO Registers:
301 ******************************************************************************/
302 #define TXGBE_MAX_PHY_ADDR 32
304 #define TXGBE_PHYID_MTD3310 0x00000000U
305 #define TXGBE_PHYID_TN1010 0x00A19410U
306 #define TXGBE_PHYID_QT2022 0x0043A400U
307 #define TXGBE_PHYID_ATH 0x03429050U
310 #define TXGBE_MD_DEV_PMA_PMD 0x1
311 #define TXGBE_MD_PHY_ID_HIGH 0x2 /* PHY ID High Reg*/
312 #define TXGBE_MD_PHY_ID_LOW 0x3 /* PHY ID Low Reg*/
313 #define TXGBE_PHY_REVISION_MASK 0xFFFFFFF0
314 #define TXGBE_MD_PHY_SPEED_ABILITY 0x4 /* Speed Ability Reg */
315 #define TXGBE_MD_PHY_SPEED_10G 0x0001 /* 10G capable */
316 #define TXGBE_MD_PHY_SPEED_1G 0x0010 /* 1G capable */
317 #define TXGBE_MD_PHY_SPEED_100M 0x0020 /* 100M capable */
318 #define TXGBE_MD_PHY_EXT_ABILITY 0xB /* Ext Ability Reg */
319 #define TXGBE_MD_PHY_10GBASET_ABILITY 0x0004 /* 10GBaseT capable */
320 #define TXGBE_MD_PHY_1000BASET_ABILITY 0x0020 /* 1000BaseT capable */
321 #define TXGBE_MD_PHY_100BASETX_ABILITY 0x0080 /* 100BaseTX capable */
322 #define TXGBE_MD_PHY_SET_LOW_POWER_MODE 0x0800 /* Set low power mode */
324 #define TXGBE_MD_TX_VENDOR_ALARMS_3 0xCC02 /* Vendor Alarms 3 Reg */
325 #define TXGBE_MD_PMA_PMD_SDA_SCL_ADDR 0xC30A /* PHY_XS SDA/SCL Addr Reg */
326 #define TXGBE_MD_PMA_PMD_SDA_SCL_DATA 0xC30B /* PHY_XS SDA/SCL Data Reg */
327 #define TXGBE_MD_PMA_PMD_SDA_SCL_STAT 0xC30C /* PHY_XS SDA/SCL Status Reg */
329 #define TXGBE_MD_FW_REV_LO 0xC011
330 #define TXGBE_MD_FW_REV_HI 0xC012
332 #define TXGBE_TN_LASI_STATUS_REG 0x9005
333 #define TXGBE_TN_LASI_STATUS_TEMP_ALARM 0x0008
336 #define TXGBE_MD_DEV_PCS 0x3
337 #define TXGBE_PCRC8ECL 0x0E810 /* PCR CRC-8 Error Count Lo */
338 #define TXGBE_PCRC8ECH 0x0E811 /* PCR CRC-8 Error Count Hi */
339 #define TXGBE_PCRC8ECH_MASK 0x1F
340 #define TXGBE_LDPCECL 0x0E820 /* PCR Uncorrected Error Count Lo */
341 #define TXGBE_LDPCECH 0x0E821 /* PCR Uncorrected Error Count Hi */
344 #define TXGBE_MD_DEV_PHY_XS 0x4
345 #define TXGBE_MD_PHY_XS_CONTROL 0x0 /* PHY_XS Control Reg */
346 #define TXGBE_MD_PHY_XS_RESET 0x8000 /* PHY_XS Reset */
349 #define TXGBE_MD_DEV_AUTO_NEG 0x7
351 #define TXGBE_MD_AUTO_NEG_CONTROL 0x0 /* AUTO_NEG Control Reg */
352 #define TXGBE_MD_AUTO_NEG_STATUS 0x1 /* AUTO_NEG Status Reg */
353 #define TXGBE_MD_AUTO_NEG_VENDOR_STAT 0xC800 /*AUTO_NEG Vendor Status Reg*/
354 #define TXGBE_MD_AUTO_NEG_VENDOR_TX_ALARM 0xCC00 /* AUTO_NEG Vendor TX Reg */
355 #define TXGBE_MD_AUTO_NEG_VENDOR_TX_ALARM2 0xCC01 /* AUTO_NEG Vendor Tx Reg */
356 #define TXGBE_MD_AUTO_NEG_VEN_LSC 0x1 /* AUTO_NEG Vendor Tx LSC */
357 #define TXGBE_MD_AUTO_NEG_ADVT 0x10 /* AUTO_NEG Advt Reg */
358 #define TXGBE_TAF_SYM_PAUSE MS16(10, 0x3)
359 #define TXGBE_TAF_ASM_PAUSE MS16(11, 0x3)
361 #define TXGBE_MD_AUTO_NEG_LP 0x13 /* AUTO_NEG LP Status Reg */
362 #define TXGBE_MD_AUTO_NEG_EEE_ADVT 0x3C /* AUTO_NEG EEE Advt Reg */
363 /* PHY address definitions for new protocol MDIO commands */
364 #define TXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG 0x20 /* 10G Control Reg */
365 #define TXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG 0xC400 /* 1G Provisioning 1 */
366 #define TXGBE_MII_AUTONEG_XNP_TX_REG 0x17 /* 1G XNP Transmit */
367 #define TXGBE_MII_AUTONEG_ADVERTISE_REG 0x10 /* 100M Advertisement */
368 #define TXGBE_MII_10GBASE_T_ADVERTISE 0x1000 /* full duplex, bit:12*/
369 #define TXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX 0x4000 /* full duplex, bit:14*/
370 #define TXGBE_MII_1GBASE_T_ADVERTISE 0x8000 /* full duplex, bit:15*/
371 #define TXGBE_MII_2_5GBASE_T_ADVERTISE 0x0400
372 #define TXGBE_MII_5GBASE_T_ADVERTISE 0x0800
373 #define TXGBE_MII_100BASE_T_ADVERTISE 0x0100 /* full duplex, bit:8 */
374 #define TXGBE_MII_100BASE_T_ADVERTISE_HALF 0x0080 /* half duplex, bit:7 */
375 #define TXGBE_MII_RESTART 0x200
376 #define TXGBE_MII_AUTONEG_COMPLETE 0x20
377 #define TXGBE_MII_AUTONEG_LINK_UP 0x04
378 #define TXGBE_MII_AUTONEG_REG 0x0
379 #define TXGBE_MD_PMA_TX_VEN_LASI_INT_MASK 0xD401 /* PHY TX Vendor LASI */
380 #define TXGBE_MD_PMA_TX_VEN_LASI_INT_EN 0x1 /* PHY TX Vendor LASI enable */
381 #define TXGBE_MD_PMD_STD_TX_DISABLE_CNTR 0x9 /* Standard Transmit Dis Reg */
382 #define TXGBE_MD_PMD_GLOBAL_TX_DISABLE 0x0001 /* PMD Global Transmit Dis */
384 /* (dev_type = 30) */
385 #define TXGBE_MD_DEV_VENDOR_1 30
386 #define TXGBE_MD_DEV_XFI_DSP 30
387 #define TNX_FW_REV 0xB
388 #define TXGBE_MD_VENDOR_SPECIFIC_1_CONTROL 0x0 /* VS1 Ctrl Reg */
389 #define TXGBE_MD_VENDOR_SPECIFIC_1_STATUS 0x1 /* VS1 Status Reg */
390 #define TXGBE_MD_VENDOR_SPECIFIC_1_LINK_STATUS 0x0008 /* 1 = Link Up */
391 #define TXGBE_MD_VENDOR_SPECIFIC_1_SPEED_STATUS 0x0010 /* 0-10G, 1-1G */
392 #define TXGBE_MD_VENDOR_SPECIFIC_1_10G_SPEED 0x0018
393 #define TXGBE_MD_VENDOR_SPECIFIC_1_1G_SPEED 0x0010
395 /* (dev_type = 31) */
396 #define TXGBE_MD_DEV_GENERAL 31
397 #define TXGBE_MD_PORT_CTRL 0xF001
398 #define TXGBE_MD_PORT_CTRL_RESET MS16(14, 0x1)
400 #define TXGBE_BP_M_NULL 0
401 #define TXGBE_BP_M_SFI 1
402 #define TXGBE_BP_M_KR 2
403 #define TXGBE_BP_M_KX4 3
404 #define TXGBE_BP_M_KX 4
405 #define TXGBE_BP_M_NAUTO 0
406 #define TXGBE_BP_M_AUTO 1
408 #ifndef CL72_KRTR_PRBS_MODE_EN
409 #define CL72_KRTR_PRBS_MODE_EN 0xFFFF /* open kr prbs check */
412 /******************************************************************************
414 ******************************************************************************/
415 #define TXGBE_I2C_SLAVEADDR (0x50)
417 bool txgbe_validate_phy_addr(struct txgbe_hw *hw, u32 phy_addr);
418 enum txgbe_phy_type txgbe_get_phy_type_from_id(u32 phy_id);
419 s32 txgbe_get_phy_id(struct txgbe_hw *hw);
420 s32 txgbe_identify_phy(struct txgbe_hw *hw);
421 s32 txgbe_reset_phy(struct txgbe_hw *hw);
422 s32 txgbe_read_phy_reg_mdi(struct txgbe_hw *hw, u32 reg_addr, u32 device_type,
424 s32 txgbe_write_phy_reg_mdi(struct txgbe_hw *hw, u32 reg_addr, u32 device_type,
426 s32 txgbe_read_phy_reg(struct txgbe_hw *hw, u32 reg_addr,
427 u32 device_type, u16 *phy_data);
428 s32 txgbe_write_phy_reg(struct txgbe_hw *hw, u32 reg_addr,
429 u32 device_type, u16 phy_data);
430 s32 txgbe_setup_phy_link(struct txgbe_hw *hw);
431 s32 txgbe_setup_phy_link_speed(struct txgbe_hw *hw,
433 bool autoneg_wait_to_complete);
434 s32 txgbe_get_phy_fw_version(struct txgbe_hw *hw, u32 *fw_version);
435 s32 txgbe_get_copper_link_capabilities(struct txgbe_hw *hw,
438 s32 txgbe_check_reset_blocked(struct txgbe_hw *hw);
441 s32 txgbe_check_phy_link_tnx(struct txgbe_hw *hw,
444 s32 txgbe_setup_phy_link_tnx(struct txgbe_hw *hw);
446 s32 txgbe_identify_module(struct txgbe_hw *hw);
447 s32 txgbe_identify_sfp_module(struct txgbe_hw *hw);
448 s32 txgbe_identify_qsfp_module(struct txgbe_hw *hw);
450 s32 txgbe_read_i2c_byte(struct txgbe_hw *hw, u8 byte_offset,
451 u8 dev_addr, u8 *data);
452 s32 txgbe_read_i2c_byte_unlocked(struct txgbe_hw *hw, u8 byte_offset,
453 u8 dev_addr, u8 *data);
454 s32 txgbe_write_i2c_byte(struct txgbe_hw *hw, u8 byte_offset,
455 u8 dev_addr, u8 data);
456 s32 txgbe_write_i2c_byte_unlocked(struct txgbe_hw *hw, u8 byte_offset,
457 u8 dev_addr, u8 data);
458 s32 txgbe_read_i2c_sff8472(struct txgbe_hw *hw, u8 byte_offset,
460 s32 txgbe_read_i2c_eeprom(struct txgbe_hw *hw, u8 byte_offset,
462 s32 txgbe_write_i2c_eeprom(struct txgbe_hw *hw, u8 byte_offset,
464 u64 txgbe_autoc_read(struct txgbe_hw *hw);
465 void txgbe_autoc_write(struct txgbe_hw *hw, u64 value);
466 void txgbe_bp_mode_set(struct txgbe_hw *hw);
467 void txgbe_set_phy_temp(struct txgbe_hw *hw);
468 void txgbe_bp_down_event(struct txgbe_hw *hw);
469 s32 txgbe_kr_handle(struct txgbe_hw *hw);
471 #endif /* _TXGBE_PHY_H_ */