1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2015-2020
8 #define TXGBE_LINK_UP_TIME 90 /* 9.0 Seconds */
10 #define TXGBE_ALIGN 128 /* as intel did */
12 #include "txgbe_status.h"
13 #include "txgbe_osdep.h"
14 #include "txgbe_devids.h"
16 enum txgbe_eeprom_type {
17 txgbe_eeprom_unknown = 0,
20 txgbe_eeprom_none /* No NVM support */
24 txgbe_mac_unknown = 0,
31 txgbe_phy_unknown = 0,
41 txgbe_phy_sfp_tyco_passive,
42 txgbe_phy_sfp_unknown_passive,
43 txgbe_phy_sfp_unknown_active,
46 txgbe_phy_sfp_ftl_active,
47 txgbe_phy_sfp_unknown,
49 txgbe_phy_qsfp_unknown_passive,
50 txgbe_phy_qsfp_unknown_active,
52 txgbe_phy_qsfp_unknown,
53 txgbe_phy_sfp_unsupported, /* Enforce bit set with unsupported module */
60 * SFP+ module type IDs:
67 * 3 SFP_DA_CU_CORE0 - chip-specific
68 * 4 SFP_DA_CU_CORE1 - chip-specific
69 * 5 SFP_SR/LR_CORE0 - chip-specific
70 * 6 SFP_SR/LR_CORE1 - chip-specific
73 txgbe_sfp_type_unknown = 0,
77 txgbe_sfp_type_da_cu_core0,
78 txgbe_sfp_type_da_cu_core1,
79 txgbe_sfp_type_srlr_core0,
80 txgbe_sfp_type_srlr_core1,
81 txgbe_sfp_type_da_act_lmt_core0,
82 txgbe_sfp_type_da_act_lmt_core1,
83 txgbe_sfp_type_1g_cu_core0,
84 txgbe_sfp_type_1g_cu_core1,
85 txgbe_sfp_type_1g_sx_core0,
86 txgbe_sfp_type_1g_sx_core1,
87 txgbe_sfp_type_1g_lx_core0,
88 txgbe_sfp_type_1g_lx_core1,
89 txgbe_sfp_type_not_present = 0xFFFE,
90 txgbe_sfp_type_not_known = 0xFFFF
93 enum txgbe_media_type {
94 txgbe_media_type_unknown = 0,
95 txgbe_media_type_fiber,
96 txgbe_media_type_fiber_qsfp,
97 txgbe_media_type_copper,
98 txgbe_media_type_backplane,
100 txgbe_media_type_virtual
104 enum txgbe_bus_type {
105 txgbe_bus_type_unknown = 0,
108 txgbe_bus_type_pci_express,
109 txgbe_bus_type_internal,
110 txgbe_bus_type_reserved
114 enum txgbe_bus_speed {
115 txgbe_bus_speed_unknown = 0,
116 txgbe_bus_speed_33 = 33,
117 txgbe_bus_speed_66 = 66,
118 txgbe_bus_speed_100 = 100,
119 txgbe_bus_speed_120 = 120,
120 txgbe_bus_speed_133 = 133,
121 txgbe_bus_speed_2500 = 2500,
122 txgbe_bus_speed_5000 = 5000,
123 txgbe_bus_speed_8000 = 8000,
124 txgbe_bus_speed_reserved
128 enum txgbe_bus_width {
129 txgbe_bus_width_unknown = 0,
130 txgbe_bus_width_pcie_x1 = 1,
131 txgbe_bus_width_pcie_x2 = 2,
132 txgbe_bus_width_pcie_x4 = 4,
133 txgbe_bus_width_pcie_x8 = 8,
134 txgbe_bus_width_32 = 32,
135 txgbe_bus_width_64 = 64,
136 txgbe_bus_width_reserved
142 struct txgbe_bus_info {
143 s32 (*get_bus_info)(struct txgbe_hw *hw);
144 void (*set_lan_id)(struct txgbe_hw *hw);
146 enum txgbe_bus_speed speed;
147 enum txgbe_bus_width width;
148 enum txgbe_bus_type type;
155 /* iterator type for walking multicast address lists */
156 typedef u8* (*txgbe_mc_addr_itr) (struct txgbe_hw *hw, u8 **mc_addr_ptr,
159 struct txgbe_link_info {
160 s32 (*read_link)(struct txgbe_hw *hw, u8 addr, u16 reg, u16 *val);
161 s32 (*read_link_unlocked)(struct txgbe_hw *hw, u8 addr, u16 reg,
163 s32 (*write_link)(struct txgbe_hw *hw, u8 addr, u16 reg, u16 val);
164 s32 (*write_link_unlocked)(struct txgbe_hw *hw, u8 addr, u16 reg,
170 struct txgbe_rom_info {
171 s32 (*init_params)(struct txgbe_hw *hw);
172 s32 (*read16)(struct txgbe_hw *hw, u32 offset, u16 *data);
173 s32 (*readw_sw)(struct txgbe_hw *hw, u32 offset, u16 *data);
174 s32 (*readw_buffer)(struct txgbe_hw *hw, u32 offset, u32 words,
176 s32 (*read32)(struct txgbe_hw *hw, u32 addr, u32 *data);
177 s32 (*read_buffer)(struct txgbe_hw *hw, u32 addr, u32 len, void *data);
178 s32 (*write16)(struct txgbe_hw *hw, u32 offset, u16 data);
179 s32 (*writew_sw)(struct txgbe_hw *hw, u32 offset, u16 data);
180 s32 (*writew_buffer)(struct txgbe_hw *hw, u32 offset, u32 words,
182 s32 (*write32)(struct txgbe_hw *hw, u32 addr, u32 data);
183 s32 (*write_buffer)(struct txgbe_hw *hw, u32 addr, u32 len, void *data);
184 s32 (*validate_checksum)(struct txgbe_hw *hw, u16 *checksum_val);
185 s32 (*update_checksum)(struct txgbe_hw *hw);
186 s32 (*calc_checksum)(struct txgbe_hw *hw);
188 enum txgbe_eeprom_type type;
198 struct txgbe_flash_info {
204 #define TXGBE_FLAGS_DOUBLE_RESET_REQUIRED 0x01
205 struct txgbe_mac_info {
206 s32 (*init_hw)(struct txgbe_hw *hw);
207 s32 (*reset_hw)(struct txgbe_hw *hw);
208 s32 (*start_hw)(struct txgbe_hw *hw);
209 s32 (*stop_hw)(struct txgbe_hw *hw);
210 s32 (*clear_hw_cntrs)(struct txgbe_hw *hw);
211 s32 (*get_mac_addr)(struct txgbe_hw *hw, u8 *mac_addr);
212 s32 (*get_san_mac_addr)(struct txgbe_hw *hw, u8 *san_mac_addr);
213 s32 (*set_san_mac_addr)(struct txgbe_hw *hw, u8 *san_mac_addr);
214 s32 (*get_device_caps)(struct txgbe_hw *hw, u16 *device_caps);
215 s32 (*get_wwn_prefix)(struct txgbe_hw *hw, u16 *wwnn_prefix,
217 s32 (*setup_sfp)(struct txgbe_hw *hw);
218 s32 (*enable_rx_dma)(struct txgbe_hw *hw, u32 regval);
219 s32 (*disable_sec_rx_path)(struct txgbe_hw *hw);
220 s32 (*enable_sec_rx_path)(struct txgbe_hw *hw);
221 s32 (*disable_sec_tx_path)(struct txgbe_hw *hw);
222 s32 (*enable_sec_tx_path)(struct txgbe_hw *hw);
223 s32 (*acquire_swfw_sync)(struct txgbe_hw *hw, u32 mask);
224 void (*release_swfw_sync)(struct txgbe_hw *hw, u32 mask);
225 u64 (*autoc_read)(struct txgbe_hw *hw);
226 void (*autoc_write)(struct txgbe_hw *hw, u64 value);
227 s32 (*prot_autoc_read)(struct txgbe_hw *hw, bool *locked, u64 *value);
228 s32 (*prot_autoc_write)(struct txgbe_hw *hw, bool locked, u64 value);
229 s32 (*negotiate_api_version)(struct txgbe_hw *hw, int api);
232 void (*disable_tx_laser)(struct txgbe_hw *hw);
233 void (*enable_tx_laser)(struct txgbe_hw *hw);
234 void (*flap_tx_laser)(struct txgbe_hw *hw);
235 s32 (*setup_link)(struct txgbe_hw *hw, u32 speed,
236 bool autoneg_wait_to_complete);
237 s32 (*setup_mac_link)(struct txgbe_hw *hw, u32 speed,
238 bool autoneg_wait_to_complete);
239 s32 (*check_link)(struct txgbe_hw *hw, u32 *speed,
240 bool *link_up, bool link_up_wait_to_complete);
241 s32 (*get_link_capabilities)(struct txgbe_hw *hw,
242 u32 *speed, bool *autoneg);
243 void (*set_rate_select_speed)(struct txgbe_hw *hw, u32 speed);
245 /* Packet Buffer manipulation */
246 void (*setup_pba)(struct txgbe_hw *hw, int num_pb, u32 headroom,
250 s32 (*led_on)(struct txgbe_hw *hw, u32 index);
251 s32 (*led_off)(struct txgbe_hw *hw, u32 index);
253 /* RAR, Multicast, VLAN */
254 s32 (*set_rar)(struct txgbe_hw *hw, u32 index, u8 *addr, u32 vmdq,
256 s32 (*set_uc_addr)(struct txgbe_hw *hw, u32 index, u8 *addr);
257 s32 (*clear_rar)(struct txgbe_hw *hw, u32 index);
258 s32 (*set_vmdq)(struct txgbe_hw *hw, u32 rar, u32 vmdq);
259 s32 (*clear_vmdq)(struct txgbe_hw *hw, u32 rar, u32 vmdq);
260 s32 (*init_rx_addrs)(struct txgbe_hw *hw);
261 s32 (*update_mc_addr_list)(struct txgbe_hw *hw, u8 *mc_addr_list,
263 txgbe_mc_addr_itr func, bool clear);
264 s32 (*clear_vfta)(struct txgbe_hw *hw);
265 s32 (*set_vfta)(struct txgbe_hw *hw, u32 vlan,
266 u32 vind, bool vlan_on, bool vlvf_bypass);
267 s32 (*set_vlvf)(struct txgbe_hw *hw, u32 vlan, u32 vind,
268 bool vlan_on, u32 *vfta_delta, u32 vfta,
270 s32 (*init_uta_tables)(struct txgbe_hw *hw);
271 void (*set_mac_anti_spoofing)(struct txgbe_hw *hw, bool enable, int vf);
272 void (*set_vlan_anti_spoofing)(struct txgbe_hw *hw,
273 bool enable, int vf);
274 s32 (*update_xcast_mode)(struct txgbe_hw *hw, int xcast_mode);
275 s32 (*set_rlpml)(struct txgbe_hw *hw, u16 max_size);
278 s32 (*fc_enable)(struct txgbe_hw *hw);
279 s32 (*setup_fc)(struct txgbe_hw *hw);
280 void (*fc_autoneg)(struct txgbe_hw *hw);
282 /* Manageability interface */
283 s32 (*set_fw_drv_ver)(struct txgbe_hw *hw, u8 maj, u8 min, u8 build,
284 u8 ver, u16 len, char *driver_ver);
285 s32 (*get_thermal_sensor_data)(struct txgbe_hw *hw);
286 s32 (*init_thermal_sensor_thresh)(struct txgbe_hw *hw);
287 void (*get_rtrup2tc)(struct txgbe_hw *hw, u8 *map);
288 void (*disable_rx)(struct txgbe_hw *hw);
289 void (*enable_rx)(struct txgbe_hw *hw);
290 void (*set_ethertype_anti_spoofing)(struct txgbe_hw *hw,
291 bool enable, int vf);
292 s32 (*dmac_update_tcs)(struct txgbe_hw *hw);
293 s32 (*dmac_config_tcs)(struct txgbe_hw *hw);
294 s32 (*dmac_config)(struct txgbe_hw *hw);
295 s32 (*setup_eee)(struct txgbe_hw *hw, bool enable_eee);
297 enum txgbe_mac_type type;
298 u8 perm_addr[ETH_ADDR_LEN];
299 u8 san_addr[ETH_ADDR_LEN];
300 /* prefix for World Wide Node Name (WWNN) */
302 /* prefix for World Wide Port Name (WWPN) */
309 u8 san_mac_rar_index;
310 u64 orig_autoc; /* cached value of AUTOC */
311 bool orig_link_settings_stored;
312 bool autotry_restart;
314 u32 max_link_up_time;
317 struct txgbe_phy_info {
318 u32 (*get_media_type)(struct txgbe_hw *hw);
319 s32 (*identify)(struct txgbe_hw *hw);
320 s32 (*identify_sfp)(struct txgbe_hw *hw);
321 s32 (*init)(struct txgbe_hw *hw);
322 s32 (*reset)(struct txgbe_hw *hw);
323 s32 (*read_reg)(struct txgbe_hw *hw, u32 reg_addr,
324 u32 device_type, u16 *phy_data);
325 s32 (*write_reg)(struct txgbe_hw *hw, u32 reg_addr,
326 u32 device_type, u16 phy_data);
327 s32 (*read_reg_mdi)(struct txgbe_hw *hw, u32 reg_addr,
328 u32 device_type, u16 *phy_data);
329 s32 (*write_reg_mdi)(struct txgbe_hw *hw, u32 reg_addr,
330 u32 device_type, u16 phy_data);
331 s32 (*setup_link)(struct txgbe_hw *hw);
332 s32 (*setup_internal_link)(struct txgbe_hw *hw);
333 s32 (*setup_link_speed)(struct txgbe_hw *hw, u32 speed,
334 bool autoneg_wait_to_complete);
335 s32 (*check_link)(struct txgbe_hw *hw, u32 *speed, bool *link_up);
336 s32 (*read_i2c_byte)(struct txgbe_hw *hw, u8 byte_offset,
337 u8 dev_addr, u8 *data);
338 s32 (*write_i2c_byte)(struct txgbe_hw *hw, u8 byte_offset,
339 u8 dev_addr, u8 data);
340 s32 (*read_i2c_sff8472)(struct txgbe_hw *hw, u8 byte_offset,
342 s32 (*read_i2c_eeprom)(struct txgbe_hw *hw, u8 byte_offset,
344 s32 (*write_i2c_eeprom)(struct txgbe_hw *hw, u8 byte_offset,
346 s32 (*check_overtemp)(struct txgbe_hw *hw);
347 s32 (*set_phy_power)(struct txgbe_hw *hw, bool on);
348 s32 (*handle_lasi)(struct txgbe_hw *hw);
349 s32 (*read_i2c_byte_unlocked)(struct txgbe_hw *hw, u8 offset, u8 addr,
351 s32 (*write_i2c_byte_unlocked)(struct txgbe_hw *hw, u8 offset, u8 addr,
354 enum txgbe_phy_type type;
357 enum txgbe_sfp_type sfp_type;
358 bool sfp_setup_needed;
361 u32 phy_semaphore_mask;
363 bool multispeed_fiber;
364 bool qsfp_shared_i2c_bus;
368 struct txgbe_mbx_info {
369 void (*init_params)(struct txgbe_hw *hw);
370 s32 (*read)(struct txgbe_hw *hw, u32 *msg, u16 size, u16 vf_number);
371 s32 (*write)(struct txgbe_hw *hw, u32 *msg, u16 size, u16 vf_number);
372 s32 (*read_posted)(struct txgbe_hw *hw, u32 *msg, u16 size,
374 s32 (*write_posted)(struct txgbe_hw *hw, u32 *msg, u16 size,
376 s32 (*check_for_msg)(struct txgbe_hw *hw, u16 mbx_id);
377 s32 (*check_for_ack)(struct txgbe_hw *hw, u16 mbx_id);
378 s32 (*check_for_rst)(struct txgbe_hw *hw, u16 mbx_id);
384 struct txgbe_mac_info mac;
385 struct txgbe_phy_info phy;
386 struct txgbe_link_info link;
387 struct txgbe_rom_info rom;
388 struct txgbe_flash_info flash;
389 struct txgbe_bus_info bus;
390 struct txgbe_mbx_info mbx;
393 u16 subsystem_device_id;
394 u16 subsystem_vendor_id;
396 bool allow_unsupported_sfp;
400 enum txgbe_reset_type {
407 #include "txgbe_regs.h"
408 #include "txgbe_dummy.h"
410 #endif /* _TXGBE_TYPE_H_ */