1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2015-2020
8 #define TXGBE_DCB_TC_MAX TXGBE_MAX_UP
9 #define TXGBE_DCB_UP_MAX TXGBE_MAX_UP
10 #define TXGBE_DCB_BWG_MAX TXGBE_MAX_UP
11 #define TXGBE_LINK_UP_TIME 90 /* 9.0 Seconds */
12 #define TXGBE_AUTO_NEG_TIME 45 /* 4.5 Seconds */
14 #define TXGBE_FRAME_SIZE_MAX (9728) /* Maximum frame size, +FCS */
15 #define TXGBE_FRAME_SIZE_DFT (1518) /* Default frame size, +FCS */
16 #define TXGBE_NUM_POOL (64)
17 #define TXGBE_PBTXSIZE_MAX 0x00028000 /* 160KB Packet Buffer */
18 #define TXGBE_MAX_FTQF_FILTERS 128
19 #define TXGBE_TXPKT_SIZE_MAX 0xA /* Max Tx Packet size */
20 #define TXGBE_MAX_UP 8
21 #define TXGBE_MAX_QP (128)
22 #define TXGBE_MAX_UTA 128
24 #define TXGBE_ALIGN 128 /* as intel did */
26 #include "txgbe_status.h"
27 #include "txgbe_osdep.h"
28 #include "txgbe_devids.h"
30 struct txgbe_thermal_diode_data {
36 struct txgbe_thermal_sensor_data {
37 struct txgbe_thermal_diode_data sensor[1];
40 /* Packet buffer allocation strategies */
42 PBA_STRATEGY_EQUAL = 0, /* Distribute PB space equally */
43 #define PBA_STRATEGY_EQUAL PBA_STRATEGY_EQUAL
44 PBA_STRATEGY_WEIGHTED = 1, /* Weight front half of TCs */
45 #define PBA_STRATEGY_WEIGHTED PBA_STRATEGY_WEIGHTED
48 /* Physical layer type */
49 #define TXGBE_PHYSICAL_LAYER_UNKNOWN 0
50 #define TXGBE_PHYSICAL_LAYER_10GBASE_T 0x00001
51 #define TXGBE_PHYSICAL_LAYER_1000BASE_T 0x00002
52 #define TXGBE_PHYSICAL_LAYER_100BASE_TX 0x00004
53 #define TXGBE_PHYSICAL_LAYER_SFP_PLUS_CU 0x00008
54 #define TXGBE_PHYSICAL_LAYER_10GBASE_LR 0x00010
55 #define TXGBE_PHYSICAL_LAYER_10GBASE_LRM 0x00020
56 #define TXGBE_PHYSICAL_LAYER_10GBASE_SR 0x00040
57 #define TXGBE_PHYSICAL_LAYER_10GBASE_KX4 0x00080
58 #define TXGBE_PHYSICAL_LAYER_10GBASE_CX4 0x00100
59 #define TXGBE_PHYSICAL_LAYER_1000BASE_KX 0x00200
60 #define TXGBE_PHYSICAL_LAYER_1000BASE_BX 0x00400
61 #define TXGBE_PHYSICAL_LAYER_10GBASE_KR 0x00800
62 #define TXGBE_PHYSICAL_LAYER_10GBASE_XAUI 0x01000
63 #define TXGBE_PHYSICAL_LAYER_SFP_ACTIVE_DA 0x02000
64 #define TXGBE_PHYSICAL_LAYER_1000BASE_SX 0x04000
65 #define TXGBE_PHYSICAL_LAYER_10BASE_T 0x08000
66 #define TXGBE_PHYSICAL_LAYER_2500BASE_KX 0x10000
68 #define TXGBE_ATR_HASH_MASK 0x7fff
70 enum txgbe_eeprom_type {
71 txgbe_eeprom_unknown = 0,
74 txgbe_eeprom_none /* No NVM support */
78 txgbe_mac_unknown = 0,
85 txgbe_phy_unknown = 0,
95 txgbe_phy_sfp_tyco_passive,
96 txgbe_phy_sfp_unknown_passive,
97 txgbe_phy_sfp_unknown_active,
100 txgbe_phy_sfp_ftl_active,
101 txgbe_phy_sfp_unknown,
103 txgbe_phy_qsfp_unknown_passive,
104 txgbe_phy_qsfp_unknown_active,
105 txgbe_phy_qsfp_intel,
106 txgbe_phy_qsfp_unknown,
107 txgbe_phy_sfp_unsupported, /* Enforce bit set with unsupported module */
114 * SFP+ module type IDs:
121 * 3 SFP_DA_CU_CORE0 - chip-specific
122 * 4 SFP_DA_CU_CORE1 - chip-specific
123 * 5 SFP_SR/LR_CORE0 - chip-specific
124 * 6 SFP_SR/LR_CORE1 - chip-specific
126 enum txgbe_sfp_type {
127 txgbe_sfp_type_unknown = 0,
128 txgbe_sfp_type_da_cu,
131 txgbe_sfp_type_da_cu_core0,
132 txgbe_sfp_type_da_cu_core1,
133 txgbe_sfp_type_srlr_core0,
134 txgbe_sfp_type_srlr_core1,
135 txgbe_sfp_type_da_act_lmt_core0,
136 txgbe_sfp_type_da_act_lmt_core1,
137 txgbe_sfp_type_1g_cu_core0,
138 txgbe_sfp_type_1g_cu_core1,
139 txgbe_sfp_type_1g_sx_core0,
140 txgbe_sfp_type_1g_sx_core1,
141 txgbe_sfp_type_1g_lx_core0,
142 txgbe_sfp_type_1g_lx_core1,
143 txgbe_sfp_type_not_present = 0xFFFE,
144 txgbe_sfp_type_not_known = 0xFFFF
147 enum txgbe_media_type {
148 txgbe_media_type_unknown = 0,
149 txgbe_media_type_fiber,
150 txgbe_media_type_fiber_qsfp,
151 txgbe_media_type_copper,
152 txgbe_media_type_backplane,
153 txgbe_media_type_cx4,
154 txgbe_media_type_virtual
157 /* Flow Control Settings */
166 /* Smart Speed Settings */
167 #define TXGBE_SMARTSPEED_MAX_RETRIES 3
168 enum txgbe_smart_speed {
169 txgbe_smart_speed_auto = 0,
170 txgbe_smart_speed_on,
171 txgbe_smart_speed_off
175 enum txgbe_bus_type {
176 txgbe_bus_type_unknown = 0,
179 txgbe_bus_type_pci_express,
180 txgbe_bus_type_internal,
181 txgbe_bus_type_reserved
185 enum txgbe_bus_speed {
186 txgbe_bus_speed_unknown = 0,
187 txgbe_bus_speed_33 = 33,
188 txgbe_bus_speed_66 = 66,
189 txgbe_bus_speed_100 = 100,
190 txgbe_bus_speed_120 = 120,
191 txgbe_bus_speed_133 = 133,
192 txgbe_bus_speed_2500 = 2500,
193 txgbe_bus_speed_5000 = 5000,
194 txgbe_bus_speed_8000 = 8000,
195 txgbe_bus_speed_reserved
199 enum txgbe_bus_width {
200 txgbe_bus_width_unknown = 0,
201 txgbe_bus_width_pcie_x1 = 1,
202 txgbe_bus_width_pcie_x2 = 2,
203 txgbe_bus_width_pcie_x4 = 4,
204 txgbe_bus_width_pcie_x8 = 8,
205 txgbe_bus_width_32 = 32,
206 txgbe_bus_width_64 = 64,
207 txgbe_bus_width_reserved
212 struct txgbe_addr_filter_info {
216 u32 overflow_promisc;
217 bool user_set_promisc;
221 struct txgbe_bus_info {
222 s32 (*get_bus_info)(struct txgbe_hw *hw);
223 void (*set_lan_id)(struct txgbe_hw *hw);
225 enum txgbe_bus_speed speed;
226 enum txgbe_bus_width width;
227 enum txgbe_bus_type type;
234 /* Flow control parameters */
235 struct txgbe_fc_info {
236 u32 high_water[TXGBE_DCB_TC_MAX]; /* Flow Ctrl High-water */
237 u32 low_water[TXGBE_DCB_TC_MAX]; /* Flow Ctrl Low-water */
238 u16 pause_time; /* Flow Control Pause timer */
239 bool send_xon; /* Flow control send XON */
240 bool strict_ieee; /* Strict IEEE mode */
241 bool disable_fc_autoneg; /* Do not autonegotiate FC */
242 bool fc_was_autonegged; /* Is current_mode the result of autonegging? */
243 enum txgbe_fc_mode current_mode; /* FC mode in effect */
244 enum txgbe_fc_mode requested_mode; /* FC mode requested by caller */
247 /* Statistics counters collected by the MAC */
249 struct txgbe_pb_stats {
250 u64 tx_pb_xon_packets;
251 u64 rx_pb_xon_packets;
252 u64 tx_pb_xoff_packets;
253 u64 rx_pb_xoff_packets;
255 u64 rx_pb_mbuf_alloc_errors;
256 u64 tx_pb_xon2off_packets;
260 struct txgbe_qp_stats {
265 u64 rx_qp_mc_packets;
268 struct txgbe_hw_stats {
270 u64 mng_bmc2host_packets;
271 u64 mng_host2bmc_packets;
278 u64 rx_total_packets;
279 u64 tx_total_packets;
280 u64 rx_total_missed_packets;
281 u64 rx_broadcast_packets;
282 u64 tx_broadcast_packets;
283 u64 rx_multicast_packets;
284 u64 tx_multicast_packets;
285 u64 rx_management_packets;
286 u64 tx_management_packets;
287 u64 rx_management_dropped;
292 u64 rx_illegal_byte_errors;
294 u64 rx_mac_short_packet_dropped;
295 u64 rx_length_errors;
296 u64 rx_undersize_errors;
297 u64 rx_fragment_errors;
298 u64 rx_oversize_errors;
299 u64 rx_jabber_errors;
300 u64 rx_l3_l4_xsum_error;
301 u64 mac_local_errors;
302 u64 mac_remote_errors;
305 u64 flow_director_added_filters;
306 u64 flow_director_removed_filters;
307 u64 flow_director_filter_add_errors;
308 u64 flow_director_filter_remove_errors;
309 u64 flow_director_matched_filters;
310 u64 flow_director_missed_filters;
313 u64 rx_fcoe_crc_errors;
314 u64 rx_fcoe_mbuf_allocation_errors;
321 u64 rx_fcoe_no_ddp_ext_buff;
324 u64 tx_macsec_pkts_untagged;
325 u64 tx_macsec_pkts_encrypted;
326 u64 tx_macsec_pkts_protected;
327 u64 tx_macsec_octets_encrypted;
328 u64 tx_macsec_octets_protected;
329 u64 rx_macsec_pkts_untagged;
330 u64 rx_macsec_pkts_badtag;
331 u64 rx_macsec_pkts_nosci;
332 u64 rx_macsec_pkts_unknownsci;
333 u64 rx_macsec_octets_decrypted;
334 u64 rx_macsec_octets_validated;
335 u64 rx_macsec_sc_pkts_unchecked;
336 u64 rx_macsec_sc_pkts_delayed;
337 u64 rx_macsec_sc_pkts_late;
338 u64 rx_macsec_sa_pkts_ok;
339 u64 rx_macsec_sa_pkts_invalid;
340 u64 rx_macsec_sa_pkts_notvalid;
341 u64 rx_macsec_sa_pkts_unusedsa;
342 u64 rx_macsec_sa_pkts_notusingsa;
345 u64 rx_size_64_packets;
346 u64 rx_size_65_to_127_packets;
347 u64 rx_size_128_to_255_packets;
348 u64 rx_size_256_to_511_packets;
349 u64 rx_size_512_to_1023_packets;
350 u64 rx_size_1024_to_max_packets;
351 u64 tx_size_64_packets;
352 u64 tx_size_65_to_127_packets;
353 u64 tx_size_128_to_255_packets;
354 u64 tx_size_256_to_511_packets;
355 u64 tx_size_512_to_1023_packets;
356 u64 tx_size_1024_to_max_packets;
370 u64 rx_up_drop_packets;
372 u64 tx_up_xon_packets;
373 u64 rx_up_xon_packets;
374 u64 tx_up_xoff_packets;
375 u64 rx_up_xoff_packets;
377 u64 rx_up_mbuf_alloc_errors;
378 u64 tx_up_xon2off_packets;
387 u64 rx_qp_mc_packets;
392 /* iterator type for walking multicast address lists */
393 typedef u8* (*txgbe_mc_addr_itr) (struct txgbe_hw *hw, u8 **mc_addr_ptr,
396 struct txgbe_link_info {
397 s32 (*read_link)(struct txgbe_hw *hw, u8 addr, u16 reg, u16 *val);
398 s32 (*read_link_unlocked)(struct txgbe_hw *hw, u8 addr, u16 reg,
400 s32 (*write_link)(struct txgbe_hw *hw, u8 addr, u16 reg, u16 val);
401 s32 (*write_link_unlocked)(struct txgbe_hw *hw, u8 addr, u16 reg,
407 struct txgbe_rom_info {
408 s32 (*init_params)(struct txgbe_hw *hw);
409 s32 (*read16)(struct txgbe_hw *hw, u32 offset, u16 *data);
410 s32 (*readw_sw)(struct txgbe_hw *hw, u32 offset, u16 *data);
411 s32 (*readw_buffer)(struct txgbe_hw *hw, u32 offset, u32 words,
413 s32 (*read32)(struct txgbe_hw *hw, u32 addr, u32 *data);
414 s32 (*read_buffer)(struct txgbe_hw *hw, u32 addr, u32 len, void *data);
415 s32 (*write16)(struct txgbe_hw *hw, u32 offset, u16 data);
416 s32 (*writew_sw)(struct txgbe_hw *hw, u32 offset, u16 data);
417 s32 (*writew_buffer)(struct txgbe_hw *hw, u32 offset, u32 words,
419 s32 (*write32)(struct txgbe_hw *hw, u32 addr, u32 data);
420 s32 (*write_buffer)(struct txgbe_hw *hw, u32 addr, u32 len, void *data);
421 s32 (*validate_checksum)(struct txgbe_hw *hw, u16 *checksum_val);
422 s32 (*update_checksum)(struct txgbe_hw *hw);
423 s32 (*calc_checksum)(struct txgbe_hw *hw);
425 enum txgbe_eeprom_type type;
435 struct txgbe_flash_info {
441 #define TXGBE_FLAGS_DOUBLE_RESET_REQUIRED 0x01
442 struct txgbe_mac_info {
443 s32 (*init_hw)(struct txgbe_hw *hw);
444 s32 (*reset_hw)(struct txgbe_hw *hw);
445 s32 (*start_hw)(struct txgbe_hw *hw);
446 s32 (*stop_hw)(struct txgbe_hw *hw);
447 s32 (*clear_hw_cntrs)(struct txgbe_hw *hw);
448 s32 (*get_mac_addr)(struct txgbe_hw *hw, u8 *mac_addr);
449 s32 (*get_san_mac_addr)(struct txgbe_hw *hw, u8 *san_mac_addr);
450 s32 (*set_san_mac_addr)(struct txgbe_hw *hw, u8 *san_mac_addr);
451 s32 (*get_device_caps)(struct txgbe_hw *hw, u16 *device_caps);
452 s32 (*get_wwn_prefix)(struct txgbe_hw *hw, u16 *wwnn_prefix,
454 s32 (*setup_sfp)(struct txgbe_hw *hw);
455 s32 (*enable_rx_dma)(struct txgbe_hw *hw, u32 regval);
456 s32 (*disable_sec_rx_path)(struct txgbe_hw *hw);
457 s32 (*enable_sec_rx_path)(struct txgbe_hw *hw);
458 s32 (*disable_sec_tx_path)(struct txgbe_hw *hw);
459 s32 (*enable_sec_tx_path)(struct txgbe_hw *hw);
460 s32 (*acquire_swfw_sync)(struct txgbe_hw *hw, u32 mask);
461 void (*release_swfw_sync)(struct txgbe_hw *hw, u32 mask);
462 u64 (*autoc_read)(struct txgbe_hw *hw);
463 void (*autoc_write)(struct txgbe_hw *hw, u64 value);
464 s32 (*prot_autoc_read)(struct txgbe_hw *hw, bool *locked, u64 *value);
465 s32 (*prot_autoc_write)(struct txgbe_hw *hw, bool locked, u64 value);
466 s32 (*negotiate_api_version)(struct txgbe_hw *hw, int api);
469 void (*disable_tx_laser)(struct txgbe_hw *hw);
470 void (*enable_tx_laser)(struct txgbe_hw *hw);
471 void (*flap_tx_laser)(struct txgbe_hw *hw);
472 s32 (*setup_link)(struct txgbe_hw *hw, u32 speed,
473 bool autoneg_wait_to_complete);
474 s32 (*setup_mac_link)(struct txgbe_hw *hw, u32 speed,
475 bool autoneg_wait_to_complete);
476 s32 (*check_link)(struct txgbe_hw *hw, u32 *speed,
477 bool *link_up, bool link_up_wait_to_complete);
478 s32 (*get_link_capabilities)(struct txgbe_hw *hw,
479 u32 *speed, bool *autoneg);
480 void (*set_rate_select_speed)(struct txgbe_hw *hw, u32 speed);
482 /* Packet Buffer manipulation */
483 void (*setup_pba)(struct txgbe_hw *hw, int num_pb, u32 headroom,
487 s32 (*led_on)(struct txgbe_hw *hw, u32 index);
488 s32 (*led_off)(struct txgbe_hw *hw, u32 index);
490 /* RAR, Multicast, VLAN */
491 s32 (*set_rar)(struct txgbe_hw *hw, u32 index, u8 *addr, u32 vmdq,
493 s32 (*set_uc_addr)(struct txgbe_hw *hw, u32 index, u8 *addr);
494 s32 (*clear_rar)(struct txgbe_hw *hw, u32 index);
495 s32 (*set_vmdq)(struct txgbe_hw *hw, u32 rar, u32 vmdq);
496 s32 (*clear_vmdq)(struct txgbe_hw *hw, u32 rar, u32 vmdq);
497 s32 (*init_rx_addrs)(struct txgbe_hw *hw);
498 s32 (*update_mc_addr_list)(struct txgbe_hw *hw, u8 *mc_addr_list,
500 txgbe_mc_addr_itr func, bool clear);
501 s32 (*clear_vfta)(struct txgbe_hw *hw);
502 s32 (*set_vfta)(struct txgbe_hw *hw, u32 vlan,
503 u32 vind, bool vlan_on, bool vlvf_bypass);
504 s32 (*set_vlvf)(struct txgbe_hw *hw, u32 vlan, u32 vind,
505 bool vlan_on, u32 *vfta_delta, u32 vfta,
507 s32 (*init_uta_tables)(struct txgbe_hw *hw);
508 void (*set_mac_anti_spoofing)(struct txgbe_hw *hw, bool enable, int vf);
509 void (*set_vlan_anti_spoofing)(struct txgbe_hw *hw,
510 bool enable, int vf);
511 s32 (*update_xcast_mode)(struct txgbe_hw *hw, int xcast_mode);
512 s32 (*set_rlpml)(struct txgbe_hw *hw, u16 max_size);
515 s32 (*fc_enable)(struct txgbe_hw *hw);
516 s32 (*setup_fc)(struct txgbe_hw *hw);
517 void (*fc_autoneg)(struct txgbe_hw *hw);
519 /* Manageability interface */
520 s32 (*set_fw_drv_ver)(struct txgbe_hw *hw, u8 maj, u8 min, u8 build,
521 u8 ver, u16 len, const char *driver_ver);
522 s32 (*get_thermal_sensor_data)(struct txgbe_hw *hw);
523 s32 (*init_thermal_sensor_thresh)(struct txgbe_hw *hw);
524 void (*get_rtrup2tc)(struct txgbe_hw *hw, u8 *map);
525 void (*disable_rx)(struct txgbe_hw *hw);
526 void (*enable_rx)(struct txgbe_hw *hw);
527 void (*set_ethertype_anti_spoofing)(struct txgbe_hw *hw,
528 bool enable, int vf);
529 s32 (*dmac_update_tcs)(struct txgbe_hw *hw);
530 s32 (*dmac_config_tcs)(struct txgbe_hw *hw);
531 s32 (*dmac_config)(struct txgbe_hw *hw);
532 s32 (*setup_eee)(struct txgbe_hw *hw, bool enable_eee);
534 enum txgbe_mac_type type;
535 u8 addr[ETH_ADDR_LEN];
536 u8 perm_addr[ETH_ADDR_LEN];
537 u8 san_addr[ETH_ADDR_LEN];
538 /* prefix for World Wide Node Name (WWNN) */
540 /* prefix for World Wide Port Name (WWPN) */
542 #define TXGBE_MAX_MTA 128
543 u32 mta_shadow[TXGBE_MAX_MTA];
551 u8 san_mac_rar_index;
552 bool get_link_status;
553 u64 orig_autoc; /* cached value of AUTOC */
554 bool orig_link_settings_stored;
555 bool autotry_restart;
557 struct txgbe_thermal_sensor_data thermal_sensor_data;
559 u32 max_link_up_time;
562 struct txgbe_phy_info {
563 u32 (*get_media_type)(struct txgbe_hw *hw);
564 s32 (*identify)(struct txgbe_hw *hw);
565 s32 (*identify_sfp)(struct txgbe_hw *hw);
566 s32 (*init)(struct txgbe_hw *hw);
567 s32 (*reset)(struct txgbe_hw *hw);
568 s32 (*read_reg)(struct txgbe_hw *hw, u32 reg_addr,
569 u32 device_type, u16 *phy_data);
570 s32 (*write_reg)(struct txgbe_hw *hw, u32 reg_addr,
571 u32 device_type, u16 phy_data);
572 s32 (*read_reg_mdi)(struct txgbe_hw *hw, u32 reg_addr,
573 u32 device_type, u16 *phy_data);
574 s32 (*write_reg_mdi)(struct txgbe_hw *hw, u32 reg_addr,
575 u32 device_type, u16 phy_data);
576 s32 (*setup_link)(struct txgbe_hw *hw);
577 s32 (*setup_internal_link)(struct txgbe_hw *hw);
578 s32 (*setup_link_speed)(struct txgbe_hw *hw, u32 speed,
579 bool autoneg_wait_to_complete);
580 s32 (*check_link)(struct txgbe_hw *hw, u32 *speed, bool *link_up);
581 s32 (*read_i2c_byte)(struct txgbe_hw *hw, u8 byte_offset,
582 u8 dev_addr, u8 *data);
583 s32 (*write_i2c_byte)(struct txgbe_hw *hw, u8 byte_offset,
584 u8 dev_addr, u8 data);
585 s32 (*read_i2c_sff8472)(struct txgbe_hw *hw, u8 byte_offset,
587 s32 (*read_i2c_eeprom)(struct txgbe_hw *hw, u8 byte_offset,
589 s32 (*write_i2c_eeprom)(struct txgbe_hw *hw, u8 byte_offset,
591 s32 (*check_overtemp)(struct txgbe_hw *hw);
592 s32 (*set_phy_power)(struct txgbe_hw *hw, bool on);
593 s32 (*handle_lasi)(struct txgbe_hw *hw);
594 s32 (*read_i2c_byte_unlocked)(struct txgbe_hw *hw, u8 offset, u8 addr,
596 s32 (*write_i2c_byte_unlocked)(struct txgbe_hw *hw, u8 offset, u8 addr,
599 enum txgbe_phy_type type;
602 enum txgbe_sfp_type sfp_type;
603 bool sfp_setup_needed;
606 u32 phy_semaphore_mask;
608 u32 autoneg_advertised;
609 u32 speeds_supported;
610 enum txgbe_smart_speed smart_speed;
611 bool smart_speed_active;
612 bool multispeed_fiber;
613 bool qsfp_shared_i2c_bus;
618 struct txgbe_mbx_stats {
627 struct txgbe_mbx_info {
628 void (*init_params)(struct txgbe_hw *hw);
629 s32 (*read)(struct txgbe_hw *hw, u32 *msg, u16 size, u16 vf_number);
630 s32 (*write)(struct txgbe_hw *hw, u32 *msg, u16 size, u16 vf_number);
631 s32 (*read_posted)(struct txgbe_hw *hw, u32 *msg, u16 size,
633 s32 (*write_posted)(struct txgbe_hw *hw, u32 *msg, u16 size,
635 s32 (*check_for_msg)(struct txgbe_hw *hw, u16 mbx_id);
636 s32 (*check_for_ack)(struct txgbe_hw *hw, u16 mbx_id);
637 s32 (*check_for_rst)(struct txgbe_hw *hw, u16 mbx_id);
639 struct txgbe_mbx_stats stats;
656 struct txgbe_mac_info mac;
657 struct txgbe_addr_filter_info addr_ctrl;
658 struct txgbe_fc_info fc;
659 struct txgbe_phy_info phy;
660 struct txgbe_link_info link;
661 struct txgbe_rom_info rom;
662 struct txgbe_flash_info flash;
663 struct txgbe_bus_info bus;
664 struct txgbe_mbx_info mbx;
667 u16 subsystem_device_id;
668 u16 subsystem_vendor_id;
670 bool adapter_stopped;
671 bool allow_unsupported_sfp;
672 bool need_crosstalk_fix;
680 enum txgbe_link_status {
681 TXGBE_LINK_STATUS_NONE = 0,
682 TXGBE_LINK_STATUS_KX,
683 TXGBE_LINK_STATUS_KX4
685 enum txgbe_reset_type {
691 u32 q_rx_regs[128 * 4];
692 u32 q_tx_regs[128 * 4];
699 u64 rx_qp_mc_packets;
700 } qp_last[TXGBE_MAX_QP];
703 #include "txgbe_regs.h"
704 #include "txgbe_dummy.h"
706 #endif /* _TXGBE_TYPE_H_ */