1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2015-2020
8 #define TXGBE_LINK_UP_TIME 90 /* 9.0 Seconds */
9 #define TXGBE_AUTO_NEG_TIME 45 /* 4.5 Seconds */
11 #define TXGBE_MAX_UTA 128
13 #define TXGBE_ALIGN 128 /* as intel did */
15 #include "txgbe_status.h"
16 #include "txgbe_osdep.h"
17 #include "txgbe_devids.h"
19 /* Physical layer type */
20 #define TXGBE_PHYSICAL_LAYER_UNKNOWN 0
21 #define TXGBE_PHYSICAL_LAYER_10GBASE_T 0x00001
22 #define TXGBE_PHYSICAL_LAYER_1000BASE_T 0x00002
23 #define TXGBE_PHYSICAL_LAYER_100BASE_TX 0x00004
24 #define TXGBE_PHYSICAL_LAYER_SFP_PLUS_CU 0x00008
25 #define TXGBE_PHYSICAL_LAYER_10GBASE_LR 0x00010
26 #define TXGBE_PHYSICAL_LAYER_10GBASE_LRM 0x00020
27 #define TXGBE_PHYSICAL_LAYER_10GBASE_SR 0x00040
28 #define TXGBE_PHYSICAL_LAYER_10GBASE_KX4 0x00080
29 #define TXGBE_PHYSICAL_LAYER_10GBASE_CX4 0x00100
30 #define TXGBE_PHYSICAL_LAYER_1000BASE_KX 0x00200
31 #define TXGBE_PHYSICAL_LAYER_1000BASE_BX 0x00400
32 #define TXGBE_PHYSICAL_LAYER_10GBASE_KR 0x00800
33 #define TXGBE_PHYSICAL_LAYER_10GBASE_XAUI 0x01000
34 #define TXGBE_PHYSICAL_LAYER_SFP_ACTIVE_DA 0x02000
35 #define TXGBE_PHYSICAL_LAYER_1000BASE_SX 0x04000
36 #define TXGBE_PHYSICAL_LAYER_10BASE_T 0x08000
37 #define TXGBE_PHYSICAL_LAYER_2500BASE_KX 0x10000
39 enum txgbe_eeprom_type {
40 txgbe_eeprom_unknown = 0,
43 txgbe_eeprom_none /* No NVM support */
47 txgbe_mac_unknown = 0,
54 txgbe_phy_unknown = 0,
64 txgbe_phy_sfp_tyco_passive,
65 txgbe_phy_sfp_unknown_passive,
66 txgbe_phy_sfp_unknown_active,
69 txgbe_phy_sfp_ftl_active,
70 txgbe_phy_sfp_unknown,
72 txgbe_phy_qsfp_unknown_passive,
73 txgbe_phy_qsfp_unknown_active,
75 txgbe_phy_qsfp_unknown,
76 txgbe_phy_sfp_unsupported, /* Enforce bit set with unsupported module */
83 * SFP+ module type IDs:
90 * 3 SFP_DA_CU_CORE0 - chip-specific
91 * 4 SFP_DA_CU_CORE1 - chip-specific
92 * 5 SFP_SR/LR_CORE0 - chip-specific
93 * 6 SFP_SR/LR_CORE1 - chip-specific
96 txgbe_sfp_type_unknown = 0,
100 txgbe_sfp_type_da_cu_core0,
101 txgbe_sfp_type_da_cu_core1,
102 txgbe_sfp_type_srlr_core0,
103 txgbe_sfp_type_srlr_core1,
104 txgbe_sfp_type_da_act_lmt_core0,
105 txgbe_sfp_type_da_act_lmt_core1,
106 txgbe_sfp_type_1g_cu_core0,
107 txgbe_sfp_type_1g_cu_core1,
108 txgbe_sfp_type_1g_sx_core0,
109 txgbe_sfp_type_1g_sx_core1,
110 txgbe_sfp_type_1g_lx_core0,
111 txgbe_sfp_type_1g_lx_core1,
112 txgbe_sfp_type_not_present = 0xFFFE,
113 txgbe_sfp_type_not_known = 0xFFFF
116 enum txgbe_media_type {
117 txgbe_media_type_unknown = 0,
118 txgbe_media_type_fiber,
119 txgbe_media_type_fiber_qsfp,
120 txgbe_media_type_copper,
121 txgbe_media_type_backplane,
122 txgbe_media_type_cx4,
123 txgbe_media_type_virtual
127 /* Smart Speed Settings */
128 #define TXGBE_SMARTSPEED_MAX_RETRIES 3
129 enum txgbe_smart_speed {
130 txgbe_smart_speed_auto = 0,
131 txgbe_smart_speed_on,
132 txgbe_smart_speed_off
136 enum txgbe_bus_type {
137 txgbe_bus_type_unknown = 0,
140 txgbe_bus_type_pci_express,
141 txgbe_bus_type_internal,
142 txgbe_bus_type_reserved
146 enum txgbe_bus_speed {
147 txgbe_bus_speed_unknown = 0,
148 txgbe_bus_speed_33 = 33,
149 txgbe_bus_speed_66 = 66,
150 txgbe_bus_speed_100 = 100,
151 txgbe_bus_speed_120 = 120,
152 txgbe_bus_speed_133 = 133,
153 txgbe_bus_speed_2500 = 2500,
154 txgbe_bus_speed_5000 = 5000,
155 txgbe_bus_speed_8000 = 8000,
156 txgbe_bus_speed_reserved
160 enum txgbe_bus_width {
161 txgbe_bus_width_unknown = 0,
162 txgbe_bus_width_pcie_x1 = 1,
163 txgbe_bus_width_pcie_x2 = 2,
164 txgbe_bus_width_pcie_x4 = 4,
165 txgbe_bus_width_pcie_x8 = 8,
166 txgbe_bus_width_32 = 32,
167 txgbe_bus_width_64 = 64,
168 txgbe_bus_width_reserved
173 struct txgbe_addr_filter_info {
177 u32 overflow_promisc;
178 bool user_set_promisc;
182 struct txgbe_bus_info {
183 s32 (*get_bus_info)(struct txgbe_hw *hw);
184 void (*set_lan_id)(struct txgbe_hw *hw);
186 enum txgbe_bus_speed speed;
187 enum txgbe_bus_width width;
188 enum txgbe_bus_type type;
195 /* iterator type for walking multicast address lists */
196 typedef u8* (*txgbe_mc_addr_itr) (struct txgbe_hw *hw, u8 **mc_addr_ptr,
199 struct txgbe_link_info {
200 s32 (*read_link)(struct txgbe_hw *hw, u8 addr, u16 reg, u16 *val);
201 s32 (*read_link_unlocked)(struct txgbe_hw *hw, u8 addr, u16 reg,
203 s32 (*write_link)(struct txgbe_hw *hw, u8 addr, u16 reg, u16 val);
204 s32 (*write_link_unlocked)(struct txgbe_hw *hw, u8 addr, u16 reg,
210 struct txgbe_rom_info {
211 s32 (*init_params)(struct txgbe_hw *hw);
212 s32 (*read16)(struct txgbe_hw *hw, u32 offset, u16 *data);
213 s32 (*readw_sw)(struct txgbe_hw *hw, u32 offset, u16 *data);
214 s32 (*readw_buffer)(struct txgbe_hw *hw, u32 offset, u32 words,
216 s32 (*read32)(struct txgbe_hw *hw, u32 addr, u32 *data);
217 s32 (*read_buffer)(struct txgbe_hw *hw, u32 addr, u32 len, void *data);
218 s32 (*write16)(struct txgbe_hw *hw, u32 offset, u16 data);
219 s32 (*writew_sw)(struct txgbe_hw *hw, u32 offset, u16 data);
220 s32 (*writew_buffer)(struct txgbe_hw *hw, u32 offset, u32 words,
222 s32 (*write32)(struct txgbe_hw *hw, u32 addr, u32 data);
223 s32 (*write_buffer)(struct txgbe_hw *hw, u32 addr, u32 len, void *data);
224 s32 (*validate_checksum)(struct txgbe_hw *hw, u16 *checksum_val);
225 s32 (*update_checksum)(struct txgbe_hw *hw);
226 s32 (*calc_checksum)(struct txgbe_hw *hw);
228 enum txgbe_eeprom_type type;
238 struct txgbe_flash_info {
244 #define TXGBE_FLAGS_DOUBLE_RESET_REQUIRED 0x01
245 struct txgbe_mac_info {
246 s32 (*init_hw)(struct txgbe_hw *hw);
247 s32 (*reset_hw)(struct txgbe_hw *hw);
248 s32 (*start_hw)(struct txgbe_hw *hw);
249 s32 (*stop_hw)(struct txgbe_hw *hw);
250 s32 (*clear_hw_cntrs)(struct txgbe_hw *hw);
251 s32 (*get_mac_addr)(struct txgbe_hw *hw, u8 *mac_addr);
252 s32 (*get_san_mac_addr)(struct txgbe_hw *hw, u8 *san_mac_addr);
253 s32 (*set_san_mac_addr)(struct txgbe_hw *hw, u8 *san_mac_addr);
254 s32 (*get_device_caps)(struct txgbe_hw *hw, u16 *device_caps);
255 s32 (*get_wwn_prefix)(struct txgbe_hw *hw, u16 *wwnn_prefix,
257 s32 (*setup_sfp)(struct txgbe_hw *hw);
258 s32 (*enable_rx_dma)(struct txgbe_hw *hw, u32 regval);
259 s32 (*disable_sec_rx_path)(struct txgbe_hw *hw);
260 s32 (*enable_sec_rx_path)(struct txgbe_hw *hw);
261 s32 (*disable_sec_tx_path)(struct txgbe_hw *hw);
262 s32 (*enable_sec_tx_path)(struct txgbe_hw *hw);
263 s32 (*acquire_swfw_sync)(struct txgbe_hw *hw, u32 mask);
264 void (*release_swfw_sync)(struct txgbe_hw *hw, u32 mask);
265 u64 (*autoc_read)(struct txgbe_hw *hw);
266 void (*autoc_write)(struct txgbe_hw *hw, u64 value);
267 s32 (*prot_autoc_read)(struct txgbe_hw *hw, bool *locked, u64 *value);
268 s32 (*prot_autoc_write)(struct txgbe_hw *hw, bool locked, u64 value);
269 s32 (*negotiate_api_version)(struct txgbe_hw *hw, int api);
272 void (*disable_tx_laser)(struct txgbe_hw *hw);
273 void (*enable_tx_laser)(struct txgbe_hw *hw);
274 void (*flap_tx_laser)(struct txgbe_hw *hw);
275 s32 (*setup_link)(struct txgbe_hw *hw, u32 speed,
276 bool autoneg_wait_to_complete);
277 s32 (*setup_mac_link)(struct txgbe_hw *hw, u32 speed,
278 bool autoneg_wait_to_complete);
279 s32 (*check_link)(struct txgbe_hw *hw, u32 *speed,
280 bool *link_up, bool link_up_wait_to_complete);
281 s32 (*get_link_capabilities)(struct txgbe_hw *hw,
282 u32 *speed, bool *autoneg);
283 void (*set_rate_select_speed)(struct txgbe_hw *hw, u32 speed);
285 /* Packet Buffer manipulation */
286 void (*setup_pba)(struct txgbe_hw *hw, int num_pb, u32 headroom,
290 s32 (*led_on)(struct txgbe_hw *hw, u32 index);
291 s32 (*led_off)(struct txgbe_hw *hw, u32 index);
293 /* RAR, Multicast, VLAN */
294 s32 (*set_rar)(struct txgbe_hw *hw, u32 index, u8 *addr, u32 vmdq,
296 s32 (*set_uc_addr)(struct txgbe_hw *hw, u32 index, u8 *addr);
297 s32 (*clear_rar)(struct txgbe_hw *hw, u32 index);
298 s32 (*set_vmdq)(struct txgbe_hw *hw, u32 rar, u32 vmdq);
299 s32 (*clear_vmdq)(struct txgbe_hw *hw, u32 rar, u32 vmdq);
300 s32 (*init_rx_addrs)(struct txgbe_hw *hw);
301 s32 (*update_mc_addr_list)(struct txgbe_hw *hw, u8 *mc_addr_list,
303 txgbe_mc_addr_itr func, bool clear);
304 s32 (*clear_vfta)(struct txgbe_hw *hw);
305 s32 (*set_vfta)(struct txgbe_hw *hw, u32 vlan,
306 u32 vind, bool vlan_on, bool vlvf_bypass);
307 s32 (*set_vlvf)(struct txgbe_hw *hw, u32 vlan, u32 vind,
308 bool vlan_on, u32 *vfta_delta, u32 vfta,
310 s32 (*init_uta_tables)(struct txgbe_hw *hw);
311 void (*set_mac_anti_spoofing)(struct txgbe_hw *hw, bool enable, int vf);
312 void (*set_vlan_anti_spoofing)(struct txgbe_hw *hw,
313 bool enable, int vf);
314 s32 (*update_xcast_mode)(struct txgbe_hw *hw, int xcast_mode);
315 s32 (*set_rlpml)(struct txgbe_hw *hw, u16 max_size);
318 s32 (*fc_enable)(struct txgbe_hw *hw);
319 s32 (*setup_fc)(struct txgbe_hw *hw);
320 void (*fc_autoneg)(struct txgbe_hw *hw);
322 /* Manageability interface */
323 s32 (*set_fw_drv_ver)(struct txgbe_hw *hw, u8 maj, u8 min, u8 build,
324 u8 ver, u16 len, char *driver_ver);
325 s32 (*get_thermal_sensor_data)(struct txgbe_hw *hw);
326 s32 (*init_thermal_sensor_thresh)(struct txgbe_hw *hw);
327 void (*get_rtrup2tc)(struct txgbe_hw *hw, u8 *map);
328 void (*disable_rx)(struct txgbe_hw *hw);
329 void (*enable_rx)(struct txgbe_hw *hw);
330 void (*set_ethertype_anti_spoofing)(struct txgbe_hw *hw,
331 bool enable, int vf);
332 s32 (*dmac_update_tcs)(struct txgbe_hw *hw);
333 s32 (*dmac_config_tcs)(struct txgbe_hw *hw);
334 s32 (*dmac_config)(struct txgbe_hw *hw);
335 s32 (*setup_eee)(struct txgbe_hw *hw, bool enable_eee);
337 enum txgbe_mac_type type;
338 u8 addr[ETH_ADDR_LEN];
339 u8 perm_addr[ETH_ADDR_LEN];
340 u8 san_addr[ETH_ADDR_LEN];
341 /* prefix for World Wide Node Name (WWNN) */
343 /* prefix for World Wide Port Name (WWPN) */
345 #define TXGBE_MAX_MTA 128
346 u32 mta_shadow[TXGBE_MAX_MTA];
353 u8 san_mac_rar_index;
354 bool get_link_status;
355 u64 orig_autoc; /* cached value of AUTOC */
356 bool orig_link_settings_stored;
357 bool autotry_restart;
359 u32 max_link_up_time;
362 struct txgbe_phy_info {
363 u32 (*get_media_type)(struct txgbe_hw *hw);
364 s32 (*identify)(struct txgbe_hw *hw);
365 s32 (*identify_sfp)(struct txgbe_hw *hw);
366 s32 (*init)(struct txgbe_hw *hw);
367 s32 (*reset)(struct txgbe_hw *hw);
368 s32 (*read_reg)(struct txgbe_hw *hw, u32 reg_addr,
369 u32 device_type, u16 *phy_data);
370 s32 (*write_reg)(struct txgbe_hw *hw, u32 reg_addr,
371 u32 device_type, u16 phy_data);
372 s32 (*read_reg_mdi)(struct txgbe_hw *hw, u32 reg_addr,
373 u32 device_type, u16 *phy_data);
374 s32 (*write_reg_mdi)(struct txgbe_hw *hw, u32 reg_addr,
375 u32 device_type, u16 phy_data);
376 s32 (*setup_link)(struct txgbe_hw *hw);
377 s32 (*setup_internal_link)(struct txgbe_hw *hw);
378 s32 (*setup_link_speed)(struct txgbe_hw *hw, u32 speed,
379 bool autoneg_wait_to_complete);
380 s32 (*check_link)(struct txgbe_hw *hw, u32 *speed, bool *link_up);
381 s32 (*read_i2c_byte)(struct txgbe_hw *hw, u8 byte_offset,
382 u8 dev_addr, u8 *data);
383 s32 (*write_i2c_byte)(struct txgbe_hw *hw, u8 byte_offset,
384 u8 dev_addr, u8 data);
385 s32 (*read_i2c_sff8472)(struct txgbe_hw *hw, u8 byte_offset,
387 s32 (*read_i2c_eeprom)(struct txgbe_hw *hw, u8 byte_offset,
389 s32 (*write_i2c_eeprom)(struct txgbe_hw *hw, u8 byte_offset,
391 s32 (*check_overtemp)(struct txgbe_hw *hw);
392 s32 (*set_phy_power)(struct txgbe_hw *hw, bool on);
393 s32 (*handle_lasi)(struct txgbe_hw *hw);
394 s32 (*read_i2c_byte_unlocked)(struct txgbe_hw *hw, u8 offset, u8 addr,
396 s32 (*write_i2c_byte_unlocked)(struct txgbe_hw *hw, u8 offset, u8 addr,
399 enum txgbe_phy_type type;
402 enum txgbe_sfp_type sfp_type;
403 bool sfp_setup_needed;
406 u32 phy_semaphore_mask;
408 u32 autoneg_advertised;
409 u32 speeds_supported;
410 enum txgbe_smart_speed smart_speed;
411 bool smart_speed_active;
412 bool multispeed_fiber;
413 bool qsfp_shared_i2c_bus;
418 struct txgbe_mbx_info {
419 void (*init_params)(struct txgbe_hw *hw);
420 s32 (*read)(struct txgbe_hw *hw, u32 *msg, u16 size, u16 vf_number);
421 s32 (*write)(struct txgbe_hw *hw, u32 *msg, u16 size, u16 vf_number);
422 s32 (*read_posted)(struct txgbe_hw *hw, u32 *msg, u16 size,
424 s32 (*write_posted)(struct txgbe_hw *hw, u32 *msg, u16 size,
426 s32 (*check_for_msg)(struct txgbe_hw *hw, u16 mbx_id);
427 s32 (*check_for_ack)(struct txgbe_hw *hw, u16 mbx_id);
428 s32 (*check_for_rst)(struct txgbe_hw *hw, u16 mbx_id);
442 struct txgbe_mac_info mac;
443 struct txgbe_addr_filter_info addr_ctrl;
444 struct txgbe_phy_info phy;
445 struct txgbe_link_info link;
446 struct txgbe_rom_info rom;
447 struct txgbe_flash_info flash;
448 struct txgbe_bus_info bus;
449 struct txgbe_mbx_info mbx;
452 u16 subsystem_device_id;
453 u16 subsystem_vendor_id;
455 bool allow_unsupported_sfp;
456 bool need_crosstalk_fix;
460 enum txgbe_link_status {
461 TXGBE_LINK_STATUS_NONE = 0,
462 TXGBE_LINK_STATUS_KX,
463 TXGBE_LINK_STATUS_KX4
465 enum txgbe_reset_type {
472 #include "txgbe_regs.h"
473 #include "txgbe_dummy.h"
475 #endif /* _TXGBE_TYPE_H_ */