1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2015-2020
8 #define TXGBE_DCB_TC_MAX TXGBE_MAX_UP
9 #define TXGBE_LINK_UP_TIME 90 /* 9.0 Seconds */
10 #define TXGBE_AUTO_NEG_TIME 45 /* 4.5 Seconds */
12 #define TXGBE_FRAME_SIZE_MAX (9728) /* Maximum frame size, +FCS */
13 #define TXGBE_FRAME_SIZE_DFT (1518) /* Default frame size, +FCS */
14 #define TXGBE_NUM_POOL (64)
15 #define TXGBE_MAX_UP 8
16 #define TXGBE_MAX_QP (128)
17 #define TXGBE_MAX_UTA 128
19 #define TXGBE_ALIGN 128 /* as intel did */
21 #include "txgbe_status.h"
22 #include "txgbe_osdep.h"
23 #include "txgbe_devids.h"
25 struct txgbe_thermal_diode_data {
31 struct txgbe_thermal_sensor_data {
32 struct txgbe_thermal_diode_data sensor[1];
35 /* Physical layer type */
36 #define TXGBE_PHYSICAL_LAYER_UNKNOWN 0
37 #define TXGBE_PHYSICAL_LAYER_10GBASE_T 0x00001
38 #define TXGBE_PHYSICAL_LAYER_1000BASE_T 0x00002
39 #define TXGBE_PHYSICAL_LAYER_100BASE_TX 0x00004
40 #define TXGBE_PHYSICAL_LAYER_SFP_PLUS_CU 0x00008
41 #define TXGBE_PHYSICAL_LAYER_10GBASE_LR 0x00010
42 #define TXGBE_PHYSICAL_LAYER_10GBASE_LRM 0x00020
43 #define TXGBE_PHYSICAL_LAYER_10GBASE_SR 0x00040
44 #define TXGBE_PHYSICAL_LAYER_10GBASE_KX4 0x00080
45 #define TXGBE_PHYSICAL_LAYER_10GBASE_CX4 0x00100
46 #define TXGBE_PHYSICAL_LAYER_1000BASE_KX 0x00200
47 #define TXGBE_PHYSICAL_LAYER_1000BASE_BX 0x00400
48 #define TXGBE_PHYSICAL_LAYER_10GBASE_KR 0x00800
49 #define TXGBE_PHYSICAL_LAYER_10GBASE_XAUI 0x01000
50 #define TXGBE_PHYSICAL_LAYER_SFP_ACTIVE_DA 0x02000
51 #define TXGBE_PHYSICAL_LAYER_1000BASE_SX 0x04000
52 #define TXGBE_PHYSICAL_LAYER_10BASE_T 0x08000
53 #define TXGBE_PHYSICAL_LAYER_2500BASE_KX 0x10000
55 #define TXGBE_ATR_HASH_MASK 0x7fff
57 enum txgbe_eeprom_type {
58 txgbe_eeprom_unknown = 0,
61 txgbe_eeprom_none /* No NVM support */
65 txgbe_mac_unknown = 0,
72 txgbe_phy_unknown = 0,
82 txgbe_phy_sfp_tyco_passive,
83 txgbe_phy_sfp_unknown_passive,
84 txgbe_phy_sfp_unknown_active,
87 txgbe_phy_sfp_ftl_active,
88 txgbe_phy_sfp_unknown,
90 txgbe_phy_qsfp_unknown_passive,
91 txgbe_phy_qsfp_unknown_active,
93 txgbe_phy_qsfp_unknown,
94 txgbe_phy_sfp_unsupported, /* Enforce bit set with unsupported module */
101 * SFP+ module type IDs:
108 * 3 SFP_DA_CU_CORE0 - chip-specific
109 * 4 SFP_DA_CU_CORE1 - chip-specific
110 * 5 SFP_SR/LR_CORE0 - chip-specific
111 * 6 SFP_SR/LR_CORE1 - chip-specific
113 enum txgbe_sfp_type {
114 txgbe_sfp_type_unknown = 0,
115 txgbe_sfp_type_da_cu,
118 txgbe_sfp_type_da_cu_core0,
119 txgbe_sfp_type_da_cu_core1,
120 txgbe_sfp_type_srlr_core0,
121 txgbe_sfp_type_srlr_core1,
122 txgbe_sfp_type_da_act_lmt_core0,
123 txgbe_sfp_type_da_act_lmt_core1,
124 txgbe_sfp_type_1g_cu_core0,
125 txgbe_sfp_type_1g_cu_core1,
126 txgbe_sfp_type_1g_sx_core0,
127 txgbe_sfp_type_1g_sx_core1,
128 txgbe_sfp_type_1g_lx_core0,
129 txgbe_sfp_type_1g_lx_core1,
130 txgbe_sfp_type_not_present = 0xFFFE,
131 txgbe_sfp_type_not_known = 0xFFFF
134 enum txgbe_media_type {
135 txgbe_media_type_unknown = 0,
136 txgbe_media_type_fiber,
137 txgbe_media_type_fiber_qsfp,
138 txgbe_media_type_copper,
139 txgbe_media_type_backplane,
140 txgbe_media_type_cx4,
141 txgbe_media_type_virtual
145 /* Smart Speed Settings */
146 #define TXGBE_SMARTSPEED_MAX_RETRIES 3
147 enum txgbe_smart_speed {
148 txgbe_smart_speed_auto = 0,
149 txgbe_smart_speed_on,
150 txgbe_smart_speed_off
154 enum txgbe_bus_type {
155 txgbe_bus_type_unknown = 0,
158 txgbe_bus_type_pci_express,
159 txgbe_bus_type_internal,
160 txgbe_bus_type_reserved
164 enum txgbe_bus_speed {
165 txgbe_bus_speed_unknown = 0,
166 txgbe_bus_speed_33 = 33,
167 txgbe_bus_speed_66 = 66,
168 txgbe_bus_speed_100 = 100,
169 txgbe_bus_speed_120 = 120,
170 txgbe_bus_speed_133 = 133,
171 txgbe_bus_speed_2500 = 2500,
172 txgbe_bus_speed_5000 = 5000,
173 txgbe_bus_speed_8000 = 8000,
174 txgbe_bus_speed_reserved
178 enum txgbe_bus_width {
179 txgbe_bus_width_unknown = 0,
180 txgbe_bus_width_pcie_x1 = 1,
181 txgbe_bus_width_pcie_x2 = 2,
182 txgbe_bus_width_pcie_x4 = 4,
183 txgbe_bus_width_pcie_x8 = 8,
184 txgbe_bus_width_32 = 32,
185 txgbe_bus_width_64 = 64,
186 txgbe_bus_width_reserved
191 struct txgbe_addr_filter_info {
195 u32 overflow_promisc;
196 bool user_set_promisc;
200 struct txgbe_bus_info {
201 s32 (*get_bus_info)(struct txgbe_hw *hw);
202 void (*set_lan_id)(struct txgbe_hw *hw);
204 enum txgbe_bus_speed speed;
205 enum txgbe_bus_width width;
206 enum txgbe_bus_type type;
213 /* Statistics counters collected by the MAC */
215 struct txgbe_pb_stats {
216 u64 tx_pb_xon_packets;
217 u64 rx_pb_xon_packets;
218 u64 tx_pb_xoff_packets;
219 u64 rx_pb_xoff_packets;
221 u64 rx_pb_mbuf_alloc_errors;
222 u64 tx_pb_xon2off_packets;
226 struct txgbe_qp_stats {
231 u64 rx_qp_mc_packets;
234 struct txgbe_hw_stats {
236 u64 mng_bmc2host_packets;
237 u64 mng_host2bmc_packets;
244 u64 rx_total_packets;
245 u64 tx_total_packets;
246 u64 rx_total_missed_packets;
247 u64 rx_broadcast_packets;
248 u64 tx_broadcast_packets;
249 u64 rx_multicast_packets;
250 u64 tx_multicast_packets;
251 u64 rx_management_packets;
252 u64 tx_management_packets;
253 u64 rx_management_dropped;
258 u64 rx_illegal_byte_errors;
260 u64 rx_mac_short_packet_dropped;
261 u64 rx_length_errors;
262 u64 rx_undersize_errors;
263 u64 rx_fragment_errors;
264 u64 rx_oversize_errors;
265 u64 rx_jabber_errors;
266 u64 rx_l3_l4_xsum_error;
267 u64 mac_local_errors;
268 u64 mac_remote_errors;
271 u64 flow_director_added_filters;
272 u64 flow_director_removed_filters;
273 u64 flow_director_filter_add_errors;
274 u64 flow_director_filter_remove_errors;
275 u64 flow_director_matched_filters;
276 u64 flow_director_missed_filters;
279 u64 rx_fcoe_crc_errors;
280 u64 rx_fcoe_mbuf_allocation_errors;
287 u64 rx_fcoe_no_ddp_ext_buff;
290 u64 tx_macsec_pkts_untagged;
291 u64 tx_macsec_pkts_encrypted;
292 u64 tx_macsec_pkts_protected;
293 u64 tx_macsec_octets_encrypted;
294 u64 tx_macsec_octets_protected;
295 u64 rx_macsec_pkts_untagged;
296 u64 rx_macsec_pkts_badtag;
297 u64 rx_macsec_pkts_nosci;
298 u64 rx_macsec_pkts_unknownsci;
299 u64 rx_macsec_octets_decrypted;
300 u64 rx_macsec_octets_validated;
301 u64 rx_macsec_sc_pkts_unchecked;
302 u64 rx_macsec_sc_pkts_delayed;
303 u64 rx_macsec_sc_pkts_late;
304 u64 rx_macsec_sa_pkts_ok;
305 u64 rx_macsec_sa_pkts_invalid;
306 u64 rx_macsec_sa_pkts_notvalid;
307 u64 rx_macsec_sa_pkts_unusedsa;
308 u64 rx_macsec_sa_pkts_notusingsa;
311 u64 rx_size_64_packets;
312 u64 rx_size_65_to_127_packets;
313 u64 rx_size_128_to_255_packets;
314 u64 rx_size_256_to_511_packets;
315 u64 rx_size_512_to_1023_packets;
316 u64 rx_size_1024_to_max_packets;
317 u64 tx_size_64_packets;
318 u64 tx_size_65_to_127_packets;
319 u64 tx_size_128_to_255_packets;
320 u64 tx_size_256_to_511_packets;
321 u64 tx_size_512_to_1023_packets;
322 u64 tx_size_1024_to_max_packets;
336 u64 rx_up_drop_packets;
338 u64 tx_up_xon_packets;
339 u64 rx_up_xon_packets;
340 u64 tx_up_xoff_packets;
341 u64 rx_up_xoff_packets;
343 u64 rx_up_mbuf_alloc_errors;
344 u64 tx_up_xon2off_packets;
353 u64 rx_qp_mc_packets;
358 /* iterator type for walking multicast address lists */
359 typedef u8* (*txgbe_mc_addr_itr) (struct txgbe_hw *hw, u8 **mc_addr_ptr,
362 struct txgbe_link_info {
363 s32 (*read_link)(struct txgbe_hw *hw, u8 addr, u16 reg, u16 *val);
364 s32 (*read_link_unlocked)(struct txgbe_hw *hw, u8 addr, u16 reg,
366 s32 (*write_link)(struct txgbe_hw *hw, u8 addr, u16 reg, u16 val);
367 s32 (*write_link_unlocked)(struct txgbe_hw *hw, u8 addr, u16 reg,
373 struct txgbe_rom_info {
374 s32 (*init_params)(struct txgbe_hw *hw);
375 s32 (*read16)(struct txgbe_hw *hw, u32 offset, u16 *data);
376 s32 (*readw_sw)(struct txgbe_hw *hw, u32 offset, u16 *data);
377 s32 (*readw_buffer)(struct txgbe_hw *hw, u32 offset, u32 words,
379 s32 (*read32)(struct txgbe_hw *hw, u32 addr, u32 *data);
380 s32 (*read_buffer)(struct txgbe_hw *hw, u32 addr, u32 len, void *data);
381 s32 (*write16)(struct txgbe_hw *hw, u32 offset, u16 data);
382 s32 (*writew_sw)(struct txgbe_hw *hw, u32 offset, u16 data);
383 s32 (*writew_buffer)(struct txgbe_hw *hw, u32 offset, u32 words,
385 s32 (*write32)(struct txgbe_hw *hw, u32 addr, u32 data);
386 s32 (*write_buffer)(struct txgbe_hw *hw, u32 addr, u32 len, void *data);
387 s32 (*validate_checksum)(struct txgbe_hw *hw, u16 *checksum_val);
388 s32 (*update_checksum)(struct txgbe_hw *hw);
389 s32 (*calc_checksum)(struct txgbe_hw *hw);
391 enum txgbe_eeprom_type type;
401 struct txgbe_flash_info {
407 #define TXGBE_FLAGS_DOUBLE_RESET_REQUIRED 0x01
408 struct txgbe_mac_info {
409 s32 (*init_hw)(struct txgbe_hw *hw);
410 s32 (*reset_hw)(struct txgbe_hw *hw);
411 s32 (*start_hw)(struct txgbe_hw *hw);
412 s32 (*stop_hw)(struct txgbe_hw *hw);
413 s32 (*clear_hw_cntrs)(struct txgbe_hw *hw);
414 s32 (*get_mac_addr)(struct txgbe_hw *hw, u8 *mac_addr);
415 s32 (*get_san_mac_addr)(struct txgbe_hw *hw, u8 *san_mac_addr);
416 s32 (*set_san_mac_addr)(struct txgbe_hw *hw, u8 *san_mac_addr);
417 s32 (*get_device_caps)(struct txgbe_hw *hw, u16 *device_caps);
418 s32 (*get_wwn_prefix)(struct txgbe_hw *hw, u16 *wwnn_prefix,
420 s32 (*setup_sfp)(struct txgbe_hw *hw);
421 s32 (*enable_rx_dma)(struct txgbe_hw *hw, u32 regval);
422 s32 (*disable_sec_rx_path)(struct txgbe_hw *hw);
423 s32 (*enable_sec_rx_path)(struct txgbe_hw *hw);
424 s32 (*disable_sec_tx_path)(struct txgbe_hw *hw);
425 s32 (*enable_sec_tx_path)(struct txgbe_hw *hw);
426 s32 (*acquire_swfw_sync)(struct txgbe_hw *hw, u32 mask);
427 void (*release_swfw_sync)(struct txgbe_hw *hw, u32 mask);
428 u64 (*autoc_read)(struct txgbe_hw *hw);
429 void (*autoc_write)(struct txgbe_hw *hw, u64 value);
430 s32 (*prot_autoc_read)(struct txgbe_hw *hw, bool *locked, u64 *value);
431 s32 (*prot_autoc_write)(struct txgbe_hw *hw, bool locked, u64 value);
432 s32 (*negotiate_api_version)(struct txgbe_hw *hw, int api);
435 void (*disable_tx_laser)(struct txgbe_hw *hw);
436 void (*enable_tx_laser)(struct txgbe_hw *hw);
437 void (*flap_tx_laser)(struct txgbe_hw *hw);
438 s32 (*setup_link)(struct txgbe_hw *hw, u32 speed,
439 bool autoneg_wait_to_complete);
440 s32 (*setup_mac_link)(struct txgbe_hw *hw, u32 speed,
441 bool autoneg_wait_to_complete);
442 s32 (*check_link)(struct txgbe_hw *hw, u32 *speed,
443 bool *link_up, bool link_up_wait_to_complete);
444 s32 (*get_link_capabilities)(struct txgbe_hw *hw,
445 u32 *speed, bool *autoneg);
446 void (*set_rate_select_speed)(struct txgbe_hw *hw, u32 speed);
448 /* Packet Buffer manipulation */
449 void (*setup_pba)(struct txgbe_hw *hw, int num_pb, u32 headroom,
453 s32 (*led_on)(struct txgbe_hw *hw, u32 index);
454 s32 (*led_off)(struct txgbe_hw *hw, u32 index);
456 /* RAR, Multicast, VLAN */
457 s32 (*set_rar)(struct txgbe_hw *hw, u32 index, u8 *addr, u32 vmdq,
459 s32 (*set_uc_addr)(struct txgbe_hw *hw, u32 index, u8 *addr);
460 s32 (*clear_rar)(struct txgbe_hw *hw, u32 index);
461 s32 (*set_vmdq)(struct txgbe_hw *hw, u32 rar, u32 vmdq);
462 s32 (*clear_vmdq)(struct txgbe_hw *hw, u32 rar, u32 vmdq);
463 s32 (*init_rx_addrs)(struct txgbe_hw *hw);
464 s32 (*update_mc_addr_list)(struct txgbe_hw *hw, u8 *mc_addr_list,
466 txgbe_mc_addr_itr func, bool clear);
467 s32 (*clear_vfta)(struct txgbe_hw *hw);
468 s32 (*set_vfta)(struct txgbe_hw *hw, u32 vlan,
469 u32 vind, bool vlan_on, bool vlvf_bypass);
470 s32 (*set_vlvf)(struct txgbe_hw *hw, u32 vlan, u32 vind,
471 bool vlan_on, u32 *vfta_delta, u32 vfta,
473 s32 (*init_uta_tables)(struct txgbe_hw *hw);
474 void (*set_mac_anti_spoofing)(struct txgbe_hw *hw, bool enable, int vf);
475 void (*set_vlan_anti_spoofing)(struct txgbe_hw *hw,
476 bool enable, int vf);
477 s32 (*update_xcast_mode)(struct txgbe_hw *hw, int xcast_mode);
478 s32 (*set_rlpml)(struct txgbe_hw *hw, u16 max_size);
481 s32 (*fc_enable)(struct txgbe_hw *hw);
482 s32 (*setup_fc)(struct txgbe_hw *hw);
483 void (*fc_autoneg)(struct txgbe_hw *hw);
485 /* Manageability interface */
486 s32 (*set_fw_drv_ver)(struct txgbe_hw *hw, u8 maj, u8 min, u8 build,
487 u8 ver, u16 len, const char *driver_ver);
488 s32 (*get_thermal_sensor_data)(struct txgbe_hw *hw);
489 s32 (*init_thermal_sensor_thresh)(struct txgbe_hw *hw);
490 void (*get_rtrup2tc)(struct txgbe_hw *hw, u8 *map);
491 void (*disable_rx)(struct txgbe_hw *hw);
492 void (*enable_rx)(struct txgbe_hw *hw);
493 void (*set_ethertype_anti_spoofing)(struct txgbe_hw *hw,
494 bool enable, int vf);
495 s32 (*dmac_update_tcs)(struct txgbe_hw *hw);
496 s32 (*dmac_config_tcs)(struct txgbe_hw *hw);
497 s32 (*dmac_config)(struct txgbe_hw *hw);
498 s32 (*setup_eee)(struct txgbe_hw *hw, bool enable_eee);
500 enum txgbe_mac_type type;
501 u8 addr[ETH_ADDR_LEN];
502 u8 perm_addr[ETH_ADDR_LEN];
503 u8 san_addr[ETH_ADDR_LEN];
504 /* prefix for World Wide Node Name (WWNN) */
506 /* prefix for World Wide Port Name (WWPN) */
508 #define TXGBE_MAX_MTA 128
509 u32 mta_shadow[TXGBE_MAX_MTA];
517 u8 san_mac_rar_index;
518 bool get_link_status;
519 u64 orig_autoc; /* cached value of AUTOC */
520 bool orig_link_settings_stored;
521 bool autotry_restart;
523 struct txgbe_thermal_sensor_data thermal_sensor_data;
525 u32 max_link_up_time;
528 struct txgbe_phy_info {
529 u32 (*get_media_type)(struct txgbe_hw *hw);
530 s32 (*identify)(struct txgbe_hw *hw);
531 s32 (*identify_sfp)(struct txgbe_hw *hw);
532 s32 (*init)(struct txgbe_hw *hw);
533 s32 (*reset)(struct txgbe_hw *hw);
534 s32 (*read_reg)(struct txgbe_hw *hw, u32 reg_addr,
535 u32 device_type, u16 *phy_data);
536 s32 (*write_reg)(struct txgbe_hw *hw, u32 reg_addr,
537 u32 device_type, u16 phy_data);
538 s32 (*read_reg_mdi)(struct txgbe_hw *hw, u32 reg_addr,
539 u32 device_type, u16 *phy_data);
540 s32 (*write_reg_mdi)(struct txgbe_hw *hw, u32 reg_addr,
541 u32 device_type, u16 phy_data);
542 s32 (*setup_link)(struct txgbe_hw *hw);
543 s32 (*setup_internal_link)(struct txgbe_hw *hw);
544 s32 (*setup_link_speed)(struct txgbe_hw *hw, u32 speed,
545 bool autoneg_wait_to_complete);
546 s32 (*check_link)(struct txgbe_hw *hw, u32 *speed, bool *link_up);
547 s32 (*read_i2c_byte)(struct txgbe_hw *hw, u8 byte_offset,
548 u8 dev_addr, u8 *data);
549 s32 (*write_i2c_byte)(struct txgbe_hw *hw, u8 byte_offset,
550 u8 dev_addr, u8 data);
551 s32 (*read_i2c_sff8472)(struct txgbe_hw *hw, u8 byte_offset,
553 s32 (*read_i2c_eeprom)(struct txgbe_hw *hw, u8 byte_offset,
555 s32 (*write_i2c_eeprom)(struct txgbe_hw *hw, u8 byte_offset,
557 s32 (*check_overtemp)(struct txgbe_hw *hw);
558 s32 (*set_phy_power)(struct txgbe_hw *hw, bool on);
559 s32 (*handle_lasi)(struct txgbe_hw *hw);
560 s32 (*read_i2c_byte_unlocked)(struct txgbe_hw *hw, u8 offset, u8 addr,
562 s32 (*write_i2c_byte_unlocked)(struct txgbe_hw *hw, u8 offset, u8 addr,
565 enum txgbe_phy_type type;
568 enum txgbe_sfp_type sfp_type;
569 bool sfp_setup_needed;
572 u32 phy_semaphore_mask;
574 u32 autoneg_advertised;
575 u32 speeds_supported;
576 enum txgbe_smart_speed smart_speed;
577 bool smart_speed_active;
578 bool multispeed_fiber;
579 bool qsfp_shared_i2c_bus;
584 struct txgbe_mbx_stats {
593 struct txgbe_mbx_info {
594 void (*init_params)(struct txgbe_hw *hw);
595 s32 (*read)(struct txgbe_hw *hw, u32 *msg, u16 size, u16 vf_number);
596 s32 (*write)(struct txgbe_hw *hw, u32 *msg, u16 size, u16 vf_number);
597 s32 (*read_posted)(struct txgbe_hw *hw, u32 *msg, u16 size,
599 s32 (*write_posted)(struct txgbe_hw *hw, u32 *msg, u16 size,
601 s32 (*check_for_msg)(struct txgbe_hw *hw, u16 mbx_id);
602 s32 (*check_for_ack)(struct txgbe_hw *hw, u16 mbx_id);
603 s32 (*check_for_rst)(struct txgbe_hw *hw, u16 mbx_id);
605 struct txgbe_mbx_stats stats;
622 struct txgbe_mac_info mac;
623 struct txgbe_addr_filter_info addr_ctrl;
624 struct txgbe_phy_info phy;
625 struct txgbe_link_info link;
626 struct txgbe_rom_info rom;
627 struct txgbe_flash_info flash;
628 struct txgbe_bus_info bus;
629 struct txgbe_mbx_info mbx;
632 u16 subsystem_device_id;
633 u16 subsystem_vendor_id;
634 bool adapter_stopped;
635 bool allow_unsupported_sfp;
636 bool need_crosstalk_fix;
642 enum txgbe_link_status {
643 TXGBE_LINK_STATUS_NONE = 0,
644 TXGBE_LINK_STATUS_KX,
645 TXGBE_LINK_STATUS_KX4
647 enum txgbe_reset_type {
653 u32 q_rx_regs[128 * 4];
654 u32 q_tx_regs[128 * 4];
661 u64 rx_qp_mc_packets;
662 } qp_last[TXGBE_MAX_QP];
665 #include "txgbe_regs.h"
666 #include "txgbe_dummy.h"
668 #endif /* _TXGBE_TYPE_H_ */