1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2015-2020
8 #define TXGBE_DCB_TC_MAX TXGBE_MAX_UP
9 #define TXGBE_DCB_UP_MAX TXGBE_MAX_UP
10 #define TXGBE_DCB_BWG_MAX TXGBE_MAX_UP
11 #define TXGBE_LINK_UP_TIME 90 /* 9.0 Seconds */
12 #define TXGBE_AUTO_NEG_TIME 45 /* 4.5 Seconds */
14 #define TXGBE_FRAME_SIZE_MAX (9728) /* Maximum frame size, +FCS */
15 #define TXGBE_FRAME_SIZE_DFT (1518) /* Default frame size, +FCS */
16 #define TXGBE_NUM_POOL (64)
17 #define TXGBE_PBTXSIZE_MAX 0x00028000 /* 160KB Packet Buffer */
18 #define TXGBE_MAX_FTQF_FILTERS 128
19 #define TXGBE_TXPKT_SIZE_MAX 0xA /* Max Tx Packet size */
20 #define TXGBE_MAX_UP 8
21 #define TXGBE_MAX_QP (128)
22 #define TXGBE_MAX_UTA 128
24 #define TXGBE_ALIGN 128 /* as intel did */
26 #include "txgbe_status.h"
27 #include "txgbe_osdep.h"
28 #include "txgbe_devids.h"
30 struct txgbe_thermal_diode_data {
36 struct txgbe_thermal_sensor_data {
37 struct txgbe_thermal_diode_data sensor[1];
40 /* Packet buffer allocation strategies */
42 PBA_STRATEGY_EQUAL = 0, /* Distribute PB space equally */
43 #define PBA_STRATEGY_EQUAL PBA_STRATEGY_EQUAL
44 PBA_STRATEGY_WEIGHTED = 1, /* Weight front half of TCs */
45 #define PBA_STRATEGY_WEIGHTED PBA_STRATEGY_WEIGHTED
48 /* Physical layer type */
49 #define TXGBE_PHYSICAL_LAYER_UNKNOWN 0
50 #define TXGBE_PHYSICAL_LAYER_10GBASE_T 0x00001
51 #define TXGBE_PHYSICAL_LAYER_1000BASE_T 0x00002
52 #define TXGBE_PHYSICAL_LAYER_100BASE_TX 0x00004
53 #define TXGBE_PHYSICAL_LAYER_SFP_PLUS_CU 0x00008
54 #define TXGBE_PHYSICAL_LAYER_10GBASE_LR 0x00010
55 #define TXGBE_PHYSICAL_LAYER_10GBASE_LRM 0x00020
56 #define TXGBE_PHYSICAL_LAYER_10GBASE_SR 0x00040
57 #define TXGBE_PHYSICAL_LAYER_10GBASE_KX4 0x00080
58 #define TXGBE_PHYSICAL_LAYER_10GBASE_CX4 0x00100
59 #define TXGBE_PHYSICAL_LAYER_1000BASE_KX 0x00200
60 #define TXGBE_PHYSICAL_LAYER_1000BASE_BX 0x00400
61 #define TXGBE_PHYSICAL_LAYER_10GBASE_KR 0x00800
62 #define TXGBE_PHYSICAL_LAYER_10GBASE_XAUI 0x01000
63 #define TXGBE_PHYSICAL_LAYER_SFP_ACTIVE_DA 0x02000
64 #define TXGBE_PHYSICAL_LAYER_1000BASE_SX 0x04000
65 #define TXGBE_PHYSICAL_LAYER_10BASE_T 0x08000
66 #define TXGBE_PHYSICAL_LAYER_2500BASE_KX 0x10000
68 #define TXGBE_ATR_HASH_MASK 0x7fff
70 /* Flow Director ATR input struct. */
71 struct txgbe_atr_input {
73 * Byte layout in order, all values with MSB first:
80 * cloud_mode - 2 bytes
85 * flex_bytes - 2 bytes
99 enum txgbe_eeprom_type {
100 txgbe_eeprom_unknown = 0,
103 txgbe_eeprom_none /* No NVM support */
106 enum txgbe_mac_type {
107 txgbe_mac_unknown = 0,
113 enum txgbe_phy_type {
114 txgbe_phy_unknown = 0,
120 txgbe_phy_cu_unknown,
124 txgbe_phy_sfp_tyco_passive,
125 txgbe_phy_sfp_unknown_passive,
126 txgbe_phy_sfp_unknown_active,
129 txgbe_phy_sfp_ftl_active,
130 txgbe_phy_sfp_unknown,
132 txgbe_phy_qsfp_unknown_passive,
133 txgbe_phy_qsfp_unknown_active,
134 txgbe_phy_qsfp_intel,
135 txgbe_phy_qsfp_unknown,
136 txgbe_phy_sfp_unsupported, /* Enforce bit set with unsupported module */
143 * SFP+ module type IDs:
150 * 3 SFP_DA_CU_CORE0 - chip-specific
151 * 4 SFP_DA_CU_CORE1 - chip-specific
152 * 5 SFP_SR/LR_CORE0 - chip-specific
153 * 6 SFP_SR/LR_CORE1 - chip-specific
155 enum txgbe_sfp_type {
156 txgbe_sfp_type_unknown = 0,
157 txgbe_sfp_type_da_cu,
160 txgbe_sfp_type_da_cu_core0,
161 txgbe_sfp_type_da_cu_core1,
162 txgbe_sfp_type_srlr_core0,
163 txgbe_sfp_type_srlr_core1,
164 txgbe_sfp_type_da_act_lmt_core0,
165 txgbe_sfp_type_da_act_lmt_core1,
166 txgbe_sfp_type_1g_cu_core0,
167 txgbe_sfp_type_1g_cu_core1,
168 txgbe_sfp_type_1g_sx_core0,
169 txgbe_sfp_type_1g_sx_core1,
170 txgbe_sfp_type_1g_lx_core0,
171 txgbe_sfp_type_1g_lx_core1,
172 txgbe_sfp_type_not_present = 0xFFFE,
173 txgbe_sfp_type_not_known = 0xFFFF
176 enum txgbe_media_type {
177 txgbe_media_type_unknown = 0,
178 txgbe_media_type_fiber,
179 txgbe_media_type_fiber_qsfp,
180 txgbe_media_type_copper,
181 txgbe_media_type_backplane,
182 txgbe_media_type_cx4,
183 txgbe_media_type_virtual
186 /* Flow Control Settings */
195 /* Smart Speed Settings */
196 #define TXGBE_SMARTSPEED_MAX_RETRIES 3
197 enum txgbe_smart_speed {
198 txgbe_smart_speed_auto = 0,
199 txgbe_smart_speed_on,
200 txgbe_smart_speed_off
204 enum txgbe_bus_type {
205 txgbe_bus_type_unknown = 0,
208 txgbe_bus_type_pci_express,
209 txgbe_bus_type_internal,
210 txgbe_bus_type_reserved
214 enum txgbe_bus_speed {
215 txgbe_bus_speed_unknown = 0,
216 txgbe_bus_speed_33 = 33,
217 txgbe_bus_speed_66 = 66,
218 txgbe_bus_speed_100 = 100,
219 txgbe_bus_speed_120 = 120,
220 txgbe_bus_speed_133 = 133,
221 txgbe_bus_speed_2500 = 2500,
222 txgbe_bus_speed_5000 = 5000,
223 txgbe_bus_speed_8000 = 8000,
224 txgbe_bus_speed_reserved
228 enum txgbe_bus_width {
229 txgbe_bus_width_unknown = 0,
230 txgbe_bus_width_pcie_x1 = 1,
231 txgbe_bus_width_pcie_x2 = 2,
232 txgbe_bus_width_pcie_x4 = 4,
233 txgbe_bus_width_pcie_x8 = 8,
234 txgbe_bus_width_32 = 32,
235 txgbe_bus_width_64 = 64,
236 txgbe_bus_width_reserved
241 struct txgbe_addr_filter_info {
245 u32 overflow_promisc;
246 bool user_set_promisc;
250 struct txgbe_bus_info {
251 s32 (*get_bus_info)(struct txgbe_hw *hw);
252 void (*set_lan_id)(struct txgbe_hw *hw);
254 enum txgbe_bus_speed speed;
255 enum txgbe_bus_width width;
256 enum txgbe_bus_type type;
263 /* Flow control parameters */
264 struct txgbe_fc_info {
265 u32 high_water[TXGBE_DCB_TC_MAX]; /* Flow Ctrl High-water */
266 u32 low_water[TXGBE_DCB_TC_MAX]; /* Flow Ctrl Low-water */
267 u16 pause_time; /* Flow Control Pause timer */
268 bool send_xon; /* Flow control send XON */
269 bool strict_ieee; /* Strict IEEE mode */
270 bool disable_fc_autoneg; /* Do not autonegotiate FC */
271 bool fc_was_autonegged; /* Is current_mode the result of autonegging? */
272 enum txgbe_fc_mode current_mode; /* FC mode in effect */
273 enum txgbe_fc_mode requested_mode; /* FC mode requested by caller */
276 /* Statistics counters collected by the MAC */
278 struct txgbe_pb_stats {
279 u64 tx_pb_xon_packets;
280 u64 rx_pb_xon_packets;
281 u64 tx_pb_xoff_packets;
282 u64 rx_pb_xoff_packets;
284 u64 rx_pb_mbuf_alloc_errors;
285 u64 tx_pb_xon2off_packets;
289 struct txgbe_qp_stats {
294 u64 rx_qp_mc_packets;
297 struct txgbe_hw_stats {
299 u64 mng_bmc2host_packets;
300 u64 mng_host2bmc_packets;
307 u64 rx_total_packets;
308 u64 tx_total_packets;
309 u64 rx_total_missed_packets;
310 u64 rx_broadcast_packets;
311 u64 tx_broadcast_packets;
312 u64 rx_multicast_packets;
313 u64 tx_multicast_packets;
314 u64 rx_management_packets;
315 u64 tx_management_packets;
316 u64 rx_management_dropped;
321 u64 rx_illegal_byte_errors;
323 u64 rx_mac_short_packet_dropped;
324 u64 rx_length_errors;
325 u64 rx_undersize_errors;
326 u64 rx_fragment_errors;
327 u64 rx_oversize_errors;
328 u64 rx_jabber_errors;
329 u64 rx_l3_l4_xsum_error;
330 u64 mac_local_errors;
331 u64 mac_remote_errors;
334 u64 flow_director_added_filters;
335 u64 flow_director_removed_filters;
336 u64 flow_director_filter_add_errors;
337 u64 flow_director_filter_remove_errors;
338 u64 flow_director_matched_filters;
339 u64 flow_director_missed_filters;
342 u64 rx_fcoe_crc_errors;
343 u64 rx_fcoe_mbuf_allocation_errors;
350 u64 rx_fcoe_no_ddp_ext_buff;
353 u64 tx_macsec_pkts_untagged;
354 u64 tx_macsec_pkts_encrypted;
355 u64 tx_macsec_pkts_protected;
356 u64 tx_macsec_octets_encrypted;
357 u64 tx_macsec_octets_protected;
358 u64 rx_macsec_pkts_untagged;
359 u64 rx_macsec_pkts_badtag;
360 u64 rx_macsec_pkts_nosci;
361 u64 rx_macsec_pkts_unknownsci;
362 u64 rx_macsec_octets_decrypted;
363 u64 rx_macsec_octets_validated;
364 u64 rx_macsec_sc_pkts_unchecked;
365 u64 rx_macsec_sc_pkts_delayed;
366 u64 rx_macsec_sc_pkts_late;
367 u64 rx_macsec_sa_pkts_ok;
368 u64 rx_macsec_sa_pkts_invalid;
369 u64 rx_macsec_sa_pkts_notvalid;
370 u64 rx_macsec_sa_pkts_unusedsa;
371 u64 rx_macsec_sa_pkts_notusingsa;
374 u64 rx_size_64_packets;
375 u64 rx_size_65_to_127_packets;
376 u64 rx_size_128_to_255_packets;
377 u64 rx_size_256_to_511_packets;
378 u64 rx_size_512_to_1023_packets;
379 u64 rx_size_1024_to_max_packets;
380 u64 tx_size_64_packets;
381 u64 tx_size_65_to_127_packets;
382 u64 tx_size_128_to_255_packets;
383 u64 tx_size_256_to_511_packets;
384 u64 tx_size_512_to_1023_packets;
385 u64 tx_size_1024_to_max_packets;
399 u64 rx_up_drop_packets;
401 u64 tx_up_xon_packets;
402 u64 rx_up_xon_packets;
403 u64 tx_up_xoff_packets;
404 u64 rx_up_xoff_packets;
406 u64 rx_up_mbuf_alloc_errors;
407 u64 tx_up_xon2off_packets;
416 u64 rx_qp_mc_packets;
421 /* iterator type for walking multicast address lists */
422 typedef u8* (*txgbe_mc_addr_itr) (struct txgbe_hw *hw, u8 **mc_addr_ptr,
425 struct txgbe_link_info {
426 s32 (*read_link)(struct txgbe_hw *hw, u8 addr, u16 reg, u16 *val);
427 s32 (*read_link_unlocked)(struct txgbe_hw *hw, u8 addr, u16 reg,
429 s32 (*write_link)(struct txgbe_hw *hw, u8 addr, u16 reg, u16 val);
430 s32 (*write_link_unlocked)(struct txgbe_hw *hw, u8 addr, u16 reg,
436 struct txgbe_rom_info {
437 s32 (*init_params)(struct txgbe_hw *hw);
438 s32 (*read16)(struct txgbe_hw *hw, u32 offset, u16 *data);
439 s32 (*readw_sw)(struct txgbe_hw *hw, u32 offset, u16 *data);
440 s32 (*readw_buffer)(struct txgbe_hw *hw, u32 offset, u32 words,
442 s32 (*read32)(struct txgbe_hw *hw, u32 addr, u32 *data);
443 s32 (*read_buffer)(struct txgbe_hw *hw, u32 addr, u32 len, void *data);
444 s32 (*write16)(struct txgbe_hw *hw, u32 offset, u16 data);
445 s32 (*writew_sw)(struct txgbe_hw *hw, u32 offset, u16 data);
446 s32 (*writew_buffer)(struct txgbe_hw *hw, u32 offset, u32 words,
448 s32 (*write32)(struct txgbe_hw *hw, u32 addr, u32 data);
449 s32 (*write_buffer)(struct txgbe_hw *hw, u32 addr, u32 len, void *data);
450 s32 (*validate_checksum)(struct txgbe_hw *hw, u16 *checksum_val);
451 s32 (*update_checksum)(struct txgbe_hw *hw);
452 s32 (*calc_checksum)(struct txgbe_hw *hw);
454 enum txgbe_eeprom_type type;
464 struct txgbe_flash_info {
470 #define TXGBE_FLAGS_DOUBLE_RESET_REQUIRED 0x01
471 struct txgbe_mac_info {
472 s32 (*init_hw)(struct txgbe_hw *hw);
473 s32 (*reset_hw)(struct txgbe_hw *hw);
474 s32 (*start_hw)(struct txgbe_hw *hw);
475 s32 (*stop_hw)(struct txgbe_hw *hw);
476 s32 (*clear_hw_cntrs)(struct txgbe_hw *hw);
477 s32 (*get_mac_addr)(struct txgbe_hw *hw, u8 *mac_addr);
478 s32 (*get_san_mac_addr)(struct txgbe_hw *hw, u8 *san_mac_addr);
479 s32 (*set_san_mac_addr)(struct txgbe_hw *hw, u8 *san_mac_addr);
480 s32 (*get_device_caps)(struct txgbe_hw *hw, u16 *device_caps);
481 s32 (*get_wwn_prefix)(struct txgbe_hw *hw, u16 *wwnn_prefix,
483 s32 (*setup_sfp)(struct txgbe_hw *hw);
484 s32 (*enable_rx_dma)(struct txgbe_hw *hw, u32 regval);
485 s32 (*disable_sec_rx_path)(struct txgbe_hw *hw);
486 s32 (*enable_sec_rx_path)(struct txgbe_hw *hw);
487 s32 (*disable_sec_tx_path)(struct txgbe_hw *hw);
488 s32 (*enable_sec_tx_path)(struct txgbe_hw *hw);
489 s32 (*acquire_swfw_sync)(struct txgbe_hw *hw, u32 mask);
490 void (*release_swfw_sync)(struct txgbe_hw *hw, u32 mask);
491 u64 (*autoc_read)(struct txgbe_hw *hw);
492 void (*autoc_write)(struct txgbe_hw *hw, u64 value);
493 s32 (*prot_autoc_read)(struct txgbe_hw *hw, bool *locked, u64 *value);
494 s32 (*prot_autoc_write)(struct txgbe_hw *hw, bool locked, u64 value);
495 s32 (*negotiate_api_version)(struct txgbe_hw *hw, int api);
498 void (*disable_tx_laser)(struct txgbe_hw *hw);
499 void (*enable_tx_laser)(struct txgbe_hw *hw);
500 void (*flap_tx_laser)(struct txgbe_hw *hw);
501 s32 (*setup_link)(struct txgbe_hw *hw, u32 speed,
502 bool autoneg_wait_to_complete);
503 s32 (*setup_mac_link)(struct txgbe_hw *hw, u32 speed,
504 bool autoneg_wait_to_complete);
505 s32 (*check_link)(struct txgbe_hw *hw, u32 *speed,
506 bool *link_up, bool link_up_wait_to_complete);
507 s32 (*get_link_capabilities)(struct txgbe_hw *hw,
508 u32 *speed, bool *autoneg);
509 void (*set_rate_select_speed)(struct txgbe_hw *hw, u32 speed);
511 /* Packet Buffer manipulation */
512 void (*setup_pba)(struct txgbe_hw *hw, int num_pb, u32 headroom,
516 s32 (*led_on)(struct txgbe_hw *hw, u32 index);
517 s32 (*led_off)(struct txgbe_hw *hw, u32 index);
519 /* RAR, Multicast, VLAN */
520 s32 (*set_rar)(struct txgbe_hw *hw, u32 index, u8 *addr, u32 vmdq,
522 s32 (*set_uc_addr)(struct txgbe_hw *hw, u32 index, u8 *addr);
523 s32 (*clear_rar)(struct txgbe_hw *hw, u32 index);
524 s32 (*set_vmdq)(struct txgbe_hw *hw, u32 rar, u32 vmdq);
525 s32 (*clear_vmdq)(struct txgbe_hw *hw, u32 rar, u32 vmdq);
526 s32 (*init_rx_addrs)(struct txgbe_hw *hw);
527 s32 (*update_mc_addr_list)(struct txgbe_hw *hw, u8 *mc_addr_list,
529 txgbe_mc_addr_itr func, bool clear);
530 s32 (*clear_vfta)(struct txgbe_hw *hw);
531 s32 (*set_vfta)(struct txgbe_hw *hw, u32 vlan,
532 u32 vind, bool vlan_on, bool vlvf_bypass);
533 s32 (*set_vlvf)(struct txgbe_hw *hw, u32 vlan, u32 vind,
534 bool vlan_on, u32 *vfta_delta, u32 vfta,
536 s32 (*init_uta_tables)(struct txgbe_hw *hw);
537 void (*set_mac_anti_spoofing)(struct txgbe_hw *hw, bool enable, int vf);
538 void (*set_vlan_anti_spoofing)(struct txgbe_hw *hw,
539 bool enable, int vf);
540 s32 (*update_xcast_mode)(struct txgbe_hw *hw, int xcast_mode);
541 s32 (*set_rlpml)(struct txgbe_hw *hw, u16 max_size);
544 s32 (*fc_enable)(struct txgbe_hw *hw);
545 s32 (*setup_fc)(struct txgbe_hw *hw);
546 void (*fc_autoneg)(struct txgbe_hw *hw);
548 /* Manageability interface */
549 s32 (*set_fw_drv_ver)(struct txgbe_hw *hw, u8 maj, u8 min, u8 build,
550 u8 ver, u16 len, const char *driver_ver);
551 s32 (*get_thermal_sensor_data)(struct txgbe_hw *hw);
552 s32 (*init_thermal_sensor_thresh)(struct txgbe_hw *hw);
553 void (*get_rtrup2tc)(struct txgbe_hw *hw, u8 *map);
554 void (*disable_rx)(struct txgbe_hw *hw);
555 void (*enable_rx)(struct txgbe_hw *hw);
556 void (*set_ethertype_anti_spoofing)(struct txgbe_hw *hw,
557 bool enable, int vf);
558 s32 (*dmac_update_tcs)(struct txgbe_hw *hw);
559 s32 (*dmac_config_tcs)(struct txgbe_hw *hw);
560 s32 (*dmac_config)(struct txgbe_hw *hw);
561 s32 (*setup_eee)(struct txgbe_hw *hw, bool enable_eee);
563 enum txgbe_mac_type type;
564 u8 addr[ETH_ADDR_LEN];
565 u8 perm_addr[ETH_ADDR_LEN];
566 u8 san_addr[ETH_ADDR_LEN];
567 /* prefix for World Wide Node Name (WWNN) */
569 /* prefix for World Wide Port Name (WWPN) */
571 #define TXGBE_MAX_MTA 128
572 u32 mta_shadow[TXGBE_MAX_MTA];
580 u8 san_mac_rar_index;
581 bool get_link_status;
582 u64 orig_autoc; /* cached value of AUTOC */
583 bool orig_link_settings_stored;
584 bool autotry_restart;
586 struct txgbe_thermal_sensor_data thermal_sensor_data;
588 u32 max_link_up_time;
591 struct txgbe_phy_info {
592 u32 (*get_media_type)(struct txgbe_hw *hw);
593 s32 (*identify)(struct txgbe_hw *hw);
594 s32 (*identify_sfp)(struct txgbe_hw *hw);
595 s32 (*init)(struct txgbe_hw *hw);
596 s32 (*reset)(struct txgbe_hw *hw);
597 s32 (*read_reg)(struct txgbe_hw *hw, u32 reg_addr,
598 u32 device_type, u16 *phy_data);
599 s32 (*write_reg)(struct txgbe_hw *hw, u32 reg_addr,
600 u32 device_type, u16 phy_data);
601 s32 (*read_reg_mdi)(struct txgbe_hw *hw, u32 reg_addr,
602 u32 device_type, u16 *phy_data);
603 s32 (*write_reg_mdi)(struct txgbe_hw *hw, u32 reg_addr,
604 u32 device_type, u16 phy_data);
605 s32 (*setup_link)(struct txgbe_hw *hw);
606 s32 (*setup_internal_link)(struct txgbe_hw *hw);
607 s32 (*setup_link_speed)(struct txgbe_hw *hw, u32 speed,
608 bool autoneg_wait_to_complete);
609 s32 (*check_link)(struct txgbe_hw *hw, u32 *speed, bool *link_up);
610 s32 (*read_i2c_byte)(struct txgbe_hw *hw, u8 byte_offset,
611 u8 dev_addr, u8 *data);
612 s32 (*write_i2c_byte)(struct txgbe_hw *hw, u8 byte_offset,
613 u8 dev_addr, u8 data);
614 s32 (*read_i2c_sff8472)(struct txgbe_hw *hw, u8 byte_offset,
616 s32 (*read_i2c_eeprom)(struct txgbe_hw *hw, u8 byte_offset,
618 s32 (*write_i2c_eeprom)(struct txgbe_hw *hw, u8 byte_offset,
620 s32 (*check_overtemp)(struct txgbe_hw *hw);
621 s32 (*set_phy_power)(struct txgbe_hw *hw, bool on);
622 s32 (*handle_lasi)(struct txgbe_hw *hw);
623 s32 (*read_i2c_byte_unlocked)(struct txgbe_hw *hw, u8 offset, u8 addr,
625 s32 (*write_i2c_byte_unlocked)(struct txgbe_hw *hw, u8 offset, u8 addr,
628 enum txgbe_phy_type type;
631 enum txgbe_sfp_type sfp_type;
632 bool sfp_setup_needed;
635 u32 phy_semaphore_mask;
637 u32 autoneg_advertised;
638 u32 speeds_supported;
639 enum txgbe_smart_speed smart_speed;
640 bool smart_speed_active;
641 bool multispeed_fiber;
642 bool qsfp_shared_i2c_bus;
647 struct txgbe_mbx_stats {
656 struct txgbe_mbx_info {
657 void (*init_params)(struct txgbe_hw *hw);
658 s32 (*read)(struct txgbe_hw *hw, u32 *msg, u16 size, u16 vf_number);
659 s32 (*write)(struct txgbe_hw *hw, u32 *msg, u16 size, u16 vf_number);
660 s32 (*read_posted)(struct txgbe_hw *hw, u32 *msg, u16 size,
662 s32 (*write_posted)(struct txgbe_hw *hw, u32 *msg, u16 size,
664 s32 (*check_for_msg)(struct txgbe_hw *hw, u16 mbx_id);
665 s32 (*check_for_ack)(struct txgbe_hw *hw, u16 mbx_id);
666 s32 (*check_for_rst)(struct txgbe_hw *hw, u16 mbx_id);
668 struct txgbe_mbx_stats stats;
685 struct txgbe_mac_info mac;
686 struct txgbe_addr_filter_info addr_ctrl;
687 struct txgbe_fc_info fc;
688 struct txgbe_phy_info phy;
689 struct txgbe_link_info link;
690 struct txgbe_rom_info rom;
691 struct txgbe_flash_info flash;
692 struct txgbe_bus_info bus;
693 struct txgbe_mbx_info mbx;
696 u16 subsystem_device_id;
697 u16 subsystem_vendor_id;
699 bool adapter_stopped;
700 bool allow_unsupported_sfp;
701 bool need_crosstalk_fix;
709 enum txgbe_link_status {
710 TXGBE_LINK_STATUS_NONE = 0,
711 TXGBE_LINK_STATUS_KX,
712 TXGBE_LINK_STATUS_KX4
714 enum txgbe_reset_type {
720 u32 q_rx_regs[128 * 4];
721 u32 q_tx_regs[128 * 4];
728 u64 rx_qp_mc_packets;
729 } qp_last[TXGBE_MAX_QP];
732 #include "txgbe_regs.h"
733 #include "txgbe_dummy.h"
735 #endif /* _TXGBE_TYPE_H_ */