drivers/net/txgbe/txgbe_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2015-2020
   3  */
   4
   5 #include <stdio.h>
   6 #include <errno.h>
   7 #include <stdint.h>
   8 #include <string.h>
   9 #include <rte_common.h>
  10 #include <rte_ethdev_pci.h>
  11
  12 #include <rte_interrupts.h>
  13 #include <rte_log.h>
  14 #include <rte_debug.h>
  15 #include <rte_pci.h>
  16 #include <rte_memory.h>
  17 #include <rte_eal.h>
  18 #include <rte_alarm.h>
  19
  20 #include "txgbe_logs.h"
  21 #include "base/txgbe.h"
  22 #include "txgbe_ethdev.h"
  23 #include "txgbe_rxtx.h"
  24 #include "txgbe_regs_group.h"
  25
  26 static const struct reg_info txgbe_regs_general[] = {
  27         {TXGBE_RST, 1, 1, "TXGBE_RST"},
  28         {TXGBE_STAT, 1, 1, "TXGBE_STAT"},
  29         {TXGBE_PORTCTL, 1, 1, "TXGBE_PORTCTL"},
  30         {TXGBE_SDP, 1, 1, "TXGBE_SDP"},
  31         {TXGBE_SDPCTL, 1, 1, "TXGBE_SDPCTL"},
  32         {TXGBE_LEDCTL, 1, 1, "TXGBE_LEDCTL"},
  33         {0, 0, 0, ""}
  34 };
  35
  36 static const struct reg_info txgbe_regs_nvm[] = {
  37         {0, 0, 0, ""}
  38 };
  39
  40 static const struct reg_info txgbe_regs_interrupt[] = {
  41         {0, 0, 0, ""}
  42 };
  43
  44 static const struct reg_info txgbe_regs_fctl_others[] = {
  45         {0, 0, 0, ""}
  46 };
  47
  48 static const struct reg_info txgbe_regs_rxdma[] = {
  49         {0, 0, 0, ""}
  50 };
  51
  52 static const struct reg_info txgbe_regs_rx[] = {
  53         {0, 0, 0, ""}
  54 };
  55
  56 static struct reg_info txgbe_regs_tx[] = {
  57         {0, 0, 0, ""}
  58 };
  59
  60 static const struct reg_info txgbe_regs_wakeup[] = {
  61         {0, 0, 0, ""}
  62 };
  63
  64 static const struct reg_info txgbe_regs_dcb[] = {
  65         {0, 0, 0, ""}
  66 };
  67
  68 static const struct reg_info txgbe_regs_mac[] = {
  69         {0, 0, 0, ""}
  70 };
  71
  72 static const struct reg_info txgbe_regs_diagnostic[] = {
  73         {0, 0, 0, ""},
  74 };
  75
  76 /* PF registers */
  77 static const struct reg_info *txgbe_regs_others[] = {
  78                                 txgbe_regs_general,
  79                                 txgbe_regs_nvm,
  80                                 txgbe_regs_interrupt,
  81                                 txgbe_regs_fctl_others,
  82                                 txgbe_regs_rxdma,
  83                                 txgbe_regs_rx,
  84                                 txgbe_regs_tx,
  85                                 txgbe_regs_wakeup,
  86                                 txgbe_regs_dcb,
  87                                 txgbe_regs_mac,
  88                                 txgbe_regs_diagnostic,
  89                                 NULL};
  90
  91 static int txgbe_fdir_filter_init(struct rte_eth_dev *eth_dev);
  92 static int txgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev);
  93 static int txgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev);
  94 static int txgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev);
  95 static int  txgbe_dev_set_link_up(struct rte_eth_dev *dev);
  96 static int  txgbe_dev_set_link_down(struct rte_eth_dev *dev);
  97 static int txgbe_dev_close(struct rte_eth_dev *dev);
  98 static int txgbe_dev_link_update(struct rte_eth_dev *dev,
  99                                 int wait_to_complete);
 100 static int txgbe_dev_stats_reset(struct rte_eth_dev *dev);
 101 static void txgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
 102 static void txgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev,
 103                                         uint16_t queue);
 104
 105 static void txgbe_dev_link_status_print(struct rte_eth_dev *dev);
 106 static int txgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on);
 107 static int txgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev);
 108 static int txgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
 109 static int txgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
 110 static int txgbe_dev_interrupt_action(struct rte_eth_dev *dev,
 111                                       struct rte_intr_handle *handle);
 112 static void txgbe_dev_interrupt_handler(void *param);
 113 static void txgbe_dev_interrupt_delayed_handler(void *param);
 114 static void txgbe_configure_msix(struct rte_eth_dev *dev);
 115
 116 static int txgbe_filter_restore(struct rte_eth_dev *dev);
 117 static void txgbe_l2_tunnel_conf(struct rte_eth_dev *dev);
 118
 119 #define TXGBE_SET_HWSTRIP(h, q) do {\
 120                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 121                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 122                 (h)->bitmap[idx] |= 1 << bit;\
 123         } while (0)
 124
 125 #define TXGBE_CLEAR_HWSTRIP(h, q) do {\
 126                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 127                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 128                 (h)->bitmap[idx] &= ~(1 << bit);\
 129         } while (0)
 130
 131 #define TXGBE_GET_HWSTRIP(h, q, r) do {\
 132                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 133                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 134                 (r) = (h)->bitmap[idx] >> bit & 1;\
 135         } while (0)
 136
 137 /*
 138  * The set of PCI devices this driver supports
 139  */
 140 static const struct rte_pci_id pci_id_txgbe_map[] = {
 141         { RTE_PCI_DEVICE(PCI_VENDOR_ID_WANGXUN, TXGBE_DEV_ID_RAPTOR_SFP) },
 142         { RTE_PCI_DEVICE(PCI_VENDOR_ID_WANGXUN, TXGBE_DEV_ID_WX1820_SFP) },
 143         { .vendor_id = 0, /* sentinel */ },
 144 };
 145
 146 static const struct rte_eth_desc_lim rx_desc_lim = {
 147         .nb_max = TXGBE_RING_DESC_MAX,
 148         .nb_min = TXGBE_RING_DESC_MIN,
 149         .nb_align = TXGBE_RXD_ALIGN,
 150 };
 151
 152 static const struct rte_eth_desc_lim tx_desc_lim = {
 153         .nb_max = TXGBE_RING_DESC_MAX,
 154         .nb_min = TXGBE_RING_DESC_MIN,
 155         .nb_align = TXGBE_TXD_ALIGN,
 156         .nb_seg_max = TXGBE_TX_MAX_SEG,
 157         .nb_mtu_seg_max = TXGBE_TX_MAX_SEG,
 158 };
 159
 160 static const struct eth_dev_ops txgbe_eth_dev_ops;
 161
 162 #define HW_XSTAT(m) {#m, offsetof(struct txgbe_hw_stats, m)}
 163 #define HW_XSTAT_NAME(m, n) {n, offsetof(struct txgbe_hw_stats, m)}
 164 static const struct rte_txgbe_xstats_name_off rte_txgbe_stats_strings[] = {
 165         /* MNG RxTx */
 166         HW_XSTAT(mng_bmc2host_packets),
 167         HW_XSTAT(mng_host2bmc_packets),
 168         /* Basic RxTx */
 169         HW_XSTAT(rx_packets),
 170         HW_XSTAT(tx_packets),
 171         HW_XSTAT(rx_bytes),
 172         HW_XSTAT(tx_bytes),
 173         HW_XSTAT(rx_total_bytes),
 174         HW_XSTAT(rx_total_packets),
 175         HW_XSTAT(tx_total_packets),
 176         HW_XSTAT(rx_total_missed_packets),
 177         HW_XSTAT(rx_broadcast_packets),
 178         HW_XSTAT(rx_multicast_packets),
 179         HW_XSTAT(rx_management_packets),
 180         HW_XSTAT(tx_management_packets),
 181         HW_XSTAT(rx_management_dropped),
 182
 183         /* Basic Error */
 184         HW_XSTAT(rx_crc_errors),
 185         HW_XSTAT(rx_illegal_byte_errors),
 186         HW_XSTAT(rx_error_bytes),
 187         HW_XSTAT(rx_mac_short_packet_dropped),
 188         HW_XSTAT(rx_length_errors),
 189         HW_XSTAT(rx_undersize_errors),
 190         HW_XSTAT(rx_fragment_errors),
 191         HW_XSTAT(rx_oversize_errors),
 192         HW_XSTAT(rx_jabber_errors),
 193         HW_XSTAT(rx_l3_l4_xsum_error),
 194         HW_XSTAT(mac_local_errors),
 195         HW_XSTAT(mac_remote_errors),
 196
 197         /* Flow Director */
 198         HW_XSTAT(flow_director_added_filters),
 199         HW_XSTAT(flow_director_removed_filters),
 200         HW_XSTAT(flow_director_filter_add_errors),
 201         HW_XSTAT(flow_director_filter_remove_errors),
 202         HW_XSTAT(flow_director_matched_filters),
 203         HW_XSTAT(flow_director_missed_filters),
 204
 205         /* FCoE */
 206         HW_XSTAT(rx_fcoe_crc_errors),
 207         HW_XSTAT(rx_fcoe_mbuf_allocation_errors),
 208         HW_XSTAT(rx_fcoe_dropped),
 209         HW_XSTAT(rx_fcoe_packets),
 210         HW_XSTAT(tx_fcoe_packets),
 211         HW_XSTAT(rx_fcoe_bytes),
 212         HW_XSTAT(tx_fcoe_bytes),
 213         HW_XSTAT(rx_fcoe_no_ddp),
 214         HW_XSTAT(rx_fcoe_no_ddp_ext_buff),
 215
 216         /* MACSEC */
 217         HW_XSTAT(tx_macsec_pkts_untagged),
 218         HW_XSTAT(tx_macsec_pkts_encrypted),
 219         HW_XSTAT(tx_macsec_pkts_protected),
 220         HW_XSTAT(tx_macsec_octets_encrypted),
 221         HW_XSTAT(tx_macsec_octets_protected),
 222         HW_XSTAT(rx_macsec_pkts_untagged),
 223         HW_XSTAT(rx_macsec_pkts_badtag),
 224         HW_XSTAT(rx_macsec_pkts_nosci),
 225         HW_XSTAT(rx_macsec_pkts_unknownsci),
 226         HW_XSTAT(rx_macsec_octets_decrypted),
 227         HW_XSTAT(rx_macsec_octets_validated),
 228         HW_XSTAT(rx_macsec_sc_pkts_unchecked),
 229         HW_XSTAT(rx_macsec_sc_pkts_delayed),
 230         HW_XSTAT(rx_macsec_sc_pkts_late),
 231         HW_XSTAT(rx_macsec_sa_pkts_ok),
 232         HW_XSTAT(rx_macsec_sa_pkts_invalid),
 233         HW_XSTAT(rx_macsec_sa_pkts_notvalid),
 234         HW_XSTAT(rx_macsec_sa_pkts_unusedsa),
 235         HW_XSTAT(rx_macsec_sa_pkts_notusingsa),
 236
 237         /* MAC RxTx */
 238         HW_XSTAT(rx_size_64_packets),
 239         HW_XSTAT(rx_size_65_to_127_packets),
 240         HW_XSTAT(rx_size_128_to_255_packets),
 241         HW_XSTAT(rx_size_256_to_511_packets),
 242         HW_XSTAT(rx_size_512_to_1023_packets),
 243         HW_XSTAT(rx_size_1024_to_max_packets),
 244         HW_XSTAT(tx_size_64_packets),
 245         HW_XSTAT(tx_size_65_to_127_packets),
 246         HW_XSTAT(tx_size_128_to_255_packets),
 247         HW_XSTAT(tx_size_256_to_511_packets),
 248         HW_XSTAT(tx_size_512_to_1023_packets),
 249         HW_XSTAT(tx_size_1024_to_max_packets),
 250
 251         /* Flow Control */
 252         HW_XSTAT(tx_xon_packets),
 253         HW_XSTAT(rx_xon_packets),
 254         HW_XSTAT(tx_xoff_packets),
 255         HW_XSTAT(rx_xoff_packets),
 256
 257         HW_XSTAT_NAME(tx_xon_packets, "tx_flow_control_xon_packets"),
 258         HW_XSTAT_NAME(rx_xon_packets, "rx_flow_control_xon_packets"),
 259         HW_XSTAT_NAME(tx_xoff_packets, "tx_flow_control_xoff_packets"),
 260         HW_XSTAT_NAME(rx_xoff_packets, "rx_flow_control_xoff_packets"),
 261 };
 262
 263 #define TXGBE_NB_HW_STATS (sizeof(rte_txgbe_stats_strings) / \
 264                            sizeof(rte_txgbe_stats_strings[0]))
 265
 266 /* Per-priority statistics */
 267 #define UP_XSTAT(m) {#m, offsetof(struct txgbe_hw_stats, up[0].m)}
 268 static const struct rte_txgbe_xstats_name_off rte_txgbe_up_strings[] = {
 269         UP_XSTAT(rx_up_packets),
 270         UP_XSTAT(tx_up_packets),
 271         UP_XSTAT(rx_up_bytes),
 272         UP_XSTAT(tx_up_bytes),
 273         UP_XSTAT(rx_up_drop_packets),
 274
 275         UP_XSTAT(tx_up_xon_packets),
 276         UP_XSTAT(rx_up_xon_packets),
 277         UP_XSTAT(tx_up_xoff_packets),
 278         UP_XSTAT(rx_up_xoff_packets),
 279         UP_XSTAT(rx_up_dropped),
 280         UP_XSTAT(rx_up_mbuf_alloc_errors),
 281         UP_XSTAT(tx_up_xon2off_packets),
 282 };
 283
 284 #define TXGBE_NB_UP_STATS (sizeof(rte_txgbe_up_strings) / \
 285                            sizeof(rte_txgbe_up_strings[0]))
 286
 287 /* Per-queue statistics */
 288 #define QP_XSTAT(m) {#m, offsetof(struct txgbe_hw_stats, qp[0].m)}
 289 static const struct rte_txgbe_xstats_name_off rte_txgbe_qp_strings[] = {
 290         QP_XSTAT(rx_qp_packets),
 291         QP_XSTAT(tx_qp_packets),
 292         QP_XSTAT(rx_qp_bytes),
 293         QP_XSTAT(tx_qp_bytes),
 294         QP_XSTAT(rx_qp_mc_packets),
 295 };
 296
 297 #define TXGBE_NB_QP_STATS (sizeof(rte_txgbe_qp_strings) / \
 298                            sizeof(rte_txgbe_qp_strings[0]))
 299
 300 static inline int
 301 txgbe_is_sfp(struct txgbe_hw *hw)
 302 {
 303         switch (hw->phy.type) {
 304         case txgbe_phy_sfp_avago:
 305         case txgbe_phy_sfp_ftl:
 306         case txgbe_phy_sfp_intel:
 307         case txgbe_phy_sfp_unknown:
 308         case txgbe_phy_sfp_tyco_passive:
 309         case txgbe_phy_sfp_unknown_passive:
 310                 return 1;
 311         default:
 312                 return 0;
 313         }
 314 }
 315
 316 static inline int32_t
 317 txgbe_pf_reset_hw(struct txgbe_hw *hw)
 318 {
 319         uint32_t ctrl_ext;
 320         int32_t status;
 321
 322         status = hw->mac.reset_hw(hw);
 323
 324         ctrl_ext = rd32(hw, TXGBE_PORTCTL);
 325         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 326         ctrl_ext |= TXGBE_PORTCTL_RSTDONE;
 327         wr32(hw, TXGBE_PORTCTL, ctrl_ext);
 328         txgbe_flush(hw);
 329
 330         if (status == TXGBE_ERR_SFP_NOT_PRESENT)
 331                 status = 0;
 332         return status;
 333 }
 334
 335 static inline void
 336 txgbe_enable_intr(struct rte_eth_dev *dev)
 337 {
 338         struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);
 339         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
 340
 341         wr32(hw, TXGBE_IENMISC, intr->mask_misc);
 342         wr32(hw, TXGBE_IMC(0), TXGBE_IMC_MASK);
 343         wr32(hw, TXGBE_IMC(1), TXGBE_IMC_MASK);
 344         txgbe_flush(hw);
 345 }
 346
 347 static void
 348 txgbe_disable_intr(struct txgbe_hw *hw)
 349 {
 350         PMD_INIT_FUNC_TRACE();
 351
 352         wr32(hw, TXGBE_IENMISC, ~BIT_MASK32);
 353         wr32(hw, TXGBE_IMS(0), TXGBE_IMC_MASK);
 354         wr32(hw, TXGBE_IMS(1), TXGBE_IMC_MASK);
 355         txgbe_flush(hw);
 356 }
 357
 358 static int
 359 txgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 360                                   uint16_t queue_id,
 361                                   uint8_t stat_idx,
 362                                   uint8_t is_rx)
 363 {
 364         struct txgbe_hw *hw = TXGBE_DEV_HW(eth_dev);
 365         struct txgbe_stat_mappings *stat_mappings =
 366                 TXGBE_DEV_STAT_MAPPINGS(eth_dev);
 367         uint32_t qsmr_mask = 0;
 368         uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
 369         uint32_t q_map;
 370         uint8_t n, offset;
 371
 372         if (hw->mac.type != txgbe_mac_raptor)
 373                 return -ENOSYS;
 374
 375         if (stat_idx & !QMAP_FIELD_RESERVED_BITS_MASK)
 376                 return -EIO;
 377
 378         PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d",
 379                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 380                      queue_id, stat_idx);
 381
 382         n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
 383         if (n >= TXGBE_NB_STAT_MAPPING) {
 384                 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
 385                 return -EIO;
 386         }
 387         offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
 388
 389         /* Now clear any previous stat_idx set */
 390         clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 391         if (!is_rx)
 392                 stat_mappings->tqsm[n] &= ~clearing_mask;
 393         else
 394                 stat_mappings->rqsm[n] &= ~clearing_mask;
 395
 396         q_map = (uint32_t)stat_idx;
 397         q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
 398         qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 399         if (!is_rx)
 400                 stat_mappings->tqsm[n] |= qsmr_mask;
 401         else
 402                 stat_mappings->rqsm[n] |= qsmr_mask;
 403
 404         PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d",
 405                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 406                      queue_id, stat_idx);
 407         PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
 408                      is_rx ? stat_mappings->rqsm[n] : stat_mappings->tqsm[n]);
 409         return 0;
 410 }
 411
 412 static void
 413 txgbe_dcb_init(struct txgbe_hw *hw, struct txgbe_dcb_config *dcb_config)
 414 {
 415         int i;
 416         u8 bwgp;
 417         struct txgbe_dcb_tc_config *tc;
 418
 419         UNREFERENCED_PARAMETER(hw);
 420
 421         dcb_config->num_tcs.pg_tcs = TXGBE_DCB_TC_MAX;
 422         dcb_config->num_tcs.pfc_tcs = TXGBE_DCB_TC_MAX;
 423         bwgp = (u8)(100 / TXGBE_DCB_TC_MAX);
 424         for (i = 0; i < TXGBE_DCB_TC_MAX; i++) {
 425                 tc = &dcb_config->tc_config[i];
 426                 tc->path[TXGBE_DCB_TX_CONFIG].bwg_id = i;
 427                 tc->path[TXGBE_DCB_TX_CONFIG].bwg_percent = bwgp + (i & 1);
 428                 tc->path[TXGBE_DCB_RX_CONFIG].bwg_id = i;
 429                 tc->path[TXGBE_DCB_RX_CONFIG].bwg_percent = bwgp + (i & 1);
 430                 tc->pfc = txgbe_dcb_pfc_disabled;
 431         }
 432
 433         /* Initialize default user to priority mapping, UPx->TC0 */
 434         tc = &dcb_config->tc_config[0];
 435         tc->path[TXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
 436         tc->path[TXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
 437         for (i = 0; i < TXGBE_DCB_BWG_MAX; i++) {
 438                 dcb_config->bw_percentage[i][TXGBE_DCB_TX_CONFIG] = 100;
 439                 dcb_config->bw_percentage[i][TXGBE_DCB_RX_CONFIG] = 100;
 440         }
 441         dcb_config->rx_pba_cfg = txgbe_dcb_pba_equal;
 442         dcb_config->pfc_mode_enable = false;
 443         dcb_config->vt_mode = true;
 444         dcb_config->round_robin_enable = false;
 445         /* support all DCB capabilities */
 446         dcb_config->support.capabilities = 0xFF;
 447 }
 448
 449 /*
 450  * Ensure that all locks are released before first NVM or PHY access
 451  */
 452 static void
 453 txgbe_swfw_lock_reset(struct txgbe_hw *hw)
 454 {
 455         uint16_t mask;
 456
 457         /*
 458          * These ones are more tricky since they are common to all ports; but
 459          * swfw_sync retries last long enough (1s) to be almost sure that if
 460          * lock can not be taken it is due to an improper lock of the
 461          * semaphore.
 462          */
 463         mask = TXGBE_MNGSEM_SWPHY |
 464                TXGBE_MNGSEM_SWMBX |
 465                TXGBE_MNGSEM_SWFLASH;
 466         if (hw->mac.acquire_swfw_sync(hw, mask) < 0)
 467                 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
 468
 469         hw->mac.release_swfw_sync(hw, mask);
 470 }
 471
 472 static int
 473 eth_txgbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params __rte_unused)
 474 {
 475         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
 476         struct txgbe_hw *hw = TXGBE_DEV_HW(eth_dev);
 477         struct txgbe_vfta *shadow_vfta = TXGBE_DEV_VFTA(eth_dev);
 478         struct txgbe_hwstrip *hwstrip = TXGBE_DEV_HWSTRIP(eth_dev);
 479         struct txgbe_dcb_config *dcb_config = TXGBE_DEV_DCB_CONFIG(eth_dev);
 480         struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(eth_dev);
 481         struct txgbe_bw_conf *bw_conf = TXGBE_DEV_BW_CONF(eth_dev);
 482         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 483         const struct rte_memzone *mz;
 484         uint32_t ctrl_ext;
 485         uint16_t csum;
 486         int err, i, ret;
 487
 488         PMD_INIT_FUNC_TRACE();
 489
 490         eth_dev->dev_ops = &txgbe_eth_dev_ops;
 491         eth_dev->rx_queue_count       = txgbe_dev_rx_queue_count;
 492         eth_dev->rx_descriptor_status = txgbe_dev_rx_descriptor_status;
 493         eth_dev->tx_descriptor_status = txgbe_dev_tx_descriptor_status;
 494         eth_dev->rx_pkt_burst = &txgbe_recv_pkts;
 495         eth_dev->tx_pkt_burst = &txgbe_xmit_pkts;
 496         eth_dev->tx_pkt_prepare = &txgbe_prep_pkts;
 497
 498         /*
 499          * For secondary processes, we don't initialise any further as primary
 500          * has already done this work. Only check we don't need a different
 501          * RX and TX function.
 502          */
 503         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
 504                 struct txgbe_tx_queue *txq;
 505                 /* TX queue function in primary, set by last queue initialized
 506                  * Tx queue may not initialized by primary process
 507                  */
 508                 if (eth_dev->data->tx_queues) {
 509                         uint16_t nb_tx_queues = eth_dev->data->nb_tx_queues;
 510                         txq = eth_dev->data->tx_queues[nb_tx_queues - 1];
 511                         txgbe_set_tx_function(eth_dev, txq);
 512                 } else {
 513                         /* Use default TX function if we get here */
 514                         PMD_INIT_LOG(NOTICE, "No TX queues configured yet. "
 515                                      "Using default TX function.");
 516                 }
 517
 518                 txgbe_set_rx_function(eth_dev);
 519
 520                 return 0;
 521         }
 522
 523         rte_eth_copy_pci_info(eth_dev, pci_dev);
 524
 525         /* Vendor and Device ID need to be set before init of shared code */
 526         hw->device_id = pci_dev->id.device_id;
 527         hw->vendor_id = pci_dev->id.vendor_id;
 528         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
 529         hw->allow_unsupported_sfp = 1;
 530
 531         /* Reserve memory for interrupt status block */
 532         mz = rte_eth_dma_zone_reserve(eth_dev, "txgbe_driver", -1,
 533                 16, TXGBE_ALIGN, SOCKET_ID_ANY);
 534         if (mz == NULL)
 535                 return -ENOMEM;
 536
 537         hw->isb_dma = TMZ_PADDR(mz);
 538         hw->isb_mem = TMZ_VADDR(mz);
 539
 540         /* Initialize the shared code (base driver) */
 541         err = txgbe_init_shared_code(hw);
 542         if (err != 0) {
 543                 PMD_INIT_LOG(ERR, "Shared code init failed: %d", err);
 544                 return -EIO;
 545         }
 546
 547         /* Unlock any pending hardware semaphore */
 548         txgbe_swfw_lock_reset(hw);
 549
 550         /* Initialize DCB configuration*/
 551         memset(dcb_config, 0, sizeof(struct txgbe_dcb_config));
 552         txgbe_dcb_init(hw, dcb_config);
 553
 554         /* Get Hardware Flow Control setting */
 555         hw->fc.requested_mode = txgbe_fc_full;
 556         hw->fc.current_mode = txgbe_fc_full;
 557         hw->fc.pause_time = TXGBE_FC_PAUSE_TIME;
 558         for (i = 0; i < TXGBE_DCB_TC_MAX; i++) {
 559                 hw->fc.low_water[i] = TXGBE_FC_XON_LOTH;
 560                 hw->fc.high_water[i] = TXGBE_FC_XOFF_HITH;
 561         }
 562         hw->fc.send_xon = 1;
 563
 564         err = hw->rom.init_params(hw);
 565         if (err != 0) {
 566                 PMD_INIT_LOG(ERR, "The EEPROM init failed: %d", err);
 567                 return -EIO;
 568         }
 569
 570         /* Make sure we have a good EEPROM before we read from it */
 571         err = hw->rom.validate_checksum(hw, &csum);
 572         if (err != 0) {
 573                 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", err);
 574                 return -EIO;
 575         }
 576
 577         err = hw->mac.init_hw(hw);
 578
 579         /*
 580          * Devices with copper phys will fail to initialise if txgbe_init_hw()
 581          * is called too soon after the kernel driver unbinding/binding occurs.
 582          * The failure occurs in txgbe_identify_phy() for all devices,
 583          * but for non-copper devies, txgbe_identify_sfp_module() is
 584          * also called. See txgbe_identify_phy(). The reason for the
 585          * failure is not known, and only occuts when virtualisation features
 586          * are disabled in the bios. A delay of 200ms  was found to be enough by
 587          * trial-and-error, and is doubled to be safe.
 588          */
 589         if (err && hw->phy.media_type == txgbe_media_type_copper) {
 590                 rte_delay_ms(200);
 591                 err = hw->mac.init_hw(hw);
 592         }
 593
 594         if (err == TXGBE_ERR_SFP_NOT_PRESENT)
 595                 err = 0;
 596
 597         if (err == TXGBE_ERR_EEPROM_VERSION) {
 598                 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
 599                              "LOM.  Please be aware there may be issues associated "
 600                              "with your hardware.");
 601                 PMD_INIT_LOG(ERR, "If you are experiencing problems "
 602                              "please contact your hardware representative "
 603                              "who provided you with this hardware.");
 604         } else if (err == TXGBE_ERR_SFP_NOT_SUPPORTED) {
 605                 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
 606         }
 607         if (err) {
 608                 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", err);
 609                 return -EIO;
 610         }
 611
 612         /* Reset the hw statistics */
 613         txgbe_dev_stats_reset(eth_dev);
 614
 615         /* disable interrupt */
 616         txgbe_disable_intr(hw);
 617
 618         /* Allocate memory for storing MAC addresses */
 619         eth_dev->data->mac_addrs = rte_zmalloc("txgbe", RTE_ETHER_ADDR_LEN *
 620                                                hw->mac.num_rar_entries, 0);
 621         if (eth_dev->data->mac_addrs == NULL) {
 622                 PMD_INIT_LOG(ERR,
 623                              "Failed to allocate %u bytes needed to store "
 624                              "MAC addresses",
 625                              RTE_ETHER_ADDR_LEN * hw->mac.num_rar_entries);
 626                 return -ENOMEM;
 627         }
 628
 629         /* Copy the permanent MAC address */
 630         rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.perm_addr,
 631                         &eth_dev->data->mac_addrs[0]);
 632
 633         /* Allocate memory for storing hash filter MAC addresses */
 634         eth_dev->data->hash_mac_addrs = rte_zmalloc("txgbe",
 635                         RTE_ETHER_ADDR_LEN * TXGBE_VMDQ_NUM_UC_MAC, 0);
 636         if (eth_dev->data->hash_mac_addrs == NULL) {
 637                 PMD_INIT_LOG(ERR,
 638                              "Failed to allocate %d bytes needed to store MAC addresses",
 639                              RTE_ETHER_ADDR_LEN * TXGBE_VMDQ_NUM_UC_MAC);
 640                 return -ENOMEM;
 641         }
 642
 643         /* initialize the vfta */
 644         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
 645
 646         /* initialize the hw strip bitmap*/
 647         memset(hwstrip, 0, sizeof(*hwstrip));
 648
 649         /* initialize PF if max_vfs not zero */
 650         ret = txgbe_pf_host_init(eth_dev);
 651         if (ret) {
 652                 rte_free(eth_dev->data->mac_addrs);
 653                 eth_dev->data->mac_addrs = NULL;
 654                 rte_free(eth_dev->data->hash_mac_addrs);
 655                 eth_dev->data->hash_mac_addrs = NULL;
 656                 return ret;
 657         }
 658
 659         ctrl_ext = rd32(hw, TXGBE_PORTCTL);
 660         /* let hardware know driver is loaded */
 661         ctrl_ext |= TXGBE_PORTCTL_DRVLOAD;
 662         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 663         ctrl_ext |= TXGBE_PORTCTL_RSTDONE;
 664         wr32(hw, TXGBE_PORTCTL, ctrl_ext);
 665         txgbe_flush(hw);
 666
 667         if (txgbe_is_sfp(hw) && hw->phy.sfp_type != txgbe_sfp_type_not_present)
 668                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
 669                              (int)hw->mac.type, (int)hw->phy.type,
 670                              (int)hw->phy.sfp_type);
 671         else
 672                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
 673                              (int)hw->mac.type, (int)hw->phy.type);
 674
 675         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
 676                      eth_dev->data->port_id, pci_dev->id.vendor_id,
 677                      pci_dev->id.device_id);
 678
 679         rte_intr_callback_register(intr_handle,
 680                                    txgbe_dev_interrupt_handler, eth_dev);
 681
 682         /* enable uio/vfio intr/eventfd mapping */
 683         rte_intr_enable(intr_handle);
 684
 685         /* enable support intr */
 686         txgbe_enable_intr(eth_dev);
 687
 688         /* initialize filter info */
 689         memset(filter_info, 0,
 690                sizeof(struct txgbe_filter_info));
 691
 692         /* initialize 5tuple filter list */
 693         TAILQ_INIT(&filter_info->fivetuple_list);
 694
 695         /* initialize flow director filter list & hash */
 696         txgbe_fdir_filter_init(eth_dev);
 697
 698         /* initialize l2 tunnel filter list & hash */
 699         txgbe_l2_tn_filter_init(eth_dev);
 700
 701         /* initialize flow filter lists */
 702         txgbe_filterlist_init();
 703
 704         /* initialize bandwidth configuration info */
 705         memset(bw_conf, 0, sizeof(struct txgbe_bw_conf));
 706
 707         /* initialize Traffic Manager configuration */
 708         txgbe_tm_conf_init(eth_dev);
 709
 710         return 0;
 711 }
 712
 713 static int
 714 eth_txgbe_dev_uninit(struct rte_eth_dev *eth_dev)
 715 {
 716         PMD_INIT_FUNC_TRACE();
 717
 718         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 719                 return 0;
 720
 721         txgbe_dev_close(eth_dev);
 722
 723         return 0;
 724 }
 725
 726 static int txgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev)
 727 {
 728         struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(eth_dev);
 729         struct txgbe_5tuple_filter *p_5tuple;
 730
 731         while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) {
 732                 TAILQ_REMOVE(&filter_info->fivetuple_list,
 733                              p_5tuple,
 734                              entries);
 735                 rte_free(p_5tuple);
 736         }
 737         memset(filter_info->fivetuple_mask, 0,
 738                sizeof(uint32_t) * TXGBE_5TUPLE_ARRAY_SIZE);
 739
 740         return 0;
 741 }
 742
 743 static int txgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev)
 744 {
 745         struct txgbe_hw_fdir_info *fdir_info = TXGBE_DEV_FDIR(eth_dev);
 746         struct txgbe_fdir_filter *fdir_filter;
 747
 748         if (fdir_info->hash_map)
 749                 rte_free(fdir_info->hash_map);
 750         if (fdir_info->hash_handle)
 751                 rte_hash_free(fdir_info->hash_handle);
 752
 753         while ((fdir_filter = TAILQ_FIRST(&fdir_info->fdir_list))) {
 754                 TAILQ_REMOVE(&fdir_info->fdir_list,
 755                              fdir_filter,
 756                              entries);
 757                 rte_free(fdir_filter);
 758         }
 759
 760         return 0;
 761 }
 762
 763 static int txgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev)
 764 {
 765         struct txgbe_l2_tn_info *l2_tn_info = TXGBE_DEV_L2_TN(eth_dev);
 766         struct txgbe_l2_tn_filter *l2_tn_filter;
 767
 768         if (l2_tn_info->hash_map)
 769                 rte_free(l2_tn_info->hash_map);
 770         if (l2_tn_info->hash_handle)
 771                 rte_hash_free(l2_tn_info->hash_handle);
 772
 773         while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
 774                 TAILQ_REMOVE(&l2_tn_info->l2_tn_list,
 775                              l2_tn_filter,
 776                              entries);
 777                 rte_free(l2_tn_filter);
 778         }
 779
 780         return 0;
 781 }
 782
 783 static int txgbe_fdir_filter_init(struct rte_eth_dev *eth_dev)
 784 {
 785         struct txgbe_hw_fdir_info *fdir_info = TXGBE_DEV_FDIR(eth_dev);
 786         char fdir_hash_name[RTE_HASH_NAMESIZE];
 787         struct rte_hash_parameters fdir_hash_params = {
 788                 .name = fdir_hash_name,
 789                 .entries = TXGBE_MAX_FDIR_FILTER_NUM,
 790                 .key_len = sizeof(struct txgbe_atr_input),
 791                 .hash_func = rte_hash_crc,
 792                 .hash_func_init_val = 0,
 793                 .socket_id = rte_socket_id(),
 794         };
 795
 796         TAILQ_INIT(&fdir_info->fdir_list);
 797         snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
 798                  "fdir_%s", TDEV_NAME(eth_dev));
 799         fdir_info->hash_handle = rte_hash_create(&fdir_hash_params);
 800         if (!fdir_info->hash_handle) {
 801                 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
 802                 return -EINVAL;
 803         }
 804         fdir_info->hash_map = rte_zmalloc("txgbe",
 805                                           sizeof(struct txgbe_fdir_filter *) *
 806                                           TXGBE_MAX_FDIR_FILTER_NUM,
 807                                           0);
 808         if (!fdir_info->hash_map) {
 809                 PMD_INIT_LOG(ERR,
 810                              "Failed to allocate memory for fdir hash map!");
 811                 return -ENOMEM;
 812         }
 813         fdir_info->mask_added = FALSE;
 814
 815         return 0;
 816 }
 817
 818 static int txgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev)
 819 {
 820         struct txgbe_l2_tn_info *l2_tn_info = TXGBE_DEV_L2_TN(eth_dev);
 821         char l2_tn_hash_name[RTE_HASH_NAMESIZE];
 822         struct rte_hash_parameters l2_tn_hash_params = {
 823                 .name = l2_tn_hash_name,
 824                 .entries = TXGBE_MAX_L2_TN_FILTER_NUM,
 825                 .key_len = sizeof(struct txgbe_l2_tn_key),
 826                 .hash_func = rte_hash_crc,
 827                 .hash_func_init_val = 0,
 828                 .socket_id = rte_socket_id(),
 829         };
 830
 831         TAILQ_INIT(&l2_tn_info->l2_tn_list);
 832         snprintf(l2_tn_hash_name, RTE_HASH_NAMESIZE,
 833                  "l2_tn_%s", TDEV_NAME(eth_dev));
 834         l2_tn_info->hash_handle = rte_hash_create(&l2_tn_hash_params);
 835         if (!l2_tn_info->hash_handle) {
 836                 PMD_INIT_LOG(ERR, "Failed to create L2 TN hash table!");
 837                 return -EINVAL;
 838         }
 839         l2_tn_info->hash_map = rte_zmalloc("txgbe",
 840                                    sizeof(struct txgbe_l2_tn_filter *) *
 841                                    TXGBE_MAX_L2_TN_FILTER_NUM,
 842                                    0);
 843         if (!l2_tn_info->hash_map) {
 844                 PMD_INIT_LOG(ERR,
 845                         "Failed to allocate memory for L2 TN hash map!");
 846                 return -ENOMEM;
 847         }
 848         l2_tn_info->e_tag_en = FALSE;
 849         l2_tn_info->e_tag_fwd_en = FALSE;
 850         l2_tn_info->e_tag_ether_type = RTE_ETHER_TYPE_ETAG;
 851
 852         return 0;
 853 }
 854
 855 static int
 856 eth_txgbe_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
 857                 struct rte_pci_device *pci_dev)
 858 {
 859         struct rte_eth_dev *pf_ethdev;
 860         struct rte_eth_devargs eth_da;
 861         int retval;
 862
 863         if (pci_dev->device.devargs) {
 864                 retval = rte_eth_devargs_parse(pci_dev->device.devargs->args,
 865                                 &eth_da);
 866                 if (retval)
 867                         return retval;
 868         } else {
 869                 memset(&eth_da, 0, sizeof(eth_da));
 870         }
 871
 872         retval = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
 873                         sizeof(struct txgbe_adapter),
 874                         eth_dev_pci_specific_init, pci_dev,
 875                         eth_txgbe_dev_init, NULL);
 876
 877         if (retval || eth_da.nb_representor_ports < 1)
 878                 return retval;
 879
 880         pf_ethdev = rte_eth_dev_allocated(pci_dev->device.name);
 881         if (pf_ethdev == NULL)
 882                 return -ENODEV;
 883
 884         return 0;
 885 }
 886
 887 static int eth_txgbe_pci_remove(struct rte_pci_device *pci_dev)
 888 {
 889         struct rte_eth_dev *ethdev;
 890
 891         ethdev = rte_eth_dev_allocated(pci_dev->device.name);
 892         if (!ethdev)
 893                 return -ENODEV;
 894
 895         return rte_eth_dev_destroy(ethdev, eth_txgbe_dev_uninit);
 896 }
 897
 898 static struct rte_pci_driver rte_txgbe_pmd = {
 899         .id_table = pci_id_txgbe_map,
 900         .drv_flags = RTE_PCI_DRV_NEED_MAPPING |
 901                      RTE_PCI_DRV_INTR_LSC,
 902         .probe = eth_txgbe_pci_probe,
 903         .remove = eth_txgbe_pci_remove,
 904 };
 905
 906 static int
 907 txgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
 908 {
 909         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
 910         struct txgbe_vfta *shadow_vfta = TXGBE_DEV_VFTA(dev);
 911         uint32_t vfta;
 912         uint32_t vid_idx;
 913         uint32_t vid_bit;
 914
 915         vid_idx = (uint32_t)((vlan_id >> 5) & 0x7F);
 916         vid_bit = (uint32_t)(1 << (vlan_id & 0x1F));
 917         vfta = rd32(hw, TXGBE_VLANTBL(vid_idx));
 918         if (on)
 919                 vfta |= vid_bit;
 920         else
 921                 vfta &= ~vid_bit;
 922         wr32(hw, TXGBE_VLANTBL(vid_idx), vfta);
 923
 924         /* update local VFTA copy */
 925         shadow_vfta->vfta[vid_idx] = vfta;
 926
 927         return 0;
 928 }
 929
 930 static void
 931 txgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
 932 {
 933         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
 934         struct txgbe_rx_queue *rxq;
 935         bool restart;
 936         uint32_t rxcfg, rxbal, rxbah;
 937
 938         if (on)
 939                 txgbe_vlan_hw_strip_enable(dev, queue);
 940         else
 941                 txgbe_vlan_hw_strip_disable(dev, queue);
 942
 943         rxq = dev->data->rx_queues[queue];
 944         rxbal = rd32(hw, TXGBE_RXBAL(rxq->reg_idx));
 945         rxbah = rd32(hw, TXGBE_RXBAH(rxq->reg_idx));
 946         rxcfg = rd32(hw, TXGBE_RXCFG(rxq->reg_idx));
 947         if (rxq->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) {
 948                 restart = (rxcfg & TXGBE_RXCFG_ENA) &&
 949                         !(rxcfg & TXGBE_RXCFG_VLAN);
 950                 rxcfg |= TXGBE_RXCFG_VLAN;
 951         } else {
 952                 restart = (rxcfg & TXGBE_RXCFG_ENA) &&
 953                         (rxcfg & TXGBE_RXCFG_VLAN);
 954                 rxcfg &= ~TXGBE_RXCFG_VLAN;
 955         }
 956         rxcfg &= ~TXGBE_RXCFG_ENA;
 957
 958         if (restart) {
 959                 /* set vlan strip for ring */
 960                 txgbe_dev_rx_queue_stop(dev, queue);
 961                 wr32(hw, TXGBE_RXBAL(rxq->reg_idx), rxbal);
 962                 wr32(hw, TXGBE_RXBAH(rxq->reg_idx), rxbah);
 963                 wr32(hw, TXGBE_RXCFG(rxq->reg_idx), rxcfg);
 964                 txgbe_dev_rx_queue_start(dev, queue);
 965         }
 966 }
 967
 968 static int
 969 txgbe_vlan_tpid_set(struct rte_eth_dev *dev,
 970                     enum rte_vlan_type vlan_type,
 971                     uint16_t tpid)
 972 {
 973         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
 974         int ret = 0;
 975         uint32_t portctrl, vlan_ext, qinq;
 976
 977         portctrl = rd32(hw, TXGBE_PORTCTL);
 978
 979         vlan_ext = (portctrl & TXGBE_PORTCTL_VLANEXT);
 980         qinq = vlan_ext && (portctrl & TXGBE_PORTCTL_QINQ);
 981         switch (vlan_type) {
 982         case ETH_VLAN_TYPE_INNER:
 983                 if (vlan_ext) {
 984                         wr32m(hw, TXGBE_VLANCTL,
 985                                 TXGBE_VLANCTL_TPID_MASK,
 986                                 TXGBE_VLANCTL_TPID(tpid));
 987                         wr32m(hw, TXGBE_DMATXCTRL,
 988                                 TXGBE_DMATXCTRL_TPID_MASK,
 989                                 TXGBE_DMATXCTRL_TPID(tpid));
 990                 } else {
 991                         ret = -ENOTSUP;
 992                         PMD_DRV_LOG(ERR, "Inner type is not supported"
 993                                     " by single VLAN");
 994                 }
 995
 996                 if (qinq) {
 997                         wr32m(hw, TXGBE_TAGTPID(0),
 998                                 TXGBE_TAGTPID_LSB_MASK,
 999                                 TXGBE_TAGTPID_LSB(tpid));
1000                 }
1001                 break;
1002         case ETH_VLAN_TYPE_OUTER:
1003                 if (vlan_ext) {
1004                         /* Only the high 16-bits is valid */
1005                         wr32m(hw, TXGBE_EXTAG,
1006                                 TXGBE_EXTAG_VLAN_MASK,
1007                                 TXGBE_EXTAG_VLAN(tpid));
1008                 } else {
1009                         wr32m(hw, TXGBE_VLANCTL,
1010                                 TXGBE_VLANCTL_TPID_MASK,
1011                                 TXGBE_VLANCTL_TPID(tpid));
1012                         wr32m(hw, TXGBE_DMATXCTRL,
1013                                 TXGBE_DMATXCTRL_TPID_MASK,
1014                                 TXGBE_DMATXCTRL_TPID(tpid));
1015                 }
1016
1017                 if (qinq) {
1018                         wr32m(hw, TXGBE_TAGTPID(0),
1019                                 TXGBE_TAGTPID_MSB_MASK,
1020                                 TXGBE_TAGTPID_MSB(tpid));
1021                 }
1022                 break;
1023         default:
1024                 PMD_DRV_LOG(ERR, "Unsupported VLAN type %d", vlan_type);
1025                 return -EINVAL;
1026         }
1027
1028         return ret;
1029 }
1030
1031 void
1032 txgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1033 {
1034         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
1035         uint32_t vlnctrl;
1036
1037         PMD_INIT_FUNC_TRACE();
1038
1039         /* Filter Table Disable */
1040         vlnctrl = rd32(hw, TXGBE_VLANCTL);
1041         vlnctrl &= ~TXGBE_VLANCTL_VFE;
1042         wr32(hw, TXGBE_VLANCTL, vlnctrl);
1043 }
1044
1045 void
1046 txgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1047 {
1048         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
1049         struct txgbe_vfta *shadow_vfta = TXGBE_DEV_VFTA(dev);
1050         uint32_t vlnctrl;
1051         uint16_t i;
1052
1053         PMD_INIT_FUNC_TRACE();
1054
1055         /* Filter Table Enable */
1056         vlnctrl = rd32(hw, TXGBE_VLANCTL);
1057         vlnctrl &= ~TXGBE_VLANCTL_CFIENA;
1058         vlnctrl |= TXGBE_VLANCTL_VFE;
1059         wr32(hw, TXGBE_VLANCTL, vlnctrl);
1060
1061         /* write whatever is in local vfta copy */
1062         for (i = 0; i < TXGBE_VFTA_SIZE; i++)
1063                 wr32(hw, TXGBE_VLANTBL(i), shadow_vfta->vfta[i]);
1064 }
1065
1066 void
1067 txgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1068 {
1069         struct txgbe_hwstrip *hwstrip = TXGBE_DEV_HWSTRIP(dev);
1070         struct txgbe_rx_queue *rxq;
1071
1072         if (queue >= TXGBE_MAX_RX_QUEUE_NUM)
1073                 return;
1074
1075         if (on)
1076                 TXGBE_SET_HWSTRIP(hwstrip, queue);
1077         else
1078                 TXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1079
1080         if (queue >= dev->data->nb_rx_queues)
1081                 return;
1082
1083         rxq = dev->data->rx_queues[queue];
1084
1085         if (on) {
1086                 rxq->vlan_flags = PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
1087                 rxq->offloads |= DEV_RX_OFFLOAD_VLAN_STRIP;
1088         } else {
1089                 rxq->vlan_flags = PKT_RX_VLAN;
1090                 rxq->offloads &= ~DEV_RX_OFFLOAD_VLAN_STRIP;
1091         }
1092 }
1093
1094 static void
1095 txgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
1096 {
1097         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
1098         uint32_t ctrl;
1099
1100         PMD_INIT_FUNC_TRACE();
1101
1102         ctrl = rd32(hw, TXGBE_RXCFG(queue));
1103         ctrl &= ~TXGBE_RXCFG_VLAN;
1104         wr32(hw, TXGBE_RXCFG(queue), ctrl);
1105
1106         /* record those setting for HW strip per queue */
1107         txgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
1108 }
1109
1110 static void
1111 txgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
1112 {
1113         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
1114         uint32_t ctrl;
1115
1116         PMD_INIT_FUNC_TRACE();
1117
1118         ctrl = rd32(hw, TXGBE_RXCFG(queue));
1119         ctrl |= TXGBE_RXCFG_VLAN;
1120         wr32(hw, TXGBE_RXCFG(queue), ctrl);
1121
1122         /* record those setting for HW strip per queue */
1123         txgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
1124 }
1125
1126 static void
1127 txgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
1128 {
1129         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
1130         uint32_t ctrl;
1131
1132         PMD_INIT_FUNC_TRACE();
1133
1134         ctrl = rd32(hw, TXGBE_PORTCTL);
1135         ctrl &= ~TXGBE_PORTCTL_VLANEXT;
1136         ctrl &= ~TXGBE_PORTCTL_QINQ;
1137         wr32(hw, TXGBE_PORTCTL, ctrl);
1138 }
1139
1140 static void
1141 txgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
1142 {
1143         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
1144         struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
1145         struct rte_eth_txmode *txmode = &dev->data->dev_conf.txmode;
1146         uint32_t ctrl;
1147
1148         PMD_INIT_FUNC_TRACE();
1149
1150         ctrl  = rd32(hw, TXGBE_PORTCTL);
1151         ctrl |= TXGBE_PORTCTL_VLANEXT;
1152         if (rxmode->offloads & DEV_RX_OFFLOAD_QINQ_STRIP ||
1153             txmode->offloads & DEV_TX_OFFLOAD_QINQ_INSERT)
1154                 ctrl |= TXGBE_PORTCTL_QINQ;
1155         wr32(hw, TXGBE_PORTCTL, ctrl);
1156 }
1157
1158 void
1159 txgbe_vlan_hw_strip_config(struct rte_eth_dev *dev)
1160 {
1161         struct txgbe_rx_queue *rxq;
1162         uint16_t i;
1163
1164         PMD_INIT_FUNC_TRACE();
1165
1166         for (i = 0; i < dev->data->nb_rx_queues; i++) {
1167                 rxq = dev->data->rx_queues[i];
1168
1169                 if (rxq->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1170                         txgbe_vlan_strip_queue_set(dev, i, 1);
1171                 else
1172                         txgbe_vlan_strip_queue_set(dev, i, 0);
1173         }
1174 }
1175
1176 void
1177 txgbe_config_vlan_strip_on_all_queues(struct rte_eth_dev *dev, int mask)
1178 {
1179         uint16_t i;
1180         struct rte_eth_rxmode *rxmode;
1181         struct txgbe_rx_queue *rxq;
1182
1183         if (mask & ETH_VLAN_STRIP_MASK) {
1184                 rxmode = &dev->data->dev_conf.rxmode;
1185                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1186                         for (i = 0; i < dev->data->nb_rx_queues; i++) {
1187                                 rxq = dev->data->rx_queues[i];
1188                                 rxq->offloads |= DEV_RX_OFFLOAD_VLAN_STRIP;
1189                         }
1190                 else
1191                         for (i = 0; i < dev->data->nb_rx_queues; i++) {
1192                                 rxq = dev->data->rx_queues[i];
1193                                 rxq->offloads &= ~DEV_RX_OFFLOAD_VLAN_STRIP;
1194                         }
1195         }
1196 }
1197
1198 static int
1199 txgbe_vlan_offload_config(struct rte_eth_dev *dev, int mask)
1200 {
1201         struct rte_eth_rxmode *rxmode;
1202         rxmode = &dev->data->dev_conf.rxmode;
1203
1204         if (mask & ETH_VLAN_STRIP_MASK)
1205                 txgbe_vlan_hw_strip_config(dev);
1206
1207         if (mask & ETH_VLAN_FILTER_MASK) {
1208                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
1209                         txgbe_vlan_hw_filter_enable(dev);
1210                 else
1211                         txgbe_vlan_hw_filter_disable(dev);
1212         }
1213
1214         if (mask & ETH_VLAN_EXTEND_MASK) {
1215                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
1216                         txgbe_vlan_hw_extend_enable(dev);
1217                 else
1218                         txgbe_vlan_hw_extend_disable(dev);
1219         }
1220
1221         return 0;
1222 }
1223
1224 static int
1225 txgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1226 {
1227         txgbe_config_vlan_strip_on_all_queues(dev, mask);
1228
1229         txgbe_vlan_offload_config(dev, mask);
1230
1231         return 0;
1232 }
1233
1234 static void
1235 txgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1236 {
1237         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
1238         /* VLNCTL: enable vlan filtering and allow all vlan tags through */
1239         uint32_t vlanctrl = rd32(hw, TXGBE_VLANCTL);
1240
1241         vlanctrl |= TXGBE_VLANCTL_VFE; /* enable vlan filters */
1242         wr32(hw, TXGBE_VLANCTL, vlanctrl);
1243 }
1244
1245 static int
1246 txgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q)
1247 {
1248         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1249
1250         switch (nb_rx_q) {
1251         case 1:
1252         case 2:
1253                 RTE_ETH_DEV_SRIOV(dev).active = ETH_64_POOLS;
1254                 break;
1255         case 4:
1256                 RTE_ETH_DEV_SRIOV(dev).active = ETH_32_POOLS;
1257                 break;
1258         default:
1259                 return -EINVAL;
1260         }
1261
1262         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool =
1263                 TXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
1264         RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx =
1265                 pci_dev->max_vfs * RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
1266         return 0;
1267 }
1268
1269 static int
1270 txgbe_check_mq_mode(struct rte_eth_dev *dev)
1271 {
1272         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
1273         uint16_t nb_rx_q = dev->data->nb_rx_queues;
1274         uint16_t nb_tx_q = dev->data->nb_tx_queues;
1275
1276         if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
1277                 /* check multi-queue mode */
1278                 switch (dev_conf->rxmode.mq_mode) {
1279                 case ETH_MQ_RX_VMDQ_DCB:
1280                         PMD_INIT_LOG(INFO, "ETH_MQ_RX_VMDQ_DCB mode supported in SRIOV");
1281                         break;
1282                 case ETH_MQ_RX_VMDQ_DCB_RSS:
1283                         /* DCB/RSS VMDQ in SRIOV mode, not implement yet */
1284                         PMD_INIT_LOG(ERR, "SRIOV active,"
1285                                         " unsupported mq_mode rx %d.",
1286                                         dev_conf->rxmode.mq_mode);
1287                         return -EINVAL;
1288                 case ETH_MQ_RX_RSS:
1289                 case ETH_MQ_RX_VMDQ_RSS:
1290                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_RSS;
1291                         if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)
1292                                 if (txgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) {
1293                                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1294                                                 " invalid queue number"
1295                                                 " for VMDQ RSS, allowed"
1296                                                 " value are 1, 2 or 4.");
1297                                         return -EINVAL;
1298                                 }
1299                         break;
1300                 case ETH_MQ_RX_VMDQ_ONLY:
1301                 case ETH_MQ_RX_NONE:
1302                         /* if nothing mq mode configure, use default scheme */
1303                         dev->data->dev_conf.rxmode.mq_mode =
1304                                 ETH_MQ_RX_VMDQ_ONLY;
1305                         break;
1306                 default: /* ETH_MQ_RX_DCB, ETH_MQ_RX_DCB_RSS or ETH_MQ_TX_DCB*/
1307                         /* SRIOV only works in VMDq enable mode */
1308                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1309                                         " wrong mq_mode rx %d.",
1310                                         dev_conf->rxmode.mq_mode);
1311                         return -EINVAL;
1312                 }
1313
1314                 switch (dev_conf->txmode.mq_mode) {
1315                 case ETH_MQ_TX_VMDQ_DCB:
1316                         PMD_INIT_LOG(INFO, "ETH_MQ_TX_VMDQ_DCB mode supported in SRIOV");
1317                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_DCB;
1318                         break;
1319                 default: /* ETH_MQ_TX_VMDQ_ONLY or ETH_MQ_TX_NONE */
1320                         dev->data->dev_conf.txmode.mq_mode =
1321                                 ETH_MQ_TX_VMDQ_ONLY;
1322                         break;
1323                 }
1324
1325                 /* check valid queue number */
1326                 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) ||
1327                     (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) {
1328                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1329                                         " nb_rx_q=%d nb_tx_q=%d queue number"
1330                                         " must be less than or equal to %d.",
1331                                         nb_rx_q, nb_tx_q,
1332                                         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool);
1333                         return -EINVAL;
1334                 }
1335         } else {
1336                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
1337                         PMD_INIT_LOG(ERR, "VMDQ+DCB+RSS mq_mode is"
1338                                           " not supported.");
1339                         return -EINVAL;
1340                 }
1341                 /* check configuration for vmdb+dcb mode */
1342                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB) {
1343                         const struct rte_eth_vmdq_dcb_conf *conf;
1344
1345                         if (nb_rx_q != TXGBE_VMDQ_DCB_NB_QUEUES) {
1346                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.",
1347                                                 TXGBE_VMDQ_DCB_NB_QUEUES);
1348                                 return -EINVAL;
1349                         }
1350                         conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf;
1351                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
1352                                conf->nb_queue_pools == ETH_32_POOLS)) {
1353                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
1354                                                 " nb_queue_pools must be %d or %d.",
1355                                                 ETH_16_POOLS, ETH_32_POOLS);
1356                                 return -EINVAL;
1357                         }
1358                 }
1359                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) {
1360                         const struct rte_eth_vmdq_dcb_tx_conf *conf;
1361
1362                         if (nb_tx_q != TXGBE_VMDQ_DCB_NB_QUEUES) {
1363                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d",
1364                                                  TXGBE_VMDQ_DCB_NB_QUEUES);
1365                                 return -EINVAL;
1366                         }
1367                         conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf;
1368                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
1369                                conf->nb_queue_pools == ETH_32_POOLS)) {
1370                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
1371                                                 " nb_queue_pools != %d and"
1372                                                 " nb_queue_pools != %d.",
1373                                                 ETH_16_POOLS, ETH_32_POOLS);
1374                                 return -EINVAL;
1375                         }
1376                 }
1377
1378                 /* For DCB mode check our configuration before we go further */
1379                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_DCB) {
1380                         const struct rte_eth_dcb_rx_conf *conf;
1381
1382                         conf = &dev_conf->rx_adv_conf.dcb_rx_conf;
1383                         if (!(conf->nb_tcs == ETH_4_TCS ||
1384                                conf->nb_tcs == ETH_8_TCS)) {
1385                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
1386                                                 " and nb_tcs != %d.",
1387                                                 ETH_4_TCS, ETH_8_TCS);
1388                                 return -EINVAL;
1389                         }
1390                 }
1391
1392                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_DCB) {
1393                         const struct rte_eth_dcb_tx_conf *conf;
1394
1395                         conf = &dev_conf->tx_adv_conf.dcb_tx_conf;
1396                         if (!(conf->nb_tcs == ETH_4_TCS ||
1397                                conf->nb_tcs == ETH_8_TCS)) {
1398                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
1399                                                 " and nb_tcs != %d.",
1400                                                 ETH_4_TCS, ETH_8_TCS);
1401                                 return -EINVAL;
1402                         }
1403                 }
1404         }
1405         return 0;
1406 }
1407
1408 static int
1409 txgbe_dev_configure(struct rte_eth_dev *dev)
1410 {
1411         struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);
1412         struct txgbe_adapter *adapter = TXGBE_DEV_ADAPTER(dev);
1413         int ret;
1414
1415         PMD_INIT_FUNC_TRACE();
1416
1417         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
1418                 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
1419
1420         /* multiple queue mode checking */
1421         ret  = txgbe_check_mq_mode(dev);
1422         if (ret != 0) {
1423                 PMD_DRV_LOG(ERR, "txgbe_check_mq_mode fails with %d.",
1424                             ret);
1425                 return ret;
1426         }
1427
1428         /* set flag to update link status after init */
1429         intr->flags |= TXGBE_FLAG_NEED_LINK_UPDATE;
1430
1431         /*
1432          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
1433          * allocation Rx preconditions we will reset it.
1434          */
1435         adapter->rx_bulk_alloc_allowed = true;
1436
1437         return 0;
1438 }
1439
1440 static void
1441 txgbe_dev_phy_intr_setup(struct rte_eth_dev *dev)
1442 {
1443         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
1444         struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);
1445         uint32_t gpie;
1446
1447         gpie = rd32(hw, TXGBE_GPIOINTEN);
1448         gpie |= TXGBE_GPIOBIT_6;
1449         wr32(hw, TXGBE_GPIOINTEN, gpie);
1450         intr->mask_misc |= TXGBE_ICRMISC_GPIO;
1451 }
1452
1453 int
1454 txgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
1455                         uint16_t tx_rate, uint64_t q_msk)
1456 {
1457         struct txgbe_hw *hw;
1458         struct txgbe_vf_info *vfinfo;
1459         struct rte_eth_link link;
1460         uint8_t  nb_q_per_pool;
1461         uint32_t queue_stride;
1462         uint32_t queue_idx, idx = 0, vf_idx;
1463         uint32_t queue_end;
1464         uint16_t total_rate = 0;
1465         struct rte_pci_device *pci_dev;
1466         int ret;
1467
1468         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1469         ret = rte_eth_link_get_nowait(dev->data->port_id, &link);
1470         if (ret < 0)
1471                 return ret;
1472
1473         if (vf >= pci_dev->max_vfs)
1474                 return -EINVAL;
1475
1476         if (tx_rate > link.link_speed)
1477                 return -EINVAL;
1478
1479         if (q_msk == 0)
1480                 return 0;
1481
1482         hw = TXGBE_DEV_HW(dev);
1483         vfinfo = *(TXGBE_DEV_VFDATA(dev));
1484         nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
1485         queue_stride = TXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
1486         queue_idx = vf * queue_stride;
1487         queue_end = queue_idx + nb_q_per_pool - 1;
1488         if (queue_end >= hw->mac.max_tx_queues)
1489                 return -EINVAL;
1490
1491         if (vfinfo) {
1492                 for (vf_idx = 0; vf_idx < pci_dev->max_vfs; vf_idx++) {
1493                         if (vf_idx == vf)
1494                                 continue;
1495                         for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
1496                                 idx++)
1497                                 total_rate += vfinfo[vf_idx].tx_rate[idx];
1498                 }
1499         } else {
1500                 return -EINVAL;
1501         }
1502
1503         /* Store tx_rate for this vf. */
1504         for (idx = 0; idx < nb_q_per_pool; idx++) {
1505                 if (((uint64_t)0x1 << idx) & q_msk) {
1506                         if (vfinfo[vf].tx_rate[idx] != tx_rate)
1507                                 vfinfo[vf].tx_rate[idx] = tx_rate;
1508                         total_rate += tx_rate;
1509                 }
1510         }
1511
1512         if (total_rate > dev->data->dev_link.link_speed) {
1513                 /* Reset stored TX rate of the VF if it causes exceed
1514                  * link speed.
1515                  */
1516                 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
1517                 return -EINVAL;
1518         }
1519
1520         /* Set ARBTXRATE of each queue/pool for vf X  */
1521         for (; queue_idx <= queue_end; queue_idx++) {
1522                 if (0x1 & q_msk)
1523                         txgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
1524                 q_msk = q_msk >> 1;
1525         }
1526
1527         return 0;
1528 }
1529
1530 /*
1531  * Configure device link speed and setup link.
1532  * It returns 0 on success.
1533  */
1534 static int
1535 txgbe_dev_start(struct rte_eth_dev *dev)
1536 {
1537         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
1538         struct txgbe_hw_stats *hw_stats = TXGBE_DEV_STATS(dev);
1539         struct txgbe_vf_info *vfinfo = *TXGBE_DEV_VFDATA(dev);
1540         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1541         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1542         uint32_t intr_vector = 0;
1543         int err;
1544         bool link_up = false, negotiate = 0;
1545         uint32_t speed = 0;
1546         uint32_t allowed_speeds = 0;
1547         int mask = 0;
1548         int status;
1549         uint16_t vf, idx;
1550         uint32_t *link_speeds;
1551         struct txgbe_tm_conf *tm_conf = TXGBE_DEV_TM_CONF(dev);
1552
1553         PMD_INIT_FUNC_TRACE();
1554
1555         /* TXGBE devices don't support:
1556          *    - half duplex (checked afterwards for valid speeds)
1557          *    - fixed speed: TODO implement
1558          */
1559         if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
1560                 PMD_INIT_LOG(ERR,
1561                 "Invalid link_speeds for port %u, fix speed not supported",
1562                                 dev->data->port_id);
1563                 return -EINVAL;
1564         }
1565
1566         /* Stop the link setup handler before resetting the HW. */
1567         rte_eal_alarm_cancel(txgbe_dev_setup_link_alarm_handler, dev);
1568
1569         /* disable uio/vfio intr/eventfd mapping */
1570         rte_intr_disable(intr_handle);
1571
1572         /* stop adapter */
1573         hw->adapter_stopped = 0;
1574         txgbe_stop_hw(hw);
1575
1576         /* reinitialize adapter
1577          * this calls reset and start
1578          */
1579         hw->nb_rx_queues = dev->data->nb_rx_queues;
1580         hw->nb_tx_queues = dev->data->nb_tx_queues;
1581         status = txgbe_pf_reset_hw(hw);
1582         if (status != 0)
1583                 return -1;
1584         hw->mac.start_hw(hw);
1585         hw->mac.get_link_status = true;
1586
1587         /* configure PF module if SRIOV enabled */
1588         txgbe_pf_host_configure(dev);
1589
1590         txgbe_dev_phy_intr_setup(dev);
1591
1592         /* check and configure queue intr-vector mapping */
1593         if ((rte_intr_cap_multiple(intr_handle) ||
1594              !RTE_ETH_DEV_SRIOV(dev).active) &&
1595             dev->data->dev_conf.intr_conf.rxq != 0) {
1596                 intr_vector = dev->data->nb_rx_queues;
1597                 if (rte_intr_efd_enable(intr_handle, intr_vector))
1598                         return -1;
1599         }
1600
1601         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1602                 intr_handle->intr_vec =
1603                         rte_zmalloc("intr_vec",
1604                                     dev->data->nb_rx_queues * sizeof(int), 0);
1605                 if (intr_handle->intr_vec == NULL) {
1606                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
1607                                      " intr_vec", dev->data->nb_rx_queues);
1608                         return -ENOMEM;
1609                 }
1610         }
1611
1612         /* confiugre msix for sleep until rx interrupt */
1613         txgbe_configure_msix(dev);
1614
1615         /* initialize transmission unit */
1616         txgbe_dev_tx_init(dev);
1617
1618         /* This can fail when allocating mbufs for descriptor rings */
1619         err = txgbe_dev_rx_init(dev);
1620         if (err) {
1621                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
1622                 goto error;
1623         }
1624
1625         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
1626                 ETH_VLAN_EXTEND_MASK;
1627         err = txgbe_vlan_offload_config(dev, mask);
1628         if (err) {
1629                 PMD_INIT_LOG(ERR, "Unable to set VLAN offload");
1630                 goto error;
1631         }
1632
1633         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1634                 /* Enable vlan filtering for VMDq */
1635                 txgbe_vmdq_vlan_hw_filter_enable(dev);
1636         }
1637
1638         /* Configure DCB hw */
1639         txgbe_configure_pb(dev);
1640         txgbe_configure_port(dev);
1641         txgbe_configure_dcb(dev);
1642
1643         if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
1644                 err = txgbe_fdir_configure(dev);
1645                 if (err)
1646                         goto error;
1647         }
1648
1649         /* Restore vf rate limit */
1650         if (vfinfo != NULL) {
1651                 for (vf = 0; vf < pci_dev->max_vfs; vf++)
1652                         for (idx = 0; idx < TXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
1653                                 if (vfinfo[vf].tx_rate[idx] != 0)
1654                                         txgbe_set_vf_rate_limit(dev, vf,
1655                                                 vfinfo[vf].tx_rate[idx],
1656                                                 1 << idx);
1657         }
1658
1659         err = txgbe_dev_rxtx_start(dev);
1660         if (err < 0) {
1661                 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
1662                 goto error;
1663         }
1664
1665         /* Skip link setup if loopback mode is enabled. */
1666         if (hw->mac.type == txgbe_mac_raptor &&
1667             dev->data->dev_conf.lpbk_mode)
1668                 goto skip_link_setup;
1669
1670         if (txgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
1671                 err = hw->mac.setup_sfp(hw);
1672                 if (err)
1673                         goto error;
1674         }
1675
1676         if (hw->phy.media_type == txgbe_media_type_copper) {
1677                 /* Turn on the copper */
1678                 hw->phy.set_phy_power(hw, true);
1679         } else {
1680                 /* Turn on the laser */
1681                 hw->mac.enable_tx_laser(hw);
1682         }
1683
1684         err = hw->mac.check_link(hw, &speed, &link_up, 0);
1685         if (err)
1686                 goto error;
1687         dev->data->dev_link.link_status = link_up;
1688
1689         err = hw->mac.get_link_capabilities(hw, &speed, &negotiate);
1690         if (err)
1691                 goto error;
1692
1693         allowed_speeds = ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
1694                         ETH_LINK_SPEED_10G;
1695
1696         link_speeds = &dev->data->dev_conf.link_speeds;
1697         if (*link_speeds & ~allowed_speeds) {
1698                 PMD_INIT_LOG(ERR, "Invalid link setting");
1699                 goto error;
1700         }
1701
1702         speed = 0x0;
1703         if (*link_speeds == ETH_LINK_SPEED_AUTONEG) {
1704                 speed = (TXGBE_LINK_SPEED_100M_FULL |
1705                          TXGBE_LINK_SPEED_1GB_FULL |
1706                          TXGBE_LINK_SPEED_10GB_FULL);
1707         } else {
1708                 if (*link_speeds & ETH_LINK_SPEED_10G)
1709                         speed |= TXGBE_LINK_SPEED_10GB_FULL;
1710                 if (*link_speeds & ETH_LINK_SPEED_5G)
1711                         speed |= TXGBE_LINK_SPEED_5GB_FULL;
1712                 if (*link_speeds & ETH_LINK_SPEED_2_5G)
1713                         speed |= TXGBE_LINK_SPEED_2_5GB_FULL;
1714                 if (*link_speeds & ETH_LINK_SPEED_1G)
1715                         speed |= TXGBE_LINK_SPEED_1GB_FULL;
1716                 if (*link_speeds & ETH_LINK_SPEED_100M)
1717                         speed |= TXGBE_LINK_SPEED_100M_FULL;
1718         }
1719
1720         err = hw->mac.setup_link(hw, speed, link_up);
1721         if (err)
1722                 goto error;
1723
1724 skip_link_setup:
1725
1726         if (rte_intr_allow_others(intr_handle)) {
1727                 /* check if lsc interrupt is enabled */
1728                 if (dev->data->dev_conf.intr_conf.lsc != 0)
1729                         txgbe_dev_lsc_interrupt_setup(dev, TRUE);
1730                 else
1731                         txgbe_dev_lsc_interrupt_setup(dev, FALSE);
1732                 txgbe_dev_macsec_interrupt_setup(dev);
1733                 txgbe_set_ivar_map(hw, -1, 1, TXGBE_MISC_VEC_ID);
1734         } else {
1735                 rte_intr_callback_unregister(intr_handle,
1736                                              txgbe_dev_interrupt_handler, dev);
1737                 if (dev->data->dev_conf.intr_conf.lsc != 0)
1738                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
1739                                      " no intr multiplex");
1740         }
1741
1742         /* check if rxq interrupt is enabled */
1743         if (dev->data->dev_conf.intr_conf.rxq != 0 &&
1744             rte_intr_dp_is_en(intr_handle))
1745                 txgbe_dev_rxq_interrupt_setup(dev);
1746
1747         /* enable uio/vfio intr/eventfd mapping */
1748         rte_intr_enable(intr_handle);
1749
1750         /* resume enabled intr since hw reset */
1751         txgbe_enable_intr(dev);
1752         txgbe_l2_tunnel_conf(dev);
1753         txgbe_filter_restore(dev);
1754
1755         if (tm_conf->root && !tm_conf->committed)
1756                 PMD_DRV_LOG(WARNING,
1757                             "please call hierarchy_commit() "
1758                             "before starting the port");
1759
1760         /*
1761          * Update link status right before return, because it may
1762          * start link configuration process in a separate thread.
1763          */
1764         txgbe_dev_link_update(dev, 0);
1765
1766         wr32m(hw, TXGBE_LEDCTL, 0xFFFFFFFF, TXGBE_LEDCTL_ORD_MASK);
1767
1768         txgbe_read_stats_registers(hw, hw_stats);
1769         hw->offset_loaded = 1;
1770
1771         return 0;
1772
1773 error:
1774         PMD_INIT_LOG(ERR, "failure in dev start: %d", err);
1775         txgbe_dev_clear_queues(dev);
1776         return -EIO;
1777 }
1778
1779 /*
1780  * Stop device: disable rx and tx functions to allow for reconfiguring.
1781  */
1782 static int
1783 txgbe_dev_stop(struct rte_eth_dev *dev)
1784 {
1785         struct rte_eth_link link;
1786         struct txgbe_adapter *adapter = TXGBE_DEV_ADAPTER(dev);
1787         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
1788         struct txgbe_vf_info *vfinfo = *TXGBE_DEV_VFDATA(dev);
1789         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1790         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1791         int vf;
1792         struct txgbe_tm_conf *tm_conf = TXGBE_DEV_TM_CONF(dev);
1793
1794         if (hw->adapter_stopped)
1795                 return 0;
1796
1797         PMD_INIT_FUNC_TRACE();
1798
1799         rte_eal_alarm_cancel(txgbe_dev_setup_link_alarm_handler, dev);
1800
1801         /* disable interrupts */
1802         txgbe_disable_intr(hw);
1803
1804         /* reset the NIC */
1805         txgbe_pf_reset_hw(hw);
1806         hw->adapter_stopped = 0;
1807
1808         /* stop adapter */
1809         txgbe_stop_hw(hw);
1810
1811         for (vf = 0; vfinfo != NULL && vf < pci_dev->max_vfs; vf++)
1812                 vfinfo[vf].clear_to_send = false;
1813
1814         if (hw->phy.media_type == txgbe_media_type_copper) {
1815                 /* Turn off the copper */
1816                 hw->phy.set_phy_power(hw, false);
1817         } else {
1818                 /* Turn off the laser */
1819                 hw->mac.disable_tx_laser(hw);
1820         }
1821
1822         txgbe_dev_clear_queues(dev);
1823
1824         /* Clear stored conf */
1825         dev->data->scattered_rx = 0;
1826         dev->data->lro = 0;
1827
1828         /* Clear recorded link status */
1829         memset(&link, 0, sizeof(link));
1830         rte_eth_linkstatus_set(dev, &link);
1831
1832         if (!rte_intr_allow_others(intr_handle))
1833                 /* resume to the default handler */
1834                 rte_intr_callback_register(intr_handle,
1835                                            txgbe_dev_interrupt_handler,
1836                                            (void *)dev);
1837
1838         /* Clean datapath event and queue/vec mapping */
1839         rte_intr_efd_disable(intr_handle);
1840         if (intr_handle->intr_vec != NULL) {
1841                 rte_free(intr_handle->intr_vec);
1842                 intr_handle->intr_vec = NULL;
1843         }
1844
1845         /* reset hierarchy commit */
1846         tm_conf->committed = false;
1847
1848         adapter->rss_reta_updated = 0;
1849         wr32m(hw, TXGBE_LEDCTL, 0xFFFFFFFF, TXGBE_LEDCTL_SEL_MASK);
1850
1851         hw->adapter_stopped = true;
1852         dev->data->dev_started = 0;
1853
1854         return 0;
1855 }
1856
1857 /*
1858  * Set device link up: enable tx.
1859  */
1860 static int
1861 txgbe_dev_set_link_up(struct rte_eth_dev *dev)
1862 {
1863         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
1864
1865         if (hw->phy.media_type == txgbe_media_type_copper) {
1866                 /* Turn on the copper */
1867                 hw->phy.set_phy_power(hw, true);
1868         } else {
1869                 /* Turn on the laser */
1870                 hw->mac.enable_tx_laser(hw);
1871                 txgbe_dev_link_update(dev, 0);
1872         }
1873
1874         return 0;
1875 }
1876
1877 /*
1878  * Set device link down: disable tx.
1879  */
1880 static int
1881 txgbe_dev_set_link_down(struct rte_eth_dev *dev)
1882 {
1883         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
1884
1885         if (hw->phy.media_type == txgbe_media_type_copper) {
1886                 /* Turn off the copper */
1887                 hw->phy.set_phy_power(hw, false);
1888         } else {
1889                 /* Turn off the laser */
1890                 hw->mac.disable_tx_laser(hw);
1891                 txgbe_dev_link_update(dev, 0);
1892         }
1893
1894         return 0;
1895 }
1896
1897 /*
1898  * Reset and stop device.
1899  */
1900 static int
1901 txgbe_dev_close(struct rte_eth_dev *dev)
1902 {
1903         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
1904         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1905         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1906         int retries = 0;
1907         int ret;
1908
1909         PMD_INIT_FUNC_TRACE();
1910
1911         txgbe_pf_reset_hw(hw);
1912
1913         ret = txgbe_dev_stop(dev);
1914
1915         txgbe_dev_free_queues(dev);
1916
1917         /* reprogram the RAR[0] in case user changed it. */
1918         txgbe_set_rar(hw, 0, hw->mac.addr, 0, true);
1919
1920         /* Unlock any pending hardware semaphore */
1921         txgbe_swfw_lock_reset(hw);
1922
1923         /* disable uio intr before callback unregister */
1924         rte_intr_disable(intr_handle);
1925
1926         do {
1927                 ret = rte_intr_callback_unregister(intr_handle,
1928                                 txgbe_dev_interrupt_handler, dev);
1929                 if (ret >= 0 || ret == -ENOENT) {
1930                         break;
1931                 } else if (ret != -EAGAIN) {
1932                         PMD_INIT_LOG(ERR,
1933                                 "intr callback unregister failed: %d",
1934                                 ret);
1935                 }
1936                 rte_delay_ms(100);
1937         } while (retries++ < (10 + TXGBE_LINK_UP_TIME));
1938
1939         /* cancel the delay handler before remove dev */
1940         rte_eal_alarm_cancel(txgbe_dev_interrupt_delayed_handler, dev);
1941
1942         /* uninitialize PF if max_vfs not zero */
1943         txgbe_pf_host_uninit(dev);
1944
1945         rte_free(dev->data->mac_addrs);
1946         dev->data->mac_addrs = NULL;
1947
1948         rte_free(dev->data->hash_mac_addrs);
1949         dev->data->hash_mac_addrs = NULL;
1950
1951         /* remove all the fdir filters & hash */
1952         txgbe_fdir_filter_uninit(dev);
1953
1954         /* remove all the L2 tunnel filters & hash */
1955         txgbe_l2_tn_filter_uninit(dev);
1956
1957         /* Remove all ntuple filters of the device */
1958         txgbe_ntuple_filter_uninit(dev);
1959
1960         /* clear all the filters list */
1961         txgbe_filterlist_flush();
1962
1963         /* Remove all Traffic Manager configuration */
1964         txgbe_tm_conf_uninit(dev);
1965
1966         return ret;
1967 }
1968
1969 /*
1970  * Reset PF device.
1971  */
1972 static int
1973 txgbe_dev_reset(struct rte_eth_dev *dev)
1974 {
1975         int ret;
1976
1977         /* When a DPDK PMD PF begin to reset PF port, it should notify all
1978          * its VF to make them align with it. The detailed notification
1979          * mechanism is PMD specific. As to txgbe PF, it is rather complex.
1980          * To avoid unexpected behavior in VF, currently reset of PF with
1981          * SR-IOV activation is not supported. It might be supported later.
1982          */
1983         if (dev->data->sriov.active)
1984                 return -ENOTSUP;
1985
1986         ret = eth_txgbe_dev_uninit(dev);
1987         if (ret)
1988                 return ret;
1989
1990         ret = eth_txgbe_dev_init(dev, NULL);
1991
1992         return ret;
1993 }
1994
1995 #define UPDATE_QP_COUNTER_32bit(reg, last_counter, counter)     \
1996         {                                                       \
1997                 uint32_t current_counter = rd32(hw, reg);       \
1998                 if (current_counter < last_counter)             \
1999                         current_counter += 0x100000000LL;       \
2000                 if (!hw->offset_loaded)                         \
2001                         last_counter = current_counter;         \
2002                 counter = current_counter - last_counter;       \
2003                 counter &= 0xFFFFFFFFLL;                        \
2004         }
2005
2006 #define UPDATE_QP_COUNTER_36bit(reg_lsb, reg_msb, last_counter, counter) \
2007         {                                                                \
2008                 uint64_t current_counter_lsb = rd32(hw, reg_lsb);        \
2009                 uint64_t current_counter_msb = rd32(hw, reg_msb);        \
2010                 uint64_t current_counter = (current_counter_msb << 32) | \
2011                         current_counter_lsb;                             \
2012                 if (current_counter < last_counter)                      \
2013                         current_counter += 0x1000000000LL;               \
2014                 if (!hw->offset_loaded)                                  \
2015                         last_counter = current_counter;                  \
2016                 counter = current_counter - last_counter;                \
2017                 counter &= 0xFFFFFFFFFLL;                                \
2018         }
2019
2020 void
2021 txgbe_read_stats_registers(struct txgbe_hw *hw,
2022                            struct txgbe_hw_stats *hw_stats)
2023 {
2024         unsigned int i;
2025
2026         /* QP Stats */
2027         for (i = 0; i < hw->nb_rx_queues; i++) {
2028                 UPDATE_QP_COUNTER_32bit(TXGBE_QPRXPKT(i),
2029                         hw->qp_last[i].rx_qp_packets,
2030                         hw_stats->qp[i].rx_qp_packets);
2031                 UPDATE_QP_COUNTER_36bit(TXGBE_QPRXOCTL(i), TXGBE_QPRXOCTH(i),
2032                         hw->qp_last[i].rx_qp_bytes,
2033                         hw_stats->qp[i].rx_qp_bytes);
2034                 UPDATE_QP_COUNTER_32bit(TXGBE_QPRXMPKT(i),
2035                         hw->qp_last[i].rx_qp_mc_packets,
2036                         hw_stats->qp[i].rx_qp_mc_packets);
2037         }
2038
2039         for (i = 0; i < hw->nb_tx_queues; i++) {
2040                 UPDATE_QP_COUNTER_32bit(TXGBE_QPTXPKT(i),
2041                         hw->qp_last[i].tx_qp_packets,
2042                         hw_stats->qp[i].tx_qp_packets);
2043                 UPDATE_QP_COUNTER_36bit(TXGBE_QPTXOCTL(i), TXGBE_QPTXOCTH(i),
2044                         hw->qp_last[i].tx_qp_bytes,
2045                         hw_stats->qp[i].tx_qp_bytes);
2046         }
2047         /* PB Stats */
2048         for (i = 0; i < TXGBE_MAX_UP; i++) {
2049                 hw_stats->up[i].rx_up_xon_packets +=
2050                                 rd32(hw, TXGBE_PBRXUPXON(i));
2051                 hw_stats->up[i].rx_up_xoff_packets +=
2052                                 rd32(hw, TXGBE_PBRXUPXOFF(i));
2053                 hw_stats->up[i].tx_up_xon_packets +=
2054                                 rd32(hw, TXGBE_PBTXUPXON(i));
2055                 hw_stats->up[i].tx_up_xoff_packets +=
2056                                 rd32(hw, TXGBE_PBTXUPXOFF(i));
2057                 hw_stats->up[i].tx_up_xon2off_packets +=
2058                                 rd32(hw, TXGBE_PBTXUPOFF(i));
2059                 hw_stats->up[i].rx_up_dropped +=
2060                                 rd32(hw, TXGBE_PBRXMISS(i));
2061         }
2062         hw_stats->rx_xon_packets += rd32(hw, TXGBE_PBRXLNKXON);
2063         hw_stats->rx_xoff_packets += rd32(hw, TXGBE_PBRXLNKXOFF);
2064         hw_stats->tx_xon_packets += rd32(hw, TXGBE_PBTXLNKXON);
2065         hw_stats->tx_xoff_packets += rd32(hw, TXGBE_PBTXLNKXOFF);
2066
2067         /* DMA Stats */
2068         hw_stats->rx_packets += rd32(hw, TXGBE_DMARXPKT);
2069         hw_stats->tx_packets += rd32(hw, TXGBE_DMATXPKT);
2070
2071         hw_stats->rx_bytes += rd64(hw, TXGBE_DMARXOCTL);
2072         hw_stats->tx_bytes += rd64(hw, TXGBE_DMATXOCTL);
2073         hw_stats->rx_drop_packets += rd32(hw, TXGBE_PBRXDROP);
2074
2075         /* MAC Stats */
2076         hw_stats->rx_crc_errors += rd64(hw, TXGBE_MACRXERRCRCL);
2077         hw_stats->rx_multicast_packets += rd64(hw, TXGBE_MACRXMPKTL);
2078         hw_stats->tx_multicast_packets += rd64(hw, TXGBE_MACTXMPKTL);
2079
2080         hw_stats->rx_total_packets += rd64(hw, TXGBE_MACRXPKTL);
2081         hw_stats->tx_total_packets += rd64(hw, TXGBE_MACTXPKTL);
2082         hw_stats->rx_total_bytes += rd64(hw, TXGBE_MACRXGBOCTL);
2083
2084         hw_stats->rx_broadcast_packets += rd64(hw, TXGBE_MACRXOCTL);
2085         hw_stats->tx_broadcast_packets += rd32(hw, TXGBE_MACTXOCTL);
2086
2087         hw_stats->rx_size_64_packets += rd64(hw, TXGBE_MACRX1TO64L);
2088         hw_stats->rx_size_65_to_127_packets += rd64(hw, TXGBE_MACRX65TO127L);
2089         hw_stats->rx_size_128_to_255_packets += rd64(hw, TXGBE_MACRX128TO255L);
2090         hw_stats->rx_size_256_to_511_packets += rd64(hw, TXGBE_MACRX256TO511L);
2091         hw_stats->rx_size_512_to_1023_packets +=
2092                         rd64(hw, TXGBE_MACRX512TO1023L);
2093         hw_stats->rx_size_1024_to_max_packets +=
2094                         rd64(hw, TXGBE_MACRX1024TOMAXL);
2095         hw_stats->tx_size_64_packets += rd64(hw, TXGBE_MACTX1TO64L);
2096         hw_stats->tx_size_65_to_127_packets += rd64(hw, TXGBE_MACTX65TO127L);
2097         hw_stats->tx_size_128_to_255_packets += rd64(hw, TXGBE_MACTX128TO255L);
2098         hw_stats->tx_size_256_to_511_packets += rd64(hw, TXGBE_MACTX256TO511L);
2099         hw_stats->tx_size_512_to_1023_packets +=
2100                         rd64(hw, TXGBE_MACTX512TO1023L);
2101         hw_stats->tx_size_1024_to_max_packets +=
2102                         rd64(hw, TXGBE_MACTX1024TOMAXL);
2103
2104         hw_stats->rx_undersize_errors += rd64(hw, TXGBE_MACRXERRLENL);
2105         hw_stats->rx_oversize_errors += rd32(hw, TXGBE_MACRXOVERSIZE);
2106         hw_stats->rx_jabber_errors += rd32(hw, TXGBE_MACRXJABBER);
2107
2108         /* MNG Stats */
2109         hw_stats->mng_bmc2host_packets = rd32(hw, TXGBE_MNGBMC2OS);
2110         hw_stats->mng_host2bmc_packets = rd32(hw, TXGBE_MNGOS2BMC);
2111         hw_stats->rx_management_packets = rd32(hw, TXGBE_DMARXMNG);
2112         hw_stats->tx_management_packets = rd32(hw, TXGBE_DMATXMNG);
2113
2114         /* FCoE Stats */
2115         hw_stats->rx_fcoe_crc_errors += rd32(hw, TXGBE_FCOECRC);
2116         hw_stats->rx_fcoe_mbuf_allocation_errors += rd32(hw, TXGBE_FCOELAST);
2117         hw_stats->rx_fcoe_dropped += rd32(hw, TXGBE_FCOERPDC);
2118         hw_stats->rx_fcoe_packets += rd32(hw, TXGBE_FCOEPRC);
2119         hw_stats->tx_fcoe_packets += rd32(hw, TXGBE_FCOEPTC);
2120         hw_stats->rx_fcoe_bytes += rd32(hw, TXGBE_FCOEDWRC);
2121         hw_stats->tx_fcoe_bytes += rd32(hw, TXGBE_FCOEDWTC);
2122
2123         /* Flow Director Stats */
2124         hw_stats->flow_director_matched_filters += rd32(hw, TXGBE_FDIRMATCH);
2125         hw_stats->flow_director_missed_filters += rd32(hw, TXGBE_FDIRMISS);
2126         hw_stats->flow_director_added_filters +=
2127                 TXGBE_FDIRUSED_ADD(rd32(hw, TXGBE_FDIRUSED));
2128         hw_stats->flow_director_removed_filters +=
2129                 TXGBE_FDIRUSED_REM(rd32(hw, TXGBE_FDIRUSED));
2130         hw_stats->flow_director_filter_add_errors +=
2131                 TXGBE_FDIRFAIL_ADD(rd32(hw, TXGBE_FDIRFAIL));
2132         hw_stats->flow_director_filter_remove_errors +=
2133                 TXGBE_FDIRFAIL_REM(rd32(hw, TXGBE_FDIRFAIL));
2134
2135         /* MACsec Stats */
2136         hw_stats->tx_macsec_pkts_untagged += rd32(hw, TXGBE_LSECTX_UTPKT);
2137         hw_stats->tx_macsec_pkts_encrypted +=
2138                         rd32(hw, TXGBE_LSECTX_ENCPKT);
2139         hw_stats->tx_macsec_pkts_protected +=
2140                         rd32(hw, TXGBE_LSECTX_PROTPKT);
2141         hw_stats->tx_macsec_octets_encrypted +=
2142                         rd32(hw, TXGBE_LSECTX_ENCOCT);
2143         hw_stats->tx_macsec_octets_protected +=
2144                         rd32(hw, TXGBE_LSECTX_PROTOCT);
2145         hw_stats->rx_macsec_pkts_untagged += rd32(hw, TXGBE_LSECRX_UTPKT);
2146         hw_stats->rx_macsec_pkts_badtag += rd32(hw, TXGBE_LSECRX_BTPKT);
2147         hw_stats->rx_macsec_pkts_nosci += rd32(hw, TXGBE_LSECRX_NOSCIPKT);
2148         hw_stats->rx_macsec_pkts_unknownsci += rd32(hw, TXGBE_LSECRX_UNSCIPKT);
2149         hw_stats->rx_macsec_octets_decrypted += rd32(hw, TXGBE_LSECRX_DECOCT);
2150         hw_stats->rx_macsec_octets_validated += rd32(hw, TXGBE_LSECRX_VLDOCT);
2151         hw_stats->rx_macsec_sc_pkts_unchecked +=
2152                         rd32(hw, TXGBE_LSECRX_UNCHKPKT);
2153         hw_stats->rx_macsec_sc_pkts_delayed += rd32(hw, TXGBE_LSECRX_DLYPKT);
2154         hw_stats->rx_macsec_sc_pkts_late += rd32(hw, TXGBE_LSECRX_LATEPKT);
2155         for (i = 0; i < 2; i++) {
2156                 hw_stats->rx_macsec_sa_pkts_ok +=
2157                         rd32(hw, TXGBE_LSECRX_OKPKT(i));
2158                 hw_stats->rx_macsec_sa_pkts_invalid +=
2159                         rd32(hw, TXGBE_LSECRX_INVPKT(i));
2160                 hw_stats->rx_macsec_sa_pkts_notvalid +=
2161                         rd32(hw, TXGBE_LSECRX_BADPKT(i));
2162         }
2163         hw_stats->rx_macsec_sa_pkts_unusedsa +=
2164                         rd32(hw, TXGBE_LSECRX_INVSAPKT);
2165         hw_stats->rx_macsec_sa_pkts_notusingsa +=
2166                         rd32(hw, TXGBE_LSECRX_BADSAPKT);
2167
2168         hw_stats->rx_total_missed_packets = 0;
2169         for (i = 0; i < TXGBE_MAX_UP; i++) {
2170                 hw_stats->rx_total_missed_packets +=
2171                         hw_stats->up[i].rx_up_dropped;
2172         }
2173 }
2174
2175 static int
2176 txgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2177 {
2178         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2179         struct txgbe_hw_stats *hw_stats = TXGBE_DEV_STATS(dev);
2180         struct txgbe_stat_mappings *stat_mappings =
2181                         TXGBE_DEV_STAT_MAPPINGS(dev);
2182         uint32_t i, j;
2183
2184         txgbe_read_stats_registers(hw, hw_stats);
2185
2186         if (stats == NULL)
2187                 return -EINVAL;
2188
2189         /* Fill out the rte_eth_stats statistics structure */
2190         stats->ipackets = hw_stats->rx_packets;
2191         stats->ibytes = hw_stats->rx_bytes;
2192         stats->opackets = hw_stats->tx_packets;
2193         stats->obytes = hw_stats->tx_bytes;
2194
2195         memset(&stats->q_ipackets, 0, sizeof(stats->q_ipackets));
2196         memset(&stats->q_opackets, 0, sizeof(stats->q_opackets));
2197         memset(&stats->q_ibytes, 0, sizeof(stats->q_ibytes));
2198         memset(&stats->q_obytes, 0, sizeof(stats->q_obytes));
2199         memset(&stats->q_errors, 0, sizeof(stats->q_errors));
2200         for (i = 0; i < TXGBE_MAX_QP; i++) {
2201                 uint32_t n = i / NB_QMAP_FIELDS_PER_QSM_REG;
2202                 uint32_t offset = (i % NB_QMAP_FIELDS_PER_QSM_REG) * 8;
2203                 uint32_t q_map;
2204
2205                 q_map = (stat_mappings->rqsm[n] >> offset)
2206                                 & QMAP_FIELD_RESERVED_BITS_MASK;
2207                 j = (q_map < RTE_ETHDEV_QUEUE_STAT_CNTRS
2208                      ? q_map : q_map % RTE_ETHDEV_QUEUE_STAT_CNTRS);
2209                 stats->q_ipackets[j] += hw_stats->qp[i].rx_qp_packets;
2210                 stats->q_ibytes[j] += hw_stats->qp[i].rx_qp_bytes;
2211
2212                 q_map = (stat_mappings->tqsm[n] >> offset)
2213                                 & QMAP_FIELD_RESERVED_BITS_MASK;
2214                 j = (q_map < RTE_ETHDEV_QUEUE_STAT_CNTRS
2215                      ? q_map : q_map % RTE_ETHDEV_QUEUE_STAT_CNTRS);
2216                 stats->q_opackets[j] += hw_stats->qp[i].tx_qp_packets;
2217                 stats->q_obytes[j] += hw_stats->qp[i].tx_qp_bytes;
2218         }
2219
2220         /* Rx Errors */
2221         stats->imissed  = hw_stats->rx_total_missed_packets;
2222         stats->ierrors  = hw_stats->rx_crc_errors +
2223                           hw_stats->rx_mac_short_packet_dropped +
2224                           hw_stats->rx_length_errors +
2225                           hw_stats->rx_undersize_errors +
2226                           hw_stats->rx_oversize_errors +
2227                           hw_stats->rx_drop_packets +
2228                           hw_stats->rx_illegal_byte_errors +
2229                           hw_stats->rx_error_bytes +
2230                           hw_stats->rx_fragment_errors +
2231                           hw_stats->rx_fcoe_crc_errors +
2232                           hw_stats->rx_fcoe_mbuf_allocation_errors;
2233
2234         /* Tx Errors */
2235         stats->oerrors  = 0;
2236         return 0;
2237 }
2238
2239 static int
2240 txgbe_dev_stats_reset(struct rte_eth_dev *dev)
2241 {
2242         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2243         struct txgbe_hw_stats *hw_stats = TXGBE_DEV_STATS(dev);
2244
2245         /* HW registers are cleared on read */
2246         hw->offset_loaded = 0;
2247         txgbe_dev_stats_get(dev, NULL);
2248         hw->offset_loaded = 1;
2249
2250         /* Reset software totals */
2251         memset(hw_stats, 0, sizeof(*hw_stats));
2252
2253         return 0;
2254 }
2255
2256 /* This function calculates the number of xstats based on the current config */
2257 static unsigned
2258 txgbe_xstats_calc_num(struct rte_eth_dev *dev)
2259 {
2260         int nb_queues = max(dev->data->nb_rx_queues, dev->data->nb_tx_queues);
2261         return TXGBE_NB_HW_STATS +
2262                TXGBE_NB_UP_STATS * TXGBE_MAX_UP +
2263                TXGBE_NB_QP_STATS * nb_queues;
2264 }
2265
2266 static inline int
2267 txgbe_get_name_by_id(uint32_t id, char *name, uint32_t size)
2268 {
2269         int nb, st;
2270
2271         /* Extended stats from txgbe_hw_stats */
2272         if (id < TXGBE_NB_HW_STATS) {
2273                 snprintf(name, size, "[hw]%s",
2274                         rte_txgbe_stats_strings[id].name);
2275                 return 0;
2276         }
2277         id -= TXGBE_NB_HW_STATS;
2278
2279         /* Priority Stats */
2280         if (id < TXGBE_NB_UP_STATS * TXGBE_MAX_UP) {
2281                 nb = id / TXGBE_NB_UP_STATS;
2282                 st = id % TXGBE_NB_UP_STATS;
2283                 snprintf(name, size, "[p%u]%s", nb,
2284                         rte_txgbe_up_strings[st].name);
2285                 return 0;
2286         }
2287         id -= TXGBE_NB_UP_STATS * TXGBE_MAX_UP;
2288
2289         /* Queue Stats */
2290         if (id < TXGBE_NB_QP_STATS * TXGBE_MAX_QP) {
2291                 nb = id / TXGBE_NB_QP_STATS;
2292                 st = id % TXGBE_NB_QP_STATS;
2293                 snprintf(name, size, "[q%u]%s", nb,
2294                         rte_txgbe_qp_strings[st].name);
2295                 return 0;
2296         }
2297         id -= TXGBE_NB_QP_STATS * TXGBE_MAX_QP;
2298
2299         return -(int)(id + 1);
2300 }
2301
2302 static inline int
2303 txgbe_get_offset_by_id(uint32_t id, uint32_t *offset)
2304 {
2305         int nb, st;
2306
2307         /* Extended stats from txgbe_hw_stats */
2308         if (id < TXGBE_NB_HW_STATS) {
2309                 *offset = rte_txgbe_stats_strings[id].offset;
2310                 return 0;
2311         }
2312         id -= TXGBE_NB_HW_STATS;
2313
2314         /* Priority Stats */
2315         if (id < TXGBE_NB_UP_STATS * TXGBE_MAX_UP) {
2316                 nb = id / TXGBE_NB_UP_STATS;
2317                 st = id % TXGBE_NB_UP_STATS;
2318                 *offset = rte_txgbe_up_strings[st].offset +
2319                         nb * (TXGBE_NB_UP_STATS * sizeof(uint64_t));
2320                 return 0;
2321         }
2322         id -= TXGBE_NB_UP_STATS * TXGBE_MAX_UP;
2323
2324         /* Queue Stats */
2325         if (id < TXGBE_NB_QP_STATS * TXGBE_MAX_QP) {
2326                 nb = id / TXGBE_NB_QP_STATS;
2327                 st = id % TXGBE_NB_QP_STATS;
2328                 *offset = rte_txgbe_qp_strings[st].offset +
2329                         nb * (TXGBE_NB_QP_STATS * sizeof(uint64_t));
2330                 return 0;
2331         }
2332
2333         return -1;
2334 }
2335
2336 static int txgbe_dev_xstats_get_names(struct rte_eth_dev *dev,
2337         struct rte_eth_xstat_name *xstats_names, unsigned int limit)
2338 {
2339         unsigned int i, count;
2340
2341         count = txgbe_xstats_calc_num(dev);
2342         if (xstats_names == NULL)
2343                 return count;
2344
2345         /* Note: limit >= cnt_stats checked upstream
2346          * in rte_eth_xstats_names()
2347          */
2348         limit = min(limit, count);
2349
2350         /* Extended stats from txgbe_hw_stats */
2351         for (i = 0; i < limit; i++) {
2352                 if (txgbe_get_name_by_id(i, xstats_names[i].name,
2353                         sizeof(xstats_names[i].name))) {
2354                         PMD_INIT_LOG(WARNING, "id value %d isn't valid", i);
2355                         break;
2356                 }
2357         }
2358
2359         return i;
2360 }
2361
2362 static int txgbe_dev_xstats_get_names_by_id(struct rte_eth_dev *dev,
2363         struct rte_eth_xstat_name *xstats_names,
2364         const uint64_t *ids,
2365         unsigned int limit)
2366 {
2367         unsigned int i;
2368
2369         if (ids == NULL)
2370                 return txgbe_dev_xstats_get_names(dev, xstats_names, limit);
2371
2372         for (i = 0; i < limit; i++) {
2373                 if (txgbe_get_name_by_id(ids[i], xstats_names[i].name,
2374                                 sizeof(xstats_names[i].name))) {
2375                         PMD_INIT_LOG(WARNING, "id value %d isn't valid", i);
2376                         return -1;
2377                 }
2378         }
2379
2380         return i;
2381 }
2382
2383 static int
2384 txgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2385                                          unsigned int limit)
2386 {
2387         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2388         struct txgbe_hw_stats *hw_stats = TXGBE_DEV_STATS(dev);
2389         unsigned int i, count;
2390
2391         txgbe_read_stats_registers(hw, hw_stats);
2392
2393         /* If this is a reset xstats is NULL, and we have cleared the
2394          * registers by reading them.
2395          */
2396         count = txgbe_xstats_calc_num(dev);
2397         if (xstats == NULL)
2398                 return count;
2399
2400         limit = min(limit, txgbe_xstats_calc_num(dev));
2401
2402         /* Extended stats from txgbe_hw_stats */
2403         for (i = 0; i < limit; i++) {
2404                 uint32_t offset = 0;
2405
2406                 if (txgbe_get_offset_by_id(i, &offset)) {
2407                         PMD_INIT_LOG(WARNING, "id value %d isn't valid", i);
2408                         break;
2409                 }
2410                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) + offset);
2411                 xstats[i].id = i;
2412         }
2413
2414         return i;
2415 }
2416
2417 static int
2418 txgbe_dev_xstats_get_(struct rte_eth_dev *dev, uint64_t *values,
2419                                          unsigned int limit)
2420 {
2421         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2422         struct txgbe_hw_stats *hw_stats = TXGBE_DEV_STATS(dev);
2423         unsigned int i, count;
2424
2425         txgbe_read_stats_registers(hw, hw_stats);
2426
2427         /* If this is a reset xstats is NULL, and we have cleared the
2428          * registers by reading them.
2429          */
2430         count = txgbe_xstats_calc_num(dev);
2431         if (values == NULL)
2432                 return count;
2433
2434         limit = min(limit, txgbe_xstats_calc_num(dev));
2435
2436         /* Extended stats from txgbe_hw_stats */
2437         for (i = 0; i < limit; i++) {
2438                 uint32_t offset;
2439
2440                 if (txgbe_get_offset_by_id(i, &offset)) {
2441                         PMD_INIT_LOG(WARNING, "id value %d isn't valid", i);
2442                         break;
2443                 }
2444                 values[i] = *(uint64_t *)(((char *)hw_stats) + offset);
2445         }
2446
2447         return i;
2448 }
2449
2450 static int
2451 txgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
2452                 uint64_t *values, unsigned int limit)
2453 {
2454         struct txgbe_hw_stats *hw_stats = TXGBE_DEV_STATS(dev);
2455         unsigned int i;
2456
2457         if (ids == NULL)
2458                 return txgbe_dev_xstats_get_(dev, values, limit);
2459
2460         for (i = 0; i < limit; i++) {
2461                 uint32_t offset;
2462
2463                 if (txgbe_get_offset_by_id(ids[i], &offset)) {
2464                         PMD_INIT_LOG(WARNING, "id value %d isn't valid", i);
2465                         break;
2466                 }
2467                 values[i] = *(uint64_t *)(((char *)hw_stats) + offset);
2468         }
2469
2470         return i;
2471 }
2472
2473 static int
2474 txgbe_dev_xstats_reset(struct rte_eth_dev *dev)
2475 {
2476         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2477         struct txgbe_hw_stats *hw_stats = TXGBE_DEV_STATS(dev);
2478
2479         /* HW registers are cleared on read */
2480         hw->offset_loaded = 0;
2481         txgbe_read_stats_registers(hw, hw_stats);
2482         hw->offset_loaded = 1;
2483
2484         /* Reset software totals */
2485         memset(hw_stats, 0, sizeof(*hw_stats));
2486
2487         return 0;
2488 }
2489
2490 static int
2491 txgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
2492 {
2493         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2494         u16 eeprom_verh, eeprom_verl;
2495         u32 etrack_id;
2496         int ret;
2497
2498         hw->rom.readw_sw(hw, TXGBE_EEPROM_VERSION_H, &eeprom_verh);
2499         hw->rom.readw_sw(hw, TXGBE_EEPROM_VERSION_L, &eeprom_verl);
2500
2501         etrack_id = (eeprom_verh << 16) | eeprom_verl;
2502         ret = snprintf(fw_version, fw_size, "0x%08x", etrack_id);
2503
2504         ret += 1; /* add the size of '\0' */
2505         if (fw_size < (u32)ret)
2506                 return ret;
2507         else
2508                 return 0;
2509 }
2510
2511 static int
2512 txgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2513 {
2514         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2515         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2516
2517         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
2518         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
2519         dev_info->min_rx_bufsize = 1024;
2520         dev_info->max_rx_pktlen = 15872;
2521         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
2522         dev_info->max_hash_mac_addrs = TXGBE_VMDQ_NUM_UC_MAC;
2523         dev_info->max_vfs = pci_dev->max_vfs;
2524         dev_info->max_vmdq_pools = ETH_64_POOLS;
2525         dev_info->vmdq_queue_num = dev_info->max_rx_queues;
2526         dev_info->rx_queue_offload_capa = txgbe_get_rx_queue_offloads(dev);
2527         dev_info->rx_offload_capa = (txgbe_get_rx_port_offloads(dev) |
2528                                      dev_info->rx_queue_offload_capa);
2529         dev_info->tx_queue_offload_capa = txgbe_get_tx_queue_offloads(dev);
2530         dev_info->tx_offload_capa = txgbe_get_tx_port_offloads(dev);
2531
2532         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2533                 .rx_thresh = {
2534                         .pthresh = TXGBE_DEFAULT_RX_PTHRESH,
2535                         .hthresh = TXGBE_DEFAULT_RX_HTHRESH,
2536                         .wthresh = TXGBE_DEFAULT_RX_WTHRESH,
2537                 },
2538                 .rx_free_thresh = TXGBE_DEFAULT_RX_FREE_THRESH,
2539                 .rx_drop_en = 0,
2540                 .offloads = 0,
2541         };
2542
2543         dev_info->default_txconf = (struct rte_eth_txconf) {
2544                 .tx_thresh = {
2545                         .pthresh = TXGBE_DEFAULT_TX_PTHRESH,
2546                         .hthresh = TXGBE_DEFAULT_TX_HTHRESH,
2547                         .wthresh = TXGBE_DEFAULT_TX_WTHRESH,
2548                 },
2549                 .tx_free_thresh = TXGBE_DEFAULT_TX_FREE_THRESH,
2550                 .offloads = 0,
2551         };
2552
2553         dev_info->rx_desc_lim = rx_desc_lim;
2554         dev_info->tx_desc_lim = tx_desc_lim;
2555
2556         dev_info->hash_key_size = TXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
2557         dev_info->reta_size = ETH_RSS_RETA_SIZE_128;
2558         dev_info->flow_type_rss_offloads = TXGBE_RSS_OFFLOAD_ALL;
2559
2560         dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
2561         dev_info->speed_capa |= ETH_LINK_SPEED_100M;
2562
2563         /* Driver-preferred Rx/Tx parameters */
2564         dev_info->default_rxportconf.burst_size = 32;
2565         dev_info->default_txportconf.burst_size = 32;
2566         dev_info->default_rxportconf.nb_queues = 1;
2567         dev_info->default_txportconf.nb_queues = 1;
2568         dev_info->default_rxportconf.ring_size = 256;
2569         dev_info->default_txportconf.ring_size = 256;
2570
2571         return 0;
2572 }
2573
2574 const uint32_t *
2575 txgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev)
2576 {
2577         if (dev->rx_pkt_burst == txgbe_recv_pkts ||
2578             dev->rx_pkt_burst == txgbe_recv_pkts_lro_single_alloc ||
2579             dev->rx_pkt_burst == txgbe_recv_pkts_lro_bulk_alloc ||
2580             dev->rx_pkt_burst == txgbe_recv_pkts_bulk_alloc)
2581                 return txgbe_get_supported_ptypes();
2582
2583         return NULL;
2584 }
2585
2586 void
2587 txgbe_dev_setup_link_alarm_handler(void *param)
2588 {
2589         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2590         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2591         struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);
2592         u32 speed;
2593         bool autoneg = false;
2594
2595         speed = hw->phy.autoneg_advertised;
2596         if (!speed)
2597                 hw->mac.get_link_capabilities(hw, &speed, &autoneg);
2598
2599         hw->mac.setup_link(hw, speed, true);
2600
2601         intr->flags &= ~TXGBE_FLAG_NEED_LINK_CONFIG;
2602 }
2603
2604 /* return 0 means link status changed, -1 means not changed */
2605 int
2606 txgbe_dev_link_update_share(struct rte_eth_dev *dev,
2607                             int wait_to_complete)
2608 {
2609         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2610         struct rte_eth_link link;
2611         u32 link_speed = TXGBE_LINK_SPEED_UNKNOWN;
2612         struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);
2613         bool link_up;
2614         int err;
2615         int wait = 1;
2616
2617         memset(&link, 0, sizeof(link));
2618         link.link_status = ETH_LINK_DOWN;
2619         link.link_speed = ETH_SPEED_NUM_NONE;
2620         link.link_duplex = ETH_LINK_HALF_DUPLEX;
2621         link.link_autoneg = ETH_LINK_AUTONEG;
2622
2623         hw->mac.get_link_status = true;
2624
2625         if (intr->flags & TXGBE_FLAG_NEED_LINK_CONFIG)
2626                 return rte_eth_linkstatus_set(dev, &link);
2627
2628         /* check if it needs to wait to complete, if lsc interrupt is enabled */
2629         if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
2630                 wait = 0;
2631
2632         err = hw->mac.check_link(hw, &link_speed, &link_up, wait);
2633
2634         if (err != 0) {
2635                 link.link_speed = ETH_SPEED_NUM_100M;
2636                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
2637                 return rte_eth_linkstatus_set(dev, &link);
2638         }
2639
2640         if (link_up == 0) {
2641                 if (hw->phy.media_type == txgbe_media_type_fiber) {
2642                         intr->flags |= TXGBE_FLAG_NEED_LINK_CONFIG;
2643                         rte_eal_alarm_set(10,
2644                                 txgbe_dev_setup_link_alarm_handler, dev);
2645                 }
2646                 return rte_eth_linkstatus_set(dev, &link);
2647         }
2648
2649         intr->flags &= ~TXGBE_FLAG_NEED_LINK_CONFIG;
2650         link.link_status = ETH_LINK_UP;
2651         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2652
2653         switch (link_speed) {
2654         default:
2655         case TXGBE_LINK_SPEED_UNKNOWN:
2656                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
2657                 link.link_speed = ETH_SPEED_NUM_100M;
2658                 break;
2659
2660         case TXGBE_LINK_SPEED_100M_FULL:
2661                 link.link_speed = ETH_SPEED_NUM_100M;
2662                 break;
2663
2664         case TXGBE_LINK_SPEED_1GB_FULL:
2665                 link.link_speed = ETH_SPEED_NUM_1G;
2666                 break;
2667
2668         case TXGBE_LINK_SPEED_2_5GB_FULL:
2669                 link.link_speed = ETH_SPEED_NUM_2_5G;
2670                 break;
2671
2672         case TXGBE_LINK_SPEED_5GB_FULL:
2673                 link.link_speed = ETH_SPEED_NUM_5G;
2674                 break;
2675
2676         case TXGBE_LINK_SPEED_10GB_FULL:
2677                 link.link_speed = ETH_SPEED_NUM_10G;
2678                 break;
2679         }
2680
2681         return rte_eth_linkstatus_set(dev, &link);
2682 }
2683
2684 static int
2685 txgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
2686 {
2687         return txgbe_dev_link_update_share(dev, wait_to_complete);
2688 }
2689
2690 static int
2691 txgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
2692 {
2693         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2694         uint32_t fctrl;
2695
2696         fctrl = rd32(hw, TXGBE_PSRCTL);
2697         fctrl |= (TXGBE_PSRCTL_UCP | TXGBE_PSRCTL_MCP);
2698         wr32(hw, TXGBE_PSRCTL, fctrl);
2699
2700         return 0;
2701 }
2702
2703 static int
2704 txgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
2705 {
2706         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2707         uint32_t fctrl;
2708
2709         fctrl = rd32(hw, TXGBE_PSRCTL);
2710         fctrl &= (~TXGBE_PSRCTL_UCP);
2711         if (dev->data->all_multicast == 1)
2712                 fctrl |= TXGBE_PSRCTL_MCP;
2713         else
2714                 fctrl &= (~TXGBE_PSRCTL_MCP);
2715         wr32(hw, TXGBE_PSRCTL, fctrl);
2716
2717         return 0;
2718 }
2719
2720 static int
2721 txgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
2722 {
2723         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2724         uint32_t fctrl;
2725
2726         fctrl = rd32(hw, TXGBE_PSRCTL);
2727         fctrl |= TXGBE_PSRCTL_MCP;
2728         wr32(hw, TXGBE_PSRCTL, fctrl);
2729
2730         return 0;
2731 }
2732
2733 static int
2734 txgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
2735 {
2736         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2737         uint32_t fctrl;
2738
2739         if (dev->data->promiscuous == 1)
2740                 return 0; /* must remain in all_multicast mode */
2741
2742         fctrl = rd32(hw, TXGBE_PSRCTL);
2743         fctrl &= (~TXGBE_PSRCTL_MCP);
2744         wr32(hw, TXGBE_PSRCTL, fctrl);
2745
2746         return 0;
2747 }
2748
2749 /**
2750  * It clears the interrupt causes and enables the interrupt.
2751  * It will be called once only during nic initialized.
2752  *
2753  * @param dev
2754  *  Pointer to struct rte_eth_dev.
2755  * @param on
2756  *  Enable or Disable.
2757  *
2758  * @return
2759  *  - On success, zero.
2760  *  - On failure, a negative value.
2761  */
2762 static int
2763 txgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on)
2764 {
2765         struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);
2766
2767         txgbe_dev_link_status_print(dev);
2768         if (on)
2769                 intr->mask_misc |= TXGBE_ICRMISC_LSC;
2770         else
2771                 intr->mask_misc &= ~TXGBE_ICRMISC_LSC;
2772
2773         return 0;
2774 }
2775
2776 /**
2777  * It clears the interrupt causes and enables the interrupt.
2778  * It will be called once only during nic initialized.
2779  *
2780  * @param dev
2781  *  Pointer to struct rte_eth_dev.
2782  *
2783  * @return
2784  *  - On success, zero.
2785  *  - On failure, a negative value.
2786  */
2787 static int
2788 txgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
2789 {
2790         struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);
2791
2792         intr->mask[0] |= TXGBE_ICR_MASK;
2793         intr->mask[1] |= TXGBE_ICR_MASK;
2794
2795         return 0;
2796 }
2797
2798 /**
2799  * It clears the interrupt causes and enables the interrupt.
2800  * It will be called once only during nic initialized.
2801  *
2802  * @param dev
2803  *  Pointer to struct rte_eth_dev.
2804  *
2805  * @return
2806  *  - On success, zero.
2807  *  - On failure, a negative value.
2808  */
2809 static int
2810 txgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev)
2811 {
2812         struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);
2813
2814         intr->mask_misc |= TXGBE_ICRMISC_LNKSEC;
2815
2816         return 0;
2817 }
2818
2819 /*
2820  * It reads ICR and sets flag (TXGBE_ICRMISC_LSC) for the link_update.
2821  *
2822  * @param dev
2823  *  Pointer to struct rte_eth_dev.
2824  *
2825  * @return
2826  *  - On success, zero.
2827  *  - On failure, a negative value.
2828  */
2829 static int
2830 txgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
2831 {
2832         uint32_t eicr;
2833         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2834         struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);
2835
2836         /* clear all cause mask */
2837         txgbe_disable_intr(hw);
2838
2839         /* read-on-clear nic registers here */
2840         eicr = ((u32 *)hw->isb_mem)[TXGBE_ISB_MISC];
2841         PMD_DRV_LOG(DEBUG, "eicr %x", eicr);
2842
2843         intr->flags = 0;
2844
2845         /* set flag for async link update */
2846         if (eicr & TXGBE_ICRMISC_LSC)
2847                 intr->flags |= TXGBE_FLAG_NEED_LINK_UPDATE;
2848
2849         if (eicr & TXGBE_ICRMISC_VFMBX)
2850                 intr->flags |= TXGBE_FLAG_MAILBOX;
2851
2852         if (eicr & TXGBE_ICRMISC_LNKSEC)
2853                 intr->flags |= TXGBE_FLAG_MACSEC;
2854
2855         if (eicr & TXGBE_ICRMISC_GPIO)
2856                 intr->flags |= TXGBE_FLAG_PHY_INTERRUPT;
2857
2858         return 0;
2859 }
2860
2861 /**
2862  * It gets and then prints the link status.
2863  *
2864  * @param dev
2865  *  Pointer to struct rte_eth_dev.
2866  *
2867  * @return
2868  *  - On success, zero.
2869  *  - On failure, a negative value.
2870  */
2871 static void
2872 txgbe_dev_link_status_print(struct rte_eth_dev *dev)
2873 {
2874         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2875         struct rte_eth_link link;
2876
2877         rte_eth_linkstatus_get(dev, &link);
2878
2879         if (link.link_status) {
2880                 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
2881                                         (int)(dev->data->port_id),
2882                                         (unsigned int)link.link_speed,
2883                         link.link_duplex == ETH_LINK_FULL_DUPLEX ?
2884                                         "full-duplex" : "half-duplex");
2885         } else {
2886                 PMD_INIT_LOG(INFO, " Port %d: Link Down",
2887                                 (int)(dev->data->port_id));
2888         }
2889         PMD_INIT_LOG(DEBUG, "PCI Address: " PCI_PRI_FMT,
2890                                 pci_dev->addr.domain,
2891                                 pci_dev->addr.bus,
2892                                 pci_dev->addr.devid,
2893                                 pci_dev->addr.function);
2894 }
2895
2896 /*
2897  * It executes link_update after knowing an interrupt occurred.
2898  *
2899  * @param dev
2900  *  Pointer to struct rte_eth_dev.
2901  *
2902  * @return
2903  *  - On success, zero.
2904  *  - On failure, a negative value.
2905  */
2906 static int
2907 txgbe_dev_interrupt_action(struct rte_eth_dev *dev,
2908                            struct rte_intr_handle *intr_handle)
2909 {
2910         struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);
2911         int64_t timeout;
2912         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2913
2914         PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
2915
2916         if (intr->flags & TXGBE_FLAG_MAILBOX) {
2917                 txgbe_pf_mbx_process(dev);
2918                 intr->flags &= ~TXGBE_FLAG_MAILBOX;
2919         }
2920
2921         if (intr->flags & TXGBE_FLAG_PHY_INTERRUPT) {
2922                 hw->phy.handle_lasi(hw);
2923                 intr->flags &= ~TXGBE_FLAG_PHY_INTERRUPT;
2924         }
2925
2926         if (intr->flags & TXGBE_FLAG_NEED_LINK_UPDATE) {
2927                 struct rte_eth_link link;
2928
2929                 /*get the link status before link update, for predicting later*/
2930                 rte_eth_linkstatus_get(dev, &link);
2931
2932                 txgbe_dev_link_update(dev, 0);
2933
2934                 /* likely to up */
2935                 if (!link.link_status)
2936                         /* handle it 1 sec later, wait it being stable */
2937                         timeout = TXGBE_LINK_UP_CHECK_TIMEOUT;
2938                 /* likely to down */
2939                 else
2940                         /* handle it 4 sec later, wait it being stable */
2941                         timeout = TXGBE_LINK_DOWN_CHECK_TIMEOUT;
2942
2943                 txgbe_dev_link_status_print(dev);
2944                 if (rte_eal_alarm_set(timeout * 1000,
2945                                       txgbe_dev_interrupt_delayed_handler,
2946                                       (void *)dev) < 0) {
2947                         PMD_DRV_LOG(ERR, "Error setting alarm");
2948                 } else {
2949                         /* remember original mask */
2950                         intr->mask_misc_orig = intr->mask_misc;
2951                         /* only disable lsc interrupt */
2952                         intr->mask_misc &= ~TXGBE_ICRMISC_LSC;
2953                 }
2954         }
2955
2956         PMD_DRV_LOG(DEBUG, "enable intr immediately");
2957         txgbe_enable_intr(dev);
2958         rte_intr_enable(intr_handle);
2959
2960         return 0;
2961 }
2962
2963 /**
2964  * Interrupt handler which shall be registered for alarm callback for delayed
2965  * handling specific interrupt to wait for the stable nic state. As the
2966  * NIC interrupt state is not stable for txgbe after link is just down,
2967  * it needs to wait 4 seconds to get the stable status.
2968  *
2969  * @param handle
2970  *  Pointer to interrupt handle.
2971  * @param param
2972  *  The address of parameter (struct rte_eth_dev *) registered before.
2973  *
2974  * @return
2975  *  void
2976  */
2977 static void
2978 txgbe_dev_interrupt_delayed_handler(void *param)
2979 {
2980         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2981         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2982         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2983         struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);
2984         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2985         uint32_t eicr;
2986
2987         txgbe_disable_intr(hw);
2988
2989         eicr = ((u32 *)hw->isb_mem)[TXGBE_ISB_MISC];
2990         if (eicr & TXGBE_ICRMISC_VFMBX)
2991                 txgbe_pf_mbx_process(dev);
2992
2993         if (intr->flags & TXGBE_FLAG_PHY_INTERRUPT) {
2994                 hw->phy.handle_lasi(hw);
2995                 intr->flags &= ~TXGBE_FLAG_PHY_INTERRUPT;
2996         }
2997
2998         if (intr->flags & TXGBE_FLAG_NEED_LINK_UPDATE) {
2999                 txgbe_dev_link_update(dev, 0);
3000                 intr->flags &= ~TXGBE_FLAG_NEED_LINK_UPDATE;
3001                 txgbe_dev_link_status_print(dev);
3002                 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC,
3003                                               NULL);
3004         }
3005
3006         if (intr->flags & TXGBE_FLAG_MACSEC) {
3007                 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_MACSEC,
3008                                               NULL);
3009                 intr->flags &= ~TXGBE_FLAG_MACSEC;
3010         }
3011
3012         /* restore original mask */
3013         intr->mask_misc = intr->mask_misc_orig;
3014         intr->mask_misc_orig = 0;
3015
3016         PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
3017         txgbe_enable_intr(dev);
3018         rte_intr_enable(intr_handle);
3019 }
3020
3021 /**
3022  * Interrupt handler triggered by NIC  for handling
3023  * specific interrupt.
3024  *
3025  * @param handle
3026  *  Pointer to interrupt handle.
3027  * @param param
3028  *  The address of parameter (struct rte_eth_dev *) registered before.
3029  *
3030  * @return
3031  *  void
3032  */
3033 static void
3034 txgbe_dev_interrupt_handler(void *param)
3035 {
3036         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3037
3038         txgbe_dev_interrupt_get_status(dev);
3039         txgbe_dev_interrupt_action(dev, dev->intr_handle);
3040 }
3041
3042 static int
3043 txgbe_dev_led_on(struct rte_eth_dev *dev)
3044 {
3045         struct txgbe_hw *hw;
3046
3047         hw = TXGBE_DEV_HW(dev);
3048         return txgbe_led_on(hw, 4) == 0 ? 0 : -ENOTSUP;
3049 }
3050
3051 static int
3052 txgbe_dev_led_off(struct rte_eth_dev *dev)
3053 {
3054         struct txgbe_hw *hw;
3055
3056         hw = TXGBE_DEV_HW(dev);
3057         return txgbe_led_off(hw, 4) == 0 ? 0 : -ENOTSUP;
3058 }
3059
3060 static int
3061 txgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3062 {
3063         struct txgbe_hw *hw;
3064         uint32_t mflcn_reg;
3065         uint32_t fccfg_reg;
3066         int rx_pause;
3067         int tx_pause;
3068
3069         hw = TXGBE_DEV_HW(dev);
3070
3071         fc_conf->pause_time = hw->fc.pause_time;
3072         fc_conf->high_water = hw->fc.high_water[0];
3073         fc_conf->low_water = hw->fc.low_water[0];
3074         fc_conf->send_xon = hw->fc.send_xon;
3075         fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
3076
3077         /*
3078          * Return rx_pause status according to actual setting of
3079          * RXFCCFG register.
3080          */
3081         mflcn_reg = rd32(hw, TXGBE_RXFCCFG);
3082         if (mflcn_reg & (TXGBE_RXFCCFG_FC | TXGBE_RXFCCFG_PFC))
3083                 rx_pause = 1;
3084         else
3085                 rx_pause = 0;
3086
3087         /*
3088          * Return tx_pause status according to actual setting of
3089          * TXFCCFG register.
3090          */
3091         fccfg_reg = rd32(hw, TXGBE_TXFCCFG);
3092         if (fccfg_reg & (TXGBE_TXFCCFG_FC | TXGBE_TXFCCFG_PFC))
3093                 tx_pause = 1;
3094         else
3095                 tx_pause = 0;
3096
3097         if (rx_pause && tx_pause)
3098                 fc_conf->mode = RTE_FC_FULL;
3099         else if (rx_pause)
3100                 fc_conf->mode = RTE_FC_RX_PAUSE;
3101         else if (tx_pause)
3102                 fc_conf->mode = RTE_FC_TX_PAUSE;
3103         else
3104                 fc_conf->mode = RTE_FC_NONE;
3105
3106         return 0;
3107 }
3108
3109 static int
3110 txgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3111 {
3112         struct txgbe_hw *hw;
3113         int err;
3114         uint32_t rx_buf_size;
3115         uint32_t max_high_water;
3116         enum txgbe_fc_mode rte_fcmode_2_txgbe_fcmode[] = {
3117                 txgbe_fc_none,
3118                 txgbe_fc_rx_pause,
3119                 txgbe_fc_tx_pause,
3120                 txgbe_fc_full
3121         };
3122
3123         PMD_INIT_FUNC_TRACE();
3124
3125         hw = TXGBE_DEV_HW(dev);
3126         rx_buf_size = rd32(hw, TXGBE_PBRXSIZE(0));
3127         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
3128
3129         /*
3130          * At least reserve one Ethernet frame for watermark
3131          * high_water/low_water in kilo bytes for txgbe
3132          */
3133         max_high_water = (rx_buf_size - RTE_ETHER_MAX_LEN) >> 10;
3134         if (fc_conf->high_water > max_high_water ||
3135             fc_conf->high_water < fc_conf->low_water) {
3136                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
3137                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
3138                 return -EINVAL;
3139         }
3140
3141         hw->fc.requested_mode = rte_fcmode_2_txgbe_fcmode[fc_conf->mode];
3142         hw->fc.pause_time     = fc_conf->pause_time;
3143         hw->fc.high_water[0]  = fc_conf->high_water;
3144         hw->fc.low_water[0]   = fc_conf->low_water;
3145         hw->fc.send_xon       = fc_conf->send_xon;
3146         hw->fc.disable_fc_autoneg = !fc_conf->autoneg;
3147
3148         err = txgbe_fc_enable(hw);
3149
3150         /* Not negotiated is not an error case */
3151         if (err == 0 || err == TXGBE_ERR_FC_NOT_NEGOTIATED) {
3152                 wr32m(hw, TXGBE_MACRXFLT, TXGBE_MACRXFLT_CTL_MASK,
3153                       (fc_conf->mac_ctrl_frame_fwd
3154                        ? TXGBE_MACRXFLT_CTL_NOPS : TXGBE_MACRXFLT_CTL_DROP));
3155                 txgbe_flush(hw);
3156
3157                 return 0;
3158         }
3159
3160         PMD_INIT_LOG(ERR, "txgbe_fc_enable = 0x%x", err);
3161         return -EIO;
3162 }
3163
3164 static int
3165 txgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
3166                 struct rte_eth_pfc_conf *pfc_conf)
3167 {
3168         int err;
3169         uint32_t rx_buf_size;
3170         uint32_t max_high_water;
3171         uint8_t tc_num;
3172         uint8_t  map[TXGBE_DCB_UP_MAX] = { 0 };
3173         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3174         struct txgbe_dcb_config *dcb_config = TXGBE_DEV_DCB_CONFIG(dev);
3175
3176         enum txgbe_fc_mode rte_fcmode_2_txgbe_fcmode[] = {
3177                 txgbe_fc_none,
3178                 txgbe_fc_rx_pause,
3179                 txgbe_fc_tx_pause,
3180                 txgbe_fc_full
3181         };
3182
3183         PMD_INIT_FUNC_TRACE();
3184
3185         txgbe_dcb_unpack_map_cee(dcb_config, TXGBE_DCB_RX_CONFIG, map);
3186         tc_num = map[pfc_conf->priority];
3187         rx_buf_size = rd32(hw, TXGBE_PBRXSIZE(tc_num));
3188         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
3189         /*
3190          * At least reserve one Ethernet frame for watermark
3191          * high_water/low_water in kilo bytes for txgbe
3192          */
3193         max_high_water = (rx_buf_size - RTE_ETHER_MAX_LEN) >> 10;
3194         if (pfc_conf->fc.high_water > max_high_water ||
3195             pfc_conf->fc.high_water <= pfc_conf->fc.low_water) {
3196                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
3197                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
3198                 return -EINVAL;
3199         }
3200
3201         hw->fc.requested_mode = rte_fcmode_2_txgbe_fcmode[pfc_conf->fc.mode];
3202         hw->fc.pause_time = pfc_conf->fc.pause_time;
3203         hw->fc.send_xon = pfc_conf->fc.send_xon;
3204         hw->fc.low_water[tc_num] =  pfc_conf->fc.low_water;
3205         hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
3206
3207         err = txgbe_dcb_pfc_enable(hw, tc_num);
3208
3209         /* Not negotiated is not an error case */
3210         if (err == 0 || err == TXGBE_ERR_FC_NOT_NEGOTIATED)
3211                 return 0;
3212
3213         PMD_INIT_LOG(ERR, "txgbe_dcb_pfc_enable = 0x%x", err);
3214         return -EIO;
3215 }
3216
3217 int
3218 txgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
3219                           struct rte_eth_rss_reta_entry64 *reta_conf,
3220                           uint16_t reta_size)
3221 {
3222         uint8_t i, j, mask;
3223         uint32_t reta;
3224         uint16_t idx, shift;
3225         struct txgbe_adapter *adapter = TXGBE_DEV_ADAPTER(dev);
3226         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3227
3228         PMD_INIT_FUNC_TRACE();
3229
3230         if (!txgbe_rss_update_sp(hw->mac.type)) {
3231                 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this "
3232                         "NIC.");
3233                 return -ENOTSUP;
3234         }
3235
3236         if (reta_size != ETH_RSS_RETA_SIZE_128) {
3237                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3238                         "(%d) doesn't match the number hardware can supported "
3239                         "(%d)", reta_size, ETH_RSS_RETA_SIZE_128);
3240                 return -EINVAL;
3241         }
3242
3243         for (i = 0; i < reta_size; i += 4) {
3244                 idx = i / RTE_RETA_GROUP_SIZE;
3245                 shift = i % RTE_RETA_GROUP_SIZE;
3246                 mask = (uint8_t)RS64(reta_conf[idx].mask, shift, 0xF);
3247                 if (!mask)
3248                         continue;
3249
3250                 reta = rd32a(hw, TXGBE_REG_RSSTBL, i >> 2);
3251                 for (j = 0; j < 4; j++) {
3252                         if (RS8(mask, j, 0x1)) {
3253                                 reta  &= ~(MS32(8 * j, 0xFF));
3254                                 reta |= LS32(reta_conf[idx].reta[shift + j],
3255                                                 8 * j, 0xFF);
3256                         }
3257                 }
3258                 wr32a(hw, TXGBE_REG_RSSTBL, i >> 2, reta);
3259         }
3260         adapter->rss_reta_updated = 1;
3261
3262         return 0;
3263 }
3264
3265 int
3266 txgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
3267                          struct rte_eth_rss_reta_entry64 *reta_conf,
3268                          uint16_t reta_size)
3269 {
3270         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3271         uint8_t i, j, mask;
3272         uint32_t reta;
3273         uint16_t idx, shift;
3274
3275         PMD_INIT_FUNC_TRACE();
3276
3277         if (reta_size != ETH_RSS_RETA_SIZE_128) {
3278                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3279                         "(%d) doesn't match the number hardware can supported "
3280                         "(%d)", reta_size, ETH_RSS_RETA_SIZE_128);
3281                 return -EINVAL;
3282         }
3283
3284         for (i = 0; i < reta_size; i += 4) {
3285                 idx = i / RTE_RETA_GROUP_SIZE;
3286                 shift = i % RTE_RETA_GROUP_SIZE;
3287                 mask = (uint8_t)RS64(reta_conf[idx].mask, shift, 0xF);
3288                 if (!mask)
3289                         continue;
3290
3291                 reta = rd32a(hw, TXGBE_REG_RSSTBL, i >> 2);
3292                 for (j = 0; j < 4; j++) {
3293                         if (RS8(mask, j, 0x1))
3294                                 reta_conf[idx].reta[shift + j] =
3295                                         (uint16_t)RS32(reta, 8 * j, 0xFF);
3296                 }
3297         }
3298
3299         return 0;
3300 }
3301
3302 static int
3303 txgbe_add_rar(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
3304                                 uint32_t index, uint32_t pool)
3305 {
3306         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3307         uint32_t enable_addr = 1;
3308
3309         return txgbe_set_rar(hw, index, mac_addr->addr_bytes,
3310                              pool, enable_addr);
3311 }
3312
3313 static void
3314 txgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
3315 {
3316         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3317
3318         txgbe_clear_rar(hw, index);
3319 }
3320
3321 static int
3322 txgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *addr)
3323 {
3324         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3325
3326         txgbe_remove_rar(dev, 0);
3327         txgbe_add_rar(dev, addr, 0, pci_dev->max_vfs);
3328
3329         return 0;
3330 }
3331
3332 static int
3333 txgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
3334 {
3335         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3336         struct rte_eth_dev_info dev_info;
3337         uint32_t frame_size = mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN;
3338         struct rte_eth_dev_data *dev_data = dev->data;
3339         int ret;
3340
3341         ret = txgbe_dev_info_get(dev, &dev_info);
3342         if (ret != 0)
3343                 return ret;
3344
3345         /* check that mtu is within the allowed range */
3346         if (mtu < RTE_ETHER_MIN_MTU || frame_size > dev_info.max_rx_pktlen)
3347                 return -EINVAL;
3348
3349         /* If device is started, refuse mtu that requires the support of
3350          * scattered packets when this feature has not been enabled before.
3351          */
3352         if (dev_data->dev_started && !dev_data->scattered_rx &&
3353             (frame_size + 2 * TXGBE_VLAN_TAG_SIZE >
3354              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
3355                 PMD_INIT_LOG(ERR, "Stop port first.");
3356                 return -EINVAL;
3357         }
3358
3359         /* update max frame size */
3360         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
3361
3362         if (hw->mode)
3363                 wr32m(hw, TXGBE_FRMSZ, TXGBE_FRMSZ_MAX_MASK,
3364                         TXGBE_FRAME_SIZE_MAX);
3365         else
3366                 wr32m(hw, TXGBE_FRMSZ, TXGBE_FRMSZ_MAX_MASK,
3367                         TXGBE_FRMSZ_MAX(frame_size));
3368
3369         return 0;
3370 }
3371
3372 static uint32_t
3373 txgbe_uta_vector(struct txgbe_hw *hw, struct rte_ether_addr *uc_addr)
3374 {
3375         uint32_t vector = 0;
3376
3377         switch (hw->mac.mc_filter_type) {
3378         case 0:   /* use bits [47:36] of the address */
3379                 vector = ((uc_addr->addr_bytes[4] >> 4) |
3380                         (((uint16_t)uc_addr->addr_bytes[5]) << 4));
3381                 break;
3382         case 1:   /* use bits [46:35] of the address */
3383                 vector = ((uc_addr->addr_bytes[4] >> 3) |
3384                         (((uint16_t)uc_addr->addr_bytes[5]) << 5));
3385                 break;
3386         case 2:   /* use bits [45:34] of the address */
3387                 vector = ((uc_addr->addr_bytes[4] >> 2) |
3388                         (((uint16_t)uc_addr->addr_bytes[5]) << 6));
3389                 break;
3390         case 3:   /* use bits [43:32] of the address */
3391                 vector = ((uc_addr->addr_bytes[4]) |
3392                         (((uint16_t)uc_addr->addr_bytes[5]) << 8));
3393                 break;
3394         default:  /* Invalid mc_filter_type */
3395                 break;
3396         }
3397
3398         /* vector can only be 12-bits or boundary will be exceeded */
3399         vector &= 0xFFF;
3400         return vector;
3401 }
3402
3403 static int
3404 txgbe_uc_hash_table_set(struct rte_eth_dev *dev,
3405                         struct rte_ether_addr *mac_addr, uint8_t on)
3406 {
3407         uint32_t vector;
3408         uint32_t uta_idx;
3409         uint32_t reg_val;
3410         uint32_t uta_mask;
3411         uint32_t psrctl;
3412
3413         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3414         struct txgbe_uta_info *uta_info = TXGBE_DEV_UTA_INFO(dev);
3415
3416         /* The UTA table only exists on pf hardware */
3417         if (hw->mac.type < txgbe_mac_raptor)
3418                 return -ENOTSUP;
3419
3420         vector = txgbe_uta_vector(hw, mac_addr);
3421         uta_idx = (vector >> 5) & 0x7F;
3422         uta_mask = 0x1UL << (vector & 0x1F);
3423
3424         if (!!on == !!(uta_info->uta_shadow[uta_idx] & uta_mask))
3425                 return 0;
3426
3427         reg_val = rd32(hw, TXGBE_UCADDRTBL(uta_idx));
3428         if (on) {
3429                 uta_info->uta_in_use++;
3430                 reg_val |= uta_mask;
3431                 uta_info->uta_shadow[uta_idx] |= uta_mask;
3432         } else {
3433                 uta_info->uta_in_use--;
3434                 reg_val &= ~uta_mask;
3435                 uta_info->uta_shadow[uta_idx] &= ~uta_mask;
3436         }
3437
3438         wr32(hw, TXGBE_UCADDRTBL(uta_idx), reg_val);
3439
3440         psrctl = rd32(hw, TXGBE_PSRCTL);
3441         if (uta_info->uta_in_use > 0)
3442                 psrctl |= TXGBE_PSRCTL_UCHFENA;
3443         else
3444                 psrctl &= ~TXGBE_PSRCTL_UCHFENA;
3445
3446         psrctl &= ~TXGBE_PSRCTL_ADHF12_MASK;
3447         psrctl |= TXGBE_PSRCTL_ADHF12(hw->mac.mc_filter_type);
3448         wr32(hw, TXGBE_PSRCTL, psrctl);
3449
3450         return 0;
3451 }
3452
3453 static int
3454 txgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
3455 {
3456         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3457         struct txgbe_uta_info *uta_info = TXGBE_DEV_UTA_INFO(dev);
3458         uint32_t psrctl;
3459         int i;
3460
3461         /* The UTA table only exists on pf hardware */
3462         if (hw->mac.type < txgbe_mac_raptor)
3463                 return -ENOTSUP;
3464
3465         if (on) {
3466                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
3467                         uta_info->uta_shadow[i] = ~0;
3468                         wr32(hw, TXGBE_UCADDRTBL(i), ~0);
3469                 }
3470         } else {
3471                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
3472                         uta_info->uta_shadow[i] = 0;
3473                         wr32(hw, TXGBE_UCADDRTBL(i), 0);
3474                 }
3475         }
3476
3477         psrctl = rd32(hw, TXGBE_PSRCTL);
3478         if (on)
3479                 psrctl |= TXGBE_PSRCTL_UCHFENA;
3480         else
3481                 psrctl &= ~TXGBE_PSRCTL_UCHFENA;
3482
3483         psrctl &= ~TXGBE_PSRCTL_ADHF12_MASK;
3484         psrctl |= TXGBE_PSRCTL_ADHF12(hw->mac.mc_filter_type);
3485         wr32(hw, TXGBE_PSRCTL, psrctl);
3486
3487         return 0;
3488 }
3489
3490 uint32_t
3491 txgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
3492 {
3493         uint32_t new_val = orig_val;
3494
3495         if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
3496                 new_val |= TXGBE_POOLETHCTL_UTA;
3497         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
3498                 new_val |= TXGBE_POOLETHCTL_MCHA;
3499         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
3500                 new_val |= TXGBE_POOLETHCTL_UCHA;
3501         if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
3502                 new_val |= TXGBE_POOLETHCTL_BCA;
3503         if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
3504                 new_val |= TXGBE_POOLETHCTL_MCP;
3505
3506         return new_val;
3507 }
3508
3509 static int
3510 txgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
3511 {
3512         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3513         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3514         uint32_t mask;
3515         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3516
3517         if (queue_id < 32) {
3518                 mask = rd32(hw, TXGBE_IMS(0));
3519                 mask &= (1 << queue_id);
3520                 wr32(hw, TXGBE_IMS(0), mask);
3521         } else if (queue_id < 64) {
3522                 mask = rd32(hw, TXGBE_IMS(1));
3523                 mask &= (1 << (queue_id - 32));
3524                 wr32(hw, TXGBE_IMS(1), mask);
3525         }
3526         rte_intr_enable(intr_handle);
3527
3528         return 0;
3529 }
3530
3531 static int
3532 txgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
3533 {
3534         uint32_t mask;
3535         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3536
3537         if (queue_id < 32) {
3538                 mask = rd32(hw, TXGBE_IMS(0));
3539                 mask &= ~(1 << queue_id);
3540                 wr32(hw, TXGBE_IMS(0), mask);
3541         } else if (queue_id < 64) {
3542                 mask = rd32(hw, TXGBE_IMS(1));
3543                 mask &= ~(1 << (queue_id - 32));
3544                 wr32(hw, TXGBE_IMS(1), mask);
3545         }
3546
3547         return 0;
3548 }
3549
3550 /**
3551  * set the IVAR registers, mapping interrupt causes to vectors
3552  * @param hw
3553  *  pointer to txgbe_hw struct
3554  * @direction
3555  *  0 for Rx, 1 for Tx, -1 for other causes
3556  * @queue
3557  *  queue to map the corresponding interrupt to
3558  * @msix_vector
3559  *  the vector to map to the corresponding queue
3560  */
3561 void
3562 txgbe_set_ivar_map(struct txgbe_hw *hw, int8_t direction,
3563                    uint8_t queue, uint8_t msix_vector)
3564 {
3565         uint32_t tmp, idx;
3566
3567         if (direction == -1) {
3568                 /* other causes */
3569                 msix_vector |= TXGBE_IVARMISC_VLD;
3570                 idx = 0;
3571                 tmp = rd32(hw, TXGBE_IVARMISC);
3572                 tmp &= ~(0xFF << idx);
3573                 tmp |= (msix_vector << idx);
3574                 wr32(hw, TXGBE_IVARMISC, tmp);
3575         } else {
3576                 /* rx or tx causes */
3577                 /* Workround for ICR lost */
3578                 idx = ((16 * (queue & 1)) + (8 * direction));
3579                 tmp = rd32(hw, TXGBE_IVAR(queue >> 1));
3580                 tmp &= ~(0xFF << idx);
3581                 tmp |= (msix_vector << idx);
3582                 wr32(hw, TXGBE_IVAR(queue >> 1), tmp);
3583         }
3584 }
3585
3586 /**
3587  * Sets up the hardware to properly generate MSI-X interrupts
3588  * @hw
3589  *  board private structure
3590  */
3591 static void
3592 txgbe_configure_msix(struct rte_eth_dev *dev)
3593 {
3594         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3595         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3596         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3597         uint32_t queue_id, base = TXGBE_MISC_VEC_ID;
3598         uint32_t vec = TXGBE_MISC_VEC_ID;
3599         uint32_t gpie;
3600
3601         /* won't configure msix register if no mapping is done
3602          * between intr vector and event fd
3603          * but if misx has been enabled already, need to configure
3604          * auto clean, auto mask and throttling.
3605          */
3606         gpie = rd32(hw, TXGBE_GPIE);
3607         if (!rte_intr_dp_is_en(intr_handle) &&
3608             !(gpie & TXGBE_GPIE_MSIX))
3609                 return;
3610
3611         if (rte_intr_allow_others(intr_handle)) {
3612                 base = TXGBE_RX_VEC_START;
3613                 vec = base;
3614         }
3615
3616         /* setup GPIE for MSI-x mode */
3617         gpie = rd32(hw, TXGBE_GPIE);
3618         gpie |= TXGBE_GPIE_MSIX;
3619         wr32(hw, TXGBE_GPIE, gpie);
3620
3621         /* Populate the IVAR table and set the ITR values to the
3622          * corresponding register.
3623          */
3624         if (rte_intr_dp_is_en(intr_handle)) {
3625                 for (queue_id = 0; queue_id < dev->data->nb_rx_queues;
3626                         queue_id++) {
3627                         /* by default, 1:1 mapping */
3628                         txgbe_set_ivar_map(hw, 0, queue_id, vec);
3629                         intr_handle->intr_vec[queue_id] = vec;
3630                         if (vec < base + intr_handle->nb_efd - 1)
3631                                 vec++;
3632                 }
3633
3634                 txgbe_set_ivar_map(hw, -1, 1, TXGBE_MISC_VEC_ID);
3635         }
3636         wr32(hw, TXGBE_ITR(TXGBE_MISC_VEC_ID),
3637                         TXGBE_ITR_IVAL_10G(TXGBE_QUEUE_ITR_INTERVAL_DEFAULT)
3638                         | TXGBE_ITR_WRDSA);
3639 }
3640
3641 int
3642 txgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
3643                            uint16_t queue_idx, uint16_t tx_rate)
3644 {
3645         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3646         uint32_t bcnrc_val;
3647
3648         if (queue_idx >= hw->mac.max_tx_queues)
3649                 return -EINVAL;
3650
3651         if (tx_rate != 0) {
3652                 bcnrc_val = TXGBE_ARBTXRATE_MAX(tx_rate);
3653                 bcnrc_val |= TXGBE_ARBTXRATE_MIN(tx_rate / 2);
3654         } else {
3655                 bcnrc_val = 0;
3656         }
3657
3658         /*
3659          * Set global transmit compensation time to the MMW_SIZE in ARBTXMMW
3660          * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported.
3661          */
3662         wr32(hw, TXGBE_ARBTXMMW, 0x14);
3663
3664         /* Set ARBTXRATE of queue X */
3665         wr32(hw, TXGBE_ARBPOOLIDX, queue_idx);
3666         wr32(hw, TXGBE_ARBTXRATE, bcnrc_val);
3667         txgbe_flush(hw);
3668
3669         return 0;
3670 }
3671
3672 int
3673 txgbe_syn_filter_set(struct rte_eth_dev *dev,
3674                         struct rte_eth_syn_filter *filter,
3675                         bool add)
3676 {
3677         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3678         struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(dev);
3679         uint32_t syn_info;
3680         uint32_t synqf;
3681
3682         if (filter->queue >= TXGBE_MAX_RX_QUEUE_NUM)
3683                 return -EINVAL;
3684
3685         syn_info = filter_info->syn_info;
3686
3687         if (add) {
3688                 if (syn_info & TXGBE_SYNCLS_ENA)
3689                         return -EINVAL;
3690                 synqf = (uint32_t)TXGBE_SYNCLS_QPID(filter->queue);
3691                 synqf |= TXGBE_SYNCLS_ENA;
3692
3693                 if (filter->hig_pri)
3694                         synqf |= TXGBE_SYNCLS_HIPRIO;
3695                 else
3696                         synqf &= ~TXGBE_SYNCLS_HIPRIO;
3697         } else {
3698                 synqf = rd32(hw, TXGBE_SYNCLS);
3699                 if (!(syn_info & TXGBE_SYNCLS_ENA))
3700                         return -ENOENT;
3701                 synqf &= ~(TXGBE_SYNCLS_QPID_MASK | TXGBE_SYNCLS_ENA);
3702         }
3703
3704         filter_info->syn_info = synqf;
3705         wr32(hw, TXGBE_SYNCLS, synqf);
3706         txgbe_flush(hw);
3707         return 0;
3708 }
3709
3710 static inline enum txgbe_5tuple_protocol
3711 convert_protocol_type(uint8_t protocol_value)
3712 {
3713         if (protocol_value == IPPROTO_TCP)
3714                 return TXGBE_5TF_PROT_TCP;
3715         else if (protocol_value == IPPROTO_UDP)
3716                 return TXGBE_5TF_PROT_UDP;
3717         else if (protocol_value == IPPROTO_SCTP)
3718                 return TXGBE_5TF_PROT_SCTP;
3719         else
3720                 return TXGBE_5TF_PROT_NONE;
3721 }
3722
3723 /* inject a 5-tuple filter to HW */
3724 static inline void
3725 txgbe_inject_5tuple_filter(struct rte_eth_dev *dev,
3726                            struct txgbe_5tuple_filter *filter)
3727 {
3728         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3729         int i;
3730         uint32_t ftqf, sdpqf;
3731         uint32_t l34timir = 0;
3732         uint32_t mask = TXGBE_5TFCTL0_MASK;
3733
3734         i = filter->index;
3735         sdpqf = TXGBE_5TFPORT_DST(be_to_le16(filter->filter_info.dst_port));
3736         sdpqf |= TXGBE_5TFPORT_SRC(be_to_le16(filter->filter_info.src_port));
3737
3738         ftqf = TXGBE_5TFCTL0_PROTO(filter->filter_info.proto);
3739         ftqf |= TXGBE_5TFCTL0_PRI(filter->filter_info.priority);
3740         if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
3741                 mask &= ~TXGBE_5TFCTL0_MSADDR;
3742         if (filter->filter_info.dst_ip_mask == 0)
3743                 mask &= ~TXGBE_5TFCTL0_MDADDR;
3744         if (filter->filter_info.src_port_mask == 0)
3745                 mask &= ~TXGBE_5TFCTL0_MSPORT;
3746         if (filter->filter_info.dst_port_mask == 0)
3747                 mask &= ~TXGBE_5TFCTL0_MDPORT;
3748         if (filter->filter_info.proto_mask == 0)
3749                 mask &= ~TXGBE_5TFCTL0_MPROTO;
3750         ftqf |= mask;
3751         ftqf |= TXGBE_5TFCTL0_MPOOL;
3752         ftqf |= TXGBE_5TFCTL0_ENA;
3753
3754         wr32(hw, TXGBE_5TFDADDR(i), be_to_le32(filter->filter_info.dst_ip));
3755         wr32(hw, TXGBE_5TFSADDR(i), be_to_le32(filter->filter_info.src_ip));
3756         wr32(hw, TXGBE_5TFPORT(i), sdpqf);
3757         wr32(hw, TXGBE_5TFCTL0(i), ftqf);
3758
3759         l34timir |= TXGBE_5TFCTL1_QP(filter->queue);
3760         wr32(hw, TXGBE_5TFCTL1(i), l34timir);
3761 }
3762
3763 /*
3764  * add a 5tuple filter
3765  *
3766  * @param
3767  * dev: Pointer to struct rte_eth_dev.
3768  * index: the index the filter allocates.
3769  * filter: pointer to the filter that will be added.
3770  * rx_queue: the queue id the filter assigned to.
3771  *
3772  * @return
3773  *    - On success, zero.
3774  *    - On failure, a negative value.
3775  */
3776 static int
3777 txgbe_add_5tuple_filter(struct rte_eth_dev *dev,
3778                         struct txgbe_5tuple_filter *filter)
3779 {
3780         struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(dev);
3781         int i, idx, shift;
3782
3783         /*
3784          * look for an unused 5tuple filter index,
3785          * and insert the filter to list.
3786          */
3787         for (i = 0; i < TXGBE_MAX_FTQF_FILTERS; i++) {
3788                 idx = i / (sizeof(uint32_t) * NBBY);
3789                 shift = i % (sizeof(uint32_t) * NBBY);
3790                 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
3791                         filter_info->fivetuple_mask[idx] |= 1 << shift;
3792                         filter->index = i;
3793                         TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
3794                                           filter,
3795                                           entries);
3796                         break;
3797                 }
3798         }
3799         if (i >= TXGBE_MAX_FTQF_FILTERS) {
3800                 PMD_DRV_LOG(ERR, "5tuple filters are full.");
3801                 return -ENOSYS;
3802         }
3803
3804         txgbe_inject_5tuple_filter(dev, filter);
3805
3806         return 0;
3807 }
3808
3809 /*
3810  * remove a 5tuple filter
3811  *
3812  * @param
3813  * dev: Pointer to struct rte_eth_dev.
3814  * filter: the pointer of the filter will be removed.
3815  */
3816 static void
3817 txgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
3818                         struct txgbe_5tuple_filter *filter)
3819 {
3820         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3821         struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(dev);
3822         uint16_t index = filter->index;
3823
3824         filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
3825                                 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
3826         TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
3827         rte_free(filter);
3828
3829         wr32(hw, TXGBE_5TFDADDR(index), 0);
3830         wr32(hw, TXGBE_5TFSADDR(index), 0);
3831         wr32(hw, TXGBE_5TFPORT(index), 0);
3832         wr32(hw, TXGBE_5TFCTL0(index), 0);
3833         wr32(hw, TXGBE_5TFCTL1(index), 0);
3834 }
3835
3836 static inline struct txgbe_5tuple_filter *
3837 txgbe_5tuple_filter_lookup(struct txgbe_5tuple_filter_list *filter_list,
3838                         struct txgbe_5tuple_filter_info *key)
3839 {
3840         struct txgbe_5tuple_filter *it;
3841
3842         TAILQ_FOREACH(it, filter_list, entries) {
3843                 if (memcmp(key, &it->filter_info,
3844                         sizeof(struct txgbe_5tuple_filter_info)) == 0) {
3845                         return it;
3846                 }
3847         }
3848         return NULL;
3849 }
3850
3851 /* translate elements in struct rte_eth_ntuple_filter
3852  * to struct txgbe_5tuple_filter_info
3853  */
3854 static inline int
3855 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
3856                         struct txgbe_5tuple_filter_info *filter_info)
3857 {
3858         if (filter->queue >= TXGBE_MAX_RX_QUEUE_NUM ||
3859                 filter->priority > TXGBE_5TUPLE_MAX_PRI ||
3860                 filter->priority < TXGBE_5TUPLE_MIN_PRI)
3861                 return -EINVAL;
3862
3863         switch (filter->dst_ip_mask) {
3864         case UINT32_MAX:
3865                 filter_info->dst_ip_mask = 0;
3866                 filter_info->dst_ip = filter->dst_ip;
3867                 break;
3868         case 0:
3869                 filter_info->dst_ip_mask = 1;
3870                 break;
3871         default:
3872                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
3873                 return -EINVAL;
3874         }
3875
3876         switch (filter->src_ip_mask) {
3877         case UINT32_MAX:
3878                 filter_info->src_ip_mask = 0;
3879                 filter_info->src_ip = filter->src_ip;
3880                 break;
3881         case 0:
3882                 filter_info->src_ip_mask = 1;
3883                 break;
3884         default:
3885                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
3886                 return -EINVAL;
3887         }
3888
3889         switch (filter->dst_port_mask) {
3890         case UINT16_MAX:
3891                 filter_info->dst_port_mask = 0;
3892                 filter_info->dst_port = filter->dst_port;
3893                 break;
3894         case 0:
3895                 filter_info->dst_port_mask = 1;
3896                 break;
3897         default:
3898                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
3899                 return -EINVAL;
3900         }
3901
3902         switch (filter->src_port_mask) {
3903         case UINT16_MAX:
3904                 filter_info->src_port_mask = 0;
3905                 filter_info->src_port = filter->src_port;
3906                 break;
3907         case 0:
3908                 filter_info->src_port_mask = 1;
3909                 break;
3910         default:
3911                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
3912                 return -EINVAL;
3913         }
3914
3915         switch (filter->proto_mask) {
3916         case UINT8_MAX:
3917                 filter_info->proto_mask = 0;
3918                 filter_info->proto =
3919                         convert_protocol_type(filter->proto);
3920                 break;
3921         case 0:
3922                 filter_info->proto_mask = 1;
3923                 break;
3924         default:
3925                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
3926                 return -EINVAL;
3927         }
3928
3929         filter_info->priority = (uint8_t)filter->priority;
3930         return 0;
3931 }
3932
3933 /*
3934  * add or delete a ntuple filter
3935  *
3936  * @param
3937  * dev: Pointer to struct rte_eth_dev.
3938  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
3939  * add: if true, add filter, if false, remove filter
3940  *
3941  * @return
3942  *    - On success, zero.
3943  *    - On failure, a negative value.
3944  */
3945 int
3946 txgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
3947                         struct rte_eth_ntuple_filter *ntuple_filter,
3948                         bool add)
3949 {
3950         struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(dev);
3951         struct txgbe_5tuple_filter_info filter_5tuple;
3952         struct txgbe_5tuple_filter *filter;
3953         int ret;
3954
3955         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
3956                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
3957                 return -EINVAL;
3958         }
3959
3960         memset(&filter_5tuple, 0, sizeof(struct txgbe_5tuple_filter_info));
3961         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
3962         if (ret < 0)
3963                 return ret;
3964
3965         filter = txgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
3966                                          &filter_5tuple);
3967         if (filter != NULL && add) {
3968                 PMD_DRV_LOG(ERR, "filter exists.");
3969                 return -EEXIST;
3970         }
3971         if (filter == NULL && !add) {
3972                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3973                 return -ENOENT;
3974         }
3975
3976         if (add) {
3977                 filter = rte_zmalloc("txgbe_5tuple_filter",
3978                                 sizeof(struct txgbe_5tuple_filter), 0);
3979                 if (filter == NULL)
3980                         return -ENOMEM;
3981                 rte_memcpy(&filter->filter_info,
3982                                  &filter_5tuple,
3983                                  sizeof(struct txgbe_5tuple_filter_info));
3984                 filter->queue = ntuple_filter->queue;
3985                 ret = txgbe_add_5tuple_filter(dev, filter);
3986                 if (ret < 0) {
3987                         rte_free(filter);
3988                         return ret;
3989                 }
3990         } else {
3991                 txgbe_remove_5tuple_filter(dev, filter);
3992         }
3993
3994         return 0;
3995 }
3996
3997 int
3998 txgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
3999                         struct rte_eth_ethertype_filter *filter,
4000                         bool add)
4001 {
4002         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4003         struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(dev);
4004         uint32_t etqf = 0;
4005         uint32_t etqs = 0;
4006         int ret;
4007         struct txgbe_ethertype_filter ethertype_filter;
4008
4009         if (filter->queue >= TXGBE_MAX_RX_QUEUE_NUM)
4010                 return -EINVAL;
4011
4012         if (filter->ether_type == RTE_ETHER_TYPE_IPV4 ||
4013             filter->ether_type == RTE_ETHER_TYPE_IPV6) {
4014                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
4015                         " ethertype filter.", filter->ether_type);
4016                 return -EINVAL;
4017         }
4018
4019         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
4020                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
4021                 return -EINVAL;
4022         }
4023         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
4024                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
4025                 return -EINVAL;
4026         }
4027
4028         ret = txgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
4029         if (ret >= 0 && add) {
4030                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
4031                             filter->ether_type);
4032                 return -EEXIST;
4033         }
4034         if (ret < 0 && !add) {
4035                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
4036                             filter->ether_type);
4037                 return -ENOENT;
4038         }
4039
4040         if (add) {
4041                 etqf = TXGBE_ETFLT_ENA;
4042                 etqf |= TXGBE_ETFLT_ETID(filter->ether_type);
4043                 etqs |= TXGBE_ETCLS_QPID(filter->queue);
4044                 etqs |= TXGBE_ETCLS_QENA;
4045
4046                 ethertype_filter.ethertype = filter->ether_type;
4047                 ethertype_filter.etqf = etqf;
4048                 ethertype_filter.etqs = etqs;
4049                 ethertype_filter.conf = FALSE;
4050                 ret = txgbe_ethertype_filter_insert(filter_info,
4051                                                     &ethertype_filter);
4052                 if (ret < 0) {
4053                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
4054                         return -ENOSPC;
4055                 }
4056         } else {
4057                 ret = txgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
4058                 if (ret < 0)
4059                         return -ENOSYS;
4060         }
4061         wr32(hw, TXGBE_ETFLT(ret), etqf);
4062         wr32(hw, TXGBE_ETCLS(ret), etqs);
4063         txgbe_flush(hw);
4064
4065         return 0;
4066 }
4067
4068 static int
4069 txgbe_dev_filter_ctrl(__rte_unused struct rte_eth_dev *dev,
4070                      enum rte_filter_type filter_type,
4071                      enum rte_filter_op filter_op,
4072                      void *arg)
4073 {
4074         int ret = 0;
4075
4076         switch (filter_type) {
4077         case RTE_ETH_FILTER_GENERIC:
4078                 if (filter_op != RTE_ETH_FILTER_GET)
4079                         return -EINVAL;
4080                 *(const void **)arg = &txgbe_flow_ops;
4081                 break;
4082         default:
4083                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
4084                                                         filter_type);
4085                 ret = -EINVAL;
4086                 break;
4087         }
4088
4089         return ret;
4090 }
4091
4092 static u8 *
4093 txgbe_dev_addr_list_itr(__rte_unused struct txgbe_hw *hw,
4094                         u8 **mc_addr_ptr, u32 *vmdq)
4095 {
4096         u8 *mc_addr;
4097
4098         *vmdq = 0;
4099         mc_addr = *mc_addr_ptr;
4100         *mc_addr_ptr = (mc_addr + sizeof(struct rte_ether_addr));
4101         return mc_addr;
4102 }
4103
4104 int
4105 txgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
4106                           struct rte_ether_addr *mc_addr_set,
4107                           uint32_t nb_mc_addr)
4108 {
4109         struct txgbe_hw *hw;
4110         u8 *mc_addr_list;
4111
4112         hw = TXGBE_DEV_HW(dev);
4113         mc_addr_list = (u8 *)mc_addr_set;
4114         return txgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
4115                                          txgbe_dev_addr_list_itr, TRUE);
4116 }
4117
4118 static uint64_t
4119 txgbe_read_systime_cyclecounter(struct rte_eth_dev *dev)
4120 {
4121         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4122         uint64_t systime_cycles;
4123
4124         systime_cycles = (uint64_t)rd32(hw, TXGBE_TSTIMEL);
4125         systime_cycles |= (uint64_t)rd32(hw, TXGBE_TSTIMEH) << 32;
4126
4127         return systime_cycles;
4128 }
4129
4130 static uint64_t
4131 txgbe_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
4132 {
4133         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4134         uint64_t rx_tstamp_cycles;
4135
4136         /* TSRXSTMPL stores ns and TSRXSTMPH stores seconds. */
4137         rx_tstamp_cycles = (uint64_t)rd32(hw, TXGBE_TSRXSTMPL);
4138         rx_tstamp_cycles |= (uint64_t)rd32(hw, TXGBE_TSRXSTMPH) << 32;
4139
4140         return rx_tstamp_cycles;
4141 }
4142
4143 static uint64_t
4144 txgbe_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
4145 {
4146         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4147         uint64_t tx_tstamp_cycles;
4148
4149         /* TSTXSTMPL stores ns and TSTXSTMPH stores seconds. */
4150         tx_tstamp_cycles = (uint64_t)rd32(hw, TXGBE_TSTXSTMPL);
4151         tx_tstamp_cycles |= (uint64_t)rd32(hw, TXGBE_TSTXSTMPH) << 32;
4152
4153         return tx_tstamp_cycles;
4154 }
4155
4156 static void
4157 txgbe_start_timecounters(struct rte_eth_dev *dev)
4158 {
4159         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4160         struct txgbe_adapter *adapter = TXGBE_DEV_ADAPTER(dev);
4161         struct rte_eth_link link;
4162         uint32_t incval = 0;
4163         uint32_t shift = 0;
4164
4165         /* Get current link speed. */
4166         txgbe_dev_link_update(dev, 1);
4167         rte_eth_linkstatus_get(dev, &link);
4168
4169         switch (link.link_speed) {
4170         case ETH_SPEED_NUM_100M:
4171                 incval = TXGBE_INCVAL_100;
4172                 shift = TXGBE_INCVAL_SHIFT_100;
4173                 break;
4174         case ETH_SPEED_NUM_1G:
4175                 incval = TXGBE_INCVAL_1GB;
4176                 shift = TXGBE_INCVAL_SHIFT_1GB;
4177                 break;
4178         case ETH_SPEED_NUM_10G:
4179         default:
4180                 incval = TXGBE_INCVAL_10GB;
4181                 shift = TXGBE_INCVAL_SHIFT_10GB;
4182                 break;
4183         }
4184
4185         wr32(hw, TXGBE_TSTIMEINC, TXGBE_TSTIMEINC_VP(incval, 2));
4186
4187         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
4188         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
4189         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
4190
4191         adapter->systime_tc.cc_mask = TXGBE_CYCLECOUNTER_MASK;
4192         adapter->systime_tc.cc_shift = shift;
4193         adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
4194
4195         adapter->rx_tstamp_tc.cc_mask = TXGBE_CYCLECOUNTER_MASK;
4196         adapter->rx_tstamp_tc.cc_shift = shift;
4197         adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
4198
4199         adapter->tx_tstamp_tc.cc_mask = TXGBE_CYCLECOUNTER_MASK;
4200         adapter->tx_tstamp_tc.cc_shift = shift;
4201         adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
4202 }
4203
4204 static int
4205 txgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
4206 {
4207         struct txgbe_adapter *adapter = TXGBE_DEV_ADAPTER(dev);
4208
4209         adapter->systime_tc.nsec += delta;
4210         adapter->rx_tstamp_tc.nsec += delta;
4211         adapter->tx_tstamp_tc.nsec += delta;
4212
4213         return 0;
4214 }
4215
4216 static int
4217 txgbe_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
4218 {
4219         uint64_t ns;
4220         struct txgbe_adapter *adapter = TXGBE_DEV_ADAPTER(dev);
4221
4222         ns = rte_timespec_to_ns(ts);
4223         /* Set the timecounters to a new value. */
4224         adapter->systime_tc.nsec = ns;
4225         adapter->rx_tstamp_tc.nsec = ns;
4226         adapter->tx_tstamp_tc.nsec = ns;
4227
4228         return 0;
4229 }
4230
4231 static int
4232 txgbe_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
4233 {
4234         uint64_t ns, systime_cycles;
4235         struct txgbe_adapter *adapter = TXGBE_DEV_ADAPTER(dev);
4236
4237         systime_cycles = txgbe_read_systime_cyclecounter(dev);
4238         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
4239         *ts = rte_ns_to_timespec(ns);
4240
4241         return 0;
4242 }
4243
4244 static int
4245 txgbe_timesync_enable(struct rte_eth_dev *dev)
4246 {
4247         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4248         uint32_t tsync_ctl;
4249
4250         /* Stop the timesync system time. */
4251         wr32(hw, TXGBE_TSTIMEINC, 0x0);
4252         /* Reset the timesync system time value. */
4253         wr32(hw, TXGBE_TSTIMEL, 0x0);
4254         wr32(hw, TXGBE_TSTIMEH, 0x0);
4255
4256         txgbe_start_timecounters(dev);
4257
4258         /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
4259         wr32(hw, TXGBE_ETFLT(TXGBE_ETF_ID_1588),
4260                 RTE_ETHER_TYPE_1588 | TXGBE_ETFLT_ENA | TXGBE_ETFLT_1588);
4261
4262         /* Enable timestamping of received PTP packets. */
4263         tsync_ctl = rd32(hw, TXGBE_TSRXCTL);
4264         tsync_ctl |= TXGBE_TSRXCTL_ENA;
4265         wr32(hw, TXGBE_TSRXCTL, tsync_ctl);
4266
4267         /* Enable timestamping of transmitted PTP packets. */
4268         tsync_ctl = rd32(hw, TXGBE_TSTXCTL);
4269         tsync_ctl |= TXGBE_TSTXCTL_ENA;
4270         wr32(hw, TXGBE_TSTXCTL, tsync_ctl);
4271
4272         txgbe_flush(hw);
4273
4274         return 0;
4275 }
4276
4277 static int
4278 txgbe_timesync_disable(struct rte_eth_dev *dev)
4279 {
4280         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4281         uint32_t tsync_ctl;
4282
4283         /* Disable timestamping of transmitted PTP packets. */
4284         tsync_ctl = rd32(hw, TXGBE_TSTXCTL);
4285         tsync_ctl &= ~TXGBE_TSTXCTL_ENA;
4286         wr32(hw, TXGBE_TSTXCTL, tsync_ctl);
4287
4288         /* Disable timestamping of received PTP packets. */
4289         tsync_ctl = rd32(hw, TXGBE_TSRXCTL);
4290         tsync_ctl &= ~TXGBE_TSRXCTL_ENA;
4291         wr32(hw, TXGBE_TSRXCTL, tsync_ctl);
4292
4293         /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
4294         wr32(hw, TXGBE_ETFLT(TXGBE_ETF_ID_1588), 0);
4295
4296         /* Stop incrementating the System Time registers. */
4297         wr32(hw, TXGBE_TSTIMEINC, 0);
4298
4299         return 0;
4300 }
4301
4302 static int
4303 txgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
4304                                  struct timespec *timestamp,
4305                                  uint32_t flags __rte_unused)
4306 {
4307         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4308         struct txgbe_adapter *adapter = TXGBE_DEV_ADAPTER(dev);
4309         uint32_t tsync_rxctl;
4310         uint64_t rx_tstamp_cycles;
4311         uint64_t ns;
4312
4313         tsync_rxctl = rd32(hw, TXGBE_TSRXCTL);
4314         if ((tsync_rxctl & TXGBE_TSRXCTL_VLD) == 0)
4315                 return -EINVAL;
4316
4317         rx_tstamp_cycles = txgbe_read_rx_tstamp_cyclecounter(dev);
4318         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
4319         *timestamp = rte_ns_to_timespec(ns);
4320
4321         return  0;
4322 }
4323
4324 static int
4325 txgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
4326                                  struct timespec *timestamp)
4327 {
4328         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4329         struct txgbe_adapter *adapter = TXGBE_DEV_ADAPTER(dev);
4330         uint32_t tsync_txctl;
4331         uint64_t tx_tstamp_cycles;
4332         uint64_t ns;
4333
4334         tsync_txctl = rd32(hw, TXGBE_TSTXCTL);
4335         if ((tsync_txctl & TXGBE_TSTXCTL_VLD) == 0)
4336                 return -EINVAL;
4337
4338         tx_tstamp_cycles = txgbe_read_tx_tstamp_cyclecounter(dev);
4339         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
4340         *timestamp = rte_ns_to_timespec(ns);
4341
4342         return 0;
4343 }
4344
4345 static int
4346 txgbe_get_reg_length(struct rte_eth_dev *dev __rte_unused)
4347 {
4348         int count = 0;
4349         int g_ind = 0;
4350         const struct reg_info *reg_group;
4351         const struct reg_info **reg_set = txgbe_regs_others;
4352
4353         while ((reg_group = reg_set[g_ind++]))
4354                 count += txgbe_regs_group_count(reg_group);
4355
4356         return count;
4357 }
4358
4359 static int
4360 txgbe_get_regs(struct rte_eth_dev *dev,
4361               struct rte_dev_reg_info *regs)
4362 {
4363         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4364         uint32_t *data = regs->data;
4365         int g_ind = 0;
4366         int count = 0;
4367         const struct reg_info *reg_group;
4368         const struct reg_info **reg_set = txgbe_regs_others;
4369
4370         if (data == NULL) {
4371                 regs->length = txgbe_get_reg_length(dev);
4372                 regs->width = sizeof(uint32_t);
4373                 return 0;
4374         }
4375
4376         /* Support only full register dump */
4377         if (regs->length == 0 ||
4378             regs->length == (uint32_t)txgbe_get_reg_length(dev)) {
4379                 regs->version = hw->mac.type << 24 |
4380                                 hw->revision_id << 16 |
4381                                 hw->device_id;
4382                 while ((reg_group = reg_set[g_ind++]))
4383                         count += txgbe_read_regs_group(dev, &data[count],
4384                                                       reg_group);
4385                 return 0;
4386         }
4387
4388         return -ENOTSUP;
4389 }
4390
4391 static int
4392 txgbe_get_eeprom_length(struct rte_eth_dev *dev)
4393 {
4394         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4395
4396         /* Return unit is byte count */
4397         return hw->rom.word_size * 2;
4398 }
4399
4400 static int
4401 txgbe_get_eeprom(struct rte_eth_dev *dev,
4402                 struct rte_dev_eeprom_info *in_eeprom)
4403 {
4404         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4405         struct txgbe_rom_info *eeprom = &hw->rom;
4406         uint16_t *data = in_eeprom->data;
4407         int first, length;
4408
4409         first = in_eeprom->offset >> 1;
4410         length = in_eeprom->length >> 1;
4411         if (first > hw->rom.word_size ||
4412             ((first + length) > hw->rom.word_size))
4413                 return -EINVAL;
4414
4415         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
4416
4417         return eeprom->readw_buffer(hw, first, length, data);
4418 }
4419
4420 static int
4421 txgbe_set_eeprom(struct rte_eth_dev *dev,
4422                 struct rte_dev_eeprom_info *in_eeprom)
4423 {
4424         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4425         struct txgbe_rom_info *eeprom = &hw->rom;
4426         uint16_t *data = in_eeprom->data;
4427         int first, length;
4428
4429         first = in_eeprom->offset >> 1;
4430         length = in_eeprom->length >> 1;
4431         if (first > hw->rom.word_size ||
4432             ((first + length) > hw->rom.word_size))
4433                 return -EINVAL;
4434
4435         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
4436
4437         return eeprom->writew_buffer(hw,  first, length, data);
4438 }
4439
4440 static int
4441 txgbe_get_module_info(struct rte_eth_dev *dev,
4442                       struct rte_eth_dev_module_info *modinfo)
4443 {
4444         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4445         uint32_t status;
4446         uint8_t sff8472_rev, addr_mode;
4447         bool page_swap = false;
4448
4449         /* Check whether we support SFF-8472 or not */
4450         status = hw->phy.read_i2c_eeprom(hw,
4451                                              TXGBE_SFF_SFF_8472_COMP,
4452                                              &sff8472_rev);
4453         if (status != 0)
4454                 return -EIO;
4455
4456         /* addressing mode is not supported */
4457         status = hw->phy.read_i2c_eeprom(hw,
4458                                              TXGBE_SFF_SFF_8472_SWAP,
4459                                              &addr_mode);
4460         if (status != 0)
4461                 return -EIO;
4462
4463         if (addr_mode & TXGBE_SFF_ADDRESSING_MODE) {
4464                 PMD_DRV_LOG(ERR,
4465                             "Address change required to access page 0xA2, "
4466                             "but not supported. Please report the module "
4467                             "type to the driver maintainers.");
4468                 page_swap = true;
4469         }
4470
4471         if (sff8472_rev == TXGBE_SFF_SFF_8472_UNSUP || page_swap) {
4472                 /* We have a SFP, but it does not support SFF-8472 */
4473                 modinfo->type = RTE_ETH_MODULE_SFF_8079;
4474                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
4475         } else {
4476                 /* We have a SFP which supports a revision of SFF-8472. */
4477                 modinfo->type = RTE_ETH_MODULE_SFF_8472;
4478                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
4479         }
4480
4481         return 0;
4482 }
4483
4484 static int
4485 txgbe_get_module_eeprom(struct rte_eth_dev *dev,
4486                         struct rte_dev_eeprom_info *info)
4487 {
4488         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4489         uint32_t status = TXGBE_ERR_PHY_ADDR_INVALID;
4490         uint8_t databyte = 0xFF;
4491         uint8_t *data = info->data;
4492         uint32_t i = 0;
4493
4494         if (info->length == 0)
4495                 return -EINVAL;
4496
4497         for (i = info->offset; i < info->offset + info->length; i++) {
4498                 if (i < RTE_ETH_MODULE_SFF_8079_LEN)
4499                         status = hw->phy.read_i2c_eeprom(hw, i, &databyte);
4500                 else
4501                         status = hw->phy.read_i2c_sff8472(hw, i, &databyte);
4502
4503                 if (status != 0)
4504                         return -EIO;
4505
4506                 data[i - info->offset] = databyte;
4507         }
4508
4509         return 0;
4510 }
4511
4512 bool
4513 txgbe_rss_update_sp(enum txgbe_mac_type mac_type)
4514 {
4515         switch (mac_type) {
4516         case txgbe_mac_raptor:
4517                 return 1;
4518         default:
4519                 return 0;
4520         }
4521 }
4522
4523 static int
4524 txgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
4525                         struct rte_eth_dcb_info *dcb_info)
4526 {
4527         struct txgbe_dcb_config *dcb_config = TXGBE_DEV_DCB_CONFIG(dev);
4528         struct txgbe_dcb_tc_config *tc;
4529         struct rte_eth_dcb_tc_queue_mapping *tc_queue;
4530         uint8_t nb_tcs;
4531         uint8_t i, j;
4532
4533         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
4534                 dcb_info->nb_tcs = dcb_config->num_tcs.pg_tcs;
4535         else
4536                 dcb_info->nb_tcs = 1;
4537
4538         tc_queue = &dcb_info->tc_queue;
4539         nb_tcs = dcb_info->nb_tcs;
4540
4541         if (dcb_config->vt_mode) { /* vt is enabled */
4542                 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
4543                                 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
4544                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
4545                         dcb_info->prio_tc[i] = vmdq_rx_conf->dcb_tc[i];
4546                 if (RTE_ETH_DEV_SRIOV(dev).active > 0) {
4547                         for (j = 0; j < nb_tcs; j++) {
4548                                 tc_queue->tc_rxq[0][j].base = j;
4549                                 tc_queue->tc_rxq[0][j].nb_queue = 1;
4550                                 tc_queue->tc_txq[0][j].base = j;
4551                                 tc_queue->tc_txq[0][j].nb_queue = 1;
4552                         }
4553                 } else {
4554                         for (i = 0; i < vmdq_rx_conf->nb_queue_pools; i++) {
4555                                 for (j = 0; j < nb_tcs; j++) {
4556                                         tc_queue->tc_rxq[i][j].base =
4557                                                 i * nb_tcs + j;
4558                                         tc_queue->tc_rxq[i][j].nb_queue = 1;
4559                                         tc_queue->tc_txq[i][j].base =
4560                                                 i * nb_tcs + j;
4561                                         tc_queue->tc_txq[i][j].nb_queue = 1;
4562                                 }
4563                         }
4564                 }
4565         } else { /* vt is disabled */
4566                 struct rte_eth_dcb_rx_conf *rx_conf =
4567                                 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
4568                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
4569                         dcb_info->prio_tc[i] = rx_conf->dcb_tc[i];
4570                 if (dcb_info->nb_tcs == ETH_4_TCS) {
4571                         for (i = 0; i < dcb_info->nb_tcs; i++) {
4572                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 32;
4573                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
4574                         }
4575                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
4576                         dcb_info->tc_queue.tc_txq[0][1].base = 64;
4577                         dcb_info->tc_queue.tc_txq[0][2].base = 96;
4578                         dcb_info->tc_queue.tc_txq[0][3].base = 112;
4579                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 64;
4580                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
4581                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
4582                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
4583                 } else if (dcb_info->nb_tcs == ETH_8_TCS) {
4584                         for (i = 0; i < dcb_info->nb_tcs; i++) {
4585                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 16;
4586                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
4587                         }
4588                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
4589                         dcb_info->tc_queue.tc_txq[0][1].base = 32;
4590                         dcb_info->tc_queue.tc_txq[0][2].base = 64;
4591                         dcb_info->tc_queue.tc_txq[0][3].base = 80;
4592                         dcb_info->tc_queue.tc_txq[0][4].base = 96;
4593                         dcb_info->tc_queue.tc_txq[0][5].base = 104;
4594                         dcb_info->tc_queue.tc_txq[0][6].base = 112;
4595                         dcb_info->tc_queue.tc_txq[0][7].base = 120;
4596                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 32;
4597                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
4598                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
4599                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
4600                         dcb_info->tc_queue.tc_txq[0][4].nb_queue = 8;
4601                         dcb_info->tc_queue.tc_txq[0][5].nb_queue = 8;
4602                         dcb_info->tc_queue.tc_txq[0][6].nb_queue = 8;
4603                         dcb_info->tc_queue.tc_txq[0][7].nb_queue = 8;
4604                 }
4605         }
4606         for (i = 0; i < dcb_info->nb_tcs; i++) {
4607                 tc = &dcb_config->tc_config[i];
4608                 dcb_info->tc_bws[i] = tc->path[TXGBE_DCB_TX_CONFIG].bwg_percent;
4609         }
4610         return 0;
4611 }
4612
4613 /* Update e-tag ether type */
4614 static int
4615 txgbe_update_e_tag_eth_type(struct txgbe_hw *hw,
4616                             uint16_t ether_type)
4617 {
4618         uint32_t etag_etype;
4619
4620         etag_etype = rd32(hw, TXGBE_EXTAG);
4621         etag_etype &= ~TXGBE_EXTAG_ETAG_MASK;
4622         etag_etype |= ether_type;
4623         wr32(hw, TXGBE_EXTAG, etag_etype);
4624         txgbe_flush(hw);
4625
4626         return 0;
4627 }
4628
4629 /* Enable e-tag tunnel */
4630 static int
4631 txgbe_e_tag_enable(struct txgbe_hw *hw)
4632 {
4633         uint32_t etag_etype;
4634
4635         etag_etype = rd32(hw, TXGBE_PORTCTL);
4636         etag_etype |= TXGBE_PORTCTL_ETAG;
4637         wr32(hw, TXGBE_PORTCTL, etag_etype);
4638         txgbe_flush(hw);
4639
4640         return 0;
4641 }
4642
4643 static int
4644 txgbe_e_tag_filter_del(struct rte_eth_dev *dev,
4645                        struct txgbe_l2_tunnel_conf  *l2_tunnel)
4646 {
4647         int ret = 0;
4648         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4649         uint32_t i, rar_entries;
4650         uint32_t rar_low, rar_high;
4651
4652         rar_entries = hw->mac.num_rar_entries;
4653
4654         for (i = 1; i < rar_entries; i++) {
4655                 wr32(hw, TXGBE_ETHADDRIDX, i);
4656                 rar_high = rd32(hw, TXGBE_ETHADDRH);
4657                 rar_low  = rd32(hw, TXGBE_ETHADDRL);
4658                 if ((rar_high & TXGBE_ETHADDRH_VLD) &&
4659                     (rar_high & TXGBE_ETHADDRH_ETAG) &&
4660                     (TXGBE_ETHADDRL_ETAG(rar_low) ==
4661                      l2_tunnel->tunnel_id)) {
4662                         wr32(hw, TXGBE_ETHADDRL, 0);
4663                         wr32(hw, TXGBE_ETHADDRH, 0);
4664
4665                         txgbe_clear_vmdq(hw, i, BIT_MASK32);
4666
4667                         return ret;
4668                 }
4669         }
4670
4671         return ret;
4672 }
4673
4674 static int
4675 txgbe_e_tag_filter_add(struct rte_eth_dev *dev,
4676                        struct txgbe_l2_tunnel_conf *l2_tunnel)
4677 {
4678         int ret = 0;
4679         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4680         uint32_t i, rar_entries;
4681         uint32_t rar_low, rar_high;
4682
4683         /* One entry for one tunnel. Try to remove potential existing entry. */
4684         txgbe_e_tag_filter_del(dev, l2_tunnel);
4685
4686         rar_entries = hw->mac.num_rar_entries;
4687
4688         for (i = 1; i < rar_entries; i++) {
4689                 wr32(hw, TXGBE_ETHADDRIDX, i);
4690                 rar_high = rd32(hw, TXGBE_ETHADDRH);
4691                 if (rar_high & TXGBE_ETHADDRH_VLD) {
4692                         continue;
4693                 } else {
4694                         txgbe_set_vmdq(hw, i, l2_tunnel->pool);
4695                         rar_high = TXGBE_ETHADDRH_VLD | TXGBE_ETHADDRH_ETAG;
4696                         rar_low = l2_tunnel->tunnel_id;
4697
4698                         wr32(hw, TXGBE_ETHADDRL, rar_low);
4699                         wr32(hw, TXGBE_ETHADDRH, rar_high);
4700
4701                         return ret;
4702                 }
4703         }
4704
4705         PMD_INIT_LOG(NOTICE, "The table of E-tag forwarding rule is full."
4706                      " Please remove a rule before adding a new one.");
4707         return -EINVAL;
4708 }
4709
4710 static inline struct txgbe_l2_tn_filter *
4711 txgbe_l2_tn_filter_lookup(struct txgbe_l2_tn_info *l2_tn_info,
4712                           struct txgbe_l2_tn_key *key)
4713 {
4714         int ret;
4715
4716         ret = rte_hash_lookup(l2_tn_info->hash_handle, (const void *)key);
4717         if (ret < 0)
4718                 return NULL;
4719
4720         return l2_tn_info->hash_map[ret];
4721 }
4722
4723 static inline int
4724 txgbe_insert_l2_tn_filter(struct txgbe_l2_tn_info *l2_tn_info,
4725                           struct txgbe_l2_tn_filter *l2_tn_filter)
4726 {
4727         int ret;
4728
4729         ret = rte_hash_add_key(l2_tn_info->hash_handle,
4730                                &l2_tn_filter->key);
4731
4732         if (ret < 0) {
4733                 PMD_DRV_LOG(ERR,
4734                             "Failed to insert L2 tunnel filter"
4735                             " to hash table %d!",
4736                             ret);
4737                 return ret;
4738         }
4739
4740         l2_tn_info->hash_map[ret] = l2_tn_filter;
4741
4742         TAILQ_INSERT_TAIL(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
4743
4744         return 0;
4745 }
4746
4747 static inline int
4748 txgbe_remove_l2_tn_filter(struct txgbe_l2_tn_info *l2_tn_info,
4749                           struct txgbe_l2_tn_key *key)
4750 {
4751         int ret;
4752         struct txgbe_l2_tn_filter *l2_tn_filter;
4753
4754         ret = rte_hash_del_key(l2_tn_info->hash_handle, key);
4755
4756         if (ret < 0) {
4757                 PMD_DRV_LOG(ERR,
4758                             "No such L2 tunnel filter to delete %d!",
4759                             ret);
4760                 return ret;
4761         }
4762
4763         l2_tn_filter = l2_tn_info->hash_map[ret];
4764         l2_tn_info->hash_map[ret] = NULL;
4765
4766         TAILQ_REMOVE(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
4767         rte_free(l2_tn_filter);
4768
4769         return 0;
4770 }
4771
4772 /* Add l2 tunnel filter */
4773 int
4774 txgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev,
4775                                struct txgbe_l2_tunnel_conf *l2_tunnel,
4776                                bool restore)
4777 {
4778         int ret;
4779         struct txgbe_l2_tn_info *l2_tn_info = TXGBE_DEV_L2_TN(dev);
4780         struct txgbe_l2_tn_key key;
4781         struct txgbe_l2_tn_filter *node;
4782
4783         if (!restore) {
4784                 key.l2_tn_type = l2_tunnel->l2_tunnel_type;
4785                 key.tn_id = l2_tunnel->tunnel_id;
4786
4787                 node = txgbe_l2_tn_filter_lookup(l2_tn_info, &key);
4788
4789                 if (node) {
4790                         PMD_DRV_LOG(ERR,
4791                                     "The L2 tunnel filter already exists!");
4792                         return -EINVAL;
4793                 }
4794
4795                 node = rte_zmalloc("txgbe_l2_tn",
4796                                    sizeof(struct txgbe_l2_tn_filter),
4797                                    0);
4798                 if (!node)
4799                         return -ENOMEM;
4800
4801                 rte_memcpy(&node->key,
4802                                  &key,
4803                                  sizeof(struct txgbe_l2_tn_key));
4804                 node->pool = l2_tunnel->pool;
4805                 ret = txgbe_insert_l2_tn_filter(l2_tn_info, node);
4806                 if (ret < 0) {
4807                         rte_free(node);
4808                         return ret;
4809                 }
4810         }
4811
4812         switch (l2_tunnel->l2_tunnel_type) {
4813         case RTE_L2_TUNNEL_TYPE_E_TAG:
4814                 ret = txgbe_e_tag_filter_add(dev, l2_tunnel);
4815                 break;
4816         default:
4817                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
4818                 ret = -EINVAL;
4819                 break;
4820         }
4821
4822         if (!restore && ret < 0)
4823                 (void)txgbe_remove_l2_tn_filter(l2_tn_info, &key);
4824
4825         return ret;
4826 }
4827
4828 /* Delete l2 tunnel filter */
4829 int
4830 txgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev,
4831                                struct txgbe_l2_tunnel_conf *l2_tunnel)
4832 {
4833         int ret;
4834         struct txgbe_l2_tn_info *l2_tn_info = TXGBE_DEV_L2_TN(dev);
4835         struct txgbe_l2_tn_key key;
4836
4837         key.l2_tn_type = l2_tunnel->l2_tunnel_type;
4838         key.tn_id = l2_tunnel->tunnel_id;
4839         ret = txgbe_remove_l2_tn_filter(l2_tn_info, &key);
4840         if (ret < 0)
4841                 return ret;
4842
4843         switch (l2_tunnel->l2_tunnel_type) {
4844         case RTE_L2_TUNNEL_TYPE_E_TAG:
4845                 ret = txgbe_e_tag_filter_del(dev, l2_tunnel);
4846                 break;
4847         default:
4848                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
4849                 ret = -EINVAL;
4850                 break;
4851         }
4852
4853         return ret;
4854 }
4855
4856 static int
4857 txgbe_e_tag_forwarding_en_dis(struct rte_eth_dev *dev, bool en)
4858 {
4859         int ret = 0;
4860         uint32_t ctrl;
4861         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4862
4863         ctrl = rd32(hw, TXGBE_POOLCTL);
4864         ctrl &= ~TXGBE_POOLCTL_MODE_MASK;
4865         if (en)
4866                 ctrl |= TXGBE_PSRPOOL_MODE_ETAG;
4867         wr32(hw, TXGBE_POOLCTL, ctrl);
4868
4869         return ret;
4870 }
4871
4872 /* Add UDP tunneling port */
4873 static int
4874 txgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
4875                               struct rte_eth_udp_tunnel *udp_tunnel)
4876 {
4877         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4878         int ret = 0;
4879
4880         if (udp_tunnel == NULL)
4881                 return -EINVAL;
4882
4883         switch (udp_tunnel->prot_type) {
4884         case RTE_TUNNEL_TYPE_VXLAN:
4885                 if (udp_tunnel->udp_port == 0) {
4886                         PMD_DRV_LOG(ERR, "Add VxLAN port 0 is not allowed.");
4887                         ret = -EINVAL;
4888                         break;
4889                 }
4890                 wr32(hw, TXGBE_VXLANPORT, udp_tunnel->udp_port);
4891                 wr32(hw, TXGBE_VXLANPORTGPE, udp_tunnel->udp_port);
4892                 break;
4893         case RTE_TUNNEL_TYPE_GENEVE:
4894                 if (udp_tunnel->udp_port == 0) {
4895                         PMD_DRV_LOG(ERR, "Add Geneve port 0 is not allowed.");
4896                         ret = -EINVAL;
4897                         break;
4898                 }
4899                 wr32(hw, TXGBE_GENEVEPORT, udp_tunnel->udp_port);
4900                 break;
4901         case RTE_TUNNEL_TYPE_TEREDO:
4902                 if (udp_tunnel->udp_port == 0) {
4903                         PMD_DRV_LOG(ERR, "Add Teredo port 0 is not allowed.");
4904                         ret = -EINVAL;
4905                         break;
4906                 }
4907                 wr32(hw, TXGBE_TEREDOPORT, udp_tunnel->udp_port);
4908                 break;
4909         default:
4910                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
4911                 ret = -EINVAL;
4912                 break;
4913         }
4914
4915         txgbe_flush(hw);
4916
4917         return ret;
4918 }
4919
4920 /* Remove UDP tunneling port */
4921 static int
4922 txgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
4923                               struct rte_eth_udp_tunnel *udp_tunnel)
4924 {
4925         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4926         int ret = 0;
4927         uint16_t cur_port;
4928
4929         if (udp_tunnel == NULL)
4930                 return -EINVAL;
4931
4932         switch (udp_tunnel->prot_type) {
4933         case RTE_TUNNEL_TYPE_VXLAN:
4934                 cur_port = (uint16_t)rd32(hw, TXGBE_VXLANPORT);
4935                 if (cur_port != udp_tunnel->udp_port) {
4936                         PMD_DRV_LOG(ERR, "Port %u does not exist.",
4937                                         udp_tunnel->udp_port);
4938                         ret = -EINVAL;
4939                         break;
4940                 }
4941                 wr32(hw, TXGBE_VXLANPORT, 0);
4942                 wr32(hw, TXGBE_VXLANPORTGPE, 0);
4943                 break;
4944         case RTE_TUNNEL_TYPE_GENEVE:
4945                 cur_port = (uint16_t)rd32(hw, TXGBE_GENEVEPORT);
4946                 if (cur_port != udp_tunnel->udp_port) {
4947                         PMD_DRV_LOG(ERR, "Port %u does not exist.",
4948                                         udp_tunnel->udp_port);
4949                         ret = -EINVAL;
4950                         break;
4951                 }
4952                 wr32(hw, TXGBE_GENEVEPORT, 0);
4953                 break;
4954         case RTE_TUNNEL_TYPE_TEREDO:
4955                 cur_port = (uint16_t)rd32(hw, TXGBE_TEREDOPORT);
4956                 if (cur_port != udp_tunnel->udp_port) {
4957                         PMD_DRV_LOG(ERR, "Port %u does not exist.",
4958                                         udp_tunnel->udp_port);
4959                         ret = -EINVAL;
4960                         break;
4961                 }
4962                 wr32(hw, TXGBE_TEREDOPORT, 0);
4963                 break;
4964         default:
4965                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
4966                 ret = -EINVAL;
4967                 break;
4968         }
4969
4970         txgbe_flush(hw);
4971
4972         return ret;
4973 }
4974
4975 /* restore n-tuple filter */
4976 static inline void
4977 txgbe_ntuple_filter_restore(struct rte_eth_dev *dev)
4978 {
4979         struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(dev);
4980         struct txgbe_5tuple_filter *node;
4981
4982         TAILQ_FOREACH(node, &filter_info->fivetuple_list, entries) {
4983                 txgbe_inject_5tuple_filter(dev, node);
4984         }
4985 }
4986
4987 /* restore ethernet type filter */
4988 static inline void
4989 txgbe_ethertype_filter_restore(struct rte_eth_dev *dev)
4990 {
4991         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4992         struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(dev);
4993         int i;
4994
4995         for (i = 0; i < TXGBE_ETF_ID_MAX; i++) {
4996                 if (filter_info->ethertype_mask & (1 << i)) {
4997                         wr32(hw, TXGBE_ETFLT(i),
4998                                         filter_info->ethertype_filters[i].etqf);
4999                         wr32(hw, TXGBE_ETCLS(i),
5000                                         filter_info->ethertype_filters[i].etqs);
5001                         txgbe_flush(hw);
5002                 }
5003         }
5004 }
5005
5006 /* restore SYN filter */
5007 static inline void
5008 txgbe_syn_filter_restore(struct rte_eth_dev *dev)
5009 {
5010         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
5011         struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(dev);
5012         uint32_t synqf;
5013
5014         synqf = filter_info->syn_info;
5015
5016         if (synqf & TXGBE_SYNCLS_ENA) {
5017                 wr32(hw, TXGBE_SYNCLS, synqf);
5018                 txgbe_flush(hw);
5019         }
5020 }
5021
5022 /* restore L2 tunnel filter */
5023 static inline void
5024 txgbe_l2_tn_filter_restore(struct rte_eth_dev *dev)
5025 {
5026         struct txgbe_l2_tn_info *l2_tn_info = TXGBE_DEV_L2_TN(dev);
5027         struct txgbe_l2_tn_filter *node;
5028         struct txgbe_l2_tunnel_conf l2_tn_conf;
5029
5030         TAILQ_FOREACH(node, &l2_tn_info->l2_tn_list, entries) {
5031                 l2_tn_conf.l2_tunnel_type = node->key.l2_tn_type;
5032                 l2_tn_conf.tunnel_id      = node->key.tn_id;
5033                 l2_tn_conf.pool           = node->pool;
5034                 (void)txgbe_dev_l2_tunnel_filter_add(dev, &l2_tn_conf, TRUE);
5035         }
5036 }
5037
5038 /* restore rss filter */
5039 static inline void
5040 txgbe_rss_filter_restore(struct rte_eth_dev *dev)
5041 {
5042         struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(dev);
5043
5044         if (filter_info->rss_info.conf.queue_num)
5045                 txgbe_config_rss_filter(dev,
5046                         &filter_info->rss_info, TRUE);
5047 }
5048
5049 static int
5050 txgbe_filter_restore(struct rte_eth_dev *dev)
5051 {
5052         txgbe_ntuple_filter_restore(dev);
5053         txgbe_ethertype_filter_restore(dev);
5054         txgbe_syn_filter_restore(dev);
5055         txgbe_fdir_filter_restore(dev);
5056         txgbe_l2_tn_filter_restore(dev);
5057         txgbe_rss_filter_restore(dev);
5058
5059         return 0;
5060 }
5061
5062 static void
5063 txgbe_l2_tunnel_conf(struct rte_eth_dev *dev)
5064 {
5065         struct txgbe_l2_tn_info *l2_tn_info = TXGBE_DEV_L2_TN(dev);
5066         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
5067
5068         if (l2_tn_info->e_tag_en)
5069                 (void)txgbe_e_tag_enable(hw);
5070
5071         if (l2_tn_info->e_tag_fwd_en)
5072                 (void)txgbe_e_tag_forwarding_en_dis(dev, 1);
5073
5074         (void)txgbe_update_e_tag_eth_type(hw, l2_tn_info->e_tag_ether_type);
5075 }
5076
5077 /* remove all the n-tuple filters */
5078 void
5079 txgbe_clear_all_ntuple_filter(struct rte_eth_dev *dev)
5080 {
5081         struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(dev);
5082         struct txgbe_5tuple_filter *p_5tuple;
5083
5084         while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list)))
5085                 txgbe_remove_5tuple_filter(dev, p_5tuple);
5086 }
5087
5088 /* remove all the ether type filters */
5089 void
5090 txgbe_clear_all_ethertype_filter(struct rte_eth_dev *dev)
5091 {
5092         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
5093         struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(dev);
5094         int i;
5095
5096         for (i = 0; i < TXGBE_ETF_ID_MAX; i++) {
5097                 if (filter_info->ethertype_mask & (1 << i) &&
5098                     !filter_info->ethertype_filters[i].conf) {
5099                         (void)txgbe_ethertype_filter_remove(filter_info,
5100                                                             (uint8_t)i);
5101                         wr32(hw, TXGBE_ETFLT(i), 0);
5102                         wr32(hw, TXGBE_ETCLS(i), 0);
5103                         txgbe_flush(hw);
5104                 }
5105         }
5106 }
5107
5108 /* remove the SYN filter */
5109 void
5110 txgbe_clear_syn_filter(struct rte_eth_dev *dev)
5111 {
5112         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
5113         struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(dev);
5114
5115         if (filter_info->syn_info & TXGBE_SYNCLS_ENA) {
5116                 filter_info->syn_info = 0;
5117
5118                 wr32(hw, TXGBE_SYNCLS, 0);
5119                 txgbe_flush(hw);
5120         }
5121 }
5122
5123 /* remove all the L2 tunnel filters */
5124 int
5125 txgbe_clear_all_l2_tn_filter(struct rte_eth_dev *dev)
5126 {
5127         struct txgbe_l2_tn_info *l2_tn_info = TXGBE_DEV_L2_TN(dev);
5128         struct txgbe_l2_tn_filter *l2_tn_filter;
5129         struct txgbe_l2_tunnel_conf l2_tn_conf;
5130         int ret = 0;
5131
5132         while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
5133                 l2_tn_conf.l2_tunnel_type = l2_tn_filter->key.l2_tn_type;
5134                 l2_tn_conf.tunnel_id      = l2_tn_filter->key.tn_id;
5135                 l2_tn_conf.pool           = l2_tn_filter->pool;
5136                 ret = txgbe_dev_l2_tunnel_filter_del(dev, &l2_tn_conf);
5137                 if (ret < 0)
5138                         return ret;
5139         }
5140
5141         return 0;
5142 }
5143
5144 static const struct eth_dev_ops txgbe_eth_dev_ops = {
5145         .dev_configure              = txgbe_dev_configure,
5146         .dev_infos_get              = txgbe_dev_info_get,
5147         .dev_start                  = txgbe_dev_start,
5148         .dev_stop                   = txgbe_dev_stop,
5149         .dev_set_link_up            = txgbe_dev_set_link_up,
5150         .dev_set_link_down          = txgbe_dev_set_link_down,
5151         .dev_close                  = txgbe_dev_close,
5152         .dev_reset                  = txgbe_dev_reset,
5153         .promiscuous_enable         = txgbe_dev_promiscuous_enable,
5154         .promiscuous_disable        = txgbe_dev_promiscuous_disable,
5155         .allmulticast_enable        = txgbe_dev_allmulticast_enable,
5156         .allmulticast_disable       = txgbe_dev_allmulticast_disable,
5157         .link_update                = txgbe_dev_link_update,
5158         .stats_get                  = txgbe_dev_stats_get,
5159         .xstats_get                 = txgbe_dev_xstats_get,
5160         .xstats_get_by_id           = txgbe_dev_xstats_get_by_id,
5161         .stats_reset                = txgbe_dev_stats_reset,
5162         .xstats_reset               = txgbe_dev_xstats_reset,
5163         .xstats_get_names           = txgbe_dev_xstats_get_names,
5164         .xstats_get_names_by_id     = txgbe_dev_xstats_get_names_by_id,
5165         .queue_stats_mapping_set    = txgbe_dev_queue_stats_mapping_set,
5166         .fw_version_get             = txgbe_fw_version_get,
5167         .dev_supported_ptypes_get   = txgbe_dev_supported_ptypes_get,
5168         .mtu_set                    = txgbe_dev_mtu_set,
5169         .vlan_filter_set            = txgbe_vlan_filter_set,
5170         .vlan_tpid_set              = txgbe_vlan_tpid_set,
5171         .vlan_offload_set           = txgbe_vlan_offload_set,
5172         .vlan_strip_queue_set       = txgbe_vlan_strip_queue_set,
5173         .rx_queue_start             = txgbe_dev_rx_queue_start,
5174         .rx_queue_stop              = txgbe_dev_rx_queue_stop,
5175         .tx_queue_start             = txgbe_dev_tx_queue_start,
5176         .tx_queue_stop              = txgbe_dev_tx_queue_stop,
5177         .rx_queue_setup             = txgbe_dev_rx_queue_setup,
5178         .rx_queue_intr_enable       = txgbe_dev_rx_queue_intr_enable,
5179         .rx_queue_intr_disable      = txgbe_dev_rx_queue_intr_disable,
5180         .rx_queue_release           = txgbe_dev_rx_queue_release,
5181         .tx_queue_setup             = txgbe_dev_tx_queue_setup,
5182         .tx_queue_release           = txgbe_dev_tx_queue_release,
5183         .dev_led_on                 = txgbe_dev_led_on,
5184         .dev_led_off                = txgbe_dev_led_off,
5185         .flow_ctrl_get              = txgbe_flow_ctrl_get,
5186         .flow_ctrl_set              = txgbe_flow_ctrl_set,
5187         .priority_flow_ctrl_set     = txgbe_priority_flow_ctrl_set,
5188         .mac_addr_add               = txgbe_add_rar,
5189         .mac_addr_remove            = txgbe_remove_rar,
5190         .mac_addr_set               = txgbe_set_default_mac_addr,
5191         .uc_hash_table_set          = txgbe_uc_hash_table_set,
5192         .uc_all_hash_table_set      = txgbe_uc_all_hash_table_set,
5193         .set_queue_rate_limit       = txgbe_set_queue_rate_limit,
5194         .reta_update                = txgbe_dev_rss_reta_update,
5195         .reta_query                 = txgbe_dev_rss_reta_query,
5196         .rss_hash_update            = txgbe_dev_rss_hash_update,
5197         .rss_hash_conf_get          = txgbe_dev_rss_hash_conf_get,
5198         .filter_ctrl                = txgbe_dev_filter_ctrl,
5199         .set_mc_addr_list           = txgbe_dev_set_mc_addr_list,
5200         .rxq_info_get               = txgbe_rxq_info_get,
5201         .txq_info_get               = txgbe_txq_info_get,
5202         .timesync_enable            = txgbe_timesync_enable,
5203         .timesync_disable           = txgbe_timesync_disable,
5204         .timesync_read_rx_timestamp = txgbe_timesync_read_rx_timestamp,
5205         .timesync_read_tx_timestamp = txgbe_timesync_read_tx_timestamp,
5206         .get_reg                    = txgbe_get_regs,
5207         .get_eeprom_length          = txgbe_get_eeprom_length,
5208         .get_eeprom                 = txgbe_get_eeprom,
5209         .set_eeprom                 = txgbe_set_eeprom,
5210         .get_module_info            = txgbe_get_module_info,
5211         .get_module_eeprom          = txgbe_get_module_eeprom,
5212         .get_dcb_info               = txgbe_dev_get_dcb_info,
5213         .timesync_adjust_time       = txgbe_timesync_adjust_time,
5214         .timesync_read_time         = txgbe_timesync_read_time,
5215         .timesync_write_time        = txgbe_timesync_write_time,
5216         .udp_tunnel_port_add        = txgbe_dev_udp_tunnel_port_add,
5217         .udp_tunnel_port_del        = txgbe_dev_udp_tunnel_port_del,
5218         .tx_done_cleanup            = txgbe_dev_tx_done_cleanup,
5219 };
5220
5221 RTE_PMD_REGISTER_PCI(net_txgbe, rte_txgbe_pmd);
5222 RTE_PMD_REGISTER_PCI_TABLE(net_txgbe, pci_id_txgbe_map);
5223 RTE_PMD_REGISTER_KMOD_DEP(net_txgbe, "* igb_uio | uio_pci_generic | vfio-pci");
5224
5225 RTE_LOG_REGISTER(txgbe_logtype_init, pmd.net.txgbe.init, NOTICE);
5226 RTE_LOG_REGISTER(txgbe_logtype_driver, pmd.net.txgbe.driver, NOTICE);
5227
5228 #ifdef RTE_LIBRTE_TXGBE_DEBUG_RX
5229         RTE_LOG_REGISTER(txgbe_logtype_rx, pmd.net.txgbe.rx, DEBUG);
5230 #endif
5231 #ifdef RTE_LIBRTE_TXGBE_DEBUG_TX
5232         RTE_LOG_REGISTER(txgbe_logtype_tx, pmd.net.txgbe.tx, DEBUG);
5233 #endif
5234
5235 #ifdef RTE_LIBRTE_TXGBE_DEBUG_TX_FREE
5236         RTE_LOG_REGISTER(txgbe_logtype_tx_free, pmd.net.txgbe.tx_free, DEBUG);
5237 #endif