1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2015-2020
9 #include <rte_common.h>
10 #include <rte_ethdev_pci.h>
12 #include <rte_interrupts.h>
14 #include <rte_debug.h>
16 #include <rte_memory.h>
18 #include <rte_alarm.h>
20 #include "txgbe_logs.h"
21 #include "base/txgbe.h"
22 #include "txgbe_ethdev.h"
23 #include "txgbe_rxtx.h"
24 #include "txgbe_regs_group.h"
26 static const struct reg_info txgbe_regs_general[] = {
27 {TXGBE_RST, 1, 1, "TXGBE_RST"},
28 {TXGBE_STAT, 1, 1, "TXGBE_STAT"},
29 {TXGBE_PORTCTL, 1, 1, "TXGBE_PORTCTL"},
30 {TXGBE_SDP, 1, 1, "TXGBE_SDP"},
31 {TXGBE_SDPCTL, 1, 1, "TXGBE_SDPCTL"},
32 {TXGBE_LEDCTL, 1, 1, "TXGBE_LEDCTL"},
36 static const struct reg_info txgbe_regs_nvm[] = {
40 static const struct reg_info txgbe_regs_interrupt[] = {
44 static const struct reg_info txgbe_regs_fctl_others[] = {
48 static const struct reg_info txgbe_regs_rxdma[] = {
52 static const struct reg_info txgbe_regs_rx[] = {
56 static struct reg_info txgbe_regs_tx[] = {
60 static const struct reg_info txgbe_regs_wakeup[] = {
64 static const struct reg_info txgbe_regs_dcb[] = {
68 static const struct reg_info txgbe_regs_mac[] = {
72 static const struct reg_info txgbe_regs_diagnostic[] = {
77 static const struct reg_info *txgbe_regs_others[] = {
81 txgbe_regs_fctl_others,
88 txgbe_regs_diagnostic,
91 static int txgbe_dev_set_link_up(struct rte_eth_dev *dev);
92 static int txgbe_dev_set_link_down(struct rte_eth_dev *dev);
93 static int txgbe_dev_close(struct rte_eth_dev *dev);
94 static int txgbe_dev_link_update(struct rte_eth_dev *dev,
95 int wait_to_complete);
96 static int txgbe_dev_stats_reset(struct rte_eth_dev *dev);
97 static void txgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
98 static void txgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev,
101 static void txgbe_dev_link_status_print(struct rte_eth_dev *dev);
102 static int txgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on);
103 static int txgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev);
104 static int txgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
105 static int txgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
106 static int txgbe_dev_interrupt_action(struct rte_eth_dev *dev,
107 struct rte_intr_handle *handle);
108 static void txgbe_dev_interrupt_handler(void *param);
109 static void txgbe_dev_interrupt_delayed_handler(void *param);
110 static void txgbe_configure_msix(struct rte_eth_dev *dev);
112 #define TXGBE_SET_HWSTRIP(h, q) do {\
113 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
114 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
115 (h)->bitmap[idx] |= 1 << bit;\
118 #define TXGBE_CLEAR_HWSTRIP(h, q) do {\
119 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
120 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
121 (h)->bitmap[idx] &= ~(1 << bit);\
124 #define TXGBE_GET_HWSTRIP(h, q, r) do {\
125 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
126 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
127 (r) = (h)->bitmap[idx] >> bit & 1;\
131 * The set of PCI devices this driver supports
133 static const struct rte_pci_id pci_id_txgbe_map[] = {
134 { RTE_PCI_DEVICE(PCI_VENDOR_ID_WANGXUN, TXGBE_DEV_ID_RAPTOR_SFP) },
135 { RTE_PCI_DEVICE(PCI_VENDOR_ID_WANGXUN, TXGBE_DEV_ID_WX1820_SFP) },
136 { .vendor_id = 0, /* sentinel */ },
139 static const struct rte_eth_desc_lim rx_desc_lim = {
140 .nb_max = TXGBE_RING_DESC_MAX,
141 .nb_min = TXGBE_RING_DESC_MIN,
142 .nb_align = TXGBE_RXD_ALIGN,
145 static const struct rte_eth_desc_lim tx_desc_lim = {
146 .nb_max = TXGBE_RING_DESC_MAX,
147 .nb_min = TXGBE_RING_DESC_MIN,
148 .nb_align = TXGBE_TXD_ALIGN,
149 .nb_seg_max = TXGBE_TX_MAX_SEG,
150 .nb_mtu_seg_max = TXGBE_TX_MAX_SEG,
153 static const struct eth_dev_ops txgbe_eth_dev_ops;
155 #define HW_XSTAT(m) {#m, offsetof(struct txgbe_hw_stats, m)}
156 #define HW_XSTAT_NAME(m, n) {n, offsetof(struct txgbe_hw_stats, m)}
157 static const struct rte_txgbe_xstats_name_off rte_txgbe_stats_strings[] = {
159 HW_XSTAT(mng_bmc2host_packets),
160 HW_XSTAT(mng_host2bmc_packets),
162 HW_XSTAT(rx_packets),
163 HW_XSTAT(tx_packets),
166 HW_XSTAT(rx_total_bytes),
167 HW_XSTAT(rx_total_packets),
168 HW_XSTAT(tx_total_packets),
169 HW_XSTAT(rx_total_missed_packets),
170 HW_XSTAT(rx_broadcast_packets),
171 HW_XSTAT(rx_multicast_packets),
172 HW_XSTAT(rx_management_packets),
173 HW_XSTAT(tx_management_packets),
174 HW_XSTAT(rx_management_dropped),
177 HW_XSTAT(rx_crc_errors),
178 HW_XSTAT(rx_illegal_byte_errors),
179 HW_XSTAT(rx_error_bytes),
180 HW_XSTAT(rx_mac_short_packet_dropped),
181 HW_XSTAT(rx_length_errors),
182 HW_XSTAT(rx_undersize_errors),
183 HW_XSTAT(rx_fragment_errors),
184 HW_XSTAT(rx_oversize_errors),
185 HW_XSTAT(rx_jabber_errors),
186 HW_XSTAT(rx_l3_l4_xsum_error),
187 HW_XSTAT(mac_local_errors),
188 HW_XSTAT(mac_remote_errors),
191 HW_XSTAT(flow_director_added_filters),
192 HW_XSTAT(flow_director_removed_filters),
193 HW_XSTAT(flow_director_filter_add_errors),
194 HW_XSTAT(flow_director_filter_remove_errors),
195 HW_XSTAT(flow_director_matched_filters),
196 HW_XSTAT(flow_director_missed_filters),
199 HW_XSTAT(rx_fcoe_crc_errors),
200 HW_XSTAT(rx_fcoe_mbuf_allocation_errors),
201 HW_XSTAT(rx_fcoe_dropped),
202 HW_XSTAT(rx_fcoe_packets),
203 HW_XSTAT(tx_fcoe_packets),
204 HW_XSTAT(rx_fcoe_bytes),
205 HW_XSTAT(tx_fcoe_bytes),
206 HW_XSTAT(rx_fcoe_no_ddp),
207 HW_XSTAT(rx_fcoe_no_ddp_ext_buff),
210 HW_XSTAT(tx_macsec_pkts_untagged),
211 HW_XSTAT(tx_macsec_pkts_encrypted),
212 HW_XSTAT(tx_macsec_pkts_protected),
213 HW_XSTAT(tx_macsec_octets_encrypted),
214 HW_XSTAT(tx_macsec_octets_protected),
215 HW_XSTAT(rx_macsec_pkts_untagged),
216 HW_XSTAT(rx_macsec_pkts_badtag),
217 HW_XSTAT(rx_macsec_pkts_nosci),
218 HW_XSTAT(rx_macsec_pkts_unknownsci),
219 HW_XSTAT(rx_macsec_octets_decrypted),
220 HW_XSTAT(rx_macsec_octets_validated),
221 HW_XSTAT(rx_macsec_sc_pkts_unchecked),
222 HW_XSTAT(rx_macsec_sc_pkts_delayed),
223 HW_XSTAT(rx_macsec_sc_pkts_late),
224 HW_XSTAT(rx_macsec_sa_pkts_ok),
225 HW_XSTAT(rx_macsec_sa_pkts_invalid),
226 HW_XSTAT(rx_macsec_sa_pkts_notvalid),
227 HW_XSTAT(rx_macsec_sa_pkts_unusedsa),
228 HW_XSTAT(rx_macsec_sa_pkts_notusingsa),
231 HW_XSTAT(rx_size_64_packets),
232 HW_XSTAT(rx_size_65_to_127_packets),
233 HW_XSTAT(rx_size_128_to_255_packets),
234 HW_XSTAT(rx_size_256_to_511_packets),
235 HW_XSTAT(rx_size_512_to_1023_packets),
236 HW_XSTAT(rx_size_1024_to_max_packets),
237 HW_XSTAT(tx_size_64_packets),
238 HW_XSTAT(tx_size_65_to_127_packets),
239 HW_XSTAT(tx_size_128_to_255_packets),
240 HW_XSTAT(tx_size_256_to_511_packets),
241 HW_XSTAT(tx_size_512_to_1023_packets),
242 HW_XSTAT(tx_size_1024_to_max_packets),
245 HW_XSTAT(tx_xon_packets),
246 HW_XSTAT(rx_xon_packets),
247 HW_XSTAT(tx_xoff_packets),
248 HW_XSTAT(rx_xoff_packets),
250 HW_XSTAT_NAME(tx_xon_packets, "tx_flow_control_xon_packets"),
251 HW_XSTAT_NAME(rx_xon_packets, "rx_flow_control_xon_packets"),
252 HW_XSTAT_NAME(tx_xoff_packets, "tx_flow_control_xoff_packets"),
253 HW_XSTAT_NAME(rx_xoff_packets, "rx_flow_control_xoff_packets"),
256 #define TXGBE_NB_HW_STATS (sizeof(rte_txgbe_stats_strings) / \
257 sizeof(rte_txgbe_stats_strings[0]))
259 /* Per-priority statistics */
260 #define UP_XSTAT(m) {#m, offsetof(struct txgbe_hw_stats, up[0].m)}
261 static const struct rte_txgbe_xstats_name_off rte_txgbe_up_strings[] = {
262 UP_XSTAT(rx_up_packets),
263 UP_XSTAT(tx_up_packets),
264 UP_XSTAT(rx_up_bytes),
265 UP_XSTAT(tx_up_bytes),
266 UP_XSTAT(rx_up_drop_packets),
268 UP_XSTAT(tx_up_xon_packets),
269 UP_XSTAT(rx_up_xon_packets),
270 UP_XSTAT(tx_up_xoff_packets),
271 UP_XSTAT(rx_up_xoff_packets),
272 UP_XSTAT(rx_up_dropped),
273 UP_XSTAT(rx_up_mbuf_alloc_errors),
274 UP_XSTAT(tx_up_xon2off_packets),
277 #define TXGBE_NB_UP_STATS (sizeof(rte_txgbe_up_strings) / \
278 sizeof(rte_txgbe_up_strings[0]))
280 /* Per-queue statistics */
281 #define QP_XSTAT(m) {#m, offsetof(struct txgbe_hw_stats, qp[0].m)}
282 static const struct rte_txgbe_xstats_name_off rte_txgbe_qp_strings[] = {
283 QP_XSTAT(rx_qp_packets),
284 QP_XSTAT(tx_qp_packets),
285 QP_XSTAT(rx_qp_bytes),
286 QP_XSTAT(tx_qp_bytes),
287 QP_XSTAT(rx_qp_mc_packets),
290 #define TXGBE_NB_QP_STATS (sizeof(rte_txgbe_qp_strings) / \
291 sizeof(rte_txgbe_qp_strings[0]))
294 txgbe_is_sfp(struct txgbe_hw *hw)
296 switch (hw->phy.type) {
297 case txgbe_phy_sfp_avago:
298 case txgbe_phy_sfp_ftl:
299 case txgbe_phy_sfp_intel:
300 case txgbe_phy_sfp_unknown:
301 case txgbe_phy_sfp_tyco_passive:
302 case txgbe_phy_sfp_unknown_passive:
309 static inline int32_t
310 txgbe_pf_reset_hw(struct txgbe_hw *hw)
315 status = hw->mac.reset_hw(hw);
317 ctrl_ext = rd32(hw, TXGBE_PORTCTL);
318 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
319 ctrl_ext |= TXGBE_PORTCTL_RSTDONE;
320 wr32(hw, TXGBE_PORTCTL, ctrl_ext);
323 if (status == TXGBE_ERR_SFP_NOT_PRESENT)
329 txgbe_enable_intr(struct rte_eth_dev *dev)
331 struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);
332 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
334 wr32(hw, TXGBE_IENMISC, intr->mask_misc);
335 wr32(hw, TXGBE_IMC(0), TXGBE_IMC_MASK);
336 wr32(hw, TXGBE_IMC(1), TXGBE_IMC_MASK);
341 txgbe_disable_intr(struct txgbe_hw *hw)
343 PMD_INIT_FUNC_TRACE();
345 wr32(hw, TXGBE_IENMISC, ~BIT_MASK32);
346 wr32(hw, TXGBE_IMS(0), TXGBE_IMC_MASK);
347 wr32(hw, TXGBE_IMS(1), TXGBE_IMC_MASK);
352 txgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
357 struct txgbe_hw *hw = TXGBE_DEV_HW(eth_dev);
358 struct txgbe_stat_mappings *stat_mappings =
359 TXGBE_DEV_STAT_MAPPINGS(eth_dev);
360 uint32_t qsmr_mask = 0;
361 uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
365 if (hw->mac.type != txgbe_mac_raptor)
368 if (stat_idx & !QMAP_FIELD_RESERVED_BITS_MASK)
371 PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d",
372 (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
375 n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
376 if (n >= TXGBE_NB_STAT_MAPPING) {
377 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
380 offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
382 /* Now clear any previous stat_idx set */
383 clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
385 stat_mappings->tqsm[n] &= ~clearing_mask;
387 stat_mappings->rqsm[n] &= ~clearing_mask;
389 q_map = (uint32_t)stat_idx;
390 q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
391 qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
393 stat_mappings->tqsm[n] |= qsmr_mask;
395 stat_mappings->rqsm[n] |= qsmr_mask;
397 PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d",
398 (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
400 PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
401 is_rx ? stat_mappings->rqsm[n] : stat_mappings->tqsm[n]);
406 txgbe_dcb_init(struct txgbe_hw *hw, struct txgbe_dcb_config *dcb_config)
410 struct txgbe_dcb_tc_config *tc;
412 UNREFERENCED_PARAMETER(hw);
414 dcb_config->num_tcs.pg_tcs = TXGBE_DCB_TC_MAX;
415 dcb_config->num_tcs.pfc_tcs = TXGBE_DCB_TC_MAX;
416 bwgp = (u8)(100 / TXGBE_DCB_TC_MAX);
417 for (i = 0; i < TXGBE_DCB_TC_MAX; i++) {
418 tc = &dcb_config->tc_config[i];
419 tc->path[TXGBE_DCB_TX_CONFIG].bwg_id = i;
420 tc->path[TXGBE_DCB_TX_CONFIG].bwg_percent = bwgp + (i & 1);
421 tc->path[TXGBE_DCB_RX_CONFIG].bwg_id = i;
422 tc->path[TXGBE_DCB_RX_CONFIG].bwg_percent = bwgp + (i & 1);
423 tc->pfc = txgbe_dcb_pfc_disabled;
426 /* Initialize default user to priority mapping, UPx->TC0 */
427 tc = &dcb_config->tc_config[0];
428 tc->path[TXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
429 tc->path[TXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
430 for (i = 0; i < TXGBE_DCB_BWG_MAX; i++) {
431 dcb_config->bw_percentage[i][TXGBE_DCB_TX_CONFIG] = 100;
432 dcb_config->bw_percentage[i][TXGBE_DCB_RX_CONFIG] = 100;
434 dcb_config->rx_pba_cfg = txgbe_dcb_pba_equal;
435 dcb_config->pfc_mode_enable = false;
436 dcb_config->vt_mode = true;
437 dcb_config->round_robin_enable = false;
438 /* support all DCB capabilities */
439 dcb_config->support.capabilities = 0xFF;
443 * Ensure that all locks are released before first NVM or PHY access
446 txgbe_swfw_lock_reset(struct txgbe_hw *hw)
451 * These ones are more tricky since they are common to all ports; but
452 * swfw_sync retries last long enough (1s) to be almost sure that if
453 * lock can not be taken it is due to an improper lock of the
456 mask = TXGBE_MNGSEM_SWPHY |
458 TXGBE_MNGSEM_SWFLASH;
459 if (hw->mac.acquire_swfw_sync(hw, mask) < 0)
460 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
462 hw->mac.release_swfw_sync(hw, mask);
466 eth_txgbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params __rte_unused)
468 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
469 struct txgbe_hw *hw = TXGBE_DEV_HW(eth_dev);
470 struct txgbe_vfta *shadow_vfta = TXGBE_DEV_VFTA(eth_dev);
471 struct txgbe_hwstrip *hwstrip = TXGBE_DEV_HWSTRIP(eth_dev);
472 struct txgbe_dcb_config *dcb_config = TXGBE_DEV_DCB_CONFIG(eth_dev);
473 struct txgbe_bw_conf *bw_conf = TXGBE_DEV_BW_CONF(eth_dev);
474 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
475 const struct rte_memzone *mz;
480 PMD_INIT_FUNC_TRACE();
482 eth_dev->dev_ops = &txgbe_eth_dev_ops;
483 eth_dev->rx_queue_count = txgbe_dev_rx_queue_count;
484 eth_dev->rx_descriptor_status = txgbe_dev_rx_descriptor_status;
485 eth_dev->tx_descriptor_status = txgbe_dev_tx_descriptor_status;
486 eth_dev->rx_pkt_burst = &txgbe_recv_pkts;
487 eth_dev->tx_pkt_burst = &txgbe_xmit_pkts;
488 eth_dev->tx_pkt_prepare = &txgbe_prep_pkts;
491 * For secondary processes, we don't initialise any further as primary
492 * has already done this work. Only check we don't need a different
493 * RX and TX function.
495 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
496 struct txgbe_tx_queue *txq;
497 /* TX queue function in primary, set by last queue initialized
498 * Tx queue may not initialized by primary process
500 if (eth_dev->data->tx_queues) {
501 uint16_t nb_tx_queues = eth_dev->data->nb_tx_queues;
502 txq = eth_dev->data->tx_queues[nb_tx_queues - 1];
503 txgbe_set_tx_function(eth_dev, txq);
505 /* Use default TX function if we get here */
506 PMD_INIT_LOG(NOTICE, "No TX queues configured yet. "
507 "Using default TX function.");
510 txgbe_set_rx_function(eth_dev);
515 rte_eth_copy_pci_info(eth_dev, pci_dev);
517 /* Vendor and Device ID need to be set before init of shared code */
518 hw->device_id = pci_dev->id.device_id;
519 hw->vendor_id = pci_dev->id.vendor_id;
520 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
521 hw->allow_unsupported_sfp = 1;
523 /* Reserve memory for interrupt status block */
524 mz = rte_eth_dma_zone_reserve(eth_dev, "txgbe_driver", -1,
525 16, TXGBE_ALIGN, SOCKET_ID_ANY);
529 hw->isb_dma = TMZ_PADDR(mz);
530 hw->isb_mem = TMZ_VADDR(mz);
532 /* Initialize the shared code (base driver) */
533 err = txgbe_init_shared_code(hw);
535 PMD_INIT_LOG(ERR, "Shared code init failed: %d", err);
539 /* Unlock any pending hardware semaphore */
540 txgbe_swfw_lock_reset(hw);
542 /* Initialize DCB configuration*/
543 memset(dcb_config, 0, sizeof(struct txgbe_dcb_config));
544 txgbe_dcb_init(hw, dcb_config);
546 /* Get Hardware Flow Control setting */
547 hw->fc.requested_mode = txgbe_fc_full;
548 hw->fc.current_mode = txgbe_fc_full;
549 hw->fc.pause_time = TXGBE_FC_PAUSE_TIME;
550 for (i = 0; i < TXGBE_DCB_TC_MAX; i++) {
551 hw->fc.low_water[i] = TXGBE_FC_XON_LOTH;
552 hw->fc.high_water[i] = TXGBE_FC_XOFF_HITH;
556 err = hw->rom.init_params(hw);
558 PMD_INIT_LOG(ERR, "The EEPROM init failed: %d", err);
562 /* Make sure we have a good EEPROM before we read from it */
563 err = hw->rom.validate_checksum(hw, &csum);
565 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", err);
569 err = hw->mac.init_hw(hw);
572 * Devices with copper phys will fail to initialise if txgbe_init_hw()
573 * is called too soon after the kernel driver unbinding/binding occurs.
574 * The failure occurs in txgbe_identify_phy() for all devices,
575 * but for non-copper devies, txgbe_identify_sfp_module() is
576 * also called. See txgbe_identify_phy(). The reason for the
577 * failure is not known, and only occuts when virtualisation features
578 * are disabled in the bios. A delay of 200ms was found to be enough by
579 * trial-and-error, and is doubled to be safe.
581 if (err && hw->phy.media_type == txgbe_media_type_copper) {
583 err = hw->mac.init_hw(hw);
586 if (err == TXGBE_ERR_SFP_NOT_PRESENT)
589 if (err == TXGBE_ERR_EEPROM_VERSION) {
590 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
591 "LOM. Please be aware there may be issues associated "
592 "with your hardware.");
593 PMD_INIT_LOG(ERR, "If you are experiencing problems "
594 "please contact your hardware representative "
595 "who provided you with this hardware.");
596 } else if (err == TXGBE_ERR_SFP_NOT_SUPPORTED) {
597 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
600 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", err);
604 /* Reset the hw statistics */
605 txgbe_dev_stats_reset(eth_dev);
607 /* disable interrupt */
608 txgbe_disable_intr(hw);
610 /* Allocate memory for storing MAC addresses */
611 eth_dev->data->mac_addrs = rte_zmalloc("txgbe", RTE_ETHER_ADDR_LEN *
612 hw->mac.num_rar_entries, 0);
613 if (eth_dev->data->mac_addrs == NULL) {
615 "Failed to allocate %u bytes needed to store "
617 RTE_ETHER_ADDR_LEN * hw->mac.num_rar_entries);
621 /* Copy the permanent MAC address */
622 rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.perm_addr,
623 ð_dev->data->mac_addrs[0]);
625 /* Allocate memory for storing hash filter MAC addresses */
626 eth_dev->data->hash_mac_addrs = rte_zmalloc("txgbe",
627 RTE_ETHER_ADDR_LEN * TXGBE_VMDQ_NUM_UC_MAC, 0);
628 if (eth_dev->data->hash_mac_addrs == NULL) {
630 "Failed to allocate %d bytes needed to store MAC addresses",
631 RTE_ETHER_ADDR_LEN * TXGBE_VMDQ_NUM_UC_MAC);
635 /* initialize the vfta */
636 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
638 /* initialize the hw strip bitmap*/
639 memset(hwstrip, 0, sizeof(*hwstrip));
641 /* initialize PF if max_vfs not zero */
642 txgbe_pf_host_init(eth_dev);
644 ctrl_ext = rd32(hw, TXGBE_PORTCTL);
645 /* let hardware know driver is loaded */
646 ctrl_ext |= TXGBE_PORTCTL_DRVLOAD;
647 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
648 ctrl_ext |= TXGBE_PORTCTL_RSTDONE;
649 wr32(hw, TXGBE_PORTCTL, ctrl_ext);
652 if (txgbe_is_sfp(hw) && hw->phy.sfp_type != txgbe_sfp_type_not_present)
653 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
654 (int)hw->mac.type, (int)hw->phy.type,
655 (int)hw->phy.sfp_type);
657 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
658 (int)hw->mac.type, (int)hw->phy.type);
660 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
661 eth_dev->data->port_id, pci_dev->id.vendor_id,
662 pci_dev->id.device_id);
664 rte_intr_callback_register(intr_handle,
665 txgbe_dev_interrupt_handler, eth_dev);
667 /* enable uio/vfio intr/eventfd mapping */
668 rte_intr_enable(intr_handle);
670 /* enable support intr */
671 txgbe_enable_intr(eth_dev);
673 /* initialize bandwidth configuration info */
674 memset(bw_conf, 0, sizeof(struct txgbe_bw_conf));
680 eth_txgbe_dev_uninit(struct rte_eth_dev *eth_dev)
682 PMD_INIT_FUNC_TRACE();
684 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
687 txgbe_dev_close(eth_dev);
693 eth_txgbe_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
694 struct rte_pci_device *pci_dev)
696 struct rte_eth_dev *pf_ethdev;
697 struct rte_eth_devargs eth_da;
700 if (pci_dev->device.devargs) {
701 retval = rte_eth_devargs_parse(pci_dev->device.devargs->args,
706 memset(ð_da, 0, sizeof(eth_da));
709 retval = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
710 sizeof(struct txgbe_adapter),
711 eth_dev_pci_specific_init, pci_dev,
712 eth_txgbe_dev_init, NULL);
714 if (retval || eth_da.nb_representor_ports < 1)
717 pf_ethdev = rte_eth_dev_allocated(pci_dev->device.name);
718 if (pf_ethdev == NULL)
724 static int eth_txgbe_pci_remove(struct rte_pci_device *pci_dev)
726 struct rte_eth_dev *ethdev;
728 ethdev = rte_eth_dev_allocated(pci_dev->device.name);
732 return rte_eth_dev_destroy(ethdev, eth_txgbe_dev_uninit);
735 static struct rte_pci_driver rte_txgbe_pmd = {
736 .id_table = pci_id_txgbe_map,
737 .drv_flags = RTE_PCI_DRV_NEED_MAPPING |
738 RTE_PCI_DRV_INTR_LSC,
739 .probe = eth_txgbe_pci_probe,
740 .remove = eth_txgbe_pci_remove,
744 txgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
746 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
747 struct txgbe_vfta *shadow_vfta = TXGBE_DEV_VFTA(dev);
752 vid_idx = (uint32_t)((vlan_id >> 5) & 0x7F);
753 vid_bit = (uint32_t)(1 << (vlan_id & 0x1F));
754 vfta = rd32(hw, TXGBE_VLANTBL(vid_idx));
759 wr32(hw, TXGBE_VLANTBL(vid_idx), vfta);
761 /* update local VFTA copy */
762 shadow_vfta->vfta[vid_idx] = vfta;
768 txgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
770 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
771 struct txgbe_rx_queue *rxq;
773 uint32_t rxcfg, rxbal, rxbah;
776 txgbe_vlan_hw_strip_enable(dev, queue);
778 txgbe_vlan_hw_strip_disable(dev, queue);
780 rxq = dev->data->rx_queues[queue];
781 rxbal = rd32(hw, TXGBE_RXBAL(rxq->reg_idx));
782 rxbah = rd32(hw, TXGBE_RXBAH(rxq->reg_idx));
783 rxcfg = rd32(hw, TXGBE_RXCFG(rxq->reg_idx));
784 if (rxq->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) {
785 restart = (rxcfg & TXGBE_RXCFG_ENA) &&
786 !(rxcfg & TXGBE_RXCFG_VLAN);
787 rxcfg |= TXGBE_RXCFG_VLAN;
789 restart = (rxcfg & TXGBE_RXCFG_ENA) &&
790 (rxcfg & TXGBE_RXCFG_VLAN);
791 rxcfg &= ~TXGBE_RXCFG_VLAN;
793 rxcfg &= ~TXGBE_RXCFG_ENA;
796 /* set vlan strip for ring */
797 txgbe_dev_rx_queue_stop(dev, queue);
798 wr32(hw, TXGBE_RXBAL(rxq->reg_idx), rxbal);
799 wr32(hw, TXGBE_RXBAH(rxq->reg_idx), rxbah);
800 wr32(hw, TXGBE_RXCFG(rxq->reg_idx), rxcfg);
801 txgbe_dev_rx_queue_start(dev, queue);
806 txgbe_vlan_tpid_set(struct rte_eth_dev *dev,
807 enum rte_vlan_type vlan_type,
810 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
812 uint32_t portctrl, vlan_ext, qinq;
814 portctrl = rd32(hw, TXGBE_PORTCTL);
816 vlan_ext = (portctrl & TXGBE_PORTCTL_VLANEXT);
817 qinq = vlan_ext && (portctrl & TXGBE_PORTCTL_QINQ);
819 case ETH_VLAN_TYPE_INNER:
821 wr32m(hw, TXGBE_VLANCTL,
822 TXGBE_VLANCTL_TPID_MASK,
823 TXGBE_VLANCTL_TPID(tpid));
824 wr32m(hw, TXGBE_DMATXCTRL,
825 TXGBE_DMATXCTRL_TPID_MASK,
826 TXGBE_DMATXCTRL_TPID(tpid));
829 PMD_DRV_LOG(ERR, "Inner type is not supported"
834 wr32m(hw, TXGBE_TAGTPID(0),
835 TXGBE_TAGTPID_LSB_MASK,
836 TXGBE_TAGTPID_LSB(tpid));
839 case ETH_VLAN_TYPE_OUTER:
841 /* Only the high 16-bits is valid */
842 wr32m(hw, TXGBE_EXTAG,
843 TXGBE_EXTAG_VLAN_MASK,
844 TXGBE_EXTAG_VLAN(tpid));
846 wr32m(hw, TXGBE_VLANCTL,
847 TXGBE_VLANCTL_TPID_MASK,
848 TXGBE_VLANCTL_TPID(tpid));
849 wr32m(hw, TXGBE_DMATXCTRL,
850 TXGBE_DMATXCTRL_TPID_MASK,
851 TXGBE_DMATXCTRL_TPID(tpid));
855 wr32m(hw, TXGBE_TAGTPID(0),
856 TXGBE_TAGTPID_MSB_MASK,
857 TXGBE_TAGTPID_MSB(tpid));
861 PMD_DRV_LOG(ERR, "Unsupported VLAN type %d", vlan_type);
869 txgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
871 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
874 PMD_INIT_FUNC_TRACE();
876 /* Filter Table Disable */
877 vlnctrl = rd32(hw, TXGBE_VLANCTL);
878 vlnctrl &= ~TXGBE_VLANCTL_VFE;
879 wr32(hw, TXGBE_VLANCTL, vlnctrl);
883 txgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
885 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
886 struct txgbe_vfta *shadow_vfta = TXGBE_DEV_VFTA(dev);
890 PMD_INIT_FUNC_TRACE();
892 /* Filter Table Enable */
893 vlnctrl = rd32(hw, TXGBE_VLANCTL);
894 vlnctrl &= ~TXGBE_VLANCTL_CFIENA;
895 vlnctrl |= TXGBE_VLANCTL_VFE;
896 wr32(hw, TXGBE_VLANCTL, vlnctrl);
898 /* write whatever is in local vfta copy */
899 for (i = 0; i < TXGBE_VFTA_SIZE; i++)
900 wr32(hw, TXGBE_VLANTBL(i), shadow_vfta->vfta[i]);
904 txgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
906 struct txgbe_hwstrip *hwstrip = TXGBE_DEV_HWSTRIP(dev);
907 struct txgbe_rx_queue *rxq;
909 if (queue >= TXGBE_MAX_RX_QUEUE_NUM)
913 TXGBE_SET_HWSTRIP(hwstrip, queue);
915 TXGBE_CLEAR_HWSTRIP(hwstrip, queue);
917 if (queue >= dev->data->nb_rx_queues)
920 rxq = dev->data->rx_queues[queue];
923 rxq->vlan_flags = PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
924 rxq->offloads |= DEV_RX_OFFLOAD_VLAN_STRIP;
926 rxq->vlan_flags = PKT_RX_VLAN;
927 rxq->offloads &= ~DEV_RX_OFFLOAD_VLAN_STRIP;
932 txgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
934 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
937 PMD_INIT_FUNC_TRACE();
939 ctrl = rd32(hw, TXGBE_RXCFG(queue));
940 ctrl &= ~TXGBE_RXCFG_VLAN;
941 wr32(hw, TXGBE_RXCFG(queue), ctrl);
943 /* record those setting for HW strip per queue */
944 txgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
948 txgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
950 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
953 PMD_INIT_FUNC_TRACE();
955 ctrl = rd32(hw, TXGBE_RXCFG(queue));
956 ctrl |= TXGBE_RXCFG_VLAN;
957 wr32(hw, TXGBE_RXCFG(queue), ctrl);
959 /* record those setting for HW strip per queue */
960 txgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
964 txgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
966 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
969 PMD_INIT_FUNC_TRACE();
971 ctrl = rd32(hw, TXGBE_PORTCTL);
972 ctrl &= ~TXGBE_PORTCTL_VLANEXT;
973 ctrl &= ~TXGBE_PORTCTL_QINQ;
974 wr32(hw, TXGBE_PORTCTL, ctrl);
978 txgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
980 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
981 struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
982 struct rte_eth_txmode *txmode = &dev->data->dev_conf.txmode;
985 PMD_INIT_FUNC_TRACE();
987 ctrl = rd32(hw, TXGBE_PORTCTL);
988 ctrl |= TXGBE_PORTCTL_VLANEXT;
989 if (rxmode->offloads & DEV_RX_OFFLOAD_QINQ_STRIP ||
990 txmode->offloads & DEV_TX_OFFLOAD_QINQ_INSERT)
991 ctrl |= TXGBE_PORTCTL_QINQ;
992 wr32(hw, TXGBE_PORTCTL, ctrl);
996 txgbe_vlan_hw_strip_config(struct rte_eth_dev *dev)
998 struct txgbe_rx_queue *rxq;
1001 PMD_INIT_FUNC_TRACE();
1003 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1004 rxq = dev->data->rx_queues[i];
1006 if (rxq->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1007 txgbe_vlan_strip_queue_set(dev, i, 1);
1009 txgbe_vlan_strip_queue_set(dev, i, 0);
1014 txgbe_config_vlan_strip_on_all_queues(struct rte_eth_dev *dev, int mask)
1017 struct rte_eth_rxmode *rxmode;
1018 struct txgbe_rx_queue *rxq;
1020 if (mask & ETH_VLAN_STRIP_MASK) {
1021 rxmode = &dev->data->dev_conf.rxmode;
1022 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1023 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1024 rxq = dev->data->rx_queues[i];
1025 rxq->offloads |= DEV_RX_OFFLOAD_VLAN_STRIP;
1028 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1029 rxq = dev->data->rx_queues[i];
1030 rxq->offloads &= ~DEV_RX_OFFLOAD_VLAN_STRIP;
1036 txgbe_vlan_offload_config(struct rte_eth_dev *dev, int mask)
1038 struct rte_eth_rxmode *rxmode;
1039 rxmode = &dev->data->dev_conf.rxmode;
1041 if (mask & ETH_VLAN_STRIP_MASK)
1042 txgbe_vlan_hw_strip_config(dev);
1044 if (mask & ETH_VLAN_FILTER_MASK) {
1045 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
1046 txgbe_vlan_hw_filter_enable(dev);
1048 txgbe_vlan_hw_filter_disable(dev);
1051 if (mask & ETH_VLAN_EXTEND_MASK) {
1052 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
1053 txgbe_vlan_hw_extend_enable(dev);
1055 txgbe_vlan_hw_extend_disable(dev);
1062 txgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1064 txgbe_config_vlan_strip_on_all_queues(dev, mask);
1066 txgbe_vlan_offload_config(dev, mask);
1072 txgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1074 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
1075 /* VLNCTL: enable vlan filtering and allow all vlan tags through */
1076 uint32_t vlanctrl = rd32(hw, TXGBE_VLANCTL);
1078 vlanctrl |= TXGBE_VLANCTL_VFE; /* enable vlan filters */
1079 wr32(hw, TXGBE_VLANCTL, vlanctrl);
1083 txgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q)
1085 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1090 RTE_ETH_DEV_SRIOV(dev).active = ETH_64_POOLS;
1093 RTE_ETH_DEV_SRIOV(dev).active = ETH_32_POOLS;
1099 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool =
1100 TXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
1101 RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx =
1102 pci_dev->max_vfs * RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
1107 txgbe_check_mq_mode(struct rte_eth_dev *dev)
1109 struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
1110 uint16_t nb_rx_q = dev->data->nb_rx_queues;
1111 uint16_t nb_tx_q = dev->data->nb_tx_queues;
1113 if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
1114 /* check multi-queue mode */
1115 switch (dev_conf->rxmode.mq_mode) {
1116 case ETH_MQ_RX_VMDQ_DCB:
1117 PMD_INIT_LOG(INFO, "ETH_MQ_RX_VMDQ_DCB mode supported in SRIOV");
1119 case ETH_MQ_RX_VMDQ_DCB_RSS:
1120 /* DCB/RSS VMDQ in SRIOV mode, not implement yet */
1121 PMD_INIT_LOG(ERR, "SRIOV active,"
1122 " unsupported mq_mode rx %d.",
1123 dev_conf->rxmode.mq_mode);
1126 case ETH_MQ_RX_VMDQ_RSS:
1127 dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_RSS;
1128 if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)
1129 if (txgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) {
1130 PMD_INIT_LOG(ERR, "SRIOV is active,"
1131 " invalid queue number"
1132 " for VMDQ RSS, allowed"
1133 " value are 1, 2 or 4.");
1137 case ETH_MQ_RX_VMDQ_ONLY:
1138 case ETH_MQ_RX_NONE:
1139 /* if nothing mq mode configure, use default scheme */
1140 dev->data->dev_conf.rxmode.mq_mode =
1141 ETH_MQ_RX_VMDQ_ONLY;
1143 default: /* ETH_MQ_RX_DCB, ETH_MQ_RX_DCB_RSS or ETH_MQ_TX_DCB*/
1144 /* SRIOV only works in VMDq enable mode */
1145 PMD_INIT_LOG(ERR, "SRIOV is active,"
1146 " wrong mq_mode rx %d.",
1147 dev_conf->rxmode.mq_mode);
1151 switch (dev_conf->txmode.mq_mode) {
1152 case ETH_MQ_TX_VMDQ_DCB:
1153 PMD_INIT_LOG(INFO, "ETH_MQ_TX_VMDQ_DCB mode supported in SRIOV");
1154 dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_DCB;
1156 default: /* ETH_MQ_TX_VMDQ_ONLY or ETH_MQ_TX_NONE */
1157 dev->data->dev_conf.txmode.mq_mode =
1158 ETH_MQ_TX_VMDQ_ONLY;
1162 /* check valid queue number */
1163 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) ||
1164 (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) {
1165 PMD_INIT_LOG(ERR, "SRIOV is active,"
1166 " nb_rx_q=%d nb_tx_q=%d queue number"
1167 " must be less than or equal to %d.",
1169 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool);
1173 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
1174 PMD_INIT_LOG(ERR, "VMDQ+DCB+RSS mq_mode is"
1178 /* check configuration for vmdb+dcb mode */
1179 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB) {
1180 const struct rte_eth_vmdq_dcb_conf *conf;
1182 if (nb_rx_q != TXGBE_VMDQ_DCB_NB_QUEUES) {
1183 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.",
1184 TXGBE_VMDQ_DCB_NB_QUEUES);
1187 conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf;
1188 if (!(conf->nb_queue_pools == ETH_16_POOLS ||
1189 conf->nb_queue_pools == ETH_32_POOLS)) {
1190 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
1191 " nb_queue_pools must be %d or %d.",
1192 ETH_16_POOLS, ETH_32_POOLS);
1196 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) {
1197 const struct rte_eth_vmdq_dcb_tx_conf *conf;
1199 if (nb_tx_q != TXGBE_VMDQ_DCB_NB_QUEUES) {
1200 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d",
1201 TXGBE_VMDQ_DCB_NB_QUEUES);
1204 conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf;
1205 if (!(conf->nb_queue_pools == ETH_16_POOLS ||
1206 conf->nb_queue_pools == ETH_32_POOLS)) {
1207 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
1208 " nb_queue_pools != %d and"
1209 " nb_queue_pools != %d.",
1210 ETH_16_POOLS, ETH_32_POOLS);
1215 /* For DCB mode check our configuration before we go further */
1216 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_DCB) {
1217 const struct rte_eth_dcb_rx_conf *conf;
1219 conf = &dev_conf->rx_adv_conf.dcb_rx_conf;
1220 if (!(conf->nb_tcs == ETH_4_TCS ||
1221 conf->nb_tcs == ETH_8_TCS)) {
1222 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
1223 " and nb_tcs != %d.",
1224 ETH_4_TCS, ETH_8_TCS);
1229 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_DCB) {
1230 const struct rte_eth_dcb_tx_conf *conf;
1232 conf = &dev_conf->tx_adv_conf.dcb_tx_conf;
1233 if (!(conf->nb_tcs == ETH_4_TCS ||
1234 conf->nb_tcs == ETH_8_TCS)) {
1235 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
1236 " and nb_tcs != %d.",
1237 ETH_4_TCS, ETH_8_TCS);
1246 txgbe_dev_configure(struct rte_eth_dev *dev)
1248 struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);
1249 struct txgbe_adapter *adapter = TXGBE_DEV_ADAPTER(dev);
1252 PMD_INIT_FUNC_TRACE();
1254 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
1255 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
1257 /* multiple queue mode checking */
1258 ret = txgbe_check_mq_mode(dev);
1260 PMD_DRV_LOG(ERR, "txgbe_check_mq_mode fails with %d.",
1265 /* set flag to update link status after init */
1266 intr->flags |= TXGBE_FLAG_NEED_LINK_UPDATE;
1269 * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
1270 * allocation Rx preconditions we will reset it.
1272 adapter->rx_bulk_alloc_allowed = true;
1278 txgbe_dev_phy_intr_setup(struct rte_eth_dev *dev)
1280 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
1281 struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);
1284 gpie = rd32(hw, TXGBE_GPIOINTEN);
1285 gpie |= TXGBE_GPIOBIT_6;
1286 wr32(hw, TXGBE_GPIOINTEN, gpie);
1287 intr->mask_misc |= TXGBE_ICRMISC_GPIO;
1291 txgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
1292 uint16_t tx_rate, uint64_t q_msk)
1294 struct txgbe_hw *hw;
1295 struct txgbe_vf_info *vfinfo;
1296 struct rte_eth_link link;
1297 uint8_t nb_q_per_pool;
1298 uint32_t queue_stride;
1299 uint32_t queue_idx, idx = 0, vf_idx;
1301 uint16_t total_rate = 0;
1302 struct rte_pci_device *pci_dev;
1305 pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1306 ret = rte_eth_link_get_nowait(dev->data->port_id, &link);
1310 if (vf >= pci_dev->max_vfs)
1313 if (tx_rate > link.link_speed)
1319 hw = TXGBE_DEV_HW(dev);
1320 vfinfo = *(TXGBE_DEV_VFDATA(dev));
1321 nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
1322 queue_stride = TXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
1323 queue_idx = vf * queue_stride;
1324 queue_end = queue_idx + nb_q_per_pool - 1;
1325 if (queue_end >= hw->mac.max_tx_queues)
1329 for (vf_idx = 0; vf_idx < pci_dev->max_vfs; vf_idx++) {
1332 for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
1334 total_rate += vfinfo[vf_idx].tx_rate[idx];
1340 /* Store tx_rate for this vf. */
1341 for (idx = 0; idx < nb_q_per_pool; idx++) {
1342 if (((uint64_t)0x1 << idx) & q_msk) {
1343 if (vfinfo[vf].tx_rate[idx] != tx_rate)
1344 vfinfo[vf].tx_rate[idx] = tx_rate;
1345 total_rate += tx_rate;
1349 if (total_rate > dev->data->dev_link.link_speed) {
1350 /* Reset stored TX rate of the VF if it causes exceed
1353 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
1357 /* Set ARBTXRATE of each queue/pool for vf X */
1358 for (; queue_idx <= queue_end; queue_idx++) {
1360 txgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
1368 * Configure device link speed and setup link.
1369 * It returns 0 on success.
1372 txgbe_dev_start(struct rte_eth_dev *dev)
1374 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
1375 struct txgbe_hw_stats *hw_stats = TXGBE_DEV_STATS(dev);
1376 struct txgbe_vf_info *vfinfo = *TXGBE_DEV_VFDATA(dev);
1377 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1378 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1379 uint32_t intr_vector = 0;
1381 bool link_up = false, negotiate = 0;
1383 uint32_t allowed_speeds = 0;
1387 uint32_t *link_speeds;
1389 PMD_INIT_FUNC_TRACE();
1391 /* TXGBE devices don't support:
1392 * - half duplex (checked afterwards for valid speeds)
1393 * - fixed speed: TODO implement
1395 if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
1397 "Invalid link_speeds for port %u, fix speed not supported",
1398 dev->data->port_id);
1402 /* Stop the link setup handler before resetting the HW. */
1403 rte_eal_alarm_cancel(txgbe_dev_setup_link_alarm_handler, dev);
1405 /* disable uio/vfio intr/eventfd mapping */
1406 rte_intr_disable(intr_handle);
1409 hw->adapter_stopped = 0;
1412 /* reinitialize adapter
1413 * this calls reset and start
1415 hw->nb_rx_queues = dev->data->nb_rx_queues;
1416 hw->nb_tx_queues = dev->data->nb_tx_queues;
1417 status = txgbe_pf_reset_hw(hw);
1420 hw->mac.start_hw(hw);
1421 hw->mac.get_link_status = true;
1423 /* configure PF module if SRIOV enabled */
1424 txgbe_pf_host_configure(dev);
1426 txgbe_dev_phy_intr_setup(dev);
1428 /* check and configure queue intr-vector mapping */
1429 if ((rte_intr_cap_multiple(intr_handle) ||
1430 !RTE_ETH_DEV_SRIOV(dev).active) &&
1431 dev->data->dev_conf.intr_conf.rxq != 0) {
1432 intr_vector = dev->data->nb_rx_queues;
1433 if (rte_intr_efd_enable(intr_handle, intr_vector))
1437 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1438 intr_handle->intr_vec =
1439 rte_zmalloc("intr_vec",
1440 dev->data->nb_rx_queues * sizeof(int), 0);
1441 if (intr_handle->intr_vec == NULL) {
1442 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
1443 " intr_vec", dev->data->nb_rx_queues);
1448 /* confiugre msix for sleep until rx interrupt */
1449 txgbe_configure_msix(dev);
1451 /* initialize transmission unit */
1452 txgbe_dev_tx_init(dev);
1454 /* This can fail when allocating mbufs for descriptor rings */
1455 err = txgbe_dev_rx_init(dev);
1457 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
1461 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
1462 ETH_VLAN_EXTEND_MASK;
1463 err = txgbe_vlan_offload_config(dev, mask);
1465 PMD_INIT_LOG(ERR, "Unable to set VLAN offload");
1469 if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1470 /* Enable vlan filtering for VMDq */
1471 txgbe_vmdq_vlan_hw_filter_enable(dev);
1474 /* Configure DCB hw */
1475 txgbe_configure_pb(dev);
1476 txgbe_configure_port(dev);
1477 txgbe_configure_dcb(dev);
1479 /* Restore vf rate limit */
1480 if (vfinfo != NULL) {
1481 for (vf = 0; vf < pci_dev->max_vfs; vf++)
1482 for (idx = 0; idx < TXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
1483 if (vfinfo[vf].tx_rate[idx] != 0)
1484 txgbe_set_vf_rate_limit(dev, vf,
1485 vfinfo[vf].tx_rate[idx],
1489 err = txgbe_dev_rxtx_start(dev);
1491 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
1495 /* Skip link setup if loopback mode is enabled. */
1496 if (hw->mac.type == txgbe_mac_raptor &&
1497 dev->data->dev_conf.lpbk_mode)
1498 goto skip_link_setup;
1500 if (txgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
1501 err = hw->mac.setup_sfp(hw);
1506 if (hw->phy.media_type == txgbe_media_type_copper) {
1507 /* Turn on the copper */
1508 hw->phy.set_phy_power(hw, true);
1510 /* Turn on the laser */
1511 hw->mac.enable_tx_laser(hw);
1514 err = hw->mac.check_link(hw, &speed, &link_up, 0);
1517 dev->data->dev_link.link_status = link_up;
1519 err = hw->mac.get_link_capabilities(hw, &speed, &negotiate);
1523 allowed_speeds = ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
1526 link_speeds = &dev->data->dev_conf.link_speeds;
1527 if (*link_speeds & ~allowed_speeds) {
1528 PMD_INIT_LOG(ERR, "Invalid link setting");
1533 if (*link_speeds == ETH_LINK_SPEED_AUTONEG) {
1534 speed = (TXGBE_LINK_SPEED_100M_FULL |
1535 TXGBE_LINK_SPEED_1GB_FULL |
1536 TXGBE_LINK_SPEED_10GB_FULL);
1538 if (*link_speeds & ETH_LINK_SPEED_10G)
1539 speed |= TXGBE_LINK_SPEED_10GB_FULL;
1540 if (*link_speeds & ETH_LINK_SPEED_5G)
1541 speed |= TXGBE_LINK_SPEED_5GB_FULL;
1542 if (*link_speeds & ETH_LINK_SPEED_2_5G)
1543 speed |= TXGBE_LINK_SPEED_2_5GB_FULL;
1544 if (*link_speeds & ETH_LINK_SPEED_1G)
1545 speed |= TXGBE_LINK_SPEED_1GB_FULL;
1546 if (*link_speeds & ETH_LINK_SPEED_100M)
1547 speed |= TXGBE_LINK_SPEED_100M_FULL;
1550 err = hw->mac.setup_link(hw, speed, link_up);
1556 if (rte_intr_allow_others(intr_handle)) {
1557 /* check if lsc interrupt is enabled */
1558 if (dev->data->dev_conf.intr_conf.lsc != 0)
1559 txgbe_dev_lsc_interrupt_setup(dev, TRUE);
1561 txgbe_dev_lsc_interrupt_setup(dev, FALSE);
1562 txgbe_dev_macsec_interrupt_setup(dev);
1563 txgbe_set_ivar_map(hw, -1, 1, TXGBE_MISC_VEC_ID);
1565 rte_intr_callback_unregister(intr_handle,
1566 txgbe_dev_interrupt_handler, dev);
1567 if (dev->data->dev_conf.intr_conf.lsc != 0)
1568 PMD_INIT_LOG(INFO, "lsc won't enable because of"
1569 " no intr multiplex");
1572 /* check if rxq interrupt is enabled */
1573 if (dev->data->dev_conf.intr_conf.rxq != 0 &&
1574 rte_intr_dp_is_en(intr_handle))
1575 txgbe_dev_rxq_interrupt_setup(dev);
1577 /* enable uio/vfio intr/eventfd mapping */
1578 rte_intr_enable(intr_handle);
1580 /* resume enabled intr since hw reset */
1581 txgbe_enable_intr(dev);
1584 * Update link status right before return, because it may
1585 * start link configuration process in a separate thread.
1587 txgbe_dev_link_update(dev, 0);
1589 wr32m(hw, TXGBE_LEDCTL, 0xFFFFFFFF, TXGBE_LEDCTL_ORD_MASK);
1591 txgbe_read_stats_registers(hw, hw_stats);
1592 hw->offset_loaded = 1;
1597 PMD_INIT_LOG(ERR, "failure in dev start: %d", err);
1598 txgbe_dev_clear_queues(dev);
1603 * Stop device: disable rx and tx functions to allow for reconfiguring.
1606 txgbe_dev_stop(struct rte_eth_dev *dev)
1608 struct rte_eth_link link;
1609 struct txgbe_adapter *adapter = TXGBE_DEV_ADAPTER(dev);
1610 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
1611 struct txgbe_vf_info *vfinfo = *TXGBE_DEV_VFDATA(dev);
1612 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1613 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1616 if (hw->adapter_stopped)
1619 PMD_INIT_FUNC_TRACE();
1621 rte_eal_alarm_cancel(txgbe_dev_setup_link_alarm_handler, dev);
1623 /* disable interrupts */
1624 txgbe_disable_intr(hw);
1627 txgbe_pf_reset_hw(hw);
1628 hw->adapter_stopped = 0;
1633 for (vf = 0; vfinfo != NULL && vf < pci_dev->max_vfs; vf++)
1634 vfinfo[vf].clear_to_send = false;
1636 if (hw->phy.media_type == txgbe_media_type_copper) {
1637 /* Turn off the copper */
1638 hw->phy.set_phy_power(hw, false);
1640 /* Turn off the laser */
1641 hw->mac.disable_tx_laser(hw);
1644 txgbe_dev_clear_queues(dev);
1646 /* Clear stored conf */
1647 dev->data->scattered_rx = 0;
1650 /* Clear recorded link status */
1651 memset(&link, 0, sizeof(link));
1652 rte_eth_linkstatus_set(dev, &link);
1654 if (!rte_intr_allow_others(intr_handle))
1655 /* resume to the default handler */
1656 rte_intr_callback_register(intr_handle,
1657 txgbe_dev_interrupt_handler,
1660 /* Clean datapath event and queue/vec mapping */
1661 rte_intr_efd_disable(intr_handle);
1662 if (intr_handle->intr_vec != NULL) {
1663 rte_free(intr_handle->intr_vec);
1664 intr_handle->intr_vec = NULL;
1667 adapter->rss_reta_updated = 0;
1668 wr32m(hw, TXGBE_LEDCTL, 0xFFFFFFFF, TXGBE_LEDCTL_SEL_MASK);
1670 hw->adapter_stopped = true;
1671 dev->data->dev_started = 0;
1677 * Set device link up: enable tx.
1680 txgbe_dev_set_link_up(struct rte_eth_dev *dev)
1682 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
1684 if (hw->phy.media_type == txgbe_media_type_copper) {
1685 /* Turn on the copper */
1686 hw->phy.set_phy_power(hw, true);
1688 /* Turn on the laser */
1689 hw->mac.enable_tx_laser(hw);
1690 txgbe_dev_link_update(dev, 0);
1697 * Set device link down: disable tx.
1700 txgbe_dev_set_link_down(struct rte_eth_dev *dev)
1702 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
1704 if (hw->phy.media_type == txgbe_media_type_copper) {
1705 /* Turn off the copper */
1706 hw->phy.set_phy_power(hw, false);
1708 /* Turn off the laser */
1709 hw->mac.disable_tx_laser(hw);
1710 txgbe_dev_link_update(dev, 0);
1717 * Reset and stop device.
1720 txgbe_dev_close(struct rte_eth_dev *dev)
1722 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
1723 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1724 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1728 PMD_INIT_FUNC_TRACE();
1730 txgbe_pf_reset_hw(hw);
1732 ret = txgbe_dev_stop(dev);
1734 txgbe_dev_free_queues(dev);
1736 /* reprogram the RAR[0] in case user changed it. */
1737 txgbe_set_rar(hw, 0, hw->mac.addr, 0, true);
1739 /* Unlock any pending hardware semaphore */
1740 txgbe_swfw_lock_reset(hw);
1742 /* disable uio intr before callback unregister */
1743 rte_intr_disable(intr_handle);
1746 ret = rte_intr_callback_unregister(intr_handle,
1747 txgbe_dev_interrupt_handler, dev);
1748 if (ret >= 0 || ret == -ENOENT) {
1750 } else if (ret != -EAGAIN) {
1752 "intr callback unregister failed: %d",
1756 } while (retries++ < (10 + TXGBE_LINK_UP_TIME));
1758 /* cancel the delay handler before remove dev */
1759 rte_eal_alarm_cancel(txgbe_dev_interrupt_delayed_handler, dev);
1761 /* uninitialize PF if max_vfs not zero */
1762 txgbe_pf_host_uninit(dev);
1764 rte_free(dev->data->mac_addrs);
1765 dev->data->mac_addrs = NULL;
1767 rte_free(dev->data->hash_mac_addrs);
1768 dev->data->hash_mac_addrs = NULL;
1777 txgbe_dev_reset(struct rte_eth_dev *dev)
1781 /* When a DPDK PMD PF begin to reset PF port, it should notify all
1782 * its VF to make them align with it. The detailed notification
1783 * mechanism is PMD specific. As to txgbe PF, it is rather complex.
1784 * To avoid unexpected behavior in VF, currently reset of PF with
1785 * SR-IOV activation is not supported. It might be supported later.
1787 if (dev->data->sriov.active)
1790 ret = eth_txgbe_dev_uninit(dev);
1794 ret = eth_txgbe_dev_init(dev, NULL);
1799 #define UPDATE_QP_COUNTER_32bit(reg, last_counter, counter) \
1801 uint32_t current_counter = rd32(hw, reg); \
1802 if (current_counter < last_counter) \
1803 current_counter += 0x100000000LL; \
1804 if (!hw->offset_loaded) \
1805 last_counter = current_counter; \
1806 counter = current_counter - last_counter; \
1807 counter &= 0xFFFFFFFFLL; \
1810 #define UPDATE_QP_COUNTER_36bit(reg_lsb, reg_msb, last_counter, counter) \
1812 uint64_t current_counter_lsb = rd32(hw, reg_lsb); \
1813 uint64_t current_counter_msb = rd32(hw, reg_msb); \
1814 uint64_t current_counter = (current_counter_msb << 32) | \
1815 current_counter_lsb; \
1816 if (current_counter < last_counter) \
1817 current_counter += 0x1000000000LL; \
1818 if (!hw->offset_loaded) \
1819 last_counter = current_counter; \
1820 counter = current_counter - last_counter; \
1821 counter &= 0xFFFFFFFFFLL; \
1825 txgbe_read_stats_registers(struct txgbe_hw *hw,
1826 struct txgbe_hw_stats *hw_stats)
1831 for (i = 0; i < hw->nb_rx_queues; i++) {
1832 UPDATE_QP_COUNTER_32bit(TXGBE_QPRXPKT(i),
1833 hw->qp_last[i].rx_qp_packets,
1834 hw_stats->qp[i].rx_qp_packets);
1835 UPDATE_QP_COUNTER_36bit(TXGBE_QPRXOCTL(i), TXGBE_QPRXOCTH(i),
1836 hw->qp_last[i].rx_qp_bytes,
1837 hw_stats->qp[i].rx_qp_bytes);
1838 UPDATE_QP_COUNTER_32bit(TXGBE_QPRXMPKT(i),
1839 hw->qp_last[i].rx_qp_mc_packets,
1840 hw_stats->qp[i].rx_qp_mc_packets);
1843 for (i = 0; i < hw->nb_tx_queues; i++) {
1844 UPDATE_QP_COUNTER_32bit(TXGBE_QPTXPKT(i),
1845 hw->qp_last[i].tx_qp_packets,
1846 hw_stats->qp[i].tx_qp_packets);
1847 UPDATE_QP_COUNTER_36bit(TXGBE_QPTXOCTL(i), TXGBE_QPTXOCTH(i),
1848 hw->qp_last[i].tx_qp_bytes,
1849 hw_stats->qp[i].tx_qp_bytes);
1852 for (i = 0; i < TXGBE_MAX_UP; i++) {
1853 hw_stats->up[i].rx_up_xon_packets +=
1854 rd32(hw, TXGBE_PBRXUPXON(i));
1855 hw_stats->up[i].rx_up_xoff_packets +=
1856 rd32(hw, TXGBE_PBRXUPXOFF(i));
1857 hw_stats->up[i].tx_up_xon_packets +=
1858 rd32(hw, TXGBE_PBTXUPXON(i));
1859 hw_stats->up[i].tx_up_xoff_packets +=
1860 rd32(hw, TXGBE_PBTXUPXOFF(i));
1861 hw_stats->up[i].tx_up_xon2off_packets +=
1862 rd32(hw, TXGBE_PBTXUPOFF(i));
1863 hw_stats->up[i].rx_up_dropped +=
1864 rd32(hw, TXGBE_PBRXMISS(i));
1866 hw_stats->rx_xon_packets += rd32(hw, TXGBE_PBRXLNKXON);
1867 hw_stats->rx_xoff_packets += rd32(hw, TXGBE_PBRXLNKXOFF);
1868 hw_stats->tx_xon_packets += rd32(hw, TXGBE_PBTXLNKXON);
1869 hw_stats->tx_xoff_packets += rd32(hw, TXGBE_PBTXLNKXOFF);
1872 hw_stats->rx_packets += rd32(hw, TXGBE_DMARXPKT);
1873 hw_stats->tx_packets += rd32(hw, TXGBE_DMATXPKT);
1875 hw_stats->rx_bytes += rd64(hw, TXGBE_DMARXOCTL);
1876 hw_stats->tx_bytes += rd64(hw, TXGBE_DMATXOCTL);
1877 hw_stats->rx_drop_packets += rd32(hw, TXGBE_PBRXDROP);
1880 hw_stats->rx_crc_errors += rd64(hw, TXGBE_MACRXERRCRCL);
1881 hw_stats->rx_multicast_packets += rd64(hw, TXGBE_MACRXMPKTL);
1882 hw_stats->tx_multicast_packets += rd64(hw, TXGBE_MACTXMPKTL);
1884 hw_stats->rx_total_packets += rd64(hw, TXGBE_MACRXPKTL);
1885 hw_stats->tx_total_packets += rd64(hw, TXGBE_MACTXPKTL);
1886 hw_stats->rx_total_bytes += rd64(hw, TXGBE_MACRXGBOCTL);
1888 hw_stats->rx_broadcast_packets += rd64(hw, TXGBE_MACRXOCTL);
1889 hw_stats->tx_broadcast_packets += rd32(hw, TXGBE_MACTXOCTL);
1891 hw_stats->rx_size_64_packets += rd64(hw, TXGBE_MACRX1TO64L);
1892 hw_stats->rx_size_65_to_127_packets += rd64(hw, TXGBE_MACRX65TO127L);
1893 hw_stats->rx_size_128_to_255_packets += rd64(hw, TXGBE_MACRX128TO255L);
1894 hw_stats->rx_size_256_to_511_packets += rd64(hw, TXGBE_MACRX256TO511L);
1895 hw_stats->rx_size_512_to_1023_packets +=
1896 rd64(hw, TXGBE_MACRX512TO1023L);
1897 hw_stats->rx_size_1024_to_max_packets +=
1898 rd64(hw, TXGBE_MACRX1024TOMAXL);
1899 hw_stats->tx_size_64_packets += rd64(hw, TXGBE_MACTX1TO64L);
1900 hw_stats->tx_size_65_to_127_packets += rd64(hw, TXGBE_MACTX65TO127L);
1901 hw_stats->tx_size_128_to_255_packets += rd64(hw, TXGBE_MACTX128TO255L);
1902 hw_stats->tx_size_256_to_511_packets += rd64(hw, TXGBE_MACTX256TO511L);
1903 hw_stats->tx_size_512_to_1023_packets +=
1904 rd64(hw, TXGBE_MACTX512TO1023L);
1905 hw_stats->tx_size_1024_to_max_packets +=
1906 rd64(hw, TXGBE_MACTX1024TOMAXL);
1908 hw_stats->rx_undersize_errors += rd64(hw, TXGBE_MACRXERRLENL);
1909 hw_stats->rx_oversize_errors += rd32(hw, TXGBE_MACRXOVERSIZE);
1910 hw_stats->rx_jabber_errors += rd32(hw, TXGBE_MACRXJABBER);
1913 hw_stats->mng_bmc2host_packets = rd32(hw, TXGBE_MNGBMC2OS);
1914 hw_stats->mng_host2bmc_packets = rd32(hw, TXGBE_MNGOS2BMC);
1915 hw_stats->rx_management_packets = rd32(hw, TXGBE_DMARXMNG);
1916 hw_stats->tx_management_packets = rd32(hw, TXGBE_DMATXMNG);
1919 hw_stats->rx_fcoe_crc_errors += rd32(hw, TXGBE_FCOECRC);
1920 hw_stats->rx_fcoe_mbuf_allocation_errors += rd32(hw, TXGBE_FCOELAST);
1921 hw_stats->rx_fcoe_dropped += rd32(hw, TXGBE_FCOERPDC);
1922 hw_stats->rx_fcoe_packets += rd32(hw, TXGBE_FCOEPRC);
1923 hw_stats->tx_fcoe_packets += rd32(hw, TXGBE_FCOEPTC);
1924 hw_stats->rx_fcoe_bytes += rd32(hw, TXGBE_FCOEDWRC);
1925 hw_stats->tx_fcoe_bytes += rd32(hw, TXGBE_FCOEDWTC);
1927 /* Flow Director Stats */
1928 hw_stats->flow_director_matched_filters += rd32(hw, TXGBE_FDIRMATCH);
1929 hw_stats->flow_director_missed_filters += rd32(hw, TXGBE_FDIRMISS);
1930 hw_stats->flow_director_added_filters +=
1931 TXGBE_FDIRUSED_ADD(rd32(hw, TXGBE_FDIRUSED));
1932 hw_stats->flow_director_removed_filters +=
1933 TXGBE_FDIRUSED_REM(rd32(hw, TXGBE_FDIRUSED));
1934 hw_stats->flow_director_filter_add_errors +=
1935 TXGBE_FDIRFAIL_ADD(rd32(hw, TXGBE_FDIRFAIL));
1936 hw_stats->flow_director_filter_remove_errors +=
1937 TXGBE_FDIRFAIL_REM(rd32(hw, TXGBE_FDIRFAIL));
1940 hw_stats->tx_macsec_pkts_untagged += rd32(hw, TXGBE_LSECTX_UTPKT);
1941 hw_stats->tx_macsec_pkts_encrypted +=
1942 rd32(hw, TXGBE_LSECTX_ENCPKT);
1943 hw_stats->tx_macsec_pkts_protected +=
1944 rd32(hw, TXGBE_LSECTX_PROTPKT);
1945 hw_stats->tx_macsec_octets_encrypted +=
1946 rd32(hw, TXGBE_LSECTX_ENCOCT);
1947 hw_stats->tx_macsec_octets_protected +=
1948 rd32(hw, TXGBE_LSECTX_PROTOCT);
1949 hw_stats->rx_macsec_pkts_untagged += rd32(hw, TXGBE_LSECRX_UTPKT);
1950 hw_stats->rx_macsec_pkts_badtag += rd32(hw, TXGBE_LSECRX_BTPKT);
1951 hw_stats->rx_macsec_pkts_nosci += rd32(hw, TXGBE_LSECRX_NOSCIPKT);
1952 hw_stats->rx_macsec_pkts_unknownsci += rd32(hw, TXGBE_LSECRX_UNSCIPKT);
1953 hw_stats->rx_macsec_octets_decrypted += rd32(hw, TXGBE_LSECRX_DECOCT);
1954 hw_stats->rx_macsec_octets_validated += rd32(hw, TXGBE_LSECRX_VLDOCT);
1955 hw_stats->rx_macsec_sc_pkts_unchecked +=
1956 rd32(hw, TXGBE_LSECRX_UNCHKPKT);
1957 hw_stats->rx_macsec_sc_pkts_delayed += rd32(hw, TXGBE_LSECRX_DLYPKT);
1958 hw_stats->rx_macsec_sc_pkts_late += rd32(hw, TXGBE_LSECRX_LATEPKT);
1959 for (i = 0; i < 2; i++) {
1960 hw_stats->rx_macsec_sa_pkts_ok +=
1961 rd32(hw, TXGBE_LSECRX_OKPKT(i));
1962 hw_stats->rx_macsec_sa_pkts_invalid +=
1963 rd32(hw, TXGBE_LSECRX_INVPKT(i));
1964 hw_stats->rx_macsec_sa_pkts_notvalid +=
1965 rd32(hw, TXGBE_LSECRX_BADPKT(i));
1967 hw_stats->rx_macsec_sa_pkts_unusedsa +=
1968 rd32(hw, TXGBE_LSECRX_INVSAPKT);
1969 hw_stats->rx_macsec_sa_pkts_notusingsa +=
1970 rd32(hw, TXGBE_LSECRX_BADSAPKT);
1972 hw_stats->rx_total_missed_packets = 0;
1973 for (i = 0; i < TXGBE_MAX_UP; i++) {
1974 hw_stats->rx_total_missed_packets +=
1975 hw_stats->up[i].rx_up_dropped;
1980 txgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1982 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
1983 struct txgbe_hw_stats *hw_stats = TXGBE_DEV_STATS(dev);
1984 struct txgbe_stat_mappings *stat_mappings =
1985 TXGBE_DEV_STAT_MAPPINGS(dev);
1988 txgbe_read_stats_registers(hw, hw_stats);
1993 /* Fill out the rte_eth_stats statistics structure */
1994 stats->ipackets = hw_stats->rx_packets;
1995 stats->ibytes = hw_stats->rx_bytes;
1996 stats->opackets = hw_stats->tx_packets;
1997 stats->obytes = hw_stats->tx_bytes;
1999 memset(&stats->q_ipackets, 0, sizeof(stats->q_ipackets));
2000 memset(&stats->q_opackets, 0, sizeof(stats->q_opackets));
2001 memset(&stats->q_ibytes, 0, sizeof(stats->q_ibytes));
2002 memset(&stats->q_obytes, 0, sizeof(stats->q_obytes));
2003 memset(&stats->q_errors, 0, sizeof(stats->q_errors));
2004 for (i = 0; i < TXGBE_MAX_QP; i++) {
2005 uint32_t n = i / NB_QMAP_FIELDS_PER_QSM_REG;
2006 uint32_t offset = (i % NB_QMAP_FIELDS_PER_QSM_REG) * 8;
2009 q_map = (stat_mappings->rqsm[n] >> offset)
2010 & QMAP_FIELD_RESERVED_BITS_MASK;
2011 j = (q_map < RTE_ETHDEV_QUEUE_STAT_CNTRS
2012 ? q_map : q_map % RTE_ETHDEV_QUEUE_STAT_CNTRS);
2013 stats->q_ipackets[j] += hw_stats->qp[i].rx_qp_packets;
2014 stats->q_ibytes[j] += hw_stats->qp[i].rx_qp_bytes;
2016 q_map = (stat_mappings->tqsm[n] >> offset)
2017 & QMAP_FIELD_RESERVED_BITS_MASK;
2018 j = (q_map < RTE_ETHDEV_QUEUE_STAT_CNTRS
2019 ? q_map : q_map % RTE_ETHDEV_QUEUE_STAT_CNTRS);
2020 stats->q_opackets[j] += hw_stats->qp[i].tx_qp_packets;
2021 stats->q_obytes[j] += hw_stats->qp[i].tx_qp_bytes;
2025 stats->imissed = hw_stats->rx_total_missed_packets;
2026 stats->ierrors = hw_stats->rx_crc_errors +
2027 hw_stats->rx_mac_short_packet_dropped +
2028 hw_stats->rx_length_errors +
2029 hw_stats->rx_undersize_errors +
2030 hw_stats->rx_oversize_errors +
2031 hw_stats->rx_drop_packets +
2032 hw_stats->rx_illegal_byte_errors +
2033 hw_stats->rx_error_bytes +
2034 hw_stats->rx_fragment_errors +
2035 hw_stats->rx_fcoe_crc_errors +
2036 hw_stats->rx_fcoe_mbuf_allocation_errors;
2044 txgbe_dev_stats_reset(struct rte_eth_dev *dev)
2046 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2047 struct txgbe_hw_stats *hw_stats = TXGBE_DEV_STATS(dev);
2049 /* HW registers are cleared on read */
2050 hw->offset_loaded = 0;
2051 txgbe_dev_stats_get(dev, NULL);
2052 hw->offset_loaded = 1;
2054 /* Reset software totals */
2055 memset(hw_stats, 0, sizeof(*hw_stats));
2060 /* This function calculates the number of xstats based on the current config */
2062 txgbe_xstats_calc_num(struct rte_eth_dev *dev)
2064 int nb_queues = max(dev->data->nb_rx_queues, dev->data->nb_tx_queues);
2065 return TXGBE_NB_HW_STATS +
2066 TXGBE_NB_UP_STATS * TXGBE_MAX_UP +
2067 TXGBE_NB_QP_STATS * nb_queues;
2071 txgbe_get_name_by_id(uint32_t id, char *name, uint32_t size)
2075 /* Extended stats from txgbe_hw_stats */
2076 if (id < TXGBE_NB_HW_STATS) {
2077 snprintf(name, size, "[hw]%s",
2078 rte_txgbe_stats_strings[id].name);
2081 id -= TXGBE_NB_HW_STATS;
2083 /* Priority Stats */
2084 if (id < TXGBE_NB_UP_STATS * TXGBE_MAX_UP) {
2085 nb = id / TXGBE_NB_UP_STATS;
2086 st = id % TXGBE_NB_UP_STATS;
2087 snprintf(name, size, "[p%u]%s", nb,
2088 rte_txgbe_up_strings[st].name);
2091 id -= TXGBE_NB_UP_STATS * TXGBE_MAX_UP;
2094 if (id < TXGBE_NB_QP_STATS * TXGBE_MAX_QP) {
2095 nb = id / TXGBE_NB_QP_STATS;
2096 st = id % TXGBE_NB_QP_STATS;
2097 snprintf(name, size, "[q%u]%s", nb,
2098 rte_txgbe_qp_strings[st].name);
2101 id -= TXGBE_NB_QP_STATS * TXGBE_MAX_QP;
2103 return -(int)(id + 1);
2107 txgbe_get_offset_by_id(uint32_t id, uint32_t *offset)
2111 /* Extended stats from txgbe_hw_stats */
2112 if (id < TXGBE_NB_HW_STATS) {
2113 *offset = rte_txgbe_stats_strings[id].offset;
2116 id -= TXGBE_NB_HW_STATS;
2118 /* Priority Stats */
2119 if (id < TXGBE_NB_UP_STATS * TXGBE_MAX_UP) {
2120 nb = id / TXGBE_NB_UP_STATS;
2121 st = id % TXGBE_NB_UP_STATS;
2122 *offset = rte_txgbe_up_strings[st].offset +
2123 nb * (TXGBE_NB_UP_STATS * sizeof(uint64_t));
2126 id -= TXGBE_NB_UP_STATS * TXGBE_MAX_UP;
2129 if (id < TXGBE_NB_QP_STATS * TXGBE_MAX_QP) {
2130 nb = id / TXGBE_NB_QP_STATS;
2131 st = id % TXGBE_NB_QP_STATS;
2132 *offset = rte_txgbe_qp_strings[st].offset +
2133 nb * (TXGBE_NB_QP_STATS * sizeof(uint64_t));
2136 id -= TXGBE_NB_QP_STATS * TXGBE_MAX_QP;
2138 return -(int)(id + 1);
2141 static int txgbe_dev_xstats_get_names(struct rte_eth_dev *dev,
2142 struct rte_eth_xstat_name *xstats_names, unsigned int limit)
2144 unsigned int i, count;
2146 count = txgbe_xstats_calc_num(dev);
2147 if (xstats_names == NULL)
2150 /* Note: limit >= cnt_stats checked upstream
2151 * in rte_eth_xstats_names()
2153 limit = min(limit, count);
2155 /* Extended stats from txgbe_hw_stats */
2156 for (i = 0; i < limit; i++) {
2157 if (txgbe_get_name_by_id(i, xstats_names[i].name,
2158 sizeof(xstats_names[i].name))) {
2159 PMD_INIT_LOG(WARNING, "id value %d isn't valid", i);
2167 static int txgbe_dev_xstats_get_names_by_id(struct rte_eth_dev *dev,
2168 struct rte_eth_xstat_name *xstats_names,
2169 const uint64_t *ids,
2175 return txgbe_dev_xstats_get_names(dev, xstats_names, limit);
2177 for (i = 0; i < limit; i++) {
2178 if (txgbe_get_name_by_id(ids[i], xstats_names[i].name,
2179 sizeof(xstats_names[i].name))) {
2180 PMD_INIT_LOG(WARNING, "id value %d isn't valid", i);
2189 txgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2192 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2193 struct txgbe_hw_stats *hw_stats = TXGBE_DEV_STATS(dev);
2194 unsigned int i, count;
2196 txgbe_read_stats_registers(hw, hw_stats);
2198 /* If this is a reset xstats is NULL, and we have cleared the
2199 * registers by reading them.
2201 count = txgbe_xstats_calc_num(dev);
2205 limit = min(limit, txgbe_xstats_calc_num(dev));
2207 /* Extended stats from txgbe_hw_stats */
2208 for (i = 0; i < limit; i++) {
2209 uint32_t offset = 0;
2211 if (txgbe_get_offset_by_id(i, &offset)) {
2212 PMD_INIT_LOG(WARNING, "id value %d isn't valid", i);
2215 xstats[i].value = *(uint64_t *)(((char *)hw_stats) + offset);
2223 txgbe_dev_xstats_get_(struct rte_eth_dev *dev, uint64_t *values,
2226 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2227 struct txgbe_hw_stats *hw_stats = TXGBE_DEV_STATS(dev);
2228 unsigned int i, count;
2230 txgbe_read_stats_registers(hw, hw_stats);
2232 /* If this is a reset xstats is NULL, and we have cleared the
2233 * registers by reading them.
2235 count = txgbe_xstats_calc_num(dev);
2239 limit = min(limit, txgbe_xstats_calc_num(dev));
2241 /* Extended stats from txgbe_hw_stats */
2242 for (i = 0; i < limit; i++) {
2245 if (txgbe_get_offset_by_id(i, &offset)) {
2246 PMD_INIT_LOG(WARNING, "id value %d isn't valid", i);
2249 values[i] = *(uint64_t *)(((char *)hw_stats) + offset);
2256 txgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
2257 uint64_t *values, unsigned int limit)
2259 struct txgbe_hw_stats *hw_stats = TXGBE_DEV_STATS(dev);
2263 return txgbe_dev_xstats_get_(dev, values, limit);
2265 for (i = 0; i < limit; i++) {
2268 if (txgbe_get_offset_by_id(ids[i], &offset)) {
2269 PMD_INIT_LOG(WARNING, "id value %d isn't valid", i);
2272 values[i] = *(uint64_t *)(((char *)hw_stats) + offset);
2279 txgbe_dev_xstats_reset(struct rte_eth_dev *dev)
2281 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2282 struct txgbe_hw_stats *hw_stats = TXGBE_DEV_STATS(dev);
2284 /* HW registers are cleared on read */
2285 hw->offset_loaded = 0;
2286 txgbe_read_stats_registers(hw, hw_stats);
2287 hw->offset_loaded = 1;
2289 /* Reset software totals */
2290 memset(hw_stats, 0, sizeof(*hw_stats));
2296 txgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
2298 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2299 u16 eeprom_verh, eeprom_verl;
2303 hw->rom.readw_sw(hw, TXGBE_EEPROM_VERSION_H, &eeprom_verh);
2304 hw->rom.readw_sw(hw, TXGBE_EEPROM_VERSION_L, &eeprom_verl);
2306 etrack_id = (eeprom_verh << 16) | eeprom_verl;
2307 ret = snprintf(fw_version, fw_size, "0x%08x", etrack_id);
2309 ret += 1; /* add the size of '\0' */
2310 if (fw_size < (u32)ret)
2317 txgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2319 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2320 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2322 dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
2323 dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
2324 dev_info->min_rx_bufsize = 1024;
2325 dev_info->max_rx_pktlen = 15872;
2326 dev_info->max_mac_addrs = hw->mac.num_rar_entries;
2327 dev_info->max_hash_mac_addrs = TXGBE_VMDQ_NUM_UC_MAC;
2328 dev_info->max_vfs = pci_dev->max_vfs;
2329 dev_info->max_vmdq_pools = ETH_64_POOLS;
2330 dev_info->vmdq_queue_num = dev_info->max_rx_queues;
2331 dev_info->rx_queue_offload_capa = txgbe_get_rx_queue_offloads(dev);
2332 dev_info->rx_offload_capa = (txgbe_get_rx_port_offloads(dev) |
2333 dev_info->rx_queue_offload_capa);
2334 dev_info->tx_queue_offload_capa = txgbe_get_tx_queue_offloads(dev);
2335 dev_info->tx_offload_capa = txgbe_get_tx_port_offloads(dev);
2337 dev_info->default_rxconf = (struct rte_eth_rxconf) {
2339 .pthresh = TXGBE_DEFAULT_RX_PTHRESH,
2340 .hthresh = TXGBE_DEFAULT_RX_HTHRESH,
2341 .wthresh = TXGBE_DEFAULT_RX_WTHRESH,
2343 .rx_free_thresh = TXGBE_DEFAULT_RX_FREE_THRESH,
2348 dev_info->default_txconf = (struct rte_eth_txconf) {
2350 .pthresh = TXGBE_DEFAULT_TX_PTHRESH,
2351 .hthresh = TXGBE_DEFAULT_TX_HTHRESH,
2352 .wthresh = TXGBE_DEFAULT_TX_WTHRESH,
2354 .tx_free_thresh = TXGBE_DEFAULT_TX_FREE_THRESH,
2358 dev_info->rx_desc_lim = rx_desc_lim;
2359 dev_info->tx_desc_lim = tx_desc_lim;
2361 dev_info->hash_key_size = TXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
2362 dev_info->reta_size = ETH_RSS_RETA_SIZE_128;
2363 dev_info->flow_type_rss_offloads = TXGBE_RSS_OFFLOAD_ALL;
2365 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
2366 dev_info->speed_capa |= ETH_LINK_SPEED_100M;
2368 /* Driver-preferred Rx/Tx parameters */
2369 dev_info->default_rxportconf.burst_size = 32;
2370 dev_info->default_txportconf.burst_size = 32;
2371 dev_info->default_rxportconf.nb_queues = 1;
2372 dev_info->default_txportconf.nb_queues = 1;
2373 dev_info->default_rxportconf.ring_size = 256;
2374 dev_info->default_txportconf.ring_size = 256;
2380 txgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev)
2382 if (dev->rx_pkt_burst == txgbe_recv_pkts ||
2383 dev->rx_pkt_burst == txgbe_recv_pkts_lro_single_alloc ||
2384 dev->rx_pkt_burst == txgbe_recv_pkts_lro_bulk_alloc ||
2385 dev->rx_pkt_burst == txgbe_recv_pkts_bulk_alloc)
2386 return txgbe_get_supported_ptypes();
2392 txgbe_dev_setup_link_alarm_handler(void *param)
2394 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2395 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2396 struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);
2398 bool autoneg = false;
2400 speed = hw->phy.autoneg_advertised;
2402 hw->mac.get_link_capabilities(hw, &speed, &autoneg);
2404 hw->mac.setup_link(hw, speed, true);
2406 intr->flags &= ~TXGBE_FLAG_NEED_LINK_CONFIG;
2409 /* return 0 means link status changed, -1 means not changed */
2411 txgbe_dev_link_update_share(struct rte_eth_dev *dev,
2412 int wait_to_complete)
2414 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2415 struct rte_eth_link link;
2416 u32 link_speed = TXGBE_LINK_SPEED_UNKNOWN;
2417 struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);
2422 memset(&link, 0, sizeof(link));
2423 link.link_status = ETH_LINK_DOWN;
2424 link.link_speed = ETH_SPEED_NUM_NONE;
2425 link.link_duplex = ETH_LINK_HALF_DUPLEX;
2426 link.link_autoneg = ETH_LINK_AUTONEG;
2428 hw->mac.get_link_status = true;
2430 if (intr->flags & TXGBE_FLAG_NEED_LINK_CONFIG)
2431 return rte_eth_linkstatus_set(dev, &link);
2433 /* check if it needs to wait to complete, if lsc interrupt is enabled */
2434 if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
2437 err = hw->mac.check_link(hw, &link_speed, &link_up, wait);
2440 link.link_speed = ETH_SPEED_NUM_100M;
2441 link.link_duplex = ETH_LINK_FULL_DUPLEX;
2442 return rte_eth_linkstatus_set(dev, &link);
2446 if (hw->phy.media_type == txgbe_media_type_fiber) {
2447 intr->flags |= TXGBE_FLAG_NEED_LINK_CONFIG;
2448 rte_eal_alarm_set(10,
2449 txgbe_dev_setup_link_alarm_handler, dev);
2451 return rte_eth_linkstatus_set(dev, &link);
2454 intr->flags &= ~TXGBE_FLAG_NEED_LINK_CONFIG;
2455 link.link_status = ETH_LINK_UP;
2456 link.link_duplex = ETH_LINK_FULL_DUPLEX;
2458 switch (link_speed) {
2460 case TXGBE_LINK_SPEED_UNKNOWN:
2461 link.link_duplex = ETH_LINK_FULL_DUPLEX;
2462 link.link_speed = ETH_SPEED_NUM_100M;
2465 case TXGBE_LINK_SPEED_100M_FULL:
2466 link.link_speed = ETH_SPEED_NUM_100M;
2469 case TXGBE_LINK_SPEED_1GB_FULL:
2470 link.link_speed = ETH_SPEED_NUM_1G;
2473 case TXGBE_LINK_SPEED_2_5GB_FULL:
2474 link.link_speed = ETH_SPEED_NUM_2_5G;
2477 case TXGBE_LINK_SPEED_5GB_FULL:
2478 link.link_speed = ETH_SPEED_NUM_5G;
2481 case TXGBE_LINK_SPEED_10GB_FULL:
2482 link.link_speed = ETH_SPEED_NUM_10G;
2486 return rte_eth_linkstatus_set(dev, &link);
2490 txgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
2492 return txgbe_dev_link_update_share(dev, wait_to_complete);
2496 txgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
2498 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2501 fctrl = rd32(hw, TXGBE_PSRCTL);
2502 fctrl |= (TXGBE_PSRCTL_UCP | TXGBE_PSRCTL_MCP);
2503 wr32(hw, TXGBE_PSRCTL, fctrl);
2509 txgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
2511 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2514 fctrl = rd32(hw, TXGBE_PSRCTL);
2515 fctrl &= (~TXGBE_PSRCTL_UCP);
2516 if (dev->data->all_multicast == 1)
2517 fctrl |= TXGBE_PSRCTL_MCP;
2519 fctrl &= (~TXGBE_PSRCTL_MCP);
2520 wr32(hw, TXGBE_PSRCTL, fctrl);
2526 txgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
2528 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2531 fctrl = rd32(hw, TXGBE_PSRCTL);
2532 fctrl |= TXGBE_PSRCTL_MCP;
2533 wr32(hw, TXGBE_PSRCTL, fctrl);
2539 txgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
2541 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2544 if (dev->data->promiscuous == 1)
2545 return 0; /* must remain in all_multicast mode */
2547 fctrl = rd32(hw, TXGBE_PSRCTL);
2548 fctrl &= (~TXGBE_PSRCTL_MCP);
2549 wr32(hw, TXGBE_PSRCTL, fctrl);
2555 * It clears the interrupt causes and enables the interrupt.
2556 * It will be called once only during nic initialized.
2559 * Pointer to struct rte_eth_dev.
2561 * Enable or Disable.
2564 * - On success, zero.
2565 * - On failure, a negative value.
2568 txgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on)
2570 struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);
2572 txgbe_dev_link_status_print(dev);
2574 intr->mask_misc |= TXGBE_ICRMISC_LSC;
2576 intr->mask_misc &= ~TXGBE_ICRMISC_LSC;
2582 * It clears the interrupt causes and enables the interrupt.
2583 * It will be called once only during nic initialized.
2586 * Pointer to struct rte_eth_dev.
2589 * - On success, zero.
2590 * - On failure, a negative value.
2593 txgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
2595 struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);
2597 intr->mask[0] |= TXGBE_ICR_MASK;
2598 intr->mask[1] |= TXGBE_ICR_MASK;
2604 * It clears the interrupt causes and enables the interrupt.
2605 * It will be called once only during nic initialized.
2608 * Pointer to struct rte_eth_dev.
2611 * - On success, zero.
2612 * - On failure, a negative value.
2615 txgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev)
2617 struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);
2619 intr->mask_misc |= TXGBE_ICRMISC_LNKSEC;
2625 * It reads ICR and sets flag (TXGBE_ICRMISC_LSC) for the link_update.
2628 * Pointer to struct rte_eth_dev.
2631 * - On success, zero.
2632 * - On failure, a negative value.
2635 txgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
2638 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2639 struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);
2641 /* clear all cause mask */
2642 txgbe_disable_intr(hw);
2644 /* read-on-clear nic registers here */
2645 eicr = ((u32 *)hw->isb_mem)[TXGBE_ISB_MISC];
2646 PMD_DRV_LOG(DEBUG, "eicr %x", eicr);
2650 /* set flag for async link update */
2651 if (eicr & TXGBE_ICRMISC_LSC)
2652 intr->flags |= TXGBE_FLAG_NEED_LINK_UPDATE;
2654 if (eicr & TXGBE_ICRMISC_VFMBX)
2655 intr->flags |= TXGBE_FLAG_MAILBOX;
2657 if (eicr & TXGBE_ICRMISC_LNKSEC)
2658 intr->flags |= TXGBE_FLAG_MACSEC;
2660 if (eicr & TXGBE_ICRMISC_GPIO)
2661 intr->flags |= TXGBE_FLAG_PHY_INTERRUPT;
2667 * It gets and then prints the link status.
2670 * Pointer to struct rte_eth_dev.
2673 * - On success, zero.
2674 * - On failure, a negative value.
2677 txgbe_dev_link_status_print(struct rte_eth_dev *dev)
2679 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2680 struct rte_eth_link link;
2682 rte_eth_linkstatus_get(dev, &link);
2684 if (link.link_status) {
2685 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
2686 (int)(dev->data->port_id),
2687 (unsigned int)link.link_speed,
2688 link.link_duplex == ETH_LINK_FULL_DUPLEX ?
2689 "full-duplex" : "half-duplex");
2691 PMD_INIT_LOG(INFO, " Port %d: Link Down",
2692 (int)(dev->data->port_id));
2694 PMD_INIT_LOG(DEBUG, "PCI Address: " PCI_PRI_FMT,
2695 pci_dev->addr.domain,
2697 pci_dev->addr.devid,
2698 pci_dev->addr.function);
2702 * It executes link_update after knowing an interrupt occurred.
2705 * Pointer to struct rte_eth_dev.
2708 * - On success, zero.
2709 * - On failure, a negative value.
2712 txgbe_dev_interrupt_action(struct rte_eth_dev *dev,
2713 struct rte_intr_handle *intr_handle)
2715 struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);
2717 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2719 PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
2721 if (intr->flags & TXGBE_FLAG_MAILBOX) {
2722 txgbe_pf_mbx_process(dev);
2723 intr->flags &= ~TXGBE_FLAG_MAILBOX;
2726 if (intr->flags & TXGBE_FLAG_PHY_INTERRUPT) {
2727 hw->phy.handle_lasi(hw);
2728 intr->flags &= ~TXGBE_FLAG_PHY_INTERRUPT;
2731 if (intr->flags & TXGBE_FLAG_NEED_LINK_UPDATE) {
2732 struct rte_eth_link link;
2734 /*get the link status before link update, for predicting later*/
2735 rte_eth_linkstatus_get(dev, &link);
2737 txgbe_dev_link_update(dev, 0);
2740 if (!link.link_status)
2741 /* handle it 1 sec later, wait it being stable */
2742 timeout = TXGBE_LINK_UP_CHECK_TIMEOUT;
2743 /* likely to down */
2745 /* handle it 4 sec later, wait it being stable */
2746 timeout = TXGBE_LINK_DOWN_CHECK_TIMEOUT;
2748 txgbe_dev_link_status_print(dev);
2749 if (rte_eal_alarm_set(timeout * 1000,
2750 txgbe_dev_interrupt_delayed_handler,
2752 PMD_DRV_LOG(ERR, "Error setting alarm");
2754 /* remember original mask */
2755 intr->mask_misc_orig = intr->mask_misc;
2756 /* only disable lsc interrupt */
2757 intr->mask_misc &= ~TXGBE_ICRMISC_LSC;
2761 PMD_DRV_LOG(DEBUG, "enable intr immediately");
2762 txgbe_enable_intr(dev);
2763 rte_intr_enable(intr_handle);
2769 * Interrupt handler which shall be registered for alarm callback for delayed
2770 * handling specific interrupt to wait for the stable nic state. As the
2771 * NIC interrupt state is not stable for txgbe after link is just down,
2772 * it needs to wait 4 seconds to get the stable status.
2775 * Pointer to interrupt handle.
2777 * The address of parameter (struct rte_eth_dev *) registered before.
2783 txgbe_dev_interrupt_delayed_handler(void *param)
2785 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2786 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2787 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2788 struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);
2789 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2792 txgbe_disable_intr(hw);
2794 eicr = ((u32 *)hw->isb_mem)[TXGBE_ISB_MISC];
2795 if (eicr & TXGBE_ICRMISC_VFMBX)
2796 txgbe_pf_mbx_process(dev);
2798 if (intr->flags & TXGBE_FLAG_PHY_INTERRUPT) {
2799 hw->phy.handle_lasi(hw);
2800 intr->flags &= ~TXGBE_FLAG_PHY_INTERRUPT;
2803 if (intr->flags & TXGBE_FLAG_NEED_LINK_UPDATE) {
2804 txgbe_dev_link_update(dev, 0);
2805 intr->flags &= ~TXGBE_FLAG_NEED_LINK_UPDATE;
2806 txgbe_dev_link_status_print(dev);
2807 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC,
2811 if (intr->flags & TXGBE_FLAG_MACSEC) {
2812 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_MACSEC,
2814 intr->flags &= ~TXGBE_FLAG_MACSEC;
2817 /* restore original mask */
2818 intr->mask_misc = intr->mask_misc_orig;
2819 intr->mask_misc_orig = 0;
2821 PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
2822 txgbe_enable_intr(dev);
2823 rte_intr_enable(intr_handle);
2827 * Interrupt handler triggered by NIC for handling
2828 * specific interrupt.
2831 * Pointer to interrupt handle.
2833 * The address of parameter (struct rte_eth_dev *) registered before.
2839 txgbe_dev_interrupt_handler(void *param)
2841 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2843 txgbe_dev_interrupt_get_status(dev);
2844 txgbe_dev_interrupt_action(dev, dev->intr_handle);
2848 txgbe_dev_led_on(struct rte_eth_dev *dev)
2850 struct txgbe_hw *hw;
2852 hw = TXGBE_DEV_HW(dev);
2853 return txgbe_led_on(hw, 4) == 0 ? 0 : -ENOTSUP;
2857 txgbe_dev_led_off(struct rte_eth_dev *dev)
2859 struct txgbe_hw *hw;
2861 hw = TXGBE_DEV_HW(dev);
2862 return txgbe_led_off(hw, 4) == 0 ? 0 : -ENOTSUP;
2866 txgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2868 struct txgbe_hw *hw;
2874 hw = TXGBE_DEV_HW(dev);
2876 fc_conf->pause_time = hw->fc.pause_time;
2877 fc_conf->high_water = hw->fc.high_water[0];
2878 fc_conf->low_water = hw->fc.low_water[0];
2879 fc_conf->send_xon = hw->fc.send_xon;
2880 fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
2883 * Return rx_pause status according to actual setting of
2886 mflcn_reg = rd32(hw, TXGBE_RXFCCFG);
2887 if (mflcn_reg & (TXGBE_RXFCCFG_FC | TXGBE_RXFCCFG_PFC))
2893 * Return tx_pause status according to actual setting of
2896 fccfg_reg = rd32(hw, TXGBE_TXFCCFG);
2897 if (fccfg_reg & (TXGBE_TXFCCFG_FC | TXGBE_TXFCCFG_PFC))
2902 if (rx_pause && tx_pause)
2903 fc_conf->mode = RTE_FC_FULL;
2905 fc_conf->mode = RTE_FC_RX_PAUSE;
2907 fc_conf->mode = RTE_FC_TX_PAUSE;
2909 fc_conf->mode = RTE_FC_NONE;
2915 txgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2917 struct txgbe_hw *hw;
2919 uint32_t rx_buf_size;
2920 uint32_t max_high_water;
2921 enum txgbe_fc_mode rte_fcmode_2_txgbe_fcmode[] = {
2928 PMD_INIT_FUNC_TRACE();
2930 hw = TXGBE_DEV_HW(dev);
2931 rx_buf_size = rd32(hw, TXGBE_PBRXSIZE(0));
2932 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
2935 * At least reserve one Ethernet frame for watermark
2936 * high_water/low_water in kilo bytes for txgbe
2938 max_high_water = (rx_buf_size - RTE_ETHER_MAX_LEN) >> 10;
2939 if (fc_conf->high_water > max_high_water ||
2940 fc_conf->high_water < fc_conf->low_water) {
2941 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
2942 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
2946 hw->fc.requested_mode = rte_fcmode_2_txgbe_fcmode[fc_conf->mode];
2947 hw->fc.pause_time = fc_conf->pause_time;
2948 hw->fc.high_water[0] = fc_conf->high_water;
2949 hw->fc.low_water[0] = fc_conf->low_water;
2950 hw->fc.send_xon = fc_conf->send_xon;
2951 hw->fc.disable_fc_autoneg = !fc_conf->autoneg;
2953 err = txgbe_fc_enable(hw);
2955 /* Not negotiated is not an error case */
2956 if (err == 0 || err == TXGBE_ERR_FC_NOT_NEGOTIATED) {
2957 wr32m(hw, TXGBE_MACRXFLT, TXGBE_MACRXFLT_CTL_MASK,
2958 (fc_conf->mac_ctrl_frame_fwd
2959 ? TXGBE_MACRXFLT_CTL_NOPS : TXGBE_MACRXFLT_CTL_DROP));
2965 PMD_INIT_LOG(ERR, "txgbe_fc_enable = 0x%x", err);
2970 txgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
2971 struct rte_eth_pfc_conf *pfc_conf)
2974 uint32_t rx_buf_size;
2975 uint32_t max_high_water;
2977 uint8_t map[TXGBE_DCB_UP_MAX] = { 0 };
2978 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2979 struct txgbe_dcb_config *dcb_config = TXGBE_DEV_DCB_CONFIG(dev);
2981 enum txgbe_fc_mode rte_fcmode_2_txgbe_fcmode[] = {
2988 PMD_INIT_FUNC_TRACE();
2990 txgbe_dcb_unpack_map_cee(dcb_config, TXGBE_DCB_RX_CONFIG, map);
2991 tc_num = map[pfc_conf->priority];
2992 rx_buf_size = rd32(hw, TXGBE_PBRXSIZE(tc_num));
2993 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
2995 * At least reserve one Ethernet frame for watermark
2996 * high_water/low_water in kilo bytes for txgbe
2998 max_high_water = (rx_buf_size - RTE_ETHER_MAX_LEN) >> 10;
2999 if (pfc_conf->fc.high_water > max_high_water ||
3000 pfc_conf->fc.high_water <= pfc_conf->fc.low_water) {
3001 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
3002 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
3006 hw->fc.requested_mode = rte_fcmode_2_txgbe_fcmode[pfc_conf->fc.mode];
3007 hw->fc.pause_time = pfc_conf->fc.pause_time;
3008 hw->fc.send_xon = pfc_conf->fc.send_xon;
3009 hw->fc.low_water[tc_num] = pfc_conf->fc.low_water;
3010 hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
3012 err = txgbe_dcb_pfc_enable(hw, tc_num);
3014 /* Not negotiated is not an error case */
3015 if (err == 0 || err == TXGBE_ERR_FC_NOT_NEGOTIATED)
3018 PMD_INIT_LOG(ERR, "txgbe_dcb_pfc_enable = 0x%x", err);
3023 txgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
3024 struct rte_eth_rss_reta_entry64 *reta_conf,
3029 uint16_t idx, shift;
3030 struct txgbe_adapter *adapter = TXGBE_DEV_ADAPTER(dev);
3031 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3033 PMD_INIT_FUNC_TRACE();
3035 if (!txgbe_rss_update_sp(hw->mac.type)) {
3036 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this "
3041 if (reta_size != ETH_RSS_RETA_SIZE_128) {
3042 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3043 "(%d) doesn't match the number hardware can supported "
3044 "(%d)", reta_size, ETH_RSS_RETA_SIZE_128);
3048 for (i = 0; i < reta_size; i += 4) {
3049 idx = i / RTE_RETA_GROUP_SIZE;
3050 shift = i % RTE_RETA_GROUP_SIZE;
3051 mask = (uint8_t)RS64(reta_conf[idx].mask, shift, 0xF);
3055 reta = rd32a(hw, TXGBE_REG_RSSTBL, i >> 2);
3056 for (j = 0; j < 4; j++) {
3057 if (RS8(mask, j, 0x1)) {
3058 reta &= ~(MS32(8 * j, 0xFF));
3059 reta |= LS32(reta_conf[idx].reta[shift + j],
3063 wr32a(hw, TXGBE_REG_RSSTBL, i >> 2, reta);
3065 adapter->rss_reta_updated = 1;
3071 txgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
3072 struct rte_eth_rss_reta_entry64 *reta_conf,
3075 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3078 uint16_t idx, shift;
3080 PMD_INIT_FUNC_TRACE();
3082 if (reta_size != ETH_RSS_RETA_SIZE_128) {
3083 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3084 "(%d) doesn't match the number hardware can supported "
3085 "(%d)", reta_size, ETH_RSS_RETA_SIZE_128);
3089 for (i = 0; i < reta_size; i += 4) {
3090 idx = i / RTE_RETA_GROUP_SIZE;
3091 shift = i % RTE_RETA_GROUP_SIZE;
3092 mask = (uint8_t)RS64(reta_conf[idx].mask, shift, 0xF);
3096 reta = rd32a(hw, TXGBE_REG_RSSTBL, i >> 2);
3097 for (j = 0; j < 4; j++) {
3098 if (RS8(mask, j, 0x1))
3099 reta_conf[idx].reta[shift + j] =
3100 (uint16_t)RS32(reta, 8 * j, 0xFF);
3108 txgbe_add_rar(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
3109 uint32_t index, uint32_t pool)
3111 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3112 uint32_t enable_addr = 1;
3114 return txgbe_set_rar(hw, index, mac_addr->addr_bytes,
3119 txgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
3121 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3123 txgbe_clear_rar(hw, index);
3127 txgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *addr)
3129 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3131 txgbe_remove_rar(dev, 0);
3132 txgbe_add_rar(dev, addr, 0, pci_dev->max_vfs);
3138 txgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
3140 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3141 struct rte_eth_dev_info dev_info;
3142 uint32_t frame_size = mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN;
3143 struct rte_eth_dev_data *dev_data = dev->data;
3146 ret = txgbe_dev_info_get(dev, &dev_info);
3150 /* check that mtu is within the allowed range */
3151 if (mtu < RTE_ETHER_MIN_MTU || frame_size > dev_info.max_rx_pktlen)
3154 /* If device is started, refuse mtu that requires the support of
3155 * scattered packets when this feature has not been enabled before.
3157 if (dev_data->dev_started && !dev_data->scattered_rx &&
3158 (frame_size + 2 * TXGBE_VLAN_TAG_SIZE >
3159 dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
3160 PMD_INIT_LOG(ERR, "Stop port first.");
3164 /* update max frame size */
3165 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
3168 wr32m(hw, TXGBE_FRMSZ, TXGBE_FRMSZ_MAX_MASK,
3169 TXGBE_FRAME_SIZE_MAX);
3171 wr32m(hw, TXGBE_FRMSZ, TXGBE_FRMSZ_MAX_MASK,
3172 TXGBE_FRMSZ_MAX(frame_size));
3178 txgbe_uta_vector(struct txgbe_hw *hw, struct rte_ether_addr *uc_addr)
3180 uint32_t vector = 0;
3182 switch (hw->mac.mc_filter_type) {
3183 case 0: /* use bits [47:36] of the address */
3184 vector = ((uc_addr->addr_bytes[4] >> 4) |
3185 (((uint16_t)uc_addr->addr_bytes[5]) << 4));
3187 case 1: /* use bits [46:35] of the address */
3188 vector = ((uc_addr->addr_bytes[4] >> 3) |
3189 (((uint16_t)uc_addr->addr_bytes[5]) << 5));
3191 case 2: /* use bits [45:34] of the address */
3192 vector = ((uc_addr->addr_bytes[4] >> 2) |
3193 (((uint16_t)uc_addr->addr_bytes[5]) << 6));
3195 case 3: /* use bits [43:32] of the address */
3196 vector = ((uc_addr->addr_bytes[4]) |
3197 (((uint16_t)uc_addr->addr_bytes[5]) << 8));
3199 default: /* Invalid mc_filter_type */
3203 /* vector can only be 12-bits or boundary will be exceeded */
3209 txgbe_uc_hash_table_set(struct rte_eth_dev *dev,
3210 struct rte_ether_addr *mac_addr, uint8_t on)
3218 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3219 struct txgbe_uta_info *uta_info = TXGBE_DEV_UTA_INFO(dev);
3221 /* The UTA table only exists on pf hardware */
3222 if (hw->mac.type < txgbe_mac_raptor)
3225 vector = txgbe_uta_vector(hw, mac_addr);
3226 uta_idx = (vector >> 5) & 0x7F;
3227 uta_mask = 0x1UL << (vector & 0x1F);
3229 if (!!on == !!(uta_info->uta_shadow[uta_idx] & uta_mask))
3232 reg_val = rd32(hw, TXGBE_UCADDRTBL(uta_idx));
3234 uta_info->uta_in_use++;
3235 reg_val |= uta_mask;
3236 uta_info->uta_shadow[uta_idx] |= uta_mask;
3238 uta_info->uta_in_use--;
3239 reg_val &= ~uta_mask;
3240 uta_info->uta_shadow[uta_idx] &= ~uta_mask;
3243 wr32(hw, TXGBE_UCADDRTBL(uta_idx), reg_val);
3245 psrctl = rd32(hw, TXGBE_PSRCTL);
3246 if (uta_info->uta_in_use > 0)
3247 psrctl |= TXGBE_PSRCTL_UCHFENA;
3249 psrctl &= ~TXGBE_PSRCTL_UCHFENA;
3251 psrctl &= ~TXGBE_PSRCTL_ADHF12_MASK;
3252 psrctl |= TXGBE_PSRCTL_ADHF12(hw->mac.mc_filter_type);
3253 wr32(hw, TXGBE_PSRCTL, psrctl);
3259 txgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
3261 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3262 struct txgbe_uta_info *uta_info = TXGBE_DEV_UTA_INFO(dev);
3266 /* The UTA table only exists on pf hardware */
3267 if (hw->mac.type < txgbe_mac_raptor)
3271 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
3272 uta_info->uta_shadow[i] = ~0;
3273 wr32(hw, TXGBE_UCADDRTBL(i), ~0);
3276 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
3277 uta_info->uta_shadow[i] = 0;
3278 wr32(hw, TXGBE_UCADDRTBL(i), 0);
3282 psrctl = rd32(hw, TXGBE_PSRCTL);
3284 psrctl |= TXGBE_PSRCTL_UCHFENA;
3286 psrctl &= ~TXGBE_PSRCTL_UCHFENA;
3288 psrctl &= ~TXGBE_PSRCTL_ADHF12_MASK;
3289 psrctl |= TXGBE_PSRCTL_ADHF12(hw->mac.mc_filter_type);
3290 wr32(hw, TXGBE_PSRCTL, psrctl);
3296 txgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
3298 uint32_t new_val = orig_val;
3300 if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
3301 new_val |= TXGBE_POOLETHCTL_UTA;
3302 if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
3303 new_val |= TXGBE_POOLETHCTL_MCHA;
3304 if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
3305 new_val |= TXGBE_POOLETHCTL_UCHA;
3306 if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
3307 new_val |= TXGBE_POOLETHCTL_BCA;
3308 if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
3309 new_val |= TXGBE_POOLETHCTL_MCP;
3315 txgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
3317 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3318 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3320 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3322 if (queue_id < 32) {
3323 mask = rd32(hw, TXGBE_IMS(0));
3324 mask &= (1 << queue_id);
3325 wr32(hw, TXGBE_IMS(0), mask);
3326 } else if (queue_id < 64) {
3327 mask = rd32(hw, TXGBE_IMS(1));
3328 mask &= (1 << (queue_id - 32));
3329 wr32(hw, TXGBE_IMS(1), mask);
3331 rte_intr_enable(intr_handle);
3337 txgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
3340 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3342 if (queue_id < 32) {
3343 mask = rd32(hw, TXGBE_IMS(0));
3344 mask &= ~(1 << queue_id);
3345 wr32(hw, TXGBE_IMS(0), mask);
3346 } else if (queue_id < 64) {
3347 mask = rd32(hw, TXGBE_IMS(1));
3348 mask &= ~(1 << (queue_id - 32));
3349 wr32(hw, TXGBE_IMS(1), mask);
3356 * set the IVAR registers, mapping interrupt causes to vectors
3358 * pointer to txgbe_hw struct
3360 * 0 for Rx, 1 for Tx, -1 for other causes
3362 * queue to map the corresponding interrupt to
3364 * the vector to map to the corresponding queue
3367 txgbe_set_ivar_map(struct txgbe_hw *hw, int8_t direction,
3368 uint8_t queue, uint8_t msix_vector)
3372 if (direction == -1) {
3374 msix_vector |= TXGBE_IVARMISC_VLD;
3376 tmp = rd32(hw, TXGBE_IVARMISC);
3377 tmp &= ~(0xFF << idx);
3378 tmp |= (msix_vector << idx);
3379 wr32(hw, TXGBE_IVARMISC, tmp);
3381 /* rx or tx causes */
3382 /* Workround for ICR lost */
3383 idx = ((16 * (queue & 1)) + (8 * direction));
3384 tmp = rd32(hw, TXGBE_IVAR(queue >> 1));
3385 tmp &= ~(0xFF << idx);
3386 tmp |= (msix_vector << idx);
3387 wr32(hw, TXGBE_IVAR(queue >> 1), tmp);
3392 * Sets up the hardware to properly generate MSI-X interrupts
3394 * board private structure
3397 txgbe_configure_msix(struct rte_eth_dev *dev)
3399 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3400 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3401 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3402 uint32_t queue_id, base = TXGBE_MISC_VEC_ID;
3403 uint32_t vec = TXGBE_MISC_VEC_ID;
3406 /* won't configure msix register if no mapping is done
3407 * between intr vector and event fd
3408 * but if misx has been enabled already, need to configure
3409 * auto clean, auto mask and throttling.
3411 gpie = rd32(hw, TXGBE_GPIE);
3412 if (!rte_intr_dp_is_en(intr_handle) &&
3413 !(gpie & TXGBE_GPIE_MSIX))
3416 if (rte_intr_allow_others(intr_handle)) {
3417 base = TXGBE_RX_VEC_START;
3421 /* setup GPIE for MSI-x mode */
3422 gpie = rd32(hw, TXGBE_GPIE);
3423 gpie |= TXGBE_GPIE_MSIX;
3424 wr32(hw, TXGBE_GPIE, gpie);
3426 /* Populate the IVAR table and set the ITR values to the
3427 * corresponding register.
3429 if (rte_intr_dp_is_en(intr_handle)) {
3430 for (queue_id = 0; queue_id < dev->data->nb_rx_queues;
3432 /* by default, 1:1 mapping */
3433 txgbe_set_ivar_map(hw, 0, queue_id, vec);
3434 intr_handle->intr_vec[queue_id] = vec;
3435 if (vec < base + intr_handle->nb_efd - 1)
3439 txgbe_set_ivar_map(hw, -1, 1, TXGBE_MISC_VEC_ID);
3441 wr32(hw, TXGBE_ITR(TXGBE_MISC_VEC_ID),
3442 TXGBE_ITR_IVAL_10G(TXGBE_QUEUE_ITR_INTERVAL_DEFAULT)
3447 txgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
3448 uint16_t queue_idx, uint16_t tx_rate)
3450 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3453 if (queue_idx >= hw->mac.max_tx_queues)
3457 bcnrc_val = TXGBE_ARBTXRATE_MAX(tx_rate);
3458 bcnrc_val |= TXGBE_ARBTXRATE_MIN(tx_rate / 2);
3464 * Set global transmit compensation time to the MMW_SIZE in ARBTXMMW
3465 * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported.
3467 wr32(hw, TXGBE_ARBTXMMW, 0x14);
3469 /* Set ARBTXRATE of queue X */
3470 wr32(hw, TXGBE_ARBPOOLIDX, queue_idx);
3471 wr32(hw, TXGBE_ARBTXRATE, bcnrc_val);
3478 txgbe_dev_addr_list_itr(__rte_unused struct txgbe_hw *hw,
3479 u8 **mc_addr_ptr, u32 *vmdq)
3484 mc_addr = *mc_addr_ptr;
3485 *mc_addr_ptr = (mc_addr + sizeof(struct rte_ether_addr));
3490 txgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
3491 struct rte_ether_addr *mc_addr_set,
3492 uint32_t nb_mc_addr)
3494 struct txgbe_hw *hw;
3497 hw = TXGBE_DEV_HW(dev);
3498 mc_addr_list = (u8 *)mc_addr_set;
3499 return txgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
3500 txgbe_dev_addr_list_itr, TRUE);
3504 txgbe_read_systime_cyclecounter(struct rte_eth_dev *dev)
3506 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3507 uint64_t systime_cycles;
3509 systime_cycles = (uint64_t)rd32(hw, TXGBE_TSTIMEL);
3510 systime_cycles |= (uint64_t)rd32(hw, TXGBE_TSTIMEH) << 32;
3512 return systime_cycles;
3516 txgbe_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
3518 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3519 uint64_t rx_tstamp_cycles;
3521 /* TSRXSTMPL stores ns and TSRXSTMPH stores seconds. */
3522 rx_tstamp_cycles = (uint64_t)rd32(hw, TXGBE_TSRXSTMPL);
3523 rx_tstamp_cycles |= (uint64_t)rd32(hw, TXGBE_TSRXSTMPH) << 32;
3525 return rx_tstamp_cycles;
3529 txgbe_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
3531 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3532 uint64_t tx_tstamp_cycles;
3534 /* TSTXSTMPL stores ns and TSTXSTMPH stores seconds. */
3535 tx_tstamp_cycles = (uint64_t)rd32(hw, TXGBE_TSTXSTMPL);
3536 tx_tstamp_cycles |= (uint64_t)rd32(hw, TXGBE_TSTXSTMPH) << 32;
3538 return tx_tstamp_cycles;
3542 txgbe_start_timecounters(struct rte_eth_dev *dev)
3544 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3545 struct txgbe_adapter *adapter = TXGBE_DEV_ADAPTER(dev);
3546 struct rte_eth_link link;
3547 uint32_t incval = 0;
3550 /* Get current link speed. */
3551 txgbe_dev_link_update(dev, 1);
3552 rte_eth_linkstatus_get(dev, &link);
3554 switch (link.link_speed) {
3555 case ETH_SPEED_NUM_100M:
3556 incval = TXGBE_INCVAL_100;
3557 shift = TXGBE_INCVAL_SHIFT_100;
3559 case ETH_SPEED_NUM_1G:
3560 incval = TXGBE_INCVAL_1GB;
3561 shift = TXGBE_INCVAL_SHIFT_1GB;
3563 case ETH_SPEED_NUM_10G:
3565 incval = TXGBE_INCVAL_10GB;
3566 shift = TXGBE_INCVAL_SHIFT_10GB;
3570 wr32(hw, TXGBE_TSTIMEINC, TXGBE_TSTIMEINC_VP(incval, 2));
3572 memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
3573 memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3574 memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3576 adapter->systime_tc.cc_mask = TXGBE_CYCLECOUNTER_MASK;
3577 adapter->systime_tc.cc_shift = shift;
3578 adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
3580 adapter->rx_tstamp_tc.cc_mask = TXGBE_CYCLECOUNTER_MASK;
3581 adapter->rx_tstamp_tc.cc_shift = shift;
3582 adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3584 adapter->tx_tstamp_tc.cc_mask = TXGBE_CYCLECOUNTER_MASK;
3585 adapter->tx_tstamp_tc.cc_shift = shift;
3586 adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3590 txgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
3592 struct txgbe_adapter *adapter = TXGBE_DEV_ADAPTER(dev);
3594 adapter->systime_tc.nsec += delta;
3595 adapter->rx_tstamp_tc.nsec += delta;
3596 adapter->tx_tstamp_tc.nsec += delta;
3602 txgbe_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
3605 struct txgbe_adapter *adapter = TXGBE_DEV_ADAPTER(dev);
3607 ns = rte_timespec_to_ns(ts);
3608 /* Set the timecounters to a new value. */
3609 adapter->systime_tc.nsec = ns;
3610 adapter->rx_tstamp_tc.nsec = ns;
3611 adapter->tx_tstamp_tc.nsec = ns;
3617 txgbe_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
3619 uint64_t ns, systime_cycles;
3620 struct txgbe_adapter *adapter = TXGBE_DEV_ADAPTER(dev);
3622 systime_cycles = txgbe_read_systime_cyclecounter(dev);
3623 ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
3624 *ts = rte_ns_to_timespec(ns);
3630 txgbe_timesync_enable(struct rte_eth_dev *dev)
3632 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3635 /* Stop the timesync system time. */
3636 wr32(hw, TXGBE_TSTIMEINC, 0x0);
3637 /* Reset the timesync system time value. */
3638 wr32(hw, TXGBE_TSTIMEL, 0x0);
3639 wr32(hw, TXGBE_TSTIMEH, 0x0);
3641 txgbe_start_timecounters(dev);
3643 /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
3644 wr32(hw, TXGBE_ETFLT(TXGBE_ETF_ID_1588),
3645 RTE_ETHER_TYPE_1588 | TXGBE_ETFLT_ENA | TXGBE_ETFLT_1588);
3647 /* Enable timestamping of received PTP packets. */
3648 tsync_ctl = rd32(hw, TXGBE_TSRXCTL);
3649 tsync_ctl |= TXGBE_TSRXCTL_ENA;
3650 wr32(hw, TXGBE_TSRXCTL, tsync_ctl);
3652 /* Enable timestamping of transmitted PTP packets. */
3653 tsync_ctl = rd32(hw, TXGBE_TSTXCTL);
3654 tsync_ctl |= TXGBE_TSTXCTL_ENA;
3655 wr32(hw, TXGBE_TSTXCTL, tsync_ctl);
3663 txgbe_timesync_disable(struct rte_eth_dev *dev)
3665 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3668 /* Disable timestamping of transmitted PTP packets. */
3669 tsync_ctl = rd32(hw, TXGBE_TSTXCTL);
3670 tsync_ctl &= ~TXGBE_TSTXCTL_ENA;
3671 wr32(hw, TXGBE_TSTXCTL, tsync_ctl);
3673 /* Disable timestamping of received PTP packets. */
3674 tsync_ctl = rd32(hw, TXGBE_TSRXCTL);
3675 tsync_ctl &= ~TXGBE_TSRXCTL_ENA;
3676 wr32(hw, TXGBE_TSRXCTL, tsync_ctl);
3678 /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
3679 wr32(hw, TXGBE_ETFLT(TXGBE_ETF_ID_1588), 0);
3681 /* Stop incrementating the System Time registers. */
3682 wr32(hw, TXGBE_TSTIMEINC, 0);
3688 txgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
3689 struct timespec *timestamp,
3690 uint32_t flags __rte_unused)
3692 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3693 struct txgbe_adapter *adapter = TXGBE_DEV_ADAPTER(dev);
3694 uint32_t tsync_rxctl;
3695 uint64_t rx_tstamp_cycles;
3698 tsync_rxctl = rd32(hw, TXGBE_TSRXCTL);
3699 if ((tsync_rxctl & TXGBE_TSRXCTL_VLD) == 0)
3702 rx_tstamp_cycles = txgbe_read_rx_tstamp_cyclecounter(dev);
3703 ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
3704 *timestamp = rte_ns_to_timespec(ns);
3710 txgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
3711 struct timespec *timestamp)
3713 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3714 struct txgbe_adapter *adapter = TXGBE_DEV_ADAPTER(dev);
3715 uint32_t tsync_txctl;
3716 uint64_t tx_tstamp_cycles;
3719 tsync_txctl = rd32(hw, TXGBE_TSTXCTL);
3720 if ((tsync_txctl & TXGBE_TSTXCTL_VLD) == 0)
3723 tx_tstamp_cycles = txgbe_read_tx_tstamp_cyclecounter(dev);
3724 ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
3725 *timestamp = rte_ns_to_timespec(ns);
3731 txgbe_get_reg_length(struct rte_eth_dev *dev __rte_unused)
3735 const struct reg_info *reg_group;
3736 const struct reg_info **reg_set = txgbe_regs_others;
3738 while ((reg_group = reg_set[g_ind++]))
3739 count += txgbe_regs_group_count(reg_group);
3745 txgbe_get_regs(struct rte_eth_dev *dev,
3746 struct rte_dev_reg_info *regs)
3748 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3749 uint32_t *data = regs->data;
3752 const struct reg_info *reg_group;
3753 const struct reg_info **reg_set = txgbe_regs_others;
3756 regs->length = txgbe_get_reg_length(dev);
3757 regs->width = sizeof(uint32_t);
3761 /* Support only full register dump */
3762 if (regs->length == 0 ||
3763 regs->length == (uint32_t)txgbe_get_reg_length(dev)) {
3764 regs->version = hw->mac.type << 24 |
3765 hw->revision_id << 16 |
3767 while ((reg_group = reg_set[g_ind++]))
3768 count += txgbe_read_regs_group(dev, &data[count],
3777 txgbe_get_eeprom_length(struct rte_eth_dev *dev)
3779 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3781 /* Return unit is byte count */
3782 return hw->rom.word_size * 2;
3786 txgbe_get_eeprom(struct rte_eth_dev *dev,
3787 struct rte_dev_eeprom_info *in_eeprom)
3789 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3790 struct txgbe_rom_info *eeprom = &hw->rom;
3791 uint16_t *data = in_eeprom->data;
3794 first = in_eeprom->offset >> 1;
3795 length = in_eeprom->length >> 1;
3796 if (first > hw->rom.word_size ||
3797 ((first + length) > hw->rom.word_size))
3800 in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
3802 return eeprom->readw_buffer(hw, first, length, data);
3806 txgbe_set_eeprom(struct rte_eth_dev *dev,
3807 struct rte_dev_eeprom_info *in_eeprom)
3809 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3810 struct txgbe_rom_info *eeprom = &hw->rom;
3811 uint16_t *data = in_eeprom->data;
3814 first = in_eeprom->offset >> 1;
3815 length = in_eeprom->length >> 1;
3816 if (first > hw->rom.word_size ||
3817 ((first + length) > hw->rom.word_size))
3820 in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
3822 return eeprom->writew_buffer(hw, first, length, data);
3826 txgbe_get_module_info(struct rte_eth_dev *dev,
3827 struct rte_eth_dev_module_info *modinfo)
3829 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3831 uint8_t sff8472_rev, addr_mode;
3832 bool page_swap = false;
3834 /* Check whether we support SFF-8472 or not */
3835 status = hw->phy.read_i2c_eeprom(hw,
3836 TXGBE_SFF_SFF_8472_COMP,
3841 /* addressing mode is not supported */
3842 status = hw->phy.read_i2c_eeprom(hw,
3843 TXGBE_SFF_SFF_8472_SWAP,
3848 if (addr_mode & TXGBE_SFF_ADDRESSING_MODE) {
3850 "Address change required to access page 0xA2, "
3851 "but not supported. Please report the module "
3852 "type to the driver maintainers.");
3856 if (sff8472_rev == TXGBE_SFF_SFF_8472_UNSUP || page_swap) {
3857 /* We have a SFP, but it does not support SFF-8472 */
3858 modinfo->type = RTE_ETH_MODULE_SFF_8079;
3859 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
3861 /* We have a SFP which supports a revision of SFF-8472. */
3862 modinfo->type = RTE_ETH_MODULE_SFF_8472;
3863 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
3870 txgbe_get_module_eeprom(struct rte_eth_dev *dev,
3871 struct rte_dev_eeprom_info *info)
3873 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3874 uint32_t status = TXGBE_ERR_PHY_ADDR_INVALID;
3875 uint8_t databyte = 0xFF;
3876 uint8_t *data = info->data;
3879 if (info->length == 0)
3882 for (i = info->offset; i < info->offset + info->length; i++) {
3883 if (i < RTE_ETH_MODULE_SFF_8079_LEN)
3884 status = hw->phy.read_i2c_eeprom(hw, i, &databyte);
3886 status = hw->phy.read_i2c_sff8472(hw, i, &databyte);
3891 data[i - info->offset] = databyte;
3898 txgbe_rss_update_sp(enum txgbe_mac_type mac_type)
3901 case txgbe_mac_raptor:
3909 txgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
3910 struct rte_eth_dcb_info *dcb_info)
3912 struct txgbe_dcb_config *dcb_config = TXGBE_DEV_DCB_CONFIG(dev);
3913 struct txgbe_dcb_tc_config *tc;
3914 struct rte_eth_dcb_tc_queue_mapping *tc_queue;
3918 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
3919 dcb_info->nb_tcs = dcb_config->num_tcs.pg_tcs;
3921 dcb_info->nb_tcs = 1;
3923 tc_queue = &dcb_info->tc_queue;
3924 nb_tcs = dcb_info->nb_tcs;
3926 if (dcb_config->vt_mode) { /* vt is enabled */
3927 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
3928 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
3929 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
3930 dcb_info->prio_tc[i] = vmdq_rx_conf->dcb_tc[i];
3931 if (RTE_ETH_DEV_SRIOV(dev).active > 0) {
3932 for (j = 0; j < nb_tcs; j++) {
3933 tc_queue->tc_rxq[0][j].base = j;
3934 tc_queue->tc_rxq[0][j].nb_queue = 1;
3935 tc_queue->tc_txq[0][j].base = j;
3936 tc_queue->tc_txq[0][j].nb_queue = 1;
3939 for (i = 0; i < vmdq_rx_conf->nb_queue_pools; i++) {
3940 for (j = 0; j < nb_tcs; j++) {
3941 tc_queue->tc_rxq[i][j].base =
3943 tc_queue->tc_rxq[i][j].nb_queue = 1;
3944 tc_queue->tc_txq[i][j].base =
3946 tc_queue->tc_txq[i][j].nb_queue = 1;
3950 } else { /* vt is disabled */
3951 struct rte_eth_dcb_rx_conf *rx_conf =
3952 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
3953 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
3954 dcb_info->prio_tc[i] = rx_conf->dcb_tc[i];
3955 if (dcb_info->nb_tcs == ETH_4_TCS) {
3956 for (i = 0; i < dcb_info->nb_tcs; i++) {
3957 dcb_info->tc_queue.tc_rxq[0][i].base = i * 32;
3958 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
3960 dcb_info->tc_queue.tc_txq[0][0].base = 0;
3961 dcb_info->tc_queue.tc_txq[0][1].base = 64;
3962 dcb_info->tc_queue.tc_txq[0][2].base = 96;
3963 dcb_info->tc_queue.tc_txq[0][3].base = 112;
3964 dcb_info->tc_queue.tc_txq[0][0].nb_queue = 64;
3965 dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
3966 dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
3967 dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
3968 } else if (dcb_info->nb_tcs == ETH_8_TCS) {
3969 for (i = 0; i < dcb_info->nb_tcs; i++) {
3970 dcb_info->tc_queue.tc_rxq[0][i].base = i * 16;
3971 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
3973 dcb_info->tc_queue.tc_txq[0][0].base = 0;
3974 dcb_info->tc_queue.tc_txq[0][1].base = 32;
3975 dcb_info->tc_queue.tc_txq[0][2].base = 64;
3976 dcb_info->tc_queue.tc_txq[0][3].base = 80;
3977 dcb_info->tc_queue.tc_txq[0][4].base = 96;
3978 dcb_info->tc_queue.tc_txq[0][5].base = 104;
3979 dcb_info->tc_queue.tc_txq[0][6].base = 112;
3980 dcb_info->tc_queue.tc_txq[0][7].base = 120;
3981 dcb_info->tc_queue.tc_txq[0][0].nb_queue = 32;
3982 dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
3983 dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
3984 dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
3985 dcb_info->tc_queue.tc_txq[0][4].nb_queue = 8;
3986 dcb_info->tc_queue.tc_txq[0][5].nb_queue = 8;
3987 dcb_info->tc_queue.tc_txq[0][6].nb_queue = 8;
3988 dcb_info->tc_queue.tc_txq[0][7].nb_queue = 8;
3991 for (i = 0; i < dcb_info->nb_tcs; i++) {
3992 tc = &dcb_config->tc_config[i];
3993 dcb_info->tc_bws[i] = tc->path[TXGBE_DCB_TX_CONFIG].bwg_percent;
3998 static const struct eth_dev_ops txgbe_eth_dev_ops = {
3999 .dev_configure = txgbe_dev_configure,
4000 .dev_infos_get = txgbe_dev_info_get,
4001 .dev_start = txgbe_dev_start,
4002 .dev_stop = txgbe_dev_stop,
4003 .dev_set_link_up = txgbe_dev_set_link_up,
4004 .dev_set_link_down = txgbe_dev_set_link_down,
4005 .dev_close = txgbe_dev_close,
4006 .dev_reset = txgbe_dev_reset,
4007 .promiscuous_enable = txgbe_dev_promiscuous_enable,
4008 .promiscuous_disable = txgbe_dev_promiscuous_disable,
4009 .allmulticast_enable = txgbe_dev_allmulticast_enable,
4010 .allmulticast_disable = txgbe_dev_allmulticast_disable,
4011 .link_update = txgbe_dev_link_update,
4012 .stats_get = txgbe_dev_stats_get,
4013 .xstats_get = txgbe_dev_xstats_get,
4014 .xstats_get_by_id = txgbe_dev_xstats_get_by_id,
4015 .stats_reset = txgbe_dev_stats_reset,
4016 .xstats_reset = txgbe_dev_xstats_reset,
4017 .xstats_get_names = txgbe_dev_xstats_get_names,
4018 .xstats_get_names_by_id = txgbe_dev_xstats_get_names_by_id,
4019 .queue_stats_mapping_set = txgbe_dev_queue_stats_mapping_set,
4020 .fw_version_get = txgbe_fw_version_get,
4021 .dev_supported_ptypes_get = txgbe_dev_supported_ptypes_get,
4022 .mtu_set = txgbe_dev_mtu_set,
4023 .vlan_filter_set = txgbe_vlan_filter_set,
4024 .vlan_tpid_set = txgbe_vlan_tpid_set,
4025 .vlan_offload_set = txgbe_vlan_offload_set,
4026 .vlan_strip_queue_set = txgbe_vlan_strip_queue_set,
4027 .rx_queue_start = txgbe_dev_rx_queue_start,
4028 .rx_queue_stop = txgbe_dev_rx_queue_stop,
4029 .tx_queue_start = txgbe_dev_tx_queue_start,
4030 .tx_queue_stop = txgbe_dev_tx_queue_stop,
4031 .rx_queue_setup = txgbe_dev_rx_queue_setup,
4032 .rx_queue_intr_enable = txgbe_dev_rx_queue_intr_enable,
4033 .rx_queue_intr_disable = txgbe_dev_rx_queue_intr_disable,
4034 .rx_queue_release = txgbe_dev_rx_queue_release,
4035 .tx_queue_setup = txgbe_dev_tx_queue_setup,
4036 .tx_queue_release = txgbe_dev_tx_queue_release,
4037 .dev_led_on = txgbe_dev_led_on,
4038 .dev_led_off = txgbe_dev_led_off,
4039 .flow_ctrl_get = txgbe_flow_ctrl_get,
4040 .flow_ctrl_set = txgbe_flow_ctrl_set,
4041 .priority_flow_ctrl_set = txgbe_priority_flow_ctrl_set,
4042 .mac_addr_add = txgbe_add_rar,
4043 .mac_addr_remove = txgbe_remove_rar,
4044 .mac_addr_set = txgbe_set_default_mac_addr,
4045 .uc_hash_table_set = txgbe_uc_hash_table_set,
4046 .uc_all_hash_table_set = txgbe_uc_all_hash_table_set,
4047 .set_queue_rate_limit = txgbe_set_queue_rate_limit,
4048 .reta_update = txgbe_dev_rss_reta_update,
4049 .reta_query = txgbe_dev_rss_reta_query,
4050 .rss_hash_update = txgbe_dev_rss_hash_update,
4051 .rss_hash_conf_get = txgbe_dev_rss_hash_conf_get,
4052 .set_mc_addr_list = txgbe_dev_set_mc_addr_list,
4053 .rxq_info_get = txgbe_rxq_info_get,
4054 .txq_info_get = txgbe_txq_info_get,
4055 .timesync_enable = txgbe_timesync_enable,
4056 .timesync_disable = txgbe_timesync_disable,
4057 .timesync_read_rx_timestamp = txgbe_timesync_read_rx_timestamp,
4058 .timesync_read_tx_timestamp = txgbe_timesync_read_tx_timestamp,
4059 .get_reg = txgbe_get_regs,
4060 .get_eeprom_length = txgbe_get_eeprom_length,
4061 .get_eeprom = txgbe_get_eeprom,
4062 .set_eeprom = txgbe_set_eeprom,
4063 .get_module_info = txgbe_get_module_info,
4064 .get_module_eeprom = txgbe_get_module_eeprom,
4065 .get_dcb_info = txgbe_dev_get_dcb_info,
4066 .timesync_adjust_time = txgbe_timesync_adjust_time,
4067 .timesync_read_time = txgbe_timesync_read_time,
4068 .timesync_write_time = txgbe_timesync_write_time,
4071 RTE_PMD_REGISTER_PCI(net_txgbe, rte_txgbe_pmd);
4072 RTE_PMD_REGISTER_PCI_TABLE(net_txgbe, pci_id_txgbe_map);
4073 RTE_PMD_REGISTER_KMOD_DEP(net_txgbe, "* igb_uio | uio_pci_generic | vfio-pci");
4075 RTE_LOG_REGISTER(txgbe_logtype_init, pmd.net.txgbe.init, NOTICE);
4076 RTE_LOG_REGISTER(txgbe_logtype_driver, pmd.net.txgbe.driver, NOTICE);
4078 #ifdef RTE_LIBRTE_TXGBE_DEBUG_RX
4079 RTE_LOG_REGISTER(txgbe_logtype_rx, pmd.net.txgbe.rx, DEBUG);
4081 #ifdef RTE_LIBRTE_TXGBE_DEBUG_TX
4082 RTE_LOG_REGISTER(txgbe_logtype_tx, pmd.net.txgbe.tx, DEBUG);
4085 #ifdef RTE_LIBRTE_TXGBE_DEBUG_TX_FREE
4086 RTE_LOG_REGISTER(txgbe_logtype_tx_free, pmd.net.txgbe.tx_free, DEBUG);