drivers/net/txgbe/txgbe_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2015-2020
   3  */
   4
   5 #include <stdio.h>
   6 #include <errno.h>
   7 #include <stdint.h>
   8 #include <string.h>
   9 #include <rte_common.h>
  10 #include <rte_ethdev_pci.h>
  11
  12 #include <rte_interrupts.h>
  13 #include <rte_log.h>
  14 #include <rte_debug.h>
  15 #include <rte_pci.h>
  16 #include <rte_memory.h>
  17 #include <rte_eal.h>
  18 #include <rte_alarm.h>
  19
  20 #include "txgbe_logs.h"
  21 #include "base/txgbe.h"
  22 #include "txgbe_ethdev.h"
  23 #include "txgbe_rxtx.h"
  24 #include "txgbe_regs_group.h"
  25
  26 static const struct reg_info txgbe_regs_general[] = {
  27         {TXGBE_RST, 1, 1, "TXGBE_RST"},
  28         {TXGBE_STAT, 1, 1, "TXGBE_STAT"},
  29         {TXGBE_PORTCTL, 1, 1, "TXGBE_PORTCTL"},
  30         {TXGBE_SDP, 1, 1, "TXGBE_SDP"},
  31         {TXGBE_SDPCTL, 1, 1, "TXGBE_SDPCTL"},
  32         {TXGBE_LEDCTL, 1, 1, "TXGBE_LEDCTL"},
  33         {0, 0, 0, ""}
  34 };
  35
  36 static const struct reg_info txgbe_regs_nvm[] = {
  37         {0, 0, 0, ""}
  38 };
  39
  40 static const struct reg_info txgbe_regs_interrupt[] = {
  41         {0, 0, 0, ""}
  42 };
  43
  44 static const struct reg_info txgbe_regs_fctl_others[] = {
  45         {0, 0, 0, ""}
  46 };
  47
  48 static const struct reg_info txgbe_regs_rxdma[] = {
  49         {0, 0, 0, ""}
  50 };
  51
  52 static const struct reg_info txgbe_regs_rx[] = {
  53         {0, 0, 0, ""}
  54 };
  55
  56 static struct reg_info txgbe_regs_tx[] = {
  57         {0, 0, 0, ""}
  58 };
  59
  60 static const struct reg_info txgbe_regs_wakeup[] = {
  61         {0, 0, 0, ""}
  62 };
  63
  64 static const struct reg_info txgbe_regs_dcb[] = {
  65         {0, 0, 0, ""}
  66 };
  67
  68 static const struct reg_info txgbe_regs_mac[] = {
  69         {0, 0, 0, ""}
  70 };
  71
  72 static const struct reg_info txgbe_regs_diagnostic[] = {
  73         {0, 0, 0, ""},
  74 };
  75
  76 /* PF registers */
  77 static const struct reg_info *txgbe_regs_others[] = {
  78                                 txgbe_regs_general,
  79                                 txgbe_regs_nvm,
  80                                 txgbe_regs_interrupt,
  81                                 txgbe_regs_fctl_others,
  82                                 txgbe_regs_rxdma,
  83                                 txgbe_regs_rx,
  84                                 txgbe_regs_tx,
  85                                 txgbe_regs_wakeup,
  86                                 txgbe_regs_dcb,
  87                                 txgbe_regs_mac,
  88                                 txgbe_regs_diagnostic,
  89                                 NULL};
  90
  91 static int txgbe_fdir_filter_init(struct rte_eth_dev *eth_dev);
  92 static int txgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev);
  93 static int txgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev);
  94 static int txgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev);
  95 static int  txgbe_dev_set_link_up(struct rte_eth_dev *dev);
  96 static int  txgbe_dev_set_link_down(struct rte_eth_dev *dev);
  97 static int txgbe_dev_close(struct rte_eth_dev *dev);
  98 static int txgbe_dev_link_update(struct rte_eth_dev *dev,
  99                                 int wait_to_complete);
 100 static int txgbe_dev_stats_reset(struct rte_eth_dev *dev);
 101 static void txgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
 102 static void txgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev,
 103                                         uint16_t queue);
 104
 105 static void txgbe_dev_link_status_print(struct rte_eth_dev *dev);
 106 static int txgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on);
 107 static int txgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev);
 108 static int txgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
 109 static int txgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
 110 static int txgbe_dev_interrupt_action(struct rte_eth_dev *dev,
 111                                       struct rte_intr_handle *handle);
 112 static void txgbe_dev_interrupt_handler(void *param);
 113 static void txgbe_dev_interrupt_delayed_handler(void *param);
 114 static void txgbe_configure_msix(struct rte_eth_dev *dev);
 115
 116 static int txgbe_filter_restore(struct rte_eth_dev *dev);
 117 static void txgbe_l2_tunnel_conf(struct rte_eth_dev *dev);
 118
 119 #define TXGBE_SET_HWSTRIP(h, q) do {\
 120                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 121                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 122                 (h)->bitmap[idx] |= 1 << bit;\
 123         } while (0)
 124
 125 #define TXGBE_CLEAR_HWSTRIP(h, q) do {\
 126                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 127                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 128                 (h)->bitmap[idx] &= ~(1 << bit);\
 129         } while (0)
 130
 131 #define TXGBE_GET_HWSTRIP(h, q, r) do {\
 132                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 133                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 134                 (r) = (h)->bitmap[idx] >> bit & 1;\
 135         } while (0)
 136
 137 /*
 138  * The set of PCI devices this driver supports
 139  */
 140 static const struct rte_pci_id pci_id_txgbe_map[] = {
 141         { RTE_PCI_DEVICE(PCI_VENDOR_ID_WANGXUN, TXGBE_DEV_ID_RAPTOR_SFP) },
 142         { RTE_PCI_DEVICE(PCI_VENDOR_ID_WANGXUN, TXGBE_DEV_ID_WX1820_SFP) },
 143         { .vendor_id = 0, /* sentinel */ },
 144 };
 145
 146 static const struct rte_eth_desc_lim rx_desc_lim = {
 147         .nb_max = TXGBE_RING_DESC_MAX,
 148         .nb_min = TXGBE_RING_DESC_MIN,
 149         .nb_align = TXGBE_RXD_ALIGN,
 150 };
 151
 152 static const struct rte_eth_desc_lim tx_desc_lim = {
 153         .nb_max = TXGBE_RING_DESC_MAX,
 154         .nb_min = TXGBE_RING_DESC_MIN,
 155         .nb_align = TXGBE_TXD_ALIGN,
 156         .nb_seg_max = TXGBE_TX_MAX_SEG,
 157         .nb_mtu_seg_max = TXGBE_TX_MAX_SEG,
 158 };
 159
 160 static const struct eth_dev_ops txgbe_eth_dev_ops;
 161
 162 #define HW_XSTAT(m) {#m, offsetof(struct txgbe_hw_stats, m)}
 163 #define HW_XSTAT_NAME(m, n) {n, offsetof(struct txgbe_hw_stats, m)}
 164 static const struct rte_txgbe_xstats_name_off rte_txgbe_stats_strings[] = {
 165         /* MNG RxTx */
 166         HW_XSTAT(mng_bmc2host_packets),
 167         HW_XSTAT(mng_host2bmc_packets),
 168         /* Basic RxTx */
 169         HW_XSTAT(rx_packets),
 170         HW_XSTAT(tx_packets),
 171         HW_XSTAT(rx_bytes),
 172         HW_XSTAT(tx_bytes),
 173         HW_XSTAT(rx_total_bytes),
 174         HW_XSTAT(rx_total_packets),
 175         HW_XSTAT(tx_total_packets),
 176         HW_XSTAT(rx_total_missed_packets),
 177         HW_XSTAT(rx_broadcast_packets),
 178         HW_XSTAT(rx_multicast_packets),
 179         HW_XSTAT(rx_management_packets),
 180         HW_XSTAT(tx_management_packets),
 181         HW_XSTAT(rx_management_dropped),
 182
 183         /* Basic Error */
 184         HW_XSTAT(rx_crc_errors),
 185         HW_XSTAT(rx_illegal_byte_errors),
 186         HW_XSTAT(rx_error_bytes),
 187         HW_XSTAT(rx_mac_short_packet_dropped),
 188         HW_XSTAT(rx_length_errors),
 189         HW_XSTAT(rx_undersize_errors),
 190         HW_XSTAT(rx_fragment_errors),
 191         HW_XSTAT(rx_oversize_errors),
 192         HW_XSTAT(rx_jabber_errors),
 193         HW_XSTAT(rx_l3_l4_xsum_error),
 194         HW_XSTAT(mac_local_errors),
 195         HW_XSTAT(mac_remote_errors),
 196
 197         /* Flow Director */
 198         HW_XSTAT(flow_director_added_filters),
 199         HW_XSTAT(flow_director_removed_filters),
 200         HW_XSTAT(flow_director_filter_add_errors),
 201         HW_XSTAT(flow_director_filter_remove_errors),
 202         HW_XSTAT(flow_director_matched_filters),
 203         HW_XSTAT(flow_director_missed_filters),
 204
 205         /* FCoE */
 206         HW_XSTAT(rx_fcoe_crc_errors),
 207         HW_XSTAT(rx_fcoe_mbuf_allocation_errors),
 208         HW_XSTAT(rx_fcoe_dropped),
 209         HW_XSTAT(rx_fcoe_packets),
 210         HW_XSTAT(tx_fcoe_packets),
 211         HW_XSTAT(rx_fcoe_bytes),
 212         HW_XSTAT(tx_fcoe_bytes),
 213         HW_XSTAT(rx_fcoe_no_ddp),
 214         HW_XSTAT(rx_fcoe_no_ddp_ext_buff),
 215
 216         /* MACSEC */
 217         HW_XSTAT(tx_macsec_pkts_untagged),
 218         HW_XSTAT(tx_macsec_pkts_encrypted),
 219         HW_XSTAT(tx_macsec_pkts_protected),
 220         HW_XSTAT(tx_macsec_octets_encrypted),
 221         HW_XSTAT(tx_macsec_octets_protected),
 222         HW_XSTAT(rx_macsec_pkts_untagged),
 223         HW_XSTAT(rx_macsec_pkts_badtag),
 224         HW_XSTAT(rx_macsec_pkts_nosci),
 225         HW_XSTAT(rx_macsec_pkts_unknownsci),
 226         HW_XSTAT(rx_macsec_octets_decrypted),
 227         HW_XSTAT(rx_macsec_octets_validated),
 228         HW_XSTAT(rx_macsec_sc_pkts_unchecked),
 229         HW_XSTAT(rx_macsec_sc_pkts_delayed),
 230         HW_XSTAT(rx_macsec_sc_pkts_late),
 231         HW_XSTAT(rx_macsec_sa_pkts_ok),
 232         HW_XSTAT(rx_macsec_sa_pkts_invalid),
 233         HW_XSTAT(rx_macsec_sa_pkts_notvalid),
 234         HW_XSTAT(rx_macsec_sa_pkts_unusedsa),
 235         HW_XSTAT(rx_macsec_sa_pkts_notusingsa),
 236
 237         /* MAC RxTx */
 238         HW_XSTAT(rx_size_64_packets),
 239         HW_XSTAT(rx_size_65_to_127_packets),
 240         HW_XSTAT(rx_size_128_to_255_packets),
 241         HW_XSTAT(rx_size_256_to_511_packets),
 242         HW_XSTAT(rx_size_512_to_1023_packets),
 243         HW_XSTAT(rx_size_1024_to_max_packets),
 244         HW_XSTAT(tx_size_64_packets),
 245         HW_XSTAT(tx_size_65_to_127_packets),
 246         HW_XSTAT(tx_size_128_to_255_packets),
 247         HW_XSTAT(tx_size_256_to_511_packets),
 248         HW_XSTAT(tx_size_512_to_1023_packets),
 249         HW_XSTAT(tx_size_1024_to_max_packets),
 250
 251         /* Flow Control */
 252         HW_XSTAT(tx_xon_packets),
 253         HW_XSTAT(rx_xon_packets),
 254         HW_XSTAT(tx_xoff_packets),
 255         HW_XSTAT(rx_xoff_packets),
 256
 257         HW_XSTAT_NAME(tx_xon_packets, "tx_flow_control_xon_packets"),
 258         HW_XSTAT_NAME(rx_xon_packets, "rx_flow_control_xon_packets"),
 259         HW_XSTAT_NAME(tx_xoff_packets, "tx_flow_control_xoff_packets"),
 260         HW_XSTAT_NAME(rx_xoff_packets, "rx_flow_control_xoff_packets"),
 261 };
 262
 263 #define TXGBE_NB_HW_STATS (sizeof(rte_txgbe_stats_strings) / \
 264                            sizeof(rte_txgbe_stats_strings[0]))
 265
 266 /* Per-priority statistics */
 267 #define UP_XSTAT(m) {#m, offsetof(struct txgbe_hw_stats, up[0].m)}
 268 static const struct rte_txgbe_xstats_name_off rte_txgbe_up_strings[] = {
 269         UP_XSTAT(rx_up_packets),
 270         UP_XSTAT(tx_up_packets),
 271         UP_XSTAT(rx_up_bytes),
 272         UP_XSTAT(tx_up_bytes),
 273         UP_XSTAT(rx_up_drop_packets),
 274
 275         UP_XSTAT(tx_up_xon_packets),
 276         UP_XSTAT(rx_up_xon_packets),
 277         UP_XSTAT(tx_up_xoff_packets),
 278         UP_XSTAT(rx_up_xoff_packets),
 279         UP_XSTAT(rx_up_dropped),
 280         UP_XSTAT(rx_up_mbuf_alloc_errors),
 281         UP_XSTAT(tx_up_xon2off_packets),
 282 };
 283
 284 #define TXGBE_NB_UP_STATS (sizeof(rte_txgbe_up_strings) / \
 285                            sizeof(rte_txgbe_up_strings[0]))
 286
 287 /* Per-queue statistics */
 288 #define QP_XSTAT(m) {#m, offsetof(struct txgbe_hw_stats, qp[0].m)}
 289 static const struct rte_txgbe_xstats_name_off rte_txgbe_qp_strings[] = {
 290         QP_XSTAT(rx_qp_packets),
 291         QP_XSTAT(tx_qp_packets),
 292         QP_XSTAT(rx_qp_bytes),
 293         QP_XSTAT(tx_qp_bytes),
 294         QP_XSTAT(rx_qp_mc_packets),
 295 };
 296
 297 #define TXGBE_NB_QP_STATS (sizeof(rte_txgbe_qp_strings) / \
 298                            sizeof(rte_txgbe_qp_strings[0]))
 299
 300 static inline int
 301 txgbe_is_sfp(struct txgbe_hw *hw)
 302 {
 303         switch (hw->phy.type) {
 304         case txgbe_phy_sfp_avago:
 305         case txgbe_phy_sfp_ftl:
 306         case txgbe_phy_sfp_intel:
 307         case txgbe_phy_sfp_unknown:
 308         case txgbe_phy_sfp_tyco_passive:
 309         case txgbe_phy_sfp_unknown_passive:
 310                 return 1;
 311         default:
 312                 return 0;
 313         }
 314 }
 315
 316 static inline int32_t
 317 txgbe_pf_reset_hw(struct txgbe_hw *hw)
 318 {
 319         uint32_t ctrl_ext;
 320         int32_t status;
 321
 322         status = hw->mac.reset_hw(hw);
 323
 324         ctrl_ext = rd32(hw, TXGBE_PORTCTL);
 325         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 326         ctrl_ext |= TXGBE_PORTCTL_RSTDONE;
 327         wr32(hw, TXGBE_PORTCTL, ctrl_ext);
 328         txgbe_flush(hw);
 329
 330         if (status == TXGBE_ERR_SFP_NOT_PRESENT)
 331                 status = 0;
 332         return status;
 333 }
 334
 335 static inline void
 336 txgbe_enable_intr(struct rte_eth_dev *dev)
 337 {
 338         struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);
 339         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
 340
 341         wr32(hw, TXGBE_IENMISC, intr->mask_misc);
 342         wr32(hw, TXGBE_IMC(0), TXGBE_IMC_MASK);
 343         wr32(hw, TXGBE_IMC(1), TXGBE_IMC_MASK);
 344         txgbe_flush(hw);
 345 }
 346
 347 static void
 348 txgbe_disable_intr(struct txgbe_hw *hw)
 349 {
 350         PMD_INIT_FUNC_TRACE();
 351
 352         wr32(hw, TXGBE_IENMISC, ~BIT_MASK32);
 353         wr32(hw, TXGBE_IMS(0), TXGBE_IMC_MASK);
 354         wr32(hw, TXGBE_IMS(1), TXGBE_IMC_MASK);
 355         txgbe_flush(hw);
 356 }
 357
 358 static int
 359 txgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 360                                   uint16_t queue_id,
 361                                   uint8_t stat_idx,
 362                                   uint8_t is_rx)
 363 {
 364         struct txgbe_hw *hw = TXGBE_DEV_HW(eth_dev);
 365         struct txgbe_stat_mappings *stat_mappings =
 366                 TXGBE_DEV_STAT_MAPPINGS(eth_dev);
 367         uint32_t qsmr_mask = 0;
 368         uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
 369         uint32_t q_map;
 370         uint8_t n, offset;
 371
 372         if (hw->mac.type != txgbe_mac_raptor)
 373                 return -ENOSYS;
 374
 375         if (stat_idx & !QMAP_FIELD_RESERVED_BITS_MASK)
 376                 return -EIO;
 377
 378         PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d",
 379                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 380                      queue_id, stat_idx);
 381
 382         n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
 383         if (n >= TXGBE_NB_STAT_MAPPING) {
 384                 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
 385                 return -EIO;
 386         }
 387         offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
 388
 389         /* Now clear any previous stat_idx set */
 390         clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 391         if (!is_rx)
 392                 stat_mappings->tqsm[n] &= ~clearing_mask;
 393         else
 394                 stat_mappings->rqsm[n] &= ~clearing_mask;
 395
 396         q_map = (uint32_t)stat_idx;
 397         q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
 398         qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 399         if (!is_rx)
 400                 stat_mappings->tqsm[n] |= qsmr_mask;
 401         else
 402                 stat_mappings->rqsm[n] |= qsmr_mask;
 403
 404         PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d",
 405                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 406                      queue_id, stat_idx);
 407         PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
 408                      is_rx ? stat_mappings->rqsm[n] : stat_mappings->tqsm[n]);
 409         return 0;
 410 }
 411
 412 static void
 413 txgbe_dcb_init(struct txgbe_hw *hw, struct txgbe_dcb_config *dcb_config)
 414 {
 415         int i;
 416         u8 bwgp;
 417         struct txgbe_dcb_tc_config *tc;
 418
 419         UNREFERENCED_PARAMETER(hw);
 420
 421         dcb_config->num_tcs.pg_tcs = TXGBE_DCB_TC_MAX;
 422         dcb_config->num_tcs.pfc_tcs = TXGBE_DCB_TC_MAX;
 423         bwgp = (u8)(100 / TXGBE_DCB_TC_MAX);
 424         for (i = 0; i < TXGBE_DCB_TC_MAX; i++) {
 425                 tc = &dcb_config->tc_config[i];
 426                 tc->path[TXGBE_DCB_TX_CONFIG].bwg_id = i;
 427                 tc->path[TXGBE_DCB_TX_CONFIG].bwg_percent = bwgp + (i & 1);
 428                 tc->path[TXGBE_DCB_RX_CONFIG].bwg_id = i;
 429                 tc->path[TXGBE_DCB_RX_CONFIG].bwg_percent = bwgp + (i & 1);
 430                 tc->pfc = txgbe_dcb_pfc_disabled;
 431         }
 432
 433         /* Initialize default user to priority mapping, UPx->TC0 */
 434         tc = &dcb_config->tc_config[0];
 435         tc->path[TXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
 436         tc->path[TXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
 437         for (i = 0; i < TXGBE_DCB_BWG_MAX; i++) {
 438                 dcb_config->bw_percentage[i][TXGBE_DCB_TX_CONFIG] = 100;
 439                 dcb_config->bw_percentage[i][TXGBE_DCB_RX_CONFIG] = 100;
 440         }
 441         dcb_config->rx_pba_cfg = txgbe_dcb_pba_equal;
 442         dcb_config->pfc_mode_enable = false;
 443         dcb_config->vt_mode = true;
 444         dcb_config->round_robin_enable = false;
 445         /* support all DCB capabilities */
 446         dcb_config->support.capabilities = 0xFF;
 447 }
 448
 449 /*
 450  * Ensure that all locks are released before first NVM or PHY access
 451  */
 452 static void
 453 txgbe_swfw_lock_reset(struct txgbe_hw *hw)
 454 {
 455         uint16_t mask;
 456
 457         /*
 458          * These ones are more tricky since they are common to all ports; but
 459          * swfw_sync retries last long enough (1s) to be almost sure that if
 460          * lock can not be taken it is due to an improper lock of the
 461          * semaphore.
 462          */
 463         mask = TXGBE_MNGSEM_SWPHY |
 464                TXGBE_MNGSEM_SWMBX |
 465                TXGBE_MNGSEM_SWFLASH;
 466         if (hw->mac.acquire_swfw_sync(hw, mask) < 0)
 467                 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
 468
 469         hw->mac.release_swfw_sync(hw, mask);
 470 }
 471
 472 static int
 473 eth_txgbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params __rte_unused)
 474 {
 475         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
 476         struct txgbe_hw *hw = TXGBE_DEV_HW(eth_dev);
 477         struct txgbe_vfta *shadow_vfta = TXGBE_DEV_VFTA(eth_dev);
 478         struct txgbe_hwstrip *hwstrip = TXGBE_DEV_HWSTRIP(eth_dev);
 479         struct txgbe_dcb_config *dcb_config = TXGBE_DEV_DCB_CONFIG(eth_dev);
 480         struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(eth_dev);
 481         struct txgbe_bw_conf *bw_conf = TXGBE_DEV_BW_CONF(eth_dev);
 482         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 483         const struct rte_memzone *mz;
 484         uint32_t ctrl_ext;
 485         uint16_t csum;
 486         int err, i, ret;
 487
 488         PMD_INIT_FUNC_TRACE();
 489
 490         eth_dev->dev_ops = &txgbe_eth_dev_ops;
 491         eth_dev->rx_queue_count       = txgbe_dev_rx_queue_count;
 492         eth_dev->rx_descriptor_status = txgbe_dev_rx_descriptor_status;
 493         eth_dev->tx_descriptor_status = txgbe_dev_tx_descriptor_status;
 494         eth_dev->rx_pkt_burst = &txgbe_recv_pkts;
 495         eth_dev->tx_pkt_burst = &txgbe_xmit_pkts;
 496         eth_dev->tx_pkt_prepare = &txgbe_prep_pkts;
 497
 498         /*
 499          * For secondary processes, we don't initialise any further as primary
 500          * has already done this work. Only check we don't need a different
 501          * RX and TX function.
 502          */
 503         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
 504                 struct txgbe_tx_queue *txq;
 505                 /* TX queue function in primary, set by last queue initialized
 506                  * Tx queue may not initialized by primary process
 507                  */
 508                 if (eth_dev->data->tx_queues) {
 509                         uint16_t nb_tx_queues = eth_dev->data->nb_tx_queues;
 510                         txq = eth_dev->data->tx_queues[nb_tx_queues - 1];
 511                         txgbe_set_tx_function(eth_dev, txq);
 512                 } else {
 513                         /* Use default TX function if we get here */
 514                         PMD_INIT_LOG(NOTICE, "No TX queues configured yet. "
 515                                      "Using default TX function.");
 516                 }
 517
 518                 txgbe_set_rx_function(eth_dev);
 519
 520                 return 0;
 521         }
 522
 523         rte_eth_copy_pci_info(eth_dev, pci_dev);
 524
 525         /* Vendor and Device ID need to be set before init of shared code */
 526         hw->device_id = pci_dev->id.device_id;
 527         hw->vendor_id = pci_dev->id.vendor_id;
 528         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
 529         hw->allow_unsupported_sfp = 1;
 530
 531         /* Reserve memory for interrupt status block */
 532         mz = rte_eth_dma_zone_reserve(eth_dev, "txgbe_driver", -1,
 533                 16, TXGBE_ALIGN, SOCKET_ID_ANY);
 534         if (mz == NULL)
 535                 return -ENOMEM;
 536
 537         hw->isb_dma = TMZ_PADDR(mz);
 538         hw->isb_mem = TMZ_VADDR(mz);
 539
 540         /* Initialize the shared code (base driver) */
 541         err = txgbe_init_shared_code(hw);
 542         if (err != 0) {
 543                 PMD_INIT_LOG(ERR, "Shared code init failed: %d", err);
 544                 return -EIO;
 545         }
 546
 547         /* Unlock any pending hardware semaphore */
 548         txgbe_swfw_lock_reset(hw);
 549
 550         /* Initialize DCB configuration*/
 551         memset(dcb_config, 0, sizeof(struct txgbe_dcb_config));
 552         txgbe_dcb_init(hw, dcb_config);
 553
 554         /* Get Hardware Flow Control setting */
 555         hw->fc.requested_mode = txgbe_fc_full;
 556         hw->fc.current_mode = txgbe_fc_full;
 557         hw->fc.pause_time = TXGBE_FC_PAUSE_TIME;
 558         for (i = 0; i < TXGBE_DCB_TC_MAX; i++) {
 559                 hw->fc.low_water[i] = TXGBE_FC_XON_LOTH;
 560                 hw->fc.high_water[i] = TXGBE_FC_XOFF_HITH;
 561         }
 562         hw->fc.send_xon = 1;
 563
 564         err = hw->rom.init_params(hw);
 565         if (err != 0) {
 566                 PMD_INIT_LOG(ERR, "The EEPROM init failed: %d", err);
 567                 return -EIO;
 568         }
 569
 570         /* Make sure we have a good EEPROM before we read from it */
 571         err = hw->rom.validate_checksum(hw, &csum);
 572         if (err != 0) {
 573                 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", err);
 574                 return -EIO;
 575         }
 576
 577         err = hw->mac.init_hw(hw);
 578
 579         /*
 580          * Devices with copper phys will fail to initialise if txgbe_init_hw()
 581          * is called too soon after the kernel driver unbinding/binding occurs.
 582          * The failure occurs in txgbe_identify_phy() for all devices,
 583          * but for non-copper devies, txgbe_identify_sfp_module() is
 584          * also called. See txgbe_identify_phy(). The reason for the
 585          * failure is not known, and only occuts when virtualisation features
 586          * are disabled in the bios. A delay of 200ms  was found to be enough by
 587          * trial-and-error, and is doubled to be safe.
 588          */
 589         if (err && hw->phy.media_type == txgbe_media_type_copper) {
 590                 rte_delay_ms(200);
 591                 err = hw->mac.init_hw(hw);
 592         }
 593
 594         if (err == TXGBE_ERR_SFP_NOT_PRESENT)
 595                 err = 0;
 596
 597         if (err == TXGBE_ERR_EEPROM_VERSION) {
 598                 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
 599                              "LOM.  Please be aware there may be issues associated "
 600                              "with your hardware.");
 601                 PMD_INIT_LOG(ERR, "If you are experiencing problems "
 602                              "please contact your hardware representative "
 603                              "who provided you with this hardware.");
 604         } else if (err == TXGBE_ERR_SFP_NOT_SUPPORTED) {
 605                 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
 606         }
 607         if (err) {
 608                 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", err);
 609                 return -EIO;
 610         }
 611
 612         /* Reset the hw statistics */
 613         txgbe_dev_stats_reset(eth_dev);
 614
 615         /* disable interrupt */
 616         txgbe_disable_intr(hw);
 617
 618         /* Allocate memory for storing MAC addresses */
 619         eth_dev->data->mac_addrs = rte_zmalloc("txgbe", RTE_ETHER_ADDR_LEN *
 620                                                hw->mac.num_rar_entries, 0);
 621         if (eth_dev->data->mac_addrs == NULL) {
 622                 PMD_INIT_LOG(ERR,
 623                              "Failed to allocate %u bytes needed to store "
 624                              "MAC addresses",
 625                              RTE_ETHER_ADDR_LEN * hw->mac.num_rar_entries);
 626                 return -ENOMEM;
 627         }
 628
 629         /* Copy the permanent MAC address */
 630         rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.perm_addr,
 631                         &eth_dev->data->mac_addrs[0]);
 632
 633         /* Allocate memory for storing hash filter MAC addresses */
 634         eth_dev->data->hash_mac_addrs = rte_zmalloc("txgbe",
 635                         RTE_ETHER_ADDR_LEN * TXGBE_VMDQ_NUM_UC_MAC, 0);
 636         if (eth_dev->data->hash_mac_addrs == NULL) {
 637                 PMD_INIT_LOG(ERR,
 638                              "Failed to allocate %d bytes needed to store MAC addresses",
 639                              RTE_ETHER_ADDR_LEN * TXGBE_VMDQ_NUM_UC_MAC);
 640                 return -ENOMEM;
 641         }
 642
 643         /* initialize the vfta */
 644         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
 645
 646         /* initialize the hw strip bitmap*/
 647         memset(hwstrip, 0, sizeof(*hwstrip));
 648
 649         /* initialize PF if max_vfs not zero */
 650         ret = txgbe_pf_host_init(eth_dev);
 651         if (ret) {
 652                 rte_free(eth_dev->data->mac_addrs);
 653                 eth_dev->data->mac_addrs = NULL;
 654                 rte_free(eth_dev->data->hash_mac_addrs);
 655                 eth_dev->data->hash_mac_addrs = NULL;
 656                 return ret;
 657         }
 658
 659         ctrl_ext = rd32(hw, TXGBE_PORTCTL);
 660         /* let hardware know driver is loaded */
 661         ctrl_ext |= TXGBE_PORTCTL_DRVLOAD;
 662         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 663         ctrl_ext |= TXGBE_PORTCTL_RSTDONE;
 664         wr32(hw, TXGBE_PORTCTL, ctrl_ext);
 665         txgbe_flush(hw);
 666
 667         if (txgbe_is_sfp(hw) && hw->phy.sfp_type != txgbe_sfp_type_not_present)
 668                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
 669                              (int)hw->mac.type, (int)hw->phy.type,
 670                              (int)hw->phy.sfp_type);
 671         else
 672                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
 673                              (int)hw->mac.type, (int)hw->phy.type);
 674
 675         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
 676                      eth_dev->data->port_id, pci_dev->id.vendor_id,
 677                      pci_dev->id.device_id);
 678
 679         rte_intr_callback_register(intr_handle,
 680                                    txgbe_dev_interrupt_handler, eth_dev);
 681
 682         /* enable uio/vfio intr/eventfd mapping */
 683         rte_intr_enable(intr_handle);
 684
 685         /* enable support intr */
 686         txgbe_enable_intr(eth_dev);
 687
 688         /* initialize filter info */
 689         memset(filter_info, 0,
 690                sizeof(struct txgbe_filter_info));
 691
 692         /* initialize 5tuple filter list */
 693         TAILQ_INIT(&filter_info->fivetuple_list);
 694
 695         /* initialize flow director filter list & hash */
 696         txgbe_fdir_filter_init(eth_dev);
 697
 698         /* initialize l2 tunnel filter list & hash */
 699         txgbe_l2_tn_filter_init(eth_dev);
 700
 701         /* initialize flow filter lists */
 702         txgbe_filterlist_init();
 703
 704         /* initialize bandwidth configuration info */
 705         memset(bw_conf, 0, sizeof(struct txgbe_bw_conf));
 706
 707         return 0;
 708 }
 709
 710 static int
 711 eth_txgbe_dev_uninit(struct rte_eth_dev *eth_dev)
 712 {
 713         PMD_INIT_FUNC_TRACE();
 714
 715         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 716                 return 0;
 717
 718         txgbe_dev_close(eth_dev);
 719
 720         return 0;
 721 }
 722
 723 static int txgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev)
 724 {
 725         struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(eth_dev);
 726         struct txgbe_5tuple_filter *p_5tuple;
 727
 728         while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) {
 729                 TAILQ_REMOVE(&filter_info->fivetuple_list,
 730                              p_5tuple,
 731                              entries);
 732                 rte_free(p_5tuple);
 733         }
 734         memset(filter_info->fivetuple_mask, 0,
 735                sizeof(uint32_t) * TXGBE_5TUPLE_ARRAY_SIZE);
 736
 737         return 0;
 738 }
 739
 740 static int txgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev)
 741 {
 742         struct txgbe_hw_fdir_info *fdir_info = TXGBE_DEV_FDIR(eth_dev);
 743         struct txgbe_fdir_filter *fdir_filter;
 744
 745         if (fdir_info->hash_map)
 746                 rte_free(fdir_info->hash_map);
 747         if (fdir_info->hash_handle)
 748                 rte_hash_free(fdir_info->hash_handle);
 749
 750         while ((fdir_filter = TAILQ_FIRST(&fdir_info->fdir_list))) {
 751                 TAILQ_REMOVE(&fdir_info->fdir_list,
 752                              fdir_filter,
 753                              entries);
 754                 rte_free(fdir_filter);
 755         }
 756
 757         return 0;
 758 }
 759
 760 static int txgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev)
 761 {
 762         struct txgbe_l2_tn_info *l2_tn_info = TXGBE_DEV_L2_TN(eth_dev);
 763         struct txgbe_l2_tn_filter *l2_tn_filter;
 764
 765         if (l2_tn_info->hash_map)
 766                 rte_free(l2_tn_info->hash_map);
 767         if (l2_tn_info->hash_handle)
 768                 rte_hash_free(l2_tn_info->hash_handle);
 769
 770         while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
 771                 TAILQ_REMOVE(&l2_tn_info->l2_tn_list,
 772                              l2_tn_filter,
 773                              entries);
 774                 rte_free(l2_tn_filter);
 775         }
 776
 777         return 0;
 778 }
 779
 780 static int txgbe_fdir_filter_init(struct rte_eth_dev *eth_dev)
 781 {
 782         struct txgbe_hw_fdir_info *fdir_info = TXGBE_DEV_FDIR(eth_dev);
 783         char fdir_hash_name[RTE_HASH_NAMESIZE];
 784         struct rte_hash_parameters fdir_hash_params = {
 785                 .name = fdir_hash_name,
 786                 .entries = TXGBE_MAX_FDIR_FILTER_NUM,
 787                 .key_len = sizeof(struct txgbe_atr_input),
 788                 .hash_func = rte_hash_crc,
 789                 .hash_func_init_val = 0,
 790                 .socket_id = rte_socket_id(),
 791         };
 792
 793         TAILQ_INIT(&fdir_info->fdir_list);
 794         snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
 795                  "fdir_%s", TDEV_NAME(eth_dev));
 796         fdir_info->hash_handle = rte_hash_create(&fdir_hash_params);
 797         if (!fdir_info->hash_handle) {
 798                 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
 799                 return -EINVAL;
 800         }
 801         fdir_info->hash_map = rte_zmalloc("txgbe",
 802                                           sizeof(struct txgbe_fdir_filter *) *
 803                                           TXGBE_MAX_FDIR_FILTER_NUM,
 804                                           0);
 805         if (!fdir_info->hash_map) {
 806                 PMD_INIT_LOG(ERR,
 807                              "Failed to allocate memory for fdir hash map!");
 808                 return -ENOMEM;
 809         }
 810         fdir_info->mask_added = FALSE;
 811
 812         return 0;
 813 }
 814
 815 static int txgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev)
 816 {
 817         struct txgbe_l2_tn_info *l2_tn_info = TXGBE_DEV_L2_TN(eth_dev);
 818         char l2_tn_hash_name[RTE_HASH_NAMESIZE];
 819         struct rte_hash_parameters l2_tn_hash_params = {
 820                 .name = l2_tn_hash_name,
 821                 .entries = TXGBE_MAX_L2_TN_FILTER_NUM,
 822                 .key_len = sizeof(struct txgbe_l2_tn_key),
 823                 .hash_func = rte_hash_crc,
 824                 .hash_func_init_val = 0,
 825                 .socket_id = rte_socket_id(),
 826         };
 827
 828         TAILQ_INIT(&l2_tn_info->l2_tn_list);
 829         snprintf(l2_tn_hash_name, RTE_HASH_NAMESIZE,
 830                  "l2_tn_%s", TDEV_NAME(eth_dev));
 831         l2_tn_info->hash_handle = rte_hash_create(&l2_tn_hash_params);
 832         if (!l2_tn_info->hash_handle) {
 833                 PMD_INIT_LOG(ERR, "Failed to create L2 TN hash table!");
 834                 return -EINVAL;
 835         }
 836         l2_tn_info->hash_map = rte_zmalloc("txgbe",
 837                                    sizeof(struct txgbe_l2_tn_filter *) *
 838                                    TXGBE_MAX_L2_TN_FILTER_NUM,
 839                                    0);
 840         if (!l2_tn_info->hash_map) {
 841                 PMD_INIT_LOG(ERR,
 842                         "Failed to allocate memory for L2 TN hash map!");
 843                 return -ENOMEM;
 844         }
 845         l2_tn_info->e_tag_en = FALSE;
 846         l2_tn_info->e_tag_fwd_en = FALSE;
 847         l2_tn_info->e_tag_ether_type = RTE_ETHER_TYPE_ETAG;
 848
 849         return 0;
 850 }
 851
 852 static int
 853 eth_txgbe_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
 854                 struct rte_pci_device *pci_dev)
 855 {
 856         struct rte_eth_dev *pf_ethdev;
 857         struct rte_eth_devargs eth_da;
 858         int retval;
 859
 860         if (pci_dev->device.devargs) {
 861                 retval = rte_eth_devargs_parse(pci_dev->device.devargs->args,
 862                                 &eth_da);
 863                 if (retval)
 864                         return retval;
 865         } else {
 866                 memset(&eth_da, 0, sizeof(eth_da));
 867         }
 868
 869         retval = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
 870                         sizeof(struct txgbe_adapter),
 871                         eth_dev_pci_specific_init, pci_dev,
 872                         eth_txgbe_dev_init, NULL);
 873
 874         if (retval || eth_da.nb_representor_ports < 1)
 875                 return retval;
 876
 877         pf_ethdev = rte_eth_dev_allocated(pci_dev->device.name);
 878         if (pf_ethdev == NULL)
 879                 return -ENODEV;
 880
 881         return 0;
 882 }
 883
 884 static int eth_txgbe_pci_remove(struct rte_pci_device *pci_dev)
 885 {
 886         struct rte_eth_dev *ethdev;
 887
 888         ethdev = rte_eth_dev_allocated(pci_dev->device.name);
 889         if (!ethdev)
 890                 return -ENODEV;
 891
 892         return rte_eth_dev_destroy(ethdev, eth_txgbe_dev_uninit);
 893 }
 894
 895 static struct rte_pci_driver rte_txgbe_pmd = {
 896         .id_table = pci_id_txgbe_map,
 897         .drv_flags = RTE_PCI_DRV_NEED_MAPPING |
 898                      RTE_PCI_DRV_INTR_LSC,
 899         .probe = eth_txgbe_pci_probe,
 900         .remove = eth_txgbe_pci_remove,
 901 };
 902
 903 static int
 904 txgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
 905 {
 906         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
 907         struct txgbe_vfta *shadow_vfta = TXGBE_DEV_VFTA(dev);
 908         uint32_t vfta;
 909         uint32_t vid_idx;
 910         uint32_t vid_bit;
 911
 912         vid_idx = (uint32_t)((vlan_id >> 5) & 0x7F);
 913         vid_bit = (uint32_t)(1 << (vlan_id & 0x1F));
 914         vfta = rd32(hw, TXGBE_VLANTBL(vid_idx));
 915         if (on)
 916                 vfta |= vid_bit;
 917         else
 918                 vfta &= ~vid_bit;
 919         wr32(hw, TXGBE_VLANTBL(vid_idx), vfta);
 920
 921         /* update local VFTA copy */
 922         shadow_vfta->vfta[vid_idx] = vfta;
 923
 924         return 0;
 925 }
 926
 927 static void
 928 txgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
 929 {
 930         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
 931         struct txgbe_rx_queue *rxq;
 932         bool restart;
 933         uint32_t rxcfg, rxbal, rxbah;
 934
 935         if (on)
 936                 txgbe_vlan_hw_strip_enable(dev, queue);
 937         else
 938                 txgbe_vlan_hw_strip_disable(dev, queue);
 939
 940         rxq = dev->data->rx_queues[queue];
 941         rxbal = rd32(hw, TXGBE_RXBAL(rxq->reg_idx));
 942         rxbah = rd32(hw, TXGBE_RXBAH(rxq->reg_idx));
 943         rxcfg = rd32(hw, TXGBE_RXCFG(rxq->reg_idx));
 944         if (rxq->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) {
 945                 restart = (rxcfg & TXGBE_RXCFG_ENA) &&
 946                         !(rxcfg & TXGBE_RXCFG_VLAN);
 947                 rxcfg |= TXGBE_RXCFG_VLAN;
 948         } else {
 949                 restart = (rxcfg & TXGBE_RXCFG_ENA) &&
 950                         (rxcfg & TXGBE_RXCFG_VLAN);
 951                 rxcfg &= ~TXGBE_RXCFG_VLAN;
 952         }
 953         rxcfg &= ~TXGBE_RXCFG_ENA;
 954
 955         if (restart) {
 956                 /* set vlan strip for ring */
 957                 txgbe_dev_rx_queue_stop(dev, queue);
 958                 wr32(hw, TXGBE_RXBAL(rxq->reg_idx), rxbal);
 959                 wr32(hw, TXGBE_RXBAH(rxq->reg_idx), rxbah);
 960                 wr32(hw, TXGBE_RXCFG(rxq->reg_idx), rxcfg);
 961                 txgbe_dev_rx_queue_start(dev, queue);
 962         }
 963 }
 964
 965 static int
 966 txgbe_vlan_tpid_set(struct rte_eth_dev *dev,
 967                     enum rte_vlan_type vlan_type,
 968                     uint16_t tpid)
 969 {
 970         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
 971         int ret = 0;
 972         uint32_t portctrl, vlan_ext, qinq;
 973
 974         portctrl = rd32(hw, TXGBE_PORTCTL);
 975
 976         vlan_ext = (portctrl & TXGBE_PORTCTL_VLANEXT);
 977         qinq = vlan_ext && (portctrl & TXGBE_PORTCTL_QINQ);
 978         switch (vlan_type) {
 979         case ETH_VLAN_TYPE_INNER:
 980                 if (vlan_ext) {
 981                         wr32m(hw, TXGBE_VLANCTL,
 982                                 TXGBE_VLANCTL_TPID_MASK,
 983                                 TXGBE_VLANCTL_TPID(tpid));
 984                         wr32m(hw, TXGBE_DMATXCTRL,
 985                                 TXGBE_DMATXCTRL_TPID_MASK,
 986                                 TXGBE_DMATXCTRL_TPID(tpid));
 987                 } else {
 988                         ret = -ENOTSUP;
 989                         PMD_DRV_LOG(ERR, "Inner type is not supported"
 990                                     " by single VLAN");
 991                 }
 992
 993                 if (qinq) {
 994                         wr32m(hw, TXGBE_TAGTPID(0),
 995                                 TXGBE_TAGTPID_LSB_MASK,
 996                                 TXGBE_TAGTPID_LSB(tpid));
 997                 }
 998                 break;
 999         case ETH_VLAN_TYPE_OUTER:
1000                 if (vlan_ext) {
1001                         /* Only the high 16-bits is valid */
1002                         wr32m(hw, TXGBE_EXTAG,
1003                                 TXGBE_EXTAG_VLAN_MASK,
1004                                 TXGBE_EXTAG_VLAN(tpid));
1005                 } else {
1006                         wr32m(hw, TXGBE_VLANCTL,
1007                                 TXGBE_VLANCTL_TPID_MASK,
1008                                 TXGBE_VLANCTL_TPID(tpid));
1009                         wr32m(hw, TXGBE_DMATXCTRL,
1010                                 TXGBE_DMATXCTRL_TPID_MASK,
1011                                 TXGBE_DMATXCTRL_TPID(tpid));
1012                 }
1013
1014                 if (qinq) {
1015                         wr32m(hw, TXGBE_TAGTPID(0),
1016                                 TXGBE_TAGTPID_MSB_MASK,
1017                                 TXGBE_TAGTPID_MSB(tpid));
1018                 }
1019                 break;
1020         default:
1021                 PMD_DRV_LOG(ERR, "Unsupported VLAN type %d", vlan_type);
1022                 return -EINVAL;
1023         }
1024
1025         return ret;
1026 }
1027
1028 void
1029 txgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1030 {
1031         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
1032         uint32_t vlnctrl;
1033
1034         PMD_INIT_FUNC_TRACE();
1035
1036         /* Filter Table Disable */
1037         vlnctrl = rd32(hw, TXGBE_VLANCTL);
1038         vlnctrl &= ~TXGBE_VLANCTL_VFE;
1039         wr32(hw, TXGBE_VLANCTL, vlnctrl);
1040 }
1041
1042 void
1043 txgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1044 {
1045         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
1046         struct txgbe_vfta *shadow_vfta = TXGBE_DEV_VFTA(dev);
1047         uint32_t vlnctrl;
1048         uint16_t i;
1049
1050         PMD_INIT_FUNC_TRACE();
1051
1052         /* Filter Table Enable */
1053         vlnctrl = rd32(hw, TXGBE_VLANCTL);
1054         vlnctrl &= ~TXGBE_VLANCTL_CFIENA;
1055         vlnctrl |= TXGBE_VLANCTL_VFE;
1056         wr32(hw, TXGBE_VLANCTL, vlnctrl);
1057
1058         /* write whatever is in local vfta copy */
1059         for (i = 0; i < TXGBE_VFTA_SIZE; i++)
1060                 wr32(hw, TXGBE_VLANTBL(i), shadow_vfta->vfta[i]);
1061 }
1062
1063 void
1064 txgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1065 {
1066         struct txgbe_hwstrip *hwstrip = TXGBE_DEV_HWSTRIP(dev);
1067         struct txgbe_rx_queue *rxq;
1068
1069         if (queue >= TXGBE_MAX_RX_QUEUE_NUM)
1070                 return;
1071
1072         if (on)
1073                 TXGBE_SET_HWSTRIP(hwstrip, queue);
1074         else
1075                 TXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1076
1077         if (queue >= dev->data->nb_rx_queues)
1078                 return;
1079
1080         rxq = dev->data->rx_queues[queue];
1081
1082         if (on) {
1083                 rxq->vlan_flags = PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
1084                 rxq->offloads |= DEV_RX_OFFLOAD_VLAN_STRIP;
1085         } else {
1086                 rxq->vlan_flags = PKT_RX_VLAN;
1087                 rxq->offloads &= ~DEV_RX_OFFLOAD_VLAN_STRIP;
1088         }
1089 }
1090
1091 static void
1092 txgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
1093 {
1094         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
1095         uint32_t ctrl;
1096
1097         PMD_INIT_FUNC_TRACE();
1098
1099         ctrl = rd32(hw, TXGBE_RXCFG(queue));
1100         ctrl &= ~TXGBE_RXCFG_VLAN;
1101         wr32(hw, TXGBE_RXCFG(queue), ctrl);
1102
1103         /* record those setting for HW strip per queue */
1104         txgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
1105 }
1106
1107 static void
1108 txgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
1109 {
1110         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
1111         uint32_t ctrl;
1112
1113         PMD_INIT_FUNC_TRACE();
1114
1115         ctrl = rd32(hw, TXGBE_RXCFG(queue));
1116         ctrl |= TXGBE_RXCFG_VLAN;
1117         wr32(hw, TXGBE_RXCFG(queue), ctrl);
1118
1119         /* record those setting for HW strip per queue */
1120         txgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
1121 }
1122
1123 static void
1124 txgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
1125 {
1126         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
1127         uint32_t ctrl;
1128
1129         PMD_INIT_FUNC_TRACE();
1130
1131         ctrl = rd32(hw, TXGBE_PORTCTL);
1132         ctrl &= ~TXGBE_PORTCTL_VLANEXT;
1133         ctrl &= ~TXGBE_PORTCTL_QINQ;
1134         wr32(hw, TXGBE_PORTCTL, ctrl);
1135 }
1136
1137 static void
1138 txgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
1139 {
1140         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
1141         struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
1142         struct rte_eth_txmode *txmode = &dev->data->dev_conf.txmode;
1143         uint32_t ctrl;
1144
1145         PMD_INIT_FUNC_TRACE();
1146
1147         ctrl  = rd32(hw, TXGBE_PORTCTL);
1148         ctrl |= TXGBE_PORTCTL_VLANEXT;
1149         if (rxmode->offloads & DEV_RX_OFFLOAD_QINQ_STRIP ||
1150             txmode->offloads & DEV_TX_OFFLOAD_QINQ_INSERT)
1151                 ctrl |= TXGBE_PORTCTL_QINQ;
1152         wr32(hw, TXGBE_PORTCTL, ctrl);
1153 }
1154
1155 void
1156 txgbe_vlan_hw_strip_config(struct rte_eth_dev *dev)
1157 {
1158         struct txgbe_rx_queue *rxq;
1159         uint16_t i;
1160
1161         PMD_INIT_FUNC_TRACE();
1162
1163         for (i = 0; i < dev->data->nb_rx_queues; i++) {
1164                 rxq = dev->data->rx_queues[i];
1165
1166                 if (rxq->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1167                         txgbe_vlan_strip_queue_set(dev, i, 1);
1168                 else
1169                         txgbe_vlan_strip_queue_set(dev, i, 0);
1170         }
1171 }
1172
1173 void
1174 txgbe_config_vlan_strip_on_all_queues(struct rte_eth_dev *dev, int mask)
1175 {
1176         uint16_t i;
1177         struct rte_eth_rxmode *rxmode;
1178         struct txgbe_rx_queue *rxq;
1179
1180         if (mask & ETH_VLAN_STRIP_MASK) {
1181                 rxmode = &dev->data->dev_conf.rxmode;
1182                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1183                         for (i = 0; i < dev->data->nb_rx_queues; i++) {
1184                                 rxq = dev->data->rx_queues[i];
1185                                 rxq->offloads |= DEV_RX_OFFLOAD_VLAN_STRIP;
1186                         }
1187                 else
1188                         for (i = 0; i < dev->data->nb_rx_queues; i++) {
1189                                 rxq = dev->data->rx_queues[i];
1190                                 rxq->offloads &= ~DEV_RX_OFFLOAD_VLAN_STRIP;
1191                         }
1192         }
1193 }
1194
1195 static int
1196 txgbe_vlan_offload_config(struct rte_eth_dev *dev, int mask)
1197 {
1198         struct rte_eth_rxmode *rxmode;
1199         rxmode = &dev->data->dev_conf.rxmode;
1200
1201         if (mask & ETH_VLAN_STRIP_MASK)
1202                 txgbe_vlan_hw_strip_config(dev);
1203
1204         if (mask & ETH_VLAN_FILTER_MASK) {
1205                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
1206                         txgbe_vlan_hw_filter_enable(dev);
1207                 else
1208                         txgbe_vlan_hw_filter_disable(dev);
1209         }
1210
1211         if (mask & ETH_VLAN_EXTEND_MASK) {
1212                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
1213                         txgbe_vlan_hw_extend_enable(dev);
1214                 else
1215                         txgbe_vlan_hw_extend_disable(dev);
1216         }
1217
1218         return 0;
1219 }
1220
1221 static int
1222 txgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1223 {
1224         txgbe_config_vlan_strip_on_all_queues(dev, mask);
1225
1226         txgbe_vlan_offload_config(dev, mask);
1227
1228         return 0;
1229 }
1230
1231 static void
1232 txgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1233 {
1234         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
1235         /* VLNCTL: enable vlan filtering and allow all vlan tags through */
1236         uint32_t vlanctrl = rd32(hw, TXGBE_VLANCTL);
1237
1238         vlanctrl |= TXGBE_VLANCTL_VFE; /* enable vlan filters */
1239         wr32(hw, TXGBE_VLANCTL, vlanctrl);
1240 }
1241
1242 static int
1243 txgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q)
1244 {
1245         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1246
1247         switch (nb_rx_q) {
1248         case 1:
1249         case 2:
1250                 RTE_ETH_DEV_SRIOV(dev).active = ETH_64_POOLS;
1251                 break;
1252         case 4:
1253                 RTE_ETH_DEV_SRIOV(dev).active = ETH_32_POOLS;
1254                 break;
1255         default:
1256                 return -EINVAL;
1257         }
1258
1259         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool =
1260                 TXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
1261         RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx =
1262                 pci_dev->max_vfs * RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
1263         return 0;
1264 }
1265
1266 static int
1267 txgbe_check_mq_mode(struct rte_eth_dev *dev)
1268 {
1269         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
1270         uint16_t nb_rx_q = dev->data->nb_rx_queues;
1271         uint16_t nb_tx_q = dev->data->nb_tx_queues;
1272
1273         if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
1274                 /* check multi-queue mode */
1275                 switch (dev_conf->rxmode.mq_mode) {
1276                 case ETH_MQ_RX_VMDQ_DCB:
1277                         PMD_INIT_LOG(INFO, "ETH_MQ_RX_VMDQ_DCB mode supported in SRIOV");
1278                         break;
1279                 case ETH_MQ_RX_VMDQ_DCB_RSS:
1280                         /* DCB/RSS VMDQ in SRIOV mode, not implement yet */
1281                         PMD_INIT_LOG(ERR, "SRIOV active,"
1282                                         " unsupported mq_mode rx %d.",
1283                                         dev_conf->rxmode.mq_mode);
1284                         return -EINVAL;
1285                 case ETH_MQ_RX_RSS:
1286                 case ETH_MQ_RX_VMDQ_RSS:
1287                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_RSS;
1288                         if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)
1289                                 if (txgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) {
1290                                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1291                                                 " invalid queue number"
1292                                                 " for VMDQ RSS, allowed"
1293                                                 " value are 1, 2 or 4.");
1294                                         return -EINVAL;
1295                                 }
1296                         break;
1297                 case ETH_MQ_RX_VMDQ_ONLY:
1298                 case ETH_MQ_RX_NONE:
1299                         /* if nothing mq mode configure, use default scheme */
1300                         dev->data->dev_conf.rxmode.mq_mode =
1301                                 ETH_MQ_RX_VMDQ_ONLY;
1302                         break;
1303                 default: /* ETH_MQ_RX_DCB, ETH_MQ_RX_DCB_RSS or ETH_MQ_TX_DCB*/
1304                         /* SRIOV only works in VMDq enable mode */
1305                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1306                                         " wrong mq_mode rx %d.",
1307                                         dev_conf->rxmode.mq_mode);
1308                         return -EINVAL;
1309                 }
1310
1311                 switch (dev_conf->txmode.mq_mode) {
1312                 case ETH_MQ_TX_VMDQ_DCB:
1313                         PMD_INIT_LOG(INFO, "ETH_MQ_TX_VMDQ_DCB mode supported in SRIOV");
1314                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_DCB;
1315                         break;
1316                 default: /* ETH_MQ_TX_VMDQ_ONLY or ETH_MQ_TX_NONE */
1317                         dev->data->dev_conf.txmode.mq_mode =
1318                                 ETH_MQ_TX_VMDQ_ONLY;
1319                         break;
1320                 }
1321
1322                 /* check valid queue number */
1323                 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) ||
1324                     (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) {
1325                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1326                                         " nb_rx_q=%d nb_tx_q=%d queue number"
1327                                         " must be less than or equal to %d.",
1328                                         nb_rx_q, nb_tx_q,
1329                                         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool);
1330                         return -EINVAL;
1331                 }
1332         } else {
1333                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
1334                         PMD_INIT_LOG(ERR, "VMDQ+DCB+RSS mq_mode is"
1335                                           " not supported.");
1336                         return -EINVAL;
1337                 }
1338                 /* check configuration for vmdb+dcb mode */
1339                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB) {
1340                         const struct rte_eth_vmdq_dcb_conf *conf;
1341
1342                         if (nb_rx_q != TXGBE_VMDQ_DCB_NB_QUEUES) {
1343                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.",
1344                                                 TXGBE_VMDQ_DCB_NB_QUEUES);
1345                                 return -EINVAL;
1346                         }
1347                         conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf;
1348                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
1349                                conf->nb_queue_pools == ETH_32_POOLS)) {
1350                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
1351                                                 " nb_queue_pools must be %d or %d.",
1352                                                 ETH_16_POOLS, ETH_32_POOLS);
1353                                 return -EINVAL;
1354                         }
1355                 }
1356                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) {
1357                         const struct rte_eth_vmdq_dcb_tx_conf *conf;
1358
1359                         if (nb_tx_q != TXGBE_VMDQ_DCB_NB_QUEUES) {
1360                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d",
1361                                                  TXGBE_VMDQ_DCB_NB_QUEUES);
1362                                 return -EINVAL;
1363                         }
1364                         conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf;
1365                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
1366                                conf->nb_queue_pools == ETH_32_POOLS)) {
1367                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
1368                                                 " nb_queue_pools != %d and"
1369                                                 " nb_queue_pools != %d.",
1370                                                 ETH_16_POOLS, ETH_32_POOLS);
1371                                 return -EINVAL;
1372                         }
1373                 }
1374
1375                 /* For DCB mode check our configuration before we go further */
1376                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_DCB) {
1377                         const struct rte_eth_dcb_rx_conf *conf;
1378
1379                         conf = &dev_conf->rx_adv_conf.dcb_rx_conf;
1380                         if (!(conf->nb_tcs == ETH_4_TCS ||
1381                                conf->nb_tcs == ETH_8_TCS)) {
1382                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
1383                                                 " and nb_tcs != %d.",
1384                                                 ETH_4_TCS, ETH_8_TCS);
1385                                 return -EINVAL;
1386                         }
1387                 }
1388
1389                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_DCB) {
1390                         const struct rte_eth_dcb_tx_conf *conf;
1391
1392                         conf = &dev_conf->tx_adv_conf.dcb_tx_conf;
1393                         if (!(conf->nb_tcs == ETH_4_TCS ||
1394                                conf->nb_tcs == ETH_8_TCS)) {
1395                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
1396                                                 " and nb_tcs != %d.",
1397                                                 ETH_4_TCS, ETH_8_TCS);
1398                                 return -EINVAL;
1399                         }
1400                 }
1401         }
1402         return 0;
1403 }
1404
1405 static int
1406 txgbe_dev_configure(struct rte_eth_dev *dev)
1407 {
1408         struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);
1409         struct txgbe_adapter *adapter = TXGBE_DEV_ADAPTER(dev);
1410         int ret;
1411
1412         PMD_INIT_FUNC_TRACE();
1413
1414         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
1415                 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
1416
1417         /* multiple queue mode checking */
1418         ret  = txgbe_check_mq_mode(dev);
1419         if (ret != 0) {
1420                 PMD_DRV_LOG(ERR, "txgbe_check_mq_mode fails with %d.",
1421                             ret);
1422                 return ret;
1423         }
1424
1425         /* set flag to update link status after init */
1426         intr->flags |= TXGBE_FLAG_NEED_LINK_UPDATE;
1427
1428         /*
1429          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
1430          * allocation Rx preconditions we will reset it.
1431          */
1432         adapter->rx_bulk_alloc_allowed = true;
1433
1434         return 0;
1435 }
1436
1437 static void
1438 txgbe_dev_phy_intr_setup(struct rte_eth_dev *dev)
1439 {
1440         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
1441         struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);
1442         uint32_t gpie;
1443
1444         gpie = rd32(hw, TXGBE_GPIOINTEN);
1445         gpie |= TXGBE_GPIOBIT_6;
1446         wr32(hw, TXGBE_GPIOINTEN, gpie);
1447         intr->mask_misc |= TXGBE_ICRMISC_GPIO;
1448 }
1449
1450 int
1451 txgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
1452                         uint16_t tx_rate, uint64_t q_msk)
1453 {
1454         struct txgbe_hw *hw;
1455         struct txgbe_vf_info *vfinfo;
1456         struct rte_eth_link link;
1457         uint8_t  nb_q_per_pool;
1458         uint32_t queue_stride;
1459         uint32_t queue_idx, idx = 0, vf_idx;
1460         uint32_t queue_end;
1461         uint16_t total_rate = 0;
1462         struct rte_pci_device *pci_dev;
1463         int ret;
1464
1465         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1466         ret = rte_eth_link_get_nowait(dev->data->port_id, &link);
1467         if (ret < 0)
1468                 return ret;
1469
1470         if (vf >= pci_dev->max_vfs)
1471                 return -EINVAL;
1472
1473         if (tx_rate > link.link_speed)
1474                 return -EINVAL;
1475
1476         if (q_msk == 0)
1477                 return 0;
1478
1479         hw = TXGBE_DEV_HW(dev);
1480         vfinfo = *(TXGBE_DEV_VFDATA(dev));
1481         nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
1482         queue_stride = TXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
1483         queue_idx = vf * queue_stride;
1484         queue_end = queue_idx + nb_q_per_pool - 1;
1485         if (queue_end >= hw->mac.max_tx_queues)
1486                 return -EINVAL;
1487
1488         if (vfinfo) {
1489                 for (vf_idx = 0; vf_idx < pci_dev->max_vfs; vf_idx++) {
1490                         if (vf_idx == vf)
1491                                 continue;
1492                         for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
1493                                 idx++)
1494                                 total_rate += vfinfo[vf_idx].tx_rate[idx];
1495                 }
1496         } else {
1497                 return -EINVAL;
1498         }
1499
1500         /* Store tx_rate for this vf. */
1501         for (idx = 0; idx < nb_q_per_pool; idx++) {
1502                 if (((uint64_t)0x1 << idx) & q_msk) {
1503                         if (vfinfo[vf].tx_rate[idx] != tx_rate)
1504                                 vfinfo[vf].tx_rate[idx] = tx_rate;
1505                         total_rate += tx_rate;
1506                 }
1507         }
1508
1509         if (total_rate > dev->data->dev_link.link_speed) {
1510                 /* Reset stored TX rate of the VF if it causes exceed
1511                  * link speed.
1512                  */
1513                 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
1514                 return -EINVAL;
1515         }
1516
1517         /* Set ARBTXRATE of each queue/pool for vf X  */
1518         for (; queue_idx <= queue_end; queue_idx++) {
1519                 if (0x1 & q_msk)
1520                         txgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
1521                 q_msk = q_msk >> 1;
1522         }
1523
1524         return 0;
1525 }
1526
1527 /*
1528  * Configure device link speed and setup link.
1529  * It returns 0 on success.
1530  */
1531 static int
1532 txgbe_dev_start(struct rte_eth_dev *dev)
1533 {
1534         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
1535         struct txgbe_hw_stats *hw_stats = TXGBE_DEV_STATS(dev);
1536         struct txgbe_vf_info *vfinfo = *TXGBE_DEV_VFDATA(dev);
1537         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1538         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1539         uint32_t intr_vector = 0;
1540         int err;
1541         bool link_up = false, negotiate = 0;
1542         uint32_t speed = 0;
1543         uint32_t allowed_speeds = 0;
1544         int mask = 0;
1545         int status;
1546         uint16_t vf, idx;
1547         uint32_t *link_speeds;
1548
1549         PMD_INIT_FUNC_TRACE();
1550
1551         /* TXGBE devices don't support:
1552          *    - half duplex (checked afterwards for valid speeds)
1553          *    - fixed speed: TODO implement
1554          */
1555         if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
1556                 PMD_INIT_LOG(ERR,
1557                 "Invalid link_speeds for port %u, fix speed not supported",
1558                                 dev->data->port_id);
1559                 return -EINVAL;
1560         }
1561
1562         /* Stop the link setup handler before resetting the HW. */
1563         rte_eal_alarm_cancel(txgbe_dev_setup_link_alarm_handler, dev);
1564
1565         /* disable uio/vfio intr/eventfd mapping */
1566         rte_intr_disable(intr_handle);
1567
1568         /* stop adapter */
1569         hw->adapter_stopped = 0;
1570         txgbe_stop_hw(hw);
1571
1572         /* reinitialize adapter
1573          * this calls reset and start
1574          */
1575         hw->nb_rx_queues = dev->data->nb_rx_queues;
1576         hw->nb_tx_queues = dev->data->nb_tx_queues;
1577         status = txgbe_pf_reset_hw(hw);
1578         if (status != 0)
1579                 return -1;
1580         hw->mac.start_hw(hw);
1581         hw->mac.get_link_status = true;
1582
1583         /* configure PF module if SRIOV enabled */
1584         txgbe_pf_host_configure(dev);
1585
1586         txgbe_dev_phy_intr_setup(dev);
1587
1588         /* check and configure queue intr-vector mapping */
1589         if ((rte_intr_cap_multiple(intr_handle) ||
1590              !RTE_ETH_DEV_SRIOV(dev).active) &&
1591             dev->data->dev_conf.intr_conf.rxq != 0) {
1592                 intr_vector = dev->data->nb_rx_queues;
1593                 if (rte_intr_efd_enable(intr_handle, intr_vector))
1594                         return -1;
1595         }
1596
1597         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1598                 intr_handle->intr_vec =
1599                         rte_zmalloc("intr_vec",
1600                                     dev->data->nb_rx_queues * sizeof(int), 0);
1601                 if (intr_handle->intr_vec == NULL) {
1602                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
1603                                      " intr_vec", dev->data->nb_rx_queues);
1604                         return -ENOMEM;
1605                 }
1606         }
1607
1608         /* confiugre msix for sleep until rx interrupt */
1609         txgbe_configure_msix(dev);
1610
1611         /* initialize transmission unit */
1612         txgbe_dev_tx_init(dev);
1613
1614         /* This can fail when allocating mbufs for descriptor rings */
1615         err = txgbe_dev_rx_init(dev);
1616         if (err) {
1617                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
1618                 goto error;
1619         }
1620
1621         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
1622                 ETH_VLAN_EXTEND_MASK;
1623         err = txgbe_vlan_offload_config(dev, mask);
1624         if (err) {
1625                 PMD_INIT_LOG(ERR, "Unable to set VLAN offload");
1626                 goto error;
1627         }
1628
1629         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1630                 /* Enable vlan filtering for VMDq */
1631                 txgbe_vmdq_vlan_hw_filter_enable(dev);
1632         }
1633
1634         /* Configure DCB hw */
1635         txgbe_configure_pb(dev);
1636         txgbe_configure_port(dev);
1637         txgbe_configure_dcb(dev);
1638
1639         if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
1640                 err = txgbe_fdir_configure(dev);
1641                 if (err)
1642                         goto error;
1643         }
1644
1645         /* Restore vf rate limit */
1646         if (vfinfo != NULL) {
1647                 for (vf = 0; vf < pci_dev->max_vfs; vf++)
1648                         for (idx = 0; idx < TXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
1649                                 if (vfinfo[vf].tx_rate[idx] != 0)
1650                                         txgbe_set_vf_rate_limit(dev, vf,
1651                                                 vfinfo[vf].tx_rate[idx],
1652                                                 1 << idx);
1653         }
1654
1655         err = txgbe_dev_rxtx_start(dev);
1656         if (err < 0) {
1657                 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
1658                 goto error;
1659         }
1660
1661         /* Skip link setup if loopback mode is enabled. */
1662         if (hw->mac.type == txgbe_mac_raptor &&
1663             dev->data->dev_conf.lpbk_mode)
1664                 goto skip_link_setup;
1665
1666         if (txgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
1667                 err = hw->mac.setup_sfp(hw);
1668                 if (err)
1669                         goto error;
1670         }
1671
1672         if (hw->phy.media_type == txgbe_media_type_copper) {
1673                 /* Turn on the copper */
1674                 hw->phy.set_phy_power(hw, true);
1675         } else {
1676                 /* Turn on the laser */
1677                 hw->mac.enable_tx_laser(hw);
1678         }
1679
1680         err = hw->mac.check_link(hw, &speed, &link_up, 0);
1681         if (err)
1682                 goto error;
1683         dev->data->dev_link.link_status = link_up;
1684
1685         err = hw->mac.get_link_capabilities(hw, &speed, &negotiate);
1686         if (err)
1687                 goto error;
1688
1689         allowed_speeds = ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
1690                         ETH_LINK_SPEED_10G;
1691
1692         link_speeds = &dev->data->dev_conf.link_speeds;
1693         if (*link_speeds & ~allowed_speeds) {
1694                 PMD_INIT_LOG(ERR, "Invalid link setting");
1695                 goto error;
1696         }
1697
1698         speed = 0x0;
1699         if (*link_speeds == ETH_LINK_SPEED_AUTONEG) {
1700                 speed = (TXGBE_LINK_SPEED_100M_FULL |
1701                          TXGBE_LINK_SPEED_1GB_FULL |
1702                          TXGBE_LINK_SPEED_10GB_FULL);
1703         } else {
1704                 if (*link_speeds & ETH_LINK_SPEED_10G)
1705                         speed |= TXGBE_LINK_SPEED_10GB_FULL;
1706                 if (*link_speeds & ETH_LINK_SPEED_5G)
1707                         speed |= TXGBE_LINK_SPEED_5GB_FULL;
1708                 if (*link_speeds & ETH_LINK_SPEED_2_5G)
1709                         speed |= TXGBE_LINK_SPEED_2_5GB_FULL;
1710                 if (*link_speeds & ETH_LINK_SPEED_1G)
1711                         speed |= TXGBE_LINK_SPEED_1GB_FULL;
1712                 if (*link_speeds & ETH_LINK_SPEED_100M)
1713                         speed |= TXGBE_LINK_SPEED_100M_FULL;
1714         }
1715
1716         err = hw->mac.setup_link(hw, speed, link_up);
1717         if (err)
1718                 goto error;
1719
1720 skip_link_setup:
1721
1722         if (rte_intr_allow_others(intr_handle)) {
1723                 /* check if lsc interrupt is enabled */
1724                 if (dev->data->dev_conf.intr_conf.lsc != 0)
1725                         txgbe_dev_lsc_interrupt_setup(dev, TRUE);
1726                 else
1727                         txgbe_dev_lsc_interrupt_setup(dev, FALSE);
1728                 txgbe_dev_macsec_interrupt_setup(dev);
1729                 txgbe_set_ivar_map(hw, -1, 1, TXGBE_MISC_VEC_ID);
1730         } else {
1731                 rte_intr_callback_unregister(intr_handle,
1732                                              txgbe_dev_interrupt_handler, dev);
1733                 if (dev->data->dev_conf.intr_conf.lsc != 0)
1734                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
1735                                      " no intr multiplex");
1736         }
1737
1738         /* check if rxq interrupt is enabled */
1739         if (dev->data->dev_conf.intr_conf.rxq != 0 &&
1740             rte_intr_dp_is_en(intr_handle))
1741                 txgbe_dev_rxq_interrupt_setup(dev);
1742
1743         /* enable uio/vfio intr/eventfd mapping */
1744         rte_intr_enable(intr_handle);
1745
1746         /* resume enabled intr since hw reset */
1747         txgbe_enable_intr(dev);
1748         txgbe_l2_tunnel_conf(dev);
1749         txgbe_filter_restore(dev);
1750
1751         /*
1752          * Update link status right before return, because it may
1753          * start link configuration process in a separate thread.
1754          */
1755         txgbe_dev_link_update(dev, 0);
1756
1757         wr32m(hw, TXGBE_LEDCTL, 0xFFFFFFFF, TXGBE_LEDCTL_ORD_MASK);
1758
1759         txgbe_read_stats_registers(hw, hw_stats);
1760         hw->offset_loaded = 1;
1761
1762         return 0;
1763
1764 error:
1765         PMD_INIT_LOG(ERR, "failure in dev start: %d", err);
1766         txgbe_dev_clear_queues(dev);
1767         return -EIO;
1768 }
1769
1770 /*
1771  * Stop device: disable rx and tx functions to allow for reconfiguring.
1772  */
1773 static int
1774 txgbe_dev_stop(struct rte_eth_dev *dev)
1775 {
1776         struct rte_eth_link link;
1777         struct txgbe_adapter *adapter = TXGBE_DEV_ADAPTER(dev);
1778         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
1779         struct txgbe_vf_info *vfinfo = *TXGBE_DEV_VFDATA(dev);
1780         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1781         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1782         int vf;
1783
1784         if (hw->adapter_stopped)
1785                 return 0;
1786
1787         PMD_INIT_FUNC_TRACE();
1788
1789         rte_eal_alarm_cancel(txgbe_dev_setup_link_alarm_handler, dev);
1790
1791         /* disable interrupts */
1792         txgbe_disable_intr(hw);
1793
1794         /* reset the NIC */
1795         txgbe_pf_reset_hw(hw);
1796         hw->adapter_stopped = 0;
1797
1798         /* stop adapter */
1799         txgbe_stop_hw(hw);
1800
1801         for (vf = 0; vfinfo != NULL && vf < pci_dev->max_vfs; vf++)
1802                 vfinfo[vf].clear_to_send = false;
1803
1804         if (hw->phy.media_type == txgbe_media_type_copper) {
1805                 /* Turn off the copper */
1806                 hw->phy.set_phy_power(hw, false);
1807         } else {
1808                 /* Turn off the laser */
1809                 hw->mac.disable_tx_laser(hw);
1810         }
1811
1812         txgbe_dev_clear_queues(dev);
1813
1814         /* Clear stored conf */
1815         dev->data->scattered_rx = 0;
1816         dev->data->lro = 0;
1817
1818         /* Clear recorded link status */
1819         memset(&link, 0, sizeof(link));
1820         rte_eth_linkstatus_set(dev, &link);
1821
1822         if (!rte_intr_allow_others(intr_handle))
1823                 /* resume to the default handler */
1824                 rte_intr_callback_register(intr_handle,
1825                                            txgbe_dev_interrupt_handler,
1826                                            (void *)dev);
1827
1828         /* Clean datapath event and queue/vec mapping */
1829         rte_intr_efd_disable(intr_handle);
1830         if (intr_handle->intr_vec != NULL) {
1831                 rte_free(intr_handle->intr_vec);
1832                 intr_handle->intr_vec = NULL;
1833         }
1834
1835         adapter->rss_reta_updated = 0;
1836         wr32m(hw, TXGBE_LEDCTL, 0xFFFFFFFF, TXGBE_LEDCTL_SEL_MASK);
1837
1838         hw->adapter_stopped = true;
1839         dev->data->dev_started = 0;
1840
1841         return 0;
1842 }
1843
1844 /*
1845  * Set device link up: enable tx.
1846  */
1847 static int
1848 txgbe_dev_set_link_up(struct rte_eth_dev *dev)
1849 {
1850         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
1851
1852         if (hw->phy.media_type == txgbe_media_type_copper) {
1853                 /* Turn on the copper */
1854                 hw->phy.set_phy_power(hw, true);
1855         } else {
1856                 /* Turn on the laser */
1857                 hw->mac.enable_tx_laser(hw);
1858                 txgbe_dev_link_update(dev, 0);
1859         }
1860
1861         return 0;
1862 }
1863
1864 /*
1865  * Set device link down: disable tx.
1866  */
1867 static int
1868 txgbe_dev_set_link_down(struct rte_eth_dev *dev)
1869 {
1870         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
1871
1872         if (hw->phy.media_type == txgbe_media_type_copper) {
1873                 /* Turn off the copper */
1874                 hw->phy.set_phy_power(hw, false);
1875         } else {
1876                 /* Turn off the laser */
1877                 hw->mac.disable_tx_laser(hw);
1878                 txgbe_dev_link_update(dev, 0);
1879         }
1880
1881         return 0;
1882 }
1883
1884 /*
1885  * Reset and stop device.
1886  */
1887 static int
1888 txgbe_dev_close(struct rte_eth_dev *dev)
1889 {
1890         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
1891         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1892         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1893         int retries = 0;
1894         int ret;
1895
1896         PMD_INIT_FUNC_TRACE();
1897
1898         txgbe_pf_reset_hw(hw);
1899
1900         ret = txgbe_dev_stop(dev);
1901
1902         txgbe_dev_free_queues(dev);
1903
1904         /* reprogram the RAR[0] in case user changed it. */
1905         txgbe_set_rar(hw, 0, hw->mac.addr, 0, true);
1906
1907         /* Unlock any pending hardware semaphore */
1908         txgbe_swfw_lock_reset(hw);
1909
1910         /* disable uio intr before callback unregister */
1911         rte_intr_disable(intr_handle);
1912
1913         do {
1914                 ret = rte_intr_callback_unregister(intr_handle,
1915                                 txgbe_dev_interrupt_handler, dev);
1916                 if (ret >= 0 || ret == -ENOENT) {
1917                         break;
1918                 } else if (ret != -EAGAIN) {
1919                         PMD_INIT_LOG(ERR,
1920                                 "intr callback unregister failed: %d",
1921                                 ret);
1922                 }
1923                 rte_delay_ms(100);
1924         } while (retries++ < (10 + TXGBE_LINK_UP_TIME));
1925
1926         /* cancel the delay handler before remove dev */
1927         rte_eal_alarm_cancel(txgbe_dev_interrupt_delayed_handler, dev);
1928
1929         /* uninitialize PF if max_vfs not zero */
1930         txgbe_pf_host_uninit(dev);
1931
1932         rte_free(dev->data->mac_addrs);
1933         dev->data->mac_addrs = NULL;
1934
1935         rte_free(dev->data->hash_mac_addrs);
1936         dev->data->hash_mac_addrs = NULL;
1937
1938         /* remove all the fdir filters & hash */
1939         txgbe_fdir_filter_uninit(dev);
1940
1941         /* remove all the L2 tunnel filters & hash */
1942         txgbe_l2_tn_filter_uninit(dev);
1943
1944         /* Remove all ntuple filters of the device */
1945         txgbe_ntuple_filter_uninit(dev);
1946
1947         /* clear all the filters list */
1948         txgbe_filterlist_flush();
1949
1950         return ret;
1951 }
1952
1953 /*
1954  * Reset PF device.
1955  */
1956 static int
1957 txgbe_dev_reset(struct rte_eth_dev *dev)
1958 {
1959         int ret;
1960
1961         /* When a DPDK PMD PF begin to reset PF port, it should notify all
1962          * its VF to make them align with it. The detailed notification
1963          * mechanism is PMD specific. As to txgbe PF, it is rather complex.
1964          * To avoid unexpected behavior in VF, currently reset of PF with
1965          * SR-IOV activation is not supported. It might be supported later.
1966          */
1967         if (dev->data->sriov.active)
1968                 return -ENOTSUP;
1969
1970         ret = eth_txgbe_dev_uninit(dev);
1971         if (ret)
1972                 return ret;
1973
1974         ret = eth_txgbe_dev_init(dev, NULL);
1975
1976         return ret;
1977 }
1978
1979 #define UPDATE_QP_COUNTER_32bit(reg, last_counter, counter)     \
1980         {                                                       \
1981                 uint32_t current_counter = rd32(hw, reg);       \
1982                 if (current_counter < last_counter)             \
1983                         current_counter += 0x100000000LL;       \
1984                 if (!hw->offset_loaded)                         \
1985                         last_counter = current_counter;         \
1986                 counter = current_counter - last_counter;       \
1987                 counter &= 0xFFFFFFFFLL;                        \
1988         }
1989
1990 #define UPDATE_QP_COUNTER_36bit(reg_lsb, reg_msb, last_counter, counter) \
1991         {                                                                \
1992                 uint64_t current_counter_lsb = rd32(hw, reg_lsb);        \
1993                 uint64_t current_counter_msb = rd32(hw, reg_msb);        \
1994                 uint64_t current_counter = (current_counter_msb << 32) | \
1995                         current_counter_lsb;                             \
1996                 if (current_counter < last_counter)                      \
1997                         current_counter += 0x1000000000LL;               \
1998                 if (!hw->offset_loaded)                                  \
1999                         last_counter = current_counter;                  \
2000                 counter = current_counter - last_counter;                \
2001                 counter &= 0xFFFFFFFFFLL;                                \
2002         }
2003
2004 void
2005 txgbe_read_stats_registers(struct txgbe_hw *hw,
2006                            struct txgbe_hw_stats *hw_stats)
2007 {
2008         unsigned int i;
2009
2010         /* QP Stats */
2011         for (i = 0; i < hw->nb_rx_queues; i++) {
2012                 UPDATE_QP_COUNTER_32bit(TXGBE_QPRXPKT(i),
2013                         hw->qp_last[i].rx_qp_packets,
2014                         hw_stats->qp[i].rx_qp_packets);
2015                 UPDATE_QP_COUNTER_36bit(TXGBE_QPRXOCTL(i), TXGBE_QPRXOCTH(i),
2016                         hw->qp_last[i].rx_qp_bytes,
2017                         hw_stats->qp[i].rx_qp_bytes);
2018                 UPDATE_QP_COUNTER_32bit(TXGBE_QPRXMPKT(i),
2019                         hw->qp_last[i].rx_qp_mc_packets,
2020                         hw_stats->qp[i].rx_qp_mc_packets);
2021         }
2022
2023         for (i = 0; i < hw->nb_tx_queues; i++) {
2024                 UPDATE_QP_COUNTER_32bit(TXGBE_QPTXPKT(i),
2025                         hw->qp_last[i].tx_qp_packets,
2026                         hw_stats->qp[i].tx_qp_packets);
2027                 UPDATE_QP_COUNTER_36bit(TXGBE_QPTXOCTL(i), TXGBE_QPTXOCTH(i),
2028                         hw->qp_last[i].tx_qp_bytes,
2029                         hw_stats->qp[i].tx_qp_bytes);
2030         }
2031         /* PB Stats */
2032         for (i = 0; i < TXGBE_MAX_UP; i++) {
2033                 hw_stats->up[i].rx_up_xon_packets +=
2034                                 rd32(hw, TXGBE_PBRXUPXON(i));
2035                 hw_stats->up[i].rx_up_xoff_packets +=
2036                                 rd32(hw, TXGBE_PBRXUPXOFF(i));
2037                 hw_stats->up[i].tx_up_xon_packets +=
2038                                 rd32(hw, TXGBE_PBTXUPXON(i));
2039                 hw_stats->up[i].tx_up_xoff_packets +=
2040                                 rd32(hw, TXGBE_PBTXUPXOFF(i));
2041                 hw_stats->up[i].tx_up_xon2off_packets +=
2042                                 rd32(hw, TXGBE_PBTXUPOFF(i));
2043                 hw_stats->up[i].rx_up_dropped +=
2044                                 rd32(hw, TXGBE_PBRXMISS(i));
2045         }
2046         hw_stats->rx_xon_packets += rd32(hw, TXGBE_PBRXLNKXON);
2047         hw_stats->rx_xoff_packets += rd32(hw, TXGBE_PBRXLNKXOFF);
2048         hw_stats->tx_xon_packets += rd32(hw, TXGBE_PBTXLNKXON);
2049         hw_stats->tx_xoff_packets += rd32(hw, TXGBE_PBTXLNKXOFF);
2050
2051         /* DMA Stats */
2052         hw_stats->rx_packets += rd32(hw, TXGBE_DMARXPKT);
2053         hw_stats->tx_packets += rd32(hw, TXGBE_DMATXPKT);
2054
2055         hw_stats->rx_bytes += rd64(hw, TXGBE_DMARXOCTL);
2056         hw_stats->tx_bytes += rd64(hw, TXGBE_DMATXOCTL);
2057         hw_stats->rx_drop_packets += rd32(hw, TXGBE_PBRXDROP);
2058
2059         /* MAC Stats */
2060         hw_stats->rx_crc_errors += rd64(hw, TXGBE_MACRXERRCRCL);
2061         hw_stats->rx_multicast_packets += rd64(hw, TXGBE_MACRXMPKTL);
2062         hw_stats->tx_multicast_packets += rd64(hw, TXGBE_MACTXMPKTL);
2063
2064         hw_stats->rx_total_packets += rd64(hw, TXGBE_MACRXPKTL);
2065         hw_stats->tx_total_packets += rd64(hw, TXGBE_MACTXPKTL);
2066         hw_stats->rx_total_bytes += rd64(hw, TXGBE_MACRXGBOCTL);
2067
2068         hw_stats->rx_broadcast_packets += rd64(hw, TXGBE_MACRXOCTL);
2069         hw_stats->tx_broadcast_packets += rd32(hw, TXGBE_MACTXOCTL);
2070
2071         hw_stats->rx_size_64_packets += rd64(hw, TXGBE_MACRX1TO64L);
2072         hw_stats->rx_size_65_to_127_packets += rd64(hw, TXGBE_MACRX65TO127L);
2073         hw_stats->rx_size_128_to_255_packets += rd64(hw, TXGBE_MACRX128TO255L);
2074         hw_stats->rx_size_256_to_511_packets += rd64(hw, TXGBE_MACRX256TO511L);
2075         hw_stats->rx_size_512_to_1023_packets +=
2076                         rd64(hw, TXGBE_MACRX512TO1023L);
2077         hw_stats->rx_size_1024_to_max_packets +=
2078                         rd64(hw, TXGBE_MACRX1024TOMAXL);
2079         hw_stats->tx_size_64_packets += rd64(hw, TXGBE_MACTX1TO64L);
2080         hw_stats->tx_size_65_to_127_packets += rd64(hw, TXGBE_MACTX65TO127L);
2081         hw_stats->tx_size_128_to_255_packets += rd64(hw, TXGBE_MACTX128TO255L);
2082         hw_stats->tx_size_256_to_511_packets += rd64(hw, TXGBE_MACTX256TO511L);
2083         hw_stats->tx_size_512_to_1023_packets +=
2084                         rd64(hw, TXGBE_MACTX512TO1023L);
2085         hw_stats->tx_size_1024_to_max_packets +=
2086                         rd64(hw, TXGBE_MACTX1024TOMAXL);
2087
2088         hw_stats->rx_undersize_errors += rd64(hw, TXGBE_MACRXERRLENL);
2089         hw_stats->rx_oversize_errors += rd32(hw, TXGBE_MACRXOVERSIZE);
2090         hw_stats->rx_jabber_errors += rd32(hw, TXGBE_MACRXJABBER);
2091
2092         /* MNG Stats */
2093         hw_stats->mng_bmc2host_packets = rd32(hw, TXGBE_MNGBMC2OS);
2094         hw_stats->mng_host2bmc_packets = rd32(hw, TXGBE_MNGOS2BMC);
2095         hw_stats->rx_management_packets = rd32(hw, TXGBE_DMARXMNG);
2096         hw_stats->tx_management_packets = rd32(hw, TXGBE_DMATXMNG);
2097
2098         /* FCoE Stats */
2099         hw_stats->rx_fcoe_crc_errors += rd32(hw, TXGBE_FCOECRC);
2100         hw_stats->rx_fcoe_mbuf_allocation_errors += rd32(hw, TXGBE_FCOELAST);
2101         hw_stats->rx_fcoe_dropped += rd32(hw, TXGBE_FCOERPDC);
2102         hw_stats->rx_fcoe_packets += rd32(hw, TXGBE_FCOEPRC);
2103         hw_stats->tx_fcoe_packets += rd32(hw, TXGBE_FCOEPTC);
2104         hw_stats->rx_fcoe_bytes += rd32(hw, TXGBE_FCOEDWRC);
2105         hw_stats->tx_fcoe_bytes += rd32(hw, TXGBE_FCOEDWTC);
2106
2107         /* Flow Director Stats */
2108         hw_stats->flow_director_matched_filters += rd32(hw, TXGBE_FDIRMATCH);
2109         hw_stats->flow_director_missed_filters += rd32(hw, TXGBE_FDIRMISS);
2110         hw_stats->flow_director_added_filters +=
2111                 TXGBE_FDIRUSED_ADD(rd32(hw, TXGBE_FDIRUSED));
2112         hw_stats->flow_director_removed_filters +=
2113                 TXGBE_FDIRUSED_REM(rd32(hw, TXGBE_FDIRUSED));
2114         hw_stats->flow_director_filter_add_errors +=
2115                 TXGBE_FDIRFAIL_ADD(rd32(hw, TXGBE_FDIRFAIL));
2116         hw_stats->flow_director_filter_remove_errors +=
2117                 TXGBE_FDIRFAIL_REM(rd32(hw, TXGBE_FDIRFAIL));
2118
2119         /* MACsec Stats */
2120         hw_stats->tx_macsec_pkts_untagged += rd32(hw, TXGBE_LSECTX_UTPKT);
2121         hw_stats->tx_macsec_pkts_encrypted +=
2122                         rd32(hw, TXGBE_LSECTX_ENCPKT);
2123         hw_stats->tx_macsec_pkts_protected +=
2124                         rd32(hw, TXGBE_LSECTX_PROTPKT);
2125         hw_stats->tx_macsec_octets_encrypted +=
2126                         rd32(hw, TXGBE_LSECTX_ENCOCT);
2127         hw_stats->tx_macsec_octets_protected +=
2128                         rd32(hw, TXGBE_LSECTX_PROTOCT);
2129         hw_stats->rx_macsec_pkts_untagged += rd32(hw, TXGBE_LSECRX_UTPKT);
2130         hw_stats->rx_macsec_pkts_badtag += rd32(hw, TXGBE_LSECRX_BTPKT);
2131         hw_stats->rx_macsec_pkts_nosci += rd32(hw, TXGBE_LSECRX_NOSCIPKT);
2132         hw_stats->rx_macsec_pkts_unknownsci += rd32(hw, TXGBE_LSECRX_UNSCIPKT);
2133         hw_stats->rx_macsec_octets_decrypted += rd32(hw, TXGBE_LSECRX_DECOCT);
2134         hw_stats->rx_macsec_octets_validated += rd32(hw, TXGBE_LSECRX_VLDOCT);
2135         hw_stats->rx_macsec_sc_pkts_unchecked +=
2136                         rd32(hw, TXGBE_LSECRX_UNCHKPKT);
2137         hw_stats->rx_macsec_sc_pkts_delayed += rd32(hw, TXGBE_LSECRX_DLYPKT);
2138         hw_stats->rx_macsec_sc_pkts_late += rd32(hw, TXGBE_LSECRX_LATEPKT);
2139         for (i = 0; i < 2; i++) {
2140                 hw_stats->rx_macsec_sa_pkts_ok +=
2141                         rd32(hw, TXGBE_LSECRX_OKPKT(i));
2142                 hw_stats->rx_macsec_sa_pkts_invalid +=
2143                         rd32(hw, TXGBE_LSECRX_INVPKT(i));
2144                 hw_stats->rx_macsec_sa_pkts_notvalid +=
2145                         rd32(hw, TXGBE_LSECRX_BADPKT(i));
2146         }
2147         hw_stats->rx_macsec_sa_pkts_unusedsa +=
2148                         rd32(hw, TXGBE_LSECRX_INVSAPKT);
2149         hw_stats->rx_macsec_sa_pkts_notusingsa +=
2150                         rd32(hw, TXGBE_LSECRX_BADSAPKT);
2151
2152         hw_stats->rx_total_missed_packets = 0;
2153         for (i = 0; i < TXGBE_MAX_UP; i++) {
2154                 hw_stats->rx_total_missed_packets +=
2155                         hw_stats->up[i].rx_up_dropped;
2156         }
2157 }
2158
2159 static int
2160 txgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2161 {
2162         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2163         struct txgbe_hw_stats *hw_stats = TXGBE_DEV_STATS(dev);
2164         struct txgbe_stat_mappings *stat_mappings =
2165                         TXGBE_DEV_STAT_MAPPINGS(dev);
2166         uint32_t i, j;
2167
2168         txgbe_read_stats_registers(hw, hw_stats);
2169
2170         if (stats == NULL)
2171                 return -EINVAL;
2172
2173         /* Fill out the rte_eth_stats statistics structure */
2174         stats->ipackets = hw_stats->rx_packets;
2175         stats->ibytes = hw_stats->rx_bytes;
2176         stats->opackets = hw_stats->tx_packets;
2177         stats->obytes = hw_stats->tx_bytes;
2178
2179         memset(&stats->q_ipackets, 0, sizeof(stats->q_ipackets));
2180         memset(&stats->q_opackets, 0, sizeof(stats->q_opackets));
2181         memset(&stats->q_ibytes, 0, sizeof(stats->q_ibytes));
2182         memset(&stats->q_obytes, 0, sizeof(stats->q_obytes));
2183         memset(&stats->q_errors, 0, sizeof(stats->q_errors));
2184         for (i = 0; i < TXGBE_MAX_QP; i++) {
2185                 uint32_t n = i / NB_QMAP_FIELDS_PER_QSM_REG;
2186                 uint32_t offset = (i % NB_QMAP_FIELDS_PER_QSM_REG) * 8;
2187                 uint32_t q_map;
2188
2189                 q_map = (stat_mappings->rqsm[n] >> offset)
2190                                 & QMAP_FIELD_RESERVED_BITS_MASK;
2191                 j = (q_map < RTE_ETHDEV_QUEUE_STAT_CNTRS
2192                      ? q_map : q_map % RTE_ETHDEV_QUEUE_STAT_CNTRS);
2193                 stats->q_ipackets[j] += hw_stats->qp[i].rx_qp_packets;
2194                 stats->q_ibytes[j] += hw_stats->qp[i].rx_qp_bytes;
2195
2196                 q_map = (stat_mappings->tqsm[n] >> offset)
2197                                 & QMAP_FIELD_RESERVED_BITS_MASK;
2198                 j = (q_map < RTE_ETHDEV_QUEUE_STAT_CNTRS
2199                      ? q_map : q_map % RTE_ETHDEV_QUEUE_STAT_CNTRS);
2200                 stats->q_opackets[j] += hw_stats->qp[i].tx_qp_packets;
2201                 stats->q_obytes[j] += hw_stats->qp[i].tx_qp_bytes;
2202         }
2203
2204         /* Rx Errors */
2205         stats->imissed  = hw_stats->rx_total_missed_packets;
2206         stats->ierrors  = hw_stats->rx_crc_errors +
2207                           hw_stats->rx_mac_short_packet_dropped +
2208                           hw_stats->rx_length_errors +
2209                           hw_stats->rx_undersize_errors +
2210                           hw_stats->rx_oversize_errors +
2211                           hw_stats->rx_drop_packets +
2212                           hw_stats->rx_illegal_byte_errors +
2213                           hw_stats->rx_error_bytes +
2214                           hw_stats->rx_fragment_errors +
2215                           hw_stats->rx_fcoe_crc_errors +
2216                           hw_stats->rx_fcoe_mbuf_allocation_errors;
2217
2218         /* Tx Errors */
2219         stats->oerrors  = 0;
2220         return 0;
2221 }
2222
2223 static int
2224 txgbe_dev_stats_reset(struct rte_eth_dev *dev)
2225 {
2226         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2227         struct txgbe_hw_stats *hw_stats = TXGBE_DEV_STATS(dev);
2228
2229         /* HW registers are cleared on read */
2230         hw->offset_loaded = 0;
2231         txgbe_dev_stats_get(dev, NULL);
2232         hw->offset_loaded = 1;
2233
2234         /* Reset software totals */
2235         memset(hw_stats, 0, sizeof(*hw_stats));
2236
2237         return 0;
2238 }
2239
2240 /* This function calculates the number of xstats based on the current config */
2241 static unsigned
2242 txgbe_xstats_calc_num(struct rte_eth_dev *dev)
2243 {
2244         int nb_queues = max(dev->data->nb_rx_queues, dev->data->nb_tx_queues);
2245         return TXGBE_NB_HW_STATS +
2246                TXGBE_NB_UP_STATS * TXGBE_MAX_UP +
2247                TXGBE_NB_QP_STATS * nb_queues;
2248 }
2249
2250 static inline int
2251 txgbe_get_name_by_id(uint32_t id, char *name, uint32_t size)
2252 {
2253         int nb, st;
2254
2255         /* Extended stats from txgbe_hw_stats */
2256         if (id < TXGBE_NB_HW_STATS) {
2257                 snprintf(name, size, "[hw]%s",
2258                         rte_txgbe_stats_strings[id].name);
2259                 return 0;
2260         }
2261         id -= TXGBE_NB_HW_STATS;
2262
2263         /* Priority Stats */
2264         if (id < TXGBE_NB_UP_STATS * TXGBE_MAX_UP) {
2265                 nb = id / TXGBE_NB_UP_STATS;
2266                 st = id % TXGBE_NB_UP_STATS;
2267                 snprintf(name, size, "[p%u]%s", nb,
2268                         rte_txgbe_up_strings[st].name);
2269                 return 0;
2270         }
2271         id -= TXGBE_NB_UP_STATS * TXGBE_MAX_UP;
2272
2273         /* Queue Stats */
2274         if (id < TXGBE_NB_QP_STATS * TXGBE_MAX_QP) {
2275                 nb = id / TXGBE_NB_QP_STATS;
2276                 st = id % TXGBE_NB_QP_STATS;
2277                 snprintf(name, size, "[q%u]%s", nb,
2278                         rte_txgbe_qp_strings[st].name);
2279                 return 0;
2280         }
2281         id -= TXGBE_NB_QP_STATS * TXGBE_MAX_QP;
2282
2283         return -(int)(id + 1);
2284 }
2285
2286 static inline int
2287 txgbe_get_offset_by_id(uint32_t id, uint32_t *offset)
2288 {
2289         int nb, st;
2290
2291         /* Extended stats from txgbe_hw_stats */
2292         if (id < TXGBE_NB_HW_STATS) {
2293                 *offset = rte_txgbe_stats_strings[id].offset;
2294                 return 0;
2295         }
2296         id -= TXGBE_NB_HW_STATS;
2297
2298         /* Priority Stats */
2299         if (id < TXGBE_NB_UP_STATS * TXGBE_MAX_UP) {
2300                 nb = id / TXGBE_NB_UP_STATS;
2301                 st = id % TXGBE_NB_UP_STATS;
2302                 *offset = rte_txgbe_up_strings[st].offset +
2303                         nb * (TXGBE_NB_UP_STATS * sizeof(uint64_t));
2304                 return 0;
2305         }
2306         id -= TXGBE_NB_UP_STATS * TXGBE_MAX_UP;
2307
2308         /* Queue Stats */
2309         if (id < TXGBE_NB_QP_STATS * TXGBE_MAX_QP) {
2310                 nb = id / TXGBE_NB_QP_STATS;
2311                 st = id % TXGBE_NB_QP_STATS;
2312                 *offset = rte_txgbe_qp_strings[st].offset +
2313                         nb * (TXGBE_NB_QP_STATS * sizeof(uint64_t));
2314                 return 0;
2315         }
2316
2317         return -1;
2318 }
2319
2320 static int txgbe_dev_xstats_get_names(struct rte_eth_dev *dev,
2321         struct rte_eth_xstat_name *xstats_names, unsigned int limit)
2322 {
2323         unsigned int i, count;
2324
2325         count = txgbe_xstats_calc_num(dev);
2326         if (xstats_names == NULL)
2327                 return count;
2328
2329         /* Note: limit >= cnt_stats checked upstream
2330          * in rte_eth_xstats_names()
2331          */
2332         limit = min(limit, count);
2333
2334         /* Extended stats from txgbe_hw_stats */
2335         for (i = 0; i < limit; i++) {
2336                 if (txgbe_get_name_by_id(i, xstats_names[i].name,
2337                         sizeof(xstats_names[i].name))) {
2338                         PMD_INIT_LOG(WARNING, "id value %d isn't valid", i);
2339                         break;
2340                 }
2341         }
2342
2343         return i;
2344 }
2345
2346 static int txgbe_dev_xstats_get_names_by_id(struct rte_eth_dev *dev,
2347         struct rte_eth_xstat_name *xstats_names,
2348         const uint64_t *ids,
2349         unsigned int limit)
2350 {
2351         unsigned int i;
2352
2353         if (ids == NULL)
2354                 return txgbe_dev_xstats_get_names(dev, xstats_names, limit);
2355
2356         for (i = 0; i < limit; i++) {
2357                 if (txgbe_get_name_by_id(ids[i], xstats_names[i].name,
2358                                 sizeof(xstats_names[i].name))) {
2359                         PMD_INIT_LOG(WARNING, "id value %d isn't valid", i);
2360                         return -1;
2361                 }
2362         }
2363
2364         return i;
2365 }
2366
2367 static int
2368 txgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2369                                          unsigned int limit)
2370 {
2371         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2372         struct txgbe_hw_stats *hw_stats = TXGBE_DEV_STATS(dev);
2373         unsigned int i, count;
2374
2375         txgbe_read_stats_registers(hw, hw_stats);
2376
2377         /* If this is a reset xstats is NULL, and we have cleared the
2378          * registers by reading them.
2379          */
2380         count = txgbe_xstats_calc_num(dev);
2381         if (xstats == NULL)
2382                 return count;
2383
2384         limit = min(limit, txgbe_xstats_calc_num(dev));
2385
2386         /* Extended stats from txgbe_hw_stats */
2387         for (i = 0; i < limit; i++) {
2388                 uint32_t offset = 0;
2389
2390                 if (txgbe_get_offset_by_id(i, &offset)) {
2391                         PMD_INIT_LOG(WARNING, "id value %d isn't valid", i);
2392                         break;
2393                 }
2394                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) + offset);
2395                 xstats[i].id = i;
2396         }
2397
2398         return i;
2399 }
2400
2401 static int
2402 txgbe_dev_xstats_get_(struct rte_eth_dev *dev, uint64_t *values,
2403                                          unsigned int limit)
2404 {
2405         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2406         struct txgbe_hw_stats *hw_stats = TXGBE_DEV_STATS(dev);
2407         unsigned int i, count;
2408
2409         txgbe_read_stats_registers(hw, hw_stats);
2410
2411         /* If this is a reset xstats is NULL, and we have cleared the
2412          * registers by reading them.
2413          */
2414         count = txgbe_xstats_calc_num(dev);
2415         if (values == NULL)
2416                 return count;
2417
2418         limit = min(limit, txgbe_xstats_calc_num(dev));
2419
2420         /* Extended stats from txgbe_hw_stats */
2421         for (i = 0; i < limit; i++) {
2422                 uint32_t offset;
2423
2424                 if (txgbe_get_offset_by_id(i, &offset)) {
2425                         PMD_INIT_LOG(WARNING, "id value %d isn't valid", i);
2426                         break;
2427                 }
2428                 values[i] = *(uint64_t *)(((char *)hw_stats) + offset);
2429         }
2430
2431         return i;
2432 }
2433
2434 static int
2435 txgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
2436                 uint64_t *values, unsigned int limit)
2437 {
2438         struct txgbe_hw_stats *hw_stats = TXGBE_DEV_STATS(dev);
2439         unsigned int i;
2440
2441         if (ids == NULL)
2442                 return txgbe_dev_xstats_get_(dev, values, limit);
2443
2444         for (i = 0; i < limit; i++) {
2445                 uint32_t offset;
2446
2447                 if (txgbe_get_offset_by_id(ids[i], &offset)) {
2448                         PMD_INIT_LOG(WARNING, "id value %d isn't valid", i);
2449                         break;
2450                 }
2451                 values[i] = *(uint64_t *)(((char *)hw_stats) + offset);
2452         }
2453
2454         return i;
2455 }
2456
2457 static int
2458 txgbe_dev_xstats_reset(struct rte_eth_dev *dev)
2459 {
2460         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2461         struct txgbe_hw_stats *hw_stats = TXGBE_DEV_STATS(dev);
2462
2463         /* HW registers are cleared on read */
2464         hw->offset_loaded = 0;
2465         txgbe_read_stats_registers(hw, hw_stats);
2466         hw->offset_loaded = 1;
2467
2468         /* Reset software totals */
2469         memset(hw_stats, 0, sizeof(*hw_stats));
2470
2471         return 0;
2472 }
2473
2474 static int
2475 txgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
2476 {
2477         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2478         u16 eeprom_verh, eeprom_verl;
2479         u32 etrack_id;
2480         int ret;
2481
2482         hw->rom.readw_sw(hw, TXGBE_EEPROM_VERSION_H, &eeprom_verh);
2483         hw->rom.readw_sw(hw, TXGBE_EEPROM_VERSION_L, &eeprom_verl);
2484
2485         etrack_id = (eeprom_verh << 16) | eeprom_verl;
2486         ret = snprintf(fw_version, fw_size, "0x%08x", etrack_id);
2487
2488         ret += 1; /* add the size of '\0' */
2489         if (fw_size < (u32)ret)
2490                 return ret;
2491         else
2492                 return 0;
2493 }
2494
2495 static int
2496 txgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2497 {
2498         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2499         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2500
2501         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
2502         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
2503         dev_info->min_rx_bufsize = 1024;
2504         dev_info->max_rx_pktlen = 15872;
2505         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
2506         dev_info->max_hash_mac_addrs = TXGBE_VMDQ_NUM_UC_MAC;
2507         dev_info->max_vfs = pci_dev->max_vfs;
2508         dev_info->max_vmdq_pools = ETH_64_POOLS;
2509         dev_info->vmdq_queue_num = dev_info->max_rx_queues;
2510         dev_info->rx_queue_offload_capa = txgbe_get_rx_queue_offloads(dev);
2511         dev_info->rx_offload_capa = (txgbe_get_rx_port_offloads(dev) |
2512                                      dev_info->rx_queue_offload_capa);
2513         dev_info->tx_queue_offload_capa = txgbe_get_tx_queue_offloads(dev);
2514         dev_info->tx_offload_capa = txgbe_get_tx_port_offloads(dev);
2515
2516         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2517                 .rx_thresh = {
2518                         .pthresh = TXGBE_DEFAULT_RX_PTHRESH,
2519                         .hthresh = TXGBE_DEFAULT_RX_HTHRESH,
2520                         .wthresh = TXGBE_DEFAULT_RX_WTHRESH,
2521                 },
2522                 .rx_free_thresh = TXGBE_DEFAULT_RX_FREE_THRESH,
2523                 .rx_drop_en = 0,
2524                 .offloads = 0,
2525         };
2526
2527         dev_info->default_txconf = (struct rte_eth_txconf) {
2528                 .tx_thresh = {
2529                         .pthresh = TXGBE_DEFAULT_TX_PTHRESH,
2530                         .hthresh = TXGBE_DEFAULT_TX_HTHRESH,
2531                         .wthresh = TXGBE_DEFAULT_TX_WTHRESH,
2532                 },
2533                 .tx_free_thresh = TXGBE_DEFAULT_TX_FREE_THRESH,
2534                 .offloads = 0,
2535         };
2536
2537         dev_info->rx_desc_lim = rx_desc_lim;
2538         dev_info->tx_desc_lim = tx_desc_lim;
2539
2540         dev_info->hash_key_size = TXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
2541         dev_info->reta_size = ETH_RSS_RETA_SIZE_128;
2542         dev_info->flow_type_rss_offloads = TXGBE_RSS_OFFLOAD_ALL;
2543
2544         dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
2545         dev_info->speed_capa |= ETH_LINK_SPEED_100M;
2546
2547         /* Driver-preferred Rx/Tx parameters */
2548         dev_info->default_rxportconf.burst_size = 32;
2549         dev_info->default_txportconf.burst_size = 32;
2550         dev_info->default_rxportconf.nb_queues = 1;
2551         dev_info->default_txportconf.nb_queues = 1;
2552         dev_info->default_rxportconf.ring_size = 256;
2553         dev_info->default_txportconf.ring_size = 256;
2554
2555         return 0;
2556 }
2557
2558 const uint32_t *
2559 txgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev)
2560 {
2561         if (dev->rx_pkt_burst == txgbe_recv_pkts ||
2562             dev->rx_pkt_burst == txgbe_recv_pkts_lro_single_alloc ||
2563             dev->rx_pkt_burst == txgbe_recv_pkts_lro_bulk_alloc ||
2564             dev->rx_pkt_burst == txgbe_recv_pkts_bulk_alloc)
2565                 return txgbe_get_supported_ptypes();
2566
2567         return NULL;
2568 }
2569
2570 void
2571 txgbe_dev_setup_link_alarm_handler(void *param)
2572 {
2573         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2574         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2575         struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);
2576         u32 speed;
2577         bool autoneg = false;
2578
2579         speed = hw->phy.autoneg_advertised;
2580         if (!speed)
2581                 hw->mac.get_link_capabilities(hw, &speed, &autoneg);
2582
2583         hw->mac.setup_link(hw, speed, true);
2584
2585         intr->flags &= ~TXGBE_FLAG_NEED_LINK_CONFIG;
2586 }
2587
2588 /* return 0 means link status changed, -1 means not changed */
2589 int
2590 txgbe_dev_link_update_share(struct rte_eth_dev *dev,
2591                             int wait_to_complete)
2592 {
2593         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2594         struct rte_eth_link link;
2595         u32 link_speed = TXGBE_LINK_SPEED_UNKNOWN;
2596         struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);
2597         bool link_up;
2598         int err;
2599         int wait = 1;
2600
2601         memset(&link, 0, sizeof(link));
2602         link.link_status = ETH_LINK_DOWN;
2603         link.link_speed = ETH_SPEED_NUM_NONE;
2604         link.link_duplex = ETH_LINK_HALF_DUPLEX;
2605         link.link_autoneg = ETH_LINK_AUTONEG;
2606
2607         hw->mac.get_link_status = true;
2608
2609         if (intr->flags & TXGBE_FLAG_NEED_LINK_CONFIG)
2610                 return rte_eth_linkstatus_set(dev, &link);
2611
2612         /* check if it needs to wait to complete, if lsc interrupt is enabled */
2613         if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
2614                 wait = 0;
2615
2616         err = hw->mac.check_link(hw, &link_speed, &link_up, wait);
2617
2618         if (err != 0) {
2619                 link.link_speed = ETH_SPEED_NUM_100M;
2620                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
2621                 return rte_eth_linkstatus_set(dev, &link);
2622         }
2623
2624         if (link_up == 0) {
2625                 if (hw->phy.media_type == txgbe_media_type_fiber) {
2626                         intr->flags |= TXGBE_FLAG_NEED_LINK_CONFIG;
2627                         rte_eal_alarm_set(10,
2628                                 txgbe_dev_setup_link_alarm_handler, dev);
2629                 }
2630                 return rte_eth_linkstatus_set(dev, &link);
2631         }
2632
2633         intr->flags &= ~TXGBE_FLAG_NEED_LINK_CONFIG;
2634         link.link_status = ETH_LINK_UP;
2635         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2636
2637         switch (link_speed) {
2638         default:
2639         case TXGBE_LINK_SPEED_UNKNOWN:
2640                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
2641                 link.link_speed = ETH_SPEED_NUM_100M;
2642                 break;
2643
2644         case TXGBE_LINK_SPEED_100M_FULL:
2645                 link.link_speed = ETH_SPEED_NUM_100M;
2646                 break;
2647
2648         case TXGBE_LINK_SPEED_1GB_FULL:
2649                 link.link_speed = ETH_SPEED_NUM_1G;
2650                 break;
2651
2652         case TXGBE_LINK_SPEED_2_5GB_FULL:
2653                 link.link_speed = ETH_SPEED_NUM_2_5G;
2654                 break;
2655
2656         case TXGBE_LINK_SPEED_5GB_FULL:
2657                 link.link_speed = ETH_SPEED_NUM_5G;
2658                 break;
2659
2660         case TXGBE_LINK_SPEED_10GB_FULL:
2661                 link.link_speed = ETH_SPEED_NUM_10G;
2662                 break;
2663         }
2664
2665         return rte_eth_linkstatus_set(dev, &link);
2666 }
2667
2668 static int
2669 txgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
2670 {
2671         return txgbe_dev_link_update_share(dev, wait_to_complete);
2672 }
2673
2674 static int
2675 txgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
2676 {
2677         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2678         uint32_t fctrl;
2679
2680         fctrl = rd32(hw, TXGBE_PSRCTL);
2681         fctrl |= (TXGBE_PSRCTL_UCP | TXGBE_PSRCTL_MCP);
2682         wr32(hw, TXGBE_PSRCTL, fctrl);
2683
2684         return 0;
2685 }
2686
2687 static int
2688 txgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
2689 {
2690         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2691         uint32_t fctrl;
2692
2693         fctrl = rd32(hw, TXGBE_PSRCTL);
2694         fctrl &= (~TXGBE_PSRCTL_UCP);
2695         if (dev->data->all_multicast == 1)
2696                 fctrl |= TXGBE_PSRCTL_MCP;
2697         else
2698                 fctrl &= (~TXGBE_PSRCTL_MCP);
2699         wr32(hw, TXGBE_PSRCTL, fctrl);
2700
2701         return 0;
2702 }
2703
2704 static int
2705 txgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
2706 {
2707         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2708         uint32_t fctrl;
2709
2710         fctrl = rd32(hw, TXGBE_PSRCTL);
2711         fctrl |= TXGBE_PSRCTL_MCP;
2712         wr32(hw, TXGBE_PSRCTL, fctrl);
2713
2714         return 0;
2715 }
2716
2717 static int
2718 txgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
2719 {
2720         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2721         uint32_t fctrl;
2722
2723         if (dev->data->promiscuous == 1)
2724                 return 0; /* must remain in all_multicast mode */
2725
2726         fctrl = rd32(hw, TXGBE_PSRCTL);
2727         fctrl &= (~TXGBE_PSRCTL_MCP);
2728         wr32(hw, TXGBE_PSRCTL, fctrl);
2729
2730         return 0;
2731 }
2732
2733 /**
2734  * It clears the interrupt causes and enables the interrupt.
2735  * It will be called once only during nic initialized.
2736  *
2737  * @param dev
2738  *  Pointer to struct rte_eth_dev.
2739  * @param on
2740  *  Enable or Disable.
2741  *
2742  * @return
2743  *  - On success, zero.
2744  *  - On failure, a negative value.
2745  */
2746 static int
2747 txgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on)
2748 {
2749         struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);
2750
2751         txgbe_dev_link_status_print(dev);
2752         if (on)
2753                 intr->mask_misc |= TXGBE_ICRMISC_LSC;
2754         else
2755                 intr->mask_misc &= ~TXGBE_ICRMISC_LSC;
2756
2757         return 0;
2758 }
2759
2760 /**
2761  * It clears the interrupt causes and enables the interrupt.
2762  * It will be called once only during nic initialized.
2763  *
2764  * @param dev
2765  *  Pointer to struct rte_eth_dev.
2766  *
2767  * @return
2768  *  - On success, zero.
2769  *  - On failure, a negative value.
2770  */
2771 static int
2772 txgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
2773 {
2774         struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);
2775
2776         intr->mask[0] |= TXGBE_ICR_MASK;
2777         intr->mask[1] |= TXGBE_ICR_MASK;
2778
2779         return 0;
2780 }
2781
2782 /**
2783  * It clears the interrupt causes and enables the interrupt.
2784  * It will be called once only during nic initialized.
2785  *
2786  * @param dev
2787  *  Pointer to struct rte_eth_dev.
2788  *
2789  * @return
2790  *  - On success, zero.
2791  *  - On failure, a negative value.
2792  */
2793 static int
2794 txgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev)
2795 {
2796         struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);
2797
2798         intr->mask_misc |= TXGBE_ICRMISC_LNKSEC;
2799
2800         return 0;
2801 }
2802
2803 /*
2804  * It reads ICR and sets flag (TXGBE_ICRMISC_LSC) for the link_update.
2805  *
2806  * @param dev
2807  *  Pointer to struct rte_eth_dev.
2808  *
2809  * @return
2810  *  - On success, zero.
2811  *  - On failure, a negative value.
2812  */
2813 static int
2814 txgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
2815 {
2816         uint32_t eicr;
2817         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2818         struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);
2819
2820         /* clear all cause mask */
2821         txgbe_disable_intr(hw);
2822
2823         /* read-on-clear nic registers here */
2824         eicr = ((u32 *)hw->isb_mem)[TXGBE_ISB_MISC];
2825         PMD_DRV_LOG(DEBUG, "eicr %x", eicr);
2826
2827         intr->flags = 0;
2828
2829         /* set flag for async link update */
2830         if (eicr & TXGBE_ICRMISC_LSC)
2831                 intr->flags |= TXGBE_FLAG_NEED_LINK_UPDATE;
2832
2833         if (eicr & TXGBE_ICRMISC_VFMBX)
2834                 intr->flags |= TXGBE_FLAG_MAILBOX;
2835
2836         if (eicr & TXGBE_ICRMISC_LNKSEC)
2837                 intr->flags |= TXGBE_FLAG_MACSEC;
2838
2839         if (eicr & TXGBE_ICRMISC_GPIO)
2840                 intr->flags |= TXGBE_FLAG_PHY_INTERRUPT;
2841
2842         return 0;
2843 }
2844
2845 /**
2846  * It gets and then prints the link status.
2847  *
2848  * @param dev
2849  *  Pointer to struct rte_eth_dev.
2850  *
2851  * @return
2852  *  - On success, zero.
2853  *  - On failure, a negative value.
2854  */
2855 static void
2856 txgbe_dev_link_status_print(struct rte_eth_dev *dev)
2857 {
2858         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2859         struct rte_eth_link link;
2860
2861         rte_eth_linkstatus_get(dev, &link);
2862
2863         if (link.link_status) {
2864                 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
2865                                         (int)(dev->data->port_id),
2866                                         (unsigned int)link.link_speed,
2867                         link.link_duplex == ETH_LINK_FULL_DUPLEX ?
2868                                         "full-duplex" : "half-duplex");
2869         } else {
2870                 PMD_INIT_LOG(INFO, " Port %d: Link Down",
2871                                 (int)(dev->data->port_id));
2872         }
2873         PMD_INIT_LOG(DEBUG, "PCI Address: " PCI_PRI_FMT,
2874                                 pci_dev->addr.domain,
2875                                 pci_dev->addr.bus,
2876                                 pci_dev->addr.devid,
2877                                 pci_dev->addr.function);
2878 }
2879
2880 /*
2881  * It executes link_update after knowing an interrupt occurred.
2882  *
2883  * @param dev
2884  *  Pointer to struct rte_eth_dev.
2885  *
2886  * @return
2887  *  - On success, zero.
2888  *  - On failure, a negative value.
2889  */
2890 static int
2891 txgbe_dev_interrupt_action(struct rte_eth_dev *dev,
2892                            struct rte_intr_handle *intr_handle)
2893 {
2894         struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);
2895         int64_t timeout;
2896         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2897
2898         PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
2899
2900         if (intr->flags & TXGBE_FLAG_MAILBOX) {
2901                 txgbe_pf_mbx_process(dev);
2902                 intr->flags &= ~TXGBE_FLAG_MAILBOX;
2903         }
2904
2905         if (intr->flags & TXGBE_FLAG_PHY_INTERRUPT) {
2906                 hw->phy.handle_lasi(hw);
2907                 intr->flags &= ~TXGBE_FLAG_PHY_INTERRUPT;
2908         }
2909
2910         if (intr->flags & TXGBE_FLAG_NEED_LINK_UPDATE) {
2911                 struct rte_eth_link link;
2912
2913                 /*get the link status before link update, for predicting later*/
2914                 rte_eth_linkstatus_get(dev, &link);
2915
2916                 txgbe_dev_link_update(dev, 0);
2917
2918                 /* likely to up */
2919                 if (!link.link_status)
2920                         /* handle it 1 sec later, wait it being stable */
2921                         timeout = TXGBE_LINK_UP_CHECK_TIMEOUT;
2922                 /* likely to down */
2923                 else
2924                         /* handle it 4 sec later, wait it being stable */
2925                         timeout = TXGBE_LINK_DOWN_CHECK_TIMEOUT;
2926
2927                 txgbe_dev_link_status_print(dev);
2928                 if (rte_eal_alarm_set(timeout * 1000,
2929                                       txgbe_dev_interrupt_delayed_handler,
2930                                       (void *)dev) < 0) {
2931                         PMD_DRV_LOG(ERR, "Error setting alarm");
2932                 } else {
2933                         /* remember original mask */
2934                         intr->mask_misc_orig = intr->mask_misc;
2935                         /* only disable lsc interrupt */
2936                         intr->mask_misc &= ~TXGBE_ICRMISC_LSC;
2937                 }
2938         }
2939
2940         PMD_DRV_LOG(DEBUG, "enable intr immediately");
2941         txgbe_enable_intr(dev);
2942         rte_intr_enable(intr_handle);
2943
2944         return 0;
2945 }
2946
2947 /**
2948  * Interrupt handler which shall be registered for alarm callback for delayed
2949  * handling specific interrupt to wait for the stable nic state. As the
2950  * NIC interrupt state is not stable for txgbe after link is just down,
2951  * it needs to wait 4 seconds to get the stable status.
2952  *
2953  * @param handle
2954  *  Pointer to interrupt handle.
2955  * @param param
2956  *  The address of parameter (struct rte_eth_dev *) registered before.
2957  *
2958  * @return
2959  *  void
2960  */
2961 static void
2962 txgbe_dev_interrupt_delayed_handler(void *param)
2963 {
2964         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2965         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2966         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2967         struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);
2968         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2969         uint32_t eicr;
2970
2971         txgbe_disable_intr(hw);
2972
2973         eicr = ((u32 *)hw->isb_mem)[TXGBE_ISB_MISC];
2974         if (eicr & TXGBE_ICRMISC_VFMBX)
2975                 txgbe_pf_mbx_process(dev);
2976
2977         if (intr->flags & TXGBE_FLAG_PHY_INTERRUPT) {
2978                 hw->phy.handle_lasi(hw);
2979                 intr->flags &= ~TXGBE_FLAG_PHY_INTERRUPT;
2980         }
2981
2982         if (intr->flags & TXGBE_FLAG_NEED_LINK_UPDATE) {
2983                 txgbe_dev_link_update(dev, 0);
2984                 intr->flags &= ~TXGBE_FLAG_NEED_LINK_UPDATE;
2985                 txgbe_dev_link_status_print(dev);
2986                 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC,
2987                                               NULL);
2988         }
2989
2990         if (intr->flags & TXGBE_FLAG_MACSEC) {
2991                 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_MACSEC,
2992                                               NULL);
2993                 intr->flags &= ~TXGBE_FLAG_MACSEC;
2994         }
2995
2996         /* restore original mask */
2997         intr->mask_misc = intr->mask_misc_orig;
2998         intr->mask_misc_orig = 0;
2999
3000         PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
3001         txgbe_enable_intr(dev);
3002         rte_intr_enable(intr_handle);
3003 }
3004
3005 /**
3006  * Interrupt handler triggered by NIC  for handling
3007  * specific interrupt.
3008  *
3009  * @param handle
3010  *  Pointer to interrupt handle.
3011  * @param param
3012  *  The address of parameter (struct rte_eth_dev *) registered before.
3013  *
3014  * @return
3015  *  void
3016  */
3017 static void
3018 txgbe_dev_interrupt_handler(void *param)
3019 {
3020         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3021
3022         txgbe_dev_interrupt_get_status(dev);
3023         txgbe_dev_interrupt_action(dev, dev->intr_handle);
3024 }
3025
3026 static int
3027 txgbe_dev_led_on(struct rte_eth_dev *dev)
3028 {
3029         struct txgbe_hw *hw;
3030
3031         hw = TXGBE_DEV_HW(dev);
3032         return txgbe_led_on(hw, 4) == 0 ? 0 : -ENOTSUP;
3033 }
3034
3035 static int
3036 txgbe_dev_led_off(struct rte_eth_dev *dev)
3037 {
3038         struct txgbe_hw *hw;
3039
3040         hw = TXGBE_DEV_HW(dev);
3041         return txgbe_led_off(hw, 4) == 0 ? 0 : -ENOTSUP;
3042 }
3043
3044 static int
3045 txgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3046 {
3047         struct txgbe_hw *hw;
3048         uint32_t mflcn_reg;
3049         uint32_t fccfg_reg;
3050         int rx_pause;
3051         int tx_pause;
3052
3053         hw = TXGBE_DEV_HW(dev);
3054
3055         fc_conf->pause_time = hw->fc.pause_time;
3056         fc_conf->high_water = hw->fc.high_water[0];
3057         fc_conf->low_water = hw->fc.low_water[0];
3058         fc_conf->send_xon = hw->fc.send_xon;
3059         fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
3060
3061         /*
3062          * Return rx_pause status according to actual setting of
3063          * RXFCCFG register.
3064          */
3065         mflcn_reg = rd32(hw, TXGBE_RXFCCFG);
3066         if (mflcn_reg & (TXGBE_RXFCCFG_FC | TXGBE_RXFCCFG_PFC))
3067                 rx_pause = 1;
3068         else
3069                 rx_pause = 0;
3070
3071         /*
3072          * Return tx_pause status according to actual setting of
3073          * TXFCCFG register.
3074          */
3075         fccfg_reg = rd32(hw, TXGBE_TXFCCFG);
3076         if (fccfg_reg & (TXGBE_TXFCCFG_FC | TXGBE_TXFCCFG_PFC))
3077                 tx_pause = 1;
3078         else
3079                 tx_pause = 0;
3080
3081         if (rx_pause && tx_pause)
3082                 fc_conf->mode = RTE_FC_FULL;
3083         else if (rx_pause)
3084                 fc_conf->mode = RTE_FC_RX_PAUSE;
3085         else if (tx_pause)
3086                 fc_conf->mode = RTE_FC_TX_PAUSE;
3087         else
3088                 fc_conf->mode = RTE_FC_NONE;
3089
3090         return 0;
3091 }
3092
3093 static int
3094 txgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3095 {
3096         struct txgbe_hw *hw;
3097         int err;
3098         uint32_t rx_buf_size;
3099         uint32_t max_high_water;
3100         enum txgbe_fc_mode rte_fcmode_2_txgbe_fcmode[] = {
3101                 txgbe_fc_none,
3102                 txgbe_fc_rx_pause,
3103                 txgbe_fc_tx_pause,
3104                 txgbe_fc_full
3105         };
3106
3107         PMD_INIT_FUNC_TRACE();
3108
3109         hw = TXGBE_DEV_HW(dev);
3110         rx_buf_size = rd32(hw, TXGBE_PBRXSIZE(0));
3111         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
3112
3113         /*
3114          * At least reserve one Ethernet frame for watermark
3115          * high_water/low_water in kilo bytes for txgbe
3116          */
3117         max_high_water = (rx_buf_size - RTE_ETHER_MAX_LEN) >> 10;
3118         if (fc_conf->high_water > max_high_water ||
3119             fc_conf->high_water < fc_conf->low_water) {
3120                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
3121                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
3122                 return -EINVAL;
3123         }
3124
3125         hw->fc.requested_mode = rte_fcmode_2_txgbe_fcmode[fc_conf->mode];
3126         hw->fc.pause_time     = fc_conf->pause_time;
3127         hw->fc.high_water[0]  = fc_conf->high_water;
3128         hw->fc.low_water[0]   = fc_conf->low_water;
3129         hw->fc.send_xon       = fc_conf->send_xon;
3130         hw->fc.disable_fc_autoneg = !fc_conf->autoneg;
3131
3132         err = txgbe_fc_enable(hw);
3133
3134         /* Not negotiated is not an error case */
3135         if (err == 0 || err == TXGBE_ERR_FC_NOT_NEGOTIATED) {
3136                 wr32m(hw, TXGBE_MACRXFLT, TXGBE_MACRXFLT_CTL_MASK,
3137                       (fc_conf->mac_ctrl_frame_fwd
3138                        ? TXGBE_MACRXFLT_CTL_NOPS : TXGBE_MACRXFLT_CTL_DROP));
3139                 txgbe_flush(hw);
3140
3141                 return 0;
3142         }
3143
3144         PMD_INIT_LOG(ERR, "txgbe_fc_enable = 0x%x", err);
3145         return -EIO;
3146 }
3147
3148 static int
3149 txgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
3150                 struct rte_eth_pfc_conf *pfc_conf)
3151 {
3152         int err;
3153         uint32_t rx_buf_size;
3154         uint32_t max_high_water;
3155         uint8_t tc_num;
3156         uint8_t  map[TXGBE_DCB_UP_MAX] = { 0 };
3157         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3158         struct txgbe_dcb_config *dcb_config = TXGBE_DEV_DCB_CONFIG(dev);
3159
3160         enum txgbe_fc_mode rte_fcmode_2_txgbe_fcmode[] = {
3161                 txgbe_fc_none,
3162                 txgbe_fc_rx_pause,
3163                 txgbe_fc_tx_pause,
3164                 txgbe_fc_full
3165         };
3166
3167         PMD_INIT_FUNC_TRACE();
3168
3169         txgbe_dcb_unpack_map_cee(dcb_config, TXGBE_DCB_RX_CONFIG, map);
3170         tc_num = map[pfc_conf->priority];
3171         rx_buf_size = rd32(hw, TXGBE_PBRXSIZE(tc_num));
3172         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
3173         /*
3174          * At least reserve one Ethernet frame for watermark
3175          * high_water/low_water in kilo bytes for txgbe
3176          */
3177         max_high_water = (rx_buf_size - RTE_ETHER_MAX_LEN) >> 10;
3178         if (pfc_conf->fc.high_water > max_high_water ||
3179             pfc_conf->fc.high_water <= pfc_conf->fc.low_water) {
3180                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
3181                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
3182                 return -EINVAL;
3183         }
3184
3185         hw->fc.requested_mode = rte_fcmode_2_txgbe_fcmode[pfc_conf->fc.mode];
3186         hw->fc.pause_time = pfc_conf->fc.pause_time;
3187         hw->fc.send_xon = pfc_conf->fc.send_xon;
3188         hw->fc.low_water[tc_num] =  pfc_conf->fc.low_water;
3189         hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
3190
3191         err = txgbe_dcb_pfc_enable(hw, tc_num);
3192
3193         /* Not negotiated is not an error case */
3194         if (err == 0 || err == TXGBE_ERR_FC_NOT_NEGOTIATED)
3195                 return 0;
3196
3197         PMD_INIT_LOG(ERR, "txgbe_dcb_pfc_enable = 0x%x", err);
3198         return -EIO;
3199 }
3200
3201 int
3202 txgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
3203                           struct rte_eth_rss_reta_entry64 *reta_conf,
3204                           uint16_t reta_size)
3205 {
3206         uint8_t i, j, mask;
3207         uint32_t reta;
3208         uint16_t idx, shift;
3209         struct txgbe_adapter *adapter = TXGBE_DEV_ADAPTER(dev);
3210         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3211
3212         PMD_INIT_FUNC_TRACE();
3213
3214         if (!txgbe_rss_update_sp(hw->mac.type)) {
3215                 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this "
3216                         "NIC.");
3217                 return -ENOTSUP;
3218         }
3219
3220         if (reta_size != ETH_RSS_RETA_SIZE_128) {
3221                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3222                         "(%d) doesn't match the number hardware can supported "
3223                         "(%d)", reta_size, ETH_RSS_RETA_SIZE_128);
3224                 return -EINVAL;
3225         }
3226
3227         for (i = 0; i < reta_size; i += 4) {
3228                 idx = i / RTE_RETA_GROUP_SIZE;
3229                 shift = i % RTE_RETA_GROUP_SIZE;
3230                 mask = (uint8_t)RS64(reta_conf[idx].mask, shift, 0xF);
3231                 if (!mask)
3232                         continue;
3233
3234                 reta = rd32a(hw, TXGBE_REG_RSSTBL, i >> 2);
3235                 for (j = 0; j < 4; j++) {
3236                         if (RS8(mask, j, 0x1)) {
3237                                 reta  &= ~(MS32(8 * j, 0xFF));
3238                                 reta |= LS32(reta_conf[idx].reta[shift + j],
3239                                                 8 * j, 0xFF);
3240                         }
3241                 }
3242                 wr32a(hw, TXGBE_REG_RSSTBL, i >> 2, reta);
3243         }
3244         adapter->rss_reta_updated = 1;
3245
3246         return 0;
3247 }
3248
3249 int
3250 txgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
3251                          struct rte_eth_rss_reta_entry64 *reta_conf,
3252                          uint16_t reta_size)
3253 {
3254         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3255         uint8_t i, j, mask;
3256         uint32_t reta;
3257         uint16_t idx, shift;
3258
3259         PMD_INIT_FUNC_TRACE();
3260
3261         if (reta_size != ETH_RSS_RETA_SIZE_128) {
3262                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3263                         "(%d) doesn't match the number hardware can supported "
3264                         "(%d)", reta_size, ETH_RSS_RETA_SIZE_128);
3265                 return -EINVAL;
3266         }
3267
3268         for (i = 0; i < reta_size; i += 4) {
3269                 idx = i / RTE_RETA_GROUP_SIZE;
3270                 shift = i % RTE_RETA_GROUP_SIZE;
3271                 mask = (uint8_t)RS64(reta_conf[idx].mask, shift, 0xF);
3272                 if (!mask)
3273                         continue;
3274
3275                 reta = rd32a(hw, TXGBE_REG_RSSTBL, i >> 2);
3276                 for (j = 0; j < 4; j++) {
3277                         if (RS8(mask, j, 0x1))
3278                                 reta_conf[idx].reta[shift + j] =
3279                                         (uint16_t)RS32(reta, 8 * j, 0xFF);
3280                 }
3281         }
3282
3283         return 0;
3284 }
3285
3286 static int
3287 txgbe_add_rar(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
3288                                 uint32_t index, uint32_t pool)
3289 {
3290         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3291         uint32_t enable_addr = 1;
3292
3293         return txgbe_set_rar(hw, index, mac_addr->addr_bytes,
3294                              pool, enable_addr);
3295 }
3296
3297 static void
3298 txgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
3299 {
3300         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3301
3302         txgbe_clear_rar(hw, index);
3303 }
3304
3305 static int
3306 txgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *addr)
3307 {
3308         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3309
3310         txgbe_remove_rar(dev, 0);
3311         txgbe_add_rar(dev, addr, 0, pci_dev->max_vfs);
3312
3313         return 0;
3314 }
3315
3316 static int
3317 txgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
3318 {
3319         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3320         struct rte_eth_dev_info dev_info;
3321         uint32_t frame_size = mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN;
3322         struct rte_eth_dev_data *dev_data = dev->data;
3323         int ret;
3324
3325         ret = txgbe_dev_info_get(dev, &dev_info);
3326         if (ret != 0)
3327                 return ret;
3328
3329         /* check that mtu is within the allowed range */
3330         if (mtu < RTE_ETHER_MIN_MTU || frame_size > dev_info.max_rx_pktlen)
3331                 return -EINVAL;
3332
3333         /* If device is started, refuse mtu that requires the support of
3334          * scattered packets when this feature has not been enabled before.
3335          */
3336         if (dev_data->dev_started && !dev_data->scattered_rx &&
3337             (frame_size + 2 * TXGBE_VLAN_TAG_SIZE >
3338              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
3339                 PMD_INIT_LOG(ERR, "Stop port first.");
3340                 return -EINVAL;
3341         }
3342
3343         /* update max frame size */
3344         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
3345
3346         if (hw->mode)
3347                 wr32m(hw, TXGBE_FRMSZ, TXGBE_FRMSZ_MAX_MASK,
3348                         TXGBE_FRAME_SIZE_MAX);
3349         else
3350                 wr32m(hw, TXGBE_FRMSZ, TXGBE_FRMSZ_MAX_MASK,
3351                         TXGBE_FRMSZ_MAX(frame_size));
3352
3353         return 0;
3354 }
3355
3356 static uint32_t
3357 txgbe_uta_vector(struct txgbe_hw *hw, struct rte_ether_addr *uc_addr)
3358 {
3359         uint32_t vector = 0;
3360
3361         switch (hw->mac.mc_filter_type) {
3362         case 0:   /* use bits [47:36] of the address */
3363                 vector = ((uc_addr->addr_bytes[4] >> 4) |
3364                         (((uint16_t)uc_addr->addr_bytes[5]) << 4));
3365                 break;
3366         case 1:   /* use bits [46:35] of the address */
3367                 vector = ((uc_addr->addr_bytes[4] >> 3) |
3368                         (((uint16_t)uc_addr->addr_bytes[5]) << 5));
3369                 break;
3370         case 2:   /* use bits [45:34] of the address */
3371                 vector = ((uc_addr->addr_bytes[4] >> 2) |
3372                         (((uint16_t)uc_addr->addr_bytes[5]) << 6));
3373                 break;
3374         case 3:   /* use bits [43:32] of the address */
3375                 vector = ((uc_addr->addr_bytes[4]) |
3376                         (((uint16_t)uc_addr->addr_bytes[5]) << 8));
3377                 break;
3378         default:  /* Invalid mc_filter_type */
3379                 break;
3380         }
3381
3382         /* vector can only be 12-bits or boundary will be exceeded */
3383         vector &= 0xFFF;
3384         return vector;
3385 }
3386
3387 static int
3388 txgbe_uc_hash_table_set(struct rte_eth_dev *dev,
3389                         struct rte_ether_addr *mac_addr, uint8_t on)
3390 {
3391         uint32_t vector;
3392         uint32_t uta_idx;
3393         uint32_t reg_val;
3394         uint32_t uta_mask;
3395         uint32_t psrctl;
3396
3397         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3398         struct txgbe_uta_info *uta_info = TXGBE_DEV_UTA_INFO(dev);
3399
3400         /* The UTA table only exists on pf hardware */
3401         if (hw->mac.type < txgbe_mac_raptor)
3402                 return -ENOTSUP;
3403
3404         vector = txgbe_uta_vector(hw, mac_addr);
3405         uta_idx = (vector >> 5) & 0x7F;
3406         uta_mask = 0x1UL << (vector & 0x1F);
3407
3408         if (!!on == !!(uta_info->uta_shadow[uta_idx] & uta_mask))
3409                 return 0;
3410
3411         reg_val = rd32(hw, TXGBE_UCADDRTBL(uta_idx));
3412         if (on) {
3413                 uta_info->uta_in_use++;
3414                 reg_val |= uta_mask;
3415                 uta_info->uta_shadow[uta_idx] |= uta_mask;
3416         } else {
3417                 uta_info->uta_in_use--;
3418                 reg_val &= ~uta_mask;
3419                 uta_info->uta_shadow[uta_idx] &= ~uta_mask;
3420         }
3421
3422         wr32(hw, TXGBE_UCADDRTBL(uta_idx), reg_val);
3423
3424         psrctl = rd32(hw, TXGBE_PSRCTL);
3425         if (uta_info->uta_in_use > 0)
3426                 psrctl |= TXGBE_PSRCTL_UCHFENA;
3427         else
3428                 psrctl &= ~TXGBE_PSRCTL_UCHFENA;
3429
3430         psrctl &= ~TXGBE_PSRCTL_ADHF12_MASK;
3431         psrctl |= TXGBE_PSRCTL_ADHF12(hw->mac.mc_filter_type);
3432         wr32(hw, TXGBE_PSRCTL, psrctl);
3433
3434         return 0;
3435 }
3436
3437 static int
3438 txgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
3439 {
3440         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3441         struct txgbe_uta_info *uta_info = TXGBE_DEV_UTA_INFO(dev);
3442         uint32_t psrctl;
3443         int i;
3444
3445         /* The UTA table only exists on pf hardware */
3446         if (hw->mac.type < txgbe_mac_raptor)
3447                 return -ENOTSUP;
3448
3449         if (on) {
3450                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
3451                         uta_info->uta_shadow[i] = ~0;
3452                         wr32(hw, TXGBE_UCADDRTBL(i), ~0);
3453                 }
3454         } else {
3455                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
3456                         uta_info->uta_shadow[i] = 0;
3457                         wr32(hw, TXGBE_UCADDRTBL(i), 0);
3458                 }
3459         }
3460
3461         psrctl = rd32(hw, TXGBE_PSRCTL);
3462         if (on)
3463                 psrctl |= TXGBE_PSRCTL_UCHFENA;
3464         else
3465                 psrctl &= ~TXGBE_PSRCTL_UCHFENA;
3466
3467         psrctl &= ~TXGBE_PSRCTL_ADHF12_MASK;
3468         psrctl |= TXGBE_PSRCTL_ADHF12(hw->mac.mc_filter_type);
3469         wr32(hw, TXGBE_PSRCTL, psrctl);
3470
3471         return 0;
3472 }
3473
3474 uint32_t
3475 txgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
3476 {
3477         uint32_t new_val = orig_val;
3478
3479         if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
3480                 new_val |= TXGBE_POOLETHCTL_UTA;
3481         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
3482                 new_val |= TXGBE_POOLETHCTL_MCHA;
3483         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
3484                 new_val |= TXGBE_POOLETHCTL_UCHA;
3485         if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
3486                 new_val |= TXGBE_POOLETHCTL_BCA;
3487         if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
3488                 new_val |= TXGBE_POOLETHCTL_MCP;
3489
3490         return new_val;
3491 }
3492
3493 static int
3494 txgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
3495 {
3496         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3497         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3498         uint32_t mask;
3499         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3500
3501         if (queue_id < 32) {
3502                 mask = rd32(hw, TXGBE_IMS(0));
3503                 mask &= (1 << queue_id);
3504                 wr32(hw, TXGBE_IMS(0), mask);
3505         } else if (queue_id < 64) {
3506                 mask = rd32(hw, TXGBE_IMS(1));
3507                 mask &= (1 << (queue_id - 32));
3508                 wr32(hw, TXGBE_IMS(1), mask);
3509         }
3510         rte_intr_enable(intr_handle);
3511
3512         return 0;
3513 }
3514
3515 static int
3516 txgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
3517 {
3518         uint32_t mask;
3519         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3520
3521         if (queue_id < 32) {
3522                 mask = rd32(hw, TXGBE_IMS(0));
3523                 mask &= ~(1 << queue_id);
3524                 wr32(hw, TXGBE_IMS(0), mask);
3525         } else if (queue_id < 64) {
3526                 mask = rd32(hw, TXGBE_IMS(1));
3527                 mask &= ~(1 << (queue_id - 32));
3528                 wr32(hw, TXGBE_IMS(1), mask);
3529         }
3530
3531         return 0;
3532 }
3533
3534 /**
3535  * set the IVAR registers, mapping interrupt causes to vectors
3536  * @param hw
3537  *  pointer to txgbe_hw struct
3538  * @direction
3539  *  0 for Rx, 1 for Tx, -1 for other causes
3540  * @queue
3541  *  queue to map the corresponding interrupt to
3542  * @msix_vector
3543  *  the vector to map to the corresponding queue
3544  */
3545 void
3546 txgbe_set_ivar_map(struct txgbe_hw *hw, int8_t direction,
3547                    uint8_t queue, uint8_t msix_vector)
3548 {
3549         uint32_t tmp, idx;
3550
3551         if (direction == -1) {
3552                 /* other causes */
3553                 msix_vector |= TXGBE_IVARMISC_VLD;
3554                 idx = 0;
3555                 tmp = rd32(hw, TXGBE_IVARMISC);
3556                 tmp &= ~(0xFF << idx);
3557                 tmp |= (msix_vector << idx);
3558                 wr32(hw, TXGBE_IVARMISC, tmp);
3559         } else {
3560                 /* rx or tx causes */
3561                 /* Workround for ICR lost */
3562                 idx = ((16 * (queue & 1)) + (8 * direction));
3563                 tmp = rd32(hw, TXGBE_IVAR(queue >> 1));
3564                 tmp &= ~(0xFF << idx);
3565                 tmp |= (msix_vector << idx);
3566                 wr32(hw, TXGBE_IVAR(queue >> 1), tmp);
3567         }
3568 }
3569
3570 /**
3571  * Sets up the hardware to properly generate MSI-X interrupts
3572  * @hw
3573  *  board private structure
3574  */
3575 static void
3576 txgbe_configure_msix(struct rte_eth_dev *dev)
3577 {
3578         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3579         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3580         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3581         uint32_t queue_id, base = TXGBE_MISC_VEC_ID;
3582         uint32_t vec = TXGBE_MISC_VEC_ID;
3583         uint32_t gpie;
3584
3585         /* won't configure msix register if no mapping is done
3586          * between intr vector and event fd
3587          * but if misx has been enabled already, need to configure
3588          * auto clean, auto mask and throttling.
3589          */
3590         gpie = rd32(hw, TXGBE_GPIE);
3591         if (!rte_intr_dp_is_en(intr_handle) &&
3592             !(gpie & TXGBE_GPIE_MSIX))
3593                 return;
3594
3595         if (rte_intr_allow_others(intr_handle)) {
3596                 base = TXGBE_RX_VEC_START;
3597                 vec = base;
3598         }
3599
3600         /* setup GPIE for MSI-x mode */
3601         gpie = rd32(hw, TXGBE_GPIE);
3602         gpie |= TXGBE_GPIE_MSIX;
3603         wr32(hw, TXGBE_GPIE, gpie);
3604
3605         /* Populate the IVAR table and set the ITR values to the
3606          * corresponding register.
3607          */
3608         if (rte_intr_dp_is_en(intr_handle)) {
3609                 for (queue_id = 0; queue_id < dev->data->nb_rx_queues;
3610                         queue_id++) {
3611                         /* by default, 1:1 mapping */
3612                         txgbe_set_ivar_map(hw, 0, queue_id, vec);
3613                         intr_handle->intr_vec[queue_id] = vec;
3614                         if (vec < base + intr_handle->nb_efd - 1)
3615                                 vec++;
3616                 }
3617
3618                 txgbe_set_ivar_map(hw, -1, 1, TXGBE_MISC_VEC_ID);
3619         }
3620         wr32(hw, TXGBE_ITR(TXGBE_MISC_VEC_ID),
3621                         TXGBE_ITR_IVAL_10G(TXGBE_QUEUE_ITR_INTERVAL_DEFAULT)
3622                         | TXGBE_ITR_WRDSA);
3623 }
3624
3625 int
3626 txgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
3627                            uint16_t queue_idx, uint16_t tx_rate)
3628 {
3629         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3630         uint32_t bcnrc_val;
3631
3632         if (queue_idx >= hw->mac.max_tx_queues)
3633                 return -EINVAL;
3634
3635         if (tx_rate != 0) {
3636                 bcnrc_val = TXGBE_ARBTXRATE_MAX(tx_rate);
3637                 bcnrc_val |= TXGBE_ARBTXRATE_MIN(tx_rate / 2);
3638         } else {
3639                 bcnrc_val = 0;
3640         }
3641
3642         /*
3643          * Set global transmit compensation time to the MMW_SIZE in ARBTXMMW
3644          * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported.
3645          */
3646         wr32(hw, TXGBE_ARBTXMMW, 0x14);
3647
3648         /* Set ARBTXRATE of queue X */
3649         wr32(hw, TXGBE_ARBPOOLIDX, queue_idx);
3650         wr32(hw, TXGBE_ARBTXRATE, bcnrc_val);
3651         txgbe_flush(hw);
3652
3653         return 0;
3654 }
3655
3656 int
3657 txgbe_syn_filter_set(struct rte_eth_dev *dev,
3658                         struct rte_eth_syn_filter *filter,
3659                         bool add)
3660 {
3661         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3662         struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(dev);
3663         uint32_t syn_info;
3664         uint32_t synqf;
3665
3666         if (filter->queue >= TXGBE_MAX_RX_QUEUE_NUM)
3667                 return -EINVAL;
3668
3669         syn_info = filter_info->syn_info;
3670
3671         if (add) {
3672                 if (syn_info & TXGBE_SYNCLS_ENA)
3673                         return -EINVAL;
3674                 synqf = (uint32_t)TXGBE_SYNCLS_QPID(filter->queue);
3675                 synqf |= TXGBE_SYNCLS_ENA;
3676
3677                 if (filter->hig_pri)
3678                         synqf |= TXGBE_SYNCLS_HIPRIO;
3679                 else
3680                         synqf &= ~TXGBE_SYNCLS_HIPRIO;
3681         } else {
3682                 synqf = rd32(hw, TXGBE_SYNCLS);
3683                 if (!(syn_info & TXGBE_SYNCLS_ENA))
3684                         return -ENOENT;
3685                 synqf &= ~(TXGBE_SYNCLS_QPID_MASK | TXGBE_SYNCLS_ENA);
3686         }
3687
3688         filter_info->syn_info = synqf;
3689         wr32(hw, TXGBE_SYNCLS, synqf);
3690         txgbe_flush(hw);
3691         return 0;
3692 }
3693
3694 static inline enum txgbe_5tuple_protocol
3695 convert_protocol_type(uint8_t protocol_value)
3696 {
3697         if (protocol_value == IPPROTO_TCP)
3698                 return TXGBE_5TF_PROT_TCP;
3699         else if (protocol_value == IPPROTO_UDP)
3700                 return TXGBE_5TF_PROT_UDP;
3701         else if (protocol_value == IPPROTO_SCTP)
3702                 return TXGBE_5TF_PROT_SCTP;
3703         else
3704                 return TXGBE_5TF_PROT_NONE;
3705 }
3706
3707 /* inject a 5-tuple filter to HW */
3708 static inline void
3709 txgbe_inject_5tuple_filter(struct rte_eth_dev *dev,
3710                            struct txgbe_5tuple_filter *filter)
3711 {
3712         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3713         int i;
3714         uint32_t ftqf, sdpqf;
3715         uint32_t l34timir = 0;
3716         uint32_t mask = TXGBE_5TFCTL0_MASK;
3717
3718         i = filter->index;
3719         sdpqf = TXGBE_5TFPORT_DST(be_to_le16(filter->filter_info.dst_port));
3720         sdpqf |= TXGBE_5TFPORT_SRC(be_to_le16(filter->filter_info.src_port));
3721
3722         ftqf = TXGBE_5TFCTL0_PROTO(filter->filter_info.proto);
3723         ftqf |= TXGBE_5TFCTL0_PRI(filter->filter_info.priority);
3724         if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
3725                 mask &= ~TXGBE_5TFCTL0_MSADDR;
3726         if (filter->filter_info.dst_ip_mask == 0)
3727                 mask &= ~TXGBE_5TFCTL0_MDADDR;
3728         if (filter->filter_info.src_port_mask == 0)
3729                 mask &= ~TXGBE_5TFCTL0_MSPORT;
3730         if (filter->filter_info.dst_port_mask == 0)
3731                 mask &= ~TXGBE_5TFCTL0_MDPORT;
3732         if (filter->filter_info.proto_mask == 0)
3733                 mask &= ~TXGBE_5TFCTL0_MPROTO;
3734         ftqf |= mask;
3735         ftqf |= TXGBE_5TFCTL0_MPOOL;
3736         ftqf |= TXGBE_5TFCTL0_ENA;
3737
3738         wr32(hw, TXGBE_5TFDADDR(i), be_to_le32(filter->filter_info.dst_ip));
3739         wr32(hw, TXGBE_5TFSADDR(i), be_to_le32(filter->filter_info.src_ip));
3740         wr32(hw, TXGBE_5TFPORT(i), sdpqf);
3741         wr32(hw, TXGBE_5TFCTL0(i), ftqf);
3742
3743         l34timir |= TXGBE_5TFCTL1_QP(filter->queue);
3744         wr32(hw, TXGBE_5TFCTL1(i), l34timir);
3745 }
3746
3747 /*
3748  * add a 5tuple filter
3749  *
3750  * @param
3751  * dev: Pointer to struct rte_eth_dev.
3752  * index: the index the filter allocates.
3753  * filter: pointer to the filter that will be added.
3754  * rx_queue: the queue id the filter assigned to.
3755  *
3756  * @return
3757  *    - On success, zero.
3758  *    - On failure, a negative value.
3759  */
3760 static int
3761 txgbe_add_5tuple_filter(struct rte_eth_dev *dev,
3762                         struct txgbe_5tuple_filter *filter)
3763 {
3764         struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(dev);
3765         int i, idx, shift;
3766
3767         /*
3768          * look for an unused 5tuple filter index,
3769          * and insert the filter to list.
3770          */
3771         for (i = 0; i < TXGBE_MAX_FTQF_FILTERS; i++) {
3772                 idx = i / (sizeof(uint32_t) * NBBY);
3773                 shift = i % (sizeof(uint32_t) * NBBY);
3774                 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
3775                         filter_info->fivetuple_mask[idx] |= 1 << shift;
3776                         filter->index = i;
3777                         TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
3778                                           filter,
3779                                           entries);
3780                         break;
3781                 }
3782         }
3783         if (i >= TXGBE_MAX_FTQF_FILTERS) {
3784                 PMD_DRV_LOG(ERR, "5tuple filters are full.");
3785                 return -ENOSYS;
3786         }
3787
3788         txgbe_inject_5tuple_filter(dev, filter);
3789
3790         return 0;
3791 }
3792
3793 /*
3794  * remove a 5tuple filter
3795  *
3796  * @param
3797  * dev: Pointer to struct rte_eth_dev.
3798  * filter: the pointer of the filter will be removed.
3799  */
3800 static void
3801 txgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
3802                         struct txgbe_5tuple_filter *filter)
3803 {
3804         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3805         struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(dev);
3806         uint16_t index = filter->index;
3807
3808         filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
3809                                 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
3810         TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
3811         rte_free(filter);
3812
3813         wr32(hw, TXGBE_5TFDADDR(index), 0);
3814         wr32(hw, TXGBE_5TFSADDR(index), 0);
3815         wr32(hw, TXGBE_5TFPORT(index), 0);
3816         wr32(hw, TXGBE_5TFCTL0(index), 0);
3817         wr32(hw, TXGBE_5TFCTL1(index), 0);
3818 }
3819
3820 static inline struct txgbe_5tuple_filter *
3821 txgbe_5tuple_filter_lookup(struct txgbe_5tuple_filter_list *filter_list,
3822                         struct txgbe_5tuple_filter_info *key)
3823 {
3824         struct txgbe_5tuple_filter *it;
3825
3826         TAILQ_FOREACH(it, filter_list, entries) {
3827                 if (memcmp(key, &it->filter_info,
3828                         sizeof(struct txgbe_5tuple_filter_info)) == 0) {
3829                         return it;
3830                 }
3831         }
3832         return NULL;
3833 }
3834
3835 /* translate elements in struct rte_eth_ntuple_filter
3836  * to struct txgbe_5tuple_filter_info
3837  */
3838 static inline int
3839 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
3840                         struct txgbe_5tuple_filter_info *filter_info)
3841 {
3842         if (filter->queue >= TXGBE_MAX_RX_QUEUE_NUM ||
3843                 filter->priority > TXGBE_5TUPLE_MAX_PRI ||
3844                 filter->priority < TXGBE_5TUPLE_MIN_PRI)
3845                 return -EINVAL;
3846
3847         switch (filter->dst_ip_mask) {
3848         case UINT32_MAX:
3849                 filter_info->dst_ip_mask = 0;
3850                 filter_info->dst_ip = filter->dst_ip;
3851                 break;
3852         case 0:
3853                 filter_info->dst_ip_mask = 1;
3854                 break;
3855         default:
3856                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
3857                 return -EINVAL;
3858         }
3859
3860         switch (filter->src_ip_mask) {
3861         case UINT32_MAX:
3862                 filter_info->src_ip_mask = 0;
3863                 filter_info->src_ip = filter->src_ip;
3864                 break;
3865         case 0:
3866                 filter_info->src_ip_mask = 1;
3867                 break;
3868         default:
3869                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
3870                 return -EINVAL;
3871         }
3872
3873         switch (filter->dst_port_mask) {
3874         case UINT16_MAX:
3875                 filter_info->dst_port_mask = 0;
3876                 filter_info->dst_port = filter->dst_port;
3877                 break;
3878         case 0:
3879                 filter_info->dst_port_mask = 1;
3880                 break;
3881         default:
3882                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
3883                 return -EINVAL;
3884         }
3885
3886         switch (filter->src_port_mask) {
3887         case UINT16_MAX:
3888                 filter_info->src_port_mask = 0;
3889                 filter_info->src_port = filter->src_port;
3890                 break;
3891         case 0:
3892                 filter_info->src_port_mask = 1;
3893                 break;
3894         default:
3895                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
3896                 return -EINVAL;
3897         }
3898
3899         switch (filter->proto_mask) {
3900         case UINT8_MAX:
3901                 filter_info->proto_mask = 0;
3902                 filter_info->proto =
3903                         convert_protocol_type(filter->proto);
3904                 break;
3905         case 0:
3906                 filter_info->proto_mask = 1;
3907                 break;
3908         default:
3909                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
3910                 return -EINVAL;
3911         }
3912
3913         filter_info->priority = (uint8_t)filter->priority;
3914         return 0;
3915 }
3916
3917 /*
3918  * add or delete a ntuple filter
3919  *
3920  * @param
3921  * dev: Pointer to struct rte_eth_dev.
3922  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
3923  * add: if true, add filter, if false, remove filter
3924  *
3925  * @return
3926  *    - On success, zero.
3927  *    - On failure, a negative value.
3928  */
3929 int
3930 txgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
3931                         struct rte_eth_ntuple_filter *ntuple_filter,
3932                         bool add)
3933 {
3934         struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(dev);
3935         struct txgbe_5tuple_filter_info filter_5tuple;
3936         struct txgbe_5tuple_filter *filter;
3937         int ret;
3938
3939         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
3940                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
3941                 return -EINVAL;
3942         }
3943
3944         memset(&filter_5tuple, 0, sizeof(struct txgbe_5tuple_filter_info));
3945         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
3946         if (ret < 0)
3947                 return ret;
3948
3949         filter = txgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
3950                                          &filter_5tuple);
3951         if (filter != NULL && add) {
3952                 PMD_DRV_LOG(ERR, "filter exists.");
3953                 return -EEXIST;
3954         }
3955         if (filter == NULL && !add) {
3956                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3957                 return -ENOENT;
3958         }
3959
3960         if (add) {
3961                 filter = rte_zmalloc("txgbe_5tuple_filter",
3962                                 sizeof(struct txgbe_5tuple_filter), 0);
3963                 if (filter == NULL)
3964                         return -ENOMEM;
3965                 rte_memcpy(&filter->filter_info,
3966                                  &filter_5tuple,
3967                                  sizeof(struct txgbe_5tuple_filter_info));
3968                 filter->queue = ntuple_filter->queue;
3969                 ret = txgbe_add_5tuple_filter(dev, filter);
3970                 if (ret < 0) {
3971                         rte_free(filter);
3972                         return ret;
3973                 }
3974         } else {
3975                 txgbe_remove_5tuple_filter(dev, filter);
3976         }
3977
3978         return 0;
3979 }
3980
3981 int
3982 txgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
3983                         struct rte_eth_ethertype_filter *filter,
3984                         bool add)
3985 {
3986         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3987         struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(dev);
3988         uint32_t etqf = 0;
3989         uint32_t etqs = 0;
3990         int ret;
3991         struct txgbe_ethertype_filter ethertype_filter;
3992
3993         if (filter->queue >= TXGBE_MAX_RX_QUEUE_NUM)
3994                 return -EINVAL;
3995
3996         if (filter->ether_type == RTE_ETHER_TYPE_IPV4 ||
3997             filter->ether_type == RTE_ETHER_TYPE_IPV6) {
3998                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
3999                         " ethertype filter.", filter->ether_type);
4000                 return -EINVAL;
4001         }
4002
4003         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
4004                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
4005                 return -EINVAL;
4006         }
4007         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
4008                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
4009                 return -EINVAL;
4010         }
4011
4012         ret = txgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
4013         if (ret >= 0 && add) {
4014                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
4015                             filter->ether_type);
4016                 return -EEXIST;
4017         }
4018         if (ret < 0 && !add) {
4019                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
4020                             filter->ether_type);
4021                 return -ENOENT;
4022         }
4023
4024         if (add) {
4025                 etqf = TXGBE_ETFLT_ENA;
4026                 etqf |= TXGBE_ETFLT_ETID(filter->ether_type);
4027                 etqs |= TXGBE_ETCLS_QPID(filter->queue);
4028                 etqs |= TXGBE_ETCLS_QENA;
4029
4030                 ethertype_filter.ethertype = filter->ether_type;
4031                 ethertype_filter.etqf = etqf;
4032                 ethertype_filter.etqs = etqs;
4033                 ethertype_filter.conf = FALSE;
4034                 ret = txgbe_ethertype_filter_insert(filter_info,
4035                                                     &ethertype_filter);
4036                 if (ret < 0) {
4037                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
4038                         return -ENOSPC;
4039                 }
4040         } else {
4041                 ret = txgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
4042                 if (ret < 0)
4043                         return -ENOSYS;
4044         }
4045         wr32(hw, TXGBE_ETFLT(ret), etqf);
4046         wr32(hw, TXGBE_ETCLS(ret), etqs);
4047         txgbe_flush(hw);
4048
4049         return 0;
4050 }
4051
4052 static int
4053 txgbe_dev_filter_ctrl(__rte_unused struct rte_eth_dev *dev,
4054                      enum rte_filter_type filter_type,
4055                      enum rte_filter_op filter_op,
4056                      void *arg)
4057 {
4058         int ret = 0;
4059
4060         switch (filter_type) {
4061         case RTE_ETH_FILTER_GENERIC:
4062                 if (filter_op != RTE_ETH_FILTER_GET)
4063                         return -EINVAL;
4064                 *(const void **)arg = &txgbe_flow_ops;
4065                 break;
4066         default:
4067                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
4068                                                         filter_type);
4069                 ret = -EINVAL;
4070                 break;
4071         }
4072
4073         return ret;
4074 }
4075
4076 static u8 *
4077 txgbe_dev_addr_list_itr(__rte_unused struct txgbe_hw *hw,
4078                         u8 **mc_addr_ptr, u32 *vmdq)
4079 {
4080         u8 *mc_addr;
4081
4082         *vmdq = 0;
4083         mc_addr = *mc_addr_ptr;
4084         *mc_addr_ptr = (mc_addr + sizeof(struct rte_ether_addr));
4085         return mc_addr;
4086 }
4087
4088 int
4089 txgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
4090                           struct rte_ether_addr *mc_addr_set,
4091                           uint32_t nb_mc_addr)
4092 {
4093         struct txgbe_hw *hw;
4094         u8 *mc_addr_list;
4095
4096         hw = TXGBE_DEV_HW(dev);
4097         mc_addr_list = (u8 *)mc_addr_set;
4098         return txgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
4099                                          txgbe_dev_addr_list_itr, TRUE);
4100 }
4101
4102 static uint64_t
4103 txgbe_read_systime_cyclecounter(struct rte_eth_dev *dev)
4104 {
4105         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4106         uint64_t systime_cycles;
4107
4108         systime_cycles = (uint64_t)rd32(hw, TXGBE_TSTIMEL);
4109         systime_cycles |= (uint64_t)rd32(hw, TXGBE_TSTIMEH) << 32;
4110
4111         return systime_cycles;
4112 }
4113
4114 static uint64_t
4115 txgbe_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
4116 {
4117         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4118         uint64_t rx_tstamp_cycles;
4119
4120         /* TSRXSTMPL stores ns and TSRXSTMPH stores seconds. */
4121         rx_tstamp_cycles = (uint64_t)rd32(hw, TXGBE_TSRXSTMPL);
4122         rx_tstamp_cycles |= (uint64_t)rd32(hw, TXGBE_TSRXSTMPH) << 32;
4123
4124         return rx_tstamp_cycles;
4125 }
4126
4127 static uint64_t
4128 txgbe_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
4129 {
4130         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4131         uint64_t tx_tstamp_cycles;
4132
4133         /* TSTXSTMPL stores ns and TSTXSTMPH stores seconds. */
4134         tx_tstamp_cycles = (uint64_t)rd32(hw, TXGBE_TSTXSTMPL);
4135         tx_tstamp_cycles |= (uint64_t)rd32(hw, TXGBE_TSTXSTMPH) << 32;
4136
4137         return tx_tstamp_cycles;
4138 }
4139
4140 static void
4141 txgbe_start_timecounters(struct rte_eth_dev *dev)
4142 {
4143         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4144         struct txgbe_adapter *adapter = TXGBE_DEV_ADAPTER(dev);
4145         struct rte_eth_link link;
4146         uint32_t incval = 0;
4147         uint32_t shift = 0;
4148
4149         /* Get current link speed. */
4150         txgbe_dev_link_update(dev, 1);
4151         rte_eth_linkstatus_get(dev, &link);
4152
4153         switch (link.link_speed) {
4154         case ETH_SPEED_NUM_100M:
4155                 incval = TXGBE_INCVAL_100;
4156                 shift = TXGBE_INCVAL_SHIFT_100;
4157                 break;
4158         case ETH_SPEED_NUM_1G:
4159                 incval = TXGBE_INCVAL_1GB;
4160                 shift = TXGBE_INCVAL_SHIFT_1GB;
4161                 break;
4162         case ETH_SPEED_NUM_10G:
4163         default:
4164                 incval = TXGBE_INCVAL_10GB;
4165                 shift = TXGBE_INCVAL_SHIFT_10GB;
4166                 break;
4167         }
4168
4169         wr32(hw, TXGBE_TSTIMEINC, TXGBE_TSTIMEINC_VP(incval, 2));
4170
4171         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
4172         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
4173         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
4174
4175         adapter->systime_tc.cc_mask = TXGBE_CYCLECOUNTER_MASK;
4176         adapter->systime_tc.cc_shift = shift;
4177         adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
4178
4179         adapter->rx_tstamp_tc.cc_mask = TXGBE_CYCLECOUNTER_MASK;
4180         adapter->rx_tstamp_tc.cc_shift = shift;
4181         adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
4182
4183         adapter->tx_tstamp_tc.cc_mask = TXGBE_CYCLECOUNTER_MASK;
4184         adapter->tx_tstamp_tc.cc_shift = shift;
4185         adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
4186 }
4187
4188 static int
4189 txgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
4190 {
4191         struct txgbe_adapter *adapter = TXGBE_DEV_ADAPTER(dev);
4192
4193         adapter->systime_tc.nsec += delta;
4194         adapter->rx_tstamp_tc.nsec += delta;
4195         adapter->tx_tstamp_tc.nsec += delta;
4196
4197         return 0;
4198 }
4199
4200 static int
4201 txgbe_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
4202 {
4203         uint64_t ns;
4204         struct txgbe_adapter *adapter = TXGBE_DEV_ADAPTER(dev);
4205
4206         ns = rte_timespec_to_ns(ts);
4207         /* Set the timecounters to a new value. */
4208         adapter->systime_tc.nsec = ns;
4209         adapter->rx_tstamp_tc.nsec = ns;
4210         adapter->tx_tstamp_tc.nsec = ns;
4211
4212         return 0;
4213 }
4214
4215 static int
4216 txgbe_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
4217 {
4218         uint64_t ns, systime_cycles;
4219         struct txgbe_adapter *adapter = TXGBE_DEV_ADAPTER(dev);
4220
4221         systime_cycles = txgbe_read_systime_cyclecounter(dev);
4222         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
4223         *ts = rte_ns_to_timespec(ns);
4224
4225         return 0;
4226 }
4227
4228 static int
4229 txgbe_timesync_enable(struct rte_eth_dev *dev)
4230 {
4231         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4232         uint32_t tsync_ctl;
4233
4234         /* Stop the timesync system time. */
4235         wr32(hw, TXGBE_TSTIMEINC, 0x0);
4236         /* Reset the timesync system time value. */
4237         wr32(hw, TXGBE_TSTIMEL, 0x0);
4238         wr32(hw, TXGBE_TSTIMEH, 0x0);
4239
4240         txgbe_start_timecounters(dev);
4241
4242         /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
4243         wr32(hw, TXGBE_ETFLT(TXGBE_ETF_ID_1588),
4244                 RTE_ETHER_TYPE_1588 | TXGBE_ETFLT_ENA | TXGBE_ETFLT_1588);
4245
4246         /* Enable timestamping of received PTP packets. */
4247         tsync_ctl = rd32(hw, TXGBE_TSRXCTL);
4248         tsync_ctl |= TXGBE_TSRXCTL_ENA;
4249         wr32(hw, TXGBE_TSRXCTL, tsync_ctl);
4250
4251         /* Enable timestamping of transmitted PTP packets. */
4252         tsync_ctl = rd32(hw, TXGBE_TSTXCTL);
4253         tsync_ctl |= TXGBE_TSTXCTL_ENA;
4254         wr32(hw, TXGBE_TSTXCTL, tsync_ctl);
4255
4256         txgbe_flush(hw);
4257
4258         return 0;
4259 }
4260
4261 static int
4262 txgbe_timesync_disable(struct rte_eth_dev *dev)
4263 {
4264         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4265         uint32_t tsync_ctl;
4266
4267         /* Disable timestamping of transmitted PTP packets. */
4268         tsync_ctl = rd32(hw, TXGBE_TSTXCTL);
4269         tsync_ctl &= ~TXGBE_TSTXCTL_ENA;
4270         wr32(hw, TXGBE_TSTXCTL, tsync_ctl);
4271
4272         /* Disable timestamping of received PTP packets. */
4273         tsync_ctl = rd32(hw, TXGBE_TSRXCTL);
4274         tsync_ctl &= ~TXGBE_TSRXCTL_ENA;
4275         wr32(hw, TXGBE_TSRXCTL, tsync_ctl);
4276
4277         /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
4278         wr32(hw, TXGBE_ETFLT(TXGBE_ETF_ID_1588), 0);
4279
4280         /* Stop incrementating the System Time registers. */
4281         wr32(hw, TXGBE_TSTIMEINC, 0);
4282
4283         return 0;
4284 }
4285
4286 static int
4287 txgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
4288                                  struct timespec *timestamp,
4289                                  uint32_t flags __rte_unused)
4290 {
4291         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4292         struct txgbe_adapter *adapter = TXGBE_DEV_ADAPTER(dev);
4293         uint32_t tsync_rxctl;
4294         uint64_t rx_tstamp_cycles;
4295         uint64_t ns;
4296
4297         tsync_rxctl = rd32(hw, TXGBE_TSRXCTL);
4298         if ((tsync_rxctl & TXGBE_TSRXCTL_VLD) == 0)
4299                 return -EINVAL;
4300
4301         rx_tstamp_cycles = txgbe_read_rx_tstamp_cyclecounter(dev);
4302         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
4303         *timestamp = rte_ns_to_timespec(ns);
4304
4305         return  0;
4306 }
4307
4308 static int
4309 txgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
4310                                  struct timespec *timestamp)
4311 {
4312         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4313         struct txgbe_adapter *adapter = TXGBE_DEV_ADAPTER(dev);
4314         uint32_t tsync_txctl;
4315         uint64_t tx_tstamp_cycles;
4316         uint64_t ns;
4317
4318         tsync_txctl = rd32(hw, TXGBE_TSTXCTL);
4319         if ((tsync_txctl & TXGBE_TSTXCTL_VLD) == 0)
4320                 return -EINVAL;
4321
4322         tx_tstamp_cycles = txgbe_read_tx_tstamp_cyclecounter(dev);
4323         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
4324         *timestamp = rte_ns_to_timespec(ns);
4325
4326         return 0;
4327 }
4328
4329 static int
4330 txgbe_get_reg_length(struct rte_eth_dev *dev __rte_unused)
4331 {
4332         int count = 0;
4333         int g_ind = 0;
4334         const struct reg_info *reg_group;
4335         const struct reg_info **reg_set = txgbe_regs_others;
4336
4337         while ((reg_group = reg_set[g_ind++]))
4338                 count += txgbe_regs_group_count(reg_group);
4339
4340         return count;
4341 }
4342
4343 static int
4344 txgbe_get_regs(struct rte_eth_dev *dev,
4345               struct rte_dev_reg_info *regs)
4346 {
4347         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4348         uint32_t *data = regs->data;
4349         int g_ind = 0;
4350         int count = 0;
4351         const struct reg_info *reg_group;
4352         const struct reg_info **reg_set = txgbe_regs_others;
4353
4354         if (data == NULL) {
4355                 regs->length = txgbe_get_reg_length(dev);
4356                 regs->width = sizeof(uint32_t);
4357                 return 0;
4358         }
4359
4360         /* Support only full register dump */
4361         if (regs->length == 0 ||
4362             regs->length == (uint32_t)txgbe_get_reg_length(dev)) {
4363                 regs->version = hw->mac.type << 24 |
4364                                 hw->revision_id << 16 |
4365                                 hw->device_id;
4366                 while ((reg_group = reg_set[g_ind++]))
4367                         count += txgbe_read_regs_group(dev, &data[count],
4368                                                       reg_group);
4369                 return 0;
4370         }
4371
4372         return -ENOTSUP;
4373 }
4374
4375 static int
4376 txgbe_get_eeprom_length(struct rte_eth_dev *dev)
4377 {
4378         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4379
4380         /* Return unit is byte count */
4381         return hw->rom.word_size * 2;
4382 }
4383
4384 static int
4385 txgbe_get_eeprom(struct rte_eth_dev *dev,
4386                 struct rte_dev_eeprom_info *in_eeprom)
4387 {
4388         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4389         struct txgbe_rom_info *eeprom = &hw->rom;
4390         uint16_t *data = in_eeprom->data;
4391         int first, length;
4392
4393         first = in_eeprom->offset >> 1;
4394         length = in_eeprom->length >> 1;
4395         if (first > hw->rom.word_size ||
4396             ((first + length) > hw->rom.word_size))
4397                 return -EINVAL;
4398
4399         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
4400
4401         return eeprom->readw_buffer(hw, first, length, data);
4402 }
4403
4404 static int
4405 txgbe_set_eeprom(struct rte_eth_dev *dev,
4406                 struct rte_dev_eeprom_info *in_eeprom)
4407 {
4408         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4409         struct txgbe_rom_info *eeprom = &hw->rom;
4410         uint16_t *data = in_eeprom->data;
4411         int first, length;
4412
4413         first = in_eeprom->offset >> 1;
4414         length = in_eeprom->length >> 1;
4415         if (first > hw->rom.word_size ||
4416             ((first + length) > hw->rom.word_size))
4417                 return -EINVAL;
4418
4419         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
4420
4421         return eeprom->writew_buffer(hw,  first, length, data);
4422 }
4423
4424 static int
4425 txgbe_get_module_info(struct rte_eth_dev *dev,
4426                       struct rte_eth_dev_module_info *modinfo)
4427 {
4428         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4429         uint32_t status;
4430         uint8_t sff8472_rev, addr_mode;
4431         bool page_swap = false;
4432
4433         /* Check whether we support SFF-8472 or not */
4434         status = hw->phy.read_i2c_eeprom(hw,
4435                                              TXGBE_SFF_SFF_8472_COMP,
4436                                              &sff8472_rev);
4437         if (status != 0)
4438                 return -EIO;
4439
4440         /* addressing mode is not supported */
4441         status = hw->phy.read_i2c_eeprom(hw,
4442                                              TXGBE_SFF_SFF_8472_SWAP,
4443                                              &addr_mode);
4444         if (status != 0)
4445                 return -EIO;
4446
4447         if (addr_mode & TXGBE_SFF_ADDRESSING_MODE) {
4448                 PMD_DRV_LOG(ERR,
4449                             "Address change required to access page 0xA2, "
4450                             "but not supported. Please report the module "
4451                             "type to the driver maintainers.");
4452                 page_swap = true;
4453         }
4454
4455         if (sff8472_rev == TXGBE_SFF_SFF_8472_UNSUP || page_swap) {
4456                 /* We have a SFP, but it does not support SFF-8472 */
4457                 modinfo->type = RTE_ETH_MODULE_SFF_8079;
4458                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
4459         } else {
4460                 /* We have a SFP which supports a revision of SFF-8472. */
4461                 modinfo->type = RTE_ETH_MODULE_SFF_8472;
4462                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
4463         }
4464
4465         return 0;
4466 }
4467
4468 static int
4469 txgbe_get_module_eeprom(struct rte_eth_dev *dev,
4470                         struct rte_dev_eeprom_info *info)
4471 {
4472         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4473         uint32_t status = TXGBE_ERR_PHY_ADDR_INVALID;
4474         uint8_t databyte = 0xFF;
4475         uint8_t *data = info->data;
4476         uint32_t i = 0;
4477
4478         if (info->length == 0)
4479                 return -EINVAL;
4480
4481         for (i = info->offset; i < info->offset + info->length; i++) {
4482                 if (i < RTE_ETH_MODULE_SFF_8079_LEN)
4483                         status = hw->phy.read_i2c_eeprom(hw, i, &databyte);
4484                 else
4485                         status = hw->phy.read_i2c_sff8472(hw, i, &databyte);
4486
4487                 if (status != 0)
4488                         return -EIO;
4489
4490                 data[i - info->offset] = databyte;
4491         }
4492
4493         return 0;
4494 }
4495
4496 bool
4497 txgbe_rss_update_sp(enum txgbe_mac_type mac_type)
4498 {
4499         switch (mac_type) {
4500         case txgbe_mac_raptor:
4501                 return 1;
4502         default:
4503                 return 0;
4504         }
4505 }
4506
4507 static int
4508 txgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
4509                         struct rte_eth_dcb_info *dcb_info)
4510 {
4511         struct txgbe_dcb_config *dcb_config = TXGBE_DEV_DCB_CONFIG(dev);
4512         struct txgbe_dcb_tc_config *tc;
4513         struct rte_eth_dcb_tc_queue_mapping *tc_queue;
4514         uint8_t nb_tcs;
4515         uint8_t i, j;
4516
4517         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
4518                 dcb_info->nb_tcs = dcb_config->num_tcs.pg_tcs;
4519         else
4520                 dcb_info->nb_tcs = 1;
4521
4522         tc_queue = &dcb_info->tc_queue;
4523         nb_tcs = dcb_info->nb_tcs;
4524
4525         if (dcb_config->vt_mode) { /* vt is enabled */
4526                 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
4527                                 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
4528                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
4529                         dcb_info->prio_tc[i] = vmdq_rx_conf->dcb_tc[i];
4530                 if (RTE_ETH_DEV_SRIOV(dev).active > 0) {
4531                         for (j = 0; j < nb_tcs; j++) {
4532                                 tc_queue->tc_rxq[0][j].base = j;
4533                                 tc_queue->tc_rxq[0][j].nb_queue = 1;
4534                                 tc_queue->tc_txq[0][j].base = j;
4535                                 tc_queue->tc_txq[0][j].nb_queue = 1;
4536                         }
4537                 } else {
4538                         for (i = 0; i < vmdq_rx_conf->nb_queue_pools; i++) {
4539                                 for (j = 0; j < nb_tcs; j++) {
4540                                         tc_queue->tc_rxq[i][j].base =
4541                                                 i * nb_tcs + j;
4542                                         tc_queue->tc_rxq[i][j].nb_queue = 1;
4543                                         tc_queue->tc_txq[i][j].base =
4544                                                 i * nb_tcs + j;
4545                                         tc_queue->tc_txq[i][j].nb_queue = 1;
4546                                 }
4547                         }
4548                 }
4549         } else { /* vt is disabled */
4550                 struct rte_eth_dcb_rx_conf *rx_conf =
4551                                 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
4552                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
4553                         dcb_info->prio_tc[i] = rx_conf->dcb_tc[i];
4554                 if (dcb_info->nb_tcs == ETH_4_TCS) {
4555                         for (i = 0; i < dcb_info->nb_tcs; i++) {
4556                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 32;
4557                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
4558                         }
4559                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
4560                         dcb_info->tc_queue.tc_txq[0][1].base = 64;
4561                         dcb_info->tc_queue.tc_txq[0][2].base = 96;
4562                         dcb_info->tc_queue.tc_txq[0][3].base = 112;
4563                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 64;
4564                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
4565                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
4566                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
4567                 } else if (dcb_info->nb_tcs == ETH_8_TCS) {
4568                         for (i = 0; i < dcb_info->nb_tcs; i++) {
4569                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 16;
4570                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
4571                         }
4572                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
4573                         dcb_info->tc_queue.tc_txq[0][1].base = 32;
4574                         dcb_info->tc_queue.tc_txq[0][2].base = 64;
4575                         dcb_info->tc_queue.tc_txq[0][3].base = 80;
4576                         dcb_info->tc_queue.tc_txq[0][4].base = 96;
4577                         dcb_info->tc_queue.tc_txq[0][5].base = 104;
4578                         dcb_info->tc_queue.tc_txq[0][6].base = 112;
4579                         dcb_info->tc_queue.tc_txq[0][7].base = 120;
4580                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 32;
4581                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
4582                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
4583                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
4584                         dcb_info->tc_queue.tc_txq[0][4].nb_queue = 8;
4585                         dcb_info->tc_queue.tc_txq[0][5].nb_queue = 8;
4586                         dcb_info->tc_queue.tc_txq[0][6].nb_queue = 8;
4587                         dcb_info->tc_queue.tc_txq[0][7].nb_queue = 8;
4588                 }
4589         }
4590         for (i = 0; i < dcb_info->nb_tcs; i++) {
4591                 tc = &dcb_config->tc_config[i];
4592                 dcb_info->tc_bws[i] = tc->path[TXGBE_DCB_TX_CONFIG].bwg_percent;
4593         }
4594         return 0;
4595 }
4596
4597 /* Update e-tag ether type */
4598 static int
4599 txgbe_update_e_tag_eth_type(struct txgbe_hw *hw,
4600                             uint16_t ether_type)
4601 {
4602         uint32_t etag_etype;
4603
4604         etag_etype = rd32(hw, TXGBE_EXTAG);
4605         etag_etype &= ~TXGBE_EXTAG_ETAG_MASK;
4606         etag_etype |= ether_type;
4607         wr32(hw, TXGBE_EXTAG, etag_etype);
4608         txgbe_flush(hw);
4609
4610         return 0;
4611 }
4612
4613 /* Enable e-tag tunnel */
4614 static int
4615 txgbe_e_tag_enable(struct txgbe_hw *hw)
4616 {
4617         uint32_t etag_etype;
4618
4619         etag_etype = rd32(hw, TXGBE_PORTCTL);
4620         etag_etype |= TXGBE_PORTCTL_ETAG;
4621         wr32(hw, TXGBE_PORTCTL, etag_etype);
4622         txgbe_flush(hw);
4623
4624         return 0;
4625 }
4626
4627 static int
4628 txgbe_e_tag_filter_del(struct rte_eth_dev *dev,
4629                        struct txgbe_l2_tunnel_conf  *l2_tunnel)
4630 {
4631         int ret = 0;
4632         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4633         uint32_t i, rar_entries;
4634         uint32_t rar_low, rar_high;
4635
4636         rar_entries = hw->mac.num_rar_entries;
4637
4638         for (i = 1; i < rar_entries; i++) {
4639                 wr32(hw, TXGBE_ETHADDRIDX, i);
4640                 rar_high = rd32(hw, TXGBE_ETHADDRH);
4641                 rar_low  = rd32(hw, TXGBE_ETHADDRL);
4642                 if ((rar_high & TXGBE_ETHADDRH_VLD) &&
4643                     (rar_high & TXGBE_ETHADDRH_ETAG) &&
4644                     (TXGBE_ETHADDRL_ETAG(rar_low) ==
4645                      l2_tunnel->tunnel_id)) {
4646                         wr32(hw, TXGBE_ETHADDRL, 0);
4647                         wr32(hw, TXGBE_ETHADDRH, 0);
4648
4649                         txgbe_clear_vmdq(hw, i, BIT_MASK32);
4650
4651                         return ret;
4652                 }
4653         }
4654
4655         return ret;
4656 }
4657
4658 static int
4659 txgbe_e_tag_filter_add(struct rte_eth_dev *dev,
4660                        struct txgbe_l2_tunnel_conf *l2_tunnel)
4661 {
4662         int ret = 0;
4663         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4664         uint32_t i, rar_entries;
4665         uint32_t rar_low, rar_high;
4666
4667         /* One entry for one tunnel. Try to remove potential existing entry. */
4668         txgbe_e_tag_filter_del(dev, l2_tunnel);
4669
4670         rar_entries = hw->mac.num_rar_entries;
4671
4672         for (i = 1; i < rar_entries; i++) {
4673                 wr32(hw, TXGBE_ETHADDRIDX, i);
4674                 rar_high = rd32(hw, TXGBE_ETHADDRH);
4675                 if (rar_high & TXGBE_ETHADDRH_VLD) {
4676                         continue;
4677                 } else {
4678                         txgbe_set_vmdq(hw, i, l2_tunnel->pool);
4679                         rar_high = TXGBE_ETHADDRH_VLD | TXGBE_ETHADDRH_ETAG;
4680                         rar_low = l2_tunnel->tunnel_id;
4681
4682                         wr32(hw, TXGBE_ETHADDRL, rar_low);
4683                         wr32(hw, TXGBE_ETHADDRH, rar_high);
4684
4685                         return ret;
4686                 }
4687         }
4688
4689         PMD_INIT_LOG(NOTICE, "The table of E-tag forwarding rule is full."
4690                      " Please remove a rule before adding a new one.");
4691         return -EINVAL;
4692 }
4693
4694 static inline struct txgbe_l2_tn_filter *
4695 txgbe_l2_tn_filter_lookup(struct txgbe_l2_tn_info *l2_tn_info,
4696                           struct txgbe_l2_tn_key *key)
4697 {
4698         int ret;
4699
4700         ret = rte_hash_lookup(l2_tn_info->hash_handle, (const void *)key);
4701         if (ret < 0)
4702                 return NULL;
4703
4704         return l2_tn_info->hash_map[ret];
4705 }
4706
4707 static inline int
4708 txgbe_insert_l2_tn_filter(struct txgbe_l2_tn_info *l2_tn_info,
4709                           struct txgbe_l2_tn_filter *l2_tn_filter)
4710 {
4711         int ret;
4712
4713         ret = rte_hash_add_key(l2_tn_info->hash_handle,
4714                                &l2_tn_filter->key);
4715
4716         if (ret < 0) {
4717                 PMD_DRV_LOG(ERR,
4718                             "Failed to insert L2 tunnel filter"
4719                             " to hash table %d!",
4720                             ret);
4721                 return ret;
4722         }
4723
4724         l2_tn_info->hash_map[ret] = l2_tn_filter;
4725
4726         TAILQ_INSERT_TAIL(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
4727
4728         return 0;
4729 }
4730
4731 static inline int
4732 txgbe_remove_l2_tn_filter(struct txgbe_l2_tn_info *l2_tn_info,
4733                           struct txgbe_l2_tn_key *key)
4734 {
4735         int ret;
4736         struct txgbe_l2_tn_filter *l2_tn_filter;
4737
4738         ret = rte_hash_del_key(l2_tn_info->hash_handle, key);
4739
4740         if (ret < 0) {
4741                 PMD_DRV_LOG(ERR,
4742                             "No such L2 tunnel filter to delete %d!",
4743                             ret);
4744                 return ret;
4745         }
4746
4747         l2_tn_filter = l2_tn_info->hash_map[ret];
4748         l2_tn_info->hash_map[ret] = NULL;
4749
4750         TAILQ_REMOVE(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
4751         rte_free(l2_tn_filter);
4752
4753         return 0;
4754 }
4755
4756 /* Add l2 tunnel filter */
4757 int
4758 txgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev,
4759                                struct txgbe_l2_tunnel_conf *l2_tunnel,
4760                                bool restore)
4761 {
4762         int ret;
4763         struct txgbe_l2_tn_info *l2_tn_info = TXGBE_DEV_L2_TN(dev);
4764         struct txgbe_l2_tn_key key;
4765         struct txgbe_l2_tn_filter *node;
4766
4767         if (!restore) {
4768                 key.l2_tn_type = l2_tunnel->l2_tunnel_type;
4769                 key.tn_id = l2_tunnel->tunnel_id;
4770
4771                 node = txgbe_l2_tn_filter_lookup(l2_tn_info, &key);
4772
4773                 if (node) {
4774                         PMD_DRV_LOG(ERR,
4775                                     "The L2 tunnel filter already exists!");
4776                         return -EINVAL;
4777                 }
4778
4779                 node = rte_zmalloc("txgbe_l2_tn",
4780                                    sizeof(struct txgbe_l2_tn_filter),
4781                                    0);
4782                 if (!node)
4783                         return -ENOMEM;
4784
4785                 rte_memcpy(&node->key,
4786                                  &key,
4787                                  sizeof(struct txgbe_l2_tn_key));
4788                 node->pool = l2_tunnel->pool;
4789                 ret = txgbe_insert_l2_tn_filter(l2_tn_info, node);
4790                 if (ret < 0) {
4791                         rte_free(node);
4792                         return ret;
4793                 }
4794         }
4795
4796         switch (l2_tunnel->l2_tunnel_type) {
4797         case RTE_L2_TUNNEL_TYPE_E_TAG:
4798                 ret = txgbe_e_tag_filter_add(dev, l2_tunnel);
4799                 break;
4800         default:
4801                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
4802                 ret = -EINVAL;
4803                 break;
4804         }
4805
4806         if (!restore && ret < 0)
4807                 (void)txgbe_remove_l2_tn_filter(l2_tn_info, &key);
4808
4809         return ret;
4810 }
4811
4812 /* Delete l2 tunnel filter */
4813 int
4814 txgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev,
4815                                struct txgbe_l2_tunnel_conf *l2_tunnel)
4816 {
4817         int ret;
4818         struct txgbe_l2_tn_info *l2_tn_info = TXGBE_DEV_L2_TN(dev);
4819         struct txgbe_l2_tn_key key;
4820
4821         key.l2_tn_type = l2_tunnel->l2_tunnel_type;
4822         key.tn_id = l2_tunnel->tunnel_id;
4823         ret = txgbe_remove_l2_tn_filter(l2_tn_info, &key);
4824         if (ret < 0)
4825                 return ret;
4826
4827         switch (l2_tunnel->l2_tunnel_type) {
4828         case RTE_L2_TUNNEL_TYPE_E_TAG:
4829                 ret = txgbe_e_tag_filter_del(dev, l2_tunnel);
4830                 break;
4831         default:
4832                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
4833                 ret = -EINVAL;
4834                 break;
4835         }
4836
4837         return ret;
4838 }
4839
4840 static int
4841 txgbe_e_tag_forwarding_en_dis(struct rte_eth_dev *dev, bool en)
4842 {
4843         int ret = 0;
4844         uint32_t ctrl;
4845         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4846
4847         ctrl = rd32(hw, TXGBE_POOLCTL);
4848         ctrl &= ~TXGBE_POOLCTL_MODE_MASK;
4849         if (en)
4850                 ctrl |= TXGBE_PSRPOOL_MODE_ETAG;
4851         wr32(hw, TXGBE_POOLCTL, ctrl);
4852
4853         return ret;
4854 }
4855
4856 /* Add UDP tunneling port */
4857 static int
4858 txgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
4859                               struct rte_eth_udp_tunnel *udp_tunnel)
4860 {
4861         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4862         int ret = 0;
4863
4864         if (udp_tunnel == NULL)
4865                 return -EINVAL;
4866
4867         switch (udp_tunnel->prot_type) {
4868         case RTE_TUNNEL_TYPE_VXLAN:
4869                 if (udp_tunnel->udp_port == 0) {
4870                         PMD_DRV_LOG(ERR, "Add VxLAN port 0 is not allowed.");
4871                         ret = -EINVAL;
4872                         break;
4873                 }
4874                 wr32(hw, TXGBE_VXLANPORT, udp_tunnel->udp_port);
4875                 wr32(hw, TXGBE_VXLANPORTGPE, udp_tunnel->udp_port);
4876                 break;
4877         case RTE_TUNNEL_TYPE_GENEVE:
4878                 if (udp_tunnel->udp_port == 0) {
4879                         PMD_DRV_LOG(ERR, "Add Geneve port 0 is not allowed.");
4880                         ret = -EINVAL;
4881                         break;
4882                 }
4883                 wr32(hw, TXGBE_GENEVEPORT, udp_tunnel->udp_port);
4884                 break;
4885         case RTE_TUNNEL_TYPE_TEREDO:
4886                 if (udp_tunnel->udp_port == 0) {
4887                         PMD_DRV_LOG(ERR, "Add Teredo port 0 is not allowed.");
4888                         ret = -EINVAL;
4889                         break;
4890                 }
4891                 wr32(hw, TXGBE_TEREDOPORT, udp_tunnel->udp_port);
4892                 break;
4893         default:
4894                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
4895                 ret = -EINVAL;
4896                 break;
4897         }
4898
4899         txgbe_flush(hw);
4900
4901         return ret;
4902 }
4903
4904 /* Remove UDP tunneling port */
4905 static int
4906 txgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
4907                               struct rte_eth_udp_tunnel *udp_tunnel)
4908 {
4909         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4910         int ret = 0;
4911         uint16_t cur_port;
4912
4913         if (udp_tunnel == NULL)
4914                 return -EINVAL;
4915
4916         switch (udp_tunnel->prot_type) {
4917         case RTE_TUNNEL_TYPE_VXLAN:
4918                 cur_port = (uint16_t)rd32(hw, TXGBE_VXLANPORT);
4919                 if (cur_port != udp_tunnel->udp_port) {
4920                         PMD_DRV_LOG(ERR, "Port %u does not exist.",
4921                                         udp_tunnel->udp_port);
4922                         ret = -EINVAL;
4923                         break;
4924                 }
4925                 wr32(hw, TXGBE_VXLANPORT, 0);
4926                 wr32(hw, TXGBE_VXLANPORTGPE, 0);
4927                 break;
4928         case RTE_TUNNEL_TYPE_GENEVE:
4929                 cur_port = (uint16_t)rd32(hw, TXGBE_GENEVEPORT);
4930                 if (cur_port != udp_tunnel->udp_port) {
4931                         PMD_DRV_LOG(ERR, "Port %u does not exist.",
4932                                         udp_tunnel->udp_port);
4933                         ret = -EINVAL;
4934                         break;
4935                 }
4936                 wr32(hw, TXGBE_GENEVEPORT, 0);
4937                 break;
4938         case RTE_TUNNEL_TYPE_TEREDO:
4939                 cur_port = (uint16_t)rd32(hw, TXGBE_TEREDOPORT);
4940                 if (cur_port != udp_tunnel->udp_port) {
4941                         PMD_DRV_LOG(ERR, "Port %u does not exist.",
4942                                         udp_tunnel->udp_port);
4943                         ret = -EINVAL;
4944                         break;
4945                 }
4946                 wr32(hw, TXGBE_TEREDOPORT, 0);
4947                 break;
4948         default:
4949                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
4950                 ret = -EINVAL;
4951                 break;
4952         }
4953
4954         txgbe_flush(hw);
4955
4956         return ret;
4957 }
4958
4959 /* restore n-tuple filter */
4960 static inline void
4961 txgbe_ntuple_filter_restore(struct rte_eth_dev *dev)
4962 {
4963         struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(dev);
4964         struct txgbe_5tuple_filter *node;
4965
4966         TAILQ_FOREACH(node, &filter_info->fivetuple_list, entries) {
4967                 txgbe_inject_5tuple_filter(dev, node);
4968         }
4969 }
4970
4971 /* restore ethernet type filter */
4972 static inline void
4973 txgbe_ethertype_filter_restore(struct rte_eth_dev *dev)
4974 {
4975         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4976         struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(dev);
4977         int i;
4978
4979         for (i = 0; i < TXGBE_ETF_ID_MAX; i++) {
4980                 if (filter_info->ethertype_mask & (1 << i)) {
4981                         wr32(hw, TXGBE_ETFLT(i),
4982                                         filter_info->ethertype_filters[i].etqf);
4983                         wr32(hw, TXGBE_ETCLS(i),
4984                                         filter_info->ethertype_filters[i].etqs);
4985                         txgbe_flush(hw);
4986                 }
4987         }
4988 }
4989
4990 /* restore SYN filter */
4991 static inline void
4992 txgbe_syn_filter_restore(struct rte_eth_dev *dev)
4993 {
4994         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4995         struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(dev);
4996         uint32_t synqf;
4997
4998         synqf = filter_info->syn_info;
4999
5000         if (synqf & TXGBE_SYNCLS_ENA) {
5001                 wr32(hw, TXGBE_SYNCLS, synqf);
5002                 txgbe_flush(hw);
5003         }
5004 }
5005
5006 /* restore L2 tunnel filter */
5007 static inline void
5008 txgbe_l2_tn_filter_restore(struct rte_eth_dev *dev)
5009 {
5010         struct txgbe_l2_tn_info *l2_tn_info = TXGBE_DEV_L2_TN(dev);
5011         struct txgbe_l2_tn_filter *node;
5012         struct txgbe_l2_tunnel_conf l2_tn_conf;
5013
5014         TAILQ_FOREACH(node, &l2_tn_info->l2_tn_list, entries) {
5015                 l2_tn_conf.l2_tunnel_type = node->key.l2_tn_type;
5016                 l2_tn_conf.tunnel_id      = node->key.tn_id;
5017                 l2_tn_conf.pool           = node->pool;
5018                 (void)txgbe_dev_l2_tunnel_filter_add(dev, &l2_tn_conf, TRUE);
5019         }
5020 }
5021
5022 /* restore rss filter */
5023 static inline void
5024 txgbe_rss_filter_restore(struct rte_eth_dev *dev)
5025 {
5026         struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(dev);
5027
5028         if (filter_info->rss_info.conf.queue_num)
5029                 txgbe_config_rss_filter(dev,
5030                         &filter_info->rss_info, TRUE);
5031 }
5032
5033 static int
5034 txgbe_filter_restore(struct rte_eth_dev *dev)
5035 {
5036         txgbe_ntuple_filter_restore(dev);
5037         txgbe_ethertype_filter_restore(dev);
5038         txgbe_syn_filter_restore(dev);
5039         txgbe_fdir_filter_restore(dev);
5040         txgbe_l2_tn_filter_restore(dev);
5041         txgbe_rss_filter_restore(dev);
5042
5043         return 0;
5044 }
5045
5046 static void
5047 txgbe_l2_tunnel_conf(struct rte_eth_dev *dev)
5048 {
5049         struct txgbe_l2_tn_info *l2_tn_info = TXGBE_DEV_L2_TN(dev);
5050         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
5051
5052         if (l2_tn_info->e_tag_en)
5053                 (void)txgbe_e_tag_enable(hw);
5054
5055         if (l2_tn_info->e_tag_fwd_en)
5056                 (void)txgbe_e_tag_forwarding_en_dis(dev, 1);
5057
5058         (void)txgbe_update_e_tag_eth_type(hw, l2_tn_info->e_tag_ether_type);
5059 }
5060
5061 /* remove all the n-tuple filters */
5062 void
5063 txgbe_clear_all_ntuple_filter(struct rte_eth_dev *dev)
5064 {
5065         struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(dev);
5066         struct txgbe_5tuple_filter *p_5tuple;
5067
5068         while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list)))
5069                 txgbe_remove_5tuple_filter(dev, p_5tuple);
5070 }
5071
5072 /* remove all the ether type filters */
5073 void
5074 txgbe_clear_all_ethertype_filter(struct rte_eth_dev *dev)
5075 {
5076         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
5077         struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(dev);
5078         int i;
5079
5080         for (i = 0; i < TXGBE_ETF_ID_MAX; i++) {
5081                 if (filter_info->ethertype_mask & (1 << i) &&
5082                     !filter_info->ethertype_filters[i].conf) {
5083                         (void)txgbe_ethertype_filter_remove(filter_info,
5084                                                             (uint8_t)i);
5085                         wr32(hw, TXGBE_ETFLT(i), 0);
5086                         wr32(hw, TXGBE_ETCLS(i), 0);
5087                         txgbe_flush(hw);
5088                 }
5089         }
5090 }
5091
5092 /* remove the SYN filter */
5093 void
5094 txgbe_clear_syn_filter(struct rte_eth_dev *dev)
5095 {
5096         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
5097         struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(dev);
5098
5099         if (filter_info->syn_info & TXGBE_SYNCLS_ENA) {
5100                 filter_info->syn_info = 0;
5101
5102                 wr32(hw, TXGBE_SYNCLS, 0);
5103                 txgbe_flush(hw);
5104         }
5105 }
5106
5107 /* remove all the L2 tunnel filters */
5108 int
5109 txgbe_clear_all_l2_tn_filter(struct rte_eth_dev *dev)
5110 {
5111         struct txgbe_l2_tn_info *l2_tn_info = TXGBE_DEV_L2_TN(dev);
5112         struct txgbe_l2_tn_filter *l2_tn_filter;
5113         struct txgbe_l2_tunnel_conf l2_tn_conf;
5114         int ret = 0;
5115
5116         while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
5117                 l2_tn_conf.l2_tunnel_type = l2_tn_filter->key.l2_tn_type;
5118                 l2_tn_conf.tunnel_id      = l2_tn_filter->key.tn_id;
5119                 l2_tn_conf.pool           = l2_tn_filter->pool;
5120                 ret = txgbe_dev_l2_tunnel_filter_del(dev, &l2_tn_conf);
5121                 if (ret < 0)
5122                         return ret;
5123         }
5124
5125         return 0;
5126 }
5127
5128 static const struct eth_dev_ops txgbe_eth_dev_ops = {
5129         .dev_configure              = txgbe_dev_configure,
5130         .dev_infos_get              = txgbe_dev_info_get,
5131         .dev_start                  = txgbe_dev_start,
5132         .dev_stop                   = txgbe_dev_stop,
5133         .dev_set_link_up            = txgbe_dev_set_link_up,
5134         .dev_set_link_down          = txgbe_dev_set_link_down,
5135         .dev_close                  = txgbe_dev_close,
5136         .dev_reset                  = txgbe_dev_reset,
5137         .promiscuous_enable         = txgbe_dev_promiscuous_enable,
5138         .promiscuous_disable        = txgbe_dev_promiscuous_disable,
5139         .allmulticast_enable        = txgbe_dev_allmulticast_enable,
5140         .allmulticast_disable       = txgbe_dev_allmulticast_disable,
5141         .link_update                = txgbe_dev_link_update,
5142         .stats_get                  = txgbe_dev_stats_get,
5143         .xstats_get                 = txgbe_dev_xstats_get,
5144         .xstats_get_by_id           = txgbe_dev_xstats_get_by_id,
5145         .stats_reset                = txgbe_dev_stats_reset,
5146         .xstats_reset               = txgbe_dev_xstats_reset,
5147         .xstats_get_names           = txgbe_dev_xstats_get_names,
5148         .xstats_get_names_by_id     = txgbe_dev_xstats_get_names_by_id,
5149         .queue_stats_mapping_set    = txgbe_dev_queue_stats_mapping_set,
5150         .fw_version_get             = txgbe_fw_version_get,
5151         .dev_supported_ptypes_get   = txgbe_dev_supported_ptypes_get,
5152         .mtu_set                    = txgbe_dev_mtu_set,
5153         .vlan_filter_set            = txgbe_vlan_filter_set,
5154         .vlan_tpid_set              = txgbe_vlan_tpid_set,
5155         .vlan_offload_set           = txgbe_vlan_offload_set,
5156         .vlan_strip_queue_set       = txgbe_vlan_strip_queue_set,
5157         .rx_queue_start             = txgbe_dev_rx_queue_start,
5158         .rx_queue_stop              = txgbe_dev_rx_queue_stop,
5159         .tx_queue_start             = txgbe_dev_tx_queue_start,
5160         .tx_queue_stop              = txgbe_dev_tx_queue_stop,
5161         .rx_queue_setup             = txgbe_dev_rx_queue_setup,
5162         .rx_queue_intr_enable       = txgbe_dev_rx_queue_intr_enable,
5163         .rx_queue_intr_disable      = txgbe_dev_rx_queue_intr_disable,
5164         .rx_queue_release           = txgbe_dev_rx_queue_release,
5165         .tx_queue_setup             = txgbe_dev_tx_queue_setup,
5166         .tx_queue_release           = txgbe_dev_tx_queue_release,
5167         .dev_led_on                 = txgbe_dev_led_on,
5168         .dev_led_off                = txgbe_dev_led_off,
5169         .flow_ctrl_get              = txgbe_flow_ctrl_get,
5170         .flow_ctrl_set              = txgbe_flow_ctrl_set,
5171         .priority_flow_ctrl_set     = txgbe_priority_flow_ctrl_set,
5172         .mac_addr_add               = txgbe_add_rar,
5173         .mac_addr_remove            = txgbe_remove_rar,
5174         .mac_addr_set               = txgbe_set_default_mac_addr,
5175         .uc_hash_table_set          = txgbe_uc_hash_table_set,
5176         .uc_all_hash_table_set      = txgbe_uc_all_hash_table_set,
5177         .set_queue_rate_limit       = txgbe_set_queue_rate_limit,
5178         .reta_update                = txgbe_dev_rss_reta_update,
5179         .reta_query                 = txgbe_dev_rss_reta_query,
5180         .rss_hash_update            = txgbe_dev_rss_hash_update,
5181         .rss_hash_conf_get          = txgbe_dev_rss_hash_conf_get,
5182         .filter_ctrl                = txgbe_dev_filter_ctrl,
5183         .set_mc_addr_list           = txgbe_dev_set_mc_addr_list,
5184         .rxq_info_get               = txgbe_rxq_info_get,
5185         .txq_info_get               = txgbe_txq_info_get,
5186         .timesync_enable            = txgbe_timesync_enable,
5187         .timesync_disable           = txgbe_timesync_disable,
5188         .timesync_read_rx_timestamp = txgbe_timesync_read_rx_timestamp,
5189         .timesync_read_tx_timestamp = txgbe_timesync_read_tx_timestamp,
5190         .get_reg                    = txgbe_get_regs,
5191         .get_eeprom_length          = txgbe_get_eeprom_length,
5192         .get_eeprom                 = txgbe_get_eeprom,
5193         .set_eeprom                 = txgbe_set_eeprom,
5194         .get_module_info            = txgbe_get_module_info,
5195         .get_module_eeprom          = txgbe_get_module_eeprom,
5196         .get_dcb_info               = txgbe_dev_get_dcb_info,
5197         .timesync_adjust_time       = txgbe_timesync_adjust_time,
5198         .timesync_read_time         = txgbe_timesync_read_time,
5199         .timesync_write_time        = txgbe_timesync_write_time,
5200         .udp_tunnel_port_add        = txgbe_dev_udp_tunnel_port_add,
5201         .udp_tunnel_port_del        = txgbe_dev_udp_tunnel_port_del,
5202         .tx_done_cleanup            = txgbe_dev_tx_done_cleanup,
5203 };
5204
5205 RTE_PMD_REGISTER_PCI(net_txgbe, rte_txgbe_pmd);
5206 RTE_PMD_REGISTER_PCI_TABLE(net_txgbe, pci_id_txgbe_map);
5207 RTE_PMD_REGISTER_KMOD_DEP(net_txgbe, "* igb_uio | uio_pci_generic | vfio-pci");
5208
5209 RTE_LOG_REGISTER(txgbe_logtype_init, pmd.net.txgbe.init, NOTICE);
5210 RTE_LOG_REGISTER(txgbe_logtype_driver, pmd.net.txgbe.driver, NOTICE);
5211
5212 #ifdef RTE_LIBRTE_TXGBE_DEBUG_RX
5213         RTE_LOG_REGISTER(txgbe_logtype_rx, pmd.net.txgbe.rx, DEBUG);
5214 #endif
5215 #ifdef RTE_LIBRTE_TXGBE_DEBUG_TX
5216         RTE_LOG_REGISTER(txgbe_logtype_tx, pmd.net.txgbe.tx, DEBUG);
5217 #endif
5218
5219 #ifdef RTE_LIBRTE_TXGBE_DEBUG_TX_FREE
5220         RTE_LOG_REGISTER(txgbe_logtype_tx_free, pmd.net.txgbe.tx_free, DEBUG);
5221 #endif