1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2015-2020
9 #include <rte_common.h>
10 #include <rte_ethdev_pci.h>
12 #include <rte_interrupts.h>
14 #include <rte_debug.h>
16 #include <rte_memory.h>
18 #include <rte_alarm.h>
20 #include "txgbe_logs.h"
21 #include "base/txgbe.h"
22 #include "txgbe_ethdev.h"
23 #include "txgbe_rxtx.h"
25 static int txgbe_dev_set_link_up(struct rte_eth_dev *dev);
26 static int txgbe_dev_set_link_down(struct rte_eth_dev *dev);
27 static int txgbe_dev_close(struct rte_eth_dev *dev);
28 static int txgbe_dev_link_update(struct rte_eth_dev *dev,
29 int wait_to_complete);
31 static void txgbe_dev_link_status_print(struct rte_eth_dev *dev);
32 static int txgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on);
33 static int txgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev);
34 static int txgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
35 static int txgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
36 static int txgbe_dev_interrupt_action(struct rte_eth_dev *dev,
37 struct rte_intr_handle *handle);
38 static void txgbe_dev_interrupt_handler(void *param);
39 static void txgbe_dev_interrupt_delayed_handler(void *param);
40 static void txgbe_configure_msix(struct rte_eth_dev *dev);
43 * The set of PCI devices this driver supports
45 static const struct rte_pci_id pci_id_txgbe_map[] = {
46 { RTE_PCI_DEVICE(PCI_VENDOR_ID_WANGXUN, TXGBE_DEV_ID_RAPTOR_SFP) },
47 { RTE_PCI_DEVICE(PCI_VENDOR_ID_WANGXUN, TXGBE_DEV_ID_WX1820_SFP) },
48 { .vendor_id = 0, /* sentinel */ },
51 static const struct rte_eth_desc_lim rx_desc_lim = {
52 .nb_max = TXGBE_RING_DESC_MAX,
53 .nb_min = TXGBE_RING_DESC_MIN,
54 .nb_align = TXGBE_RXD_ALIGN,
57 static const struct rte_eth_desc_lim tx_desc_lim = {
58 .nb_max = TXGBE_RING_DESC_MAX,
59 .nb_min = TXGBE_RING_DESC_MIN,
60 .nb_align = TXGBE_TXD_ALIGN,
61 .nb_seg_max = TXGBE_TX_MAX_SEG,
62 .nb_mtu_seg_max = TXGBE_TX_MAX_SEG,
65 static const struct eth_dev_ops txgbe_eth_dev_ops;
68 txgbe_is_sfp(struct txgbe_hw *hw)
70 switch (hw->phy.type) {
71 case txgbe_phy_sfp_avago:
72 case txgbe_phy_sfp_ftl:
73 case txgbe_phy_sfp_intel:
74 case txgbe_phy_sfp_unknown:
75 case txgbe_phy_sfp_tyco_passive:
76 case txgbe_phy_sfp_unknown_passive:
84 txgbe_enable_intr(struct rte_eth_dev *dev)
86 struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);
87 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
89 wr32(hw, TXGBE_IENMISC, intr->mask_misc);
90 wr32(hw, TXGBE_IMC(0), TXGBE_IMC_MASK);
91 wr32(hw, TXGBE_IMC(1), TXGBE_IMC_MASK);
96 txgbe_disable_intr(struct txgbe_hw *hw)
98 PMD_INIT_FUNC_TRACE();
100 wr32(hw, TXGBE_IENMISC, ~BIT_MASK32);
101 wr32(hw, TXGBE_IMS(0), TXGBE_IMC_MASK);
102 wr32(hw, TXGBE_IMS(1), TXGBE_IMC_MASK);
107 eth_txgbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params __rte_unused)
109 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
110 struct txgbe_hw *hw = TXGBE_DEV_HW(eth_dev);
111 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
112 const struct rte_memzone *mz;
116 PMD_INIT_FUNC_TRACE();
118 eth_dev->dev_ops = &txgbe_eth_dev_ops;
120 rte_eth_copy_pci_info(eth_dev, pci_dev);
122 /* Vendor and Device ID need to be set before init of shared code */
123 hw->device_id = pci_dev->id.device_id;
124 hw->vendor_id = pci_dev->id.vendor_id;
125 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
126 hw->allow_unsupported_sfp = 1;
128 /* Reserve memory for interrupt status block */
129 mz = rte_eth_dma_zone_reserve(eth_dev, "txgbe_driver", -1,
130 16, TXGBE_ALIGN, SOCKET_ID_ANY);
134 hw->isb_dma = TMZ_PADDR(mz);
135 hw->isb_mem = TMZ_VADDR(mz);
137 /* Initialize the shared code (base driver) */
138 err = txgbe_init_shared_code(hw);
140 PMD_INIT_LOG(ERR, "Shared code init failed: %d", err);
144 err = hw->rom.init_params(hw);
146 PMD_INIT_LOG(ERR, "The EEPROM init failed: %d", err);
150 /* Make sure we have a good EEPROM before we read from it */
151 err = hw->rom.validate_checksum(hw, &csum);
153 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", err);
157 err = hw->mac.init_hw(hw);
160 * Devices with copper phys will fail to initialise if txgbe_init_hw()
161 * is called too soon after the kernel driver unbinding/binding occurs.
162 * The failure occurs in txgbe_identify_phy() for all devices,
163 * but for non-copper devies, txgbe_identify_sfp_module() is
164 * also called. See txgbe_identify_phy(). The reason for the
165 * failure is not known, and only occuts when virtualisation features
166 * are disabled in the bios. A delay of 200ms was found to be enough by
167 * trial-and-error, and is doubled to be safe.
169 if (err && hw->phy.media_type == txgbe_media_type_copper) {
171 err = hw->mac.init_hw(hw);
174 if (err == TXGBE_ERR_SFP_NOT_PRESENT)
177 if (err == TXGBE_ERR_EEPROM_VERSION) {
178 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
179 "LOM. Please be aware there may be issues associated "
180 "with your hardware.");
181 PMD_INIT_LOG(ERR, "If you are experiencing problems "
182 "please contact your hardware representative "
183 "who provided you with this hardware.");
184 } else if (err == TXGBE_ERR_SFP_NOT_SUPPORTED) {
185 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
188 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", err);
192 /* disable interrupt */
193 txgbe_disable_intr(hw);
195 /* Allocate memory for storing MAC addresses */
196 eth_dev->data->mac_addrs = rte_zmalloc("txgbe", RTE_ETHER_ADDR_LEN *
197 hw->mac.num_rar_entries, 0);
198 if (eth_dev->data->mac_addrs == NULL) {
200 "Failed to allocate %u bytes needed to store "
202 RTE_ETHER_ADDR_LEN * hw->mac.num_rar_entries);
206 /* Copy the permanent MAC address */
207 rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.perm_addr,
208 ð_dev->data->mac_addrs[0]);
210 /* Allocate memory for storing hash filter MAC addresses */
211 eth_dev->data->hash_mac_addrs = rte_zmalloc("txgbe",
212 RTE_ETHER_ADDR_LEN * TXGBE_VMDQ_NUM_UC_MAC, 0);
213 if (eth_dev->data->hash_mac_addrs == NULL) {
215 "Failed to allocate %d bytes needed to store MAC addresses",
216 RTE_ETHER_ADDR_LEN * TXGBE_VMDQ_NUM_UC_MAC);
220 if (txgbe_is_sfp(hw) && hw->phy.sfp_type != txgbe_sfp_type_not_present)
221 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
222 (int)hw->mac.type, (int)hw->phy.type,
223 (int)hw->phy.sfp_type);
225 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
226 (int)hw->mac.type, (int)hw->phy.type);
228 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
229 eth_dev->data->port_id, pci_dev->id.vendor_id,
230 pci_dev->id.device_id);
232 rte_intr_callback_register(intr_handle,
233 txgbe_dev_interrupt_handler, eth_dev);
235 /* enable uio/vfio intr/eventfd mapping */
236 rte_intr_enable(intr_handle);
238 /* enable support intr */
239 txgbe_enable_intr(eth_dev);
245 eth_txgbe_dev_uninit(struct rte_eth_dev *eth_dev)
247 PMD_INIT_FUNC_TRACE();
249 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
252 txgbe_dev_close(eth_dev);
258 eth_txgbe_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
259 struct rte_pci_device *pci_dev)
261 struct rte_eth_dev *pf_ethdev;
262 struct rte_eth_devargs eth_da;
265 if (pci_dev->device.devargs) {
266 retval = rte_eth_devargs_parse(pci_dev->device.devargs->args,
271 memset(ð_da, 0, sizeof(eth_da));
274 retval = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
275 sizeof(struct txgbe_adapter),
276 eth_dev_pci_specific_init, pci_dev,
277 eth_txgbe_dev_init, NULL);
279 if (retval || eth_da.nb_representor_ports < 1)
282 pf_ethdev = rte_eth_dev_allocated(pci_dev->device.name);
283 if (pf_ethdev == NULL)
289 static int eth_txgbe_pci_remove(struct rte_pci_device *pci_dev)
291 struct rte_eth_dev *ethdev;
293 ethdev = rte_eth_dev_allocated(pci_dev->device.name);
297 return rte_eth_dev_destroy(ethdev, eth_txgbe_dev_uninit);
300 static struct rte_pci_driver rte_txgbe_pmd = {
301 .id_table = pci_id_txgbe_map,
302 .drv_flags = RTE_PCI_DRV_NEED_MAPPING |
303 RTE_PCI_DRV_INTR_LSC,
304 .probe = eth_txgbe_pci_probe,
305 .remove = eth_txgbe_pci_remove,
309 txgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q)
311 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
316 RTE_ETH_DEV_SRIOV(dev).active = ETH_64_POOLS;
319 RTE_ETH_DEV_SRIOV(dev).active = ETH_32_POOLS;
325 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool =
326 TXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
327 RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx =
328 pci_dev->max_vfs * RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
333 txgbe_check_mq_mode(struct rte_eth_dev *dev)
335 struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
336 uint16_t nb_rx_q = dev->data->nb_rx_queues;
337 uint16_t nb_tx_q = dev->data->nb_tx_queues;
339 if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
340 /* check multi-queue mode */
341 switch (dev_conf->rxmode.mq_mode) {
342 case ETH_MQ_RX_VMDQ_DCB:
343 PMD_INIT_LOG(INFO, "ETH_MQ_RX_VMDQ_DCB mode supported in SRIOV");
345 case ETH_MQ_RX_VMDQ_DCB_RSS:
346 /* DCB/RSS VMDQ in SRIOV mode, not implement yet */
347 PMD_INIT_LOG(ERR, "SRIOV active,"
348 " unsupported mq_mode rx %d.",
349 dev_conf->rxmode.mq_mode);
352 case ETH_MQ_RX_VMDQ_RSS:
353 dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_RSS;
354 if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)
355 if (txgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) {
356 PMD_INIT_LOG(ERR, "SRIOV is active,"
357 " invalid queue number"
358 " for VMDQ RSS, allowed"
359 " value are 1, 2 or 4.");
363 case ETH_MQ_RX_VMDQ_ONLY:
365 /* if nothing mq mode configure, use default scheme */
366 dev->data->dev_conf.rxmode.mq_mode =
369 default: /* ETH_MQ_RX_DCB, ETH_MQ_RX_DCB_RSS or ETH_MQ_TX_DCB*/
370 /* SRIOV only works in VMDq enable mode */
371 PMD_INIT_LOG(ERR, "SRIOV is active,"
372 " wrong mq_mode rx %d.",
373 dev_conf->rxmode.mq_mode);
377 switch (dev_conf->txmode.mq_mode) {
378 case ETH_MQ_TX_VMDQ_DCB:
379 PMD_INIT_LOG(INFO, "ETH_MQ_TX_VMDQ_DCB mode supported in SRIOV");
380 dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_DCB;
382 default: /* ETH_MQ_TX_VMDQ_ONLY or ETH_MQ_TX_NONE */
383 dev->data->dev_conf.txmode.mq_mode =
388 /* check valid queue number */
389 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) ||
390 (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) {
391 PMD_INIT_LOG(ERR, "SRIOV is active,"
392 " nb_rx_q=%d nb_tx_q=%d queue number"
393 " must be less than or equal to %d.",
395 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool);
399 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
400 PMD_INIT_LOG(ERR, "VMDQ+DCB+RSS mq_mode is"
404 /* check configuration for vmdb+dcb mode */
405 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB) {
406 const struct rte_eth_vmdq_dcb_conf *conf;
408 if (nb_rx_q != TXGBE_VMDQ_DCB_NB_QUEUES) {
409 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.",
410 TXGBE_VMDQ_DCB_NB_QUEUES);
413 conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf;
414 if (!(conf->nb_queue_pools == ETH_16_POOLS ||
415 conf->nb_queue_pools == ETH_32_POOLS)) {
416 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
417 " nb_queue_pools must be %d or %d.",
418 ETH_16_POOLS, ETH_32_POOLS);
422 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) {
423 const struct rte_eth_vmdq_dcb_tx_conf *conf;
425 if (nb_tx_q != TXGBE_VMDQ_DCB_NB_QUEUES) {
426 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d",
427 TXGBE_VMDQ_DCB_NB_QUEUES);
430 conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf;
431 if (!(conf->nb_queue_pools == ETH_16_POOLS ||
432 conf->nb_queue_pools == ETH_32_POOLS)) {
433 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
434 " nb_queue_pools != %d and"
435 " nb_queue_pools != %d.",
436 ETH_16_POOLS, ETH_32_POOLS);
441 /* For DCB mode check our configuration before we go further */
442 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_DCB) {
443 const struct rte_eth_dcb_rx_conf *conf;
445 conf = &dev_conf->rx_adv_conf.dcb_rx_conf;
446 if (!(conf->nb_tcs == ETH_4_TCS ||
447 conf->nb_tcs == ETH_8_TCS)) {
448 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
449 " and nb_tcs != %d.",
450 ETH_4_TCS, ETH_8_TCS);
455 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_DCB) {
456 const struct rte_eth_dcb_tx_conf *conf;
458 conf = &dev_conf->tx_adv_conf.dcb_tx_conf;
459 if (!(conf->nb_tcs == ETH_4_TCS ||
460 conf->nb_tcs == ETH_8_TCS)) {
461 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
462 " and nb_tcs != %d.",
463 ETH_4_TCS, ETH_8_TCS);
472 txgbe_dev_configure(struct rte_eth_dev *dev)
474 struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);
475 struct txgbe_adapter *adapter = TXGBE_DEV_ADAPTER(dev);
478 PMD_INIT_FUNC_TRACE();
480 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
481 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
483 /* multiple queue mode checking */
484 ret = txgbe_check_mq_mode(dev);
486 PMD_DRV_LOG(ERR, "txgbe_check_mq_mode fails with %d.",
491 /* set flag to update link status after init */
492 intr->flags |= TXGBE_FLAG_NEED_LINK_UPDATE;
495 * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
496 * allocation Rx preconditions we will reset it.
498 adapter->rx_bulk_alloc_allowed = true;
504 txgbe_dev_phy_intr_setup(struct rte_eth_dev *dev)
506 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
507 struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);
510 gpie = rd32(hw, TXGBE_GPIOINTEN);
511 gpie |= TXGBE_GPIOBIT_6;
512 wr32(hw, TXGBE_GPIOINTEN, gpie);
513 intr->mask_misc |= TXGBE_ICRMISC_GPIO;
517 * Set device link up: enable tx.
520 txgbe_dev_set_link_up(struct rte_eth_dev *dev)
522 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
524 if (hw->phy.media_type == txgbe_media_type_copper) {
525 /* Turn on the copper */
526 hw->phy.set_phy_power(hw, true);
528 /* Turn on the laser */
529 hw->mac.enable_tx_laser(hw);
530 txgbe_dev_link_update(dev, 0);
537 * Set device link down: disable tx.
540 txgbe_dev_set_link_down(struct rte_eth_dev *dev)
542 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
544 if (hw->phy.media_type == txgbe_media_type_copper) {
545 /* Turn off the copper */
546 hw->phy.set_phy_power(hw, false);
548 /* Turn off the laser */
549 hw->mac.disable_tx_laser(hw);
550 txgbe_dev_link_update(dev, 0);
557 * Reset and stop device.
560 txgbe_dev_close(struct rte_eth_dev *dev)
562 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
563 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
567 PMD_INIT_FUNC_TRACE();
569 /* disable uio intr before callback unregister */
570 rte_intr_disable(intr_handle);
573 ret = rte_intr_callback_unregister(intr_handle,
574 txgbe_dev_interrupt_handler, dev);
575 if (ret >= 0 || ret == -ENOENT) {
577 } else if (ret != -EAGAIN) {
579 "intr callback unregister failed: %d",
583 } while (retries++ < (10 + TXGBE_LINK_UP_TIME));
585 /* cancel the delay handler before remove dev */
586 rte_eal_alarm_cancel(txgbe_dev_interrupt_delayed_handler, dev);
588 rte_free(dev->data->mac_addrs);
589 dev->data->mac_addrs = NULL;
591 rte_free(dev->data->hash_mac_addrs);
592 dev->data->hash_mac_addrs = NULL;
598 txgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
600 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
601 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
603 dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
604 dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
605 dev_info->min_rx_bufsize = 1024;
606 dev_info->max_rx_pktlen = 15872;
607 dev_info->max_mac_addrs = hw->mac.num_rar_entries;
608 dev_info->max_hash_mac_addrs = TXGBE_VMDQ_NUM_UC_MAC;
609 dev_info->max_vfs = pci_dev->max_vfs;
610 dev_info->max_vmdq_pools = ETH_64_POOLS;
611 dev_info->vmdq_queue_num = dev_info->max_rx_queues;
612 dev_info->rx_queue_offload_capa = txgbe_get_rx_queue_offloads(dev);
613 dev_info->rx_offload_capa = (txgbe_get_rx_port_offloads(dev) |
614 dev_info->rx_queue_offload_capa);
615 dev_info->tx_queue_offload_capa = txgbe_get_tx_queue_offloads(dev);
616 dev_info->tx_offload_capa = txgbe_get_tx_port_offloads(dev);
618 dev_info->default_rxconf = (struct rte_eth_rxconf) {
620 .pthresh = TXGBE_DEFAULT_RX_PTHRESH,
621 .hthresh = TXGBE_DEFAULT_RX_HTHRESH,
622 .wthresh = TXGBE_DEFAULT_RX_WTHRESH,
624 .rx_free_thresh = TXGBE_DEFAULT_RX_FREE_THRESH,
629 dev_info->default_txconf = (struct rte_eth_txconf) {
631 .pthresh = TXGBE_DEFAULT_TX_PTHRESH,
632 .hthresh = TXGBE_DEFAULT_TX_HTHRESH,
633 .wthresh = TXGBE_DEFAULT_TX_WTHRESH,
635 .tx_free_thresh = TXGBE_DEFAULT_TX_FREE_THRESH,
639 dev_info->rx_desc_lim = rx_desc_lim;
640 dev_info->tx_desc_lim = tx_desc_lim;
642 dev_info->hash_key_size = TXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
643 dev_info->reta_size = ETH_RSS_RETA_SIZE_128;
644 dev_info->flow_type_rss_offloads = TXGBE_RSS_OFFLOAD_ALL;
646 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
647 dev_info->speed_capa |= ETH_LINK_SPEED_100M;
649 /* Driver-preferred Rx/Tx parameters */
650 dev_info->default_rxportconf.burst_size = 32;
651 dev_info->default_txportconf.burst_size = 32;
652 dev_info->default_rxportconf.nb_queues = 1;
653 dev_info->default_txportconf.nb_queues = 1;
654 dev_info->default_rxportconf.ring_size = 256;
655 dev_info->default_txportconf.ring_size = 256;
661 txgbe_dev_setup_link_alarm_handler(void *param)
663 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
664 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
665 struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);
667 bool autoneg = false;
669 speed = hw->phy.autoneg_advertised;
671 hw->mac.get_link_capabilities(hw, &speed, &autoneg);
673 hw->mac.setup_link(hw, speed, true);
675 intr->flags &= ~TXGBE_FLAG_NEED_LINK_CONFIG;
678 /* return 0 means link status changed, -1 means not changed */
680 txgbe_dev_link_update_share(struct rte_eth_dev *dev,
681 int wait_to_complete)
683 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
684 struct rte_eth_link link;
685 u32 link_speed = TXGBE_LINK_SPEED_UNKNOWN;
686 struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);
691 memset(&link, 0, sizeof(link));
692 link.link_status = ETH_LINK_DOWN;
693 link.link_speed = ETH_SPEED_NUM_NONE;
694 link.link_duplex = ETH_LINK_HALF_DUPLEX;
695 link.link_autoneg = ETH_LINK_AUTONEG;
697 hw->mac.get_link_status = true;
699 if (intr->flags & TXGBE_FLAG_NEED_LINK_CONFIG)
700 return rte_eth_linkstatus_set(dev, &link);
702 /* check if it needs to wait to complete, if lsc interrupt is enabled */
703 if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
706 err = hw->mac.check_link(hw, &link_speed, &link_up, wait);
709 link.link_speed = ETH_SPEED_NUM_100M;
710 link.link_duplex = ETH_LINK_FULL_DUPLEX;
711 return rte_eth_linkstatus_set(dev, &link);
715 if (hw->phy.media_type == txgbe_media_type_fiber) {
716 intr->flags |= TXGBE_FLAG_NEED_LINK_CONFIG;
717 rte_eal_alarm_set(10,
718 txgbe_dev_setup_link_alarm_handler, dev);
720 return rte_eth_linkstatus_set(dev, &link);
723 intr->flags &= ~TXGBE_FLAG_NEED_LINK_CONFIG;
724 link.link_status = ETH_LINK_UP;
725 link.link_duplex = ETH_LINK_FULL_DUPLEX;
727 switch (link_speed) {
729 case TXGBE_LINK_SPEED_UNKNOWN:
730 link.link_duplex = ETH_LINK_FULL_DUPLEX;
731 link.link_speed = ETH_SPEED_NUM_100M;
734 case TXGBE_LINK_SPEED_100M_FULL:
735 link.link_speed = ETH_SPEED_NUM_100M;
738 case TXGBE_LINK_SPEED_1GB_FULL:
739 link.link_speed = ETH_SPEED_NUM_1G;
742 case TXGBE_LINK_SPEED_2_5GB_FULL:
743 link.link_speed = ETH_SPEED_NUM_2_5G;
746 case TXGBE_LINK_SPEED_5GB_FULL:
747 link.link_speed = ETH_SPEED_NUM_5G;
750 case TXGBE_LINK_SPEED_10GB_FULL:
751 link.link_speed = ETH_SPEED_NUM_10G;
755 return rte_eth_linkstatus_set(dev, &link);
759 txgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
761 return txgbe_dev_link_update_share(dev, wait_to_complete);
765 * It clears the interrupt causes and enables the interrupt.
766 * It will be called once only during nic initialized.
769 * Pointer to struct rte_eth_dev.
774 * - On success, zero.
775 * - On failure, a negative value.
778 txgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on)
780 struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);
782 txgbe_dev_link_status_print(dev);
784 intr->mask_misc |= TXGBE_ICRMISC_LSC;
786 intr->mask_misc &= ~TXGBE_ICRMISC_LSC;
792 * It clears the interrupt causes and enables the interrupt.
793 * It will be called once only during nic initialized.
796 * Pointer to struct rte_eth_dev.
799 * - On success, zero.
800 * - On failure, a negative value.
803 txgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
805 struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);
807 intr->mask[0] |= TXGBE_ICR_MASK;
808 intr->mask[1] |= TXGBE_ICR_MASK;
814 * It clears the interrupt causes and enables the interrupt.
815 * It will be called once only during nic initialized.
818 * Pointer to struct rte_eth_dev.
821 * - On success, zero.
822 * - On failure, a negative value.
825 txgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev)
827 struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);
829 intr->mask_misc |= TXGBE_ICRMISC_LNKSEC;
835 * It reads ICR and sets flag (TXGBE_ICRMISC_LSC) for the link_update.
838 * Pointer to struct rte_eth_dev.
841 * - On success, zero.
842 * - On failure, a negative value.
845 txgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
848 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
849 struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);
851 /* clear all cause mask */
852 txgbe_disable_intr(hw);
854 /* read-on-clear nic registers here */
855 eicr = ((u32 *)hw->isb_mem)[TXGBE_ISB_MISC];
856 PMD_DRV_LOG(DEBUG, "eicr %x", eicr);
860 /* set flag for async link update */
861 if (eicr & TXGBE_ICRMISC_LSC)
862 intr->flags |= TXGBE_FLAG_NEED_LINK_UPDATE;
864 if (eicr & TXGBE_ICRMISC_VFMBX)
865 intr->flags |= TXGBE_FLAG_MAILBOX;
867 if (eicr & TXGBE_ICRMISC_LNKSEC)
868 intr->flags |= TXGBE_FLAG_MACSEC;
870 if (eicr & TXGBE_ICRMISC_GPIO)
871 intr->flags |= TXGBE_FLAG_PHY_INTERRUPT;
877 * It gets and then prints the link status.
880 * Pointer to struct rte_eth_dev.
883 * - On success, zero.
884 * - On failure, a negative value.
887 txgbe_dev_link_status_print(struct rte_eth_dev *dev)
889 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
890 struct rte_eth_link link;
892 rte_eth_linkstatus_get(dev, &link);
894 if (link.link_status) {
895 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
896 (int)(dev->data->port_id),
897 (unsigned int)link.link_speed,
898 link.link_duplex == ETH_LINK_FULL_DUPLEX ?
899 "full-duplex" : "half-duplex");
901 PMD_INIT_LOG(INFO, " Port %d: Link Down",
902 (int)(dev->data->port_id));
904 PMD_INIT_LOG(DEBUG, "PCI Address: " PCI_PRI_FMT,
905 pci_dev->addr.domain,
908 pci_dev->addr.function);
912 * It executes link_update after knowing an interrupt occurred.
915 * Pointer to struct rte_eth_dev.
918 * - On success, zero.
919 * - On failure, a negative value.
922 txgbe_dev_interrupt_action(struct rte_eth_dev *dev,
923 struct rte_intr_handle *intr_handle)
925 struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);
927 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
929 PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
931 if (intr->flags & TXGBE_FLAG_MAILBOX)
932 intr->flags &= ~TXGBE_FLAG_MAILBOX;
934 if (intr->flags & TXGBE_FLAG_PHY_INTERRUPT) {
935 hw->phy.handle_lasi(hw);
936 intr->flags &= ~TXGBE_FLAG_PHY_INTERRUPT;
939 if (intr->flags & TXGBE_FLAG_NEED_LINK_UPDATE) {
940 struct rte_eth_link link;
942 /*get the link status before link update, for predicting later*/
943 rte_eth_linkstatus_get(dev, &link);
945 txgbe_dev_link_update(dev, 0);
948 if (!link.link_status)
949 /* handle it 1 sec later, wait it being stable */
950 timeout = TXGBE_LINK_UP_CHECK_TIMEOUT;
953 /* handle it 4 sec later, wait it being stable */
954 timeout = TXGBE_LINK_DOWN_CHECK_TIMEOUT;
956 txgbe_dev_link_status_print(dev);
957 if (rte_eal_alarm_set(timeout * 1000,
958 txgbe_dev_interrupt_delayed_handler,
960 PMD_DRV_LOG(ERR, "Error setting alarm");
962 /* remember original mask */
963 intr->mask_misc_orig = intr->mask_misc;
964 /* only disable lsc interrupt */
965 intr->mask_misc &= ~TXGBE_ICRMISC_LSC;
969 PMD_DRV_LOG(DEBUG, "enable intr immediately");
970 txgbe_enable_intr(dev);
971 rte_intr_enable(intr_handle);
977 * Interrupt handler which shall be registered for alarm callback for delayed
978 * handling specific interrupt to wait for the stable nic state. As the
979 * NIC interrupt state is not stable for txgbe after link is just down,
980 * it needs to wait 4 seconds to get the stable status.
983 * Pointer to interrupt handle.
985 * The address of parameter (struct rte_eth_dev *) registered before.
991 txgbe_dev_interrupt_delayed_handler(void *param)
993 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
994 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
995 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
996 struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);
997 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
1000 txgbe_disable_intr(hw);
1002 eicr = ((u32 *)hw->isb_mem)[TXGBE_ISB_MISC];
1004 if (intr->flags & TXGBE_FLAG_PHY_INTERRUPT) {
1005 hw->phy.handle_lasi(hw);
1006 intr->flags &= ~TXGBE_FLAG_PHY_INTERRUPT;
1009 if (intr->flags & TXGBE_FLAG_NEED_LINK_UPDATE) {
1010 txgbe_dev_link_update(dev, 0);
1011 intr->flags &= ~TXGBE_FLAG_NEED_LINK_UPDATE;
1012 txgbe_dev_link_status_print(dev);
1013 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC,
1017 if (intr->flags & TXGBE_FLAG_MACSEC) {
1018 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_MACSEC,
1020 intr->flags &= ~TXGBE_FLAG_MACSEC;
1023 /* restore original mask */
1024 intr->mask_misc = intr->mask_misc_orig;
1025 intr->mask_misc_orig = 0;
1027 PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
1028 txgbe_enable_intr(dev);
1029 rte_intr_enable(intr_handle);
1033 * Interrupt handler triggered by NIC for handling
1034 * specific interrupt.
1037 * Pointer to interrupt handle.
1039 * The address of parameter (struct rte_eth_dev *) registered before.
1045 txgbe_dev_interrupt_handler(void *param)
1047 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1049 txgbe_dev_interrupt_get_status(dev);
1050 txgbe_dev_interrupt_action(dev, dev->intr_handle);
1054 txgbe_add_rar(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
1055 uint32_t index, uint32_t pool)
1057 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
1058 uint32_t enable_addr = 1;
1060 return txgbe_set_rar(hw, index, mac_addr->addr_bytes,
1065 txgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
1067 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
1069 txgbe_clear_rar(hw, index);
1073 txgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *addr)
1075 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1077 txgbe_remove_rar(dev, 0);
1078 txgbe_add_rar(dev, addr, 0, pci_dev->max_vfs);
1084 * set the IVAR registers, mapping interrupt causes to vectors
1086 * pointer to txgbe_hw struct
1088 * 0 for Rx, 1 for Tx, -1 for other causes
1090 * queue to map the corresponding interrupt to
1092 * the vector to map to the corresponding queue
1095 txgbe_set_ivar_map(struct txgbe_hw *hw, int8_t direction,
1096 uint8_t queue, uint8_t msix_vector)
1100 if (direction == -1) {
1102 msix_vector |= TXGBE_IVARMISC_VLD;
1104 tmp = rd32(hw, TXGBE_IVARMISC);
1105 tmp &= ~(0xFF << idx);
1106 tmp |= (msix_vector << idx);
1107 wr32(hw, TXGBE_IVARMISC, tmp);
1109 /* rx or tx causes */
1110 /* Workround for ICR lost */
1111 idx = ((16 * (queue & 1)) + (8 * direction));
1112 tmp = rd32(hw, TXGBE_IVAR(queue >> 1));
1113 tmp &= ~(0xFF << idx);
1114 tmp |= (msix_vector << idx);
1115 wr32(hw, TXGBE_IVAR(queue >> 1), tmp);
1120 * Sets up the hardware to properly generate MSI-X interrupts
1122 * board private structure
1125 txgbe_configure_msix(struct rte_eth_dev *dev)
1127 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1128 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1129 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
1130 uint32_t queue_id, base = TXGBE_MISC_VEC_ID;
1131 uint32_t vec = TXGBE_MISC_VEC_ID;
1134 /* won't configure msix register if no mapping is done
1135 * between intr vector and event fd
1136 * but if misx has been enabled already, need to configure
1137 * auto clean, auto mask and throttling.
1139 gpie = rd32(hw, TXGBE_GPIE);
1140 if (!rte_intr_dp_is_en(intr_handle) &&
1141 !(gpie & TXGBE_GPIE_MSIX))
1144 if (rte_intr_allow_others(intr_handle)) {
1145 base = TXGBE_RX_VEC_START;
1149 /* setup GPIE for MSI-x mode */
1150 gpie = rd32(hw, TXGBE_GPIE);
1151 gpie |= TXGBE_GPIE_MSIX;
1152 wr32(hw, TXGBE_GPIE, gpie);
1154 /* Populate the IVAR table and set the ITR values to the
1155 * corresponding register.
1157 if (rte_intr_dp_is_en(intr_handle)) {
1158 for (queue_id = 0; queue_id < dev->data->nb_rx_queues;
1160 /* by default, 1:1 mapping */
1161 txgbe_set_ivar_map(hw, 0, queue_id, vec);
1162 intr_handle->intr_vec[queue_id] = vec;
1163 if (vec < base + intr_handle->nb_efd - 1)
1167 txgbe_set_ivar_map(hw, -1, 1, TXGBE_MISC_VEC_ID);
1169 wr32(hw, TXGBE_ITR(TXGBE_MISC_VEC_ID),
1170 TXGBE_ITR_IVAL_10G(TXGBE_QUEUE_ITR_INTERVAL_DEFAULT)
1175 txgbe_dev_addr_list_itr(__rte_unused struct txgbe_hw *hw,
1176 u8 **mc_addr_ptr, u32 *vmdq)
1181 mc_addr = *mc_addr_ptr;
1182 *mc_addr_ptr = (mc_addr + sizeof(struct rte_ether_addr));
1187 txgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
1188 struct rte_ether_addr *mc_addr_set,
1189 uint32_t nb_mc_addr)
1191 struct txgbe_hw *hw;
1194 hw = TXGBE_DEV_HW(dev);
1195 mc_addr_list = (u8 *)mc_addr_set;
1196 return txgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
1197 txgbe_dev_addr_list_itr, TRUE);
1200 static const struct eth_dev_ops txgbe_eth_dev_ops = {
1201 .dev_configure = txgbe_dev_configure,
1202 .dev_infos_get = txgbe_dev_info_get,
1203 .dev_set_link_up = txgbe_dev_set_link_up,
1204 .dev_set_link_down = txgbe_dev_set_link_down,
1205 .mac_addr_add = txgbe_add_rar,
1206 .mac_addr_remove = txgbe_remove_rar,
1207 .mac_addr_set = txgbe_set_default_mac_addr,
1208 .set_mc_addr_list = txgbe_dev_set_mc_addr_list,
1211 RTE_PMD_REGISTER_PCI(net_txgbe, rte_txgbe_pmd);
1212 RTE_PMD_REGISTER_PCI_TABLE(net_txgbe, pci_id_txgbe_map);
1213 RTE_PMD_REGISTER_KMOD_DEP(net_txgbe, "* igb_uio | uio_pci_generic | vfio-pci");
1215 RTE_LOG_REGISTER(txgbe_logtype_init, pmd.net.txgbe.init, NOTICE);
1216 RTE_LOG_REGISTER(txgbe_logtype_driver, pmd.net.txgbe.driver, NOTICE);
1218 #ifdef RTE_LIBRTE_TXGBE_DEBUG_RX
1219 RTE_LOG_REGISTER(txgbe_logtype_rx, pmd.net.txgbe.rx, DEBUG);
1221 #ifdef RTE_LIBRTE_TXGBE_DEBUG_TX
1222 RTE_LOG_REGISTER(txgbe_logtype_tx, pmd.net.txgbe.tx, DEBUG);
1225 #ifdef RTE_LIBRTE_TXGBE_DEBUG_TX_FREE
1226 RTE_LOG_REGISTER(txgbe_logtype_tx_free, pmd.net.txgbe.tx_free, DEBUG);