1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2015-2020
9 #include <rte_common.h>
10 #include <rte_ethdev_pci.h>
12 #include <rte_interrupts.h>
14 #include <rte_debug.h>
16 #include <rte_memory.h>
18 #include <rte_alarm.h>
20 #include "txgbe_logs.h"
21 #include "base/txgbe.h"
22 #include "txgbe_ethdev.h"
23 #include "txgbe_rxtx.h"
24 #include "txgbe_regs_group.h"
26 static const struct reg_info txgbe_regs_general[] = {
27 {TXGBE_RST, 1, 1, "TXGBE_RST"},
28 {TXGBE_STAT, 1, 1, "TXGBE_STAT"},
29 {TXGBE_PORTCTL, 1, 1, "TXGBE_PORTCTL"},
30 {TXGBE_SDP, 1, 1, "TXGBE_SDP"},
31 {TXGBE_SDPCTL, 1, 1, "TXGBE_SDPCTL"},
32 {TXGBE_LEDCTL, 1, 1, "TXGBE_LEDCTL"},
36 static const struct reg_info txgbe_regs_nvm[] = {
40 static const struct reg_info txgbe_regs_interrupt[] = {
44 static const struct reg_info txgbe_regs_fctl_others[] = {
48 static const struct reg_info txgbe_regs_rxdma[] = {
52 static const struct reg_info txgbe_regs_rx[] = {
56 static struct reg_info txgbe_regs_tx[] = {
60 static const struct reg_info txgbe_regs_wakeup[] = {
64 static const struct reg_info txgbe_regs_dcb[] = {
68 static const struct reg_info txgbe_regs_mac[] = {
72 static const struct reg_info txgbe_regs_diagnostic[] = {
77 static const struct reg_info *txgbe_regs_others[] = {
81 txgbe_regs_fctl_others,
88 txgbe_regs_diagnostic,
91 static int txgbe_dev_set_link_up(struct rte_eth_dev *dev);
92 static int txgbe_dev_set_link_down(struct rte_eth_dev *dev);
93 static int txgbe_dev_close(struct rte_eth_dev *dev);
94 static int txgbe_dev_link_update(struct rte_eth_dev *dev,
95 int wait_to_complete);
96 static int txgbe_dev_stats_reset(struct rte_eth_dev *dev);
97 static void txgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
98 static void txgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev,
101 static void txgbe_dev_link_status_print(struct rte_eth_dev *dev);
102 static int txgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on);
103 static int txgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev);
104 static int txgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
105 static int txgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
106 static int txgbe_dev_interrupt_action(struct rte_eth_dev *dev,
107 struct rte_intr_handle *handle);
108 static void txgbe_dev_interrupt_handler(void *param);
109 static void txgbe_dev_interrupt_delayed_handler(void *param);
110 static void txgbe_configure_msix(struct rte_eth_dev *dev);
112 #define TXGBE_SET_HWSTRIP(h, q) do {\
113 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
114 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
115 (h)->bitmap[idx] |= 1 << bit;\
118 #define TXGBE_CLEAR_HWSTRIP(h, q) do {\
119 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
120 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
121 (h)->bitmap[idx] &= ~(1 << bit);\
124 #define TXGBE_GET_HWSTRIP(h, q, r) do {\
125 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
126 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
127 (r) = (h)->bitmap[idx] >> bit & 1;\
131 * The set of PCI devices this driver supports
133 static const struct rte_pci_id pci_id_txgbe_map[] = {
134 { RTE_PCI_DEVICE(PCI_VENDOR_ID_WANGXUN, TXGBE_DEV_ID_RAPTOR_SFP) },
135 { RTE_PCI_DEVICE(PCI_VENDOR_ID_WANGXUN, TXGBE_DEV_ID_WX1820_SFP) },
136 { .vendor_id = 0, /* sentinel */ },
139 static const struct rte_eth_desc_lim rx_desc_lim = {
140 .nb_max = TXGBE_RING_DESC_MAX,
141 .nb_min = TXGBE_RING_DESC_MIN,
142 .nb_align = TXGBE_RXD_ALIGN,
145 static const struct rte_eth_desc_lim tx_desc_lim = {
146 .nb_max = TXGBE_RING_DESC_MAX,
147 .nb_min = TXGBE_RING_DESC_MIN,
148 .nb_align = TXGBE_TXD_ALIGN,
149 .nb_seg_max = TXGBE_TX_MAX_SEG,
150 .nb_mtu_seg_max = TXGBE_TX_MAX_SEG,
153 static const struct eth_dev_ops txgbe_eth_dev_ops;
155 #define HW_XSTAT(m) {#m, offsetof(struct txgbe_hw_stats, m)}
156 #define HW_XSTAT_NAME(m, n) {n, offsetof(struct txgbe_hw_stats, m)}
157 static const struct rte_txgbe_xstats_name_off rte_txgbe_stats_strings[] = {
159 HW_XSTAT(mng_bmc2host_packets),
160 HW_XSTAT(mng_host2bmc_packets),
162 HW_XSTAT(rx_packets),
163 HW_XSTAT(tx_packets),
166 HW_XSTAT(rx_total_bytes),
167 HW_XSTAT(rx_total_packets),
168 HW_XSTAT(tx_total_packets),
169 HW_XSTAT(rx_total_missed_packets),
170 HW_XSTAT(rx_broadcast_packets),
171 HW_XSTAT(rx_multicast_packets),
172 HW_XSTAT(rx_management_packets),
173 HW_XSTAT(tx_management_packets),
174 HW_XSTAT(rx_management_dropped),
177 HW_XSTAT(rx_crc_errors),
178 HW_XSTAT(rx_illegal_byte_errors),
179 HW_XSTAT(rx_error_bytes),
180 HW_XSTAT(rx_mac_short_packet_dropped),
181 HW_XSTAT(rx_length_errors),
182 HW_XSTAT(rx_undersize_errors),
183 HW_XSTAT(rx_fragment_errors),
184 HW_XSTAT(rx_oversize_errors),
185 HW_XSTAT(rx_jabber_errors),
186 HW_XSTAT(rx_l3_l4_xsum_error),
187 HW_XSTAT(mac_local_errors),
188 HW_XSTAT(mac_remote_errors),
191 HW_XSTAT(flow_director_added_filters),
192 HW_XSTAT(flow_director_removed_filters),
193 HW_XSTAT(flow_director_filter_add_errors),
194 HW_XSTAT(flow_director_filter_remove_errors),
195 HW_XSTAT(flow_director_matched_filters),
196 HW_XSTAT(flow_director_missed_filters),
199 HW_XSTAT(rx_fcoe_crc_errors),
200 HW_XSTAT(rx_fcoe_mbuf_allocation_errors),
201 HW_XSTAT(rx_fcoe_dropped),
202 HW_XSTAT(rx_fcoe_packets),
203 HW_XSTAT(tx_fcoe_packets),
204 HW_XSTAT(rx_fcoe_bytes),
205 HW_XSTAT(tx_fcoe_bytes),
206 HW_XSTAT(rx_fcoe_no_ddp),
207 HW_XSTAT(rx_fcoe_no_ddp_ext_buff),
210 HW_XSTAT(tx_macsec_pkts_untagged),
211 HW_XSTAT(tx_macsec_pkts_encrypted),
212 HW_XSTAT(tx_macsec_pkts_protected),
213 HW_XSTAT(tx_macsec_octets_encrypted),
214 HW_XSTAT(tx_macsec_octets_protected),
215 HW_XSTAT(rx_macsec_pkts_untagged),
216 HW_XSTAT(rx_macsec_pkts_badtag),
217 HW_XSTAT(rx_macsec_pkts_nosci),
218 HW_XSTAT(rx_macsec_pkts_unknownsci),
219 HW_XSTAT(rx_macsec_octets_decrypted),
220 HW_XSTAT(rx_macsec_octets_validated),
221 HW_XSTAT(rx_macsec_sc_pkts_unchecked),
222 HW_XSTAT(rx_macsec_sc_pkts_delayed),
223 HW_XSTAT(rx_macsec_sc_pkts_late),
224 HW_XSTAT(rx_macsec_sa_pkts_ok),
225 HW_XSTAT(rx_macsec_sa_pkts_invalid),
226 HW_XSTAT(rx_macsec_sa_pkts_notvalid),
227 HW_XSTAT(rx_macsec_sa_pkts_unusedsa),
228 HW_XSTAT(rx_macsec_sa_pkts_notusingsa),
231 HW_XSTAT(rx_size_64_packets),
232 HW_XSTAT(rx_size_65_to_127_packets),
233 HW_XSTAT(rx_size_128_to_255_packets),
234 HW_XSTAT(rx_size_256_to_511_packets),
235 HW_XSTAT(rx_size_512_to_1023_packets),
236 HW_XSTAT(rx_size_1024_to_max_packets),
237 HW_XSTAT(tx_size_64_packets),
238 HW_XSTAT(tx_size_65_to_127_packets),
239 HW_XSTAT(tx_size_128_to_255_packets),
240 HW_XSTAT(tx_size_256_to_511_packets),
241 HW_XSTAT(tx_size_512_to_1023_packets),
242 HW_XSTAT(tx_size_1024_to_max_packets),
245 HW_XSTAT(tx_xon_packets),
246 HW_XSTAT(rx_xon_packets),
247 HW_XSTAT(tx_xoff_packets),
248 HW_XSTAT(rx_xoff_packets),
250 HW_XSTAT_NAME(tx_xon_packets, "tx_flow_control_xon_packets"),
251 HW_XSTAT_NAME(rx_xon_packets, "rx_flow_control_xon_packets"),
252 HW_XSTAT_NAME(tx_xoff_packets, "tx_flow_control_xoff_packets"),
253 HW_XSTAT_NAME(rx_xoff_packets, "rx_flow_control_xoff_packets"),
256 #define TXGBE_NB_HW_STATS (sizeof(rte_txgbe_stats_strings) / \
257 sizeof(rte_txgbe_stats_strings[0]))
259 /* Per-priority statistics */
260 #define UP_XSTAT(m) {#m, offsetof(struct txgbe_hw_stats, up[0].m)}
261 static const struct rte_txgbe_xstats_name_off rte_txgbe_up_strings[] = {
262 UP_XSTAT(rx_up_packets),
263 UP_XSTAT(tx_up_packets),
264 UP_XSTAT(rx_up_bytes),
265 UP_XSTAT(tx_up_bytes),
266 UP_XSTAT(rx_up_drop_packets),
268 UP_XSTAT(tx_up_xon_packets),
269 UP_XSTAT(rx_up_xon_packets),
270 UP_XSTAT(tx_up_xoff_packets),
271 UP_XSTAT(rx_up_xoff_packets),
272 UP_XSTAT(rx_up_dropped),
273 UP_XSTAT(rx_up_mbuf_alloc_errors),
274 UP_XSTAT(tx_up_xon2off_packets),
277 #define TXGBE_NB_UP_STATS (sizeof(rte_txgbe_up_strings) / \
278 sizeof(rte_txgbe_up_strings[0]))
280 /* Per-queue statistics */
281 #define QP_XSTAT(m) {#m, offsetof(struct txgbe_hw_stats, qp[0].m)}
282 static const struct rte_txgbe_xstats_name_off rte_txgbe_qp_strings[] = {
283 QP_XSTAT(rx_qp_packets),
284 QP_XSTAT(tx_qp_packets),
285 QP_XSTAT(rx_qp_bytes),
286 QP_XSTAT(tx_qp_bytes),
287 QP_XSTAT(rx_qp_mc_packets),
290 #define TXGBE_NB_QP_STATS (sizeof(rte_txgbe_qp_strings) / \
291 sizeof(rte_txgbe_qp_strings[0]))
294 txgbe_is_sfp(struct txgbe_hw *hw)
296 switch (hw->phy.type) {
297 case txgbe_phy_sfp_avago:
298 case txgbe_phy_sfp_ftl:
299 case txgbe_phy_sfp_intel:
300 case txgbe_phy_sfp_unknown:
301 case txgbe_phy_sfp_tyco_passive:
302 case txgbe_phy_sfp_unknown_passive:
309 static inline int32_t
310 txgbe_pf_reset_hw(struct txgbe_hw *hw)
315 status = hw->mac.reset_hw(hw);
317 ctrl_ext = rd32(hw, TXGBE_PORTCTL);
318 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
319 ctrl_ext |= TXGBE_PORTCTL_RSTDONE;
320 wr32(hw, TXGBE_PORTCTL, ctrl_ext);
323 if (status == TXGBE_ERR_SFP_NOT_PRESENT)
329 txgbe_enable_intr(struct rte_eth_dev *dev)
331 struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);
332 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
334 wr32(hw, TXGBE_IENMISC, intr->mask_misc);
335 wr32(hw, TXGBE_IMC(0), TXGBE_IMC_MASK);
336 wr32(hw, TXGBE_IMC(1), TXGBE_IMC_MASK);
341 txgbe_disable_intr(struct txgbe_hw *hw)
343 PMD_INIT_FUNC_TRACE();
345 wr32(hw, TXGBE_IENMISC, ~BIT_MASK32);
346 wr32(hw, TXGBE_IMS(0), TXGBE_IMC_MASK);
347 wr32(hw, TXGBE_IMS(1), TXGBE_IMC_MASK);
352 txgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
357 struct txgbe_hw *hw = TXGBE_DEV_HW(eth_dev);
358 struct txgbe_stat_mappings *stat_mappings =
359 TXGBE_DEV_STAT_MAPPINGS(eth_dev);
360 uint32_t qsmr_mask = 0;
361 uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
365 if (hw->mac.type != txgbe_mac_raptor)
368 if (stat_idx & !QMAP_FIELD_RESERVED_BITS_MASK)
371 PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d",
372 (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
375 n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
376 if (n >= TXGBE_NB_STAT_MAPPING) {
377 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
380 offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
382 /* Now clear any previous stat_idx set */
383 clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
385 stat_mappings->tqsm[n] &= ~clearing_mask;
387 stat_mappings->rqsm[n] &= ~clearing_mask;
389 q_map = (uint32_t)stat_idx;
390 q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
391 qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
393 stat_mappings->tqsm[n] |= qsmr_mask;
395 stat_mappings->rqsm[n] |= qsmr_mask;
397 PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d",
398 (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
400 PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
401 is_rx ? stat_mappings->rqsm[n] : stat_mappings->tqsm[n]);
406 txgbe_dcb_init(struct txgbe_hw *hw, struct txgbe_dcb_config *dcb_config)
410 struct txgbe_dcb_tc_config *tc;
412 UNREFERENCED_PARAMETER(hw);
414 dcb_config->num_tcs.pg_tcs = TXGBE_DCB_TC_MAX;
415 dcb_config->num_tcs.pfc_tcs = TXGBE_DCB_TC_MAX;
416 bwgp = (u8)(100 / TXGBE_DCB_TC_MAX);
417 for (i = 0; i < TXGBE_DCB_TC_MAX; i++) {
418 tc = &dcb_config->tc_config[i];
419 tc->path[TXGBE_DCB_TX_CONFIG].bwg_id = i;
420 tc->path[TXGBE_DCB_TX_CONFIG].bwg_percent = bwgp + (i & 1);
421 tc->path[TXGBE_DCB_RX_CONFIG].bwg_id = i;
422 tc->path[TXGBE_DCB_RX_CONFIG].bwg_percent = bwgp + (i & 1);
423 tc->pfc = txgbe_dcb_pfc_disabled;
426 /* Initialize default user to priority mapping, UPx->TC0 */
427 tc = &dcb_config->tc_config[0];
428 tc->path[TXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
429 tc->path[TXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
430 for (i = 0; i < TXGBE_DCB_BWG_MAX; i++) {
431 dcb_config->bw_percentage[i][TXGBE_DCB_TX_CONFIG] = 100;
432 dcb_config->bw_percentage[i][TXGBE_DCB_RX_CONFIG] = 100;
434 dcb_config->rx_pba_cfg = txgbe_dcb_pba_equal;
435 dcb_config->pfc_mode_enable = false;
436 dcb_config->vt_mode = true;
437 dcb_config->round_robin_enable = false;
438 /* support all DCB capabilities */
439 dcb_config->support.capabilities = 0xFF;
443 * Ensure that all locks are released before first NVM or PHY access
446 txgbe_swfw_lock_reset(struct txgbe_hw *hw)
451 * These ones are more tricky since they are common to all ports; but
452 * swfw_sync retries last long enough (1s) to be almost sure that if
453 * lock can not be taken it is due to an improper lock of the
456 mask = TXGBE_MNGSEM_SWPHY |
458 TXGBE_MNGSEM_SWFLASH;
459 if (hw->mac.acquire_swfw_sync(hw, mask) < 0)
460 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
462 hw->mac.release_swfw_sync(hw, mask);
466 eth_txgbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params __rte_unused)
468 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
469 struct txgbe_hw *hw = TXGBE_DEV_HW(eth_dev);
470 struct txgbe_vfta *shadow_vfta = TXGBE_DEV_VFTA(eth_dev);
471 struct txgbe_hwstrip *hwstrip = TXGBE_DEV_HWSTRIP(eth_dev);
472 struct txgbe_dcb_config *dcb_config = TXGBE_DEV_DCB_CONFIG(eth_dev);
473 struct txgbe_bw_conf *bw_conf = TXGBE_DEV_BW_CONF(eth_dev);
474 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
475 const struct rte_memzone *mz;
480 PMD_INIT_FUNC_TRACE();
482 eth_dev->dev_ops = &txgbe_eth_dev_ops;
483 eth_dev->rx_pkt_burst = &txgbe_recv_pkts;
484 eth_dev->tx_pkt_burst = &txgbe_xmit_pkts;
485 eth_dev->tx_pkt_prepare = &txgbe_prep_pkts;
488 * For secondary processes, we don't initialise any further as primary
489 * has already done this work. Only check we don't need a different
490 * RX and TX function.
492 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
493 struct txgbe_tx_queue *txq;
494 /* TX queue function in primary, set by last queue initialized
495 * Tx queue may not initialized by primary process
497 if (eth_dev->data->tx_queues) {
498 uint16_t nb_tx_queues = eth_dev->data->nb_tx_queues;
499 txq = eth_dev->data->tx_queues[nb_tx_queues - 1];
500 txgbe_set_tx_function(eth_dev, txq);
502 /* Use default TX function if we get here */
503 PMD_INIT_LOG(NOTICE, "No TX queues configured yet. "
504 "Using default TX function.");
507 txgbe_set_rx_function(eth_dev);
512 rte_eth_copy_pci_info(eth_dev, pci_dev);
514 /* Vendor and Device ID need to be set before init of shared code */
515 hw->device_id = pci_dev->id.device_id;
516 hw->vendor_id = pci_dev->id.vendor_id;
517 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
518 hw->allow_unsupported_sfp = 1;
520 /* Reserve memory for interrupt status block */
521 mz = rte_eth_dma_zone_reserve(eth_dev, "txgbe_driver", -1,
522 16, TXGBE_ALIGN, SOCKET_ID_ANY);
526 hw->isb_dma = TMZ_PADDR(mz);
527 hw->isb_mem = TMZ_VADDR(mz);
529 /* Initialize the shared code (base driver) */
530 err = txgbe_init_shared_code(hw);
532 PMD_INIT_LOG(ERR, "Shared code init failed: %d", err);
536 /* Unlock any pending hardware semaphore */
537 txgbe_swfw_lock_reset(hw);
539 /* Initialize DCB configuration*/
540 memset(dcb_config, 0, sizeof(struct txgbe_dcb_config));
541 txgbe_dcb_init(hw, dcb_config);
543 /* Get Hardware Flow Control setting */
544 hw->fc.requested_mode = txgbe_fc_full;
545 hw->fc.current_mode = txgbe_fc_full;
546 hw->fc.pause_time = TXGBE_FC_PAUSE_TIME;
547 for (i = 0; i < TXGBE_DCB_TC_MAX; i++) {
548 hw->fc.low_water[i] = TXGBE_FC_XON_LOTH;
549 hw->fc.high_water[i] = TXGBE_FC_XOFF_HITH;
553 err = hw->rom.init_params(hw);
555 PMD_INIT_LOG(ERR, "The EEPROM init failed: %d", err);
559 /* Make sure we have a good EEPROM before we read from it */
560 err = hw->rom.validate_checksum(hw, &csum);
562 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", err);
566 err = hw->mac.init_hw(hw);
569 * Devices with copper phys will fail to initialise if txgbe_init_hw()
570 * is called too soon after the kernel driver unbinding/binding occurs.
571 * The failure occurs in txgbe_identify_phy() for all devices,
572 * but for non-copper devies, txgbe_identify_sfp_module() is
573 * also called. See txgbe_identify_phy(). The reason for the
574 * failure is not known, and only occuts when virtualisation features
575 * are disabled in the bios. A delay of 200ms was found to be enough by
576 * trial-and-error, and is doubled to be safe.
578 if (err && hw->phy.media_type == txgbe_media_type_copper) {
580 err = hw->mac.init_hw(hw);
583 if (err == TXGBE_ERR_SFP_NOT_PRESENT)
586 if (err == TXGBE_ERR_EEPROM_VERSION) {
587 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
588 "LOM. Please be aware there may be issues associated "
589 "with your hardware.");
590 PMD_INIT_LOG(ERR, "If you are experiencing problems "
591 "please contact your hardware representative "
592 "who provided you with this hardware.");
593 } else if (err == TXGBE_ERR_SFP_NOT_SUPPORTED) {
594 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
597 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", err);
601 /* Reset the hw statistics */
602 txgbe_dev_stats_reset(eth_dev);
604 /* disable interrupt */
605 txgbe_disable_intr(hw);
607 /* Allocate memory for storing MAC addresses */
608 eth_dev->data->mac_addrs = rte_zmalloc("txgbe", RTE_ETHER_ADDR_LEN *
609 hw->mac.num_rar_entries, 0);
610 if (eth_dev->data->mac_addrs == NULL) {
612 "Failed to allocate %u bytes needed to store "
614 RTE_ETHER_ADDR_LEN * hw->mac.num_rar_entries);
618 /* Copy the permanent MAC address */
619 rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.perm_addr,
620 ð_dev->data->mac_addrs[0]);
622 /* Allocate memory for storing hash filter MAC addresses */
623 eth_dev->data->hash_mac_addrs = rte_zmalloc("txgbe",
624 RTE_ETHER_ADDR_LEN * TXGBE_VMDQ_NUM_UC_MAC, 0);
625 if (eth_dev->data->hash_mac_addrs == NULL) {
627 "Failed to allocate %d bytes needed to store MAC addresses",
628 RTE_ETHER_ADDR_LEN * TXGBE_VMDQ_NUM_UC_MAC);
632 /* initialize the vfta */
633 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
635 /* initialize the hw strip bitmap*/
636 memset(hwstrip, 0, sizeof(*hwstrip));
638 /* initialize PF if max_vfs not zero */
639 txgbe_pf_host_init(eth_dev);
641 ctrl_ext = rd32(hw, TXGBE_PORTCTL);
642 /* let hardware know driver is loaded */
643 ctrl_ext |= TXGBE_PORTCTL_DRVLOAD;
644 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
645 ctrl_ext |= TXGBE_PORTCTL_RSTDONE;
646 wr32(hw, TXGBE_PORTCTL, ctrl_ext);
649 if (txgbe_is_sfp(hw) && hw->phy.sfp_type != txgbe_sfp_type_not_present)
650 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
651 (int)hw->mac.type, (int)hw->phy.type,
652 (int)hw->phy.sfp_type);
654 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
655 (int)hw->mac.type, (int)hw->phy.type);
657 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
658 eth_dev->data->port_id, pci_dev->id.vendor_id,
659 pci_dev->id.device_id);
661 rte_intr_callback_register(intr_handle,
662 txgbe_dev_interrupt_handler, eth_dev);
664 /* enable uio/vfio intr/eventfd mapping */
665 rte_intr_enable(intr_handle);
667 /* enable support intr */
668 txgbe_enable_intr(eth_dev);
670 /* initialize bandwidth configuration info */
671 memset(bw_conf, 0, sizeof(struct txgbe_bw_conf));
677 eth_txgbe_dev_uninit(struct rte_eth_dev *eth_dev)
679 PMD_INIT_FUNC_TRACE();
681 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
684 txgbe_dev_close(eth_dev);
690 eth_txgbe_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
691 struct rte_pci_device *pci_dev)
693 struct rte_eth_dev *pf_ethdev;
694 struct rte_eth_devargs eth_da;
697 if (pci_dev->device.devargs) {
698 retval = rte_eth_devargs_parse(pci_dev->device.devargs->args,
703 memset(ð_da, 0, sizeof(eth_da));
706 retval = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
707 sizeof(struct txgbe_adapter),
708 eth_dev_pci_specific_init, pci_dev,
709 eth_txgbe_dev_init, NULL);
711 if (retval || eth_da.nb_representor_ports < 1)
714 pf_ethdev = rte_eth_dev_allocated(pci_dev->device.name);
715 if (pf_ethdev == NULL)
721 static int eth_txgbe_pci_remove(struct rte_pci_device *pci_dev)
723 struct rte_eth_dev *ethdev;
725 ethdev = rte_eth_dev_allocated(pci_dev->device.name);
729 return rte_eth_dev_destroy(ethdev, eth_txgbe_dev_uninit);
732 static struct rte_pci_driver rte_txgbe_pmd = {
733 .id_table = pci_id_txgbe_map,
734 .drv_flags = RTE_PCI_DRV_NEED_MAPPING |
735 RTE_PCI_DRV_INTR_LSC,
736 .probe = eth_txgbe_pci_probe,
737 .remove = eth_txgbe_pci_remove,
741 txgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
743 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
744 struct txgbe_vfta *shadow_vfta = TXGBE_DEV_VFTA(dev);
749 vid_idx = (uint32_t)((vlan_id >> 5) & 0x7F);
750 vid_bit = (uint32_t)(1 << (vlan_id & 0x1F));
751 vfta = rd32(hw, TXGBE_VLANTBL(vid_idx));
756 wr32(hw, TXGBE_VLANTBL(vid_idx), vfta);
758 /* update local VFTA copy */
759 shadow_vfta->vfta[vid_idx] = vfta;
765 txgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
767 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
768 struct txgbe_rx_queue *rxq;
770 uint32_t rxcfg, rxbal, rxbah;
773 txgbe_vlan_hw_strip_enable(dev, queue);
775 txgbe_vlan_hw_strip_disable(dev, queue);
777 rxq = dev->data->rx_queues[queue];
778 rxbal = rd32(hw, TXGBE_RXBAL(rxq->reg_idx));
779 rxbah = rd32(hw, TXGBE_RXBAH(rxq->reg_idx));
780 rxcfg = rd32(hw, TXGBE_RXCFG(rxq->reg_idx));
781 if (rxq->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) {
782 restart = (rxcfg & TXGBE_RXCFG_ENA) &&
783 !(rxcfg & TXGBE_RXCFG_VLAN);
784 rxcfg |= TXGBE_RXCFG_VLAN;
786 restart = (rxcfg & TXGBE_RXCFG_ENA) &&
787 (rxcfg & TXGBE_RXCFG_VLAN);
788 rxcfg &= ~TXGBE_RXCFG_VLAN;
790 rxcfg &= ~TXGBE_RXCFG_ENA;
793 /* set vlan strip for ring */
794 txgbe_dev_rx_queue_stop(dev, queue);
795 wr32(hw, TXGBE_RXBAL(rxq->reg_idx), rxbal);
796 wr32(hw, TXGBE_RXBAH(rxq->reg_idx), rxbah);
797 wr32(hw, TXGBE_RXCFG(rxq->reg_idx), rxcfg);
798 txgbe_dev_rx_queue_start(dev, queue);
803 txgbe_vlan_tpid_set(struct rte_eth_dev *dev,
804 enum rte_vlan_type vlan_type,
807 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
809 uint32_t portctrl, vlan_ext, qinq;
811 portctrl = rd32(hw, TXGBE_PORTCTL);
813 vlan_ext = (portctrl & TXGBE_PORTCTL_VLANEXT);
814 qinq = vlan_ext && (portctrl & TXGBE_PORTCTL_QINQ);
816 case ETH_VLAN_TYPE_INNER:
818 wr32m(hw, TXGBE_VLANCTL,
819 TXGBE_VLANCTL_TPID_MASK,
820 TXGBE_VLANCTL_TPID(tpid));
821 wr32m(hw, TXGBE_DMATXCTRL,
822 TXGBE_DMATXCTRL_TPID_MASK,
823 TXGBE_DMATXCTRL_TPID(tpid));
826 PMD_DRV_LOG(ERR, "Inner type is not supported"
831 wr32m(hw, TXGBE_TAGTPID(0),
832 TXGBE_TAGTPID_LSB_MASK,
833 TXGBE_TAGTPID_LSB(tpid));
836 case ETH_VLAN_TYPE_OUTER:
838 /* Only the high 16-bits is valid */
839 wr32m(hw, TXGBE_EXTAG,
840 TXGBE_EXTAG_VLAN_MASK,
841 TXGBE_EXTAG_VLAN(tpid));
843 wr32m(hw, TXGBE_VLANCTL,
844 TXGBE_VLANCTL_TPID_MASK,
845 TXGBE_VLANCTL_TPID(tpid));
846 wr32m(hw, TXGBE_DMATXCTRL,
847 TXGBE_DMATXCTRL_TPID_MASK,
848 TXGBE_DMATXCTRL_TPID(tpid));
852 wr32m(hw, TXGBE_TAGTPID(0),
853 TXGBE_TAGTPID_MSB_MASK,
854 TXGBE_TAGTPID_MSB(tpid));
858 PMD_DRV_LOG(ERR, "Unsupported VLAN type %d", vlan_type);
866 txgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
868 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
871 PMD_INIT_FUNC_TRACE();
873 /* Filter Table Disable */
874 vlnctrl = rd32(hw, TXGBE_VLANCTL);
875 vlnctrl &= ~TXGBE_VLANCTL_VFE;
876 wr32(hw, TXGBE_VLANCTL, vlnctrl);
880 txgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
882 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
883 struct txgbe_vfta *shadow_vfta = TXGBE_DEV_VFTA(dev);
887 PMD_INIT_FUNC_TRACE();
889 /* Filter Table Enable */
890 vlnctrl = rd32(hw, TXGBE_VLANCTL);
891 vlnctrl &= ~TXGBE_VLANCTL_CFIENA;
892 vlnctrl |= TXGBE_VLANCTL_VFE;
893 wr32(hw, TXGBE_VLANCTL, vlnctrl);
895 /* write whatever is in local vfta copy */
896 for (i = 0; i < TXGBE_VFTA_SIZE; i++)
897 wr32(hw, TXGBE_VLANTBL(i), shadow_vfta->vfta[i]);
901 txgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
903 struct txgbe_hwstrip *hwstrip = TXGBE_DEV_HWSTRIP(dev);
904 struct txgbe_rx_queue *rxq;
906 if (queue >= TXGBE_MAX_RX_QUEUE_NUM)
910 TXGBE_SET_HWSTRIP(hwstrip, queue);
912 TXGBE_CLEAR_HWSTRIP(hwstrip, queue);
914 if (queue >= dev->data->nb_rx_queues)
917 rxq = dev->data->rx_queues[queue];
920 rxq->vlan_flags = PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
921 rxq->offloads |= DEV_RX_OFFLOAD_VLAN_STRIP;
923 rxq->vlan_flags = PKT_RX_VLAN;
924 rxq->offloads &= ~DEV_RX_OFFLOAD_VLAN_STRIP;
929 txgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
931 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
934 PMD_INIT_FUNC_TRACE();
936 ctrl = rd32(hw, TXGBE_RXCFG(queue));
937 ctrl &= ~TXGBE_RXCFG_VLAN;
938 wr32(hw, TXGBE_RXCFG(queue), ctrl);
940 /* record those setting for HW strip per queue */
941 txgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
945 txgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
947 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
950 PMD_INIT_FUNC_TRACE();
952 ctrl = rd32(hw, TXGBE_RXCFG(queue));
953 ctrl |= TXGBE_RXCFG_VLAN;
954 wr32(hw, TXGBE_RXCFG(queue), ctrl);
956 /* record those setting for HW strip per queue */
957 txgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
961 txgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
963 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
966 PMD_INIT_FUNC_TRACE();
968 ctrl = rd32(hw, TXGBE_PORTCTL);
969 ctrl &= ~TXGBE_PORTCTL_VLANEXT;
970 ctrl &= ~TXGBE_PORTCTL_QINQ;
971 wr32(hw, TXGBE_PORTCTL, ctrl);
975 txgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
977 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
978 struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
979 struct rte_eth_txmode *txmode = &dev->data->dev_conf.txmode;
982 PMD_INIT_FUNC_TRACE();
984 ctrl = rd32(hw, TXGBE_PORTCTL);
985 ctrl |= TXGBE_PORTCTL_VLANEXT;
986 if (rxmode->offloads & DEV_RX_OFFLOAD_QINQ_STRIP ||
987 txmode->offloads & DEV_TX_OFFLOAD_QINQ_INSERT)
988 ctrl |= TXGBE_PORTCTL_QINQ;
989 wr32(hw, TXGBE_PORTCTL, ctrl);
993 txgbe_vlan_hw_strip_config(struct rte_eth_dev *dev)
995 struct txgbe_rx_queue *rxq;
998 PMD_INIT_FUNC_TRACE();
1000 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1001 rxq = dev->data->rx_queues[i];
1003 if (rxq->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1004 txgbe_vlan_strip_queue_set(dev, i, 1);
1006 txgbe_vlan_strip_queue_set(dev, i, 0);
1011 txgbe_config_vlan_strip_on_all_queues(struct rte_eth_dev *dev, int mask)
1014 struct rte_eth_rxmode *rxmode;
1015 struct txgbe_rx_queue *rxq;
1017 if (mask & ETH_VLAN_STRIP_MASK) {
1018 rxmode = &dev->data->dev_conf.rxmode;
1019 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1020 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1021 rxq = dev->data->rx_queues[i];
1022 rxq->offloads |= DEV_RX_OFFLOAD_VLAN_STRIP;
1025 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1026 rxq = dev->data->rx_queues[i];
1027 rxq->offloads &= ~DEV_RX_OFFLOAD_VLAN_STRIP;
1033 txgbe_vlan_offload_config(struct rte_eth_dev *dev, int mask)
1035 struct rte_eth_rxmode *rxmode;
1036 rxmode = &dev->data->dev_conf.rxmode;
1038 if (mask & ETH_VLAN_STRIP_MASK)
1039 txgbe_vlan_hw_strip_config(dev);
1041 if (mask & ETH_VLAN_FILTER_MASK) {
1042 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
1043 txgbe_vlan_hw_filter_enable(dev);
1045 txgbe_vlan_hw_filter_disable(dev);
1048 if (mask & ETH_VLAN_EXTEND_MASK) {
1049 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
1050 txgbe_vlan_hw_extend_enable(dev);
1052 txgbe_vlan_hw_extend_disable(dev);
1059 txgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1061 txgbe_config_vlan_strip_on_all_queues(dev, mask);
1063 txgbe_vlan_offload_config(dev, mask);
1069 txgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1071 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
1072 /* VLNCTL: enable vlan filtering and allow all vlan tags through */
1073 uint32_t vlanctrl = rd32(hw, TXGBE_VLANCTL);
1075 vlanctrl |= TXGBE_VLANCTL_VFE; /* enable vlan filters */
1076 wr32(hw, TXGBE_VLANCTL, vlanctrl);
1080 txgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q)
1082 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1087 RTE_ETH_DEV_SRIOV(dev).active = ETH_64_POOLS;
1090 RTE_ETH_DEV_SRIOV(dev).active = ETH_32_POOLS;
1096 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool =
1097 TXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
1098 RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx =
1099 pci_dev->max_vfs * RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
1104 txgbe_check_mq_mode(struct rte_eth_dev *dev)
1106 struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
1107 uint16_t nb_rx_q = dev->data->nb_rx_queues;
1108 uint16_t nb_tx_q = dev->data->nb_tx_queues;
1110 if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
1111 /* check multi-queue mode */
1112 switch (dev_conf->rxmode.mq_mode) {
1113 case ETH_MQ_RX_VMDQ_DCB:
1114 PMD_INIT_LOG(INFO, "ETH_MQ_RX_VMDQ_DCB mode supported in SRIOV");
1116 case ETH_MQ_RX_VMDQ_DCB_RSS:
1117 /* DCB/RSS VMDQ in SRIOV mode, not implement yet */
1118 PMD_INIT_LOG(ERR, "SRIOV active,"
1119 " unsupported mq_mode rx %d.",
1120 dev_conf->rxmode.mq_mode);
1123 case ETH_MQ_RX_VMDQ_RSS:
1124 dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_RSS;
1125 if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)
1126 if (txgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) {
1127 PMD_INIT_LOG(ERR, "SRIOV is active,"
1128 " invalid queue number"
1129 " for VMDQ RSS, allowed"
1130 " value are 1, 2 or 4.");
1134 case ETH_MQ_RX_VMDQ_ONLY:
1135 case ETH_MQ_RX_NONE:
1136 /* if nothing mq mode configure, use default scheme */
1137 dev->data->dev_conf.rxmode.mq_mode =
1138 ETH_MQ_RX_VMDQ_ONLY;
1140 default: /* ETH_MQ_RX_DCB, ETH_MQ_RX_DCB_RSS or ETH_MQ_TX_DCB*/
1141 /* SRIOV only works in VMDq enable mode */
1142 PMD_INIT_LOG(ERR, "SRIOV is active,"
1143 " wrong mq_mode rx %d.",
1144 dev_conf->rxmode.mq_mode);
1148 switch (dev_conf->txmode.mq_mode) {
1149 case ETH_MQ_TX_VMDQ_DCB:
1150 PMD_INIT_LOG(INFO, "ETH_MQ_TX_VMDQ_DCB mode supported in SRIOV");
1151 dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_DCB;
1153 default: /* ETH_MQ_TX_VMDQ_ONLY or ETH_MQ_TX_NONE */
1154 dev->data->dev_conf.txmode.mq_mode =
1155 ETH_MQ_TX_VMDQ_ONLY;
1159 /* check valid queue number */
1160 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) ||
1161 (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) {
1162 PMD_INIT_LOG(ERR, "SRIOV is active,"
1163 " nb_rx_q=%d nb_tx_q=%d queue number"
1164 " must be less than or equal to %d.",
1166 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool);
1170 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
1171 PMD_INIT_LOG(ERR, "VMDQ+DCB+RSS mq_mode is"
1175 /* check configuration for vmdb+dcb mode */
1176 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB) {
1177 const struct rte_eth_vmdq_dcb_conf *conf;
1179 if (nb_rx_q != TXGBE_VMDQ_DCB_NB_QUEUES) {
1180 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.",
1181 TXGBE_VMDQ_DCB_NB_QUEUES);
1184 conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf;
1185 if (!(conf->nb_queue_pools == ETH_16_POOLS ||
1186 conf->nb_queue_pools == ETH_32_POOLS)) {
1187 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
1188 " nb_queue_pools must be %d or %d.",
1189 ETH_16_POOLS, ETH_32_POOLS);
1193 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) {
1194 const struct rte_eth_vmdq_dcb_tx_conf *conf;
1196 if (nb_tx_q != TXGBE_VMDQ_DCB_NB_QUEUES) {
1197 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d",
1198 TXGBE_VMDQ_DCB_NB_QUEUES);
1201 conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf;
1202 if (!(conf->nb_queue_pools == ETH_16_POOLS ||
1203 conf->nb_queue_pools == ETH_32_POOLS)) {
1204 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
1205 " nb_queue_pools != %d and"
1206 " nb_queue_pools != %d.",
1207 ETH_16_POOLS, ETH_32_POOLS);
1212 /* For DCB mode check our configuration before we go further */
1213 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_DCB) {
1214 const struct rte_eth_dcb_rx_conf *conf;
1216 conf = &dev_conf->rx_adv_conf.dcb_rx_conf;
1217 if (!(conf->nb_tcs == ETH_4_TCS ||
1218 conf->nb_tcs == ETH_8_TCS)) {
1219 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
1220 " and nb_tcs != %d.",
1221 ETH_4_TCS, ETH_8_TCS);
1226 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_DCB) {
1227 const struct rte_eth_dcb_tx_conf *conf;
1229 conf = &dev_conf->tx_adv_conf.dcb_tx_conf;
1230 if (!(conf->nb_tcs == ETH_4_TCS ||
1231 conf->nb_tcs == ETH_8_TCS)) {
1232 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
1233 " and nb_tcs != %d.",
1234 ETH_4_TCS, ETH_8_TCS);
1243 txgbe_dev_configure(struct rte_eth_dev *dev)
1245 struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);
1246 struct txgbe_adapter *adapter = TXGBE_DEV_ADAPTER(dev);
1249 PMD_INIT_FUNC_TRACE();
1251 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
1252 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
1254 /* multiple queue mode checking */
1255 ret = txgbe_check_mq_mode(dev);
1257 PMD_DRV_LOG(ERR, "txgbe_check_mq_mode fails with %d.",
1262 /* set flag to update link status after init */
1263 intr->flags |= TXGBE_FLAG_NEED_LINK_UPDATE;
1266 * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
1267 * allocation Rx preconditions we will reset it.
1269 adapter->rx_bulk_alloc_allowed = true;
1275 txgbe_dev_phy_intr_setup(struct rte_eth_dev *dev)
1277 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
1278 struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);
1281 gpie = rd32(hw, TXGBE_GPIOINTEN);
1282 gpie |= TXGBE_GPIOBIT_6;
1283 wr32(hw, TXGBE_GPIOINTEN, gpie);
1284 intr->mask_misc |= TXGBE_ICRMISC_GPIO;
1288 txgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
1289 uint16_t tx_rate, uint64_t q_msk)
1291 struct txgbe_hw *hw;
1292 struct txgbe_vf_info *vfinfo;
1293 struct rte_eth_link link;
1294 uint8_t nb_q_per_pool;
1295 uint32_t queue_stride;
1296 uint32_t queue_idx, idx = 0, vf_idx;
1298 uint16_t total_rate = 0;
1299 struct rte_pci_device *pci_dev;
1302 pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1303 ret = rte_eth_link_get_nowait(dev->data->port_id, &link);
1307 if (vf >= pci_dev->max_vfs)
1310 if (tx_rate > link.link_speed)
1316 hw = TXGBE_DEV_HW(dev);
1317 vfinfo = *(TXGBE_DEV_VFDATA(dev));
1318 nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
1319 queue_stride = TXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
1320 queue_idx = vf * queue_stride;
1321 queue_end = queue_idx + nb_q_per_pool - 1;
1322 if (queue_end >= hw->mac.max_tx_queues)
1326 for (vf_idx = 0; vf_idx < pci_dev->max_vfs; vf_idx++) {
1329 for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
1331 total_rate += vfinfo[vf_idx].tx_rate[idx];
1337 /* Store tx_rate for this vf. */
1338 for (idx = 0; idx < nb_q_per_pool; idx++) {
1339 if (((uint64_t)0x1 << idx) & q_msk) {
1340 if (vfinfo[vf].tx_rate[idx] != tx_rate)
1341 vfinfo[vf].tx_rate[idx] = tx_rate;
1342 total_rate += tx_rate;
1346 if (total_rate > dev->data->dev_link.link_speed) {
1347 /* Reset stored TX rate of the VF if it causes exceed
1350 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
1354 /* Set ARBTXRATE of each queue/pool for vf X */
1355 for (; queue_idx <= queue_end; queue_idx++) {
1357 txgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
1365 * Configure device link speed and setup link.
1366 * It returns 0 on success.
1369 txgbe_dev_start(struct rte_eth_dev *dev)
1371 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
1372 struct txgbe_hw_stats *hw_stats = TXGBE_DEV_STATS(dev);
1373 struct txgbe_vf_info *vfinfo = *TXGBE_DEV_VFDATA(dev);
1374 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1375 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1376 uint32_t intr_vector = 0;
1378 bool link_up = false, negotiate = 0;
1380 uint32_t allowed_speeds = 0;
1384 uint32_t *link_speeds;
1386 PMD_INIT_FUNC_TRACE();
1388 /* TXGBE devices don't support:
1389 * - half duplex (checked afterwards for valid speeds)
1390 * - fixed speed: TODO implement
1392 if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
1394 "Invalid link_speeds for port %u, fix speed not supported",
1395 dev->data->port_id);
1399 /* Stop the link setup handler before resetting the HW. */
1400 rte_eal_alarm_cancel(txgbe_dev_setup_link_alarm_handler, dev);
1402 /* disable uio/vfio intr/eventfd mapping */
1403 rte_intr_disable(intr_handle);
1406 hw->adapter_stopped = 0;
1409 /* reinitialize adapter
1410 * this calls reset and start
1412 hw->nb_rx_queues = dev->data->nb_rx_queues;
1413 hw->nb_tx_queues = dev->data->nb_tx_queues;
1414 status = txgbe_pf_reset_hw(hw);
1417 hw->mac.start_hw(hw);
1418 hw->mac.get_link_status = true;
1420 /* configure PF module if SRIOV enabled */
1421 txgbe_pf_host_configure(dev);
1423 txgbe_dev_phy_intr_setup(dev);
1425 /* check and configure queue intr-vector mapping */
1426 if ((rte_intr_cap_multiple(intr_handle) ||
1427 !RTE_ETH_DEV_SRIOV(dev).active) &&
1428 dev->data->dev_conf.intr_conf.rxq != 0) {
1429 intr_vector = dev->data->nb_rx_queues;
1430 if (rte_intr_efd_enable(intr_handle, intr_vector))
1434 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1435 intr_handle->intr_vec =
1436 rte_zmalloc("intr_vec",
1437 dev->data->nb_rx_queues * sizeof(int), 0);
1438 if (intr_handle->intr_vec == NULL) {
1439 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
1440 " intr_vec", dev->data->nb_rx_queues);
1445 /* confiugre msix for sleep until rx interrupt */
1446 txgbe_configure_msix(dev);
1448 /* initialize transmission unit */
1449 txgbe_dev_tx_init(dev);
1451 /* This can fail when allocating mbufs for descriptor rings */
1452 err = txgbe_dev_rx_init(dev);
1454 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
1458 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
1459 ETH_VLAN_EXTEND_MASK;
1460 err = txgbe_vlan_offload_config(dev, mask);
1462 PMD_INIT_LOG(ERR, "Unable to set VLAN offload");
1466 if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1467 /* Enable vlan filtering for VMDq */
1468 txgbe_vmdq_vlan_hw_filter_enable(dev);
1471 /* Configure DCB hw */
1472 txgbe_configure_pb(dev);
1473 txgbe_configure_port(dev);
1474 txgbe_configure_dcb(dev);
1476 /* Restore vf rate limit */
1477 if (vfinfo != NULL) {
1478 for (vf = 0; vf < pci_dev->max_vfs; vf++)
1479 for (idx = 0; idx < TXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
1480 if (vfinfo[vf].tx_rate[idx] != 0)
1481 txgbe_set_vf_rate_limit(dev, vf,
1482 vfinfo[vf].tx_rate[idx],
1486 err = txgbe_dev_rxtx_start(dev);
1488 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
1492 /* Skip link setup if loopback mode is enabled. */
1493 if (hw->mac.type == txgbe_mac_raptor &&
1494 dev->data->dev_conf.lpbk_mode)
1495 goto skip_link_setup;
1497 if (txgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
1498 err = hw->mac.setup_sfp(hw);
1503 if (hw->phy.media_type == txgbe_media_type_copper) {
1504 /* Turn on the copper */
1505 hw->phy.set_phy_power(hw, true);
1507 /* Turn on the laser */
1508 hw->mac.enable_tx_laser(hw);
1511 err = hw->mac.check_link(hw, &speed, &link_up, 0);
1514 dev->data->dev_link.link_status = link_up;
1516 err = hw->mac.get_link_capabilities(hw, &speed, &negotiate);
1520 allowed_speeds = ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
1523 link_speeds = &dev->data->dev_conf.link_speeds;
1524 if (*link_speeds & ~allowed_speeds) {
1525 PMD_INIT_LOG(ERR, "Invalid link setting");
1530 if (*link_speeds == ETH_LINK_SPEED_AUTONEG) {
1531 speed = (TXGBE_LINK_SPEED_100M_FULL |
1532 TXGBE_LINK_SPEED_1GB_FULL |
1533 TXGBE_LINK_SPEED_10GB_FULL);
1535 if (*link_speeds & ETH_LINK_SPEED_10G)
1536 speed |= TXGBE_LINK_SPEED_10GB_FULL;
1537 if (*link_speeds & ETH_LINK_SPEED_5G)
1538 speed |= TXGBE_LINK_SPEED_5GB_FULL;
1539 if (*link_speeds & ETH_LINK_SPEED_2_5G)
1540 speed |= TXGBE_LINK_SPEED_2_5GB_FULL;
1541 if (*link_speeds & ETH_LINK_SPEED_1G)
1542 speed |= TXGBE_LINK_SPEED_1GB_FULL;
1543 if (*link_speeds & ETH_LINK_SPEED_100M)
1544 speed |= TXGBE_LINK_SPEED_100M_FULL;
1547 err = hw->mac.setup_link(hw, speed, link_up);
1553 if (rte_intr_allow_others(intr_handle)) {
1554 /* check if lsc interrupt is enabled */
1555 if (dev->data->dev_conf.intr_conf.lsc != 0)
1556 txgbe_dev_lsc_interrupt_setup(dev, TRUE);
1558 txgbe_dev_lsc_interrupt_setup(dev, FALSE);
1559 txgbe_dev_macsec_interrupt_setup(dev);
1560 txgbe_set_ivar_map(hw, -1, 1, TXGBE_MISC_VEC_ID);
1562 rte_intr_callback_unregister(intr_handle,
1563 txgbe_dev_interrupt_handler, dev);
1564 if (dev->data->dev_conf.intr_conf.lsc != 0)
1565 PMD_INIT_LOG(INFO, "lsc won't enable because of"
1566 " no intr multiplex");
1569 /* check if rxq interrupt is enabled */
1570 if (dev->data->dev_conf.intr_conf.rxq != 0 &&
1571 rte_intr_dp_is_en(intr_handle))
1572 txgbe_dev_rxq_interrupt_setup(dev);
1574 /* enable uio/vfio intr/eventfd mapping */
1575 rte_intr_enable(intr_handle);
1577 /* resume enabled intr since hw reset */
1578 txgbe_enable_intr(dev);
1581 * Update link status right before return, because it may
1582 * start link configuration process in a separate thread.
1584 txgbe_dev_link_update(dev, 0);
1586 wr32m(hw, TXGBE_LEDCTL, 0xFFFFFFFF, TXGBE_LEDCTL_ORD_MASK);
1588 txgbe_read_stats_registers(hw, hw_stats);
1589 hw->offset_loaded = 1;
1594 PMD_INIT_LOG(ERR, "failure in dev start: %d", err);
1595 txgbe_dev_clear_queues(dev);
1600 * Stop device: disable rx and tx functions to allow for reconfiguring.
1603 txgbe_dev_stop(struct rte_eth_dev *dev)
1605 struct rte_eth_link link;
1606 struct txgbe_adapter *adapter = TXGBE_DEV_ADAPTER(dev);
1607 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
1608 struct txgbe_vf_info *vfinfo = *TXGBE_DEV_VFDATA(dev);
1609 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1610 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1613 if (hw->adapter_stopped)
1616 PMD_INIT_FUNC_TRACE();
1618 rte_eal_alarm_cancel(txgbe_dev_setup_link_alarm_handler, dev);
1620 /* disable interrupts */
1621 txgbe_disable_intr(hw);
1624 txgbe_pf_reset_hw(hw);
1625 hw->adapter_stopped = 0;
1630 for (vf = 0; vfinfo != NULL && vf < pci_dev->max_vfs; vf++)
1631 vfinfo[vf].clear_to_send = false;
1633 if (hw->phy.media_type == txgbe_media_type_copper) {
1634 /* Turn off the copper */
1635 hw->phy.set_phy_power(hw, false);
1637 /* Turn off the laser */
1638 hw->mac.disable_tx_laser(hw);
1641 txgbe_dev_clear_queues(dev);
1643 /* Clear stored conf */
1644 dev->data->scattered_rx = 0;
1647 /* Clear recorded link status */
1648 memset(&link, 0, sizeof(link));
1649 rte_eth_linkstatus_set(dev, &link);
1651 if (!rte_intr_allow_others(intr_handle))
1652 /* resume to the default handler */
1653 rte_intr_callback_register(intr_handle,
1654 txgbe_dev_interrupt_handler,
1657 /* Clean datapath event and queue/vec mapping */
1658 rte_intr_efd_disable(intr_handle);
1659 if (intr_handle->intr_vec != NULL) {
1660 rte_free(intr_handle->intr_vec);
1661 intr_handle->intr_vec = NULL;
1664 adapter->rss_reta_updated = 0;
1665 wr32m(hw, TXGBE_LEDCTL, 0xFFFFFFFF, TXGBE_LEDCTL_SEL_MASK);
1667 hw->adapter_stopped = true;
1668 dev->data->dev_started = 0;
1674 * Set device link up: enable tx.
1677 txgbe_dev_set_link_up(struct rte_eth_dev *dev)
1679 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
1681 if (hw->phy.media_type == txgbe_media_type_copper) {
1682 /* Turn on the copper */
1683 hw->phy.set_phy_power(hw, true);
1685 /* Turn on the laser */
1686 hw->mac.enable_tx_laser(hw);
1687 txgbe_dev_link_update(dev, 0);
1694 * Set device link down: disable tx.
1697 txgbe_dev_set_link_down(struct rte_eth_dev *dev)
1699 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
1701 if (hw->phy.media_type == txgbe_media_type_copper) {
1702 /* Turn off the copper */
1703 hw->phy.set_phy_power(hw, false);
1705 /* Turn off the laser */
1706 hw->mac.disable_tx_laser(hw);
1707 txgbe_dev_link_update(dev, 0);
1714 * Reset and stop device.
1717 txgbe_dev_close(struct rte_eth_dev *dev)
1719 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
1720 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1721 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1725 PMD_INIT_FUNC_TRACE();
1727 txgbe_pf_reset_hw(hw);
1729 ret = txgbe_dev_stop(dev);
1731 txgbe_dev_free_queues(dev);
1733 /* reprogram the RAR[0] in case user changed it. */
1734 txgbe_set_rar(hw, 0, hw->mac.addr, 0, true);
1736 /* Unlock any pending hardware semaphore */
1737 txgbe_swfw_lock_reset(hw);
1739 /* disable uio intr before callback unregister */
1740 rte_intr_disable(intr_handle);
1743 ret = rte_intr_callback_unregister(intr_handle,
1744 txgbe_dev_interrupt_handler, dev);
1745 if (ret >= 0 || ret == -ENOENT) {
1747 } else if (ret != -EAGAIN) {
1749 "intr callback unregister failed: %d",
1753 } while (retries++ < (10 + TXGBE_LINK_UP_TIME));
1755 /* cancel the delay handler before remove dev */
1756 rte_eal_alarm_cancel(txgbe_dev_interrupt_delayed_handler, dev);
1758 /* uninitialize PF if max_vfs not zero */
1759 txgbe_pf_host_uninit(dev);
1761 rte_free(dev->data->mac_addrs);
1762 dev->data->mac_addrs = NULL;
1764 rte_free(dev->data->hash_mac_addrs);
1765 dev->data->hash_mac_addrs = NULL;
1774 txgbe_dev_reset(struct rte_eth_dev *dev)
1778 /* When a DPDK PMD PF begin to reset PF port, it should notify all
1779 * its VF to make them align with it. The detailed notification
1780 * mechanism is PMD specific. As to txgbe PF, it is rather complex.
1781 * To avoid unexpected behavior in VF, currently reset of PF with
1782 * SR-IOV activation is not supported. It might be supported later.
1784 if (dev->data->sriov.active)
1787 ret = eth_txgbe_dev_uninit(dev);
1791 ret = eth_txgbe_dev_init(dev, NULL);
1796 #define UPDATE_QP_COUNTER_32bit(reg, last_counter, counter) \
1798 uint32_t current_counter = rd32(hw, reg); \
1799 if (current_counter < last_counter) \
1800 current_counter += 0x100000000LL; \
1801 if (!hw->offset_loaded) \
1802 last_counter = current_counter; \
1803 counter = current_counter - last_counter; \
1804 counter &= 0xFFFFFFFFLL; \
1807 #define UPDATE_QP_COUNTER_36bit(reg_lsb, reg_msb, last_counter, counter) \
1809 uint64_t current_counter_lsb = rd32(hw, reg_lsb); \
1810 uint64_t current_counter_msb = rd32(hw, reg_msb); \
1811 uint64_t current_counter = (current_counter_msb << 32) | \
1812 current_counter_lsb; \
1813 if (current_counter < last_counter) \
1814 current_counter += 0x1000000000LL; \
1815 if (!hw->offset_loaded) \
1816 last_counter = current_counter; \
1817 counter = current_counter - last_counter; \
1818 counter &= 0xFFFFFFFFFLL; \
1822 txgbe_read_stats_registers(struct txgbe_hw *hw,
1823 struct txgbe_hw_stats *hw_stats)
1828 for (i = 0; i < hw->nb_rx_queues; i++) {
1829 UPDATE_QP_COUNTER_32bit(TXGBE_QPRXPKT(i),
1830 hw->qp_last[i].rx_qp_packets,
1831 hw_stats->qp[i].rx_qp_packets);
1832 UPDATE_QP_COUNTER_36bit(TXGBE_QPRXOCTL(i), TXGBE_QPRXOCTH(i),
1833 hw->qp_last[i].rx_qp_bytes,
1834 hw_stats->qp[i].rx_qp_bytes);
1835 UPDATE_QP_COUNTER_32bit(TXGBE_QPRXMPKT(i),
1836 hw->qp_last[i].rx_qp_mc_packets,
1837 hw_stats->qp[i].rx_qp_mc_packets);
1840 for (i = 0; i < hw->nb_tx_queues; i++) {
1841 UPDATE_QP_COUNTER_32bit(TXGBE_QPTXPKT(i),
1842 hw->qp_last[i].tx_qp_packets,
1843 hw_stats->qp[i].tx_qp_packets);
1844 UPDATE_QP_COUNTER_36bit(TXGBE_QPTXOCTL(i), TXGBE_QPTXOCTH(i),
1845 hw->qp_last[i].tx_qp_bytes,
1846 hw_stats->qp[i].tx_qp_bytes);
1849 for (i = 0; i < TXGBE_MAX_UP; i++) {
1850 hw_stats->up[i].rx_up_xon_packets +=
1851 rd32(hw, TXGBE_PBRXUPXON(i));
1852 hw_stats->up[i].rx_up_xoff_packets +=
1853 rd32(hw, TXGBE_PBRXUPXOFF(i));
1854 hw_stats->up[i].tx_up_xon_packets +=
1855 rd32(hw, TXGBE_PBTXUPXON(i));
1856 hw_stats->up[i].tx_up_xoff_packets +=
1857 rd32(hw, TXGBE_PBTXUPXOFF(i));
1858 hw_stats->up[i].tx_up_xon2off_packets +=
1859 rd32(hw, TXGBE_PBTXUPOFF(i));
1860 hw_stats->up[i].rx_up_dropped +=
1861 rd32(hw, TXGBE_PBRXMISS(i));
1863 hw_stats->rx_xon_packets += rd32(hw, TXGBE_PBRXLNKXON);
1864 hw_stats->rx_xoff_packets += rd32(hw, TXGBE_PBRXLNKXOFF);
1865 hw_stats->tx_xon_packets += rd32(hw, TXGBE_PBTXLNKXON);
1866 hw_stats->tx_xoff_packets += rd32(hw, TXGBE_PBTXLNKXOFF);
1869 hw_stats->rx_packets += rd32(hw, TXGBE_DMARXPKT);
1870 hw_stats->tx_packets += rd32(hw, TXGBE_DMATXPKT);
1872 hw_stats->rx_bytes += rd64(hw, TXGBE_DMARXOCTL);
1873 hw_stats->tx_bytes += rd64(hw, TXGBE_DMATXOCTL);
1874 hw_stats->rx_drop_packets += rd32(hw, TXGBE_PBRXDROP);
1877 hw_stats->rx_crc_errors += rd64(hw, TXGBE_MACRXERRCRCL);
1878 hw_stats->rx_multicast_packets += rd64(hw, TXGBE_MACRXMPKTL);
1879 hw_stats->tx_multicast_packets += rd64(hw, TXGBE_MACTXMPKTL);
1881 hw_stats->rx_total_packets += rd64(hw, TXGBE_MACRXPKTL);
1882 hw_stats->tx_total_packets += rd64(hw, TXGBE_MACTXPKTL);
1883 hw_stats->rx_total_bytes += rd64(hw, TXGBE_MACRXGBOCTL);
1885 hw_stats->rx_broadcast_packets += rd64(hw, TXGBE_MACRXOCTL);
1886 hw_stats->tx_broadcast_packets += rd32(hw, TXGBE_MACTXOCTL);
1888 hw_stats->rx_size_64_packets += rd64(hw, TXGBE_MACRX1TO64L);
1889 hw_stats->rx_size_65_to_127_packets += rd64(hw, TXGBE_MACRX65TO127L);
1890 hw_stats->rx_size_128_to_255_packets += rd64(hw, TXGBE_MACRX128TO255L);
1891 hw_stats->rx_size_256_to_511_packets += rd64(hw, TXGBE_MACRX256TO511L);
1892 hw_stats->rx_size_512_to_1023_packets +=
1893 rd64(hw, TXGBE_MACRX512TO1023L);
1894 hw_stats->rx_size_1024_to_max_packets +=
1895 rd64(hw, TXGBE_MACRX1024TOMAXL);
1896 hw_stats->tx_size_64_packets += rd64(hw, TXGBE_MACTX1TO64L);
1897 hw_stats->tx_size_65_to_127_packets += rd64(hw, TXGBE_MACTX65TO127L);
1898 hw_stats->tx_size_128_to_255_packets += rd64(hw, TXGBE_MACTX128TO255L);
1899 hw_stats->tx_size_256_to_511_packets += rd64(hw, TXGBE_MACTX256TO511L);
1900 hw_stats->tx_size_512_to_1023_packets +=
1901 rd64(hw, TXGBE_MACTX512TO1023L);
1902 hw_stats->tx_size_1024_to_max_packets +=
1903 rd64(hw, TXGBE_MACTX1024TOMAXL);
1905 hw_stats->rx_undersize_errors += rd64(hw, TXGBE_MACRXERRLENL);
1906 hw_stats->rx_oversize_errors += rd32(hw, TXGBE_MACRXOVERSIZE);
1907 hw_stats->rx_jabber_errors += rd32(hw, TXGBE_MACRXJABBER);
1910 hw_stats->mng_bmc2host_packets = rd32(hw, TXGBE_MNGBMC2OS);
1911 hw_stats->mng_host2bmc_packets = rd32(hw, TXGBE_MNGOS2BMC);
1912 hw_stats->rx_management_packets = rd32(hw, TXGBE_DMARXMNG);
1913 hw_stats->tx_management_packets = rd32(hw, TXGBE_DMATXMNG);
1916 hw_stats->rx_fcoe_crc_errors += rd32(hw, TXGBE_FCOECRC);
1917 hw_stats->rx_fcoe_mbuf_allocation_errors += rd32(hw, TXGBE_FCOELAST);
1918 hw_stats->rx_fcoe_dropped += rd32(hw, TXGBE_FCOERPDC);
1919 hw_stats->rx_fcoe_packets += rd32(hw, TXGBE_FCOEPRC);
1920 hw_stats->tx_fcoe_packets += rd32(hw, TXGBE_FCOEPTC);
1921 hw_stats->rx_fcoe_bytes += rd32(hw, TXGBE_FCOEDWRC);
1922 hw_stats->tx_fcoe_bytes += rd32(hw, TXGBE_FCOEDWTC);
1924 /* Flow Director Stats */
1925 hw_stats->flow_director_matched_filters += rd32(hw, TXGBE_FDIRMATCH);
1926 hw_stats->flow_director_missed_filters += rd32(hw, TXGBE_FDIRMISS);
1927 hw_stats->flow_director_added_filters +=
1928 TXGBE_FDIRUSED_ADD(rd32(hw, TXGBE_FDIRUSED));
1929 hw_stats->flow_director_removed_filters +=
1930 TXGBE_FDIRUSED_REM(rd32(hw, TXGBE_FDIRUSED));
1931 hw_stats->flow_director_filter_add_errors +=
1932 TXGBE_FDIRFAIL_ADD(rd32(hw, TXGBE_FDIRFAIL));
1933 hw_stats->flow_director_filter_remove_errors +=
1934 TXGBE_FDIRFAIL_REM(rd32(hw, TXGBE_FDIRFAIL));
1937 hw_stats->tx_macsec_pkts_untagged += rd32(hw, TXGBE_LSECTX_UTPKT);
1938 hw_stats->tx_macsec_pkts_encrypted +=
1939 rd32(hw, TXGBE_LSECTX_ENCPKT);
1940 hw_stats->tx_macsec_pkts_protected +=
1941 rd32(hw, TXGBE_LSECTX_PROTPKT);
1942 hw_stats->tx_macsec_octets_encrypted +=
1943 rd32(hw, TXGBE_LSECTX_ENCOCT);
1944 hw_stats->tx_macsec_octets_protected +=
1945 rd32(hw, TXGBE_LSECTX_PROTOCT);
1946 hw_stats->rx_macsec_pkts_untagged += rd32(hw, TXGBE_LSECRX_UTPKT);
1947 hw_stats->rx_macsec_pkts_badtag += rd32(hw, TXGBE_LSECRX_BTPKT);
1948 hw_stats->rx_macsec_pkts_nosci += rd32(hw, TXGBE_LSECRX_NOSCIPKT);
1949 hw_stats->rx_macsec_pkts_unknownsci += rd32(hw, TXGBE_LSECRX_UNSCIPKT);
1950 hw_stats->rx_macsec_octets_decrypted += rd32(hw, TXGBE_LSECRX_DECOCT);
1951 hw_stats->rx_macsec_octets_validated += rd32(hw, TXGBE_LSECRX_VLDOCT);
1952 hw_stats->rx_macsec_sc_pkts_unchecked +=
1953 rd32(hw, TXGBE_LSECRX_UNCHKPKT);
1954 hw_stats->rx_macsec_sc_pkts_delayed += rd32(hw, TXGBE_LSECRX_DLYPKT);
1955 hw_stats->rx_macsec_sc_pkts_late += rd32(hw, TXGBE_LSECRX_LATEPKT);
1956 for (i = 0; i < 2; i++) {
1957 hw_stats->rx_macsec_sa_pkts_ok +=
1958 rd32(hw, TXGBE_LSECRX_OKPKT(i));
1959 hw_stats->rx_macsec_sa_pkts_invalid +=
1960 rd32(hw, TXGBE_LSECRX_INVPKT(i));
1961 hw_stats->rx_macsec_sa_pkts_notvalid +=
1962 rd32(hw, TXGBE_LSECRX_BADPKT(i));
1964 hw_stats->rx_macsec_sa_pkts_unusedsa +=
1965 rd32(hw, TXGBE_LSECRX_INVSAPKT);
1966 hw_stats->rx_macsec_sa_pkts_notusingsa +=
1967 rd32(hw, TXGBE_LSECRX_BADSAPKT);
1969 hw_stats->rx_total_missed_packets = 0;
1970 for (i = 0; i < TXGBE_MAX_UP; i++) {
1971 hw_stats->rx_total_missed_packets +=
1972 hw_stats->up[i].rx_up_dropped;
1977 txgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1979 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
1980 struct txgbe_hw_stats *hw_stats = TXGBE_DEV_STATS(dev);
1981 struct txgbe_stat_mappings *stat_mappings =
1982 TXGBE_DEV_STAT_MAPPINGS(dev);
1985 txgbe_read_stats_registers(hw, hw_stats);
1990 /* Fill out the rte_eth_stats statistics structure */
1991 stats->ipackets = hw_stats->rx_packets;
1992 stats->ibytes = hw_stats->rx_bytes;
1993 stats->opackets = hw_stats->tx_packets;
1994 stats->obytes = hw_stats->tx_bytes;
1996 memset(&stats->q_ipackets, 0, sizeof(stats->q_ipackets));
1997 memset(&stats->q_opackets, 0, sizeof(stats->q_opackets));
1998 memset(&stats->q_ibytes, 0, sizeof(stats->q_ibytes));
1999 memset(&stats->q_obytes, 0, sizeof(stats->q_obytes));
2000 memset(&stats->q_errors, 0, sizeof(stats->q_errors));
2001 for (i = 0; i < TXGBE_MAX_QP; i++) {
2002 uint32_t n = i / NB_QMAP_FIELDS_PER_QSM_REG;
2003 uint32_t offset = (i % NB_QMAP_FIELDS_PER_QSM_REG) * 8;
2006 q_map = (stat_mappings->rqsm[n] >> offset)
2007 & QMAP_FIELD_RESERVED_BITS_MASK;
2008 j = (q_map < RTE_ETHDEV_QUEUE_STAT_CNTRS
2009 ? q_map : q_map % RTE_ETHDEV_QUEUE_STAT_CNTRS);
2010 stats->q_ipackets[j] += hw_stats->qp[i].rx_qp_packets;
2011 stats->q_ibytes[j] += hw_stats->qp[i].rx_qp_bytes;
2013 q_map = (stat_mappings->tqsm[n] >> offset)
2014 & QMAP_FIELD_RESERVED_BITS_MASK;
2015 j = (q_map < RTE_ETHDEV_QUEUE_STAT_CNTRS
2016 ? q_map : q_map % RTE_ETHDEV_QUEUE_STAT_CNTRS);
2017 stats->q_opackets[j] += hw_stats->qp[i].tx_qp_packets;
2018 stats->q_obytes[j] += hw_stats->qp[i].tx_qp_bytes;
2022 stats->imissed = hw_stats->rx_total_missed_packets;
2023 stats->ierrors = hw_stats->rx_crc_errors +
2024 hw_stats->rx_mac_short_packet_dropped +
2025 hw_stats->rx_length_errors +
2026 hw_stats->rx_undersize_errors +
2027 hw_stats->rx_oversize_errors +
2028 hw_stats->rx_drop_packets +
2029 hw_stats->rx_illegal_byte_errors +
2030 hw_stats->rx_error_bytes +
2031 hw_stats->rx_fragment_errors +
2032 hw_stats->rx_fcoe_crc_errors +
2033 hw_stats->rx_fcoe_mbuf_allocation_errors;
2041 txgbe_dev_stats_reset(struct rte_eth_dev *dev)
2043 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2044 struct txgbe_hw_stats *hw_stats = TXGBE_DEV_STATS(dev);
2046 /* HW registers are cleared on read */
2047 hw->offset_loaded = 0;
2048 txgbe_dev_stats_get(dev, NULL);
2049 hw->offset_loaded = 1;
2051 /* Reset software totals */
2052 memset(hw_stats, 0, sizeof(*hw_stats));
2057 /* This function calculates the number of xstats based on the current config */
2059 txgbe_xstats_calc_num(struct rte_eth_dev *dev)
2061 int nb_queues = max(dev->data->nb_rx_queues, dev->data->nb_tx_queues);
2062 return TXGBE_NB_HW_STATS +
2063 TXGBE_NB_UP_STATS * TXGBE_MAX_UP +
2064 TXGBE_NB_QP_STATS * nb_queues;
2068 txgbe_get_name_by_id(uint32_t id, char *name, uint32_t size)
2072 /* Extended stats from txgbe_hw_stats */
2073 if (id < TXGBE_NB_HW_STATS) {
2074 snprintf(name, size, "[hw]%s",
2075 rte_txgbe_stats_strings[id].name);
2078 id -= TXGBE_NB_HW_STATS;
2080 /* Priority Stats */
2081 if (id < TXGBE_NB_UP_STATS * TXGBE_MAX_UP) {
2082 nb = id / TXGBE_NB_UP_STATS;
2083 st = id % TXGBE_NB_UP_STATS;
2084 snprintf(name, size, "[p%u]%s", nb,
2085 rte_txgbe_up_strings[st].name);
2088 id -= TXGBE_NB_UP_STATS * TXGBE_MAX_UP;
2091 if (id < TXGBE_NB_QP_STATS * TXGBE_MAX_QP) {
2092 nb = id / TXGBE_NB_QP_STATS;
2093 st = id % TXGBE_NB_QP_STATS;
2094 snprintf(name, size, "[q%u]%s", nb,
2095 rte_txgbe_qp_strings[st].name);
2098 id -= TXGBE_NB_QP_STATS * TXGBE_MAX_QP;
2100 return -(int)(id + 1);
2104 txgbe_get_offset_by_id(uint32_t id, uint32_t *offset)
2108 /* Extended stats from txgbe_hw_stats */
2109 if (id < TXGBE_NB_HW_STATS) {
2110 *offset = rte_txgbe_stats_strings[id].offset;
2113 id -= TXGBE_NB_HW_STATS;
2115 /* Priority Stats */
2116 if (id < TXGBE_NB_UP_STATS * TXGBE_MAX_UP) {
2117 nb = id / TXGBE_NB_UP_STATS;
2118 st = id % TXGBE_NB_UP_STATS;
2119 *offset = rte_txgbe_up_strings[st].offset +
2120 nb * (TXGBE_NB_UP_STATS * sizeof(uint64_t));
2123 id -= TXGBE_NB_UP_STATS * TXGBE_MAX_UP;
2126 if (id < TXGBE_NB_QP_STATS * TXGBE_MAX_QP) {
2127 nb = id / TXGBE_NB_QP_STATS;
2128 st = id % TXGBE_NB_QP_STATS;
2129 *offset = rte_txgbe_qp_strings[st].offset +
2130 nb * (TXGBE_NB_QP_STATS * sizeof(uint64_t));
2133 id -= TXGBE_NB_QP_STATS * TXGBE_MAX_QP;
2135 return -(int)(id + 1);
2138 static int txgbe_dev_xstats_get_names(struct rte_eth_dev *dev,
2139 struct rte_eth_xstat_name *xstats_names, unsigned int limit)
2141 unsigned int i, count;
2143 count = txgbe_xstats_calc_num(dev);
2144 if (xstats_names == NULL)
2147 /* Note: limit >= cnt_stats checked upstream
2148 * in rte_eth_xstats_names()
2150 limit = min(limit, count);
2152 /* Extended stats from txgbe_hw_stats */
2153 for (i = 0; i < limit; i++) {
2154 if (txgbe_get_name_by_id(i, xstats_names[i].name,
2155 sizeof(xstats_names[i].name))) {
2156 PMD_INIT_LOG(WARNING, "id value %d isn't valid", i);
2164 static int txgbe_dev_xstats_get_names_by_id(struct rte_eth_dev *dev,
2165 struct rte_eth_xstat_name *xstats_names,
2166 const uint64_t *ids,
2172 return txgbe_dev_xstats_get_names(dev, xstats_names, limit);
2174 for (i = 0; i < limit; i++) {
2175 if (txgbe_get_name_by_id(ids[i], xstats_names[i].name,
2176 sizeof(xstats_names[i].name))) {
2177 PMD_INIT_LOG(WARNING, "id value %d isn't valid", i);
2186 txgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2189 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2190 struct txgbe_hw_stats *hw_stats = TXGBE_DEV_STATS(dev);
2191 unsigned int i, count;
2193 txgbe_read_stats_registers(hw, hw_stats);
2195 /* If this is a reset xstats is NULL, and we have cleared the
2196 * registers by reading them.
2198 count = txgbe_xstats_calc_num(dev);
2202 limit = min(limit, txgbe_xstats_calc_num(dev));
2204 /* Extended stats from txgbe_hw_stats */
2205 for (i = 0; i < limit; i++) {
2206 uint32_t offset = 0;
2208 if (txgbe_get_offset_by_id(i, &offset)) {
2209 PMD_INIT_LOG(WARNING, "id value %d isn't valid", i);
2212 xstats[i].value = *(uint64_t *)(((char *)hw_stats) + offset);
2220 txgbe_dev_xstats_get_(struct rte_eth_dev *dev, uint64_t *values,
2223 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2224 struct txgbe_hw_stats *hw_stats = TXGBE_DEV_STATS(dev);
2225 unsigned int i, count;
2227 txgbe_read_stats_registers(hw, hw_stats);
2229 /* If this is a reset xstats is NULL, and we have cleared the
2230 * registers by reading them.
2232 count = txgbe_xstats_calc_num(dev);
2236 limit = min(limit, txgbe_xstats_calc_num(dev));
2238 /* Extended stats from txgbe_hw_stats */
2239 for (i = 0; i < limit; i++) {
2242 if (txgbe_get_offset_by_id(i, &offset)) {
2243 PMD_INIT_LOG(WARNING, "id value %d isn't valid", i);
2246 values[i] = *(uint64_t *)(((char *)hw_stats) + offset);
2253 txgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
2254 uint64_t *values, unsigned int limit)
2256 struct txgbe_hw_stats *hw_stats = TXGBE_DEV_STATS(dev);
2260 return txgbe_dev_xstats_get_(dev, values, limit);
2262 for (i = 0; i < limit; i++) {
2265 if (txgbe_get_offset_by_id(ids[i], &offset)) {
2266 PMD_INIT_LOG(WARNING, "id value %d isn't valid", i);
2269 values[i] = *(uint64_t *)(((char *)hw_stats) + offset);
2276 txgbe_dev_xstats_reset(struct rte_eth_dev *dev)
2278 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2279 struct txgbe_hw_stats *hw_stats = TXGBE_DEV_STATS(dev);
2281 /* HW registers are cleared on read */
2282 hw->offset_loaded = 0;
2283 txgbe_read_stats_registers(hw, hw_stats);
2284 hw->offset_loaded = 1;
2286 /* Reset software totals */
2287 memset(hw_stats, 0, sizeof(*hw_stats));
2293 txgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
2295 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2296 u16 eeprom_verh, eeprom_verl;
2300 hw->rom.readw_sw(hw, TXGBE_EEPROM_VERSION_H, &eeprom_verh);
2301 hw->rom.readw_sw(hw, TXGBE_EEPROM_VERSION_L, &eeprom_verl);
2303 etrack_id = (eeprom_verh << 16) | eeprom_verl;
2304 ret = snprintf(fw_version, fw_size, "0x%08x", etrack_id);
2306 ret += 1; /* add the size of '\0' */
2307 if (fw_size < (u32)ret)
2314 txgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2316 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2317 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2319 dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
2320 dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
2321 dev_info->min_rx_bufsize = 1024;
2322 dev_info->max_rx_pktlen = 15872;
2323 dev_info->max_mac_addrs = hw->mac.num_rar_entries;
2324 dev_info->max_hash_mac_addrs = TXGBE_VMDQ_NUM_UC_MAC;
2325 dev_info->max_vfs = pci_dev->max_vfs;
2326 dev_info->max_vmdq_pools = ETH_64_POOLS;
2327 dev_info->vmdq_queue_num = dev_info->max_rx_queues;
2328 dev_info->rx_queue_offload_capa = txgbe_get_rx_queue_offloads(dev);
2329 dev_info->rx_offload_capa = (txgbe_get_rx_port_offloads(dev) |
2330 dev_info->rx_queue_offload_capa);
2331 dev_info->tx_queue_offload_capa = txgbe_get_tx_queue_offloads(dev);
2332 dev_info->tx_offload_capa = txgbe_get_tx_port_offloads(dev);
2334 dev_info->default_rxconf = (struct rte_eth_rxconf) {
2336 .pthresh = TXGBE_DEFAULT_RX_PTHRESH,
2337 .hthresh = TXGBE_DEFAULT_RX_HTHRESH,
2338 .wthresh = TXGBE_DEFAULT_RX_WTHRESH,
2340 .rx_free_thresh = TXGBE_DEFAULT_RX_FREE_THRESH,
2345 dev_info->default_txconf = (struct rte_eth_txconf) {
2347 .pthresh = TXGBE_DEFAULT_TX_PTHRESH,
2348 .hthresh = TXGBE_DEFAULT_TX_HTHRESH,
2349 .wthresh = TXGBE_DEFAULT_TX_WTHRESH,
2351 .tx_free_thresh = TXGBE_DEFAULT_TX_FREE_THRESH,
2355 dev_info->rx_desc_lim = rx_desc_lim;
2356 dev_info->tx_desc_lim = tx_desc_lim;
2358 dev_info->hash_key_size = TXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
2359 dev_info->reta_size = ETH_RSS_RETA_SIZE_128;
2360 dev_info->flow_type_rss_offloads = TXGBE_RSS_OFFLOAD_ALL;
2362 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
2363 dev_info->speed_capa |= ETH_LINK_SPEED_100M;
2365 /* Driver-preferred Rx/Tx parameters */
2366 dev_info->default_rxportconf.burst_size = 32;
2367 dev_info->default_txportconf.burst_size = 32;
2368 dev_info->default_rxportconf.nb_queues = 1;
2369 dev_info->default_txportconf.nb_queues = 1;
2370 dev_info->default_rxportconf.ring_size = 256;
2371 dev_info->default_txportconf.ring_size = 256;
2377 txgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev)
2379 if (dev->rx_pkt_burst == txgbe_recv_pkts ||
2380 dev->rx_pkt_burst == txgbe_recv_pkts_lro_single_alloc ||
2381 dev->rx_pkt_burst == txgbe_recv_pkts_lro_bulk_alloc ||
2382 dev->rx_pkt_burst == txgbe_recv_pkts_bulk_alloc)
2383 return txgbe_get_supported_ptypes();
2389 txgbe_dev_setup_link_alarm_handler(void *param)
2391 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2392 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2393 struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);
2395 bool autoneg = false;
2397 speed = hw->phy.autoneg_advertised;
2399 hw->mac.get_link_capabilities(hw, &speed, &autoneg);
2401 hw->mac.setup_link(hw, speed, true);
2403 intr->flags &= ~TXGBE_FLAG_NEED_LINK_CONFIG;
2406 /* return 0 means link status changed, -1 means not changed */
2408 txgbe_dev_link_update_share(struct rte_eth_dev *dev,
2409 int wait_to_complete)
2411 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2412 struct rte_eth_link link;
2413 u32 link_speed = TXGBE_LINK_SPEED_UNKNOWN;
2414 struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);
2419 memset(&link, 0, sizeof(link));
2420 link.link_status = ETH_LINK_DOWN;
2421 link.link_speed = ETH_SPEED_NUM_NONE;
2422 link.link_duplex = ETH_LINK_HALF_DUPLEX;
2423 link.link_autoneg = ETH_LINK_AUTONEG;
2425 hw->mac.get_link_status = true;
2427 if (intr->flags & TXGBE_FLAG_NEED_LINK_CONFIG)
2428 return rte_eth_linkstatus_set(dev, &link);
2430 /* check if it needs to wait to complete, if lsc interrupt is enabled */
2431 if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
2434 err = hw->mac.check_link(hw, &link_speed, &link_up, wait);
2437 link.link_speed = ETH_SPEED_NUM_100M;
2438 link.link_duplex = ETH_LINK_FULL_DUPLEX;
2439 return rte_eth_linkstatus_set(dev, &link);
2443 if (hw->phy.media_type == txgbe_media_type_fiber) {
2444 intr->flags |= TXGBE_FLAG_NEED_LINK_CONFIG;
2445 rte_eal_alarm_set(10,
2446 txgbe_dev_setup_link_alarm_handler, dev);
2448 return rte_eth_linkstatus_set(dev, &link);
2451 intr->flags &= ~TXGBE_FLAG_NEED_LINK_CONFIG;
2452 link.link_status = ETH_LINK_UP;
2453 link.link_duplex = ETH_LINK_FULL_DUPLEX;
2455 switch (link_speed) {
2457 case TXGBE_LINK_SPEED_UNKNOWN:
2458 link.link_duplex = ETH_LINK_FULL_DUPLEX;
2459 link.link_speed = ETH_SPEED_NUM_100M;
2462 case TXGBE_LINK_SPEED_100M_FULL:
2463 link.link_speed = ETH_SPEED_NUM_100M;
2466 case TXGBE_LINK_SPEED_1GB_FULL:
2467 link.link_speed = ETH_SPEED_NUM_1G;
2470 case TXGBE_LINK_SPEED_2_5GB_FULL:
2471 link.link_speed = ETH_SPEED_NUM_2_5G;
2474 case TXGBE_LINK_SPEED_5GB_FULL:
2475 link.link_speed = ETH_SPEED_NUM_5G;
2478 case TXGBE_LINK_SPEED_10GB_FULL:
2479 link.link_speed = ETH_SPEED_NUM_10G;
2483 return rte_eth_linkstatus_set(dev, &link);
2487 txgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
2489 return txgbe_dev_link_update_share(dev, wait_to_complete);
2493 txgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
2495 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2498 fctrl = rd32(hw, TXGBE_PSRCTL);
2499 fctrl |= (TXGBE_PSRCTL_UCP | TXGBE_PSRCTL_MCP);
2500 wr32(hw, TXGBE_PSRCTL, fctrl);
2506 txgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
2508 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2511 fctrl = rd32(hw, TXGBE_PSRCTL);
2512 fctrl &= (~TXGBE_PSRCTL_UCP);
2513 if (dev->data->all_multicast == 1)
2514 fctrl |= TXGBE_PSRCTL_MCP;
2516 fctrl &= (~TXGBE_PSRCTL_MCP);
2517 wr32(hw, TXGBE_PSRCTL, fctrl);
2523 txgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
2525 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2528 fctrl = rd32(hw, TXGBE_PSRCTL);
2529 fctrl |= TXGBE_PSRCTL_MCP;
2530 wr32(hw, TXGBE_PSRCTL, fctrl);
2536 txgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
2538 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2541 if (dev->data->promiscuous == 1)
2542 return 0; /* must remain in all_multicast mode */
2544 fctrl = rd32(hw, TXGBE_PSRCTL);
2545 fctrl &= (~TXGBE_PSRCTL_MCP);
2546 wr32(hw, TXGBE_PSRCTL, fctrl);
2552 * It clears the interrupt causes and enables the interrupt.
2553 * It will be called once only during nic initialized.
2556 * Pointer to struct rte_eth_dev.
2558 * Enable or Disable.
2561 * - On success, zero.
2562 * - On failure, a negative value.
2565 txgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on)
2567 struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);
2569 txgbe_dev_link_status_print(dev);
2571 intr->mask_misc |= TXGBE_ICRMISC_LSC;
2573 intr->mask_misc &= ~TXGBE_ICRMISC_LSC;
2579 * It clears the interrupt causes and enables the interrupt.
2580 * It will be called once only during nic initialized.
2583 * Pointer to struct rte_eth_dev.
2586 * - On success, zero.
2587 * - On failure, a negative value.
2590 txgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
2592 struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);
2594 intr->mask[0] |= TXGBE_ICR_MASK;
2595 intr->mask[1] |= TXGBE_ICR_MASK;
2601 * It clears the interrupt causes and enables the interrupt.
2602 * It will be called once only during nic initialized.
2605 * Pointer to struct rte_eth_dev.
2608 * - On success, zero.
2609 * - On failure, a negative value.
2612 txgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev)
2614 struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);
2616 intr->mask_misc |= TXGBE_ICRMISC_LNKSEC;
2622 * It reads ICR and sets flag (TXGBE_ICRMISC_LSC) for the link_update.
2625 * Pointer to struct rte_eth_dev.
2628 * - On success, zero.
2629 * - On failure, a negative value.
2632 txgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
2635 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2636 struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);
2638 /* clear all cause mask */
2639 txgbe_disable_intr(hw);
2641 /* read-on-clear nic registers here */
2642 eicr = ((u32 *)hw->isb_mem)[TXGBE_ISB_MISC];
2643 PMD_DRV_LOG(DEBUG, "eicr %x", eicr);
2647 /* set flag for async link update */
2648 if (eicr & TXGBE_ICRMISC_LSC)
2649 intr->flags |= TXGBE_FLAG_NEED_LINK_UPDATE;
2651 if (eicr & TXGBE_ICRMISC_VFMBX)
2652 intr->flags |= TXGBE_FLAG_MAILBOX;
2654 if (eicr & TXGBE_ICRMISC_LNKSEC)
2655 intr->flags |= TXGBE_FLAG_MACSEC;
2657 if (eicr & TXGBE_ICRMISC_GPIO)
2658 intr->flags |= TXGBE_FLAG_PHY_INTERRUPT;
2664 * It gets and then prints the link status.
2667 * Pointer to struct rte_eth_dev.
2670 * - On success, zero.
2671 * - On failure, a negative value.
2674 txgbe_dev_link_status_print(struct rte_eth_dev *dev)
2676 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2677 struct rte_eth_link link;
2679 rte_eth_linkstatus_get(dev, &link);
2681 if (link.link_status) {
2682 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
2683 (int)(dev->data->port_id),
2684 (unsigned int)link.link_speed,
2685 link.link_duplex == ETH_LINK_FULL_DUPLEX ?
2686 "full-duplex" : "half-duplex");
2688 PMD_INIT_LOG(INFO, " Port %d: Link Down",
2689 (int)(dev->data->port_id));
2691 PMD_INIT_LOG(DEBUG, "PCI Address: " PCI_PRI_FMT,
2692 pci_dev->addr.domain,
2694 pci_dev->addr.devid,
2695 pci_dev->addr.function);
2699 * It executes link_update after knowing an interrupt occurred.
2702 * Pointer to struct rte_eth_dev.
2705 * - On success, zero.
2706 * - On failure, a negative value.
2709 txgbe_dev_interrupt_action(struct rte_eth_dev *dev,
2710 struct rte_intr_handle *intr_handle)
2712 struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);
2714 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2716 PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
2718 if (intr->flags & TXGBE_FLAG_MAILBOX) {
2719 txgbe_pf_mbx_process(dev);
2720 intr->flags &= ~TXGBE_FLAG_MAILBOX;
2723 if (intr->flags & TXGBE_FLAG_PHY_INTERRUPT) {
2724 hw->phy.handle_lasi(hw);
2725 intr->flags &= ~TXGBE_FLAG_PHY_INTERRUPT;
2728 if (intr->flags & TXGBE_FLAG_NEED_LINK_UPDATE) {
2729 struct rte_eth_link link;
2731 /*get the link status before link update, for predicting later*/
2732 rte_eth_linkstatus_get(dev, &link);
2734 txgbe_dev_link_update(dev, 0);
2737 if (!link.link_status)
2738 /* handle it 1 sec later, wait it being stable */
2739 timeout = TXGBE_LINK_UP_CHECK_TIMEOUT;
2740 /* likely to down */
2742 /* handle it 4 sec later, wait it being stable */
2743 timeout = TXGBE_LINK_DOWN_CHECK_TIMEOUT;
2745 txgbe_dev_link_status_print(dev);
2746 if (rte_eal_alarm_set(timeout * 1000,
2747 txgbe_dev_interrupt_delayed_handler,
2749 PMD_DRV_LOG(ERR, "Error setting alarm");
2751 /* remember original mask */
2752 intr->mask_misc_orig = intr->mask_misc;
2753 /* only disable lsc interrupt */
2754 intr->mask_misc &= ~TXGBE_ICRMISC_LSC;
2758 PMD_DRV_LOG(DEBUG, "enable intr immediately");
2759 txgbe_enable_intr(dev);
2760 rte_intr_enable(intr_handle);
2766 * Interrupt handler which shall be registered for alarm callback for delayed
2767 * handling specific interrupt to wait for the stable nic state. As the
2768 * NIC interrupt state is not stable for txgbe after link is just down,
2769 * it needs to wait 4 seconds to get the stable status.
2772 * Pointer to interrupt handle.
2774 * The address of parameter (struct rte_eth_dev *) registered before.
2780 txgbe_dev_interrupt_delayed_handler(void *param)
2782 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2783 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2784 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2785 struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);
2786 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2789 txgbe_disable_intr(hw);
2791 eicr = ((u32 *)hw->isb_mem)[TXGBE_ISB_MISC];
2792 if (eicr & TXGBE_ICRMISC_VFMBX)
2793 txgbe_pf_mbx_process(dev);
2795 if (intr->flags & TXGBE_FLAG_PHY_INTERRUPT) {
2796 hw->phy.handle_lasi(hw);
2797 intr->flags &= ~TXGBE_FLAG_PHY_INTERRUPT;
2800 if (intr->flags & TXGBE_FLAG_NEED_LINK_UPDATE) {
2801 txgbe_dev_link_update(dev, 0);
2802 intr->flags &= ~TXGBE_FLAG_NEED_LINK_UPDATE;
2803 txgbe_dev_link_status_print(dev);
2804 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC,
2808 if (intr->flags & TXGBE_FLAG_MACSEC) {
2809 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_MACSEC,
2811 intr->flags &= ~TXGBE_FLAG_MACSEC;
2814 /* restore original mask */
2815 intr->mask_misc = intr->mask_misc_orig;
2816 intr->mask_misc_orig = 0;
2818 PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
2819 txgbe_enable_intr(dev);
2820 rte_intr_enable(intr_handle);
2824 * Interrupt handler triggered by NIC for handling
2825 * specific interrupt.
2828 * Pointer to interrupt handle.
2830 * The address of parameter (struct rte_eth_dev *) registered before.
2836 txgbe_dev_interrupt_handler(void *param)
2838 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2840 txgbe_dev_interrupt_get_status(dev);
2841 txgbe_dev_interrupt_action(dev, dev->intr_handle);
2845 txgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2847 struct txgbe_hw *hw;
2853 hw = TXGBE_DEV_HW(dev);
2855 fc_conf->pause_time = hw->fc.pause_time;
2856 fc_conf->high_water = hw->fc.high_water[0];
2857 fc_conf->low_water = hw->fc.low_water[0];
2858 fc_conf->send_xon = hw->fc.send_xon;
2859 fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
2862 * Return rx_pause status according to actual setting of
2865 mflcn_reg = rd32(hw, TXGBE_RXFCCFG);
2866 if (mflcn_reg & (TXGBE_RXFCCFG_FC | TXGBE_RXFCCFG_PFC))
2872 * Return tx_pause status according to actual setting of
2875 fccfg_reg = rd32(hw, TXGBE_TXFCCFG);
2876 if (fccfg_reg & (TXGBE_TXFCCFG_FC | TXGBE_TXFCCFG_PFC))
2881 if (rx_pause && tx_pause)
2882 fc_conf->mode = RTE_FC_FULL;
2884 fc_conf->mode = RTE_FC_RX_PAUSE;
2886 fc_conf->mode = RTE_FC_TX_PAUSE;
2888 fc_conf->mode = RTE_FC_NONE;
2894 txgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2896 struct txgbe_hw *hw;
2898 uint32_t rx_buf_size;
2899 uint32_t max_high_water;
2900 enum txgbe_fc_mode rte_fcmode_2_txgbe_fcmode[] = {
2907 PMD_INIT_FUNC_TRACE();
2909 hw = TXGBE_DEV_HW(dev);
2910 rx_buf_size = rd32(hw, TXGBE_PBRXSIZE(0));
2911 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
2914 * At least reserve one Ethernet frame for watermark
2915 * high_water/low_water in kilo bytes for txgbe
2917 max_high_water = (rx_buf_size - RTE_ETHER_MAX_LEN) >> 10;
2918 if (fc_conf->high_water > max_high_water ||
2919 fc_conf->high_water < fc_conf->low_water) {
2920 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
2921 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
2925 hw->fc.requested_mode = rte_fcmode_2_txgbe_fcmode[fc_conf->mode];
2926 hw->fc.pause_time = fc_conf->pause_time;
2927 hw->fc.high_water[0] = fc_conf->high_water;
2928 hw->fc.low_water[0] = fc_conf->low_water;
2929 hw->fc.send_xon = fc_conf->send_xon;
2930 hw->fc.disable_fc_autoneg = !fc_conf->autoneg;
2932 err = txgbe_fc_enable(hw);
2934 /* Not negotiated is not an error case */
2935 if (err == 0 || err == TXGBE_ERR_FC_NOT_NEGOTIATED) {
2936 wr32m(hw, TXGBE_MACRXFLT, TXGBE_MACRXFLT_CTL_MASK,
2937 (fc_conf->mac_ctrl_frame_fwd
2938 ? TXGBE_MACRXFLT_CTL_NOPS : TXGBE_MACRXFLT_CTL_DROP));
2944 PMD_INIT_LOG(ERR, "txgbe_fc_enable = 0x%x", err);
2949 txgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
2950 struct rte_eth_pfc_conf *pfc_conf)
2953 uint32_t rx_buf_size;
2954 uint32_t max_high_water;
2956 uint8_t map[TXGBE_DCB_UP_MAX] = { 0 };
2957 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2958 struct txgbe_dcb_config *dcb_config = TXGBE_DEV_DCB_CONFIG(dev);
2960 enum txgbe_fc_mode rte_fcmode_2_txgbe_fcmode[] = {
2967 PMD_INIT_FUNC_TRACE();
2969 txgbe_dcb_unpack_map_cee(dcb_config, TXGBE_DCB_RX_CONFIG, map);
2970 tc_num = map[pfc_conf->priority];
2971 rx_buf_size = rd32(hw, TXGBE_PBRXSIZE(tc_num));
2972 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
2974 * At least reserve one Ethernet frame for watermark
2975 * high_water/low_water in kilo bytes for txgbe
2977 max_high_water = (rx_buf_size - RTE_ETHER_MAX_LEN) >> 10;
2978 if (pfc_conf->fc.high_water > max_high_water ||
2979 pfc_conf->fc.high_water <= pfc_conf->fc.low_water) {
2980 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
2981 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
2985 hw->fc.requested_mode = rte_fcmode_2_txgbe_fcmode[pfc_conf->fc.mode];
2986 hw->fc.pause_time = pfc_conf->fc.pause_time;
2987 hw->fc.send_xon = pfc_conf->fc.send_xon;
2988 hw->fc.low_water[tc_num] = pfc_conf->fc.low_water;
2989 hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
2991 err = txgbe_dcb_pfc_enable(hw, tc_num);
2993 /* Not negotiated is not an error case */
2994 if (err == 0 || err == TXGBE_ERR_FC_NOT_NEGOTIATED)
2997 PMD_INIT_LOG(ERR, "txgbe_dcb_pfc_enable = 0x%x", err);
3002 txgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
3003 struct rte_eth_rss_reta_entry64 *reta_conf,
3008 uint16_t idx, shift;
3009 struct txgbe_adapter *adapter = TXGBE_DEV_ADAPTER(dev);
3010 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3012 PMD_INIT_FUNC_TRACE();
3014 if (!txgbe_rss_update_sp(hw->mac.type)) {
3015 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this "
3020 if (reta_size != ETH_RSS_RETA_SIZE_128) {
3021 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3022 "(%d) doesn't match the number hardware can supported "
3023 "(%d)", reta_size, ETH_RSS_RETA_SIZE_128);
3027 for (i = 0; i < reta_size; i += 4) {
3028 idx = i / RTE_RETA_GROUP_SIZE;
3029 shift = i % RTE_RETA_GROUP_SIZE;
3030 mask = (uint8_t)RS64(reta_conf[idx].mask, shift, 0xF);
3034 reta = rd32a(hw, TXGBE_REG_RSSTBL, i >> 2);
3035 for (j = 0; j < 4; j++) {
3036 if (RS8(mask, j, 0x1)) {
3037 reta &= ~(MS32(8 * j, 0xFF));
3038 reta |= LS32(reta_conf[idx].reta[shift + j],
3042 wr32a(hw, TXGBE_REG_RSSTBL, i >> 2, reta);
3044 adapter->rss_reta_updated = 1;
3050 txgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
3051 struct rte_eth_rss_reta_entry64 *reta_conf,
3054 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3057 uint16_t idx, shift;
3059 PMD_INIT_FUNC_TRACE();
3061 if (reta_size != ETH_RSS_RETA_SIZE_128) {
3062 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3063 "(%d) doesn't match the number hardware can supported "
3064 "(%d)", reta_size, ETH_RSS_RETA_SIZE_128);
3068 for (i = 0; i < reta_size; i += 4) {
3069 idx = i / RTE_RETA_GROUP_SIZE;
3070 shift = i % RTE_RETA_GROUP_SIZE;
3071 mask = (uint8_t)RS64(reta_conf[idx].mask, shift, 0xF);
3075 reta = rd32a(hw, TXGBE_REG_RSSTBL, i >> 2);
3076 for (j = 0; j < 4; j++) {
3077 if (RS8(mask, j, 0x1))
3078 reta_conf[idx].reta[shift + j] =
3079 (uint16_t)RS32(reta, 8 * j, 0xFF);
3087 txgbe_add_rar(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
3088 uint32_t index, uint32_t pool)
3090 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3091 uint32_t enable_addr = 1;
3093 return txgbe_set_rar(hw, index, mac_addr->addr_bytes,
3098 txgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
3100 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3102 txgbe_clear_rar(hw, index);
3106 txgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *addr)
3108 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3110 txgbe_remove_rar(dev, 0);
3111 txgbe_add_rar(dev, addr, 0, pci_dev->max_vfs);
3117 txgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
3119 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3120 struct rte_eth_dev_info dev_info;
3121 uint32_t frame_size = mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN;
3122 struct rte_eth_dev_data *dev_data = dev->data;
3125 ret = txgbe_dev_info_get(dev, &dev_info);
3129 /* check that mtu is within the allowed range */
3130 if (mtu < RTE_ETHER_MIN_MTU || frame_size > dev_info.max_rx_pktlen)
3133 /* If device is started, refuse mtu that requires the support of
3134 * scattered packets when this feature has not been enabled before.
3136 if (dev_data->dev_started && !dev_data->scattered_rx &&
3137 (frame_size + 2 * TXGBE_VLAN_TAG_SIZE >
3138 dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
3139 PMD_INIT_LOG(ERR, "Stop port first.");
3143 /* update max frame size */
3144 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
3147 wr32m(hw, TXGBE_FRMSZ, TXGBE_FRMSZ_MAX_MASK,
3148 TXGBE_FRAME_SIZE_MAX);
3150 wr32m(hw, TXGBE_FRMSZ, TXGBE_FRMSZ_MAX_MASK,
3151 TXGBE_FRMSZ_MAX(frame_size));
3157 txgbe_uta_vector(struct txgbe_hw *hw, struct rte_ether_addr *uc_addr)
3159 uint32_t vector = 0;
3161 switch (hw->mac.mc_filter_type) {
3162 case 0: /* use bits [47:36] of the address */
3163 vector = ((uc_addr->addr_bytes[4] >> 4) |
3164 (((uint16_t)uc_addr->addr_bytes[5]) << 4));
3166 case 1: /* use bits [46:35] of the address */
3167 vector = ((uc_addr->addr_bytes[4] >> 3) |
3168 (((uint16_t)uc_addr->addr_bytes[5]) << 5));
3170 case 2: /* use bits [45:34] of the address */
3171 vector = ((uc_addr->addr_bytes[4] >> 2) |
3172 (((uint16_t)uc_addr->addr_bytes[5]) << 6));
3174 case 3: /* use bits [43:32] of the address */
3175 vector = ((uc_addr->addr_bytes[4]) |
3176 (((uint16_t)uc_addr->addr_bytes[5]) << 8));
3178 default: /* Invalid mc_filter_type */
3182 /* vector can only be 12-bits or boundary will be exceeded */
3188 txgbe_uc_hash_table_set(struct rte_eth_dev *dev,
3189 struct rte_ether_addr *mac_addr, uint8_t on)
3197 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3198 struct txgbe_uta_info *uta_info = TXGBE_DEV_UTA_INFO(dev);
3200 /* The UTA table only exists on pf hardware */
3201 if (hw->mac.type < txgbe_mac_raptor)
3204 vector = txgbe_uta_vector(hw, mac_addr);
3205 uta_idx = (vector >> 5) & 0x7F;
3206 uta_mask = 0x1UL << (vector & 0x1F);
3208 if (!!on == !!(uta_info->uta_shadow[uta_idx] & uta_mask))
3211 reg_val = rd32(hw, TXGBE_UCADDRTBL(uta_idx));
3213 uta_info->uta_in_use++;
3214 reg_val |= uta_mask;
3215 uta_info->uta_shadow[uta_idx] |= uta_mask;
3217 uta_info->uta_in_use--;
3218 reg_val &= ~uta_mask;
3219 uta_info->uta_shadow[uta_idx] &= ~uta_mask;
3222 wr32(hw, TXGBE_UCADDRTBL(uta_idx), reg_val);
3224 psrctl = rd32(hw, TXGBE_PSRCTL);
3225 if (uta_info->uta_in_use > 0)
3226 psrctl |= TXGBE_PSRCTL_UCHFENA;
3228 psrctl &= ~TXGBE_PSRCTL_UCHFENA;
3230 psrctl &= ~TXGBE_PSRCTL_ADHF12_MASK;
3231 psrctl |= TXGBE_PSRCTL_ADHF12(hw->mac.mc_filter_type);
3232 wr32(hw, TXGBE_PSRCTL, psrctl);
3238 txgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
3240 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3241 struct txgbe_uta_info *uta_info = TXGBE_DEV_UTA_INFO(dev);
3245 /* The UTA table only exists on pf hardware */
3246 if (hw->mac.type < txgbe_mac_raptor)
3250 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
3251 uta_info->uta_shadow[i] = ~0;
3252 wr32(hw, TXGBE_UCADDRTBL(i), ~0);
3255 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
3256 uta_info->uta_shadow[i] = 0;
3257 wr32(hw, TXGBE_UCADDRTBL(i), 0);
3261 psrctl = rd32(hw, TXGBE_PSRCTL);
3263 psrctl |= TXGBE_PSRCTL_UCHFENA;
3265 psrctl &= ~TXGBE_PSRCTL_UCHFENA;
3267 psrctl &= ~TXGBE_PSRCTL_ADHF12_MASK;
3268 psrctl |= TXGBE_PSRCTL_ADHF12(hw->mac.mc_filter_type);
3269 wr32(hw, TXGBE_PSRCTL, psrctl);
3275 txgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
3277 uint32_t new_val = orig_val;
3279 if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
3280 new_val |= TXGBE_POOLETHCTL_UTA;
3281 if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
3282 new_val |= TXGBE_POOLETHCTL_MCHA;
3283 if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
3284 new_val |= TXGBE_POOLETHCTL_UCHA;
3285 if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
3286 new_val |= TXGBE_POOLETHCTL_BCA;
3287 if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
3288 new_val |= TXGBE_POOLETHCTL_MCP;
3294 txgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
3296 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3297 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3299 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3301 if (queue_id < 32) {
3302 mask = rd32(hw, TXGBE_IMS(0));
3303 mask &= (1 << queue_id);
3304 wr32(hw, TXGBE_IMS(0), mask);
3305 } else if (queue_id < 64) {
3306 mask = rd32(hw, TXGBE_IMS(1));
3307 mask &= (1 << (queue_id - 32));
3308 wr32(hw, TXGBE_IMS(1), mask);
3310 rte_intr_enable(intr_handle);
3316 txgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
3319 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3321 if (queue_id < 32) {
3322 mask = rd32(hw, TXGBE_IMS(0));
3323 mask &= ~(1 << queue_id);
3324 wr32(hw, TXGBE_IMS(0), mask);
3325 } else if (queue_id < 64) {
3326 mask = rd32(hw, TXGBE_IMS(1));
3327 mask &= ~(1 << (queue_id - 32));
3328 wr32(hw, TXGBE_IMS(1), mask);
3335 * set the IVAR registers, mapping interrupt causes to vectors
3337 * pointer to txgbe_hw struct
3339 * 0 for Rx, 1 for Tx, -1 for other causes
3341 * queue to map the corresponding interrupt to
3343 * the vector to map to the corresponding queue
3346 txgbe_set_ivar_map(struct txgbe_hw *hw, int8_t direction,
3347 uint8_t queue, uint8_t msix_vector)
3351 if (direction == -1) {
3353 msix_vector |= TXGBE_IVARMISC_VLD;
3355 tmp = rd32(hw, TXGBE_IVARMISC);
3356 tmp &= ~(0xFF << idx);
3357 tmp |= (msix_vector << idx);
3358 wr32(hw, TXGBE_IVARMISC, tmp);
3360 /* rx or tx causes */
3361 /* Workround for ICR lost */
3362 idx = ((16 * (queue & 1)) + (8 * direction));
3363 tmp = rd32(hw, TXGBE_IVAR(queue >> 1));
3364 tmp &= ~(0xFF << idx);
3365 tmp |= (msix_vector << idx);
3366 wr32(hw, TXGBE_IVAR(queue >> 1), tmp);
3371 * Sets up the hardware to properly generate MSI-X interrupts
3373 * board private structure
3376 txgbe_configure_msix(struct rte_eth_dev *dev)
3378 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3379 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3380 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3381 uint32_t queue_id, base = TXGBE_MISC_VEC_ID;
3382 uint32_t vec = TXGBE_MISC_VEC_ID;
3385 /* won't configure msix register if no mapping is done
3386 * between intr vector and event fd
3387 * but if misx has been enabled already, need to configure
3388 * auto clean, auto mask and throttling.
3390 gpie = rd32(hw, TXGBE_GPIE);
3391 if (!rte_intr_dp_is_en(intr_handle) &&
3392 !(gpie & TXGBE_GPIE_MSIX))
3395 if (rte_intr_allow_others(intr_handle)) {
3396 base = TXGBE_RX_VEC_START;
3400 /* setup GPIE for MSI-x mode */
3401 gpie = rd32(hw, TXGBE_GPIE);
3402 gpie |= TXGBE_GPIE_MSIX;
3403 wr32(hw, TXGBE_GPIE, gpie);
3405 /* Populate the IVAR table and set the ITR values to the
3406 * corresponding register.
3408 if (rte_intr_dp_is_en(intr_handle)) {
3409 for (queue_id = 0; queue_id < dev->data->nb_rx_queues;
3411 /* by default, 1:1 mapping */
3412 txgbe_set_ivar_map(hw, 0, queue_id, vec);
3413 intr_handle->intr_vec[queue_id] = vec;
3414 if (vec < base + intr_handle->nb_efd - 1)
3418 txgbe_set_ivar_map(hw, -1, 1, TXGBE_MISC_VEC_ID);
3420 wr32(hw, TXGBE_ITR(TXGBE_MISC_VEC_ID),
3421 TXGBE_ITR_IVAL_10G(TXGBE_QUEUE_ITR_INTERVAL_DEFAULT)
3426 txgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
3427 uint16_t queue_idx, uint16_t tx_rate)
3429 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3432 if (queue_idx >= hw->mac.max_tx_queues)
3436 bcnrc_val = TXGBE_ARBTXRATE_MAX(tx_rate);
3437 bcnrc_val |= TXGBE_ARBTXRATE_MIN(tx_rate / 2);
3443 * Set global transmit compensation time to the MMW_SIZE in ARBTXMMW
3444 * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported.
3446 wr32(hw, TXGBE_ARBTXMMW, 0x14);
3448 /* Set ARBTXRATE of queue X */
3449 wr32(hw, TXGBE_ARBPOOLIDX, queue_idx);
3450 wr32(hw, TXGBE_ARBTXRATE, bcnrc_val);
3457 txgbe_dev_addr_list_itr(__rte_unused struct txgbe_hw *hw,
3458 u8 **mc_addr_ptr, u32 *vmdq)
3463 mc_addr = *mc_addr_ptr;
3464 *mc_addr_ptr = (mc_addr + sizeof(struct rte_ether_addr));
3469 txgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
3470 struct rte_ether_addr *mc_addr_set,
3471 uint32_t nb_mc_addr)
3473 struct txgbe_hw *hw;
3476 hw = TXGBE_DEV_HW(dev);
3477 mc_addr_list = (u8 *)mc_addr_set;
3478 return txgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
3479 txgbe_dev_addr_list_itr, TRUE);
3483 txgbe_get_reg_length(struct rte_eth_dev *dev __rte_unused)
3487 const struct reg_info *reg_group;
3488 const struct reg_info **reg_set = txgbe_regs_others;
3490 while ((reg_group = reg_set[g_ind++]))
3491 count += txgbe_regs_group_count(reg_group);
3497 txgbe_get_regs(struct rte_eth_dev *dev,
3498 struct rte_dev_reg_info *regs)
3500 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3501 uint32_t *data = regs->data;
3504 const struct reg_info *reg_group;
3505 const struct reg_info **reg_set = txgbe_regs_others;
3508 regs->length = txgbe_get_reg_length(dev);
3509 regs->width = sizeof(uint32_t);
3513 /* Support only full register dump */
3514 if (regs->length == 0 ||
3515 regs->length == (uint32_t)txgbe_get_reg_length(dev)) {
3516 regs->version = hw->mac.type << 24 |
3517 hw->revision_id << 16 |
3519 while ((reg_group = reg_set[g_ind++]))
3520 count += txgbe_read_regs_group(dev, &data[count],
3529 txgbe_get_eeprom_length(struct rte_eth_dev *dev)
3531 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3533 /* Return unit is byte count */
3534 return hw->rom.word_size * 2;
3538 txgbe_get_eeprom(struct rte_eth_dev *dev,
3539 struct rte_dev_eeprom_info *in_eeprom)
3541 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3542 struct txgbe_rom_info *eeprom = &hw->rom;
3543 uint16_t *data = in_eeprom->data;
3546 first = in_eeprom->offset >> 1;
3547 length = in_eeprom->length >> 1;
3548 if (first > hw->rom.word_size ||
3549 ((first + length) > hw->rom.word_size))
3552 in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
3554 return eeprom->readw_buffer(hw, first, length, data);
3558 txgbe_set_eeprom(struct rte_eth_dev *dev,
3559 struct rte_dev_eeprom_info *in_eeprom)
3561 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3562 struct txgbe_rom_info *eeprom = &hw->rom;
3563 uint16_t *data = in_eeprom->data;
3566 first = in_eeprom->offset >> 1;
3567 length = in_eeprom->length >> 1;
3568 if (first > hw->rom.word_size ||
3569 ((first + length) > hw->rom.word_size))
3572 in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
3574 return eeprom->writew_buffer(hw, first, length, data);
3578 txgbe_get_module_info(struct rte_eth_dev *dev,
3579 struct rte_eth_dev_module_info *modinfo)
3581 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3583 uint8_t sff8472_rev, addr_mode;
3584 bool page_swap = false;
3586 /* Check whether we support SFF-8472 or not */
3587 status = hw->phy.read_i2c_eeprom(hw,
3588 TXGBE_SFF_SFF_8472_COMP,
3593 /* addressing mode is not supported */
3594 status = hw->phy.read_i2c_eeprom(hw,
3595 TXGBE_SFF_SFF_8472_SWAP,
3600 if (addr_mode & TXGBE_SFF_ADDRESSING_MODE) {
3602 "Address change required to access page 0xA2, "
3603 "but not supported. Please report the module "
3604 "type to the driver maintainers.");
3608 if (sff8472_rev == TXGBE_SFF_SFF_8472_UNSUP || page_swap) {
3609 /* We have a SFP, but it does not support SFF-8472 */
3610 modinfo->type = RTE_ETH_MODULE_SFF_8079;
3611 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
3613 /* We have a SFP which supports a revision of SFF-8472. */
3614 modinfo->type = RTE_ETH_MODULE_SFF_8472;
3615 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
3622 txgbe_get_module_eeprom(struct rte_eth_dev *dev,
3623 struct rte_dev_eeprom_info *info)
3625 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3626 uint32_t status = TXGBE_ERR_PHY_ADDR_INVALID;
3627 uint8_t databyte = 0xFF;
3628 uint8_t *data = info->data;
3631 if (info->length == 0)
3634 for (i = info->offset; i < info->offset + info->length; i++) {
3635 if (i < RTE_ETH_MODULE_SFF_8079_LEN)
3636 status = hw->phy.read_i2c_eeprom(hw, i, &databyte);
3638 status = hw->phy.read_i2c_sff8472(hw, i, &databyte);
3643 data[i - info->offset] = databyte;
3650 txgbe_rss_update_sp(enum txgbe_mac_type mac_type)
3653 case txgbe_mac_raptor:
3660 static const struct eth_dev_ops txgbe_eth_dev_ops = {
3661 .dev_configure = txgbe_dev_configure,
3662 .dev_infos_get = txgbe_dev_info_get,
3663 .dev_start = txgbe_dev_start,
3664 .dev_stop = txgbe_dev_stop,
3665 .dev_set_link_up = txgbe_dev_set_link_up,
3666 .dev_set_link_down = txgbe_dev_set_link_down,
3667 .dev_close = txgbe_dev_close,
3668 .dev_reset = txgbe_dev_reset,
3669 .promiscuous_enable = txgbe_dev_promiscuous_enable,
3670 .promiscuous_disable = txgbe_dev_promiscuous_disable,
3671 .allmulticast_enable = txgbe_dev_allmulticast_enable,
3672 .allmulticast_disable = txgbe_dev_allmulticast_disable,
3673 .link_update = txgbe_dev_link_update,
3674 .stats_get = txgbe_dev_stats_get,
3675 .xstats_get = txgbe_dev_xstats_get,
3676 .xstats_get_by_id = txgbe_dev_xstats_get_by_id,
3677 .stats_reset = txgbe_dev_stats_reset,
3678 .xstats_reset = txgbe_dev_xstats_reset,
3679 .xstats_get_names = txgbe_dev_xstats_get_names,
3680 .xstats_get_names_by_id = txgbe_dev_xstats_get_names_by_id,
3681 .queue_stats_mapping_set = txgbe_dev_queue_stats_mapping_set,
3682 .fw_version_get = txgbe_fw_version_get,
3683 .dev_supported_ptypes_get = txgbe_dev_supported_ptypes_get,
3684 .mtu_set = txgbe_dev_mtu_set,
3685 .vlan_filter_set = txgbe_vlan_filter_set,
3686 .vlan_tpid_set = txgbe_vlan_tpid_set,
3687 .vlan_offload_set = txgbe_vlan_offload_set,
3688 .vlan_strip_queue_set = txgbe_vlan_strip_queue_set,
3689 .rx_queue_start = txgbe_dev_rx_queue_start,
3690 .rx_queue_stop = txgbe_dev_rx_queue_stop,
3691 .tx_queue_start = txgbe_dev_tx_queue_start,
3692 .tx_queue_stop = txgbe_dev_tx_queue_stop,
3693 .rx_queue_setup = txgbe_dev_rx_queue_setup,
3694 .rx_queue_intr_enable = txgbe_dev_rx_queue_intr_enable,
3695 .rx_queue_intr_disable = txgbe_dev_rx_queue_intr_disable,
3696 .rx_queue_release = txgbe_dev_rx_queue_release,
3697 .tx_queue_setup = txgbe_dev_tx_queue_setup,
3698 .tx_queue_release = txgbe_dev_tx_queue_release,
3699 .flow_ctrl_get = txgbe_flow_ctrl_get,
3700 .flow_ctrl_set = txgbe_flow_ctrl_set,
3701 .priority_flow_ctrl_set = txgbe_priority_flow_ctrl_set,
3702 .mac_addr_add = txgbe_add_rar,
3703 .mac_addr_remove = txgbe_remove_rar,
3704 .mac_addr_set = txgbe_set_default_mac_addr,
3705 .uc_hash_table_set = txgbe_uc_hash_table_set,
3706 .uc_all_hash_table_set = txgbe_uc_all_hash_table_set,
3707 .set_queue_rate_limit = txgbe_set_queue_rate_limit,
3708 .reta_update = txgbe_dev_rss_reta_update,
3709 .reta_query = txgbe_dev_rss_reta_query,
3710 .rss_hash_update = txgbe_dev_rss_hash_update,
3711 .rss_hash_conf_get = txgbe_dev_rss_hash_conf_get,
3712 .set_mc_addr_list = txgbe_dev_set_mc_addr_list,
3713 .rxq_info_get = txgbe_rxq_info_get,
3714 .txq_info_get = txgbe_txq_info_get,
3715 .get_reg = txgbe_get_regs,
3716 .get_eeprom_length = txgbe_get_eeprom_length,
3717 .get_eeprom = txgbe_get_eeprom,
3718 .set_eeprom = txgbe_set_eeprom,
3719 .get_module_info = txgbe_get_module_info,
3720 .get_module_eeprom = txgbe_get_module_eeprom,
3723 RTE_PMD_REGISTER_PCI(net_txgbe, rte_txgbe_pmd);
3724 RTE_PMD_REGISTER_PCI_TABLE(net_txgbe, pci_id_txgbe_map);
3725 RTE_PMD_REGISTER_KMOD_DEP(net_txgbe, "* igb_uio | uio_pci_generic | vfio-pci");
3727 RTE_LOG_REGISTER(txgbe_logtype_init, pmd.net.txgbe.init, NOTICE);
3728 RTE_LOG_REGISTER(txgbe_logtype_driver, pmd.net.txgbe.driver, NOTICE);
3730 #ifdef RTE_LIBRTE_TXGBE_DEBUG_RX
3731 RTE_LOG_REGISTER(txgbe_logtype_rx, pmd.net.txgbe.rx, DEBUG);
3733 #ifdef RTE_LIBRTE_TXGBE_DEBUG_TX
3734 RTE_LOG_REGISTER(txgbe_logtype_tx, pmd.net.txgbe.tx, DEBUG);
3737 #ifdef RTE_LIBRTE_TXGBE_DEBUG_TX_FREE
3738 RTE_LOG_REGISTER(txgbe_logtype_tx_free, pmd.net.txgbe.tx_free, DEBUG);