drivers/net/txgbe/txgbe_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2015-2020
   3  */
   4
   5 #include <stdio.h>
   6 #include <errno.h>
   7 #include <stdint.h>
   8 #include <string.h>
   9 #include <rte_common.h>
  10 #include <ethdev_pci.h>
  11
  12 #include <rte_interrupts.h>
  13 #include <rte_log.h>
  14 #include <rte_debug.h>
  15 #include <rte_pci.h>
  16 #include <rte_memory.h>
  17 #include <rte_eal.h>
  18 #include <rte_alarm.h>
  19
  20 #include "txgbe_logs.h"
  21 #include "base/txgbe.h"
  22 #include "txgbe_ethdev.h"
  23 #include "txgbe_rxtx.h"
  24 #include "txgbe_regs_group.h"
  25
  26 static const struct reg_info txgbe_regs_general[] = {
  27         {TXGBE_RST, 1, 1, "TXGBE_RST"},
  28         {TXGBE_STAT, 1, 1, "TXGBE_STAT"},
  29         {TXGBE_PORTCTL, 1, 1, "TXGBE_PORTCTL"},
  30         {TXGBE_SDP, 1, 1, "TXGBE_SDP"},
  31         {TXGBE_SDPCTL, 1, 1, "TXGBE_SDPCTL"},
  32         {TXGBE_LEDCTL, 1, 1, "TXGBE_LEDCTL"},
  33         {0, 0, 0, ""}
  34 };
  35
  36 static const struct reg_info txgbe_regs_nvm[] = {
  37         {0, 0, 0, ""}
  38 };
  39
  40 static const struct reg_info txgbe_regs_interrupt[] = {
  41         {0, 0, 0, ""}
  42 };
  43
  44 static const struct reg_info txgbe_regs_fctl_others[] = {
  45         {0, 0, 0, ""}
  46 };
  47
  48 static const struct reg_info txgbe_regs_rxdma[] = {
  49         {0, 0, 0, ""}
  50 };
  51
  52 static const struct reg_info txgbe_regs_rx[] = {
  53         {0, 0, 0, ""}
  54 };
  55
  56 static struct reg_info txgbe_regs_tx[] = {
  57         {0, 0, 0, ""}
  58 };
  59
  60 static const struct reg_info txgbe_regs_wakeup[] = {
  61         {0, 0, 0, ""}
  62 };
  63
  64 static const struct reg_info txgbe_regs_dcb[] = {
  65         {0, 0, 0, ""}
  66 };
  67
  68 static const struct reg_info txgbe_regs_mac[] = {
  69         {0, 0, 0, ""}
  70 };
  71
  72 static const struct reg_info txgbe_regs_diagnostic[] = {
  73         {0, 0, 0, ""},
  74 };
  75
  76 /* PF registers */
  77 static const struct reg_info *txgbe_regs_others[] = {
  78                                 txgbe_regs_general,
  79                                 txgbe_regs_nvm,
  80                                 txgbe_regs_interrupt,
  81                                 txgbe_regs_fctl_others,
  82                                 txgbe_regs_rxdma,
  83                                 txgbe_regs_rx,
  84                                 txgbe_regs_tx,
  85                                 txgbe_regs_wakeup,
  86                                 txgbe_regs_dcb,
  87                                 txgbe_regs_mac,
  88                                 txgbe_regs_diagnostic,
  89                                 NULL};
  90
  91 static int txgbe_fdir_filter_init(struct rte_eth_dev *eth_dev);
  92 static int txgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev);
  93 static int txgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev);
  94 static int txgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev);
  95 static int  txgbe_dev_set_link_up(struct rte_eth_dev *dev);
  96 static int  txgbe_dev_set_link_down(struct rte_eth_dev *dev);
  97 static int txgbe_dev_close(struct rte_eth_dev *dev);
  98 static int txgbe_dev_link_update(struct rte_eth_dev *dev,
  99                                 int wait_to_complete);
 100 static int txgbe_dev_stats_reset(struct rte_eth_dev *dev);
 101 static void txgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
 102 static void txgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev,
 103                                         uint16_t queue);
 104
 105 static void txgbe_dev_link_status_print(struct rte_eth_dev *dev);
 106 static int txgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on);
 107 static int txgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev);
 108 static int txgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
 109 static int txgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
 110 static int txgbe_dev_interrupt_action(struct rte_eth_dev *dev,
 111                                       struct rte_intr_handle *handle);
 112 static void txgbe_dev_interrupt_handler(void *param);
 113 static void txgbe_dev_interrupt_delayed_handler(void *param);
 114 static void txgbe_configure_msix(struct rte_eth_dev *dev);
 115
 116 static int txgbe_filter_restore(struct rte_eth_dev *dev);
 117 static void txgbe_l2_tunnel_conf(struct rte_eth_dev *dev);
 118
 119 #define TXGBE_SET_HWSTRIP(h, q) do {\
 120                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 121                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 122                 (h)->bitmap[idx] |= 1 << bit;\
 123         } while (0)
 124
 125 #define TXGBE_CLEAR_HWSTRIP(h, q) do {\
 126                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 127                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 128                 (h)->bitmap[idx] &= ~(1 << bit);\
 129         } while (0)
 130
 131 #define TXGBE_GET_HWSTRIP(h, q, r) do {\
 132                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 133                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 134                 (r) = (h)->bitmap[idx] >> bit & 1;\
 135         } while (0)
 136
 137 /*
 138  * The set of PCI devices this driver supports
 139  */
 140 static const struct rte_pci_id pci_id_txgbe_map[] = {
 141         { RTE_PCI_DEVICE(PCI_VENDOR_ID_WANGXUN, TXGBE_DEV_ID_SP1000) },
 142         { RTE_PCI_DEVICE(PCI_VENDOR_ID_WANGXUN, TXGBE_DEV_ID_WX1820) },
 143         { .vendor_id = 0, /* sentinel */ },
 144 };
 145
 146 static const struct rte_eth_desc_lim rx_desc_lim = {
 147         .nb_max = TXGBE_RING_DESC_MAX,
 148         .nb_min = TXGBE_RING_DESC_MIN,
 149         .nb_align = TXGBE_RXD_ALIGN,
 150 };
 151
 152 static const struct rte_eth_desc_lim tx_desc_lim = {
 153         .nb_max = TXGBE_RING_DESC_MAX,
 154         .nb_min = TXGBE_RING_DESC_MIN,
 155         .nb_align = TXGBE_TXD_ALIGN,
 156         .nb_seg_max = TXGBE_TX_MAX_SEG,
 157         .nb_mtu_seg_max = TXGBE_TX_MAX_SEG,
 158 };
 159
 160 static const struct eth_dev_ops txgbe_eth_dev_ops;
 161
 162 #define HW_XSTAT(m) {#m, offsetof(struct txgbe_hw_stats, m)}
 163 #define HW_XSTAT_NAME(m, n) {n, offsetof(struct txgbe_hw_stats, m)}
 164 static const struct rte_txgbe_xstats_name_off rte_txgbe_stats_strings[] = {
 165         /* MNG RxTx */
 166         HW_XSTAT(mng_bmc2host_packets),
 167         HW_XSTAT(mng_host2bmc_packets),
 168         /* Basic RxTx */
 169         HW_XSTAT(rx_packets),
 170         HW_XSTAT(tx_packets),
 171         HW_XSTAT(rx_bytes),
 172         HW_XSTAT(tx_bytes),
 173         HW_XSTAT(rx_total_bytes),
 174         HW_XSTAT(rx_total_packets),
 175         HW_XSTAT(tx_total_packets),
 176         HW_XSTAT(rx_total_missed_packets),
 177         HW_XSTAT(rx_broadcast_packets),
 178         HW_XSTAT(rx_multicast_packets),
 179         HW_XSTAT(rx_management_packets),
 180         HW_XSTAT(tx_management_packets),
 181         HW_XSTAT(rx_management_dropped),
 182
 183         /* Basic Error */
 184         HW_XSTAT(rx_crc_errors),
 185         HW_XSTAT(rx_illegal_byte_errors),
 186         HW_XSTAT(rx_error_bytes),
 187         HW_XSTAT(rx_mac_short_packet_dropped),
 188         HW_XSTAT(rx_length_errors),
 189         HW_XSTAT(rx_undersize_errors),
 190         HW_XSTAT(rx_fragment_errors),
 191         HW_XSTAT(rx_oversize_errors),
 192         HW_XSTAT(rx_jabber_errors),
 193         HW_XSTAT(rx_l3_l4_xsum_error),
 194         HW_XSTAT(mac_local_errors),
 195         HW_XSTAT(mac_remote_errors),
 196
 197         /* Flow Director */
 198         HW_XSTAT(flow_director_added_filters),
 199         HW_XSTAT(flow_director_removed_filters),
 200         HW_XSTAT(flow_director_filter_add_errors),
 201         HW_XSTAT(flow_director_filter_remove_errors),
 202         HW_XSTAT(flow_director_matched_filters),
 203         HW_XSTAT(flow_director_missed_filters),
 204
 205         /* FCoE */
 206         HW_XSTAT(rx_fcoe_crc_errors),
 207         HW_XSTAT(rx_fcoe_mbuf_allocation_errors),
 208         HW_XSTAT(rx_fcoe_dropped),
 209         HW_XSTAT(rx_fcoe_packets),
 210         HW_XSTAT(tx_fcoe_packets),
 211         HW_XSTAT(rx_fcoe_bytes),
 212         HW_XSTAT(tx_fcoe_bytes),
 213         HW_XSTAT(rx_fcoe_no_ddp),
 214         HW_XSTAT(rx_fcoe_no_ddp_ext_buff),
 215
 216         /* MACSEC */
 217         HW_XSTAT(tx_macsec_pkts_untagged),
 218         HW_XSTAT(tx_macsec_pkts_encrypted),
 219         HW_XSTAT(tx_macsec_pkts_protected),
 220         HW_XSTAT(tx_macsec_octets_encrypted),
 221         HW_XSTAT(tx_macsec_octets_protected),
 222         HW_XSTAT(rx_macsec_pkts_untagged),
 223         HW_XSTAT(rx_macsec_pkts_badtag),
 224         HW_XSTAT(rx_macsec_pkts_nosci),
 225         HW_XSTAT(rx_macsec_pkts_unknownsci),
 226         HW_XSTAT(rx_macsec_octets_decrypted),
 227         HW_XSTAT(rx_macsec_octets_validated),
 228         HW_XSTAT(rx_macsec_sc_pkts_unchecked),
 229         HW_XSTAT(rx_macsec_sc_pkts_delayed),
 230         HW_XSTAT(rx_macsec_sc_pkts_late),
 231         HW_XSTAT(rx_macsec_sa_pkts_ok),
 232         HW_XSTAT(rx_macsec_sa_pkts_invalid),
 233         HW_XSTAT(rx_macsec_sa_pkts_notvalid),
 234         HW_XSTAT(rx_macsec_sa_pkts_unusedsa),
 235         HW_XSTAT(rx_macsec_sa_pkts_notusingsa),
 236
 237         /* MAC RxTx */
 238         HW_XSTAT(rx_size_64_packets),
 239         HW_XSTAT(rx_size_65_to_127_packets),
 240         HW_XSTAT(rx_size_128_to_255_packets),
 241         HW_XSTAT(rx_size_256_to_511_packets),
 242         HW_XSTAT(rx_size_512_to_1023_packets),
 243         HW_XSTAT(rx_size_1024_to_max_packets),
 244         HW_XSTAT(tx_size_64_packets),
 245         HW_XSTAT(tx_size_65_to_127_packets),
 246         HW_XSTAT(tx_size_128_to_255_packets),
 247         HW_XSTAT(tx_size_256_to_511_packets),
 248         HW_XSTAT(tx_size_512_to_1023_packets),
 249         HW_XSTAT(tx_size_1024_to_max_packets),
 250
 251         /* Flow Control */
 252         HW_XSTAT(tx_xon_packets),
 253         HW_XSTAT(rx_xon_packets),
 254         HW_XSTAT(tx_xoff_packets),
 255         HW_XSTAT(rx_xoff_packets),
 256
 257         HW_XSTAT_NAME(tx_xon_packets, "tx_flow_control_xon_packets"),
 258         HW_XSTAT_NAME(rx_xon_packets, "rx_flow_control_xon_packets"),
 259         HW_XSTAT_NAME(tx_xoff_packets, "tx_flow_control_xoff_packets"),
 260         HW_XSTAT_NAME(rx_xoff_packets, "rx_flow_control_xoff_packets"),
 261 };
 262
 263 #define TXGBE_NB_HW_STATS (sizeof(rte_txgbe_stats_strings) / \
 264                            sizeof(rte_txgbe_stats_strings[0]))
 265
 266 /* Per-priority statistics */
 267 #define UP_XSTAT(m) {#m, offsetof(struct txgbe_hw_stats, up[0].m)}
 268 static const struct rte_txgbe_xstats_name_off rte_txgbe_up_strings[] = {
 269         UP_XSTAT(rx_up_packets),
 270         UP_XSTAT(tx_up_packets),
 271         UP_XSTAT(rx_up_bytes),
 272         UP_XSTAT(tx_up_bytes),
 273         UP_XSTAT(rx_up_drop_packets),
 274
 275         UP_XSTAT(tx_up_xon_packets),
 276         UP_XSTAT(rx_up_xon_packets),
 277         UP_XSTAT(tx_up_xoff_packets),
 278         UP_XSTAT(rx_up_xoff_packets),
 279         UP_XSTAT(rx_up_dropped),
 280         UP_XSTAT(rx_up_mbuf_alloc_errors),
 281         UP_XSTAT(tx_up_xon2off_packets),
 282 };
 283
 284 #define TXGBE_NB_UP_STATS (sizeof(rte_txgbe_up_strings) / \
 285                            sizeof(rte_txgbe_up_strings[0]))
 286
 287 /* Per-queue statistics */
 288 #define QP_XSTAT(m) {#m, offsetof(struct txgbe_hw_stats, qp[0].m)}
 289 static const struct rte_txgbe_xstats_name_off rte_txgbe_qp_strings[] = {
 290         QP_XSTAT(rx_qp_packets),
 291         QP_XSTAT(tx_qp_packets),
 292         QP_XSTAT(rx_qp_bytes),
 293         QP_XSTAT(tx_qp_bytes),
 294         QP_XSTAT(rx_qp_mc_packets),
 295 };
 296
 297 #define TXGBE_NB_QP_STATS (sizeof(rte_txgbe_qp_strings) / \
 298                            sizeof(rte_txgbe_qp_strings[0]))
 299
 300 static inline int
 301 txgbe_is_sfp(struct txgbe_hw *hw)
 302 {
 303         switch (hw->phy.type) {
 304         case txgbe_phy_sfp_avago:
 305         case txgbe_phy_sfp_ftl:
 306         case txgbe_phy_sfp_intel:
 307         case txgbe_phy_sfp_unknown:
 308         case txgbe_phy_sfp_tyco_passive:
 309         case txgbe_phy_sfp_unknown_passive:
 310                 return 1;
 311         default:
 312                 return 0;
 313         }
 314 }
 315
 316 static inline int32_t
 317 txgbe_pf_reset_hw(struct txgbe_hw *hw)
 318 {
 319         uint32_t ctrl_ext;
 320         int32_t status;
 321
 322         status = hw->mac.reset_hw(hw);
 323
 324         ctrl_ext = rd32(hw, TXGBE_PORTCTL);
 325         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 326         ctrl_ext |= TXGBE_PORTCTL_RSTDONE;
 327         wr32(hw, TXGBE_PORTCTL, ctrl_ext);
 328         txgbe_flush(hw);
 329
 330         if (status == TXGBE_ERR_SFP_NOT_PRESENT)
 331                 status = 0;
 332         return status;
 333 }
 334
 335 static inline void
 336 txgbe_enable_intr(struct rte_eth_dev *dev)
 337 {
 338         struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);
 339         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
 340
 341         wr32(hw, TXGBE_IENMISC, intr->mask_misc);
 342         wr32(hw, TXGBE_IMC(0), TXGBE_IMC_MASK);
 343         wr32(hw, TXGBE_IMC(1), TXGBE_IMC_MASK);
 344         txgbe_flush(hw);
 345 }
 346
 347 static void
 348 txgbe_disable_intr(struct txgbe_hw *hw)
 349 {
 350         PMD_INIT_FUNC_TRACE();
 351
 352         wr32(hw, TXGBE_IENMISC, ~BIT_MASK32);
 353         wr32(hw, TXGBE_IMS(0), TXGBE_IMC_MASK);
 354         wr32(hw, TXGBE_IMS(1), TXGBE_IMC_MASK);
 355         txgbe_flush(hw);
 356 }
 357
 358 static int
 359 txgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 360                                   uint16_t queue_id,
 361                                   uint8_t stat_idx,
 362                                   uint8_t is_rx)
 363 {
 364         struct txgbe_hw *hw = TXGBE_DEV_HW(eth_dev);
 365         struct txgbe_stat_mappings *stat_mappings =
 366                 TXGBE_DEV_STAT_MAPPINGS(eth_dev);
 367         uint32_t qsmr_mask = 0;
 368         uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
 369         uint32_t q_map;
 370         uint8_t n, offset;
 371
 372         if (hw->mac.type != txgbe_mac_raptor)
 373                 return -ENOSYS;
 374
 375         if (stat_idx & !QMAP_FIELD_RESERVED_BITS_MASK)
 376                 return -EIO;
 377
 378         PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d",
 379                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 380                      queue_id, stat_idx);
 381
 382         n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
 383         if (n >= TXGBE_NB_STAT_MAPPING) {
 384                 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
 385                 return -EIO;
 386         }
 387         offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
 388
 389         /* Now clear any previous stat_idx set */
 390         clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 391         if (!is_rx)
 392                 stat_mappings->tqsm[n] &= ~clearing_mask;
 393         else
 394                 stat_mappings->rqsm[n] &= ~clearing_mask;
 395
 396         q_map = (uint32_t)stat_idx;
 397         q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
 398         qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 399         if (!is_rx)
 400                 stat_mappings->tqsm[n] |= qsmr_mask;
 401         else
 402                 stat_mappings->rqsm[n] |= qsmr_mask;
 403
 404         PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d",
 405                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 406                      queue_id, stat_idx);
 407         PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
 408                      is_rx ? stat_mappings->rqsm[n] : stat_mappings->tqsm[n]);
 409         return 0;
 410 }
 411
 412 static void
 413 txgbe_dcb_init(struct txgbe_hw *hw, struct txgbe_dcb_config *dcb_config)
 414 {
 415         int i;
 416         u8 bwgp;
 417         struct txgbe_dcb_tc_config *tc;
 418
 419         UNREFERENCED_PARAMETER(hw);
 420
 421         dcb_config->num_tcs.pg_tcs = TXGBE_DCB_TC_MAX;
 422         dcb_config->num_tcs.pfc_tcs = TXGBE_DCB_TC_MAX;
 423         bwgp = (u8)(100 / TXGBE_DCB_TC_MAX);
 424         for (i = 0; i < TXGBE_DCB_TC_MAX; i++) {
 425                 tc = &dcb_config->tc_config[i];
 426                 tc->path[TXGBE_DCB_TX_CONFIG].bwg_id = i;
 427                 tc->path[TXGBE_DCB_TX_CONFIG].bwg_percent = bwgp + (i & 1);
 428                 tc->path[TXGBE_DCB_RX_CONFIG].bwg_id = i;
 429                 tc->path[TXGBE_DCB_RX_CONFIG].bwg_percent = bwgp + (i & 1);
 430                 tc->pfc = txgbe_dcb_pfc_disabled;
 431         }
 432
 433         /* Initialize default user to priority mapping, UPx->TC0 */
 434         tc = &dcb_config->tc_config[0];
 435         tc->path[TXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
 436         tc->path[TXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
 437         for (i = 0; i < TXGBE_DCB_BWG_MAX; i++) {
 438                 dcb_config->bw_percentage[i][TXGBE_DCB_TX_CONFIG] = 100;
 439                 dcb_config->bw_percentage[i][TXGBE_DCB_RX_CONFIG] = 100;
 440         }
 441         dcb_config->rx_pba_cfg = txgbe_dcb_pba_equal;
 442         dcb_config->pfc_mode_enable = false;
 443         dcb_config->vt_mode = true;
 444         dcb_config->round_robin_enable = false;
 445         /* support all DCB capabilities */
 446         dcb_config->support.capabilities = 0xFF;
 447 }
 448
 449 /*
 450  * Ensure that all locks are released before first NVM or PHY access
 451  */
 452 static void
 453 txgbe_swfw_lock_reset(struct txgbe_hw *hw)
 454 {
 455         uint16_t mask;
 456
 457         /*
 458          * These ones are more tricky since they are common to all ports; but
 459          * swfw_sync retries last long enough (1s) to be almost sure that if
 460          * lock can not be taken it is due to an improper lock of the
 461          * semaphore.
 462          */
 463         mask = TXGBE_MNGSEM_SWPHY |
 464                TXGBE_MNGSEM_SWMBX |
 465                TXGBE_MNGSEM_SWFLASH;
 466         if (hw->mac.acquire_swfw_sync(hw, mask) < 0)
 467                 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
 468
 469         hw->mac.release_swfw_sync(hw, mask);
 470 }
 471
 472 static int
 473 eth_txgbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params __rte_unused)
 474 {
 475         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
 476         struct txgbe_hw *hw = TXGBE_DEV_HW(eth_dev);
 477         struct txgbe_vfta *shadow_vfta = TXGBE_DEV_VFTA(eth_dev);
 478         struct txgbe_hwstrip *hwstrip = TXGBE_DEV_HWSTRIP(eth_dev);
 479         struct txgbe_dcb_config *dcb_config = TXGBE_DEV_DCB_CONFIG(eth_dev);
 480         struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(eth_dev);
 481         struct txgbe_bw_conf *bw_conf = TXGBE_DEV_BW_CONF(eth_dev);
 482         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 483         const struct rte_memzone *mz;
 484         uint32_t ctrl_ext;
 485         uint16_t csum;
 486         int err, i, ret;
 487
 488         PMD_INIT_FUNC_TRACE();
 489
 490         eth_dev->dev_ops = &txgbe_eth_dev_ops;
 491         eth_dev->rx_queue_count       = txgbe_dev_rx_queue_count;
 492         eth_dev->rx_descriptor_status = txgbe_dev_rx_descriptor_status;
 493         eth_dev->tx_descriptor_status = txgbe_dev_tx_descriptor_status;
 494         eth_dev->rx_pkt_burst = &txgbe_recv_pkts;
 495         eth_dev->tx_pkt_burst = &txgbe_xmit_pkts;
 496         eth_dev->tx_pkt_prepare = &txgbe_prep_pkts;
 497
 498         /*
 499          * For secondary processes, we don't initialise any further as primary
 500          * has already done this work. Only check we don't need a different
 501          * RX and TX function.
 502          */
 503         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
 504                 struct txgbe_tx_queue *txq;
 505                 /* TX queue function in primary, set by last queue initialized
 506                  * Tx queue may not initialized by primary process
 507                  */
 508                 if (eth_dev->data->tx_queues) {
 509                         uint16_t nb_tx_queues = eth_dev->data->nb_tx_queues;
 510                         txq = eth_dev->data->tx_queues[nb_tx_queues - 1];
 511                         txgbe_set_tx_function(eth_dev, txq);
 512                 } else {
 513                         /* Use default TX function if we get here */
 514                         PMD_INIT_LOG(NOTICE, "No TX queues configured yet. "
 515                                      "Using default TX function.");
 516                 }
 517
 518                 txgbe_set_rx_function(eth_dev);
 519
 520                 return 0;
 521         }
 522
 523         rte_eth_copy_pci_info(eth_dev, pci_dev);
 524
 525         /* Vendor and Device ID need to be set before init of shared code */
 526         hw->device_id = pci_dev->id.device_id;
 527         hw->vendor_id = pci_dev->id.vendor_id;
 528         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
 529         hw->allow_unsupported_sfp = 1;
 530
 531         /* Reserve memory for interrupt status block */
 532         mz = rte_eth_dma_zone_reserve(eth_dev, "txgbe_driver", -1,
 533                 16, TXGBE_ALIGN, SOCKET_ID_ANY);
 534         if (mz == NULL)
 535                 return -ENOMEM;
 536
 537         hw->isb_dma = TMZ_PADDR(mz);
 538         hw->isb_mem = TMZ_VADDR(mz);
 539
 540         /* Initialize the shared code (base driver) */
 541         err = txgbe_init_shared_code(hw);
 542         if (err != 0) {
 543                 PMD_INIT_LOG(ERR, "Shared code init failed: %d", err);
 544                 return -EIO;
 545         }
 546
 547         /* Unlock any pending hardware semaphore */
 548         txgbe_swfw_lock_reset(hw);
 549
 550 #ifdef RTE_LIB_SECURITY
 551         /* Initialize security_ctx only for primary process*/
 552         if (txgbe_ipsec_ctx_create(eth_dev))
 553                 return -ENOMEM;
 554 #endif
 555
 556         /* Initialize DCB configuration*/
 557         memset(dcb_config, 0, sizeof(struct txgbe_dcb_config));
 558         txgbe_dcb_init(hw, dcb_config);
 559
 560         /* Get Hardware Flow Control setting */
 561         hw->fc.requested_mode = txgbe_fc_full;
 562         hw->fc.current_mode = txgbe_fc_full;
 563         hw->fc.pause_time = TXGBE_FC_PAUSE_TIME;
 564         for (i = 0; i < TXGBE_DCB_TC_MAX; i++) {
 565                 hw->fc.low_water[i] = TXGBE_FC_XON_LOTH;
 566                 hw->fc.high_water[i] = TXGBE_FC_XOFF_HITH;
 567         }
 568         hw->fc.send_xon = 1;
 569
 570         err = hw->rom.init_params(hw);
 571         if (err != 0) {
 572                 PMD_INIT_LOG(ERR, "The EEPROM init failed: %d", err);
 573                 return -EIO;
 574         }
 575
 576         /* Make sure we have a good EEPROM before we read from it */
 577         err = hw->rom.validate_checksum(hw, &csum);
 578         if (err != 0) {
 579                 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", err);
 580                 return -EIO;
 581         }
 582
 583         err = hw->mac.init_hw(hw);
 584
 585         /*
 586          * Devices with copper phys will fail to initialise if txgbe_init_hw()
 587          * is called too soon after the kernel driver unbinding/binding occurs.
 588          * The failure occurs in txgbe_identify_phy() for all devices,
 589          * but for non-copper devies, txgbe_identify_sfp_module() is
 590          * also called. See txgbe_identify_phy(). The reason for the
 591          * failure is not known, and only occuts when virtualisation features
 592          * are disabled in the bios. A delay of 200ms  was found to be enough by
 593          * trial-and-error, and is doubled to be safe.
 594          */
 595         if (err && hw->phy.media_type == txgbe_media_type_copper) {
 596                 rte_delay_ms(200);
 597                 err = hw->mac.init_hw(hw);
 598         }
 599
 600         if (err == TXGBE_ERR_SFP_NOT_PRESENT)
 601                 err = 0;
 602
 603         if (err == TXGBE_ERR_EEPROM_VERSION) {
 604                 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
 605                              "LOM.  Please be aware there may be issues associated "
 606                              "with your hardware.");
 607                 PMD_INIT_LOG(ERR, "If you are experiencing problems "
 608                              "please contact your hardware representative "
 609                              "who provided you with this hardware.");
 610         } else if (err == TXGBE_ERR_SFP_NOT_SUPPORTED) {
 611                 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
 612         }
 613         if (err) {
 614                 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", err);
 615                 return -EIO;
 616         }
 617
 618         /* Reset the hw statistics */
 619         txgbe_dev_stats_reset(eth_dev);
 620
 621         /* disable interrupt */
 622         txgbe_disable_intr(hw);
 623
 624         /* Allocate memory for storing MAC addresses */
 625         eth_dev->data->mac_addrs = rte_zmalloc("txgbe", RTE_ETHER_ADDR_LEN *
 626                                                hw->mac.num_rar_entries, 0);
 627         if (eth_dev->data->mac_addrs == NULL) {
 628                 PMD_INIT_LOG(ERR,
 629                              "Failed to allocate %u bytes needed to store "
 630                              "MAC addresses",
 631                              RTE_ETHER_ADDR_LEN * hw->mac.num_rar_entries);
 632                 return -ENOMEM;
 633         }
 634
 635         /* Copy the permanent MAC address */
 636         rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.perm_addr,
 637                         &eth_dev->data->mac_addrs[0]);
 638
 639         /* Allocate memory for storing hash filter MAC addresses */
 640         eth_dev->data->hash_mac_addrs = rte_zmalloc("txgbe",
 641                         RTE_ETHER_ADDR_LEN * TXGBE_VMDQ_NUM_UC_MAC, 0);
 642         if (eth_dev->data->hash_mac_addrs == NULL) {
 643                 PMD_INIT_LOG(ERR,
 644                              "Failed to allocate %d bytes needed to store MAC addresses",
 645                              RTE_ETHER_ADDR_LEN * TXGBE_VMDQ_NUM_UC_MAC);
 646                 return -ENOMEM;
 647         }
 648
 649         /* initialize the vfta */
 650         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
 651
 652         /* initialize the hw strip bitmap*/
 653         memset(hwstrip, 0, sizeof(*hwstrip));
 654
 655         /* initialize PF if max_vfs not zero */
 656         ret = txgbe_pf_host_init(eth_dev);
 657         if (ret) {
 658                 rte_free(eth_dev->data->mac_addrs);
 659                 eth_dev->data->mac_addrs = NULL;
 660                 rte_free(eth_dev->data->hash_mac_addrs);
 661                 eth_dev->data->hash_mac_addrs = NULL;
 662                 return ret;
 663         }
 664
 665         ctrl_ext = rd32(hw, TXGBE_PORTCTL);
 666         /* let hardware know driver is loaded */
 667         ctrl_ext |= TXGBE_PORTCTL_DRVLOAD;
 668         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 669         ctrl_ext |= TXGBE_PORTCTL_RSTDONE;
 670         wr32(hw, TXGBE_PORTCTL, ctrl_ext);
 671         txgbe_flush(hw);
 672
 673         if (txgbe_is_sfp(hw) && hw->phy.sfp_type != txgbe_sfp_type_not_present)
 674                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
 675                              (int)hw->mac.type, (int)hw->phy.type,
 676                              (int)hw->phy.sfp_type);
 677         else
 678                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
 679                              (int)hw->mac.type, (int)hw->phy.type);
 680
 681         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
 682                      eth_dev->data->port_id, pci_dev->id.vendor_id,
 683                      pci_dev->id.device_id);
 684
 685         rte_intr_callback_register(intr_handle,
 686                                    txgbe_dev_interrupt_handler, eth_dev);
 687
 688         /* enable uio/vfio intr/eventfd mapping */
 689         rte_intr_enable(intr_handle);
 690
 691         /* enable support intr */
 692         txgbe_enable_intr(eth_dev);
 693
 694         /* initialize filter info */
 695         memset(filter_info, 0,
 696                sizeof(struct txgbe_filter_info));
 697
 698         /* initialize 5tuple filter list */
 699         TAILQ_INIT(&filter_info->fivetuple_list);
 700
 701         /* initialize flow director filter list & hash */
 702         txgbe_fdir_filter_init(eth_dev);
 703
 704         /* initialize l2 tunnel filter list & hash */
 705         txgbe_l2_tn_filter_init(eth_dev);
 706
 707         /* initialize flow filter lists */
 708         txgbe_filterlist_init();
 709
 710         /* initialize bandwidth configuration info */
 711         memset(bw_conf, 0, sizeof(struct txgbe_bw_conf));
 712
 713         /* initialize Traffic Manager configuration */
 714         txgbe_tm_conf_init(eth_dev);
 715
 716         return 0;
 717 }
 718
 719 static int
 720 eth_txgbe_dev_uninit(struct rte_eth_dev *eth_dev)
 721 {
 722         PMD_INIT_FUNC_TRACE();
 723
 724         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 725                 return 0;
 726
 727         txgbe_dev_close(eth_dev);
 728
 729         return 0;
 730 }
 731
 732 static int txgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev)
 733 {
 734         struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(eth_dev);
 735         struct txgbe_5tuple_filter *p_5tuple;
 736
 737         while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) {
 738                 TAILQ_REMOVE(&filter_info->fivetuple_list,
 739                              p_5tuple,
 740                              entries);
 741                 rte_free(p_5tuple);
 742         }
 743         memset(filter_info->fivetuple_mask, 0,
 744                sizeof(uint32_t) * TXGBE_5TUPLE_ARRAY_SIZE);
 745
 746         return 0;
 747 }
 748
 749 static int txgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev)
 750 {
 751         struct txgbe_hw_fdir_info *fdir_info = TXGBE_DEV_FDIR(eth_dev);
 752         struct txgbe_fdir_filter *fdir_filter;
 753
 754         if (fdir_info->hash_map)
 755                 rte_free(fdir_info->hash_map);
 756         if (fdir_info->hash_handle)
 757                 rte_hash_free(fdir_info->hash_handle);
 758
 759         while ((fdir_filter = TAILQ_FIRST(&fdir_info->fdir_list))) {
 760                 TAILQ_REMOVE(&fdir_info->fdir_list,
 761                              fdir_filter,
 762                              entries);
 763                 rte_free(fdir_filter);
 764         }
 765
 766         return 0;
 767 }
 768
 769 static int txgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev)
 770 {
 771         struct txgbe_l2_tn_info *l2_tn_info = TXGBE_DEV_L2_TN(eth_dev);
 772         struct txgbe_l2_tn_filter *l2_tn_filter;
 773
 774         if (l2_tn_info->hash_map)
 775                 rte_free(l2_tn_info->hash_map);
 776         if (l2_tn_info->hash_handle)
 777                 rte_hash_free(l2_tn_info->hash_handle);
 778
 779         while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
 780                 TAILQ_REMOVE(&l2_tn_info->l2_tn_list,
 781                              l2_tn_filter,
 782                              entries);
 783                 rte_free(l2_tn_filter);
 784         }
 785
 786         return 0;
 787 }
 788
 789 static int txgbe_fdir_filter_init(struct rte_eth_dev *eth_dev)
 790 {
 791         struct txgbe_hw_fdir_info *fdir_info = TXGBE_DEV_FDIR(eth_dev);
 792         char fdir_hash_name[RTE_HASH_NAMESIZE];
 793         struct rte_hash_parameters fdir_hash_params = {
 794                 .name = fdir_hash_name,
 795                 .entries = TXGBE_MAX_FDIR_FILTER_NUM,
 796                 .key_len = sizeof(struct txgbe_atr_input),
 797                 .hash_func = rte_hash_crc,
 798                 .hash_func_init_val = 0,
 799                 .socket_id = rte_socket_id(),
 800         };
 801
 802         TAILQ_INIT(&fdir_info->fdir_list);
 803         snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
 804                  "fdir_%s", TDEV_NAME(eth_dev));
 805         fdir_info->hash_handle = rte_hash_create(&fdir_hash_params);
 806         if (!fdir_info->hash_handle) {
 807                 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
 808                 return -EINVAL;
 809         }
 810         fdir_info->hash_map = rte_zmalloc("txgbe",
 811                                           sizeof(struct txgbe_fdir_filter *) *
 812                                           TXGBE_MAX_FDIR_FILTER_NUM,
 813                                           0);
 814         if (!fdir_info->hash_map) {
 815                 PMD_INIT_LOG(ERR,
 816                              "Failed to allocate memory for fdir hash map!");
 817                 return -ENOMEM;
 818         }
 819         fdir_info->mask_added = FALSE;
 820
 821         return 0;
 822 }
 823
 824 static int txgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev)
 825 {
 826         struct txgbe_l2_tn_info *l2_tn_info = TXGBE_DEV_L2_TN(eth_dev);
 827         char l2_tn_hash_name[RTE_HASH_NAMESIZE];
 828         struct rte_hash_parameters l2_tn_hash_params = {
 829                 .name = l2_tn_hash_name,
 830                 .entries = TXGBE_MAX_L2_TN_FILTER_NUM,
 831                 .key_len = sizeof(struct txgbe_l2_tn_key),
 832                 .hash_func = rte_hash_crc,
 833                 .hash_func_init_val = 0,
 834                 .socket_id = rte_socket_id(),
 835         };
 836
 837         TAILQ_INIT(&l2_tn_info->l2_tn_list);
 838         snprintf(l2_tn_hash_name, RTE_HASH_NAMESIZE,
 839                  "l2_tn_%s", TDEV_NAME(eth_dev));
 840         l2_tn_info->hash_handle = rte_hash_create(&l2_tn_hash_params);
 841         if (!l2_tn_info->hash_handle) {
 842                 PMD_INIT_LOG(ERR, "Failed to create L2 TN hash table!");
 843                 return -EINVAL;
 844         }
 845         l2_tn_info->hash_map = rte_zmalloc("txgbe",
 846                                    sizeof(struct txgbe_l2_tn_filter *) *
 847                                    TXGBE_MAX_L2_TN_FILTER_NUM,
 848                                    0);
 849         if (!l2_tn_info->hash_map) {
 850                 PMD_INIT_LOG(ERR,
 851                         "Failed to allocate memory for L2 TN hash map!");
 852                 return -ENOMEM;
 853         }
 854         l2_tn_info->e_tag_en = FALSE;
 855         l2_tn_info->e_tag_fwd_en = FALSE;
 856         l2_tn_info->e_tag_ether_type = RTE_ETHER_TYPE_ETAG;
 857
 858         return 0;
 859 }
 860
 861 static int
 862 eth_txgbe_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
 863                 struct rte_pci_device *pci_dev)
 864 {
 865         struct rte_eth_dev *pf_ethdev;
 866         struct rte_eth_devargs eth_da;
 867         int retval;
 868
 869         if (pci_dev->device.devargs) {
 870                 retval = rte_eth_devargs_parse(pci_dev->device.devargs->args,
 871                                 &eth_da);
 872                 if (retval)
 873                         return retval;
 874         } else {
 875                 memset(&eth_da, 0, sizeof(eth_da));
 876         }
 877
 878         retval = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
 879                         sizeof(struct txgbe_adapter),
 880                         eth_dev_pci_specific_init, pci_dev,
 881                         eth_txgbe_dev_init, NULL);
 882
 883         if (retval || eth_da.nb_representor_ports < 1)
 884                 return retval;
 885         if (eth_da.type != RTE_ETH_REPRESENTOR_VF)
 886                 return -ENOTSUP;
 887
 888         pf_ethdev = rte_eth_dev_allocated(pci_dev->device.name);
 889         if (pf_ethdev == NULL)
 890                 return -ENODEV;
 891
 892         return 0;
 893 }
 894
 895 static int eth_txgbe_pci_remove(struct rte_pci_device *pci_dev)
 896 {
 897         struct rte_eth_dev *ethdev;
 898
 899         ethdev = rte_eth_dev_allocated(pci_dev->device.name);
 900         if (!ethdev)
 901                 return -ENODEV;
 902
 903         return rte_eth_dev_destroy(ethdev, eth_txgbe_dev_uninit);
 904 }
 905
 906 static struct rte_pci_driver rte_txgbe_pmd = {
 907         .id_table = pci_id_txgbe_map,
 908         .drv_flags = RTE_PCI_DRV_NEED_MAPPING |
 909                      RTE_PCI_DRV_INTR_LSC,
 910         .probe = eth_txgbe_pci_probe,
 911         .remove = eth_txgbe_pci_remove,
 912 };
 913
 914 static int
 915 txgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
 916 {
 917         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
 918         struct txgbe_vfta *shadow_vfta = TXGBE_DEV_VFTA(dev);
 919         uint32_t vfta;
 920         uint32_t vid_idx;
 921         uint32_t vid_bit;
 922
 923         vid_idx = (uint32_t)((vlan_id >> 5) & 0x7F);
 924         vid_bit = (uint32_t)(1 << (vlan_id & 0x1F));
 925         vfta = rd32(hw, TXGBE_VLANTBL(vid_idx));
 926         if (on)
 927                 vfta |= vid_bit;
 928         else
 929                 vfta &= ~vid_bit;
 930         wr32(hw, TXGBE_VLANTBL(vid_idx), vfta);
 931
 932         /* update local VFTA copy */
 933         shadow_vfta->vfta[vid_idx] = vfta;
 934
 935         return 0;
 936 }
 937
 938 static void
 939 txgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
 940 {
 941         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
 942         struct txgbe_rx_queue *rxq;
 943         bool restart;
 944         uint32_t rxcfg, rxbal, rxbah;
 945
 946         if (on)
 947                 txgbe_vlan_hw_strip_enable(dev, queue);
 948         else
 949                 txgbe_vlan_hw_strip_disable(dev, queue);
 950
 951         rxq = dev->data->rx_queues[queue];
 952         rxbal = rd32(hw, TXGBE_RXBAL(rxq->reg_idx));
 953         rxbah = rd32(hw, TXGBE_RXBAH(rxq->reg_idx));
 954         rxcfg = rd32(hw, TXGBE_RXCFG(rxq->reg_idx));
 955         if (rxq->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) {
 956                 restart = (rxcfg & TXGBE_RXCFG_ENA) &&
 957                         !(rxcfg & TXGBE_RXCFG_VLAN);
 958                 rxcfg |= TXGBE_RXCFG_VLAN;
 959         } else {
 960                 restart = (rxcfg & TXGBE_RXCFG_ENA) &&
 961                         (rxcfg & TXGBE_RXCFG_VLAN);
 962                 rxcfg &= ~TXGBE_RXCFG_VLAN;
 963         }
 964         rxcfg &= ~TXGBE_RXCFG_ENA;
 965
 966         if (restart) {
 967                 /* set vlan strip for ring */
 968                 txgbe_dev_rx_queue_stop(dev, queue);
 969                 wr32(hw, TXGBE_RXBAL(rxq->reg_idx), rxbal);
 970                 wr32(hw, TXGBE_RXBAH(rxq->reg_idx), rxbah);
 971                 wr32(hw, TXGBE_RXCFG(rxq->reg_idx), rxcfg);
 972                 txgbe_dev_rx_queue_start(dev, queue);
 973         }
 974 }
 975
 976 static int
 977 txgbe_vlan_tpid_set(struct rte_eth_dev *dev,
 978                     enum rte_vlan_type vlan_type,
 979                     uint16_t tpid)
 980 {
 981         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
 982         int ret = 0;
 983         uint32_t portctrl, vlan_ext, qinq;
 984
 985         portctrl = rd32(hw, TXGBE_PORTCTL);
 986
 987         vlan_ext = (portctrl & TXGBE_PORTCTL_VLANEXT);
 988         qinq = vlan_ext && (portctrl & TXGBE_PORTCTL_QINQ);
 989         switch (vlan_type) {
 990         case ETH_VLAN_TYPE_INNER:
 991                 if (vlan_ext) {
 992                         wr32m(hw, TXGBE_VLANCTL,
 993                                 TXGBE_VLANCTL_TPID_MASK,
 994                                 TXGBE_VLANCTL_TPID(tpid));
 995                         wr32m(hw, TXGBE_DMATXCTRL,
 996                                 TXGBE_DMATXCTRL_TPID_MASK,
 997                                 TXGBE_DMATXCTRL_TPID(tpid));
 998                 } else {
 999                         ret = -ENOTSUP;
1000                         PMD_DRV_LOG(ERR, "Inner type is not supported"
1001                                     " by single VLAN");
1002                 }
1003
1004                 if (qinq) {
1005                         wr32m(hw, TXGBE_TAGTPID(0),
1006                                 TXGBE_TAGTPID_LSB_MASK,
1007                                 TXGBE_TAGTPID_LSB(tpid));
1008                 }
1009                 break;
1010         case ETH_VLAN_TYPE_OUTER:
1011                 if (vlan_ext) {
1012                         /* Only the high 16-bits is valid */
1013                         wr32m(hw, TXGBE_EXTAG,
1014                                 TXGBE_EXTAG_VLAN_MASK,
1015                                 TXGBE_EXTAG_VLAN(tpid));
1016                 } else {
1017                         wr32m(hw, TXGBE_VLANCTL,
1018                                 TXGBE_VLANCTL_TPID_MASK,
1019                                 TXGBE_VLANCTL_TPID(tpid));
1020                         wr32m(hw, TXGBE_DMATXCTRL,
1021                                 TXGBE_DMATXCTRL_TPID_MASK,
1022                                 TXGBE_DMATXCTRL_TPID(tpid));
1023                 }
1024
1025                 if (qinq) {
1026                         wr32m(hw, TXGBE_TAGTPID(0),
1027                                 TXGBE_TAGTPID_MSB_MASK,
1028                                 TXGBE_TAGTPID_MSB(tpid));
1029                 }
1030                 break;
1031         default:
1032                 PMD_DRV_LOG(ERR, "Unsupported VLAN type %d", vlan_type);
1033                 return -EINVAL;
1034         }
1035
1036         return ret;
1037 }
1038
1039 void
1040 txgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1041 {
1042         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
1043         uint32_t vlnctrl;
1044
1045         PMD_INIT_FUNC_TRACE();
1046
1047         /* Filter Table Disable */
1048         vlnctrl = rd32(hw, TXGBE_VLANCTL);
1049         vlnctrl &= ~TXGBE_VLANCTL_VFE;
1050         wr32(hw, TXGBE_VLANCTL, vlnctrl);
1051 }
1052
1053 void
1054 txgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1055 {
1056         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
1057         struct txgbe_vfta *shadow_vfta = TXGBE_DEV_VFTA(dev);
1058         uint32_t vlnctrl;
1059         uint16_t i;
1060
1061         PMD_INIT_FUNC_TRACE();
1062
1063         /* Filter Table Enable */
1064         vlnctrl = rd32(hw, TXGBE_VLANCTL);
1065         vlnctrl &= ~TXGBE_VLANCTL_CFIENA;
1066         vlnctrl |= TXGBE_VLANCTL_VFE;
1067         wr32(hw, TXGBE_VLANCTL, vlnctrl);
1068
1069         /* write whatever is in local vfta copy */
1070         for (i = 0; i < TXGBE_VFTA_SIZE; i++)
1071                 wr32(hw, TXGBE_VLANTBL(i), shadow_vfta->vfta[i]);
1072 }
1073
1074 void
1075 txgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1076 {
1077         struct txgbe_hwstrip *hwstrip = TXGBE_DEV_HWSTRIP(dev);
1078         struct txgbe_rx_queue *rxq;
1079
1080         if (queue >= TXGBE_MAX_RX_QUEUE_NUM)
1081                 return;
1082
1083         if (on)
1084                 TXGBE_SET_HWSTRIP(hwstrip, queue);
1085         else
1086                 TXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1087
1088         if (queue >= dev->data->nb_rx_queues)
1089                 return;
1090
1091         rxq = dev->data->rx_queues[queue];
1092
1093         if (on) {
1094                 rxq->vlan_flags = PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
1095                 rxq->offloads |= DEV_RX_OFFLOAD_VLAN_STRIP;
1096         } else {
1097                 rxq->vlan_flags = PKT_RX_VLAN;
1098                 rxq->offloads &= ~DEV_RX_OFFLOAD_VLAN_STRIP;
1099         }
1100 }
1101
1102 static void
1103 txgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
1104 {
1105         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
1106         uint32_t ctrl;
1107
1108         PMD_INIT_FUNC_TRACE();
1109
1110         ctrl = rd32(hw, TXGBE_RXCFG(queue));
1111         ctrl &= ~TXGBE_RXCFG_VLAN;
1112         wr32(hw, TXGBE_RXCFG(queue), ctrl);
1113
1114         /* record those setting for HW strip per queue */
1115         txgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
1116 }
1117
1118 static void
1119 txgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
1120 {
1121         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
1122         uint32_t ctrl;
1123
1124         PMD_INIT_FUNC_TRACE();
1125
1126         ctrl = rd32(hw, TXGBE_RXCFG(queue));
1127         ctrl |= TXGBE_RXCFG_VLAN;
1128         wr32(hw, TXGBE_RXCFG(queue), ctrl);
1129
1130         /* record those setting for HW strip per queue */
1131         txgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
1132 }
1133
1134 static void
1135 txgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
1136 {
1137         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
1138         uint32_t ctrl;
1139
1140         PMD_INIT_FUNC_TRACE();
1141
1142         ctrl = rd32(hw, TXGBE_PORTCTL);
1143         ctrl &= ~TXGBE_PORTCTL_VLANEXT;
1144         ctrl &= ~TXGBE_PORTCTL_QINQ;
1145         wr32(hw, TXGBE_PORTCTL, ctrl);
1146 }
1147
1148 static void
1149 txgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
1150 {
1151         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
1152         struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
1153         struct rte_eth_txmode *txmode = &dev->data->dev_conf.txmode;
1154         uint32_t ctrl;
1155
1156         PMD_INIT_FUNC_TRACE();
1157
1158         ctrl  = rd32(hw, TXGBE_PORTCTL);
1159         ctrl |= TXGBE_PORTCTL_VLANEXT;
1160         if (rxmode->offloads & DEV_RX_OFFLOAD_QINQ_STRIP ||
1161             txmode->offloads & DEV_TX_OFFLOAD_QINQ_INSERT)
1162                 ctrl |= TXGBE_PORTCTL_QINQ;
1163         wr32(hw, TXGBE_PORTCTL, ctrl);
1164 }
1165
1166 void
1167 txgbe_vlan_hw_strip_config(struct rte_eth_dev *dev)
1168 {
1169         struct txgbe_rx_queue *rxq;
1170         uint16_t i;
1171
1172         PMD_INIT_FUNC_TRACE();
1173
1174         for (i = 0; i < dev->data->nb_rx_queues; i++) {
1175                 rxq = dev->data->rx_queues[i];
1176
1177                 if (rxq->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1178                         txgbe_vlan_strip_queue_set(dev, i, 1);
1179                 else
1180                         txgbe_vlan_strip_queue_set(dev, i, 0);
1181         }
1182 }
1183
1184 void
1185 txgbe_config_vlan_strip_on_all_queues(struct rte_eth_dev *dev, int mask)
1186 {
1187         uint16_t i;
1188         struct rte_eth_rxmode *rxmode;
1189         struct txgbe_rx_queue *rxq;
1190
1191         if (mask & ETH_VLAN_STRIP_MASK) {
1192                 rxmode = &dev->data->dev_conf.rxmode;
1193                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1194                         for (i = 0; i < dev->data->nb_rx_queues; i++) {
1195                                 rxq = dev->data->rx_queues[i];
1196                                 rxq->offloads |= DEV_RX_OFFLOAD_VLAN_STRIP;
1197                         }
1198                 else
1199                         for (i = 0; i < dev->data->nb_rx_queues; i++) {
1200                                 rxq = dev->data->rx_queues[i];
1201                                 rxq->offloads &= ~DEV_RX_OFFLOAD_VLAN_STRIP;
1202                         }
1203         }
1204 }
1205
1206 static int
1207 txgbe_vlan_offload_config(struct rte_eth_dev *dev, int mask)
1208 {
1209         struct rte_eth_rxmode *rxmode;
1210         rxmode = &dev->data->dev_conf.rxmode;
1211
1212         if (mask & ETH_VLAN_STRIP_MASK)
1213                 txgbe_vlan_hw_strip_config(dev);
1214
1215         if (mask & ETH_VLAN_FILTER_MASK) {
1216                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
1217                         txgbe_vlan_hw_filter_enable(dev);
1218                 else
1219                         txgbe_vlan_hw_filter_disable(dev);
1220         }
1221
1222         if (mask & ETH_VLAN_EXTEND_MASK) {
1223                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
1224                         txgbe_vlan_hw_extend_enable(dev);
1225                 else
1226                         txgbe_vlan_hw_extend_disable(dev);
1227         }
1228
1229         return 0;
1230 }
1231
1232 static int
1233 txgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1234 {
1235         txgbe_config_vlan_strip_on_all_queues(dev, mask);
1236
1237         txgbe_vlan_offload_config(dev, mask);
1238
1239         return 0;
1240 }
1241
1242 static void
1243 txgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1244 {
1245         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
1246         /* VLNCTL: enable vlan filtering and allow all vlan tags through */
1247         uint32_t vlanctrl = rd32(hw, TXGBE_VLANCTL);
1248
1249         vlanctrl |= TXGBE_VLANCTL_VFE; /* enable vlan filters */
1250         wr32(hw, TXGBE_VLANCTL, vlanctrl);
1251 }
1252
1253 static int
1254 txgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q)
1255 {
1256         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1257
1258         switch (nb_rx_q) {
1259         case 1:
1260         case 2:
1261                 RTE_ETH_DEV_SRIOV(dev).active = ETH_64_POOLS;
1262                 break;
1263         case 4:
1264                 RTE_ETH_DEV_SRIOV(dev).active = ETH_32_POOLS;
1265                 break;
1266         default:
1267                 return -EINVAL;
1268         }
1269
1270         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool =
1271                 TXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
1272         RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx =
1273                 pci_dev->max_vfs * RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
1274         return 0;
1275 }
1276
1277 static int
1278 txgbe_check_mq_mode(struct rte_eth_dev *dev)
1279 {
1280         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
1281         uint16_t nb_rx_q = dev->data->nb_rx_queues;
1282         uint16_t nb_tx_q = dev->data->nb_tx_queues;
1283
1284         if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
1285                 /* check multi-queue mode */
1286                 switch (dev_conf->rxmode.mq_mode) {
1287                 case ETH_MQ_RX_VMDQ_DCB:
1288                         PMD_INIT_LOG(INFO, "ETH_MQ_RX_VMDQ_DCB mode supported in SRIOV");
1289                         break;
1290                 case ETH_MQ_RX_VMDQ_DCB_RSS:
1291                         /* DCB/RSS VMDQ in SRIOV mode, not implement yet */
1292                         PMD_INIT_LOG(ERR, "SRIOV active,"
1293                                         " unsupported mq_mode rx %d.",
1294                                         dev_conf->rxmode.mq_mode);
1295                         return -EINVAL;
1296                 case ETH_MQ_RX_RSS:
1297                 case ETH_MQ_RX_VMDQ_RSS:
1298                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_RSS;
1299                         if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)
1300                                 if (txgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) {
1301                                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1302                                                 " invalid queue number"
1303                                                 " for VMDQ RSS, allowed"
1304                                                 " value are 1, 2 or 4.");
1305                                         return -EINVAL;
1306                                 }
1307                         break;
1308                 case ETH_MQ_RX_VMDQ_ONLY:
1309                 case ETH_MQ_RX_NONE:
1310                         /* if nothing mq mode configure, use default scheme */
1311                         dev->data->dev_conf.rxmode.mq_mode =
1312                                 ETH_MQ_RX_VMDQ_ONLY;
1313                         break;
1314                 default: /* ETH_MQ_RX_DCB, ETH_MQ_RX_DCB_RSS or ETH_MQ_TX_DCB*/
1315                         /* SRIOV only works in VMDq enable mode */
1316                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1317                                         " wrong mq_mode rx %d.",
1318                                         dev_conf->rxmode.mq_mode);
1319                         return -EINVAL;
1320                 }
1321
1322                 switch (dev_conf->txmode.mq_mode) {
1323                 case ETH_MQ_TX_VMDQ_DCB:
1324                         PMD_INIT_LOG(INFO, "ETH_MQ_TX_VMDQ_DCB mode supported in SRIOV");
1325                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_DCB;
1326                         break;
1327                 default: /* ETH_MQ_TX_VMDQ_ONLY or ETH_MQ_TX_NONE */
1328                         dev->data->dev_conf.txmode.mq_mode =
1329                                 ETH_MQ_TX_VMDQ_ONLY;
1330                         break;
1331                 }
1332
1333                 /* check valid queue number */
1334                 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) ||
1335                     (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) {
1336                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1337                                         " nb_rx_q=%d nb_tx_q=%d queue number"
1338                                         " must be less than or equal to %d.",
1339                                         nb_rx_q, nb_tx_q,
1340                                         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool);
1341                         return -EINVAL;
1342                 }
1343         } else {
1344                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
1345                         PMD_INIT_LOG(ERR, "VMDQ+DCB+RSS mq_mode is"
1346                                           " not supported.");
1347                         return -EINVAL;
1348                 }
1349                 /* check configuration for vmdb+dcb mode */
1350                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB) {
1351                         const struct rte_eth_vmdq_dcb_conf *conf;
1352
1353                         if (nb_rx_q != TXGBE_VMDQ_DCB_NB_QUEUES) {
1354                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.",
1355                                                 TXGBE_VMDQ_DCB_NB_QUEUES);
1356                                 return -EINVAL;
1357                         }
1358                         conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf;
1359                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
1360                                conf->nb_queue_pools == ETH_32_POOLS)) {
1361                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
1362                                                 " nb_queue_pools must be %d or %d.",
1363                                                 ETH_16_POOLS, ETH_32_POOLS);
1364                                 return -EINVAL;
1365                         }
1366                 }
1367                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) {
1368                         const struct rte_eth_vmdq_dcb_tx_conf *conf;
1369
1370                         if (nb_tx_q != TXGBE_VMDQ_DCB_NB_QUEUES) {
1371                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d",
1372                                                  TXGBE_VMDQ_DCB_NB_QUEUES);
1373                                 return -EINVAL;
1374                         }
1375                         conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf;
1376                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
1377                                conf->nb_queue_pools == ETH_32_POOLS)) {
1378                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
1379                                                 " nb_queue_pools != %d and"
1380                                                 " nb_queue_pools != %d.",
1381                                                 ETH_16_POOLS, ETH_32_POOLS);
1382                                 return -EINVAL;
1383                         }
1384                 }
1385
1386                 /* For DCB mode check our configuration before we go further */
1387                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_DCB) {
1388                         const struct rte_eth_dcb_rx_conf *conf;
1389
1390                         conf = &dev_conf->rx_adv_conf.dcb_rx_conf;
1391                         if (!(conf->nb_tcs == ETH_4_TCS ||
1392                                conf->nb_tcs == ETH_8_TCS)) {
1393                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
1394                                                 " and nb_tcs != %d.",
1395                                                 ETH_4_TCS, ETH_8_TCS);
1396                                 return -EINVAL;
1397                         }
1398                 }
1399
1400                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_DCB) {
1401                         const struct rte_eth_dcb_tx_conf *conf;
1402
1403                         conf = &dev_conf->tx_adv_conf.dcb_tx_conf;
1404                         if (!(conf->nb_tcs == ETH_4_TCS ||
1405                                conf->nb_tcs == ETH_8_TCS)) {
1406                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
1407                                                 " and nb_tcs != %d.",
1408                                                 ETH_4_TCS, ETH_8_TCS);
1409                                 return -EINVAL;
1410                         }
1411                 }
1412         }
1413         return 0;
1414 }
1415
1416 static int
1417 txgbe_dev_configure(struct rte_eth_dev *dev)
1418 {
1419         struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);
1420         struct txgbe_adapter *adapter = TXGBE_DEV_ADAPTER(dev);
1421         int ret;
1422
1423         PMD_INIT_FUNC_TRACE();
1424
1425         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
1426                 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
1427
1428         /* multiple queue mode checking */
1429         ret  = txgbe_check_mq_mode(dev);
1430         if (ret != 0) {
1431                 PMD_DRV_LOG(ERR, "txgbe_check_mq_mode fails with %d.",
1432                             ret);
1433                 return ret;
1434         }
1435
1436         /* set flag to update link status after init */
1437         intr->flags |= TXGBE_FLAG_NEED_LINK_UPDATE;
1438
1439         /*
1440          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
1441          * allocation Rx preconditions we will reset it.
1442          */
1443         adapter->rx_bulk_alloc_allowed = true;
1444
1445         return 0;
1446 }
1447
1448 static void
1449 txgbe_dev_phy_intr_setup(struct rte_eth_dev *dev)
1450 {
1451         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
1452         struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);
1453         uint32_t gpie;
1454
1455         gpie = rd32(hw, TXGBE_GPIOINTEN);
1456         gpie |= TXGBE_GPIOBIT_6;
1457         wr32(hw, TXGBE_GPIOINTEN, gpie);
1458         intr->mask_misc |= TXGBE_ICRMISC_GPIO;
1459 }
1460
1461 int
1462 txgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
1463                         uint16_t tx_rate, uint64_t q_msk)
1464 {
1465         struct txgbe_hw *hw;
1466         struct txgbe_vf_info *vfinfo;
1467         struct rte_eth_link link;
1468         uint8_t  nb_q_per_pool;
1469         uint32_t queue_stride;
1470         uint32_t queue_idx, idx = 0, vf_idx;
1471         uint32_t queue_end;
1472         uint16_t total_rate = 0;
1473         struct rte_pci_device *pci_dev;
1474         int ret;
1475
1476         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1477         ret = rte_eth_link_get_nowait(dev->data->port_id, &link);
1478         if (ret < 0)
1479                 return ret;
1480
1481         if (vf >= pci_dev->max_vfs)
1482                 return -EINVAL;
1483
1484         if (tx_rate > link.link_speed)
1485                 return -EINVAL;
1486
1487         if (q_msk == 0)
1488                 return 0;
1489
1490         hw = TXGBE_DEV_HW(dev);
1491         vfinfo = *(TXGBE_DEV_VFDATA(dev));
1492         nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
1493         queue_stride = TXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
1494         queue_idx = vf * queue_stride;
1495         queue_end = queue_idx + nb_q_per_pool - 1;
1496         if (queue_end >= hw->mac.max_tx_queues)
1497                 return -EINVAL;
1498
1499         if (vfinfo) {
1500                 for (vf_idx = 0; vf_idx < pci_dev->max_vfs; vf_idx++) {
1501                         if (vf_idx == vf)
1502                                 continue;
1503                         for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
1504                                 idx++)
1505                                 total_rate += vfinfo[vf_idx].tx_rate[idx];
1506                 }
1507         } else {
1508                 return -EINVAL;
1509         }
1510
1511         /* Store tx_rate for this vf. */
1512         for (idx = 0; idx < nb_q_per_pool; idx++) {
1513                 if (((uint64_t)0x1 << idx) & q_msk) {
1514                         if (vfinfo[vf].tx_rate[idx] != tx_rate)
1515                                 vfinfo[vf].tx_rate[idx] = tx_rate;
1516                         total_rate += tx_rate;
1517                 }
1518         }
1519
1520         if (total_rate > dev->data->dev_link.link_speed) {
1521                 /* Reset stored TX rate of the VF if it causes exceed
1522                  * link speed.
1523                  */
1524                 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
1525                 return -EINVAL;
1526         }
1527
1528         /* Set ARBTXRATE of each queue/pool for vf X  */
1529         for (; queue_idx <= queue_end; queue_idx++) {
1530                 if (0x1 & q_msk)
1531                         txgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
1532                 q_msk = q_msk >> 1;
1533         }
1534
1535         return 0;
1536 }
1537
1538 /*
1539  * Configure device link speed and setup link.
1540  * It returns 0 on success.
1541  */
1542 static int
1543 txgbe_dev_start(struct rte_eth_dev *dev)
1544 {
1545         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
1546         struct txgbe_hw_stats *hw_stats = TXGBE_DEV_STATS(dev);
1547         struct txgbe_vf_info *vfinfo = *TXGBE_DEV_VFDATA(dev);
1548         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1549         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1550         uint32_t intr_vector = 0;
1551         int err;
1552         bool link_up = false, negotiate = 0;
1553         uint32_t speed = 0;
1554         uint32_t allowed_speeds = 0;
1555         int mask = 0;
1556         int status;
1557         uint16_t vf, idx;
1558         uint32_t *link_speeds;
1559         struct txgbe_tm_conf *tm_conf = TXGBE_DEV_TM_CONF(dev);
1560
1561         PMD_INIT_FUNC_TRACE();
1562
1563         /* TXGBE devices don't support:
1564          *    - half duplex (checked afterwards for valid speeds)
1565          *    - fixed speed: TODO implement
1566          */
1567         if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
1568                 PMD_INIT_LOG(ERR,
1569                 "Invalid link_speeds for port %u, fix speed not supported",
1570                                 dev->data->port_id);
1571                 return -EINVAL;
1572         }
1573
1574         /* Stop the link setup handler before resetting the HW. */
1575         rte_eal_alarm_cancel(txgbe_dev_setup_link_alarm_handler, dev);
1576
1577         /* disable uio/vfio intr/eventfd mapping */
1578         rte_intr_disable(intr_handle);
1579
1580         /* stop adapter */
1581         hw->adapter_stopped = 0;
1582         txgbe_stop_hw(hw);
1583
1584         /* reinitialize adapter
1585          * this calls reset and start
1586          */
1587         hw->nb_rx_queues = dev->data->nb_rx_queues;
1588         hw->nb_tx_queues = dev->data->nb_tx_queues;
1589         status = txgbe_pf_reset_hw(hw);
1590         if (status != 0)
1591                 return -1;
1592         hw->mac.start_hw(hw);
1593         hw->mac.get_link_status = true;
1594
1595         /* configure PF module if SRIOV enabled */
1596         txgbe_pf_host_configure(dev);
1597
1598         txgbe_dev_phy_intr_setup(dev);
1599
1600         /* check and configure queue intr-vector mapping */
1601         if ((rte_intr_cap_multiple(intr_handle) ||
1602              !RTE_ETH_DEV_SRIOV(dev).active) &&
1603             dev->data->dev_conf.intr_conf.rxq != 0) {
1604                 intr_vector = dev->data->nb_rx_queues;
1605                 if (rte_intr_efd_enable(intr_handle, intr_vector))
1606                         return -1;
1607         }
1608
1609         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1610                 intr_handle->intr_vec =
1611                         rte_zmalloc("intr_vec",
1612                                     dev->data->nb_rx_queues * sizeof(int), 0);
1613                 if (intr_handle->intr_vec == NULL) {
1614                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
1615                                      " intr_vec", dev->data->nb_rx_queues);
1616                         return -ENOMEM;
1617                 }
1618         }
1619
1620         /* confiugre msix for sleep until rx interrupt */
1621         txgbe_configure_msix(dev);
1622
1623         /* initialize transmission unit */
1624         txgbe_dev_tx_init(dev);
1625
1626         /* This can fail when allocating mbufs for descriptor rings */
1627         err = txgbe_dev_rx_init(dev);
1628         if (err) {
1629                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
1630                 goto error;
1631         }
1632
1633         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
1634                 ETH_VLAN_EXTEND_MASK;
1635         err = txgbe_vlan_offload_config(dev, mask);
1636         if (err) {
1637                 PMD_INIT_LOG(ERR, "Unable to set VLAN offload");
1638                 goto error;
1639         }
1640
1641         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1642                 /* Enable vlan filtering for VMDq */
1643                 txgbe_vmdq_vlan_hw_filter_enable(dev);
1644         }
1645
1646         /* Configure DCB hw */
1647         txgbe_configure_pb(dev);
1648         txgbe_configure_port(dev);
1649         txgbe_configure_dcb(dev);
1650
1651         if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
1652                 err = txgbe_fdir_configure(dev);
1653                 if (err)
1654                         goto error;
1655         }
1656
1657         /* Restore vf rate limit */
1658         if (vfinfo != NULL) {
1659                 for (vf = 0; vf < pci_dev->max_vfs; vf++)
1660                         for (idx = 0; idx < TXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
1661                                 if (vfinfo[vf].tx_rate[idx] != 0)
1662                                         txgbe_set_vf_rate_limit(dev, vf,
1663                                                 vfinfo[vf].tx_rate[idx],
1664                                                 1 << idx);
1665         }
1666
1667         err = txgbe_dev_rxtx_start(dev);
1668         if (err < 0) {
1669                 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
1670                 goto error;
1671         }
1672
1673         /* Skip link setup if loopback mode is enabled. */
1674         if (hw->mac.type == txgbe_mac_raptor &&
1675             dev->data->dev_conf.lpbk_mode)
1676                 goto skip_link_setup;
1677
1678         if (txgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
1679                 err = hw->mac.setup_sfp(hw);
1680                 if (err)
1681                         goto error;
1682         }
1683
1684         if (hw->phy.media_type == txgbe_media_type_copper) {
1685                 /* Turn on the copper */
1686                 hw->phy.set_phy_power(hw, true);
1687         } else {
1688                 /* Turn on the laser */
1689                 hw->mac.enable_tx_laser(hw);
1690         }
1691
1692         err = hw->mac.check_link(hw, &speed, &link_up, 0);
1693         if (err)
1694                 goto error;
1695         dev->data->dev_link.link_status = link_up;
1696
1697         err = hw->mac.get_link_capabilities(hw, &speed, &negotiate);
1698         if (err)
1699                 goto error;
1700
1701         allowed_speeds = ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
1702                         ETH_LINK_SPEED_10G;
1703
1704         link_speeds = &dev->data->dev_conf.link_speeds;
1705         if (*link_speeds & ~allowed_speeds) {
1706                 PMD_INIT_LOG(ERR, "Invalid link setting");
1707                 goto error;
1708         }
1709
1710         speed = 0x0;
1711         if (*link_speeds == ETH_LINK_SPEED_AUTONEG) {
1712                 speed = (TXGBE_LINK_SPEED_100M_FULL |
1713                          TXGBE_LINK_SPEED_1GB_FULL |
1714                          TXGBE_LINK_SPEED_10GB_FULL);
1715         } else {
1716                 if (*link_speeds & ETH_LINK_SPEED_10G)
1717                         speed |= TXGBE_LINK_SPEED_10GB_FULL;
1718                 if (*link_speeds & ETH_LINK_SPEED_5G)
1719                         speed |= TXGBE_LINK_SPEED_5GB_FULL;
1720                 if (*link_speeds & ETH_LINK_SPEED_2_5G)
1721                         speed |= TXGBE_LINK_SPEED_2_5GB_FULL;
1722                 if (*link_speeds & ETH_LINK_SPEED_1G)
1723                         speed |= TXGBE_LINK_SPEED_1GB_FULL;
1724                 if (*link_speeds & ETH_LINK_SPEED_100M)
1725                         speed |= TXGBE_LINK_SPEED_100M_FULL;
1726         }
1727
1728         err = hw->mac.setup_link(hw, speed, link_up);
1729         if (err)
1730                 goto error;
1731
1732 skip_link_setup:
1733
1734         if (rte_intr_allow_others(intr_handle)) {
1735                 /* check if lsc interrupt is enabled */
1736                 if (dev->data->dev_conf.intr_conf.lsc != 0)
1737                         txgbe_dev_lsc_interrupt_setup(dev, TRUE);
1738                 else
1739                         txgbe_dev_lsc_interrupt_setup(dev, FALSE);
1740                 txgbe_dev_macsec_interrupt_setup(dev);
1741                 txgbe_set_ivar_map(hw, -1, 1, TXGBE_MISC_VEC_ID);
1742         } else {
1743                 rte_intr_callback_unregister(intr_handle,
1744                                              txgbe_dev_interrupt_handler, dev);
1745                 if (dev->data->dev_conf.intr_conf.lsc != 0)
1746                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
1747                                      " no intr multiplex");
1748         }
1749
1750         /* check if rxq interrupt is enabled */
1751         if (dev->data->dev_conf.intr_conf.rxq != 0 &&
1752             rte_intr_dp_is_en(intr_handle))
1753                 txgbe_dev_rxq_interrupt_setup(dev);
1754
1755         /* enable uio/vfio intr/eventfd mapping */
1756         rte_intr_enable(intr_handle);
1757
1758         /* resume enabled intr since hw reset */
1759         txgbe_enable_intr(dev);
1760         txgbe_l2_tunnel_conf(dev);
1761         txgbe_filter_restore(dev);
1762
1763         if (tm_conf->root && !tm_conf->committed)
1764                 PMD_DRV_LOG(WARNING,
1765                             "please call hierarchy_commit() "
1766                             "before starting the port");
1767
1768         /*
1769          * Update link status right before return, because it may
1770          * start link configuration process in a separate thread.
1771          */
1772         txgbe_dev_link_update(dev, 0);
1773
1774         wr32m(hw, TXGBE_LEDCTL, 0xFFFFFFFF, TXGBE_LEDCTL_ORD_MASK);
1775
1776         txgbe_read_stats_registers(hw, hw_stats);
1777         hw->offset_loaded = 1;
1778
1779         return 0;
1780
1781 error:
1782         PMD_INIT_LOG(ERR, "failure in dev start: %d", err);
1783         txgbe_dev_clear_queues(dev);
1784         return -EIO;
1785 }
1786
1787 /*
1788  * Stop device: disable rx and tx functions to allow for reconfiguring.
1789  */
1790 static int
1791 txgbe_dev_stop(struct rte_eth_dev *dev)
1792 {
1793         struct rte_eth_link link;
1794         struct txgbe_adapter *adapter = TXGBE_DEV_ADAPTER(dev);
1795         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
1796         struct txgbe_vf_info *vfinfo = *TXGBE_DEV_VFDATA(dev);
1797         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1798         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1799         int vf;
1800         struct txgbe_tm_conf *tm_conf = TXGBE_DEV_TM_CONF(dev);
1801
1802         if (hw->adapter_stopped)
1803                 return 0;
1804
1805         PMD_INIT_FUNC_TRACE();
1806
1807         rte_eal_alarm_cancel(txgbe_dev_setup_link_alarm_handler, dev);
1808
1809         /* disable interrupts */
1810         txgbe_disable_intr(hw);
1811
1812         /* reset the NIC */
1813         txgbe_pf_reset_hw(hw);
1814         hw->adapter_stopped = 0;
1815
1816         /* stop adapter */
1817         txgbe_stop_hw(hw);
1818
1819         for (vf = 0; vfinfo != NULL && vf < pci_dev->max_vfs; vf++)
1820                 vfinfo[vf].clear_to_send = false;
1821
1822         if (hw->phy.media_type == txgbe_media_type_copper) {
1823                 /* Turn off the copper */
1824                 hw->phy.set_phy_power(hw, false);
1825         } else {
1826                 /* Turn off the laser */
1827                 hw->mac.disable_tx_laser(hw);
1828         }
1829
1830         txgbe_dev_clear_queues(dev);
1831
1832         /* Clear stored conf */
1833         dev->data->scattered_rx = 0;
1834         dev->data->lro = 0;
1835
1836         /* Clear recorded link status */
1837         memset(&link, 0, sizeof(link));
1838         rte_eth_linkstatus_set(dev, &link);
1839
1840         if (!rte_intr_allow_others(intr_handle))
1841                 /* resume to the default handler */
1842                 rte_intr_callback_register(intr_handle,
1843                                            txgbe_dev_interrupt_handler,
1844                                            (void *)dev);
1845
1846         /* Clean datapath event and queue/vec mapping */
1847         rte_intr_efd_disable(intr_handle);
1848         if (intr_handle->intr_vec != NULL) {
1849                 rte_free(intr_handle->intr_vec);
1850                 intr_handle->intr_vec = NULL;
1851         }
1852
1853         /* reset hierarchy commit */
1854         tm_conf->committed = false;
1855
1856         adapter->rss_reta_updated = 0;
1857         wr32m(hw, TXGBE_LEDCTL, 0xFFFFFFFF, TXGBE_LEDCTL_SEL_MASK);
1858
1859         hw->adapter_stopped = true;
1860         dev->data->dev_started = 0;
1861
1862         return 0;
1863 }
1864
1865 /*
1866  * Set device link up: enable tx.
1867  */
1868 static int
1869 txgbe_dev_set_link_up(struct rte_eth_dev *dev)
1870 {
1871         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
1872
1873         if (hw->phy.media_type == txgbe_media_type_copper) {
1874                 /* Turn on the copper */
1875                 hw->phy.set_phy_power(hw, true);
1876         } else {
1877                 /* Turn on the laser */
1878                 hw->mac.enable_tx_laser(hw);
1879                 txgbe_dev_link_update(dev, 0);
1880         }
1881
1882         return 0;
1883 }
1884
1885 /*
1886  * Set device link down: disable tx.
1887  */
1888 static int
1889 txgbe_dev_set_link_down(struct rte_eth_dev *dev)
1890 {
1891         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
1892
1893         if (hw->phy.media_type == txgbe_media_type_copper) {
1894                 /* Turn off the copper */
1895                 hw->phy.set_phy_power(hw, false);
1896         } else {
1897                 /* Turn off the laser */
1898                 hw->mac.disable_tx_laser(hw);
1899                 txgbe_dev_link_update(dev, 0);
1900         }
1901
1902         return 0;
1903 }
1904
1905 /*
1906  * Reset and stop device.
1907  */
1908 static int
1909 txgbe_dev_close(struct rte_eth_dev *dev)
1910 {
1911         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
1912         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1913         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1914         int retries = 0;
1915         int ret;
1916
1917         PMD_INIT_FUNC_TRACE();
1918
1919         txgbe_pf_reset_hw(hw);
1920
1921         ret = txgbe_dev_stop(dev);
1922
1923         txgbe_dev_free_queues(dev);
1924
1925         /* reprogram the RAR[0] in case user changed it. */
1926         txgbe_set_rar(hw, 0, hw->mac.addr, 0, true);
1927
1928         /* Unlock any pending hardware semaphore */
1929         txgbe_swfw_lock_reset(hw);
1930
1931         /* disable uio intr before callback unregister */
1932         rte_intr_disable(intr_handle);
1933
1934         do {
1935                 ret = rte_intr_callback_unregister(intr_handle,
1936                                 txgbe_dev_interrupt_handler, dev);
1937                 if (ret >= 0 || ret == -ENOENT) {
1938                         break;
1939                 } else if (ret != -EAGAIN) {
1940                         PMD_INIT_LOG(ERR,
1941                                 "intr callback unregister failed: %d",
1942                                 ret);
1943                 }
1944                 rte_delay_ms(100);
1945         } while (retries++ < (10 + TXGBE_LINK_UP_TIME));
1946
1947         /* cancel the delay handler before remove dev */
1948         rte_eal_alarm_cancel(txgbe_dev_interrupt_delayed_handler, dev);
1949
1950         /* uninitialize PF if max_vfs not zero */
1951         txgbe_pf_host_uninit(dev);
1952
1953         rte_free(dev->data->mac_addrs);
1954         dev->data->mac_addrs = NULL;
1955
1956         rte_free(dev->data->hash_mac_addrs);
1957         dev->data->hash_mac_addrs = NULL;
1958
1959         /* remove all the fdir filters & hash */
1960         txgbe_fdir_filter_uninit(dev);
1961
1962         /* remove all the L2 tunnel filters & hash */
1963         txgbe_l2_tn_filter_uninit(dev);
1964
1965         /* Remove all ntuple filters of the device */
1966         txgbe_ntuple_filter_uninit(dev);
1967
1968         /* clear all the filters list */
1969         txgbe_filterlist_flush();
1970
1971         /* Remove all Traffic Manager configuration */
1972         txgbe_tm_conf_uninit(dev);
1973
1974 #ifdef RTE_LIB_SECURITY
1975         rte_free(dev->security_ctx);
1976 #endif
1977
1978         return ret;
1979 }
1980
1981 /*
1982  * Reset PF device.
1983  */
1984 static int
1985 txgbe_dev_reset(struct rte_eth_dev *dev)
1986 {
1987         int ret;
1988
1989         /* When a DPDK PMD PF begin to reset PF port, it should notify all
1990          * its VF to make them align with it. The detailed notification
1991          * mechanism is PMD specific. As to txgbe PF, it is rather complex.
1992          * To avoid unexpected behavior in VF, currently reset of PF with
1993          * SR-IOV activation is not supported. It might be supported later.
1994          */
1995         if (dev->data->sriov.active)
1996                 return -ENOTSUP;
1997
1998         ret = eth_txgbe_dev_uninit(dev);
1999         if (ret)
2000                 return ret;
2001
2002         ret = eth_txgbe_dev_init(dev, NULL);
2003
2004         return ret;
2005 }
2006
2007 #define UPDATE_QP_COUNTER_32bit(reg, last_counter, counter)     \
2008         {                                                       \
2009                 uint32_t current_counter = rd32(hw, reg);       \
2010                 if (current_counter < last_counter)             \
2011                         current_counter += 0x100000000LL;       \
2012                 if (!hw->offset_loaded)                         \
2013                         last_counter = current_counter;         \
2014                 counter = current_counter - last_counter;       \
2015                 counter &= 0xFFFFFFFFLL;                        \
2016         }
2017
2018 #define UPDATE_QP_COUNTER_36bit(reg_lsb, reg_msb, last_counter, counter) \
2019         {                                                                \
2020                 uint64_t current_counter_lsb = rd32(hw, reg_lsb);        \
2021                 uint64_t current_counter_msb = rd32(hw, reg_msb);        \
2022                 uint64_t current_counter = (current_counter_msb << 32) | \
2023                         current_counter_lsb;                             \
2024                 if (current_counter < last_counter)                      \
2025                         current_counter += 0x1000000000LL;               \
2026                 if (!hw->offset_loaded)                                  \
2027                         last_counter = current_counter;                  \
2028                 counter = current_counter - last_counter;                \
2029                 counter &= 0xFFFFFFFFFLL;                                \
2030         }
2031
2032 void
2033 txgbe_read_stats_registers(struct txgbe_hw *hw,
2034                            struct txgbe_hw_stats *hw_stats)
2035 {
2036         unsigned int i;
2037
2038         /* QP Stats */
2039         for (i = 0; i < hw->nb_rx_queues; i++) {
2040                 UPDATE_QP_COUNTER_32bit(TXGBE_QPRXPKT(i),
2041                         hw->qp_last[i].rx_qp_packets,
2042                         hw_stats->qp[i].rx_qp_packets);
2043                 UPDATE_QP_COUNTER_36bit(TXGBE_QPRXOCTL(i), TXGBE_QPRXOCTH(i),
2044                         hw->qp_last[i].rx_qp_bytes,
2045                         hw_stats->qp[i].rx_qp_bytes);
2046                 UPDATE_QP_COUNTER_32bit(TXGBE_QPRXMPKT(i),
2047                         hw->qp_last[i].rx_qp_mc_packets,
2048                         hw_stats->qp[i].rx_qp_mc_packets);
2049         }
2050
2051         for (i = 0; i < hw->nb_tx_queues; i++) {
2052                 UPDATE_QP_COUNTER_32bit(TXGBE_QPTXPKT(i),
2053                         hw->qp_last[i].tx_qp_packets,
2054                         hw_stats->qp[i].tx_qp_packets);
2055                 UPDATE_QP_COUNTER_36bit(TXGBE_QPTXOCTL(i), TXGBE_QPTXOCTH(i),
2056                         hw->qp_last[i].tx_qp_bytes,
2057                         hw_stats->qp[i].tx_qp_bytes);
2058         }
2059         /* PB Stats */
2060         for (i = 0; i < TXGBE_MAX_UP; i++) {
2061                 hw_stats->up[i].rx_up_xon_packets +=
2062                                 rd32(hw, TXGBE_PBRXUPXON(i));
2063                 hw_stats->up[i].rx_up_xoff_packets +=
2064                                 rd32(hw, TXGBE_PBRXUPXOFF(i));
2065                 hw_stats->up[i].tx_up_xon_packets +=
2066                                 rd32(hw, TXGBE_PBTXUPXON(i));
2067                 hw_stats->up[i].tx_up_xoff_packets +=
2068                                 rd32(hw, TXGBE_PBTXUPXOFF(i));
2069                 hw_stats->up[i].tx_up_xon2off_packets +=
2070                                 rd32(hw, TXGBE_PBTXUPOFF(i));
2071                 hw_stats->up[i].rx_up_dropped +=
2072                                 rd32(hw, TXGBE_PBRXMISS(i));
2073         }
2074         hw_stats->rx_xon_packets += rd32(hw, TXGBE_PBRXLNKXON);
2075         hw_stats->rx_xoff_packets += rd32(hw, TXGBE_PBRXLNKXOFF);
2076         hw_stats->tx_xon_packets += rd32(hw, TXGBE_PBTXLNKXON);
2077         hw_stats->tx_xoff_packets += rd32(hw, TXGBE_PBTXLNKXOFF);
2078
2079         /* DMA Stats */
2080         hw_stats->rx_packets += rd32(hw, TXGBE_DMARXPKT);
2081         hw_stats->tx_packets += rd32(hw, TXGBE_DMATXPKT);
2082
2083         hw_stats->rx_bytes += rd64(hw, TXGBE_DMARXOCTL);
2084         hw_stats->tx_bytes += rd64(hw, TXGBE_DMATXOCTL);
2085         hw_stats->rx_dma_drop += rd32(hw, TXGBE_DMARXDROP);
2086         hw_stats->rx_drop_packets += rd32(hw, TXGBE_PBRXDROP);
2087
2088         /* MAC Stats */
2089         hw_stats->rx_crc_errors += rd64(hw, TXGBE_MACRXERRCRCL);
2090         hw_stats->rx_multicast_packets += rd64(hw, TXGBE_MACRXMPKTL);
2091         hw_stats->tx_multicast_packets += rd64(hw, TXGBE_MACTXMPKTL);
2092
2093         hw_stats->rx_total_packets += rd64(hw, TXGBE_MACRXPKTL);
2094         hw_stats->tx_total_packets += rd64(hw, TXGBE_MACTXPKTL);
2095         hw_stats->rx_total_bytes += rd64(hw, TXGBE_MACRXGBOCTL);
2096
2097         hw_stats->rx_broadcast_packets += rd64(hw, TXGBE_MACRXOCTL);
2098         hw_stats->tx_broadcast_packets += rd32(hw, TXGBE_MACTXOCTL);
2099
2100         hw_stats->rx_size_64_packets += rd64(hw, TXGBE_MACRX1TO64L);
2101         hw_stats->rx_size_65_to_127_packets += rd64(hw, TXGBE_MACRX65TO127L);
2102         hw_stats->rx_size_128_to_255_packets += rd64(hw, TXGBE_MACRX128TO255L);
2103         hw_stats->rx_size_256_to_511_packets += rd64(hw, TXGBE_MACRX256TO511L);
2104         hw_stats->rx_size_512_to_1023_packets +=
2105                         rd64(hw, TXGBE_MACRX512TO1023L);
2106         hw_stats->rx_size_1024_to_max_packets +=
2107                         rd64(hw, TXGBE_MACRX1024TOMAXL);
2108         hw_stats->tx_size_64_packets += rd64(hw, TXGBE_MACTX1TO64L);
2109         hw_stats->tx_size_65_to_127_packets += rd64(hw, TXGBE_MACTX65TO127L);
2110         hw_stats->tx_size_128_to_255_packets += rd64(hw, TXGBE_MACTX128TO255L);
2111         hw_stats->tx_size_256_to_511_packets += rd64(hw, TXGBE_MACTX256TO511L);
2112         hw_stats->tx_size_512_to_1023_packets +=
2113                         rd64(hw, TXGBE_MACTX512TO1023L);
2114         hw_stats->tx_size_1024_to_max_packets +=
2115                         rd64(hw, TXGBE_MACTX1024TOMAXL);
2116
2117         hw_stats->rx_undersize_errors += rd64(hw, TXGBE_MACRXERRLENL);
2118         hw_stats->rx_oversize_errors += rd32(hw, TXGBE_MACRXOVERSIZE);
2119         hw_stats->rx_jabber_errors += rd32(hw, TXGBE_MACRXJABBER);
2120
2121         /* MNG Stats */
2122         hw_stats->mng_bmc2host_packets = rd32(hw, TXGBE_MNGBMC2OS);
2123         hw_stats->mng_host2bmc_packets = rd32(hw, TXGBE_MNGOS2BMC);
2124         hw_stats->rx_management_packets = rd32(hw, TXGBE_DMARXMNG);
2125         hw_stats->tx_management_packets = rd32(hw, TXGBE_DMATXMNG);
2126
2127         /* FCoE Stats */
2128         hw_stats->rx_fcoe_crc_errors += rd32(hw, TXGBE_FCOECRC);
2129         hw_stats->rx_fcoe_mbuf_allocation_errors += rd32(hw, TXGBE_FCOELAST);
2130         hw_stats->rx_fcoe_dropped += rd32(hw, TXGBE_FCOERPDC);
2131         hw_stats->rx_fcoe_packets += rd32(hw, TXGBE_FCOEPRC);
2132         hw_stats->tx_fcoe_packets += rd32(hw, TXGBE_FCOEPTC);
2133         hw_stats->rx_fcoe_bytes += rd32(hw, TXGBE_FCOEDWRC);
2134         hw_stats->tx_fcoe_bytes += rd32(hw, TXGBE_FCOEDWTC);
2135
2136         /* Flow Director Stats */
2137         hw_stats->flow_director_matched_filters += rd32(hw, TXGBE_FDIRMATCH);
2138         hw_stats->flow_director_missed_filters += rd32(hw, TXGBE_FDIRMISS);
2139         hw_stats->flow_director_added_filters +=
2140                 TXGBE_FDIRUSED_ADD(rd32(hw, TXGBE_FDIRUSED));
2141         hw_stats->flow_director_removed_filters +=
2142                 TXGBE_FDIRUSED_REM(rd32(hw, TXGBE_FDIRUSED));
2143         hw_stats->flow_director_filter_add_errors +=
2144                 TXGBE_FDIRFAIL_ADD(rd32(hw, TXGBE_FDIRFAIL));
2145         hw_stats->flow_director_filter_remove_errors +=
2146                 TXGBE_FDIRFAIL_REM(rd32(hw, TXGBE_FDIRFAIL));
2147
2148         /* MACsec Stats */
2149         hw_stats->tx_macsec_pkts_untagged += rd32(hw, TXGBE_LSECTX_UTPKT);
2150         hw_stats->tx_macsec_pkts_encrypted +=
2151                         rd32(hw, TXGBE_LSECTX_ENCPKT);
2152         hw_stats->tx_macsec_pkts_protected +=
2153                         rd32(hw, TXGBE_LSECTX_PROTPKT);
2154         hw_stats->tx_macsec_octets_encrypted +=
2155                         rd32(hw, TXGBE_LSECTX_ENCOCT);
2156         hw_stats->tx_macsec_octets_protected +=
2157                         rd32(hw, TXGBE_LSECTX_PROTOCT);
2158         hw_stats->rx_macsec_pkts_untagged += rd32(hw, TXGBE_LSECRX_UTPKT);
2159         hw_stats->rx_macsec_pkts_badtag += rd32(hw, TXGBE_LSECRX_BTPKT);
2160         hw_stats->rx_macsec_pkts_nosci += rd32(hw, TXGBE_LSECRX_NOSCIPKT);
2161         hw_stats->rx_macsec_pkts_unknownsci += rd32(hw, TXGBE_LSECRX_UNSCIPKT);
2162         hw_stats->rx_macsec_octets_decrypted += rd32(hw, TXGBE_LSECRX_DECOCT);
2163         hw_stats->rx_macsec_octets_validated += rd32(hw, TXGBE_LSECRX_VLDOCT);
2164         hw_stats->rx_macsec_sc_pkts_unchecked +=
2165                         rd32(hw, TXGBE_LSECRX_UNCHKPKT);
2166         hw_stats->rx_macsec_sc_pkts_delayed += rd32(hw, TXGBE_LSECRX_DLYPKT);
2167         hw_stats->rx_macsec_sc_pkts_late += rd32(hw, TXGBE_LSECRX_LATEPKT);
2168         for (i = 0; i < 2; i++) {
2169                 hw_stats->rx_macsec_sa_pkts_ok +=
2170                         rd32(hw, TXGBE_LSECRX_OKPKT(i));
2171                 hw_stats->rx_macsec_sa_pkts_invalid +=
2172                         rd32(hw, TXGBE_LSECRX_INVPKT(i));
2173                 hw_stats->rx_macsec_sa_pkts_notvalid +=
2174                         rd32(hw, TXGBE_LSECRX_BADPKT(i));
2175         }
2176         hw_stats->rx_macsec_sa_pkts_unusedsa +=
2177                         rd32(hw, TXGBE_LSECRX_INVSAPKT);
2178         hw_stats->rx_macsec_sa_pkts_notusingsa +=
2179                         rd32(hw, TXGBE_LSECRX_BADSAPKT);
2180
2181         hw_stats->rx_total_missed_packets = 0;
2182         for (i = 0; i < TXGBE_MAX_UP; i++) {
2183                 hw_stats->rx_total_missed_packets +=
2184                         hw_stats->up[i].rx_up_dropped;
2185         }
2186 }
2187
2188 static int
2189 txgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2190 {
2191         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2192         struct txgbe_hw_stats *hw_stats = TXGBE_DEV_STATS(dev);
2193         struct txgbe_stat_mappings *stat_mappings =
2194                         TXGBE_DEV_STAT_MAPPINGS(dev);
2195         uint32_t i, j;
2196
2197         txgbe_read_stats_registers(hw, hw_stats);
2198
2199         if (stats == NULL)
2200                 return -EINVAL;
2201
2202         /* Fill out the rte_eth_stats statistics structure */
2203         stats->ipackets = hw_stats->rx_packets;
2204         stats->ibytes = hw_stats->rx_bytes;
2205         stats->opackets = hw_stats->tx_packets;
2206         stats->obytes = hw_stats->tx_bytes;
2207
2208         memset(&stats->q_ipackets, 0, sizeof(stats->q_ipackets));
2209         memset(&stats->q_opackets, 0, sizeof(stats->q_opackets));
2210         memset(&stats->q_ibytes, 0, sizeof(stats->q_ibytes));
2211         memset(&stats->q_obytes, 0, sizeof(stats->q_obytes));
2212         memset(&stats->q_errors, 0, sizeof(stats->q_errors));
2213         for (i = 0; i < TXGBE_MAX_QP; i++) {
2214                 uint32_t n = i / NB_QMAP_FIELDS_PER_QSM_REG;
2215                 uint32_t offset = (i % NB_QMAP_FIELDS_PER_QSM_REG) * 8;
2216                 uint32_t q_map;
2217
2218                 q_map = (stat_mappings->rqsm[n] >> offset)
2219                                 & QMAP_FIELD_RESERVED_BITS_MASK;
2220                 j = (q_map < RTE_ETHDEV_QUEUE_STAT_CNTRS
2221                      ? q_map : q_map % RTE_ETHDEV_QUEUE_STAT_CNTRS);
2222                 stats->q_ipackets[j] += hw_stats->qp[i].rx_qp_packets;
2223                 stats->q_ibytes[j] += hw_stats->qp[i].rx_qp_bytes;
2224
2225                 q_map = (stat_mappings->tqsm[n] >> offset)
2226                                 & QMAP_FIELD_RESERVED_BITS_MASK;
2227                 j = (q_map < RTE_ETHDEV_QUEUE_STAT_CNTRS
2228                      ? q_map : q_map % RTE_ETHDEV_QUEUE_STAT_CNTRS);
2229                 stats->q_opackets[j] += hw_stats->qp[i].tx_qp_packets;
2230                 stats->q_obytes[j] += hw_stats->qp[i].tx_qp_bytes;
2231         }
2232
2233         /* Rx Errors */
2234         stats->imissed  = hw_stats->rx_total_missed_packets +
2235                           hw_stats->rx_dma_drop;
2236         stats->ierrors  = hw_stats->rx_crc_errors +
2237                           hw_stats->rx_mac_short_packet_dropped +
2238                           hw_stats->rx_length_errors +
2239                           hw_stats->rx_undersize_errors +
2240                           hw_stats->rx_oversize_errors +
2241                           hw_stats->rx_drop_packets +
2242                           hw_stats->rx_illegal_byte_errors +
2243                           hw_stats->rx_error_bytes +
2244                           hw_stats->rx_fragment_errors +
2245                           hw_stats->rx_fcoe_crc_errors +
2246                           hw_stats->rx_fcoe_mbuf_allocation_errors;
2247
2248         /* Tx Errors */
2249         stats->oerrors  = 0;
2250         return 0;
2251 }
2252
2253 static int
2254 txgbe_dev_stats_reset(struct rte_eth_dev *dev)
2255 {
2256         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2257         struct txgbe_hw_stats *hw_stats = TXGBE_DEV_STATS(dev);
2258
2259         /* HW registers are cleared on read */
2260         hw->offset_loaded = 0;
2261         txgbe_dev_stats_get(dev, NULL);
2262         hw->offset_loaded = 1;
2263
2264         /* Reset software totals */
2265         memset(hw_stats, 0, sizeof(*hw_stats));
2266
2267         return 0;
2268 }
2269
2270 /* This function calculates the number of xstats based on the current config */
2271 static unsigned
2272 txgbe_xstats_calc_num(struct rte_eth_dev *dev)
2273 {
2274         int nb_queues = max(dev->data->nb_rx_queues, dev->data->nb_tx_queues);
2275         return TXGBE_NB_HW_STATS +
2276                TXGBE_NB_UP_STATS * TXGBE_MAX_UP +
2277                TXGBE_NB_QP_STATS * nb_queues;
2278 }
2279
2280 static inline int
2281 txgbe_get_name_by_id(uint32_t id, char *name, uint32_t size)
2282 {
2283         int nb, st;
2284
2285         /* Extended stats from txgbe_hw_stats */
2286         if (id < TXGBE_NB_HW_STATS) {
2287                 snprintf(name, size, "[hw]%s",
2288                         rte_txgbe_stats_strings[id].name);
2289                 return 0;
2290         }
2291         id -= TXGBE_NB_HW_STATS;
2292
2293         /* Priority Stats */
2294         if (id < TXGBE_NB_UP_STATS * TXGBE_MAX_UP) {
2295                 nb = id / TXGBE_NB_UP_STATS;
2296                 st = id % TXGBE_NB_UP_STATS;
2297                 snprintf(name, size, "[p%u]%s", nb,
2298                         rte_txgbe_up_strings[st].name);
2299                 return 0;
2300         }
2301         id -= TXGBE_NB_UP_STATS * TXGBE_MAX_UP;
2302
2303         /* Queue Stats */
2304         if (id < TXGBE_NB_QP_STATS * TXGBE_MAX_QP) {
2305                 nb = id / TXGBE_NB_QP_STATS;
2306                 st = id % TXGBE_NB_QP_STATS;
2307                 snprintf(name, size, "[q%u]%s", nb,
2308                         rte_txgbe_qp_strings[st].name);
2309                 return 0;
2310         }
2311         id -= TXGBE_NB_QP_STATS * TXGBE_MAX_QP;
2312
2313         return -(int)(id + 1);
2314 }
2315
2316 static inline int
2317 txgbe_get_offset_by_id(uint32_t id, uint32_t *offset)
2318 {
2319         int nb, st;
2320
2321         /* Extended stats from txgbe_hw_stats */
2322         if (id < TXGBE_NB_HW_STATS) {
2323                 *offset = rte_txgbe_stats_strings[id].offset;
2324                 return 0;
2325         }
2326         id -= TXGBE_NB_HW_STATS;
2327
2328         /* Priority Stats */
2329         if (id < TXGBE_NB_UP_STATS * TXGBE_MAX_UP) {
2330                 nb = id / TXGBE_NB_UP_STATS;
2331                 st = id % TXGBE_NB_UP_STATS;
2332                 *offset = rte_txgbe_up_strings[st].offset +
2333                         nb * (TXGBE_NB_UP_STATS * sizeof(uint64_t));
2334                 return 0;
2335         }
2336         id -= TXGBE_NB_UP_STATS * TXGBE_MAX_UP;
2337
2338         /* Queue Stats */
2339         if (id < TXGBE_NB_QP_STATS * TXGBE_MAX_QP) {
2340                 nb = id / TXGBE_NB_QP_STATS;
2341                 st = id % TXGBE_NB_QP_STATS;
2342                 *offset = rte_txgbe_qp_strings[st].offset +
2343                         nb * (TXGBE_NB_QP_STATS * sizeof(uint64_t));
2344                 return 0;
2345         }
2346
2347         return -1;
2348 }
2349
2350 static int txgbe_dev_xstats_get_names(struct rte_eth_dev *dev,
2351         struct rte_eth_xstat_name *xstats_names, unsigned int limit)
2352 {
2353         unsigned int i, count;
2354
2355         count = txgbe_xstats_calc_num(dev);
2356         if (xstats_names == NULL)
2357                 return count;
2358
2359         /* Note: limit >= cnt_stats checked upstream
2360          * in rte_eth_xstats_names()
2361          */
2362         limit = min(limit, count);
2363
2364         /* Extended stats from txgbe_hw_stats */
2365         for (i = 0; i < limit; i++) {
2366                 if (txgbe_get_name_by_id(i, xstats_names[i].name,
2367                         sizeof(xstats_names[i].name))) {
2368                         PMD_INIT_LOG(WARNING, "id value %d isn't valid", i);
2369                         break;
2370                 }
2371         }
2372
2373         return i;
2374 }
2375
2376 static int txgbe_dev_xstats_get_names_by_id(struct rte_eth_dev *dev,
2377         struct rte_eth_xstat_name *xstats_names,
2378         const uint64_t *ids,
2379         unsigned int limit)
2380 {
2381         unsigned int i;
2382
2383         if (ids == NULL)
2384                 return txgbe_dev_xstats_get_names(dev, xstats_names, limit);
2385
2386         for (i = 0; i < limit; i++) {
2387                 if (txgbe_get_name_by_id(ids[i], xstats_names[i].name,
2388                                 sizeof(xstats_names[i].name))) {
2389                         PMD_INIT_LOG(WARNING, "id value %d isn't valid", i);
2390                         return -1;
2391                 }
2392         }
2393
2394         return i;
2395 }
2396
2397 static int
2398 txgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2399                                          unsigned int limit)
2400 {
2401         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2402         struct txgbe_hw_stats *hw_stats = TXGBE_DEV_STATS(dev);
2403         unsigned int i, count;
2404
2405         txgbe_read_stats_registers(hw, hw_stats);
2406
2407         /* If this is a reset xstats is NULL, and we have cleared the
2408          * registers by reading them.
2409          */
2410         count = txgbe_xstats_calc_num(dev);
2411         if (xstats == NULL)
2412                 return count;
2413
2414         limit = min(limit, txgbe_xstats_calc_num(dev));
2415
2416         /* Extended stats from txgbe_hw_stats */
2417         for (i = 0; i < limit; i++) {
2418                 uint32_t offset = 0;
2419
2420                 if (txgbe_get_offset_by_id(i, &offset)) {
2421                         PMD_INIT_LOG(WARNING, "id value %d isn't valid", i);
2422                         break;
2423                 }
2424                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) + offset);
2425                 xstats[i].id = i;
2426         }
2427
2428         return i;
2429 }
2430
2431 static int
2432 txgbe_dev_xstats_get_(struct rte_eth_dev *dev, uint64_t *values,
2433                                          unsigned int limit)
2434 {
2435         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2436         struct txgbe_hw_stats *hw_stats = TXGBE_DEV_STATS(dev);
2437         unsigned int i, count;
2438
2439         txgbe_read_stats_registers(hw, hw_stats);
2440
2441         /* If this is a reset xstats is NULL, and we have cleared the
2442          * registers by reading them.
2443          */
2444         count = txgbe_xstats_calc_num(dev);
2445         if (values == NULL)
2446                 return count;
2447
2448         limit = min(limit, txgbe_xstats_calc_num(dev));
2449
2450         /* Extended stats from txgbe_hw_stats */
2451         for (i = 0; i < limit; i++) {
2452                 uint32_t offset;
2453
2454                 if (txgbe_get_offset_by_id(i, &offset)) {
2455                         PMD_INIT_LOG(WARNING, "id value %d isn't valid", i);
2456                         break;
2457                 }
2458                 values[i] = *(uint64_t *)(((char *)hw_stats) + offset);
2459         }
2460
2461         return i;
2462 }
2463
2464 static int
2465 txgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
2466                 uint64_t *values, unsigned int limit)
2467 {
2468         struct txgbe_hw_stats *hw_stats = TXGBE_DEV_STATS(dev);
2469         unsigned int i;
2470
2471         if (ids == NULL)
2472                 return txgbe_dev_xstats_get_(dev, values, limit);
2473
2474         for (i = 0; i < limit; i++) {
2475                 uint32_t offset;
2476
2477                 if (txgbe_get_offset_by_id(ids[i], &offset)) {
2478                         PMD_INIT_LOG(WARNING, "id value %d isn't valid", i);
2479                         break;
2480                 }
2481                 values[i] = *(uint64_t *)(((char *)hw_stats) + offset);
2482         }
2483
2484         return i;
2485 }
2486
2487 static int
2488 txgbe_dev_xstats_reset(struct rte_eth_dev *dev)
2489 {
2490         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2491         struct txgbe_hw_stats *hw_stats = TXGBE_DEV_STATS(dev);
2492
2493         /* HW registers are cleared on read */
2494         hw->offset_loaded = 0;
2495         txgbe_read_stats_registers(hw, hw_stats);
2496         hw->offset_loaded = 1;
2497
2498         /* Reset software totals */
2499         memset(hw_stats, 0, sizeof(*hw_stats));
2500
2501         return 0;
2502 }
2503
2504 static int
2505 txgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
2506 {
2507         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2508         u32 etrack_id;
2509         int ret;
2510
2511         hw->phy.get_fw_version(hw, &etrack_id);
2512
2513         ret = snprintf(fw_version, fw_size, "0x%08x", etrack_id);
2514
2515         ret += 1; /* add the size of '\0' */
2516         if (fw_size < (u32)ret)
2517                 return ret;
2518         else
2519                 return 0;
2520 }
2521
2522 static int
2523 txgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2524 {
2525         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2526         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2527
2528         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
2529         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
2530         dev_info->min_rx_bufsize = 1024;
2531         dev_info->max_rx_pktlen = 15872;
2532         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
2533         dev_info->max_hash_mac_addrs = TXGBE_VMDQ_NUM_UC_MAC;
2534         dev_info->max_vfs = pci_dev->max_vfs;
2535         dev_info->max_vmdq_pools = ETH_64_POOLS;
2536         dev_info->vmdq_queue_num = dev_info->max_rx_queues;
2537         dev_info->rx_queue_offload_capa = txgbe_get_rx_queue_offloads(dev);
2538         dev_info->rx_offload_capa = (txgbe_get_rx_port_offloads(dev) |
2539                                      dev_info->rx_queue_offload_capa);
2540         dev_info->tx_queue_offload_capa = txgbe_get_tx_queue_offloads(dev);
2541         dev_info->tx_offload_capa = txgbe_get_tx_port_offloads(dev);
2542
2543         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2544                 .rx_thresh = {
2545                         .pthresh = TXGBE_DEFAULT_RX_PTHRESH,
2546                         .hthresh = TXGBE_DEFAULT_RX_HTHRESH,
2547                         .wthresh = TXGBE_DEFAULT_RX_WTHRESH,
2548                 },
2549                 .rx_free_thresh = TXGBE_DEFAULT_RX_FREE_THRESH,
2550                 .rx_drop_en = 0,
2551                 .offloads = 0,
2552         };
2553
2554         dev_info->default_txconf = (struct rte_eth_txconf) {
2555                 .tx_thresh = {
2556                         .pthresh = TXGBE_DEFAULT_TX_PTHRESH,
2557                         .hthresh = TXGBE_DEFAULT_TX_HTHRESH,
2558                         .wthresh = TXGBE_DEFAULT_TX_WTHRESH,
2559                 },
2560                 .tx_free_thresh = TXGBE_DEFAULT_TX_FREE_THRESH,
2561                 .offloads = 0,
2562         };
2563
2564         dev_info->rx_desc_lim = rx_desc_lim;
2565         dev_info->tx_desc_lim = tx_desc_lim;
2566
2567         dev_info->hash_key_size = TXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
2568         dev_info->reta_size = ETH_RSS_RETA_SIZE_128;
2569         dev_info->flow_type_rss_offloads = TXGBE_RSS_OFFLOAD_ALL;
2570
2571         dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
2572         dev_info->speed_capa |= ETH_LINK_SPEED_100M;
2573
2574         /* Driver-preferred Rx/Tx parameters */
2575         dev_info->default_rxportconf.burst_size = 32;
2576         dev_info->default_txportconf.burst_size = 32;
2577         dev_info->default_rxportconf.nb_queues = 1;
2578         dev_info->default_txportconf.nb_queues = 1;
2579         dev_info->default_rxportconf.ring_size = 256;
2580         dev_info->default_txportconf.ring_size = 256;
2581
2582         return 0;
2583 }
2584
2585 const uint32_t *
2586 txgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev)
2587 {
2588         if (dev->rx_pkt_burst == txgbe_recv_pkts ||
2589             dev->rx_pkt_burst == txgbe_recv_pkts_lro_single_alloc ||
2590             dev->rx_pkt_burst == txgbe_recv_pkts_lro_bulk_alloc ||
2591             dev->rx_pkt_burst == txgbe_recv_pkts_bulk_alloc)
2592                 return txgbe_get_supported_ptypes();
2593
2594         return NULL;
2595 }
2596
2597 void
2598 txgbe_dev_setup_link_alarm_handler(void *param)
2599 {
2600         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2601         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2602         struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);
2603         u32 speed;
2604         bool autoneg = false;
2605
2606         speed = hw->phy.autoneg_advertised;
2607         if (!speed)
2608                 hw->mac.get_link_capabilities(hw, &speed, &autoneg);
2609
2610         hw->mac.setup_link(hw, speed, true);
2611
2612         intr->flags &= ~TXGBE_FLAG_NEED_LINK_CONFIG;
2613 }
2614
2615 /* return 0 means link status changed, -1 means not changed */
2616 int
2617 txgbe_dev_link_update_share(struct rte_eth_dev *dev,
2618                             int wait_to_complete)
2619 {
2620         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2621         struct rte_eth_link link;
2622         u32 link_speed = TXGBE_LINK_SPEED_UNKNOWN;
2623         struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);
2624         bool link_up;
2625         int err;
2626         int wait = 1;
2627
2628         memset(&link, 0, sizeof(link));
2629         link.link_status = ETH_LINK_DOWN;
2630         link.link_speed = ETH_SPEED_NUM_NONE;
2631         link.link_duplex = ETH_LINK_HALF_DUPLEX;
2632         link.link_autoneg = ETH_LINK_AUTONEG;
2633
2634         hw->mac.get_link_status = true;
2635
2636         if (intr->flags & TXGBE_FLAG_NEED_LINK_CONFIG)
2637                 return rte_eth_linkstatus_set(dev, &link);
2638
2639         /* check if it needs to wait to complete, if lsc interrupt is enabled */
2640         if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
2641                 wait = 0;
2642
2643         err = hw->mac.check_link(hw, &link_speed, &link_up, wait);
2644
2645         if (err != 0) {
2646                 link.link_speed = ETH_SPEED_NUM_100M;
2647                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
2648                 return rte_eth_linkstatus_set(dev, &link);
2649         }
2650
2651         if (link_up == 0) {
2652                 if (hw->phy.media_type == txgbe_media_type_fiber) {
2653                         intr->flags |= TXGBE_FLAG_NEED_LINK_CONFIG;
2654                         rte_eal_alarm_set(10,
2655                                 txgbe_dev_setup_link_alarm_handler, dev);
2656                 }
2657                 return rte_eth_linkstatus_set(dev, &link);
2658         }
2659
2660         intr->flags &= ~TXGBE_FLAG_NEED_LINK_CONFIG;
2661         link.link_status = ETH_LINK_UP;
2662         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2663
2664         switch (link_speed) {
2665         default:
2666         case TXGBE_LINK_SPEED_UNKNOWN:
2667                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
2668                 link.link_speed = ETH_SPEED_NUM_100M;
2669                 break;
2670
2671         case TXGBE_LINK_SPEED_100M_FULL:
2672                 link.link_speed = ETH_SPEED_NUM_100M;
2673                 break;
2674
2675         case TXGBE_LINK_SPEED_1GB_FULL:
2676                 link.link_speed = ETH_SPEED_NUM_1G;
2677                 break;
2678
2679         case TXGBE_LINK_SPEED_2_5GB_FULL:
2680                 link.link_speed = ETH_SPEED_NUM_2_5G;
2681                 break;
2682
2683         case TXGBE_LINK_SPEED_5GB_FULL:
2684                 link.link_speed = ETH_SPEED_NUM_5G;
2685                 break;
2686
2687         case TXGBE_LINK_SPEED_10GB_FULL:
2688                 link.link_speed = ETH_SPEED_NUM_10G;
2689                 break;
2690         }
2691
2692         return rte_eth_linkstatus_set(dev, &link);
2693 }
2694
2695 static int
2696 txgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
2697 {
2698         return txgbe_dev_link_update_share(dev, wait_to_complete);
2699 }
2700
2701 static int
2702 txgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
2703 {
2704         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2705         uint32_t fctrl;
2706
2707         fctrl = rd32(hw, TXGBE_PSRCTL);
2708         fctrl |= (TXGBE_PSRCTL_UCP | TXGBE_PSRCTL_MCP);
2709         wr32(hw, TXGBE_PSRCTL, fctrl);
2710
2711         return 0;
2712 }
2713
2714 static int
2715 txgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
2716 {
2717         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2718         uint32_t fctrl;
2719
2720         fctrl = rd32(hw, TXGBE_PSRCTL);
2721         fctrl &= (~TXGBE_PSRCTL_UCP);
2722         if (dev->data->all_multicast == 1)
2723                 fctrl |= TXGBE_PSRCTL_MCP;
2724         else
2725                 fctrl &= (~TXGBE_PSRCTL_MCP);
2726         wr32(hw, TXGBE_PSRCTL, fctrl);
2727
2728         return 0;
2729 }
2730
2731 static int
2732 txgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
2733 {
2734         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2735         uint32_t fctrl;
2736
2737         fctrl = rd32(hw, TXGBE_PSRCTL);
2738         fctrl |= TXGBE_PSRCTL_MCP;
2739         wr32(hw, TXGBE_PSRCTL, fctrl);
2740
2741         return 0;
2742 }
2743
2744 static int
2745 txgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
2746 {
2747         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2748         uint32_t fctrl;
2749
2750         if (dev->data->promiscuous == 1)
2751                 return 0; /* must remain in all_multicast mode */
2752
2753         fctrl = rd32(hw, TXGBE_PSRCTL);
2754         fctrl &= (~TXGBE_PSRCTL_MCP);
2755         wr32(hw, TXGBE_PSRCTL, fctrl);
2756
2757         return 0;
2758 }
2759
2760 /**
2761  * It clears the interrupt causes and enables the interrupt.
2762  * It will be called once only during nic initialized.
2763  *
2764  * @param dev
2765  *  Pointer to struct rte_eth_dev.
2766  * @param on
2767  *  Enable or Disable.
2768  *
2769  * @return
2770  *  - On success, zero.
2771  *  - On failure, a negative value.
2772  */
2773 static int
2774 txgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on)
2775 {
2776         struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);
2777
2778         txgbe_dev_link_status_print(dev);
2779         if (on)
2780                 intr->mask_misc |= TXGBE_ICRMISC_LSC;
2781         else
2782                 intr->mask_misc &= ~TXGBE_ICRMISC_LSC;
2783
2784         return 0;
2785 }
2786
2787 /**
2788  * It clears the interrupt causes and enables the interrupt.
2789  * It will be called once only during nic initialized.
2790  *
2791  * @param dev
2792  *  Pointer to struct rte_eth_dev.
2793  *
2794  * @return
2795  *  - On success, zero.
2796  *  - On failure, a negative value.
2797  */
2798 static int
2799 txgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
2800 {
2801         struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);
2802
2803         intr->mask[0] |= TXGBE_ICR_MASK;
2804         intr->mask[1] |= TXGBE_ICR_MASK;
2805
2806         return 0;
2807 }
2808
2809 /**
2810  * It clears the interrupt causes and enables the interrupt.
2811  * It will be called once only during nic initialized.
2812  *
2813  * @param dev
2814  *  Pointer to struct rte_eth_dev.
2815  *
2816  * @return
2817  *  - On success, zero.
2818  *  - On failure, a negative value.
2819  */
2820 static int
2821 txgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev)
2822 {
2823         struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);
2824
2825         intr->mask_misc |= TXGBE_ICRMISC_LNKSEC;
2826
2827         return 0;
2828 }
2829
2830 /*
2831  * It reads ICR and sets flag (TXGBE_ICRMISC_LSC) for the link_update.
2832  *
2833  * @param dev
2834  *  Pointer to struct rte_eth_dev.
2835  *
2836  * @return
2837  *  - On success, zero.
2838  *  - On failure, a negative value.
2839  */
2840 static int
2841 txgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
2842 {
2843         uint32_t eicr;
2844         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2845         struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);
2846
2847         /* clear all cause mask */
2848         txgbe_disable_intr(hw);
2849
2850         /* read-on-clear nic registers here */
2851         eicr = ((u32 *)hw->isb_mem)[TXGBE_ISB_MISC];
2852         PMD_DRV_LOG(DEBUG, "eicr %x", eicr);
2853
2854         intr->flags = 0;
2855
2856         /* set flag for async link update */
2857         if (eicr & TXGBE_ICRMISC_LSC)
2858                 intr->flags |= TXGBE_FLAG_NEED_LINK_UPDATE;
2859
2860         if (eicr & TXGBE_ICRMISC_VFMBX)
2861                 intr->flags |= TXGBE_FLAG_MAILBOX;
2862
2863         if (eicr & TXGBE_ICRMISC_LNKSEC)
2864                 intr->flags |= TXGBE_FLAG_MACSEC;
2865
2866         if (eicr & TXGBE_ICRMISC_GPIO)
2867                 intr->flags |= TXGBE_FLAG_PHY_INTERRUPT;
2868
2869         return 0;
2870 }
2871
2872 /**
2873  * It gets and then prints the link status.
2874  *
2875  * @param dev
2876  *  Pointer to struct rte_eth_dev.
2877  *
2878  * @return
2879  *  - On success, zero.
2880  *  - On failure, a negative value.
2881  */
2882 static void
2883 txgbe_dev_link_status_print(struct rte_eth_dev *dev)
2884 {
2885         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2886         struct rte_eth_link link;
2887
2888         rte_eth_linkstatus_get(dev, &link);
2889
2890         if (link.link_status) {
2891                 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
2892                                         (int)(dev->data->port_id),
2893                                         (unsigned int)link.link_speed,
2894                         link.link_duplex == ETH_LINK_FULL_DUPLEX ?
2895                                         "full-duplex" : "half-duplex");
2896         } else {
2897                 PMD_INIT_LOG(INFO, " Port %d: Link Down",
2898                                 (int)(dev->data->port_id));
2899         }
2900         PMD_INIT_LOG(DEBUG, "PCI Address: " PCI_PRI_FMT,
2901                                 pci_dev->addr.domain,
2902                                 pci_dev->addr.bus,
2903                                 pci_dev->addr.devid,
2904                                 pci_dev->addr.function);
2905 }
2906
2907 /*
2908  * It executes link_update after knowing an interrupt occurred.
2909  *
2910  * @param dev
2911  *  Pointer to struct rte_eth_dev.
2912  *
2913  * @return
2914  *  - On success, zero.
2915  *  - On failure, a negative value.
2916  */
2917 static int
2918 txgbe_dev_interrupt_action(struct rte_eth_dev *dev,
2919                            struct rte_intr_handle *intr_handle)
2920 {
2921         struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);
2922         int64_t timeout;
2923         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2924
2925         PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
2926
2927         if (intr->flags & TXGBE_FLAG_MAILBOX) {
2928                 txgbe_pf_mbx_process(dev);
2929                 intr->flags &= ~TXGBE_FLAG_MAILBOX;
2930         }
2931
2932         if (intr->flags & TXGBE_FLAG_PHY_INTERRUPT) {
2933                 hw->phy.handle_lasi(hw);
2934                 intr->flags &= ~TXGBE_FLAG_PHY_INTERRUPT;
2935         }
2936
2937         if (intr->flags & TXGBE_FLAG_NEED_LINK_UPDATE) {
2938                 struct rte_eth_link link;
2939
2940                 /*get the link status before link update, for predicting later*/
2941                 rte_eth_linkstatus_get(dev, &link);
2942
2943                 txgbe_dev_link_update(dev, 0);
2944
2945                 /* likely to up */
2946                 if (!link.link_status)
2947                         /* handle it 1 sec later, wait it being stable */
2948                         timeout = TXGBE_LINK_UP_CHECK_TIMEOUT;
2949                 /* likely to down */
2950                 else
2951                         /* handle it 4 sec later, wait it being stable */
2952                         timeout = TXGBE_LINK_DOWN_CHECK_TIMEOUT;
2953
2954                 txgbe_dev_link_status_print(dev);
2955                 if (rte_eal_alarm_set(timeout * 1000,
2956                                       txgbe_dev_interrupt_delayed_handler,
2957                                       (void *)dev) < 0) {
2958                         PMD_DRV_LOG(ERR, "Error setting alarm");
2959                 } else {
2960                         /* remember original mask */
2961                         intr->mask_misc_orig = intr->mask_misc;
2962                         /* only disable lsc interrupt */
2963                         intr->mask_misc &= ~TXGBE_ICRMISC_LSC;
2964                 }
2965         }
2966
2967         PMD_DRV_LOG(DEBUG, "enable intr immediately");
2968         txgbe_enable_intr(dev);
2969         rte_intr_enable(intr_handle);
2970
2971         return 0;
2972 }
2973
2974 /**
2975  * Interrupt handler which shall be registered for alarm callback for delayed
2976  * handling specific interrupt to wait for the stable nic state. As the
2977  * NIC interrupt state is not stable for txgbe after link is just down,
2978  * it needs to wait 4 seconds to get the stable status.
2979  *
2980  * @param handle
2981  *  Pointer to interrupt handle.
2982  * @param param
2983  *  The address of parameter (struct rte_eth_dev *) registered before.
2984  *
2985  * @return
2986  *  void
2987  */
2988 static void
2989 txgbe_dev_interrupt_delayed_handler(void *param)
2990 {
2991         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2992         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2993         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2994         struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);
2995         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2996         uint32_t eicr;
2997
2998         txgbe_disable_intr(hw);
2999
3000         eicr = ((u32 *)hw->isb_mem)[TXGBE_ISB_MISC];
3001         if (eicr & TXGBE_ICRMISC_VFMBX)
3002                 txgbe_pf_mbx_process(dev);
3003
3004         if (intr->flags & TXGBE_FLAG_PHY_INTERRUPT) {
3005                 hw->phy.handle_lasi(hw);
3006                 intr->flags &= ~TXGBE_FLAG_PHY_INTERRUPT;
3007         }
3008
3009         if (intr->flags & TXGBE_FLAG_NEED_LINK_UPDATE) {
3010                 txgbe_dev_link_update(dev, 0);
3011                 intr->flags &= ~TXGBE_FLAG_NEED_LINK_UPDATE;
3012                 txgbe_dev_link_status_print(dev);
3013                 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC,
3014                                               NULL);
3015         }
3016
3017         if (intr->flags & TXGBE_FLAG_MACSEC) {
3018                 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_MACSEC,
3019                                               NULL);
3020                 intr->flags &= ~TXGBE_FLAG_MACSEC;
3021         }
3022
3023         /* restore original mask */
3024         intr->mask_misc = intr->mask_misc_orig;
3025         intr->mask_misc_orig = 0;
3026
3027         PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
3028         txgbe_enable_intr(dev);
3029         rte_intr_enable(intr_handle);
3030 }
3031
3032 /**
3033  * Interrupt handler triggered by NIC  for handling
3034  * specific interrupt.
3035  *
3036  * @param handle
3037  *  Pointer to interrupt handle.
3038  * @param param
3039  *  The address of parameter (struct rte_eth_dev *) registered before.
3040  *
3041  * @return
3042  *  void
3043  */
3044 static void
3045 txgbe_dev_interrupt_handler(void *param)
3046 {
3047         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3048
3049         txgbe_dev_interrupt_get_status(dev);
3050         txgbe_dev_interrupt_action(dev, dev->intr_handle);
3051 }
3052
3053 static int
3054 txgbe_dev_led_on(struct rte_eth_dev *dev)
3055 {
3056         struct txgbe_hw *hw;
3057
3058         hw = TXGBE_DEV_HW(dev);
3059         return txgbe_led_on(hw, 4) == 0 ? 0 : -ENOTSUP;
3060 }
3061
3062 static int
3063 txgbe_dev_led_off(struct rte_eth_dev *dev)
3064 {
3065         struct txgbe_hw *hw;
3066
3067         hw = TXGBE_DEV_HW(dev);
3068         return txgbe_led_off(hw, 4) == 0 ? 0 : -ENOTSUP;
3069 }
3070
3071 static int
3072 txgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3073 {
3074         struct txgbe_hw *hw;
3075         uint32_t mflcn_reg;
3076         uint32_t fccfg_reg;
3077         int rx_pause;
3078         int tx_pause;
3079
3080         hw = TXGBE_DEV_HW(dev);
3081
3082         fc_conf->pause_time = hw->fc.pause_time;
3083         fc_conf->high_water = hw->fc.high_water[0];
3084         fc_conf->low_water = hw->fc.low_water[0];
3085         fc_conf->send_xon = hw->fc.send_xon;
3086         fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
3087
3088         /*
3089          * Return rx_pause status according to actual setting of
3090          * RXFCCFG register.
3091          */
3092         mflcn_reg = rd32(hw, TXGBE_RXFCCFG);
3093         if (mflcn_reg & (TXGBE_RXFCCFG_FC | TXGBE_RXFCCFG_PFC))
3094                 rx_pause = 1;
3095         else
3096                 rx_pause = 0;
3097
3098         /*
3099          * Return tx_pause status according to actual setting of
3100          * TXFCCFG register.
3101          */
3102         fccfg_reg = rd32(hw, TXGBE_TXFCCFG);
3103         if (fccfg_reg & (TXGBE_TXFCCFG_FC | TXGBE_TXFCCFG_PFC))
3104                 tx_pause = 1;
3105         else
3106                 tx_pause = 0;
3107
3108         if (rx_pause && tx_pause)
3109                 fc_conf->mode = RTE_FC_FULL;
3110         else if (rx_pause)
3111                 fc_conf->mode = RTE_FC_RX_PAUSE;
3112         else if (tx_pause)
3113                 fc_conf->mode = RTE_FC_TX_PAUSE;
3114         else
3115                 fc_conf->mode = RTE_FC_NONE;
3116
3117         return 0;
3118 }
3119
3120 static int
3121 txgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3122 {
3123         struct txgbe_hw *hw;
3124         int err;
3125         uint32_t rx_buf_size;
3126         uint32_t max_high_water;
3127         enum txgbe_fc_mode rte_fcmode_2_txgbe_fcmode[] = {
3128                 txgbe_fc_none,
3129                 txgbe_fc_rx_pause,
3130                 txgbe_fc_tx_pause,
3131                 txgbe_fc_full
3132         };
3133
3134         PMD_INIT_FUNC_TRACE();
3135
3136         hw = TXGBE_DEV_HW(dev);
3137         rx_buf_size = rd32(hw, TXGBE_PBRXSIZE(0));
3138         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
3139
3140         /*
3141          * At least reserve one Ethernet frame for watermark
3142          * high_water/low_water in kilo bytes for txgbe
3143          */
3144         max_high_water = (rx_buf_size - RTE_ETHER_MAX_LEN) >> 10;
3145         if (fc_conf->high_water > max_high_water ||
3146             fc_conf->high_water < fc_conf->low_water) {
3147                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
3148                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
3149                 return -EINVAL;
3150         }
3151
3152         hw->fc.requested_mode = rte_fcmode_2_txgbe_fcmode[fc_conf->mode];
3153         hw->fc.pause_time     = fc_conf->pause_time;
3154         hw->fc.high_water[0]  = fc_conf->high_water;
3155         hw->fc.low_water[0]   = fc_conf->low_water;
3156         hw->fc.send_xon       = fc_conf->send_xon;
3157         hw->fc.disable_fc_autoneg = !fc_conf->autoneg;
3158
3159         err = txgbe_fc_enable(hw);
3160
3161         /* Not negotiated is not an error case */
3162         if (err == 0 || err == TXGBE_ERR_FC_NOT_NEGOTIATED) {
3163                 wr32m(hw, TXGBE_MACRXFLT, TXGBE_MACRXFLT_CTL_MASK,
3164                       (fc_conf->mac_ctrl_frame_fwd
3165                        ? TXGBE_MACRXFLT_CTL_NOPS : TXGBE_MACRXFLT_CTL_DROP));
3166                 txgbe_flush(hw);
3167
3168                 return 0;
3169         }
3170
3171         PMD_INIT_LOG(ERR, "txgbe_fc_enable = 0x%x", err);
3172         return -EIO;
3173 }
3174
3175 static int
3176 txgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
3177                 struct rte_eth_pfc_conf *pfc_conf)
3178 {
3179         int err;
3180         uint32_t rx_buf_size;
3181         uint32_t max_high_water;
3182         uint8_t tc_num;
3183         uint8_t  map[TXGBE_DCB_UP_MAX] = { 0 };
3184         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3185         struct txgbe_dcb_config *dcb_config = TXGBE_DEV_DCB_CONFIG(dev);
3186
3187         enum txgbe_fc_mode rte_fcmode_2_txgbe_fcmode[] = {
3188                 txgbe_fc_none,
3189                 txgbe_fc_rx_pause,
3190                 txgbe_fc_tx_pause,
3191                 txgbe_fc_full
3192         };
3193
3194         PMD_INIT_FUNC_TRACE();
3195
3196         txgbe_dcb_unpack_map_cee(dcb_config, TXGBE_DCB_RX_CONFIG, map);
3197         tc_num = map[pfc_conf->priority];
3198         rx_buf_size = rd32(hw, TXGBE_PBRXSIZE(tc_num));
3199         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
3200         /*
3201          * At least reserve one Ethernet frame for watermark
3202          * high_water/low_water in kilo bytes for txgbe
3203          */
3204         max_high_water = (rx_buf_size - RTE_ETHER_MAX_LEN) >> 10;
3205         if (pfc_conf->fc.high_water > max_high_water ||
3206             pfc_conf->fc.high_water <= pfc_conf->fc.low_water) {
3207                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
3208                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
3209                 return -EINVAL;
3210         }
3211
3212         hw->fc.requested_mode = rte_fcmode_2_txgbe_fcmode[pfc_conf->fc.mode];
3213         hw->fc.pause_time = pfc_conf->fc.pause_time;
3214         hw->fc.send_xon = pfc_conf->fc.send_xon;
3215         hw->fc.low_water[tc_num] =  pfc_conf->fc.low_water;
3216         hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
3217
3218         err = txgbe_dcb_pfc_enable(hw, tc_num);
3219
3220         /* Not negotiated is not an error case */
3221         if (err == 0 || err == TXGBE_ERR_FC_NOT_NEGOTIATED)
3222                 return 0;
3223
3224         PMD_INIT_LOG(ERR, "txgbe_dcb_pfc_enable = 0x%x", err);
3225         return -EIO;
3226 }
3227
3228 int
3229 txgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
3230                           struct rte_eth_rss_reta_entry64 *reta_conf,
3231                           uint16_t reta_size)
3232 {
3233         uint8_t i, j, mask;
3234         uint32_t reta;
3235         uint16_t idx, shift;
3236         struct txgbe_adapter *adapter = TXGBE_DEV_ADAPTER(dev);
3237         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3238
3239         PMD_INIT_FUNC_TRACE();
3240
3241         if (!txgbe_rss_update_sp(hw->mac.type)) {
3242                 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this "
3243                         "NIC.");
3244                 return -ENOTSUP;
3245         }
3246
3247         if (reta_size != ETH_RSS_RETA_SIZE_128) {
3248                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3249                         "(%d) doesn't match the number hardware can supported "
3250                         "(%d)", reta_size, ETH_RSS_RETA_SIZE_128);
3251                 return -EINVAL;
3252         }
3253
3254         for (i = 0; i < reta_size; i += 4) {
3255                 idx = i / RTE_RETA_GROUP_SIZE;
3256                 shift = i % RTE_RETA_GROUP_SIZE;
3257                 mask = (uint8_t)RS64(reta_conf[idx].mask, shift, 0xF);
3258                 if (!mask)
3259                         continue;
3260
3261                 reta = rd32at(hw, TXGBE_REG_RSSTBL, i >> 2);
3262                 for (j = 0; j < 4; j++) {
3263                         if (RS8(mask, j, 0x1)) {
3264                                 reta  &= ~(MS32(8 * j, 0xFF));
3265                                 reta |= LS32(reta_conf[idx].reta[shift + j],
3266                                                 8 * j, 0xFF);
3267                         }
3268                 }
3269                 wr32at(hw, TXGBE_REG_RSSTBL, i >> 2, reta);
3270         }
3271         adapter->rss_reta_updated = 1;
3272
3273         return 0;
3274 }
3275
3276 int
3277 txgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
3278                          struct rte_eth_rss_reta_entry64 *reta_conf,
3279                          uint16_t reta_size)
3280 {
3281         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3282         uint8_t i, j, mask;
3283         uint32_t reta;
3284         uint16_t idx, shift;
3285
3286         PMD_INIT_FUNC_TRACE();
3287
3288         if (reta_size != ETH_RSS_RETA_SIZE_128) {
3289                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3290                         "(%d) doesn't match the number hardware can supported "
3291                         "(%d)", reta_size, ETH_RSS_RETA_SIZE_128);
3292                 return -EINVAL;
3293         }
3294
3295         for (i = 0; i < reta_size; i += 4) {
3296                 idx = i / RTE_RETA_GROUP_SIZE;
3297                 shift = i % RTE_RETA_GROUP_SIZE;
3298                 mask = (uint8_t)RS64(reta_conf[idx].mask, shift, 0xF);
3299                 if (!mask)
3300                         continue;
3301
3302                 reta = rd32at(hw, TXGBE_REG_RSSTBL, i >> 2);
3303                 for (j = 0; j < 4; j++) {
3304                         if (RS8(mask, j, 0x1))
3305                                 reta_conf[idx].reta[shift + j] =
3306                                         (uint16_t)RS32(reta, 8 * j, 0xFF);
3307                 }
3308         }
3309
3310         return 0;
3311 }
3312
3313 static int
3314 txgbe_add_rar(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
3315                                 uint32_t index, uint32_t pool)
3316 {
3317         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3318         uint32_t enable_addr = 1;
3319
3320         return txgbe_set_rar(hw, index, mac_addr->addr_bytes,
3321                              pool, enable_addr);
3322 }
3323
3324 static void
3325 txgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
3326 {
3327         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3328
3329         txgbe_clear_rar(hw, index);
3330 }
3331
3332 static int
3333 txgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *addr)
3334 {
3335         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3336
3337         txgbe_remove_rar(dev, 0);
3338         txgbe_add_rar(dev, addr, 0, pci_dev->max_vfs);
3339
3340         return 0;
3341 }
3342
3343 static int
3344 txgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
3345 {
3346         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3347         struct rte_eth_dev_info dev_info;
3348         uint32_t frame_size = mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN;
3349         struct rte_eth_dev_data *dev_data = dev->data;
3350         int ret;
3351
3352         ret = txgbe_dev_info_get(dev, &dev_info);
3353         if (ret != 0)
3354                 return ret;
3355
3356         /* check that mtu is within the allowed range */
3357         if (mtu < RTE_ETHER_MIN_MTU || frame_size > dev_info.max_rx_pktlen)
3358                 return -EINVAL;
3359
3360         /* If device is started, refuse mtu that requires the support of
3361          * scattered packets when this feature has not been enabled before.
3362          */
3363         if (dev_data->dev_started && !dev_data->scattered_rx &&
3364             (frame_size + 2 * TXGBE_VLAN_TAG_SIZE >
3365              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
3366                 PMD_INIT_LOG(ERR, "Stop port first.");
3367                 return -EINVAL;
3368         }
3369
3370         /* update max frame size */
3371         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
3372
3373         if (hw->mode)
3374                 wr32m(hw, TXGBE_FRMSZ, TXGBE_FRMSZ_MAX_MASK,
3375                         TXGBE_FRAME_SIZE_MAX);
3376         else
3377                 wr32m(hw, TXGBE_FRMSZ, TXGBE_FRMSZ_MAX_MASK,
3378                         TXGBE_FRMSZ_MAX(frame_size));
3379
3380         return 0;
3381 }
3382
3383 static uint32_t
3384 txgbe_uta_vector(struct txgbe_hw *hw, struct rte_ether_addr *uc_addr)
3385 {
3386         uint32_t vector = 0;
3387
3388         switch (hw->mac.mc_filter_type) {
3389         case 0:   /* use bits [47:36] of the address */
3390                 vector = ((uc_addr->addr_bytes[4] >> 4) |
3391                         (((uint16_t)uc_addr->addr_bytes[5]) << 4));
3392                 break;
3393         case 1:   /* use bits [46:35] of the address */
3394                 vector = ((uc_addr->addr_bytes[4] >> 3) |
3395                         (((uint16_t)uc_addr->addr_bytes[5]) << 5));
3396                 break;
3397         case 2:   /* use bits [45:34] of the address */
3398                 vector = ((uc_addr->addr_bytes[4] >> 2) |
3399                         (((uint16_t)uc_addr->addr_bytes[5]) << 6));
3400                 break;
3401         case 3:   /* use bits [43:32] of the address */
3402                 vector = ((uc_addr->addr_bytes[4]) |
3403                         (((uint16_t)uc_addr->addr_bytes[5]) << 8));
3404                 break;
3405         default:  /* Invalid mc_filter_type */
3406                 break;
3407         }
3408
3409         /* vector can only be 12-bits or boundary will be exceeded */
3410         vector &= 0xFFF;
3411         return vector;
3412 }
3413
3414 static int
3415 txgbe_uc_hash_table_set(struct rte_eth_dev *dev,
3416                         struct rte_ether_addr *mac_addr, uint8_t on)
3417 {
3418         uint32_t vector;
3419         uint32_t uta_idx;
3420         uint32_t reg_val;
3421         uint32_t uta_mask;
3422         uint32_t psrctl;
3423
3424         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3425         struct txgbe_uta_info *uta_info = TXGBE_DEV_UTA_INFO(dev);
3426
3427         /* The UTA table only exists on pf hardware */
3428         if (hw->mac.type < txgbe_mac_raptor)
3429                 return -ENOTSUP;
3430
3431         vector = txgbe_uta_vector(hw, mac_addr);
3432         uta_idx = (vector >> 5) & 0x7F;
3433         uta_mask = 0x1UL << (vector & 0x1F);
3434
3435         if (!!on == !!(uta_info->uta_shadow[uta_idx] & uta_mask))
3436                 return 0;
3437
3438         reg_val = rd32(hw, TXGBE_UCADDRTBL(uta_idx));
3439         if (on) {
3440                 uta_info->uta_in_use++;
3441                 reg_val |= uta_mask;
3442                 uta_info->uta_shadow[uta_idx] |= uta_mask;
3443         } else {
3444                 uta_info->uta_in_use--;
3445                 reg_val &= ~uta_mask;
3446                 uta_info->uta_shadow[uta_idx] &= ~uta_mask;
3447         }
3448
3449         wr32(hw, TXGBE_UCADDRTBL(uta_idx), reg_val);
3450
3451         psrctl = rd32(hw, TXGBE_PSRCTL);
3452         if (uta_info->uta_in_use > 0)
3453                 psrctl |= TXGBE_PSRCTL_UCHFENA;
3454         else
3455                 psrctl &= ~TXGBE_PSRCTL_UCHFENA;
3456
3457         psrctl &= ~TXGBE_PSRCTL_ADHF12_MASK;
3458         psrctl |= TXGBE_PSRCTL_ADHF12(hw->mac.mc_filter_type);
3459         wr32(hw, TXGBE_PSRCTL, psrctl);
3460
3461         return 0;
3462 }
3463
3464 static int
3465 txgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
3466 {
3467         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3468         struct txgbe_uta_info *uta_info = TXGBE_DEV_UTA_INFO(dev);
3469         uint32_t psrctl;
3470         int i;
3471
3472         /* The UTA table only exists on pf hardware */
3473         if (hw->mac.type < txgbe_mac_raptor)
3474                 return -ENOTSUP;
3475
3476         if (on) {
3477                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
3478                         uta_info->uta_shadow[i] = ~0;
3479                         wr32(hw, TXGBE_UCADDRTBL(i), ~0);
3480                 }
3481         } else {
3482                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
3483                         uta_info->uta_shadow[i] = 0;
3484                         wr32(hw, TXGBE_UCADDRTBL(i), 0);
3485                 }
3486         }
3487
3488         psrctl = rd32(hw, TXGBE_PSRCTL);
3489         if (on)
3490                 psrctl |= TXGBE_PSRCTL_UCHFENA;
3491         else
3492                 psrctl &= ~TXGBE_PSRCTL_UCHFENA;
3493
3494         psrctl &= ~TXGBE_PSRCTL_ADHF12_MASK;
3495         psrctl |= TXGBE_PSRCTL_ADHF12(hw->mac.mc_filter_type);
3496         wr32(hw, TXGBE_PSRCTL, psrctl);
3497
3498         return 0;
3499 }
3500
3501 uint32_t
3502 txgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
3503 {
3504         uint32_t new_val = orig_val;
3505
3506         if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
3507                 new_val |= TXGBE_POOLETHCTL_UTA;
3508         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
3509                 new_val |= TXGBE_POOLETHCTL_MCHA;
3510         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
3511                 new_val |= TXGBE_POOLETHCTL_UCHA;
3512         if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
3513                 new_val |= TXGBE_POOLETHCTL_BCA;
3514         if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
3515                 new_val |= TXGBE_POOLETHCTL_MCP;
3516
3517         return new_val;
3518 }
3519
3520 static int
3521 txgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
3522 {
3523         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3524         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3525         uint32_t mask;
3526         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3527
3528         if (queue_id < 32) {
3529                 mask = rd32(hw, TXGBE_IMS(0));
3530                 mask &= (1 << queue_id);
3531                 wr32(hw, TXGBE_IMS(0), mask);
3532         } else if (queue_id < 64) {
3533                 mask = rd32(hw, TXGBE_IMS(1));
3534                 mask &= (1 << (queue_id - 32));
3535                 wr32(hw, TXGBE_IMS(1), mask);
3536         }
3537         rte_intr_enable(intr_handle);
3538
3539         return 0;
3540 }
3541
3542 static int
3543 txgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
3544 {
3545         uint32_t mask;
3546         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3547
3548         if (queue_id < 32) {
3549                 mask = rd32(hw, TXGBE_IMS(0));
3550                 mask &= ~(1 << queue_id);
3551                 wr32(hw, TXGBE_IMS(0), mask);
3552         } else if (queue_id < 64) {
3553                 mask = rd32(hw, TXGBE_IMS(1));
3554                 mask &= ~(1 << (queue_id - 32));
3555                 wr32(hw, TXGBE_IMS(1), mask);
3556         }
3557
3558         return 0;
3559 }
3560
3561 /**
3562  * set the IVAR registers, mapping interrupt causes to vectors
3563  * @param hw
3564  *  pointer to txgbe_hw struct
3565  * @direction
3566  *  0 for Rx, 1 for Tx, -1 for other causes
3567  * @queue
3568  *  queue to map the corresponding interrupt to
3569  * @msix_vector
3570  *  the vector to map to the corresponding queue
3571  */
3572 void
3573 txgbe_set_ivar_map(struct txgbe_hw *hw, int8_t direction,
3574                    uint8_t queue, uint8_t msix_vector)
3575 {
3576         uint32_t tmp, idx;
3577
3578         if (direction == -1) {
3579                 /* other causes */
3580                 msix_vector |= TXGBE_IVARMISC_VLD;
3581                 idx = 0;
3582                 tmp = rd32(hw, TXGBE_IVARMISC);
3583                 tmp &= ~(0xFF << idx);
3584                 tmp |= (msix_vector << idx);
3585                 wr32(hw, TXGBE_IVARMISC, tmp);
3586         } else {
3587                 /* rx or tx causes */
3588                 /* Workround for ICR lost */
3589                 idx = ((16 * (queue & 1)) + (8 * direction));
3590                 tmp = rd32(hw, TXGBE_IVAR(queue >> 1));
3591                 tmp &= ~(0xFF << idx);
3592                 tmp |= (msix_vector << idx);
3593                 wr32(hw, TXGBE_IVAR(queue >> 1), tmp);
3594         }
3595 }
3596
3597 /**
3598  * Sets up the hardware to properly generate MSI-X interrupts
3599  * @hw
3600  *  board private structure
3601  */
3602 static void
3603 txgbe_configure_msix(struct rte_eth_dev *dev)
3604 {
3605         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3606         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3607         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3608         uint32_t queue_id, base = TXGBE_MISC_VEC_ID;
3609         uint32_t vec = TXGBE_MISC_VEC_ID;
3610         uint32_t gpie;
3611
3612         /* won't configure msix register if no mapping is done
3613          * between intr vector and event fd
3614          * but if misx has been enabled already, need to configure
3615          * auto clean, auto mask and throttling.
3616          */
3617         gpie = rd32(hw, TXGBE_GPIE);
3618         if (!rte_intr_dp_is_en(intr_handle) &&
3619             !(gpie & TXGBE_GPIE_MSIX))
3620                 return;
3621
3622         if (rte_intr_allow_others(intr_handle)) {
3623                 base = TXGBE_RX_VEC_START;
3624                 vec = base;
3625         }
3626
3627         /* setup GPIE for MSI-x mode */
3628         gpie = rd32(hw, TXGBE_GPIE);
3629         gpie |= TXGBE_GPIE_MSIX;
3630         wr32(hw, TXGBE_GPIE, gpie);
3631
3632         /* Populate the IVAR table and set the ITR values to the
3633          * corresponding register.
3634          */
3635         if (rte_intr_dp_is_en(intr_handle)) {
3636                 for (queue_id = 0; queue_id < dev->data->nb_rx_queues;
3637                         queue_id++) {
3638                         /* by default, 1:1 mapping */
3639                         txgbe_set_ivar_map(hw, 0, queue_id, vec);
3640                         intr_handle->intr_vec[queue_id] = vec;
3641                         if (vec < base + intr_handle->nb_efd - 1)
3642                                 vec++;
3643                 }
3644
3645                 txgbe_set_ivar_map(hw, -1, 1, TXGBE_MISC_VEC_ID);
3646         }
3647         wr32(hw, TXGBE_ITR(TXGBE_MISC_VEC_ID),
3648                         TXGBE_ITR_IVAL_10G(TXGBE_QUEUE_ITR_INTERVAL_DEFAULT)
3649                         | TXGBE_ITR_WRDSA);
3650 }
3651
3652 int
3653 txgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
3654                            uint16_t queue_idx, uint16_t tx_rate)
3655 {
3656         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3657         uint32_t bcnrc_val;
3658
3659         if (queue_idx >= hw->mac.max_tx_queues)
3660                 return -EINVAL;
3661
3662         if (tx_rate != 0) {
3663                 bcnrc_val = TXGBE_ARBTXRATE_MAX(tx_rate);
3664                 bcnrc_val |= TXGBE_ARBTXRATE_MIN(tx_rate / 2);
3665         } else {
3666                 bcnrc_val = 0;
3667         }
3668
3669         /*
3670          * Set global transmit compensation time to the MMW_SIZE in ARBTXMMW
3671          * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported.
3672          */
3673         wr32(hw, TXGBE_ARBTXMMW, 0x14);
3674
3675         /* Set ARBTXRATE of queue X */
3676         wr32(hw, TXGBE_ARBPOOLIDX, queue_idx);
3677         wr32(hw, TXGBE_ARBTXRATE, bcnrc_val);
3678         txgbe_flush(hw);
3679
3680         return 0;
3681 }
3682
3683 int
3684 txgbe_syn_filter_set(struct rte_eth_dev *dev,
3685                         struct rte_eth_syn_filter *filter,
3686                         bool add)
3687 {
3688         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3689         struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(dev);
3690         uint32_t syn_info;
3691         uint32_t synqf;
3692
3693         if (filter->queue >= TXGBE_MAX_RX_QUEUE_NUM)
3694                 return -EINVAL;
3695
3696         syn_info = filter_info->syn_info;
3697
3698         if (add) {
3699                 if (syn_info & TXGBE_SYNCLS_ENA)
3700                         return -EINVAL;
3701                 synqf = (uint32_t)TXGBE_SYNCLS_QPID(filter->queue);
3702                 synqf |= TXGBE_SYNCLS_ENA;
3703
3704                 if (filter->hig_pri)
3705                         synqf |= TXGBE_SYNCLS_HIPRIO;
3706                 else
3707                         synqf &= ~TXGBE_SYNCLS_HIPRIO;
3708         } else {
3709                 synqf = rd32(hw, TXGBE_SYNCLS);
3710                 if (!(syn_info & TXGBE_SYNCLS_ENA))
3711                         return -ENOENT;
3712                 synqf &= ~(TXGBE_SYNCLS_QPID_MASK | TXGBE_SYNCLS_ENA);
3713         }
3714
3715         filter_info->syn_info = synqf;
3716         wr32(hw, TXGBE_SYNCLS, synqf);
3717         txgbe_flush(hw);
3718         return 0;
3719 }
3720
3721 static inline enum txgbe_5tuple_protocol
3722 convert_protocol_type(uint8_t protocol_value)
3723 {
3724         if (protocol_value == IPPROTO_TCP)
3725                 return TXGBE_5TF_PROT_TCP;
3726         else if (protocol_value == IPPROTO_UDP)
3727                 return TXGBE_5TF_PROT_UDP;
3728         else if (protocol_value == IPPROTO_SCTP)
3729                 return TXGBE_5TF_PROT_SCTP;
3730         else
3731                 return TXGBE_5TF_PROT_NONE;
3732 }
3733
3734 /* inject a 5-tuple filter to HW */
3735 static inline void
3736 txgbe_inject_5tuple_filter(struct rte_eth_dev *dev,
3737                            struct txgbe_5tuple_filter *filter)
3738 {
3739         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3740         int i;
3741         uint32_t ftqf, sdpqf;
3742         uint32_t l34timir = 0;
3743         uint32_t mask = TXGBE_5TFCTL0_MASK;
3744
3745         i = filter->index;
3746         sdpqf = TXGBE_5TFPORT_DST(be_to_le16(filter->filter_info.dst_port));
3747         sdpqf |= TXGBE_5TFPORT_SRC(be_to_le16(filter->filter_info.src_port));
3748
3749         ftqf = TXGBE_5TFCTL0_PROTO(filter->filter_info.proto);
3750         ftqf |= TXGBE_5TFCTL0_PRI(filter->filter_info.priority);
3751         if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
3752                 mask &= ~TXGBE_5TFCTL0_MSADDR;
3753         if (filter->filter_info.dst_ip_mask == 0)
3754                 mask &= ~TXGBE_5TFCTL0_MDADDR;
3755         if (filter->filter_info.src_port_mask == 0)
3756                 mask &= ~TXGBE_5TFCTL0_MSPORT;
3757         if (filter->filter_info.dst_port_mask == 0)
3758                 mask &= ~TXGBE_5TFCTL0_MDPORT;
3759         if (filter->filter_info.proto_mask == 0)
3760                 mask &= ~TXGBE_5TFCTL0_MPROTO;
3761         ftqf |= mask;
3762         ftqf |= TXGBE_5TFCTL0_MPOOL;
3763         ftqf |= TXGBE_5TFCTL0_ENA;
3764
3765         wr32(hw, TXGBE_5TFDADDR(i), be_to_le32(filter->filter_info.dst_ip));
3766         wr32(hw, TXGBE_5TFSADDR(i), be_to_le32(filter->filter_info.src_ip));
3767         wr32(hw, TXGBE_5TFPORT(i), sdpqf);
3768         wr32(hw, TXGBE_5TFCTL0(i), ftqf);
3769
3770         l34timir |= TXGBE_5TFCTL1_QP(filter->queue);
3771         wr32(hw, TXGBE_5TFCTL1(i), l34timir);
3772 }
3773
3774 /*
3775  * add a 5tuple filter
3776  *
3777  * @param
3778  * dev: Pointer to struct rte_eth_dev.
3779  * index: the index the filter allocates.
3780  * filter: pointer to the filter that will be added.
3781  * rx_queue: the queue id the filter assigned to.
3782  *
3783  * @return
3784  *    - On success, zero.
3785  *    - On failure, a negative value.
3786  */
3787 static int
3788 txgbe_add_5tuple_filter(struct rte_eth_dev *dev,
3789                         struct txgbe_5tuple_filter *filter)
3790 {
3791         struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(dev);
3792         int i, idx, shift;
3793
3794         /*
3795          * look for an unused 5tuple filter index,
3796          * and insert the filter to list.
3797          */
3798         for (i = 0; i < TXGBE_MAX_FTQF_FILTERS; i++) {
3799                 idx = i / (sizeof(uint32_t) * NBBY);
3800                 shift = i % (sizeof(uint32_t) * NBBY);
3801                 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
3802                         filter_info->fivetuple_mask[idx] |= 1 << shift;
3803                         filter->index = i;
3804                         TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
3805                                           filter,
3806                                           entries);
3807                         break;
3808                 }
3809         }
3810         if (i >= TXGBE_MAX_FTQF_FILTERS) {
3811                 PMD_DRV_LOG(ERR, "5tuple filters are full.");
3812                 return -ENOSYS;
3813         }
3814
3815         txgbe_inject_5tuple_filter(dev, filter);
3816
3817         return 0;
3818 }
3819
3820 /*
3821  * remove a 5tuple filter
3822  *
3823  * @param
3824  * dev: Pointer to struct rte_eth_dev.
3825  * filter: the pointer of the filter will be removed.
3826  */
3827 static void
3828 txgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
3829                         struct txgbe_5tuple_filter *filter)
3830 {
3831         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3832         struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(dev);
3833         uint16_t index = filter->index;
3834
3835         filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
3836                                 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
3837         TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
3838         rte_free(filter);
3839
3840         wr32(hw, TXGBE_5TFDADDR(index), 0);
3841         wr32(hw, TXGBE_5TFSADDR(index), 0);
3842         wr32(hw, TXGBE_5TFPORT(index), 0);
3843         wr32(hw, TXGBE_5TFCTL0(index), 0);
3844         wr32(hw, TXGBE_5TFCTL1(index), 0);
3845 }
3846
3847 static inline struct txgbe_5tuple_filter *
3848 txgbe_5tuple_filter_lookup(struct txgbe_5tuple_filter_list *filter_list,
3849                         struct txgbe_5tuple_filter_info *key)
3850 {
3851         struct txgbe_5tuple_filter *it;
3852
3853         TAILQ_FOREACH(it, filter_list, entries) {
3854                 if (memcmp(key, &it->filter_info,
3855                         sizeof(struct txgbe_5tuple_filter_info)) == 0) {
3856                         return it;
3857                 }
3858         }
3859         return NULL;
3860 }
3861
3862 /* translate elements in struct rte_eth_ntuple_filter
3863  * to struct txgbe_5tuple_filter_info
3864  */
3865 static inline int
3866 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
3867                         struct txgbe_5tuple_filter_info *filter_info)
3868 {
3869         if (filter->queue >= TXGBE_MAX_RX_QUEUE_NUM ||
3870                 filter->priority > TXGBE_5TUPLE_MAX_PRI ||
3871                 filter->priority < TXGBE_5TUPLE_MIN_PRI)
3872                 return -EINVAL;
3873
3874         switch (filter->dst_ip_mask) {
3875         case UINT32_MAX:
3876                 filter_info->dst_ip_mask = 0;
3877                 filter_info->dst_ip = filter->dst_ip;
3878                 break;
3879         case 0:
3880                 filter_info->dst_ip_mask = 1;
3881                 break;
3882         default:
3883                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
3884                 return -EINVAL;
3885         }
3886
3887         switch (filter->src_ip_mask) {
3888         case UINT32_MAX:
3889                 filter_info->src_ip_mask = 0;
3890                 filter_info->src_ip = filter->src_ip;
3891                 break;
3892         case 0:
3893                 filter_info->src_ip_mask = 1;
3894                 break;
3895         default:
3896                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
3897                 return -EINVAL;
3898         }
3899
3900         switch (filter->dst_port_mask) {
3901         case UINT16_MAX:
3902                 filter_info->dst_port_mask = 0;
3903                 filter_info->dst_port = filter->dst_port;
3904                 break;
3905         case 0:
3906                 filter_info->dst_port_mask = 1;
3907                 break;
3908         default:
3909                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
3910                 return -EINVAL;
3911         }
3912
3913         switch (filter->src_port_mask) {
3914         case UINT16_MAX:
3915                 filter_info->src_port_mask = 0;
3916                 filter_info->src_port = filter->src_port;
3917                 break;
3918         case 0:
3919                 filter_info->src_port_mask = 1;
3920                 break;
3921         default:
3922                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
3923                 return -EINVAL;
3924         }
3925
3926         switch (filter->proto_mask) {
3927         case UINT8_MAX:
3928                 filter_info->proto_mask = 0;
3929                 filter_info->proto =
3930                         convert_protocol_type(filter->proto);
3931                 break;
3932         case 0:
3933                 filter_info->proto_mask = 1;
3934                 break;
3935         default:
3936                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
3937                 return -EINVAL;
3938         }
3939
3940         filter_info->priority = (uint8_t)filter->priority;
3941         return 0;
3942 }
3943
3944 /*
3945  * add or delete a ntuple filter
3946  *
3947  * @param
3948  * dev: Pointer to struct rte_eth_dev.
3949  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
3950  * add: if true, add filter, if false, remove filter
3951  *
3952  * @return
3953  *    - On success, zero.
3954  *    - On failure, a negative value.
3955  */
3956 int
3957 txgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
3958                         struct rte_eth_ntuple_filter *ntuple_filter,
3959                         bool add)
3960 {
3961         struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(dev);
3962         struct txgbe_5tuple_filter_info filter_5tuple;
3963         struct txgbe_5tuple_filter *filter;
3964         int ret;
3965
3966         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
3967                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
3968                 return -EINVAL;
3969         }
3970
3971         memset(&filter_5tuple, 0, sizeof(struct txgbe_5tuple_filter_info));
3972         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
3973         if (ret < 0)
3974                 return ret;
3975
3976         filter = txgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
3977                                          &filter_5tuple);
3978         if (filter != NULL && add) {
3979                 PMD_DRV_LOG(ERR, "filter exists.");
3980                 return -EEXIST;
3981         }
3982         if (filter == NULL && !add) {
3983                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3984                 return -ENOENT;
3985         }
3986
3987         if (add) {
3988                 filter = rte_zmalloc("txgbe_5tuple_filter",
3989                                 sizeof(struct txgbe_5tuple_filter), 0);
3990                 if (filter == NULL)
3991                         return -ENOMEM;
3992                 rte_memcpy(&filter->filter_info,
3993                                  &filter_5tuple,
3994                                  sizeof(struct txgbe_5tuple_filter_info));
3995                 filter->queue = ntuple_filter->queue;
3996                 ret = txgbe_add_5tuple_filter(dev, filter);
3997                 if (ret < 0) {
3998                         rte_free(filter);
3999                         return ret;
4000                 }
4001         } else {
4002                 txgbe_remove_5tuple_filter(dev, filter);
4003         }
4004
4005         return 0;
4006 }
4007
4008 int
4009 txgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
4010                         struct rte_eth_ethertype_filter *filter,
4011                         bool add)
4012 {
4013         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4014         struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(dev);
4015         uint32_t etqf = 0;
4016         uint32_t etqs = 0;
4017         int ret;
4018         struct txgbe_ethertype_filter ethertype_filter;
4019
4020         if (filter->queue >= TXGBE_MAX_RX_QUEUE_NUM)
4021                 return -EINVAL;
4022
4023         if (filter->ether_type == RTE_ETHER_TYPE_IPV4 ||
4024             filter->ether_type == RTE_ETHER_TYPE_IPV6) {
4025                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
4026                         " ethertype filter.", filter->ether_type);
4027                 return -EINVAL;
4028         }
4029
4030         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
4031                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
4032                 return -EINVAL;
4033         }
4034         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
4035                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
4036                 return -EINVAL;
4037         }
4038
4039         ret = txgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
4040         if (ret >= 0 && add) {
4041                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
4042                             filter->ether_type);
4043                 return -EEXIST;
4044         }
4045         if (ret < 0 && !add) {
4046                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
4047                             filter->ether_type);
4048                 return -ENOENT;
4049         }
4050
4051         if (add) {
4052                 etqf = TXGBE_ETFLT_ENA;
4053                 etqf |= TXGBE_ETFLT_ETID(filter->ether_type);
4054                 etqs |= TXGBE_ETCLS_QPID(filter->queue);
4055                 etqs |= TXGBE_ETCLS_QENA;
4056
4057                 ethertype_filter.ethertype = filter->ether_type;
4058                 ethertype_filter.etqf = etqf;
4059                 ethertype_filter.etqs = etqs;
4060                 ethertype_filter.conf = FALSE;
4061                 ret = txgbe_ethertype_filter_insert(filter_info,
4062                                                     &ethertype_filter);
4063                 if (ret < 0) {
4064                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
4065                         return -ENOSPC;
4066                 }
4067         } else {
4068                 ret = txgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
4069                 if (ret < 0)
4070                         return -ENOSYS;
4071         }
4072         wr32(hw, TXGBE_ETFLT(ret), etqf);
4073         wr32(hw, TXGBE_ETCLS(ret), etqs);
4074         txgbe_flush(hw);
4075
4076         return 0;
4077 }
4078
4079 static int
4080 txgbe_dev_flow_ops_get(__rte_unused struct rte_eth_dev *dev,
4081                        const struct rte_flow_ops **ops)
4082 {
4083         *ops = &txgbe_flow_ops;
4084         return 0;
4085 }
4086
4087 static u8 *
4088 txgbe_dev_addr_list_itr(__rte_unused struct txgbe_hw *hw,
4089                         u8 **mc_addr_ptr, u32 *vmdq)
4090 {
4091         u8 *mc_addr;
4092
4093         *vmdq = 0;
4094         mc_addr = *mc_addr_ptr;
4095         *mc_addr_ptr = (mc_addr + sizeof(struct rte_ether_addr));
4096         return mc_addr;
4097 }
4098
4099 int
4100 txgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
4101                           struct rte_ether_addr *mc_addr_set,
4102                           uint32_t nb_mc_addr)
4103 {
4104         struct txgbe_hw *hw;
4105         u8 *mc_addr_list;
4106
4107         hw = TXGBE_DEV_HW(dev);
4108         mc_addr_list = (u8 *)mc_addr_set;
4109         return hw->mac.update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
4110                                          txgbe_dev_addr_list_itr, TRUE);
4111 }
4112
4113 static uint64_t
4114 txgbe_read_systime_cyclecounter(struct rte_eth_dev *dev)
4115 {
4116         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4117         uint64_t systime_cycles;
4118
4119         systime_cycles = (uint64_t)rd32(hw, TXGBE_TSTIMEL);
4120         systime_cycles |= (uint64_t)rd32(hw, TXGBE_TSTIMEH) << 32;
4121
4122         return systime_cycles;
4123 }
4124
4125 static uint64_t
4126 txgbe_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
4127 {
4128         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4129         uint64_t rx_tstamp_cycles;
4130
4131         /* TSRXSTMPL stores ns and TSRXSTMPH stores seconds. */
4132         rx_tstamp_cycles = (uint64_t)rd32(hw, TXGBE_TSRXSTMPL);
4133         rx_tstamp_cycles |= (uint64_t)rd32(hw, TXGBE_TSRXSTMPH) << 32;
4134
4135         return rx_tstamp_cycles;
4136 }
4137
4138 static uint64_t
4139 txgbe_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
4140 {
4141         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4142         uint64_t tx_tstamp_cycles;
4143
4144         /* TSTXSTMPL stores ns and TSTXSTMPH stores seconds. */
4145         tx_tstamp_cycles = (uint64_t)rd32(hw, TXGBE_TSTXSTMPL);
4146         tx_tstamp_cycles |= (uint64_t)rd32(hw, TXGBE_TSTXSTMPH) << 32;
4147
4148         return tx_tstamp_cycles;
4149 }
4150
4151 static void
4152 txgbe_start_timecounters(struct rte_eth_dev *dev)
4153 {
4154         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4155         struct txgbe_adapter *adapter = TXGBE_DEV_ADAPTER(dev);
4156         struct rte_eth_link link;
4157         uint32_t incval = 0;
4158         uint32_t shift = 0;
4159
4160         /* Get current link speed. */
4161         txgbe_dev_link_update(dev, 1);
4162         rte_eth_linkstatus_get(dev, &link);
4163
4164         switch (link.link_speed) {
4165         case ETH_SPEED_NUM_100M:
4166                 incval = TXGBE_INCVAL_100;
4167                 shift = TXGBE_INCVAL_SHIFT_100;
4168                 break;
4169         case ETH_SPEED_NUM_1G:
4170                 incval = TXGBE_INCVAL_1GB;
4171                 shift = TXGBE_INCVAL_SHIFT_1GB;
4172                 break;
4173         case ETH_SPEED_NUM_10G:
4174         default:
4175                 incval = TXGBE_INCVAL_10GB;
4176                 shift = TXGBE_INCVAL_SHIFT_10GB;
4177                 break;
4178         }
4179
4180         wr32(hw, TXGBE_TSTIMEINC, TXGBE_TSTIMEINC_VP(incval, 2));
4181
4182         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
4183         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
4184         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
4185
4186         adapter->systime_tc.cc_mask = TXGBE_CYCLECOUNTER_MASK;
4187         adapter->systime_tc.cc_shift = shift;
4188         adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
4189
4190         adapter->rx_tstamp_tc.cc_mask = TXGBE_CYCLECOUNTER_MASK;
4191         adapter->rx_tstamp_tc.cc_shift = shift;
4192         adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
4193
4194         adapter->tx_tstamp_tc.cc_mask = TXGBE_CYCLECOUNTER_MASK;
4195         adapter->tx_tstamp_tc.cc_shift = shift;
4196         adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
4197 }
4198
4199 static int
4200 txgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
4201 {
4202         struct txgbe_adapter *adapter = TXGBE_DEV_ADAPTER(dev);
4203
4204         adapter->systime_tc.nsec += delta;
4205         adapter->rx_tstamp_tc.nsec += delta;
4206         adapter->tx_tstamp_tc.nsec += delta;
4207
4208         return 0;
4209 }
4210
4211 static int
4212 txgbe_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
4213 {
4214         uint64_t ns;
4215         struct txgbe_adapter *adapter = TXGBE_DEV_ADAPTER(dev);
4216
4217         ns = rte_timespec_to_ns(ts);
4218         /* Set the timecounters to a new value. */
4219         adapter->systime_tc.nsec = ns;
4220         adapter->rx_tstamp_tc.nsec = ns;
4221         adapter->tx_tstamp_tc.nsec = ns;
4222
4223         return 0;
4224 }
4225
4226 static int
4227 txgbe_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
4228 {
4229         uint64_t ns, systime_cycles;
4230         struct txgbe_adapter *adapter = TXGBE_DEV_ADAPTER(dev);
4231
4232         systime_cycles = txgbe_read_systime_cyclecounter(dev);
4233         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
4234         *ts = rte_ns_to_timespec(ns);
4235
4236         return 0;
4237 }
4238
4239 static int
4240 txgbe_timesync_enable(struct rte_eth_dev *dev)
4241 {
4242         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4243         uint32_t tsync_ctl;
4244
4245         /* Stop the timesync system time. */
4246         wr32(hw, TXGBE_TSTIMEINC, 0x0);
4247         /* Reset the timesync system time value. */
4248         wr32(hw, TXGBE_TSTIMEL, 0x0);
4249         wr32(hw, TXGBE_TSTIMEH, 0x0);
4250
4251         txgbe_start_timecounters(dev);
4252
4253         /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
4254         wr32(hw, TXGBE_ETFLT(TXGBE_ETF_ID_1588),
4255                 RTE_ETHER_TYPE_1588 | TXGBE_ETFLT_ENA | TXGBE_ETFLT_1588);
4256
4257         /* Enable timestamping of received PTP packets. */
4258         tsync_ctl = rd32(hw, TXGBE_TSRXCTL);
4259         tsync_ctl |= TXGBE_TSRXCTL_ENA;
4260         wr32(hw, TXGBE_TSRXCTL, tsync_ctl);
4261
4262         /* Enable timestamping of transmitted PTP packets. */
4263         tsync_ctl = rd32(hw, TXGBE_TSTXCTL);
4264         tsync_ctl |= TXGBE_TSTXCTL_ENA;
4265         wr32(hw, TXGBE_TSTXCTL, tsync_ctl);
4266
4267         txgbe_flush(hw);
4268
4269         return 0;
4270 }
4271
4272 static int
4273 txgbe_timesync_disable(struct rte_eth_dev *dev)
4274 {
4275         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4276         uint32_t tsync_ctl;
4277
4278         /* Disable timestamping of transmitted PTP packets. */
4279         tsync_ctl = rd32(hw, TXGBE_TSTXCTL);
4280         tsync_ctl &= ~TXGBE_TSTXCTL_ENA;
4281         wr32(hw, TXGBE_TSTXCTL, tsync_ctl);
4282
4283         /* Disable timestamping of received PTP packets. */
4284         tsync_ctl = rd32(hw, TXGBE_TSRXCTL);
4285         tsync_ctl &= ~TXGBE_TSRXCTL_ENA;
4286         wr32(hw, TXGBE_TSRXCTL, tsync_ctl);
4287
4288         /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
4289         wr32(hw, TXGBE_ETFLT(TXGBE_ETF_ID_1588), 0);
4290
4291         /* Stop incrementating the System Time registers. */
4292         wr32(hw, TXGBE_TSTIMEINC, 0);
4293
4294         return 0;
4295 }
4296
4297 static int
4298 txgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
4299                                  struct timespec *timestamp,
4300                                  uint32_t flags __rte_unused)
4301 {
4302         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4303         struct txgbe_adapter *adapter = TXGBE_DEV_ADAPTER(dev);
4304         uint32_t tsync_rxctl;
4305         uint64_t rx_tstamp_cycles;
4306         uint64_t ns;
4307
4308         tsync_rxctl = rd32(hw, TXGBE_TSRXCTL);
4309         if ((tsync_rxctl & TXGBE_TSRXCTL_VLD) == 0)
4310                 return -EINVAL;
4311
4312         rx_tstamp_cycles = txgbe_read_rx_tstamp_cyclecounter(dev);
4313         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
4314         *timestamp = rte_ns_to_timespec(ns);
4315
4316         return  0;
4317 }
4318
4319 static int
4320 txgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
4321                                  struct timespec *timestamp)
4322 {
4323         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4324         struct txgbe_adapter *adapter = TXGBE_DEV_ADAPTER(dev);
4325         uint32_t tsync_txctl;
4326         uint64_t tx_tstamp_cycles;
4327         uint64_t ns;
4328
4329         tsync_txctl = rd32(hw, TXGBE_TSTXCTL);
4330         if ((tsync_txctl & TXGBE_TSTXCTL_VLD) == 0)
4331                 return -EINVAL;
4332
4333         tx_tstamp_cycles = txgbe_read_tx_tstamp_cyclecounter(dev);
4334         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
4335         *timestamp = rte_ns_to_timespec(ns);
4336
4337         return 0;
4338 }
4339
4340 static int
4341 txgbe_get_reg_length(struct rte_eth_dev *dev __rte_unused)
4342 {
4343         int count = 0;
4344         int g_ind = 0;
4345         const struct reg_info *reg_group;
4346         const struct reg_info **reg_set = txgbe_regs_others;
4347
4348         while ((reg_group = reg_set[g_ind++]))
4349                 count += txgbe_regs_group_count(reg_group);
4350
4351         return count;
4352 }
4353
4354 static int
4355 txgbe_get_regs(struct rte_eth_dev *dev,
4356               struct rte_dev_reg_info *regs)
4357 {
4358         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4359         uint32_t *data = regs->data;
4360         int g_ind = 0;
4361         int count = 0;
4362         const struct reg_info *reg_group;
4363         const struct reg_info **reg_set = txgbe_regs_others;
4364
4365         if (data == NULL) {
4366                 regs->length = txgbe_get_reg_length(dev);
4367                 regs->width = sizeof(uint32_t);
4368                 return 0;
4369         }
4370
4371         /* Support only full register dump */
4372         if (regs->length == 0 ||
4373             regs->length == (uint32_t)txgbe_get_reg_length(dev)) {
4374                 regs->version = hw->mac.type << 24 |
4375                                 hw->revision_id << 16 |
4376                                 hw->device_id;
4377                 while ((reg_group = reg_set[g_ind++]))
4378                         count += txgbe_read_regs_group(dev, &data[count],
4379                                                       reg_group);
4380                 return 0;
4381         }
4382
4383         return -ENOTSUP;
4384 }
4385
4386 static int
4387 txgbe_get_eeprom_length(struct rte_eth_dev *dev)
4388 {
4389         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4390
4391         /* Return unit is byte count */
4392         return hw->rom.word_size * 2;
4393 }
4394
4395 static int
4396 txgbe_get_eeprom(struct rte_eth_dev *dev,
4397                 struct rte_dev_eeprom_info *in_eeprom)
4398 {
4399         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4400         struct txgbe_rom_info *eeprom = &hw->rom;
4401         uint16_t *data = in_eeprom->data;
4402         int first, length;
4403
4404         first = in_eeprom->offset >> 1;
4405         length = in_eeprom->length >> 1;
4406         if (first > hw->rom.word_size ||
4407             ((first + length) > hw->rom.word_size))
4408                 return -EINVAL;
4409
4410         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
4411
4412         return eeprom->readw_buffer(hw, first, length, data);
4413 }
4414
4415 static int
4416 txgbe_set_eeprom(struct rte_eth_dev *dev,
4417                 struct rte_dev_eeprom_info *in_eeprom)
4418 {
4419         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4420         struct txgbe_rom_info *eeprom = &hw->rom;
4421         uint16_t *data = in_eeprom->data;
4422         int first, length;
4423
4424         first = in_eeprom->offset >> 1;
4425         length = in_eeprom->length >> 1;
4426         if (first > hw->rom.word_size ||
4427             ((first + length) > hw->rom.word_size))
4428                 return -EINVAL;
4429
4430         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
4431
4432         return eeprom->writew_buffer(hw,  first, length, data);
4433 }
4434
4435 static int
4436 txgbe_get_module_info(struct rte_eth_dev *dev,
4437                       struct rte_eth_dev_module_info *modinfo)
4438 {
4439         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4440         uint32_t status;
4441         uint8_t sff8472_rev, addr_mode;
4442         bool page_swap = false;
4443
4444         /* Check whether we support SFF-8472 or not */
4445         status = hw->phy.read_i2c_eeprom(hw,
4446                                              TXGBE_SFF_SFF_8472_COMP,
4447                                              &sff8472_rev);
4448         if (status != 0)
4449                 return -EIO;
4450
4451         /* addressing mode is not supported */
4452         status = hw->phy.read_i2c_eeprom(hw,
4453                                              TXGBE_SFF_SFF_8472_SWAP,
4454                                              &addr_mode);
4455         if (status != 0)
4456                 return -EIO;
4457
4458         if (addr_mode & TXGBE_SFF_ADDRESSING_MODE) {
4459                 PMD_DRV_LOG(ERR,
4460                             "Address change required to access page 0xA2, "
4461                             "but not supported. Please report the module "
4462                             "type to the driver maintainers.");
4463                 page_swap = true;
4464         }
4465
4466         if (sff8472_rev == TXGBE_SFF_SFF_8472_UNSUP || page_swap) {
4467                 /* We have a SFP, but it does not support SFF-8472 */
4468                 modinfo->type = RTE_ETH_MODULE_SFF_8079;
4469                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
4470         } else {
4471                 /* We have a SFP which supports a revision of SFF-8472. */
4472                 modinfo->type = RTE_ETH_MODULE_SFF_8472;
4473                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
4474         }
4475
4476         return 0;
4477 }
4478
4479 static int
4480 txgbe_get_module_eeprom(struct rte_eth_dev *dev,
4481                         struct rte_dev_eeprom_info *info)
4482 {
4483         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4484         uint32_t status = TXGBE_ERR_PHY_ADDR_INVALID;
4485         uint8_t databyte = 0xFF;
4486         uint8_t *data = info->data;
4487         uint32_t i = 0;
4488
4489         if (info->length == 0)
4490                 return -EINVAL;
4491
4492         for (i = info->offset; i < info->offset + info->length; i++) {
4493                 if (i < RTE_ETH_MODULE_SFF_8079_LEN)
4494                         status = hw->phy.read_i2c_eeprom(hw, i, &databyte);
4495                 else
4496                         status = hw->phy.read_i2c_sff8472(hw, i, &databyte);
4497
4498                 if (status != 0)
4499                         return -EIO;
4500
4501                 data[i - info->offset] = databyte;
4502         }
4503
4504         return 0;
4505 }
4506
4507 bool
4508 txgbe_rss_update_sp(enum txgbe_mac_type mac_type)
4509 {
4510         switch (mac_type) {
4511         case txgbe_mac_raptor:
4512         case txgbe_mac_raptor_vf:
4513                 return 1;
4514         default:
4515                 return 0;
4516         }
4517 }
4518
4519 static int
4520 txgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
4521                         struct rte_eth_dcb_info *dcb_info)
4522 {
4523         struct txgbe_dcb_config *dcb_config = TXGBE_DEV_DCB_CONFIG(dev);
4524         struct txgbe_dcb_tc_config *tc;
4525         struct rte_eth_dcb_tc_queue_mapping *tc_queue;
4526         uint8_t nb_tcs;
4527         uint8_t i, j;
4528
4529         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
4530                 dcb_info->nb_tcs = dcb_config->num_tcs.pg_tcs;
4531         else
4532                 dcb_info->nb_tcs = 1;
4533
4534         tc_queue = &dcb_info->tc_queue;
4535         nb_tcs = dcb_info->nb_tcs;
4536
4537         if (dcb_config->vt_mode) { /* vt is enabled */
4538                 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
4539                                 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
4540                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
4541                         dcb_info->prio_tc[i] = vmdq_rx_conf->dcb_tc[i];
4542                 if (RTE_ETH_DEV_SRIOV(dev).active > 0) {
4543                         for (j = 0; j < nb_tcs; j++) {
4544                                 tc_queue->tc_rxq[0][j].base = j;
4545                                 tc_queue->tc_rxq[0][j].nb_queue = 1;
4546                                 tc_queue->tc_txq[0][j].base = j;
4547                                 tc_queue->tc_txq[0][j].nb_queue = 1;
4548                         }
4549                 } else {
4550                         for (i = 0; i < vmdq_rx_conf->nb_queue_pools; i++) {
4551                                 for (j = 0; j < nb_tcs; j++) {
4552                                         tc_queue->tc_rxq[i][j].base =
4553                                                 i * nb_tcs + j;
4554                                         tc_queue->tc_rxq[i][j].nb_queue = 1;
4555                                         tc_queue->tc_txq[i][j].base =
4556                                                 i * nb_tcs + j;
4557                                         tc_queue->tc_txq[i][j].nb_queue = 1;
4558                                 }
4559                         }
4560                 }
4561         } else { /* vt is disabled */
4562                 struct rte_eth_dcb_rx_conf *rx_conf =
4563                                 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
4564                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
4565                         dcb_info->prio_tc[i] = rx_conf->dcb_tc[i];
4566                 if (dcb_info->nb_tcs == ETH_4_TCS) {
4567                         for (i = 0; i < dcb_info->nb_tcs; i++) {
4568                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 32;
4569                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
4570                         }
4571                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
4572                         dcb_info->tc_queue.tc_txq[0][1].base = 64;
4573                         dcb_info->tc_queue.tc_txq[0][2].base = 96;
4574                         dcb_info->tc_queue.tc_txq[0][3].base = 112;
4575                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 64;
4576                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
4577                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
4578                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
4579                 } else if (dcb_info->nb_tcs == ETH_8_TCS) {
4580                         for (i = 0; i < dcb_info->nb_tcs; i++) {
4581                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 16;
4582                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
4583                         }
4584                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
4585                         dcb_info->tc_queue.tc_txq[0][1].base = 32;
4586                         dcb_info->tc_queue.tc_txq[0][2].base = 64;
4587                         dcb_info->tc_queue.tc_txq[0][3].base = 80;
4588                         dcb_info->tc_queue.tc_txq[0][4].base = 96;
4589                         dcb_info->tc_queue.tc_txq[0][5].base = 104;
4590                         dcb_info->tc_queue.tc_txq[0][6].base = 112;
4591                         dcb_info->tc_queue.tc_txq[0][7].base = 120;
4592                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 32;
4593                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
4594                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
4595                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
4596                         dcb_info->tc_queue.tc_txq[0][4].nb_queue = 8;
4597                         dcb_info->tc_queue.tc_txq[0][5].nb_queue = 8;
4598                         dcb_info->tc_queue.tc_txq[0][6].nb_queue = 8;
4599                         dcb_info->tc_queue.tc_txq[0][7].nb_queue = 8;
4600                 }
4601         }
4602         for (i = 0; i < dcb_info->nb_tcs; i++) {
4603                 tc = &dcb_config->tc_config[i];
4604                 dcb_info->tc_bws[i] = tc->path[TXGBE_DCB_TX_CONFIG].bwg_percent;
4605         }
4606         return 0;
4607 }
4608
4609 /* Update e-tag ether type */
4610 static int
4611 txgbe_update_e_tag_eth_type(struct txgbe_hw *hw,
4612                             uint16_t ether_type)
4613 {
4614         uint32_t etag_etype;
4615
4616         etag_etype = rd32(hw, TXGBE_EXTAG);
4617         etag_etype &= ~TXGBE_EXTAG_ETAG_MASK;
4618         etag_etype |= ether_type;
4619         wr32(hw, TXGBE_EXTAG, etag_etype);
4620         txgbe_flush(hw);
4621
4622         return 0;
4623 }
4624
4625 /* Enable e-tag tunnel */
4626 static int
4627 txgbe_e_tag_enable(struct txgbe_hw *hw)
4628 {
4629         uint32_t etag_etype;
4630
4631         etag_etype = rd32(hw, TXGBE_PORTCTL);
4632         etag_etype |= TXGBE_PORTCTL_ETAG;
4633         wr32(hw, TXGBE_PORTCTL, etag_etype);
4634         txgbe_flush(hw);
4635
4636         return 0;
4637 }
4638
4639 static int
4640 txgbe_e_tag_filter_del(struct rte_eth_dev *dev,
4641                        struct txgbe_l2_tunnel_conf  *l2_tunnel)
4642 {
4643         int ret = 0;
4644         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4645         uint32_t i, rar_entries;
4646         uint32_t rar_low, rar_high;
4647
4648         rar_entries = hw->mac.num_rar_entries;
4649
4650         for (i = 1; i < rar_entries; i++) {
4651                 wr32(hw, TXGBE_ETHADDRIDX, i);
4652                 rar_high = rd32(hw, TXGBE_ETHADDRH);
4653                 rar_low  = rd32(hw, TXGBE_ETHADDRL);
4654                 if ((rar_high & TXGBE_ETHADDRH_VLD) &&
4655                     (rar_high & TXGBE_ETHADDRH_ETAG) &&
4656                     (TXGBE_ETHADDRL_ETAG(rar_low) ==
4657                      l2_tunnel->tunnel_id)) {
4658                         wr32(hw, TXGBE_ETHADDRL, 0);
4659                         wr32(hw, TXGBE_ETHADDRH, 0);
4660
4661                         txgbe_clear_vmdq(hw, i, BIT_MASK32);
4662
4663                         return ret;
4664                 }
4665         }
4666
4667         return ret;
4668 }
4669
4670 static int
4671 txgbe_e_tag_filter_add(struct rte_eth_dev *dev,
4672                        struct txgbe_l2_tunnel_conf *l2_tunnel)
4673 {
4674         int ret = 0;
4675         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4676         uint32_t i, rar_entries;
4677         uint32_t rar_low, rar_high;
4678
4679         /* One entry for one tunnel. Try to remove potential existing entry. */
4680         txgbe_e_tag_filter_del(dev, l2_tunnel);
4681
4682         rar_entries = hw->mac.num_rar_entries;
4683
4684         for (i = 1; i < rar_entries; i++) {
4685                 wr32(hw, TXGBE_ETHADDRIDX, i);
4686                 rar_high = rd32(hw, TXGBE_ETHADDRH);
4687                 if (rar_high & TXGBE_ETHADDRH_VLD) {
4688                         continue;
4689                 } else {
4690                         txgbe_set_vmdq(hw, i, l2_tunnel->pool);
4691                         rar_high = TXGBE_ETHADDRH_VLD | TXGBE_ETHADDRH_ETAG;
4692                         rar_low = l2_tunnel->tunnel_id;
4693
4694                         wr32(hw, TXGBE_ETHADDRL, rar_low);
4695                         wr32(hw, TXGBE_ETHADDRH, rar_high);
4696
4697                         return ret;
4698                 }
4699         }
4700
4701         PMD_INIT_LOG(NOTICE, "The table of E-tag forwarding rule is full."
4702                      " Please remove a rule before adding a new one.");
4703         return -EINVAL;
4704 }
4705
4706 static inline struct txgbe_l2_tn_filter *
4707 txgbe_l2_tn_filter_lookup(struct txgbe_l2_tn_info *l2_tn_info,
4708                           struct txgbe_l2_tn_key *key)
4709 {
4710         int ret;
4711
4712         ret = rte_hash_lookup(l2_tn_info->hash_handle, (const void *)key);
4713         if (ret < 0)
4714                 return NULL;
4715
4716         return l2_tn_info->hash_map[ret];
4717 }
4718
4719 static inline int
4720 txgbe_insert_l2_tn_filter(struct txgbe_l2_tn_info *l2_tn_info,
4721                           struct txgbe_l2_tn_filter *l2_tn_filter)
4722 {
4723         int ret;
4724
4725         ret = rte_hash_add_key(l2_tn_info->hash_handle,
4726                                &l2_tn_filter->key);
4727
4728         if (ret < 0) {
4729                 PMD_DRV_LOG(ERR,
4730                             "Failed to insert L2 tunnel filter"
4731                             " to hash table %d!",
4732                             ret);
4733                 return ret;
4734         }
4735
4736         l2_tn_info->hash_map[ret] = l2_tn_filter;
4737
4738         TAILQ_INSERT_TAIL(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
4739
4740         return 0;
4741 }
4742
4743 static inline int
4744 txgbe_remove_l2_tn_filter(struct txgbe_l2_tn_info *l2_tn_info,
4745                           struct txgbe_l2_tn_key *key)
4746 {
4747         int ret;
4748         struct txgbe_l2_tn_filter *l2_tn_filter;
4749
4750         ret = rte_hash_del_key(l2_tn_info->hash_handle, key);
4751
4752         if (ret < 0) {
4753                 PMD_DRV_LOG(ERR,
4754                             "No such L2 tunnel filter to delete %d!",
4755                             ret);
4756                 return ret;
4757         }
4758
4759         l2_tn_filter = l2_tn_info->hash_map[ret];
4760         l2_tn_info->hash_map[ret] = NULL;
4761
4762         TAILQ_REMOVE(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
4763         rte_free(l2_tn_filter);
4764
4765         return 0;
4766 }
4767
4768 /* Add l2 tunnel filter */
4769 int
4770 txgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev,
4771                                struct txgbe_l2_tunnel_conf *l2_tunnel,
4772                                bool restore)
4773 {
4774         int ret;
4775         struct txgbe_l2_tn_info *l2_tn_info = TXGBE_DEV_L2_TN(dev);
4776         struct txgbe_l2_tn_key key;
4777         struct txgbe_l2_tn_filter *node;
4778
4779         if (!restore) {
4780                 key.l2_tn_type = l2_tunnel->l2_tunnel_type;
4781                 key.tn_id = l2_tunnel->tunnel_id;
4782
4783                 node = txgbe_l2_tn_filter_lookup(l2_tn_info, &key);
4784
4785                 if (node) {
4786                         PMD_DRV_LOG(ERR,
4787                                     "The L2 tunnel filter already exists!");
4788                         return -EINVAL;
4789                 }
4790
4791                 node = rte_zmalloc("txgbe_l2_tn",
4792                                    sizeof(struct txgbe_l2_tn_filter),
4793                                    0);
4794                 if (!node)
4795                         return -ENOMEM;
4796
4797                 rte_memcpy(&node->key,
4798                                  &key,
4799                                  sizeof(struct txgbe_l2_tn_key));
4800                 node->pool = l2_tunnel->pool;
4801                 ret = txgbe_insert_l2_tn_filter(l2_tn_info, node);
4802                 if (ret < 0) {
4803                         rte_free(node);
4804                         return ret;
4805                 }
4806         }
4807
4808         switch (l2_tunnel->l2_tunnel_type) {
4809         case RTE_L2_TUNNEL_TYPE_E_TAG:
4810                 ret = txgbe_e_tag_filter_add(dev, l2_tunnel);
4811                 break;
4812         default:
4813                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
4814                 ret = -EINVAL;
4815                 break;
4816         }
4817
4818         if (!restore && ret < 0)
4819                 (void)txgbe_remove_l2_tn_filter(l2_tn_info, &key);
4820
4821         return ret;
4822 }
4823
4824 /* Delete l2 tunnel filter */
4825 int
4826 txgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev,
4827                                struct txgbe_l2_tunnel_conf *l2_tunnel)
4828 {
4829         int ret;
4830         struct txgbe_l2_tn_info *l2_tn_info = TXGBE_DEV_L2_TN(dev);
4831         struct txgbe_l2_tn_key key;
4832
4833         key.l2_tn_type = l2_tunnel->l2_tunnel_type;
4834         key.tn_id = l2_tunnel->tunnel_id;
4835         ret = txgbe_remove_l2_tn_filter(l2_tn_info, &key);
4836         if (ret < 0)
4837                 return ret;
4838
4839         switch (l2_tunnel->l2_tunnel_type) {
4840         case RTE_L2_TUNNEL_TYPE_E_TAG:
4841                 ret = txgbe_e_tag_filter_del(dev, l2_tunnel);
4842                 break;
4843         default:
4844                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
4845                 ret = -EINVAL;
4846                 break;
4847         }
4848
4849         return ret;
4850 }
4851
4852 static int
4853 txgbe_e_tag_forwarding_en_dis(struct rte_eth_dev *dev, bool en)
4854 {
4855         int ret = 0;
4856         uint32_t ctrl;
4857         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4858
4859         ctrl = rd32(hw, TXGBE_POOLCTL);
4860         ctrl &= ~TXGBE_POOLCTL_MODE_MASK;
4861         if (en)
4862                 ctrl |= TXGBE_PSRPOOL_MODE_ETAG;
4863         wr32(hw, TXGBE_POOLCTL, ctrl);
4864
4865         return ret;
4866 }
4867
4868 /* Add UDP tunneling port */
4869 static int
4870 txgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
4871                               struct rte_eth_udp_tunnel *udp_tunnel)
4872 {
4873         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4874         int ret = 0;
4875
4876         if (udp_tunnel == NULL)
4877                 return -EINVAL;
4878
4879         switch (udp_tunnel->prot_type) {
4880         case RTE_TUNNEL_TYPE_VXLAN:
4881                 if (udp_tunnel->udp_port == 0) {
4882                         PMD_DRV_LOG(ERR, "Add VxLAN port 0 is not allowed.");
4883                         ret = -EINVAL;
4884                         break;
4885                 }
4886                 wr32(hw, TXGBE_VXLANPORT, udp_tunnel->udp_port);
4887                 wr32(hw, TXGBE_VXLANPORTGPE, udp_tunnel->udp_port);
4888                 break;
4889         case RTE_TUNNEL_TYPE_GENEVE:
4890                 if (udp_tunnel->udp_port == 0) {
4891                         PMD_DRV_LOG(ERR, "Add Geneve port 0 is not allowed.");
4892                         ret = -EINVAL;
4893                         break;
4894                 }
4895                 wr32(hw, TXGBE_GENEVEPORT, udp_tunnel->udp_port);
4896                 break;
4897         case RTE_TUNNEL_TYPE_TEREDO:
4898                 if (udp_tunnel->udp_port == 0) {
4899                         PMD_DRV_LOG(ERR, "Add Teredo port 0 is not allowed.");
4900                         ret = -EINVAL;
4901                         break;
4902                 }
4903                 wr32(hw, TXGBE_TEREDOPORT, udp_tunnel->udp_port);
4904                 break;
4905         default:
4906                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
4907                 ret = -EINVAL;
4908                 break;
4909         }
4910
4911         txgbe_flush(hw);
4912
4913         return ret;
4914 }
4915
4916 /* Remove UDP tunneling port */
4917 static int
4918 txgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
4919                               struct rte_eth_udp_tunnel *udp_tunnel)
4920 {
4921         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4922         int ret = 0;
4923         uint16_t cur_port;
4924
4925         if (udp_tunnel == NULL)
4926                 return -EINVAL;
4927
4928         switch (udp_tunnel->prot_type) {
4929         case RTE_TUNNEL_TYPE_VXLAN:
4930                 cur_port = (uint16_t)rd32(hw, TXGBE_VXLANPORT);
4931                 if (cur_port != udp_tunnel->udp_port) {
4932                         PMD_DRV_LOG(ERR, "Port %u does not exist.",
4933                                         udp_tunnel->udp_port);
4934                         ret = -EINVAL;
4935                         break;
4936                 }
4937                 wr32(hw, TXGBE_VXLANPORT, 0);
4938                 wr32(hw, TXGBE_VXLANPORTGPE, 0);
4939                 break;
4940         case RTE_TUNNEL_TYPE_GENEVE:
4941                 cur_port = (uint16_t)rd32(hw, TXGBE_GENEVEPORT);
4942                 if (cur_port != udp_tunnel->udp_port) {
4943                         PMD_DRV_LOG(ERR, "Port %u does not exist.",
4944                                         udp_tunnel->udp_port);
4945                         ret = -EINVAL;
4946                         break;
4947                 }
4948                 wr32(hw, TXGBE_GENEVEPORT, 0);
4949                 break;
4950         case RTE_TUNNEL_TYPE_TEREDO:
4951                 cur_port = (uint16_t)rd32(hw, TXGBE_TEREDOPORT);
4952                 if (cur_port != udp_tunnel->udp_port) {
4953                         PMD_DRV_LOG(ERR, "Port %u does not exist.",
4954                                         udp_tunnel->udp_port);
4955                         ret = -EINVAL;
4956                         break;
4957                 }
4958                 wr32(hw, TXGBE_TEREDOPORT, 0);
4959                 break;
4960         default:
4961                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
4962                 ret = -EINVAL;
4963                 break;
4964         }
4965
4966         txgbe_flush(hw);
4967
4968         return ret;
4969 }
4970
4971 /* restore n-tuple filter */
4972 static inline void
4973 txgbe_ntuple_filter_restore(struct rte_eth_dev *dev)
4974 {
4975         struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(dev);
4976         struct txgbe_5tuple_filter *node;
4977
4978         TAILQ_FOREACH(node, &filter_info->fivetuple_list, entries) {
4979                 txgbe_inject_5tuple_filter(dev, node);
4980         }
4981 }
4982
4983 /* restore ethernet type filter */
4984 static inline void
4985 txgbe_ethertype_filter_restore(struct rte_eth_dev *dev)
4986 {
4987         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4988         struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(dev);
4989         int i;
4990
4991         for (i = 0; i < TXGBE_ETF_ID_MAX; i++) {
4992                 if (filter_info->ethertype_mask & (1 << i)) {
4993                         wr32(hw, TXGBE_ETFLT(i),
4994                                         filter_info->ethertype_filters[i].etqf);
4995                         wr32(hw, TXGBE_ETCLS(i),
4996                                         filter_info->ethertype_filters[i].etqs);
4997                         txgbe_flush(hw);
4998                 }
4999         }
5000 }
5001
5002 /* restore SYN filter */
5003 static inline void
5004 txgbe_syn_filter_restore(struct rte_eth_dev *dev)
5005 {
5006         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
5007         struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(dev);
5008         uint32_t synqf;
5009
5010         synqf = filter_info->syn_info;
5011
5012         if (synqf & TXGBE_SYNCLS_ENA) {
5013                 wr32(hw, TXGBE_SYNCLS, synqf);
5014                 txgbe_flush(hw);
5015         }
5016 }
5017
5018 /* restore L2 tunnel filter */
5019 static inline void
5020 txgbe_l2_tn_filter_restore(struct rte_eth_dev *dev)
5021 {
5022         struct txgbe_l2_tn_info *l2_tn_info = TXGBE_DEV_L2_TN(dev);
5023         struct txgbe_l2_tn_filter *node;
5024         struct txgbe_l2_tunnel_conf l2_tn_conf;
5025
5026         TAILQ_FOREACH(node, &l2_tn_info->l2_tn_list, entries) {
5027                 l2_tn_conf.l2_tunnel_type = node->key.l2_tn_type;
5028                 l2_tn_conf.tunnel_id      = node->key.tn_id;
5029                 l2_tn_conf.pool           = node->pool;
5030                 (void)txgbe_dev_l2_tunnel_filter_add(dev, &l2_tn_conf, TRUE);
5031         }
5032 }
5033
5034 /* restore rss filter */
5035 static inline void
5036 txgbe_rss_filter_restore(struct rte_eth_dev *dev)
5037 {
5038         struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(dev);
5039
5040         if (filter_info->rss_info.conf.queue_num)
5041                 txgbe_config_rss_filter(dev,
5042                         &filter_info->rss_info, TRUE);
5043 }
5044
5045 static int
5046 txgbe_filter_restore(struct rte_eth_dev *dev)
5047 {
5048         txgbe_ntuple_filter_restore(dev);
5049         txgbe_ethertype_filter_restore(dev);
5050         txgbe_syn_filter_restore(dev);
5051         txgbe_fdir_filter_restore(dev);
5052         txgbe_l2_tn_filter_restore(dev);
5053         txgbe_rss_filter_restore(dev);
5054
5055         return 0;
5056 }
5057
5058 static void
5059 txgbe_l2_tunnel_conf(struct rte_eth_dev *dev)
5060 {
5061         struct txgbe_l2_tn_info *l2_tn_info = TXGBE_DEV_L2_TN(dev);
5062         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
5063
5064         if (l2_tn_info->e_tag_en)
5065                 (void)txgbe_e_tag_enable(hw);
5066
5067         if (l2_tn_info->e_tag_fwd_en)
5068                 (void)txgbe_e_tag_forwarding_en_dis(dev, 1);
5069
5070         (void)txgbe_update_e_tag_eth_type(hw, l2_tn_info->e_tag_ether_type);
5071 }
5072
5073 /* remove all the n-tuple filters */
5074 void
5075 txgbe_clear_all_ntuple_filter(struct rte_eth_dev *dev)
5076 {
5077         struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(dev);
5078         struct txgbe_5tuple_filter *p_5tuple;
5079
5080         while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list)))
5081                 txgbe_remove_5tuple_filter(dev, p_5tuple);
5082 }
5083
5084 /* remove all the ether type filters */
5085 void
5086 txgbe_clear_all_ethertype_filter(struct rte_eth_dev *dev)
5087 {
5088         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
5089         struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(dev);
5090         int i;
5091
5092         for (i = 0; i < TXGBE_ETF_ID_MAX; i++) {
5093                 if (filter_info->ethertype_mask & (1 << i) &&
5094                     !filter_info->ethertype_filters[i].conf) {
5095                         (void)txgbe_ethertype_filter_remove(filter_info,
5096                                                             (uint8_t)i);
5097                         wr32(hw, TXGBE_ETFLT(i), 0);
5098                         wr32(hw, TXGBE_ETCLS(i), 0);
5099                         txgbe_flush(hw);
5100                 }
5101         }
5102 }
5103
5104 /* remove the SYN filter */
5105 void
5106 txgbe_clear_syn_filter(struct rte_eth_dev *dev)
5107 {
5108         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
5109         struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(dev);
5110
5111         if (filter_info->syn_info & TXGBE_SYNCLS_ENA) {
5112                 filter_info->syn_info = 0;
5113
5114                 wr32(hw, TXGBE_SYNCLS, 0);
5115                 txgbe_flush(hw);
5116         }
5117 }
5118
5119 /* remove all the L2 tunnel filters */
5120 int
5121 txgbe_clear_all_l2_tn_filter(struct rte_eth_dev *dev)
5122 {
5123         struct txgbe_l2_tn_info *l2_tn_info = TXGBE_DEV_L2_TN(dev);
5124         struct txgbe_l2_tn_filter *l2_tn_filter;
5125         struct txgbe_l2_tunnel_conf l2_tn_conf;
5126         int ret = 0;
5127
5128         while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
5129                 l2_tn_conf.l2_tunnel_type = l2_tn_filter->key.l2_tn_type;
5130                 l2_tn_conf.tunnel_id      = l2_tn_filter->key.tn_id;
5131                 l2_tn_conf.pool           = l2_tn_filter->pool;
5132                 ret = txgbe_dev_l2_tunnel_filter_del(dev, &l2_tn_conf);
5133                 if (ret < 0)
5134                         return ret;
5135         }
5136
5137         return 0;
5138 }
5139
5140 static const struct eth_dev_ops txgbe_eth_dev_ops = {
5141         .dev_configure              = txgbe_dev_configure,
5142         .dev_infos_get              = txgbe_dev_info_get,
5143         .dev_start                  = txgbe_dev_start,
5144         .dev_stop                   = txgbe_dev_stop,
5145         .dev_set_link_up            = txgbe_dev_set_link_up,
5146         .dev_set_link_down          = txgbe_dev_set_link_down,
5147         .dev_close                  = txgbe_dev_close,
5148         .dev_reset                  = txgbe_dev_reset,
5149         .promiscuous_enable         = txgbe_dev_promiscuous_enable,
5150         .promiscuous_disable        = txgbe_dev_promiscuous_disable,
5151         .allmulticast_enable        = txgbe_dev_allmulticast_enable,
5152         .allmulticast_disable       = txgbe_dev_allmulticast_disable,
5153         .link_update                = txgbe_dev_link_update,
5154         .stats_get                  = txgbe_dev_stats_get,
5155         .xstats_get                 = txgbe_dev_xstats_get,
5156         .xstats_get_by_id           = txgbe_dev_xstats_get_by_id,
5157         .stats_reset                = txgbe_dev_stats_reset,
5158         .xstats_reset               = txgbe_dev_xstats_reset,
5159         .xstats_get_names           = txgbe_dev_xstats_get_names,
5160         .xstats_get_names_by_id     = txgbe_dev_xstats_get_names_by_id,
5161         .queue_stats_mapping_set    = txgbe_dev_queue_stats_mapping_set,
5162         .fw_version_get             = txgbe_fw_version_get,
5163         .dev_supported_ptypes_get   = txgbe_dev_supported_ptypes_get,
5164         .mtu_set                    = txgbe_dev_mtu_set,
5165         .vlan_filter_set            = txgbe_vlan_filter_set,
5166         .vlan_tpid_set              = txgbe_vlan_tpid_set,
5167         .vlan_offload_set           = txgbe_vlan_offload_set,
5168         .vlan_strip_queue_set       = txgbe_vlan_strip_queue_set,
5169         .rx_queue_start             = txgbe_dev_rx_queue_start,
5170         .rx_queue_stop              = txgbe_dev_rx_queue_stop,
5171         .tx_queue_start             = txgbe_dev_tx_queue_start,
5172         .tx_queue_stop              = txgbe_dev_tx_queue_stop,
5173         .rx_queue_setup             = txgbe_dev_rx_queue_setup,
5174         .rx_queue_intr_enable       = txgbe_dev_rx_queue_intr_enable,
5175         .rx_queue_intr_disable      = txgbe_dev_rx_queue_intr_disable,
5176         .rx_queue_release           = txgbe_dev_rx_queue_release,
5177         .tx_queue_setup             = txgbe_dev_tx_queue_setup,
5178         .tx_queue_release           = txgbe_dev_tx_queue_release,
5179         .dev_led_on                 = txgbe_dev_led_on,
5180         .dev_led_off                = txgbe_dev_led_off,
5181         .flow_ctrl_get              = txgbe_flow_ctrl_get,
5182         .flow_ctrl_set              = txgbe_flow_ctrl_set,
5183         .priority_flow_ctrl_set     = txgbe_priority_flow_ctrl_set,
5184         .mac_addr_add               = txgbe_add_rar,
5185         .mac_addr_remove            = txgbe_remove_rar,
5186         .mac_addr_set               = txgbe_set_default_mac_addr,
5187         .uc_hash_table_set          = txgbe_uc_hash_table_set,
5188         .uc_all_hash_table_set      = txgbe_uc_all_hash_table_set,
5189         .set_queue_rate_limit       = txgbe_set_queue_rate_limit,
5190         .reta_update                = txgbe_dev_rss_reta_update,
5191         .reta_query                 = txgbe_dev_rss_reta_query,
5192         .rss_hash_update            = txgbe_dev_rss_hash_update,
5193         .rss_hash_conf_get          = txgbe_dev_rss_hash_conf_get,
5194         .flow_ops_get               = txgbe_dev_flow_ops_get,
5195         .set_mc_addr_list           = txgbe_dev_set_mc_addr_list,
5196         .rxq_info_get               = txgbe_rxq_info_get,
5197         .txq_info_get               = txgbe_txq_info_get,
5198         .timesync_enable            = txgbe_timesync_enable,
5199         .timesync_disable           = txgbe_timesync_disable,
5200         .timesync_read_rx_timestamp = txgbe_timesync_read_rx_timestamp,
5201         .timesync_read_tx_timestamp = txgbe_timesync_read_tx_timestamp,
5202         .get_reg                    = txgbe_get_regs,
5203         .get_eeprom_length          = txgbe_get_eeprom_length,
5204         .get_eeprom                 = txgbe_get_eeprom,
5205         .set_eeprom                 = txgbe_set_eeprom,
5206         .get_module_info            = txgbe_get_module_info,
5207         .get_module_eeprom          = txgbe_get_module_eeprom,
5208         .get_dcb_info               = txgbe_dev_get_dcb_info,
5209         .timesync_adjust_time       = txgbe_timesync_adjust_time,
5210         .timesync_read_time         = txgbe_timesync_read_time,
5211         .timesync_write_time        = txgbe_timesync_write_time,
5212         .udp_tunnel_port_add        = txgbe_dev_udp_tunnel_port_add,
5213         .udp_tunnel_port_del        = txgbe_dev_udp_tunnel_port_del,
5214         .tm_ops_get                 = txgbe_tm_ops_get,
5215         .tx_done_cleanup            = txgbe_dev_tx_done_cleanup,
5216 };
5217
5218 RTE_PMD_REGISTER_PCI(net_txgbe, rte_txgbe_pmd);
5219 RTE_PMD_REGISTER_PCI_TABLE(net_txgbe, pci_id_txgbe_map);
5220 RTE_PMD_REGISTER_KMOD_DEP(net_txgbe, "* igb_uio | uio_pci_generic | vfio-pci");
5221
5222 RTE_LOG_REGISTER(txgbe_logtype_init, pmd.net.txgbe.init, NOTICE);
5223 RTE_LOG_REGISTER(txgbe_logtype_driver, pmd.net.txgbe.driver, NOTICE);
5224
5225 #ifdef RTE_LIBRTE_TXGBE_DEBUG_RX
5226         RTE_LOG_REGISTER(txgbe_logtype_rx, pmd.net.txgbe.rx, DEBUG);
5227 #endif
5228 #ifdef RTE_LIBRTE_TXGBE_DEBUG_TX
5229         RTE_LOG_REGISTER(txgbe_logtype_tx, pmd.net.txgbe.tx, DEBUG);
5230 #endif
5231
5232 #ifdef RTE_LIBRTE_TXGBE_DEBUG_TX_FREE
5233         RTE_LOG_REGISTER(txgbe_logtype_tx_free, pmd.net.txgbe.tx_free, DEBUG);
5234 #endif