drivers/net/txgbe/txgbe_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2015-2020
   3  */
   4
   5 #include <stdio.h>
   6 #include <errno.h>
   7 #include <stdint.h>
   8 #include <string.h>
   9 #include <rte_common.h>
  10 #include <ethdev_pci.h>
  11
  12 #include <rte_interrupts.h>
  13 #include <rte_log.h>
  14 #include <rte_debug.h>
  15 #include <rte_pci.h>
  16 #include <rte_memory.h>
  17 #include <rte_eal.h>
  18 #include <rte_alarm.h>
  19 #include <rte_kvargs.h>
  20
  21 #include "txgbe_logs.h"
  22 #include "base/txgbe.h"
  23 #include "txgbe_ethdev.h"
  24 #include "txgbe_rxtx.h"
  25 #include "txgbe_regs_group.h"
  26
  27 static const struct reg_info txgbe_regs_general[] = {
  28         {TXGBE_RST, 1, 1, "TXGBE_RST"},
  29         {TXGBE_STAT, 1, 1, "TXGBE_STAT"},
  30         {TXGBE_PORTCTL, 1, 1, "TXGBE_PORTCTL"},
  31         {TXGBE_SDP, 1, 1, "TXGBE_SDP"},
  32         {TXGBE_SDPCTL, 1, 1, "TXGBE_SDPCTL"},
  33         {TXGBE_LEDCTL, 1, 1, "TXGBE_LEDCTL"},
  34         {0, 0, 0, ""}
  35 };
  36
  37 static const struct reg_info txgbe_regs_nvm[] = {
  38         {0, 0, 0, ""}
  39 };
  40
  41 static const struct reg_info txgbe_regs_interrupt[] = {
  42         {0, 0, 0, ""}
  43 };
  44
  45 static const struct reg_info txgbe_regs_fctl_others[] = {
  46         {0, 0, 0, ""}
  47 };
  48
  49 static const struct reg_info txgbe_regs_rxdma[] = {
  50         {0, 0, 0, ""}
  51 };
  52
  53 static const struct reg_info txgbe_regs_rx[] = {
  54         {0, 0, 0, ""}
  55 };
  56
  57 static struct reg_info txgbe_regs_tx[] = {
  58         {0, 0, 0, ""}
  59 };
  60
  61 static const struct reg_info txgbe_regs_wakeup[] = {
  62         {0, 0, 0, ""}
  63 };
  64
  65 static const struct reg_info txgbe_regs_dcb[] = {
  66         {0, 0, 0, ""}
  67 };
  68
  69 static const struct reg_info txgbe_regs_mac[] = {
  70         {0, 0, 0, ""}
  71 };
  72
  73 static const struct reg_info txgbe_regs_diagnostic[] = {
  74         {0, 0, 0, ""},
  75 };
  76
  77 /* PF registers */
  78 static const struct reg_info *txgbe_regs_others[] = {
  79                                 txgbe_regs_general,
  80                                 txgbe_regs_nvm,
  81                                 txgbe_regs_interrupt,
  82                                 txgbe_regs_fctl_others,
  83                                 txgbe_regs_rxdma,
  84                                 txgbe_regs_rx,
  85                                 txgbe_regs_tx,
  86                                 txgbe_regs_wakeup,
  87                                 txgbe_regs_dcb,
  88                                 txgbe_regs_mac,
  89                                 txgbe_regs_diagnostic,
  90                                 NULL};
  91
  92 static int txgbe_fdir_filter_init(struct rte_eth_dev *eth_dev);
  93 static int txgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev);
  94 static int txgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev);
  95 static int txgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev);
  96 static int  txgbe_dev_set_link_up(struct rte_eth_dev *dev);
  97 static int  txgbe_dev_set_link_down(struct rte_eth_dev *dev);
  98 static int txgbe_dev_close(struct rte_eth_dev *dev);
  99 static int txgbe_dev_link_update(struct rte_eth_dev *dev,
 100                                 int wait_to_complete);
 101 static int txgbe_dev_stats_reset(struct rte_eth_dev *dev);
 102 static void txgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
 103 static void txgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev,
 104                                         uint16_t queue);
 105
 106 static void txgbe_dev_link_status_print(struct rte_eth_dev *dev);
 107 static int txgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on);
 108 static int txgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev);
 109 static int txgbe_dev_misc_interrupt_setup(struct rte_eth_dev *dev);
 110 static int txgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
 111 static int txgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
 112 static int txgbe_dev_interrupt_action(struct rte_eth_dev *dev,
 113                                       struct rte_intr_handle *handle);
 114 static void txgbe_dev_interrupt_handler(void *param);
 115 static void txgbe_dev_interrupt_delayed_handler(void *param);
 116 static void txgbe_configure_msix(struct rte_eth_dev *dev);
 117
 118 static int txgbe_filter_restore(struct rte_eth_dev *dev);
 119 static void txgbe_l2_tunnel_conf(struct rte_eth_dev *dev);
 120
 121 #define TXGBE_SET_HWSTRIP(h, q) do {\
 122                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 123                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 124                 (h)->bitmap[idx] |= 1 << bit;\
 125         } while (0)
 126
 127 #define TXGBE_CLEAR_HWSTRIP(h, q) do {\
 128                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 129                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 130                 (h)->bitmap[idx] &= ~(1 << bit);\
 131         } while (0)
 132
 133 #define TXGBE_GET_HWSTRIP(h, q, r) do {\
 134                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 135                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 136                 (r) = (h)->bitmap[idx] >> bit & 1;\
 137         } while (0)
 138
 139 /*
 140  * The set of PCI devices this driver supports
 141  */
 142 static const struct rte_pci_id pci_id_txgbe_map[] = {
 143         { RTE_PCI_DEVICE(PCI_VENDOR_ID_WANGXUN, TXGBE_DEV_ID_SP1000) },
 144         { RTE_PCI_DEVICE(PCI_VENDOR_ID_WANGXUN, TXGBE_DEV_ID_WX1820) },
 145         { .vendor_id = 0, /* sentinel */ },
 146 };
 147
 148 static const struct rte_eth_desc_lim rx_desc_lim = {
 149         .nb_max = TXGBE_RING_DESC_MAX,
 150         .nb_min = TXGBE_RING_DESC_MIN,
 151         .nb_align = TXGBE_RXD_ALIGN,
 152 };
 153
 154 static const struct rte_eth_desc_lim tx_desc_lim = {
 155         .nb_max = TXGBE_RING_DESC_MAX,
 156         .nb_min = TXGBE_RING_DESC_MIN,
 157         .nb_align = TXGBE_TXD_ALIGN,
 158         .nb_seg_max = TXGBE_TX_MAX_SEG,
 159         .nb_mtu_seg_max = TXGBE_TX_MAX_SEG,
 160 };
 161
 162 static const struct eth_dev_ops txgbe_eth_dev_ops;
 163
 164 #define HW_XSTAT(m) {#m, offsetof(struct txgbe_hw_stats, m)}
 165 #define HW_XSTAT_NAME(m, n) {n, offsetof(struct txgbe_hw_stats, m)}
 166 static const struct rte_txgbe_xstats_name_off rte_txgbe_stats_strings[] = {
 167         /* MNG RxTx */
 168         HW_XSTAT(mng_bmc2host_packets),
 169         HW_XSTAT(mng_host2bmc_packets),
 170         /* Basic RxTx */
 171         HW_XSTAT(rx_packets),
 172         HW_XSTAT(tx_packets),
 173         HW_XSTAT(rx_bytes),
 174         HW_XSTAT(tx_bytes),
 175         HW_XSTAT(rx_total_bytes),
 176         HW_XSTAT(rx_total_packets),
 177         HW_XSTAT(tx_total_packets),
 178         HW_XSTAT(rx_total_missed_packets),
 179         HW_XSTAT(rx_broadcast_packets),
 180         HW_XSTAT(rx_multicast_packets),
 181         HW_XSTAT(rx_management_packets),
 182         HW_XSTAT(tx_management_packets),
 183         HW_XSTAT(rx_management_dropped),
 184
 185         /* Basic Error */
 186         HW_XSTAT(rx_crc_errors),
 187         HW_XSTAT(rx_illegal_byte_errors),
 188         HW_XSTAT(rx_error_bytes),
 189         HW_XSTAT(rx_mac_short_packet_dropped),
 190         HW_XSTAT(rx_length_errors),
 191         HW_XSTAT(rx_undersize_errors),
 192         HW_XSTAT(rx_fragment_errors),
 193         HW_XSTAT(rx_oversize_errors),
 194         HW_XSTAT(rx_jabber_errors),
 195         HW_XSTAT(rx_l3_l4_xsum_error),
 196         HW_XSTAT(mac_local_errors),
 197         HW_XSTAT(mac_remote_errors),
 198
 199         /* Flow Director */
 200         HW_XSTAT(flow_director_added_filters),
 201         HW_XSTAT(flow_director_removed_filters),
 202         HW_XSTAT(flow_director_filter_add_errors),
 203         HW_XSTAT(flow_director_filter_remove_errors),
 204         HW_XSTAT(flow_director_matched_filters),
 205         HW_XSTAT(flow_director_missed_filters),
 206
 207         /* FCoE */
 208         HW_XSTAT(rx_fcoe_crc_errors),
 209         HW_XSTAT(rx_fcoe_mbuf_allocation_errors),
 210         HW_XSTAT(rx_fcoe_dropped),
 211         HW_XSTAT(rx_fcoe_packets),
 212         HW_XSTAT(tx_fcoe_packets),
 213         HW_XSTAT(rx_fcoe_bytes),
 214         HW_XSTAT(tx_fcoe_bytes),
 215         HW_XSTAT(rx_fcoe_no_ddp),
 216         HW_XSTAT(rx_fcoe_no_ddp_ext_buff),
 217
 218         /* MACSEC */
 219         HW_XSTAT(tx_macsec_pkts_untagged),
 220         HW_XSTAT(tx_macsec_pkts_encrypted),
 221         HW_XSTAT(tx_macsec_pkts_protected),
 222         HW_XSTAT(tx_macsec_octets_encrypted),
 223         HW_XSTAT(tx_macsec_octets_protected),
 224         HW_XSTAT(rx_macsec_pkts_untagged),
 225         HW_XSTAT(rx_macsec_pkts_badtag),
 226         HW_XSTAT(rx_macsec_pkts_nosci),
 227         HW_XSTAT(rx_macsec_pkts_unknownsci),
 228         HW_XSTAT(rx_macsec_octets_decrypted),
 229         HW_XSTAT(rx_macsec_octets_validated),
 230         HW_XSTAT(rx_macsec_sc_pkts_unchecked),
 231         HW_XSTAT(rx_macsec_sc_pkts_delayed),
 232         HW_XSTAT(rx_macsec_sc_pkts_late),
 233         HW_XSTAT(rx_macsec_sa_pkts_ok),
 234         HW_XSTAT(rx_macsec_sa_pkts_invalid),
 235         HW_XSTAT(rx_macsec_sa_pkts_notvalid),
 236         HW_XSTAT(rx_macsec_sa_pkts_unusedsa),
 237         HW_XSTAT(rx_macsec_sa_pkts_notusingsa),
 238
 239         /* MAC RxTx */
 240         HW_XSTAT(rx_size_64_packets),
 241         HW_XSTAT(rx_size_65_to_127_packets),
 242         HW_XSTAT(rx_size_128_to_255_packets),
 243         HW_XSTAT(rx_size_256_to_511_packets),
 244         HW_XSTAT(rx_size_512_to_1023_packets),
 245         HW_XSTAT(rx_size_1024_to_max_packets),
 246         HW_XSTAT(tx_size_64_packets),
 247         HW_XSTAT(tx_size_65_to_127_packets),
 248         HW_XSTAT(tx_size_128_to_255_packets),
 249         HW_XSTAT(tx_size_256_to_511_packets),
 250         HW_XSTAT(tx_size_512_to_1023_packets),
 251         HW_XSTAT(tx_size_1024_to_max_packets),
 252
 253         /* Flow Control */
 254         HW_XSTAT(tx_xon_packets),
 255         HW_XSTAT(rx_xon_packets),
 256         HW_XSTAT(tx_xoff_packets),
 257         HW_XSTAT(rx_xoff_packets),
 258
 259         HW_XSTAT_NAME(tx_xon_packets, "tx_flow_control_xon_packets"),
 260         HW_XSTAT_NAME(rx_xon_packets, "rx_flow_control_xon_packets"),
 261         HW_XSTAT_NAME(tx_xoff_packets, "tx_flow_control_xoff_packets"),
 262         HW_XSTAT_NAME(rx_xoff_packets, "rx_flow_control_xoff_packets"),
 263 };
 264
 265 #define TXGBE_NB_HW_STATS (sizeof(rte_txgbe_stats_strings) / \
 266                            sizeof(rte_txgbe_stats_strings[0]))
 267
 268 /* Per-priority statistics */
 269 #define UP_XSTAT(m) {#m, offsetof(struct txgbe_hw_stats, up[0].m)}
 270 static const struct rte_txgbe_xstats_name_off rte_txgbe_up_strings[] = {
 271         UP_XSTAT(rx_up_packets),
 272         UP_XSTAT(tx_up_packets),
 273         UP_XSTAT(rx_up_bytes),
 274         UP_XSTAT(tx_up_bytes),
 275         UP_XSTAT(rx_up_drop_packets),
 276
 277         UP_XSTAT(tx_up_xon_packets),
 278         UP_XSTAT(rx_up_xon_packets),
 279         UP_XSTAT(tx_up_xoff_packets),
 280         UP_XSTAT(rx_up_xoff_packets),
 281         UP_XSTAT(rx_up_dropped),
 282         UP_XSTAT(rx_up_mbuf_alloc_errors),
 283         UP_XSTAT(tx_up_xon2off_packets),
 284 };
 285
 286 #define TXGBE_NB_UP_STATS (sizeof(rte_txgbe_up_strings) / \
 287                            sizeof(rte_txgbe_up_strings[0]))
 288
 289 /* Per-queue statistics */
 290 #define QP_XSTAT(m) {#m, offsetof(struct txgbe_hw_stats, qp[0].m)}
 291 static const struct rte_txgbe_xstats_name_off rte_txgbe_qp_strings[] = {
 292         QP_XSTAT(rx_qp_packets),
 293         QP_XSTAT(tx_qp_packets),
 294         QP_XSTAT(rx_qp_bytes),
 295         QP_XSTAT(tx_qp_bytes),
 296         QP_XSTAT(rx_qp_mc_packets),
 297 };
 298
 299 #define TXGBE_NB_QP_STATS (sizeof(rte_txgbe_qp_strings) / \
 300                            sizeof(rte_txgbe_qp_strings[0]))
 301
 302 static inline int
 303 txgbe_is_sfp(struct txgbe_hw *hw)
 304 {
 305         switch (hw->phy.type) {
 306         case txgbe_phy_sfp_avago:
 307         case txgbe_phy_sfp_ftl:
 308         case txgbe_phy_sfp_intel:
 309         case txgbe_phy_sfp_unknown:
 310         case txgbe_phy_sfp_tyco_passive:
 311         case txgbe_phy_sfp_unknown_passive:
 312                 return 1;
 313         default:
 314                 return 0;
 315         }
 316 }
 317
 318 static inline int32_t
 319 txgbe_pf_reset_hw(struct txgbe_hw *hw)
 320 {
 321         uint32_t ctrl_ext;
 322         int32_t status;
 323
 324         status = hw->mac.reset_hw(hw);
 325
 326         ctrl_ext = rd32(hw, TXGBE_PORTCTL);
 327         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 328         ctrl_ext |= TXGBE_PORTCTL_RSTDONE;
 329         wr32(hw, TXGBE_PORTCTL, ctrl_ext);
 330         txgbe_flush(hw);
 331
 332         if (status == TXGBE_ERR_SFP_NOT_PRESENT)
 333                 status = 0;
 334         return status;
 335 }
 336
 337 static inline void
 338 txgbe_enable_intr(struct rte_eth_dev *dev)
 339 {
 340         struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);
 341         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
 342
 343         wr32(hw, TXGBE_IENMISC, intr->mask_misc);
 344         wr32(hw, TXGBE_IMC(0), TXGBE_IMC_MASK);
 345         wr32(hw, TXGBE_IMC(1), TXGBE_IMC_MASK);
 346         txgbe_flush(hw);
 347 }
 348
 349 static void
 350 txgbe_disable_intr(struct txgbe_hw *hw)
 351 {
 352         PMD_INIT_FUNC_TRACE();
 353
 354         wr32(hw, TXGBE_IENMISC, ~BIT_MASK32);
 355         wr32(hw, TXGBE_IMS(0), TXGBE_IMC_MASK);
 356         wr32(hw, TXGBE_IMS(1), TXGBE_IMC_MASK);
 357         txgbe_flush(hw);
 358 }
 359
 360 static int
 361 txgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 362                                   uint16_t queue_id,
 363                                   uint8_t stat_idx,
 364                                   uint8_t is_rx)
 365 {
 366         struct txgbe_hw *hw = TXGBE_DEV_HW(eth_dev);
 367         struct txgbe_stat_mappings *stat_mappings =
 368                 TXGBE_DEV_STAT_MAPPINGS(eth_dev);
 369         uint32_t qsmr_mask = 0;
 370         uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
 371         uint32_t q_map;
 372         uint8_t n, offset;
 373
 374         if (hw->mac.type != txgbe_mac_raptor)
 375                 return -ENOSYS;
 376
 377         if (stat_idx & !QMAP_FIELD_RESERVED_BITS_MASK)
 378                 return -EIO;
 379
 380         PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d",
 381                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 382                      queue_id, stat_idx);
 383
 384         n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
 385         if (n >= TXGBE_NB_STAT_MAPPING) {
 386                 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
 387                 return -EIO;
 388         }
 389         offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
 390
 391         /* Now clear any previous stat_idx set */
 392         clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 393         if (!is_rx)
 394                 stat_mappings->tqsm[n] &= ~clearing_mask;
 395         else
 396                 stat_mappings->rqsm[n] &= ~clearing_mask;
 397
 398         q_map = (uint32_t)stat_idx;
 399         q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
 400         qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 401         if (!is_rx)
 402                 stat_mappings->tqsm[n] |= qsmr_mask;
 403         else
 404                 stat_mappings->rqsm[n] |= qsmr_mask;
 405
 406         PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d",
 407                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 408                      queue_id, stat_idx);
 409         PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
 410                      is_rx ? stat_mappings->rqsm[n] : stat_mappings->tqsm[n]);
 411         return 0;
 412 }
 413
 414 static void
 415 txgbe_dcb_init(struct txgbe_hw *hw, struct txgbe_dcb_config *dcb_config)
 416 {
 417         int i;
 418         u8 bwgp;
 419         struct txgbe_dcb_tc_config *tc;
 420
 421         UNREFERENCED_PARAMETER(hw);
 422
 423         dcb_config->num_tcs.pg_tcs = TXGBE_DCB_TC_MAX;
 424         dcb_config->num_tcs.pfc_tcs = TXGBE_DCB_TC_MAX;
 425         bwgp = (u8)(100 / TXGBE_DCB_TC_MAX);
 426         for (i = 0; i < TXGBE_DCB_TC_MAX; i++) {
 427                 tc = &dcb_config->tc_config[i];
 428                 tc->path[TXGBE_DCB_TX_CONFIG].bwg_id = i;
 429                 tc->path[TXGBE_DCB_TX_CONFIG].bwg_percent = bwgp + (i & 1);
 430                 tc->path[TXGBE_DCB_RX_CONFIG].bwg_id = i;
 431                 tc->path[TXGBE_DCB_RX_CONFIG].bwg_percent = bwgp + (i & 1);
 432                 tc->pfc = txgbe_dcb_pfc_disabled;
 433         }
 434
 435         /* Initialize default user to priority mapping, UPx->TC0 */
 436         tc = &dcb_config->tc_config[0];
 437         tc->path[TXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
 438         tc->path[TXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
 439         for (i = 0; i < TXGBE_DCB_BWG_MAX; i++) {
 440                 dcb_config->bw_percentage[i][TXGBE_DCB_TX_CONFIG] = 100;
 441                 dcb_config->bw_percentage[i][TXGBE_DCB_RX_CONFIG] = 100;
 442         }
 443         dcb_config->rx_pba_cfg = txgbe_dcb_pba_equal;
 444         dcb_config->pfc_mode_enable = false;
 445         dcb_config->vt_mode = true;
 446         dcb_config->round_robin_enable = false;
 447         /* support all DCB capabilities */
 448         dcb_config->support.capabilities = 0xFF;
 449 }
 450
 451 /*
 452  * Ensure that all locks are released before first NVM or PHY access
 453  */
 454 static void
 455 txgbe_swfw_lock_reset(struct txgbe_hw *hw)
 456 {
 457         uint16_t mask;
 458
 459         /*
 460          * These ones are more tricky since they are common to all ports; but
 461          * swfw_sync retries last long enough (1s) to be almost sure that if
 462          * lock can not be taken it is due to an improper lock of the
 463          * semaphore.
 464          */
 465         mask = TXGBE_MNGSEM_SWPHY |
 466                TXGBE_MNGSEM_SWMBX |
 467                TXGBE_MNGSEM_SWFLASH;
 468         if (hw->mac.acquire_swfw_sync(hw, mask) < 0)
 469                 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
 470
 471         hw->mac.release_swfw_sync(hw, mask);
 472 }
 473
 474 static int
 475 txgbe_handle_devarg(__rte_unused const char *key, const char *value,
 476                   void *extra_args)
 477 {
 478         uint16_t *n = extra_args;
 479
 480         if (value == NULL || extra_args == NULL)
 481                 return -EINVAL;
 482
 483         *n = (uint16_t)strtoul(value, NULL, 10);
 484         if (*n == USHRT_MAX && errno == ERANGE)
 485                 return -1;
 486
 487         return 0;
 488 }
 489
 490 static void
 491 txgbe_parse_devargs(struct txgbe_hw *hw, struct rte_devargs *devargs)
 492 {
 493         struct rte_kvargs *kvlist;
 494         u16 auto_neg = 1;
 495         u16 poll = 0;
 496         u16 present = 1;
 497         u16 sgmii = 0;
 498         u16 ffe_set = 0;
 499         u16 ffe_main = 27;
 500         u16 ffe_pre = 8;
 501         u16 ffe_post = 44;
 502
 503         if (devargs == NULL)
 504                 goto null;
 505
 506         kvlist = rte_kvargs_parse(devargs->args, txgbe_valid_arguments);
 507         if (kvlist == NULL)
 508                 goto null;
 509
 510         rte_kvargs_process(kvlist, TXGBE_DEVARG_BP_AUTO,
 511                            &txgbe_handle_devarg, &auto_neg);
 512         rte_kvargs_process(kvlist, TXGBE_DEVARG_KR_POLL,
 513                            &txgbe_handle_devarg, &poll);
 514         rte_kvargs_process(kvlist, TXGBE_DEVARG_KR_PRESENT,
 515                            &txgbe_handle_devarg, &present);
 516         rte_kvargs_process(kvlist, TXGBE_DEVARG_KX_SGMII,
 517                            &txgbe_handle_devarg, &sgmii);
 518         rte_kvargs_process(kvlist, TXGBE_DEVARG_FFE_SET,
 519                            &txgbe_handle_devarg, &ffe_set);
 520         rte_kvargs_process(kvlist, TXGBE_DEVARG_FFE_MAIN,
 521                            &txgbe_handle_devarg, &ffe_main);
 522         rte_kvargs_process(kvlist, TXGBE_DEVARG_FFE_PRE,
 523                            &txgbe_handle_devarg, &ffe_pre);
 524         rte_kvargs_process(kvlist, TXGBE_DEVARG_FFE_POST,
 525                            &txgbe_handle_devarg, &ffe_post);
 526         rte_kvargs_free(kvlist);
 527
 528 null:
 529         hw->devarg.auto_neg = auto_neg;
 530         hw->devarg.poll = poll;
 531         hw->devarg.present = present;
 532         hw->devarg.sgmii = sgmii;
 533         hw->phy.ffe_set = ffe_set;
 534         hw->phy.ffe_main = ffe_main;
 535         hw->phy.ffe_pre = ffe_pre;
 536         hw->phy.ffe_post = ffe_post;
 537 }
 538
 539 static int
 540 eth_txgbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params __rte_unused)
 541 {
 542         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
 543         struct txgbe_hw *hw = TXGBE_DEV_HW(eth_dev);
 544         struct txgbe_vfta *shadow_vfta = TXGBE_DEV_VFTA(eth_dev);
 545         struct txgbe_hwstrip *hwstrip = TXGBE_DEV_HWSTRIP(eth_dev);
 546         struct txgbe_dcb_config *dcb_config = TXGBE_DEV_DCB_CONFIG(eth_dev);
 547         struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(eth_dev);
 548         struct txgbe_bw_conf *bw_conf = TXGBE_DEV_BW_CONF(eth_dev);
 549         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 550         const struct rte_memzone *mz;
 551         uint32_t ctrl_ext;
 552         uint16_t csum;
 553         int err, i, ret;
 554
 555         PMD_INIT_FUNC_TRACE();
 556
 557         eth_dev->dev_ops = &txgbe_eth_dev_ops;
 558         eth_dev->rx_queue_count       = txgbe_dev_rx_queue_count;
 559         eth_dev->rx_descriptor_status = txgbe_dev_rx_descriptor_status;
 560         eth_dev->tx_descriptor_status = txgbe_dev_tx_descriptor_status;
 561         eth_dev->rx_pkt_burst = &txgbe_recv_pkts;
 562         eth_dev->tx_pkt_burst = &txgbe_xmit_pkts;
 563         eth_dev->tx_pkt_prepare = &txgbe_prep_pkts;
 564
 565         /*
 566          * For secondary processes, we don't initialise any further as primary
 567          * has already done this work. Only check we don't need a different
 568          * RX and TX function.
 569          */
 570         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
 571                 struct txgbe_tx_queue *txq;
 572                 /* TX queue function in primary, set by last queue initialized
 573                  * Tx queue may not initialized by primary process
 574                  */
 575                 if (eth_dev->data->tx_queues) {
 576                         uint16_t nb_tx_queues = eth_dev->data->nb_tx_queues;
 577                         txq = eth_dev->data->tx_queues[nb_tx_queues - 1];
 578                         txgbe_set_tx_function(eth_dev, txq);
 579                 } else {
 580                         /* Use default TX function if we get here */
 581                         PMD_INIT_LOG(NOTICE, "No TX queues configured yet. "
 582                                      "Using default TX function.");
 583                 }
 584
 585                 txgbe_set_rx_function(eth_dev);
 586
 587                 return 0;
 588         }
 589
 590         rte_eth_copy_pci_info(eth_dev, pci_dev);
 591
 592         /* Vendor and Device ID need to be set before init of shared code */
 593         hw->device_id = pci_dev->id.device_id;
 594         hw->vendor_id = pci_dev->id.vendor_id;
 595         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
 596         hw->allow_unsupported_sfp = 1;
 597
 598         /* Reserve memory for interrupt status block */
 599         mz = rte_eth_dma_zone_reserve(eth_dev, "txgbe_driver", -1,
 600                 16, TXGBE_ALIGN, SOCKET_ID_ANY);
 601         if (mz == NULL)
 602                 return -ENOMEM;
 603
 604         hw->isb_dma = TMZ_PADDR(mz);
 605         hw->isb_mem = TMZ_VADDR(mz);
 606
 607         txgbe_parse_devargs(hw, pci_dev->device.devargs);
 608         /* Initialize the shared code (base driver) */
 609         err = txgbe_init_shared_code(hw);
 610         if (err != 0) {
 611                 PMD_INIT_LOG(ERR, "Shared code init failed: %d", err);
 612                 return -EIO;
 613         }
 614
 615         /* Unlock any pending hardware semaphore */
 616         txgbe_swfw_lock_reset(hw);
 617
 618 #ifdef RTE_LIB_SECURITY
 619         /* Initialize security_ctx only for primary process*/
 620         if (txgbe_ipsec_ctx_create(eth_dev))
 621                 return -ENOMEM;
 622 #endif
 623
 624         /* Initialize DCB configuration*/
 625         memset(dcb_config, 0, sizeof(struct txgbe_dcb_config));
 626         txgbe_dcb_init(hw, dcb_config);
 627
 628         /* Get Hardware Flow Control setting */
 629         hw->fc.requested_mode = txgbe_fc_full;
 630         hw->fc.current_mode = txgbe_fc_full;
 631         hw->fc.pause_time = TXGBE_FC_PAUSE_TIME;
 632         for (i = 0; i < TXGBE_DCB_TC_MAX; i++) {
 633                 hw->fc.low_water[i] = TXGBE_FC_XON_LOTH;
 634                 hw->fc.high_water[i] = TXGBE_FC_XOFF_HITH;
 635         }
 636         hw->fc.send_xon = 1;
 637
 638         err = hw->rom.init_params(hw);
 639         if (err != 0) {
 640                 PMD_INIT_LOG(ERR, "The EEPROM init failed: %d", err);
 641                 return -EIO;
 642         }
 643
 644         /* Make sure we have a good EEPROM before we read from it */
 645         err = hw->rom.validate_checksum(hw, &csum);
 646         if (err != 0) {
 647                 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", err);
 648                 return -EIO;
 649         }
 650
 651         err = hw->mac.init_hw(hw);
 652
 653         /*
 654          * Devices with copper phys will fail to initialise if txgbe_init_hw()
 655          * is called too soon after the kernel driver unbinding/binding occurs.
 656          * The failure occurs in txgbe_identify_phy() for all devices,
 657          * but for non-copper devies, txgbe_identify_sfp_module() is
 658          * also called. See txgbe_identify_phy(). The reason for the
 659          * failure is not known, and only occuts when virtualisation features
 660          * are disabled in the bios. A delay of 200ms  was found to be enough by
 661          * trial-and-error, and is doubled to be safe.
 662          */
 663         if (err && hw->phy.media_type == txgbe_media_type_copper) {
 664                 rte_delay_ms(200);
 665                 err = hw->mac.init_hw(hw);
 666         }
 667
 668         if (err == TXGBE_ERR_SFP_NOT_PRESENT)
 669                 err = 0;
 670
 671         if (err == TXGBE_ERR_EEPROM_VERSION) {
 672                 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
 673                              "LOM.  Please be aware there may be issues associated "
 674                              "with your hardware.");
 675                 PMD_INIT_LOG(ERR, "If you are experiencing problems "
 676                              "please contact your hardware representative "
 677                              "who provided you with this hardware.");
 678         } else if (err == TXGBE_ERR_SFP_NOT_SUPPORTED) {
 679                 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
 680         }
 681         if (err) {
 682                 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", err);
 683                 return -EIO;
 684         }
 685
 686         /* Reset the hw statistics */
 687         txgbe_dev_stats_reset(eth_dev);
 688
 689         /* disable interrupt */
 690         txgbe_disable_intr(hw);
 691
 692         /* Allocate memory for storing MAC addresses */
 693         eth_dev->data->mac_addrs = rte_zmalloc("txgbe", RTE_ETHER_ADDR_LEN *
 694                                                hw->mac.num_rar_entries, 0);
 695         if (eth_dev->data->mac_addrs == NULL) {
 696                 PMD_INIT_LOG(ERR,
 697                              "Failed to allocate %u bytes needed to store "
 698                              "MAC addresses",
 699                              RTE_ETHER_ADDR_LEN * hw->mac.num_rar_entries);
 700                 return -ENOMEM;
 701         }
 702
 703         /* Copy the permanent MAC address */
 704         rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.perm_addr,
 705                         &eth_dev->data->mac_addrs[0]);
 706
 707         /* Allocate memory for storing hash filter MAC addresses */
 708         eth_dev->data->hash_mac_addrs = rte_zmalloc("txgbe",
 709                         RTE_ETHER_ADDR_LEN * TXGBE_VMDQ_NUM_UC_MAC, 0);
 710         if (eth_dev->data->hash_mac_addrs == NULL) {
 711                 PMD_INIT_LOG(ERR,
 712                              "Failed to allocate %d bytes needed to store MAC addresses",
 713                              RTE_ETHER_ADDR_LEN * TXGBE_VMDQ_NUM_UC_MAC);
 714                 return -ENOMEM;
 715         }
 716
 717         /* initialize the vfta */
 718         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
 719
 720         /* initialize the hw strip bitmap*/
 721         memset(hwstrip, 0, sizeof(*hwstrip));
 722
 723         /* initialize PF if max_vfs not zero */
 724         ret = txgbe_pf_host_init(eth_dev);
 725         if (ret) {
 726                 rte_free(eth_dev->data->mac_addrs);
 727                 eth_dev->data->mac_addrs = NULL;
 728                 rte_free(eth_dev->data->hash_mac_addrs);
 729                 eth_dev->data->hash_mac_addrs = NULL;
 730                 return ret;
 731         }
 732
 733         ctrl_ext = rd32(hw, TXGBE_PORTCTL);
 734         /* let hardware know driver is loaded */
 735         ctrl_ext |= TXGBE_PORTCTL_DRVLOAD;
 736         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 737         ctrl_ext |= TXGBE_PORTCTL_RSTDONE;
 738         wr32(hw, TXGBE_PORTCTL, ctrl_ext);
 739         txgbe_flush(hw);
 740
 741         if (txgbe_is_sfp(hw) && hw->phy.sfp_type != txgbe_sfp_type_not_present)
 742                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
 743                              (int)hw->mac.type, (int)hw->phy.type,
 744                              (int)hw->phy.sfp_type);
 745         else
 746                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
 747                              (int)hw->mac.type, (int)hw->phy.type);
 748
 749         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
 750                      eth_dev->data->port_id, pci_dev->id.vendor_id,
 751                      pci_dev->id.device_id);
 752
 753         rte_intr_callback_register(intr_handle,
 754                                    txgbe_dev_interrupt_handler, eth_dev);
 755
 756         /* enable uio/vfio intr/eventfd mapping */
 757         rte_intr_enable(intr_handle);
 758
 759         /* enable support intr */
 760         txgbe_enable_intr(eth_dev);
 761
 762         /* initialize filter info */
 763         memset(filter_info, 0,
 764                sizeof(struct txgbe_filter_info));
 765
 766         /* initialize 5tuple filter list */
 767         TAILQ_INIT(&filter_info->fivetuple_list);
 768
 769         /* initialize flow director filter list & hash */
 770         txgbe_fdir_filter_init(eth_dev);
 771
 772         /* initialize l2 tunnel filter list & hash */
 773         txgbe_l2_tn_filter_init(eth_dev);
 774
 775         /* initialize flow filter lists */
 776         txgbe_filterlist_init();
 777
 778         /* initialize bandwidth configuration info */
 779         memset(bw_conf, 0, sizeof(struct txgbe_bw_conf));
 780
 781         /* initialize Traffic Manager configuration */
 782         txgbe_tm_conf_init(eth_dev);
 783
 784         return 0;
 785 }
 786
 787 static int
 788 eth_txgbe_dev_uninit(struct rte_eth_dev *eth_dev)
 789 {
 790         PMD_INIT_FUNC_TRACE();
 791
 792         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 793                 return 0;
 794
 795         txgbe_dev_close(eth_dev);
 796
 797         return 0;
 798 }
 799
 800 static int txgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev)
 801 {
 802         struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(eth_dev);
 803         struct txgbe_5tuple_filter *p_5tuple;
 804
 805         while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) {
 806                 TAILQ_REMOVE(&filter_info->fivetuple_list,
 807                              p_5tuple,
 808                              entries);
 809                 rte_free(p_5tuple);
 810         }
 811         memset(filter_info->fivetuple_mask, 0,
 812                sizeof(uint32_t) * TXGBE_5TUPLE_ARRAY_SIZE);
 813
 814         return 0;
 815 }
 816
 817 static int txgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev)
 818 {
 819         struct txgbe_hw_fdir_info *fdir_info = TXGBE_DEV_FDIR(eth_dev);
 820         struct txgbe_fdir_filter *fdir_filter;
 821
 822         if (fdir_info->hash_map)
 823                 rte_free(fdir_info->hash_map);
 824         if (fdir_info->hash_handle)
 825                 rte_hash_free(fdir_info->hash_handle);
 826
 827         while ((fdir_filter = TAILQ_FIRST(&fdir_info->fdir_list))) {
 828                 TAILQ_REMOVE(&fdir_info->fdir_list,
 829                              fdir_filter,
 830                              entries);
 831                 rte_free(fdir_filter);
 832         }
 833
 834         return 0;
 835 }
 836
 837 static int txgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev)
 838 {
 839         struct txgbe_l2_tn_info *l2_tn_info = TXGBE_DEV_L2_TN(eth_dev);
 840         struct txgbe_l2_tn_filter *l2_tn_filter;
 841
 842         if (l2_tn_info->hash_map)
 843                 rte_free(l2_tn_info->hash_map);
 844         if (l2_tn_info->hash_handle)
 845                 rte_hash_free(l2_tn_info->hash_handle);
 846
 847         while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
 848                 TAILQ_REMOVE(&l2_tn_info->l2_tn_list,
 849                              l2_tn_filter,
 850                              entries);
 851                 rte_free(l2_tn_filter);
 852         }
 853
 854         return 0;
 855 }
 856
 857 static int txgbe_fdir_filter_init(struct rte_eth_dev *eth_dev)
 858 {
 859         struct txgbe_hw_fdir_info *fdir_info = TXGBE_DEV_FDIR(eth_dev);
 860         char fdir_hash_name[RTE_HASH_NAMESIZE];
 861         struct rte_hash_parameters fdir_hash_params = {
 862                 .name = fdir_hash_name,
 863                 .entries = TXGBE_MAX_FDIR_FILTER_NUM,
 864                 .key_len = sizeof(struct txgbe_atr_input),
 865                 .hash_func = rte_hash_crc,
 866                 .hash_func_init_val = 0,
 867                 .socket_id = rte_socket_id(),
 868         };
 869
 870         TAILQ_INIT(&fdir_info->fdir_list);
 871         snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
 872                  "fdir_%s", TDEV_NAME(eth_dev));
 873         fdir_info->hash_handle = rte_hash_create(&fdir_hash_params);
 874         if (!fdir_info->hash_handle) {
 875                 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
 876                 return -EINVAL;
 877         }
 878         fdir_info->hash_map = rte_zmalloc("txgbe",
 879                                           sizeof(struct txgbe_fdir_filter *) *
 880                                           TXGBE_MAX_FDIR_FILTER_NUM,
 881                                           0);
 882         if (!fdir_info->hash_map) {
 883                 PMD_INIT_LOG(ERR,
 884                              "Failed to allocate memory for fdir hash map!");
 885                 return -ENOMEM;
 886         }
 887         fdir_info->mask_added = FALSE;
 888
 889         return 0;
 890 }
 891
 892 static int txgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev)
 893 {
 894         struct txgbe_l2_tn_info *l2_tn_info = TXGBE_DEV_L2_TN(eth_dev);
 895         char l2_tn_hash_name[RTE_HASH_NAMESIZE];
 896         struct rte_hash_parameters l2_tn_hash_params = {
 897                 .name = l2_tn_hash_name,
 898                 .entries = TXGBE_MAX_L2_TN_FILTER_NUM,
 899                 .key_len = sizeof(struct txgbe_l2_tn_key),
 900                 .hash_func = rte_hash_crc,
 901                 .hash_func_init_val = 0,
 902                 .socket_id = rte_socket_id(),
 903         };
 904
 905         TAILQ_INIT(&l2_tn_info->l2_tn_list);
 906         snprintf(l2_tn_hash_name, RTE_HASH_NAMESIZE,
 907                  "l2_tn_%s", TDEV_NAME(eth_dev));
 908         l2_tn_info->hash_handle = rte_hash_create(&l2_tn_hash_params);
 909         if (!l2_tn_info->hash_handle) {
 910                 PMD_INIT_LOG(ERR, "Failed to create L2 TN hash table!");
 911                 return -EINVAL;
 912         }
 913         l2_tn_info->hash_map = rte_zmalloc("txgbe",
 914                                    sizeof(struct txgbe_l2_tn_filter *) *
 915                                    TXGBE_MAX_L2_TN_FILTER_NUM,
 916                                    0);
 917         if (!l2_tn_info->hash_map) {
 918                 PMD_INIT_LOG(ERR,
 919                         "Failed to allocate memory for L2 TN hash map!");
 920                 return -ENOMEM;
 921         }
 922         l2_tn_info->e_tag_en = FALSE;
 923         l2_tn_info->e_tag_fwd_en = FALSE;
 924         l2_tn_info->e_tag_ether_type = RTE_ETHER_TYPE_ETAG;
 925
 926         return 0;
 927 }
 928
 929 static int
 930 eth_txgbe_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
 931                 struct rte_pci_device *pci_dev)
 932 {
 933         return rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
 934                         sizeof(struct txgbe_adapter),
 935                         eth_dev_pci_specific_init, pci_dev,
 936                         eth_txgbe_dev_init, NULL);
 937 }
 938
 939 static int eth_txgbe_pci_remove(struct rte_pci_device *pci_dev)
 940 {
 941         struct rte_eth_dev *ethdev;
 942
 943         ethdev = rte_eth_dev_allocated(pci_dev->device.name);
 944         if (!ethdev)
 945                 return 0;
 946
 947         return rte_eth_dev_destroy(ethdev, eth_txgbe_dev_uninit);
 948 }
 949
 950 static struct rte_pci_driver rte_txgbe_pmd = {
 951         .id_table = pci_id_txgbe_map,
 952         .drv_flags = RTE_PCI_DRV_NEED_MAPPING |
 953                      RTE_PCI_DRV_INTR_LSC,
 954         .probe = eth_txgbe_pci_probe,
 955         .remove = eth_txgbe_pci_remove,
 956 };
 957
 958 static int
 959 txgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
 960 {
 961         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
 962         struct txgbe_vfta *shadow_vfta = TXGBE_DEV_VFTA(dev);
 963         uint32_t vfta;
 964         uint32_t vid_idx;
 965         uint32_t vid_bit;
 966
 967         vid_idx = (uint32_t)((vlan_id >> 5) & 0x7F);
 968         vid_bit = (uint32_t)(1 << (vlan_id & 0x1F));
 969         vfta = rd32(hw, TXGBE_VLANTBL(vid_idx));
 970         if (on)
 971                 vfta |= vid_bit;
 972         else
 973                 vfta &= ~vid_bit;
 974         wr32(hw, TXGBE_VLANTBL(vid_idx), vfta);
 975
 976         /* update local VFTA copy */
 977         shadow_vfta->vfta[vid_idx] = vfta;
 978
 979         return 0;
 980 }
 981
 982 static void
 983 txgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
 984 {
 985         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
 986         struct txgbe_rx_queue *rxq;
 987         bool restart;
 988         uint32_t rxcfg, rxbal, rxbah;
 989
 990         if (on)
 991                 txgbe_vlan_hw_strip_enable(dev, queue);
 992         else
 993                 txgbe_vlan_hw_strip_disable(dev, queue);
 994
 995         rxq = dev->data->rx_queues[queue];
 996         rxbal = rd32(hw, TXGBE_RXBAL(rxq->reg_idx));
 997         rxbah = rd32(hw, TXGBE_RXBAH(rxq->reg_idx));
 998         rxcfg = rd32(hw, TXGBE_RXCFG(rxq->reg_idx));
 999         if (rxq->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) {
1000                 restart = (rxcfg & TXGBE_RXCFG_ENA) &&
1001                         !(rxcfg & TXGBE_RXCFG_VLAN);
1002                 rxcfg |= TXGBE_RXCFG_VLAN;
1003         } else {
1004                 restart = (rxcfg & TXGBE_RXCFG_ENA) &&
1005                         (rxcfg & TXGBE_RXCFG_VLAN);
1006                 rxcfg &= ~TXGBE_RXCFG_VLAN;
1007         }
1008         rxcfg &= ~TXGBE_RXCFG_ENA;
1009
1010         if (restart) {
1011                 /* set vlan strip for ring */
1012                 txgbe_dev_rx_queue_stop(dev, queue);
1013                 wr32(hw, TXGBE_RXBAL(rxq->reg_idx), rxbal);
1014                 wr32(hw, TXGBE_RXBAH(rxq->reg_idx), rxbah);
1015                 wr32(hw, TXGBE_RXCFG(rxq->reg_idx), rxcfg);
1016                 txgbe_dev_rx_queue_start(dev, queue);
1017         }
1018 }
1019
1020 static int
1021 txgbe_vlan_tpid_set(struct rte_eth_dev *dev,
1022                     enum rte_vlan_type vlan_type,
1023                     uint16_t tpid)
1024 {
1025         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
1026         int ret = 0;
1027         uint32_t portctrl, vlan_ext, qinq;
1028
1029         portctrl = rd32(hw, TXGBE_PORTCTL);
1030
1031         vlan_ext = (portctrl & TXGBE_PORTCTL_VLANEXT);
1032         qinq = vlan_ext && (portctrl & TXGBE_PORTCTL_QINQ);
1033         switch (vlan_type) {
1034         case ETH_VLAN_TYPE_INNER:
1035                 if (vlan_ext) {
1036                         wr32m(hw, TXGBE_VLANCTL,
1037                                 TXGBE_VLANCTL_TPID_MASK,
1038                                 TXGBE_VLANCTL_TPID(tpid));
1039                         wr32m(hw, TXGBE_DMATXCTRL,
1040                                 TXGBE_DMATXCTRL_TPID_MASK,
1041                                 TXGBE_DMATXCTRL_TPID(tpid));
1042                 } else {
1043                         ret = -ENOTSUP;
1044                         PMD_DRV_LOG(ERR, "Inner type is not supported"
1045                                     " by single VLAN");
1046                 }
1047
1048                 if (qinq) {
1049                         wr32m(hw, TXGBE_TAGTPID(0),
1050                                 TXGBE_TAGTPID_LSB_MASK,
1051                                 TXGBE_TAGTPID_LSB(tpid));
1052                 }
1053                 break;
1054         case ETH_VLAN_TYPE_OUTER:
1055                 if (vlan_ext) {
1056                         /* Only the high 16-bits is valid */
1057                         wr32m(hw, TXGBE_EXTAG,
1058                                 TXGBE_EXTAG_VLAN_MASK,
1059                                 TXGBE_EXTAG_VLAN(tpid));
1060                 } else {
1061                         wr32m(hw, TXGBE_VLANCTL,
1062                                 TXGBE_VLANCTL_TPID_MASK,
1063                                 TXGBE_VLANCTL_TPID(tpid));
1064                         wr32m(hw, TXGBE_DMATXCTRL,
1065                                 TXGBE_DMATXCTRL_TPID_MASK,
1066                                 TXGBE_DMATXCTRL_TPID(tpid));
1067                 }
1068
1069                 if (qinq) {
1070                         wr32m(hw, TXGBE_TAGTPID(0),
1071                                 TXGBE_TAGTPID_MSB_MASK,
1072                                 TXGBE_TAGTPID_MSB(tpid));
1073                 }
1074                 break;
1075         default:
1076                 PMD_DRV_LOG(ERR, "Unsupported VLAN type %d", vlan_type);
1077                 return -EINVAL;
1078         }
1079
1080         return ret;
1081 }
1082
1083 void
1084 txgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1085 {
1086         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
1087         uint32_t vlnctrl;
1088
1089         PMD_INIT_FUNC_TRACE();
1090
1091         /* Filter Table Disable */
1092         vlnctrl = rd32(hw, TXGBE_VLANCTL);
1093         vlnctrl &= ~TXGBE_VLANCTL_VFE;
1094         wr32(hw, TXGBE_VLANCTL, vlnctrl);
1095 }
1096
1097 void
1098 txgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1099 {
1100         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
1101         struct txgbe_vfta *shadow_vfta = TXGBE_DEV_VFTA(dev);
1102         uint32_t vlnctrl;
1103         uint16_t i;
1104
1105         PMD_INIT_FUNC_TRACE();
1106
1107         /* Filter Table Enable */
1108         vlnctrl = rd32(hw, TXGBE_VLANCTL);
1109         vlnctrl &= ~TXGBE_VLANCTL_CFIENA;
1110         vlnctrl |= TXGBE_VLANCTL_VFE;
1111         wr32(hw, TXGBE_VLANCTL, vlnctrl);
1112
1113         /* write whatever is in local vfta copy */
1114         for (i = 0; i < TXGBE_VFTA_SIZE; i++)
1115                 wr32(hw, TXGBE_VLANTBL(i), shadow_vfta->vfta[i]);
1116 }
1117
1118 void
1119 txgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1120 {
1121         struct txgbe_hwstrip *hwstrip = TXGBE_DEV_HWSTRIP(dev);
1122         struct txgbe_rx_queue *rxq;
1123
1124         if (queue >= TXGBE_MAX_RX_QUEUE_NUM)
1125                 return;
1126
1127         if (on)
1128                 TXGBE_SET_HWSTRIP(hwstrip, queue);
1129         else
1130                 TXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1131
1132         if (queue >= dev->data->nb_rx_queues)
1133                 return;
1134
1135         rxq = dev->data->rx_queues[queue];
1136
1137         if (on) {
1138                 rxq->vlan_flags = PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
1139                 rxq->offloads |= DEV_RX_OFFLOAD_VLAN_STRIP;
1140         } else {
1141                 rxq->vlan_flags = PKT_RX_VLAN;
1142                 rxq->offloads &= ~DEV_RX_OFFLOAD_VLAN_STRIP;
1143         }
1144 }
1145
1146 static void
1147 txgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
1148 {
1149         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
1150         uint32_t ctrl;
1151
1152         PMD_INIT_FUNC_TRACE();
1153
1154         ctrl = rd32(hw, TXGBE_RXCFG(queue));
1155         ctrl &= ~TXGBE_RXCFG_VLAN;
1156         wr32(hw, TXGBE_RXCFG(queue), ctrl);
1157
1158         /* record those setting for HW strip per queue */
1159         txgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
1160 }
1161
1162 static void
1163 txgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
1164 {
1165         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
1166         uint32_t ctrl;
1167
1168         PMD_INIT_FUNC_TRACE();
1169
1170         ctrl = rd32(hw, TXGBE_RXCFG(queue));
1171         ctrl |= TXGBE_RXCFG_VLAN;
1172         wr32(hw, TXGBE_RXCFG(queue), ctrl);
1173
1174         /* record those setting for HW strip per queue */
1175         txgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
1176 }
1177
1178 static void
1179 txgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
1180 {
1181         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
1182         uint32_t ctrl;
1183
1184         PMD_INIT_FUNC_TRACE();
1185
1186         ctrl = rd32(hw, TXGBE_PORTCTL);
1187         ctrl &= ~TXGBE_PORTCTL_VLANEXT;
1188         ctrl &= ~TXGBE_PORTCTL_QINQ;
1189         wr32(hw, TXGBE_PORTCTL, ctrl);
1190 }
1191
1192 static void
1193 txgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
1194 {
1195         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
1196         struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
1197         struct rte_eth_txmode *txmode = &dev->data->dev_conf.txmode;
1198         uint32_t ctrl;
1199
1200         PMD_INIT_FUNC_TRACE();
1201
1202         ctrl  = rd32(hw, TXGBE_PORTCTL);
1203         ctrl |= TXGBE_PORTCTL_VLANEXT;
1204         if (rxmode->offloads & DEV_RX_OFFLOAD_QINQ_STRIP ||
1205             txmode->offloads & DEV_TX_OFFLOAD_QINQ_INSERT)
1206                 ctrl |= TXGBE_PORTCTL_QINQ;
1207         wr32(hw, TXGBE_PORTCTL, ctrl);
1208 }
1209
1210 void
1211 txgbe_vlan_hw_strip_config(struct rte_eth_dev *dev)
1212 {
1213         struct txgbe_rx_queue *rxq;
1214         uint16_t i;
1215
1216         PMD_INIT_FUNC_TRACE();
1217
1218         for (i = 0; i < dev->data->nb_rx_queues; i++) {
1219                 rxq = dev->data->rx_queues[i];
1220
1221                 if (rxq->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1222                         txgbe_vlan_strip_queue_set(dev, i, 1);
1223                 else
1224                         txgbe_vlan_strip_queue_set(dev, i, 0);
1225         }
1226 }
1227
1228 void
1229 txgbe_config_vlan_strip_on_all_queues(struct rte_eth_dev *dev, int mask)
1230 {
1231         uint16_t i;
1232         struct rte_eth_rxmode *rxmode;
1233         struct txgbe_rx_queue *rxq;
1234
1235         if (mask & ETH_VLAN_STRIP_MASK) {
1236                 rxmode = &dev->data->dev_conf.rxmode;
1237                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1238                         for (i = 0; i < dev->data->nb_rx_queues; i++) {
1239                                 rxq = dev->data->rx_queues[i];
1240                                 rxq->offloads |= DEV_RX_OFFLOAD_VLAN_STRIP;
1241                         }
1242                 else
1243                         for (i = 0; i < dev->data->nb_rx_queues; i++) {
1244                                 rxq = dev->data->rx_queues[i];
1245                                 rxq->offloads &= ~DEV_RX_OFFLOAD_VLAN_STRIP;
1246                         }
1247         }
1248 }
1249
1250 static int
1251 txgbe_vlan_offload_config(struct rte_eth_dev *dev, int mask)
1252 {
1253         struct rte_eth_rxmode *rxmode;
1254         rxmode = &dev->data->dev_conf.rxmode;
1255
1256         if (mask & ETH_VLAN_STRIP_MASK)
1257                 txgbe_vlan_hw_strip_config(dev);
1258
1259         if (mask & ETH_VLAN_FILTER_MASK) {
1260                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
1261                         txgbe_vlan_hw_filter_enable(dev);
1262                 else
1263                         txgbe_vlan_hw_filter_disable(dev);
1264         }
1265
1266         if (mask & ETH_VLAN_EXTEND_MASK) {
1267                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
1268                         txgbe_vlan_hw_extend_enable(dev);
1269                 else
1270                         txgbe_vlan_hw_extend_disable(dev);
1271         }
1272
1273         return 0;
1274 }
1275
1276 static int
1277 txgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1278 {
1279         txgbe_config_vlan_strip_on_all_queues(dev, mask);
1280
1281         txgbe_vlan_offload_config(dev, mask);
1282
1283         return 0;
1284 }
1285
1286 static void
1287 txgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1288 {
1289         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
1290         /* VLNCTL: enable vlan filtering and allow all vlan tags through */
1291         uint32_t vlanctrl = rd32(hw, TXGBE_VLANCTL);
1292
1293         vlanctrl |= TXGBE_VLANCTL_VFE; /* enable vlan filters */
1294         wr32(hw, TXGBE_VLANCTL, vlanctrl);
1295 }
1296
1297 static int
1298 txgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q)
1299 {
1300         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1301
1302         switch (nb_rx_q) {
1303         case 1:
1304         case 2:
1305                 RTE_ETH_DEV_SRIOV(dev).active = ETH_64_POOLS;
1306                 break;
1307         case 4:
1308                 RTE_ETH_DEV_SRIOV(dev).active = ETH_32_POOLS;
1309                 break;
1310         default:
1311                 return -EINVAL;
1312         }
1313
1314         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool =
1315                 TXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
1316         RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx =
1317                 pci_dev->max_vfs * RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
1318         return 0;
1319 }
1320
1321 static int
1322 txgbe_check_mq_mode(struct rte_eth_dev *dev)
1323 {
1324         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
1325         uint16_t nb_rx_q = dev->data->nb_rx_queues;
1326         uint16_t nb_tx_q = dev->data->nb_tx_queues;
1327
1328         if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
1329                 /* check multi-queue mode */
1330                 switch (dev_conf->rxmode.mq_mode) {
1331                 case ETH_MQ_RX_VMDQ_DCB:
1332                         PMD_INIT_LOG(INFO, "ETH_MQ_RX_VMDQ_DCB mode supported in SRIOV");
1333                         break;
1334                 case ETH_MQ_RX_VMDQ_DCB_RSS:
1335                         /* DCB/RSS VMDQ in SRIOV mode, not implement yet */
1336                         PMD_INIT_LOG(ERR, "SRIOV active,"
1337                                         " unsupported mq_mode rx %d.",
1338                                         dev_conf->rxmode.mq_mode);
1339                         return -EINVAL;
1340                 case ETH_MQ_RX_RSS:
1341                 case ETH_MQ_RX_VMDQ_RSS:
1342                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_RSS;
1343                         if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)
1344                                 if (txgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) {
1345                                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1346                                                 " invalid queue number"
1347                                                 " for VMDQ RSS, allowed"
1348                                                 " value are 1, 2 or 4.");
1349                                         return -EINVAL;
1350                                 }
1351                         break;
1352                 case ETH_MQ_RX_VMDQ_ONLY:
1353                 case ETH_MQ_RX_NONE:
1354                         /* if nothing mq mode configure, use default scheme */
1355                         dev->data->dev_conf.rxmode.mq_mode =
1356                                 ETH_MQ_RX_VMDQ_ONLY;
1357                         break;
1358                 default: /* ETH_MQ_RX_DCB, ETH_MQ_RX_DCB_RSS or ETH_MQ_TX_DCB*/
1359                         /* SRIOV only works in VMDq enable mode */
1360                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1361                                         " wrong mq_mode rx %d.",
1362                                         dev_conf->rxmode.mq_mode);
1363                         return -EINVAL;
1364                 }
1365
1366                 switch (dev_conf->txmode.mq_mode) {
1367                 case ETH_MQ_TX_VMDQ_DCB:
1368                         PMD_INIT_LOG(INFO, "ETH_MQ_TX_VMDQ_DCB mode supported in SRIOV");
1369                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_DCB;
1370                         break;
1371                 default: /* ETH_MQ_TX_VMDQ_ONLY or ETH_MQ_TX_NONE */
1372                         dev->data->dev_conf.txmode.mq_mode =
1373                                 ETH_MQ_TX_VMDQ_ONLY;
1374                         break;
1375                 }
1376
1377                 /* check valid queue number */
1378                 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) ||
1379                     (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) {
1380                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1381                                         " nb_rx_q=%d nb_tx_q=%d queue number"
1382                                         " must be less than or equal to %d.",
1383                                         nb_rx_q, nb_tx_q,
1384                                         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool);
1385                         return -EINVAL;
1386                 }
1387         } else {
1388                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
1389                         PMD_INIT_LOG(ERR, "VMDQ+DCB+RSS mq_mode is"
1390                                           " not supported.");
1391                         return -EINVAL;
1392                 }
1393                 /* check configuration for vmdb+dcb mode */
1394                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB) {
1395                         const struct rte_eth_vmdq_dcb_conf *conf;
1396
1397                         if (nb_rx_q != TXGBE_VMDQ_DCB_NB_QUEUES) {
1398                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.",
1399                                                 TXGBE_VMDQ_DCB_NB_QUEUES);
1400                                 return -EINVAL;
1401                         }
1402                         conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf;
1403                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
1404                                conf->nb_queue_pools == ETH_32_POOLS)) {
1405                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
1406                                                 " nb_queue_pools must be %d or %d.",
1407                                                 ETH_16_POOLS, ETH_32_POOLS);
1408                                 return -EINVAL;
1409                         }
1410                 }
1411                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) {
1412                         const struct rte_eth_vmdq_dcb_tx_conf *conf;
1413
1414                         if (nb_tx_q != TXGBE_VMDQ_DCB_NB_QUEUES) {
1415                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d",
1416                                                  TXGBE_VMDQ_DCB_NB_QUEUES);
1417                                 return -EINVAL;
1418                         }
1419                         conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf;
1420                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
1421                                conf->nb_queue_pools == ETH_32_POOLS)) {
1422                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
1423                                                 " nb_queue_pools != %d and"
1424                                                 " nb_queue_pools != %d.",
1425                                                 ETH_16_POOLS, ETH_32_POOLS);
1426                                 return -EINVAL;
1427                         }
1428                 }
1429
1430                 /* For DCB mode check our configuration before we go further */
1431                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_DCB) {
1432                         const struct rte_eth_dcb_rx_conf *conf;
1433
1434                         conf = &dev_conf->rx_adv_conf.dcb_rx_conf;
1435                         if (!(conf->nb_tcs == ETH_4_TCS ||
1436                                conf->nb_tcs == ETH_8_TCS)) {
1437                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
1438                                                 " and nb_tcs != %d.",
1439                                                 ETH_4_TCS, ETH_8_TCS);
1440                                 return -EINVAL;
1441                         }
1442                 }
1443
1444                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_DCB) {
1445                         const struct rte_eth_dcb_tx_conf *conf;
1446
1447                         conf = &dev_conf->tx_adv_conf.dcb_tx_conf;
1448                         if (!(conf->nb_tcs == ETH_4_TCS ||
1449                                conf->nb_tcs == ETH_8_TCS)) {
1450                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
1451                                                 " and nb_tcs != %d.",
1452                                                 ETH_4_TCS, ETH_8_TCS);
1453                                 return -EINVAL;
1454                         }
1455                 }
1456         }
1457         return 0;
1458 }
1459
1460 static int
1461 txgbe_dev_configure(struct rte_eth_dev *dev)
1462 {
1463         struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);
1464         struct txgbe_adapter *adapter = TXGBE_DEV_ADAPTER(dev);
1465         int ret;
1466
1467         PMD_INIT_FUNC_TRACE();
1468
1469         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
1470                 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
1471
1472         /* multiple queue mode checking */
1473         ret  = txgbe_check_mq_mode(dev);
1474         if (ret != 0) {
1475                 PMD_DRV_LOG(ERR, "txgbe_check_mq_mode fails with %d.",
1476                             ret);
1477                 return ret;
1478         }
1479
1480         /* set flag to update link status after init */
1481         intr->flags |= TXGBE_FLAG_NEED_LINK_UPDATE;
1482
1483         /*
1484          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
1485          * allocation Rx preconditions we will reset it.
1486          */
1487         adapter->rx_bulk_alloc_allowed = true;
1488
1489         return 0;
1490 }
1491
1492 static void
1493 txgbe_dev_phy_intr_setup(struct rte_eth_dev *dev)
1494 {
1495         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
1496         struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);
1497         uint32_t gpie;
1498
1499         gpie = rd32(hw, TXGBE_GPIOINTEN);
1500         gpie |= TXGBE_GPIOBIT_6;
1501         wr32(hw, TXGBE_GPIOINTEN, gpie);
1502         intr->mask_misc |= TXGBE_ICRMISC_GPIO;
1503         intr->mask_misc |= TXGBE_ICRMISC_ANDONE;
1504 }
1505
1506 int
1507 txgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
1508                         uint16_t tx_rate, uint64_t q_msk)
1509 {
1510         struct txgbe_hw *hw;
1511         struct txgbe_vf_info *vfinfo;
1512         struct rte_eth_link link;
1513         uint8_t  nb_q_per_pool;
1514         uint32_t queue_stride;
1515         uint32_t queue_idx, idx = 0, vf_idx;
1516         uint32_t queue_end;
1517         uint16_t total_rate = 0;
1518         struct rte_pci_device *pci_dev;
1519         int ret;
1520
1521         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1522         ret = rte_eth_link_get_nowait(dev->data->port_id, &link);
1523         if (ret < 0)
1524                 return ret;
1525
1526         if (vf >= pci_dev->max_vfs)
1527                 return -EINVAL;
1528
1529         if (tx_rate > link.link_speed)
1530                 return -EINVAL;
1531
1532         if (q_msk == 0)
1533                 return 0;
1534
1535         hw = TXGBE_DEV_HW(dev);
1536         vfinfo = *(TXGBE_DEV_VFDATA(dev));
1537         nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
1538         queue_stride = TXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
1539         queue_idx = vf * queue_stride;
1540         queue_end = queue_idx + nb_q_per_pool - 1;
1541         if (queue_end >= hw->mac.max_tx_queues)
1542                 return -EINVAL;
1543
1544         if (vfinfo) {
1545                 for (vf_idx = 0; vf_idx < pci_dev->max_vfs; vf_idx++) {
1546                         if (vf_idx == vf)
1547                                 continue;
1548                         for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
1549                                 idx++)
1550                                 total_rate += vfinfo[vf_idx].tx_rate[idx];
1551                 }
1552         } else {
1553                 return -EINVAL;
1554         }
1555
1556         /* Store tx_rate for this vf. */
1557         for (idx = 0; idx < nb_q_per_pool; idx++) {
1558                 if (((uint64_t)0x1 << idx) & q_msk) {
1559                         if (vfinfo[vf].tx_rate[idx] != tx_rate)
1560                                 vfinfo[vf].tx_rate[idx] = tx_rate;
1561                         total_rate += tx_rate;
1562                 }
1563         }
1564
1565         if (total_rate > dev->data->dev_link.link_speed) {
1566                 /* Reset stored TX rate of the VF if it causes exceed
1567                  * link speed.
1568                  */
1569                 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
1570                 return -EINVAL;
1571         }
1572
1573         /* Set ARBTXRATE of each queue/pool for vf X  */
1574         for (; queue_idx <= queue_end; queue_idx++) {
1575                 if (0x1 & q_msk)
1576                         txgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
1577                 q_msk = q_msk >> 1;
1578         }
1579
1580         return 0;
1581 }
1582
1583 /*
1584  * Configure device link speed and setup link.
1585  * It returns 0 on success.
1586  */
1587 static int
1588 txgbe_dev_start(struct rte_eth_dev *dev)
1589 {
1590         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
1591         struct txgbe_hw_stats *hw_stats = TXGBE_DEV_STATS(dev);
1592         struct txgbe_vf_info *vfinfo = *TXGBE_DEV_VFDATA(dev);
1593         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1594         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1595         uint32_t intr_vector = 0;
1596         int err;
1597         bool link_up = false, negotiate = 0;
1598         uint32_t speed = 0;
1599         uint32_t allowed_speeds = 0;
1600         int mask = 0;
1601         int status;
1602         uint16_t vf, idx;
1603         uint32_t *link_speeds;
1604         struct txgbe_tm_conf *tm_conf = TXGBE_DEV_TM_CONF(dev);
1605
1606         PMD_INIT_FUNC_TRACE();
1607
1608         /* TXGBE devices don't support:
1609          *    - half duplex (checked afterwards for valid speeds)
1610          *    - fixed speed: TODO implement
1611          */
1612         if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
1613                 PMD_INIT_LOG(ERR,
1614                 "Invalid link_speeds for port %u, fix speed not supported",
1615                                 dev->data->port_id);
1616                 return -EINVAL;
1617         }
1618
1619         /* Stop the link setup handler before resetting the HW. */
1620         rte_eal_alarm_cancel(txgbe_dev_setup_link_alarm_handler, dev);
1621
1622         /* disable uio/vfio intr/eventfd mapping */
1623         rte_intr_disable(intr_handle);
1624
1625         /* stop adapter */
1626         hw->adapter_stopped = 0;
1627         txgbe_stop_hw(hw);
1628
1629         /* reinitialize adapter
1630          * this calls reset and start
1631          */
1632         hw->nb_rx_queues = dev->data->nb_rx_queues;
1633         hw->nb_tx_queues = dev->data->nb_tx_queues;
1634         status = txgbe_pf_reset_hw(hw);
1635         if (status != 0)
1636                 return -1;
1637         hw->mac.start_hw(hw);
1638         hw->mac.get_link_status = true;
1639
1640         /* configure PF module if SRIOV enabled */
1641         txgbe_pf_host_configure(dev);
1642
1643         txgbe_dev_phy_intr_setup(dev);
1644
1645         /* check and configure queue intr-vector mapping */
1646         if ((rte_intr_cap_multiple(intr_handle) ||
1647              !RTE_ETH_DEV_SRIOV(dev).active) &&
1648             dev->data->dev_conf.intr_conf.rxq != 0) {
1649                 intr_vector = dev->data->nb_rx_queues;
1650                 if (rte_intr_efd_enable(intr_handle, intr_vector))
1651                         return -1;
1652         }
1653
1654         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1655                 intr_handle->intr_vec =
1656                         rte_zmalloc("intr_vec",
1657                                     dev->data->nb_rx_queues * sizeof(int), 0);
1658                 if (intr_handle->intr_vec == NULL) {
1659                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
1660                                      " intr_vec", dev->data->nb_rx_queues);
1661                         return -ENOMEM;
1662                 }
1663         }
1664
1665         /* confiugre msix for sleep until rx interrupt */
1666         txgbe_configure_msix(dev);
1667
1668         /* initialize transmission unit */
1669         txgbe_dev_tx_init(dev);
1670
1671         /* This can fail when allocating mbufs for descriptor rings */
1672         err = txgbe_dev_rx_init(dev);
1673         if (err) {
1674                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
1675                 goto error;
1676         }
1677
1678         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
1679                 ETH_VLAN_EXTEND_MASK;
1680         err = txgbe_vlan_offload_config(dev, mask);
1681         if (err) {
1682                 PMD_INIT_LOG(ERR, "Unable to set VLAN offload");
1683                 goto error;
1684         }
1685
1686         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1687                 /* Enable vlan filtering for VMDq */
1688                 txgbe_vmdq_vlan_hw_filter_enable(dev);
1689         }
1690
1691         /* Configure DCB hw */
1692         txgbe_configure_pb(dev);
1693         txgbe_configure_port(dev);
1694         txgbe_configure_dcb(dev);
1695
1696         if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
1697                 err = txgbe_fdir_configure(dev);
1698                 if (err)
1699                         goto error;
1700         }
1701
1702         /* Restore vf rate limit */
1703         if (vfinfo != NULL) {
1704                 for (vf = 0; vf < pci_dev->max_vfs; vf++)
1705                         for (idx = 0; idx < TXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
1706                                 if (vfinfo[vf].tx_rate[idx] != 0)
1707                                         txgbe_set_vf_rate_limit(dev, vf,
1708                                                 vfinfo[vf].tx_rate[idx],
1709                                                 1 << idx);
1710         }
1711
1712         err = txgbe_dev_rxtx_start(dev);
1713         if (err < 0) {
1714                 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
1715                 goto error;
1716         }
1717
1718         /* Skip link setup if loopback mode is enabled. */
1719         if (hw->mac.type == txgbe_mac_raptor &&
1720             dev->data->dev_conf.lpbk_mode)
1721                 goto skip_link_setup;
1722
1723         if (txgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
1724                 err = hw->mac.setup_sfp(hw);
1725                 if (err)
1726                         goto error;
1727         }
1728
1729         if (hw->phy.media_type == txgbe_media_type_copper) {
1730                 /* Turn on the copper */
1731                 hw->phy.set_phy_power(hw, true);
1732         } else {
1733                 /* Turn on the laser */
1734                 hw->mac.enable_tx_laser(hw);
1735         }
1736
1737         if ((hw->subsystem_device_id & 0xFF) != TXGBE_DEV_ID_KR_KX_KX4)
1738                 err = hw->mac.check_link(hw, &speed, &link_up, 0);
1739         if (err)
1740                 goto error;
1741         dev->data->dev_link.link_status = link_up;
1742
1743         err = hw->mac.get_link_capabilities(hw, &speed, &negotiate);
1744         if (err)
1745                 goto error;
1746
1747         allowed_speeds = ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
1748                         ETH_LINK_SPEED_10G;
1749
1750         link_speeds = &dev->data->dev_conf.link_speeds;
1751         if (*link_speeds & ~allowed_speeds) {
1752                 PMD_INIT_LOG(ERR, "Invalid link setting");
1753                 goto error;
1754         }
1755
1756         speed = 0x0;
1757         if (*link_speeds == ETH_LINK_SPEED_AUTONEG) {
1758                 speed = (TXGBE_LINK_SPEED_100M_FULL |
1759                          TXGBE_LINK_SPEED_1GB_FULL |
1760                          TXGBE_LINK_SPEED_10GB_FULL);
1761         } else {
1762                 if (*link_speeds & ETH_LINK_SPEED_10G)
1763                         speed |= TXGBE_LINK_SPEED_10GB_FULL;
1764                 if (*link_speeds & ETH_LINK_SPEED_5G)
1765                         speed |= TXGBE_LINK_SPEED_5GB_FULL;
1766                 if (*link_speeds & ETH_LINK_SPEED_2_5G)
1767                         speed |= TXGBE_LINK_SPEED_2_5GB_FULL;
1768                 if (*link_speeds & ETH_LINK_SPEED_1G)
1769                         speed |= TXGBE_LINK_SPEED_1GB_FULL;
1770                 if (*link_speeds & ETH_LINK_SPEED_100M)
1771                         speed |= TXGBE_LINK_SPEED_100M_FULL;
1772         }
1773
1774         err = hw->mac.setup_link(hw, speed, link_up);
1775         if (err)
1776                 goto error;
1777
1778 skip_link_setup:
1779
1780         if (rte_intr_allow_others(intr_handle)) {
1781                 txgbe_dev_misc_interrupt_setup(dev);
1782                 /* check if lsc interrupt is enabled */
1783                 if (dev->data->dev_conf.intr_conf.lsc != 0)
1784                         txgbe_dev_lsc_interrupt_setup(dev, TRUE);
1785                 else
1786                         txgbe_dev_lsc_interrupt_setup(dev, FALSE);
1787                 txgbe_dev_macsec_interrupt_setup(dev);
1788                 txgbe_set_ivar_map(hw, -1, 1, TXGBE_MISC_VEC_ID);
1789         } else {
1790                 rte_intr_callback_unregister(intr_handle,
1791                                              txgbe_dev_interrupt_handler, dev);
1792                 if (dev->data->dev_conf.intr_conf.lsc != 0)
1793                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
1794                                      " no intr multiplex");
1795         }
1796
1797         /* check if rxq interrupt is enabled */
1798         if (dev->data->dev_conf.intr_conf.rxq != 0 &&
1799             rte_intr_dp_is_en(intr_handle))
1800                 txgbe_dev_rxq_interrupt_setup(dev);
1801
1802         /* enable uio/vfio intr/eventfd mapping */
1803         rte_intr_enable(intr_handle);
1804
1805         /* resume enabled intr since hw reset */
1806         txgbe_enable_intr(dev);
1807         txgbe_l2_tunnel_conf(dev);
1808         txgbe_filter_restore(dev);
1809
1810         if (tm_conf->root && !tm_conf->committed)
1811                 PMD_DRV_LOG(WARNING,
1812                             "please call hierarchy_commit() "
1813                             "before starting the port");
1814
1815         /*
1816          * Update link status right before return, because it may
1817          * start link configuration process in a separate thread.
1818          */
1819         txgbe_dev_link_update(dev, 0);
1820
1821         wr32m(hw, TXGBE_LEDCTL, 0xFFFFFFFF, TXGBE_LEDCTL_ORD_MASK);
1822
1823         txgbe_read_stats_registers(hw, hw_stats);
1824         hw->offset_loaded = 1;
1825
1826         return 0;
1827
1828 error:
1829         PMD_INIT_LOG(ERR, "failure in dev start: %d", err);
1830         txgbe_dev_clear_queues(dev);
1831         return -EIO;
1832 }
1833
1834 /*
1835  * Stop device: disable rx and tx functions to allow for reconfiguring.
1836  */
1837 static int
1838 txgbe_dev_stop(struct rte_eth_dev *dev)
1839 {
1840         struct rte_eth_link link;
1841         struct txgbe_adapter *adapter = TXGBE_DEV_ADAPTER(dev);
1842         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
1843         struct txgbe_vf_info *vfinfo = *TXGBE_DEV_VFDATA(dev);
1844         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1845         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1846         int vf;
1847         struct txgbe_tm_conf *tm_conf = TXGBE_DEV_TM_CONF(dev);
1848
1849         if (hw->adapter_stopped)
1850                 return 0;
1851
1852         PMD_INIT_FUNC_TRACE();
1853
1854         rte_eal_alarm_cancel(txgbe_dev_setup_link_alarm_handler, dev);
1855
1856         /* disable interrupts */
1857         txgbe_disable_intr(hw);
1858
1859         /* reset the NIC */
1860         txgbe_pf_reset_hw(hw);
1861         hw->adapter_stopped = 0;
1862
1863         /* stop adapter */
1864         txgbe_stop_hw(hw);
1865
1866         for (vf = 0; vfinfo != NULL && vf < pci_dev->max_vfs; vf++)
1867                 vfinfo[vf].clear_to_send = false;
1868
1869         if (hw->phy.media_type == txgbe_media_type_copper) {
1870                 /* Turn off the copper */
1871                 hw->phy.set_phy_power(hw, false);
1872         } else {
1873                 /* Turn off the laser */
1874                 hw->mac.disable_tx_laser(hw);
1875         }
1876
1877         txgbe_dev_clear_queues(dev);
1878
1879         /* Clear stored conf */
1880         dev->data->scattered_rx = 0;
1881         dev->data->lro = 0;
1882
1883         /* Clear recorded link status */
1884         memset(&link, 0, sizeof(link));
1885         rte_eth_linkstatus_set(dev, &link);
1886
1887         if (!rte_intr_allow_others(intr_handle))
1888                 /* resume to the default handler */
1889                 rte_intr_callback_register(intr_handle,
1890                                            txgbe_dev_interrupt_handler,
1891                                            (void *)dev);
1892
1893         /* Clean datapath event and queue/vec mapping */
1894         rte_intr_efd_disable(intr_handle);
1895         if (intr_handle->intr_vec != NULL) {
1896                 rte_free(intr_handle->intr_vec);
1897                 intr_handle->intr_vec = NULL;
1898         }
1899
1900         /* reset hierarchy commit */
1901         tm_conf->committed = false;
1902
1903         adapter->rss_reta_updated = 0;
1904         wr32m(hw, TXGBE_LEDCTL, 0xFFFFFFFF, TXGBE_LEDCTL_SEL_MASK);
1905
1906         hw->adapter_stopped = true;
1907         dev->data->dev_started = 0;
1908
1909         return 0;
1910 }
1911
1912 /*
1913  * Set device link up: enable tx.
1914  */
1915 static int
1916 txgbe_dev_set_link_up(struct rte_eth_dev *dev)
1917 {
1918         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
1919
1920         if (hw->phy.media_type == txgbe_media_type_copper) {
1921                 /* Turn on the copper */
1922                 hw->phy.set_phy_power(hw, true);
1923         } else {
1924                 /* Turn on the laser */
1925                 hw->mac.enable_tx_laser(hw);
1926                 txgbe_dev_link_update(dev, 0);
1927         }
1928
1929         return 0;
1930 }
1931
1932 /*
1933  * Set device link down: disable tx.
1934  */
1935 static int
1936 txgbe_dev_set_link_down(struct rte_eth_dev *dev)
1937 {
1938         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
1939
1940         if (hw->phy.media_type == txgbe_media_type_copper) {
1941                 /* Turn off the copper */
1942                 hw->phy.set_phy_power(hw, false);
1943         } else {
1944                 /* Turn off the laser */
1945                 hw->mac.disable_tx_laser(hw);
1946                 txgbe_dev_link_update(dev, 0);
1947         }
1948
1949         return 0;
1950 }
1951
1952 /*
1953  * Reset and stop device.
1954  */
1955 static int
1956 txgbe_dev_close(struct rte_eth_dev *dev)
1957 {
1958         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
1959         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1960         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1961         int retries = 0;
1962         int ret;
1963
1964         PMD_INIT_FUNC_TRACE();
1965
1966         txgbe_pf_reset_hw(hw);
1967
1968         ret = txgbe_dev_stop(dev);
1969
1970         txgbe_dev_free_queues(dev);
1971
1972         /* reprogram the RAR[0] in case user changed it. */
1973         txgbe_set_rar(hw, 0, hw->mac.addr, 0, true);
1974
1975         /* Unlock any pending hardware semaphore */
1976         txgbe_swfw_lock_reset(hw);
1977
1978         /* disable uio intr before callback unregister */
1979         rte_intr_disable(intr_handle);
1980
1981         do {
1982                 ret = rte_intr_callback_unregister(intr_handle,
1983                                 txgbe_dev_interrupt_handler, dev);
1984                 if (ret >= 0 || ret == -ENOENT) {
1985                         break;
1986                 } else if (ret != -EAGAIN) {
1987                         PMD_INIT_LOG(ERR,
1988                                 "intr callback unregister failed: %d",
1989                                 ret);
1990                 }
1991                 rte_delay_ms(100);
1992         } while (retries++ < (10 + TXGBE_LINK_UP_TIME));
1993
1994         /* cancel the delay handler before remove dev */
1995         rte_eal_alarm_cancel(txgbe_dev_interrupt_delayed_handler, dev);
1996
1997         /* uninitialize PF if max_vfs not zero */
1998         txgbe_pf_host_uninit(dev);
1999
2000         rte_free(dev->data->mac_addrs);
2001         dev->data->mac_addrs = NULL;
2002
2003         rte_free(dev->data->hash_mac_addrs);
2004         dev->data->hash_mac_addrs = NULL;
2005
2006         /* remove all the fdir filters & hash */
2007         txgbe_fdir_filter_uninit(dev);
2008
2009         /* remove all the L2 tunnel filters & hash */
2010         txgbe_l2_tn_filter_uninit(dev);
2011
2012         /* Remove all ntuple filters of the device */
2013         txgbe_ntuple_filter_uninit(dev);
2014
2015         /* clear all the filters list */
2016         txgbe_filterlist_flush();
2017
2018         /* Remove all Traffic Manager configuration */
2019         txgbe_tm_conf_uninit(dev);
2020
2021 #ifdef RTE_LIB_SECURITY
2022         rte_free(dev->security_ctx);
2023 #endif
2024
2025         return ret;
2026 }
2027
2028 /*
2029  * Reset PF device.
2030  */
2031 static int
2032 txgbe_dev_reset(struct rte_eth_dev *dev)
2033 {
2034         int ret;
2035
2036         /* When a DPDK PMD PF begin to reset PF port, it should notify all
2037          * its VF to make them align with it. The detailed notification
2038          * mechanism is PMD specific. As to txgbe PF, it is rather complex.
2039          * To avoid unexpected behavior in VF, currently reset of PF with
2040          * SR-IOV activation is not supported. It might be supported later.
2041          */
2042         if (dev->data->sriov.active)
2043                 return -ENOTSUP;
2044
2045         ret = eth_txgbe_dev_uninit(dev);
2046         if (ret)
2047                 return ret;
2048
2049         ret = eth_txgbe_dev_init(dev, NULL);
2050
2051         return ret;
2052 }
2053
2054 #define UPDATE_QP_COUNTER_32bit(reg, last_counter, counter)     \
2055         {                                                       \
2056                 uint32_t current_counter = rd32(hw, reg);       \
2057                 if (current_counter < last_counter)             \
2058                         current_counter += 0x100000000LL;       \
2059                 if (!hw->offset_loaded)                         \
2060                         last_counter = current_counter;         \
2061                 counter = current_counter - last_counter;       \
2062                 counter &= 0xFFFFFFFFLL;                        \
2063         }
2064
2065 #define UPDATE_QP_COUNTER_36bit(reg_lsb, reg_msb, last_counter, counter) \
2066         {                                                                \
2067                 uint64_t current_counter_lsb = rd32(hw, reg_lsb);        \
2068                 uint64_t current_counter_msb = rd32(hw, reg_msb);        \
2069                 uint64_t current_counter = (current_counter_msb << 32) | \
2070                         current_counter_lsb;                             \
2071                 if (current_counter < last_counter)                      \
2072                         current_counter += 0x1000000000LL;               \
2073                 if (!hw->offset_loaded)                                  \
2074                         last_counter = current_counter;                  \
2075                 counter = current_counter - last_counter;                \
2076                 counter &= 0xFFFFFFFFFLL;                                \
2077         }
2078
2079 void
2080 txgbe_read_stats_registers(struct txgbe_hw *hw,
2081                            struct txgbe_hw_stats *hw_stats)
2082 {
2083         unsigned int i;
2084
2085         /* QP Stats */
2086         for (i = 0; i < hw->nb_rx_queues; i++) {
2087                 UPDATE_QP_COUNTER_32bit(TXGBE_QPRXPKT(i),
2088                         hw->qp_last[i].rx_qp_packets,
2089                         hw_stats->qp[i].rx_qp_packets);
2090                 UPDATE_QP_COUNTER_36bit(TXGBE_QPRXOCTL(i), TXGBE_QPRXOCTH(i),
2091                         hw->qp_last[i].rx_qp_bytes,
2092                         hw_stats->qp[i].rx_qp_bytes);
2093                 UPDATE_QP_COUNTER_32bit(TXGBE_QPRXMPKT(i),
2094                         hw->qp_last[i].rx_qp_mc_packets,
2095                         hw_stats->qp[i].rx_qp_mc_packets);
2096         }
2097
2098         for (i = 0; i < hw->nb_tx_queues; i++) {
2099                 UPDATE_QP_COUNTER_32bit(TXGBE_QPTXPKT(i),
2100                         hw->qp_last[i].tx_qp_packets,
2101                         hw_stats->qp[i].tx_qp_packets);
2102                 UPDATE_QP_COUNTER_36bit(TXGBE_QPTXOCTL(i), TXGBE_QPTXOCTH(i),
2103                         hw->qp_last[i].tx_qp_bytes,
2104                         hw_stats->qp[i].tx_qp_bytes);
2105         }
2106         /* PB Stats */
2107         for (i = 0; i < TXGBE_MAX_UP; i++) {
2108                 hw_stats->up[i].rx_up_xon_packets +=
2109                                 rd32(hw, TXGBE_PBRXUPXON(i));
2110                 hw_stats->up[i].rx_up_xoff_packets +=
2111                                 rd32(hw, TXGBE_PBRXUPXOFF(i));
2112                 hw_stats->up[i].tx_up_xon_packets +=
2113                                 rd32(hw, TXGBE_PBTXUPXON(i));
2114                 hw_stats->up[i].tx_up_xoff_packets +=
2115                                 rd32(hw, TXGBE_PBTXUPXOFF(i));
2116                 hw_stats->up[i].tx_up_xon2off_packets +=
2117                                 rd32(hw, TXGBE_PBTXUPOFF(i));
2118                 hw_stats->up[i].rx_up_dropped +=
2119                                 rd32(hw, TXGBE_PBRXMISS(i));
2120         }
2121         hw_stats->rx_xon_packets += rd32(hw, TXGBE_PBRXLNKXON);
2122         hw_stats->rx_xoff_packets += rd32(hw, TXGBE_PBRXLNKXOFF);
2123         hw_stats->tx_xon_packets += rd32(hw, TXGBE_PBTXLNKXON);
2124         hw_stats->tx_xoff_packets += rd32(hw, TXGBE_PBTXLNKXOFF);
2125
2126         /* DMA Stats */
2127         hw_stats->rx_packets += rd32(hw, TXGBE_DMARXPKT);
2128         hw_stats->tx_packets += rd32(hw, TXGBE_DMATXPKT);
2129
2130         hw_stats->rx_bytes += rd64(hw, TXGBE_DMARXOCTL);
2131         hw_stats->tx_bytes += rd64(hw, TXGBE_DMATXOCTL);
2132         hw_stats->rx_dma_drop += rd32(hw, TXGBE_DMARXDROP);
2133         hw_stats->rx_drop_packets += rd32(hw, TXGBE_PBRXDROP);
2134
2135         /* MAC Stats */
2136         hw_stats->rx_crc_errors += rd64(hw, TXGBE_MACRXERRCRCL);
2137         hw_stats->rx_multicast_packets += rd64(hw, TXGBE_MACRXMPKTL);
2138         hw_stats->tx_multicast_packets += rd64(hw, TXGBE_MACTXMPKTL);
2139
2140         hw_stats->rx_total_packets += rd64(hw, TXGBE_MACRXPKTL);
2141         hw_stats->tx_total_packets += rd64(hw, TXGBE_MACTXPKTL);
2142         hw_stats->rx_total_bytes += rd64(hw, TXGBE_MACRXGBOCTL);
2143
2144         hw_stats->rx_broadcast_packets += rd64(hw, TXGBE_MACRXOCTL);
2145         hw_stats->tx_broadcast_packets += rd32(hw, TXGBE_MACTXOCTL);
2146
2147         hw_stats->rx_size_64_packets += rd64(hw, TXGBE_MACRX1TO64L);
2148         hw_stats->rx_size_65_to_127_packets += rd64(hw, TXGBE_MACRX65TO127L);
2149         hw_stats->rx_size_128_to_255_packets += rd64(hw, TXGBE_MACRX128TO255L);
2150         hw_stats->rx_size_256_to_511_packets += rd64(hw, TXGBE_MACRX256TO511L);
2151         hw_stats->rx_size_512_to_1023_packets +=
2152                         rd64(hw, TXGBE_MACRX512TO1023L);
2153         hw_stats->rx_size_1024_to_max_packets +=
2154                         rd64(hw, TXGBE_MACRX1024TOMAXL);
2155         hw_stats->tx_size_64_packets += rd64(hw, TXGBE_MACTX1TO64L);
2156         hw_stats->tx_size_65_to_127_packets += rd64(hw, TXGBE_MACTX65TO127L);
2157         hw_stats->tx_size_128_to_255_packets += rd64(hw, TXGBE_MACTX128TO255L);
2158         hw_stats->tx_size_256_to_511_packets += rd64(hw, TXGBE_MACTX256TO511L);
2159         hw_stats->tx_size_512_to_1023_packets +=
2160                         rd64(hw, TXGBE_MACTX512TO1023L);
2161         hw_stats->tx_size_1024_to_max_packets +=
2162                         rd64(hw, TXGBE_MACTX1024TOMAXL);
2163
2164         hw_stats->rx_undersize_errors += rd64(hw, TXGBE_MACRXERRLENL);
2165         hw_stats->rx_oversize_errors += rd32(hw, TXGBE_MACRXOVERSIZE);
2166         hw_stats->rx_jabber_errors += rd32(hw, TXGBE_MACRXJABBER);
2167
2168         /* MNG Stats */
2169         hw_stats->mng_bmc2host_packets = rd32(hw, TXGBE_MNGBMC2OS);
2170         hw_stats->mng_host2bmc_packets = rd32(hw, TXGBE_MNGOS2BMC);
2171         hw_stats->rx_management_packets = rd32(hw, TXGBE_DMARXMNG);
2172         hw_stats->tx_management_packets = rd32(hw, TXGBE_DMATXMNG);
2173
2174         /* FCoE Stats */
2175         hw_stats->rx_fcoe_crc_errors += rd32(hw, TXGBE_FCOECRC);
2176         hw_stats->rx_fcoe_mbuf_allocation_errors += rd32(hw, TXGBE_FCOELAST);
2177         hw_stats->rx_fcoe_dropped += rd32(hw, TXGBE_FCOERPDC);
2178         hw_stats->rx_fcoe_packets += rd32(hw, TXGBE_FCOEPRC);
2179         hw_stats->tx_fcoe_packets += rd32(hw, TXGBE_FCOEPTC);
2180         hw_stats->rx_fcoe_bytes += rd32(hw, TXGBE_FCOEDWRC);
2181         hw_stats->tx_fcoe_bytes += rd32(hw, TXGBE_FCOEDWTC);
2182
2183         /* Flow Director Stats */
2184         hw_stats->flow_director_matched_filters += rd32(hw, TXGBE_FDIRMATCH);
2185         hw_stats->flow_director_missed_filters += rd32(hw, TXGBE_FDIRMISS);
2186         hw_stats->flow_director_added_filters +=
2187                 TXGBE_FDIRUSED_ADD(rd32(hw, TXGBE_FDIRUSED));
2188         hw_stats->flow_director_removed_filters +=
2189                 TXGBE_FDIRUSED_REM(rd32(hw, TXGBE_FDIRUSED));
2190         hw_stats->flow_director_filter_add_errors +=
2191                 TXGBE_FDIRFAIL_ADD(rd32(hw, TXGBE_FDIRFAIL));
2192         hw_stats->flow_director_filter_remove_errors +=
2193                 TXGBE_FDIRFAIL_REM(rd32(hw, TXGBE_FDIRFAIL));
2194
2195         /* MACsec Stats */
2196         hw_stats->tx_macsec_pkts_untagged += rd32(hw, TXGBE_LSECTX_UTPKT);
2197         hw_stats->tx_macsec_pkts_encrypted +=
2198                         rd32(hw, TXGBE_LSECTX_ENCPKT);
2199         hw_stats->tx_macsec_pkts_protected +=
2200                         rd32(hw, TXGBE_LSECTX_PROTPKT);
2201         hw_stats->tx_macsec_octets_encrypted +=
2202                         rd32(hw, TXGBE_LSECTX_ENCOCT);
2203         hw_stats->tx_macsec_octets_protected +=
2204                         rd32(hw, TXGBE_LSECTX_PROTOCT);
2205         hw_stats->rx_macsec_pkts_untagged += rd32(hw, TXGBE_LSECRX_UTPKT);
2206         hw_stats->rx_macsec_pkts_badtag += rd32(hw, TXGBE_LSECRX_BTPKT);
2207         hw_stats->rx_macsec_pkts_nosci += rd32(hw, TXGBE_LSECRX_NOSCIPKT);
2208         hw_stats->rx_macsec_pkts_unknownsci += rd32(hw, TXGBE_LSECRX_UNSCIPKT);
2209         hw_stats->rx_macsec_octets_decrypted += rd32(hw, TXGBE_LSECRX_DECOCT);
2210         hw_stats->rx_macsec_octets_validated += rd32(hw, TXGBE_LSECRX_VLDOCT);
2211         hw_stats->rx_macsec_sc_pkts_unchecked +=
2212                         rd32(hw, TXGBE_LSECRX_UNCHKPKT);
2213         hw_stats->rx_macsec_sc_pkts_delayed += rd32(hw, TXGBE_LSECRX_DLYPKT);
2214         hw_stats->rx_macsec_sc_pkts_late += rd32(hw, TXGBE_LSECRX_LATEPKT);
2215         for (i = 0; i < 2; i++) {
2216                 hw_stats->rx_macsec_sa_pkts_ok +=
2217                         rd32(hw, TXGBE_LSECRX_OKPKT(i));
2218                 hw_stats->rx_macsec_sa_pkts_invalid +=
2219                         rd32(hw, TXGBE_LSECRX_INVPKT(i));
2220                 hw_stats->rx_macsec_sa_pkts_notvalid +=
2221                         rd32(hw, TXGBE_LSECRX_BADPKT(i));
2222         }
2223         hw_stats->rx_macsec_sa_pkts_unusedsa +=
2224                         rd32(hw, TXGBE_LSECRX_INVSAPKT);
2225         hw_stats->rx_macsec_sa_pkts_notusingsa +=
2226                         rd32(hw, TXGBE_LSECRX_BADSAPKT);
2227
2228         hw_stats->rx_total_missed_packets = 0;
2229         for (i = 0; i < TXGBE_MAX_UP; i++) {
2230                 hw_stats->rx_total_missed_packets +=
2231                         hw_stats->up[i].rx_up_dropped;
2232         }
2233 }
2234
2235 static int
2236 txgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2237 {
2238         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2239         struct txgbe_hw_stats *hw_stats = TXGBE_DEV_STATS(dev);
2240         struct txgbe_stat_mappings *stat_mappings =
2241                         TXGBE_DEV_STAT_MAPPINGS(dev);
2242         uint32_t i, j;
2243
2244         txgbe_read_stats_registers(hw, hw_stats);
2245
2246         if (stats == NULL)
2247                 return -EINVAL;
2248
2249         /* Fill out the rte_eth_stats statistics structure */
2250         stats->ipackets = hw_stats->rx_packets;
2251         stats->ibytes = hw_stats->rx_bytes;
2252         stats->opackets = hw_stats->tx_packets;
2253         stats->obytes = hw_stats->tx_bytes;
2254
2255         memset(&stats->q_ipackets, 0, sizeof(stats->q_ipackets));
2256         memset(&stats->q_opackets, 0, sizeof(stats->q_opackets));
2257         memset(&stats->q_ibytes, 0, sizeof(stats->q_ibytes));
2258         memset(&stats->q_obytes, 0, sizeof(stats->q_obytes));
2259         memset(&stats->q_errors, 0, sizeof(stats->q_errors));
2260         for (i = 0; i < TXGBE_MAX_QP; i++) {
2261                 uint32_t n = i / NB_QMAP_FIELDS_PER_QSM_REG;
2262                 uint32_t offset = (i % NB_QMAP_FIELDS_PER_QSM_REG) * 8;
2263                 uint32_t q_map;
2264
2265                 q_map = (stat_mappings->rqsm[n] >> offset)
2266                                 & QMAP_FIELD_RESERVED_BITS_MASK;
2267                 j = (q_map < RTE_ETHDEV_QUEUE_STAT_CNTRS
2268                      ? q_map : q_map % RTE_ETHDEV_QUEUE_STAT_CNTRS);
2269                 stats->q_ipackets[j] += hw_stats->qp[i].rx_qp_packets;
2270                 stats->q_ibytes[j] += hw_stats->qp[i].rx_qp_bytes;
2271
2272                 q_map = (stat_mappings->tqsm[n] >> offset)
2273                                 & QMAP_FIELD_RESERVED_BITS_MASK;
2274                 j = (q_map < RTE_ETHDEV_QUEUE_STAT_CNTRS
2275                      ? q_map : q_map % RTE_ETHDEV_QUEUE_STAT_CNTRS);
2276                 stats->q_opackets[j] += hw_stats->qp[i].tx_qp_packets;
2277                 stats->q_obytes[j] += hw_stats->qp[i].tx_qp_bytes;
2278         }
2279
2280         /* Rx Errors */
2281         stats->imissed  = hw_stats->rx_total_missed_packets +
2282                           hw_stats->rx_dma_drop;
2283         stats->ierrors  = hw_stats->rx_crc_errors +
2284                           hw_stats->rx_mac_short_packet_dropped +
2285                           hw_stats->rx_length_errors +
2286                           hw_stats->rx_undersize_errors +
2287                           hw_stats->rx_oversize_errors +
2288                           hw_stats->rx_drop_packets +
2289                           hw_stats->rx_illegal_byte_errors +
2290                           hw_stats->rx_error_bytes +
2291                           hw_stats->rx_fragment_errors +
2292                           hw_stats->rx_fcoe_crc_errors +
2293                           hw_stats->rx_fcoe_mbuf_allocation_errors;
2294
2295         /* Tx Errors */
2296         stats->oerrors  = 0;
2297         return 0;
2298 }
2299
2300 static int
2301 txgbe_dev_stats_reset(struct rte_eth_dev *dev)
2302 {
2303         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2304         struct txgbe_hw_stats *hw_stats = TXGBE_DEV_STATS(dev);
2305
2306         /* HW registers are cleared on read */
2307         hw->offset_loaded = 0;
2308         txgbe_dev_stats_get(dev, NULL);
2309         hw->offset_loaded = 1;
2310
2311         /* Reset software totals */
2312         memset(hw_stats, 0, sizeof(*hw_stats));
2313
2314         return 0;
2315 }
2316
2317 /* This function calculates the number of xstats based on the current config */
2318 static unsigned
2319 txgbe_xstats_calc_num(struct rte_eth_dev *dev)
2320 {
2321         int nb_queues = max(dev->data->nb_rx_queues, dev->data->nb_tx_queues);
2322         return TXGBE_NB_HW_STATS +
2323                TXGBE_NB_UP_STATS * TXGBE_MAX_UP +
2324                TXGBE_NB_QP_STATS * nb_queues;
2325 }
2326
2327 static inline int
2328 txgbe_get_name_by_id(uint32_t id, char *name, uint32_t size)
2329 {
2330         int nb, st;
2331
2332         /* Extended stats from txgbe_hw_stats */
2333         if (id < TXGBE_NB_HW_STATS) {
2334                 snprintf(name, size, "[hw]%s",
2335                         rte_txgbe_stats_strings[id].name);
2336                 return 0;
2337         }
2338         id -= TXGBE_NB_HW_STATS;
2339
2340         /* Priority Stats */
2341         if (id < TXGBE_NB_UP_STATS * TXGBE_MAX_UP) {
2342                 nb = id / TXGBE_NB_UP_STATS;
2343                 st = id % TXGBE_NB_UP_STATS;
2344                 snprintf(name, size, "[p%u]%s", nb,
2345                         rte_txgbe_up_strings[st].name);
2346                 return 0;
2347         }
2348         id -= TXGBE_NB_UP_STATS * TXGBE_MAX_UP;
2349
2350         /* Queue Stats */
2351         if (id < TXGBE_NB_QP_STATS * TXGBE_MAX_QP) {
2352                 nb = id / TXGBE_NB_QP_STATS;
2353                 st = id % TXGBE_NB_QP_STATS;
2354                 snprintf(name, size, "[q%u]%s", nb,
2355                         rte_txgbe_qp_strings[st].name);
2356                 return 0;
2357         }
2358         id -= TXGBE_NB_QP_STATS * TXGBE_MAX_QP;
2359
2360         return -(int)(id + 1);
2361 }
2362
2363 static inline int
2364 txgbe_get_offset_by_id(uint32_t id, uint32_t *offset)
2365 {
2366         int nb, st;
2367
2368         /* Extended stats from txgbe_hw_stats */
2369         if (id < TXGBE_NB_HW_STATS) {
2370                 *offset = rte_txgbe_stats_strings[id].offset;
2371                 return 0;
2372         }
2373         id -= TXGBE_NB_HW_STATS;
2374
2375         /* Priority Stats */
2376         if (id < TXGBE_NB_UP_STATS * TXGBE_MAX_UP) {
2377                 nb = id / TXGBE_NB_UP_STATS;
2378                 st = id % TXGBE_NB_UP_STATS;
2379                 *offset = rte_txgbe_up_strings[st].offset +
2380                         nb * (TXGBE_NB_UP_STATS * sizeof(uint64_t));
2381                 return 0;
2382         }
2383         id -= TXGBE_NB_UP_STATS * TXGBE_MAX_UP;
2384
2385         /* Queue Stats */
2386         if (id < TXGBE_NB_QP_STATS * TXGBE_MAX_QP) {
2387                 nb = id / TXGBE_NB_QP_STATS;
2388                 st = id % TXGBE_NB_QP_STATS;
2389                 *offset = rte_txgbe_qp_strings[st].offset +
2390                         nb * (TXGBE_NB_QP_STATS * sizeof(uint64_t));
2391                 return 0;
2392         }
2393
2394         return -1;
2395 }
2396
2397 static int txgbe_dev_xstats_get_names(struct rte_eth_dev *dev,
2398         struct rte_eth_xstat_name *xstats_names, unsigned int limit)
2399 {
2400         unsigned int i, count;
2401
2402         count = txgbe_xstats_calc_num(dev);
2403         if (xstats_names == NULL)
2404                 return count;
2405
2406         /* Note: limit >= cnt_stats checked upstream
2407          * in rte_eth_xstats_names()
2408          */
2409         limit = min(limit, count);
2410
2411         /* Extended stats from txgbe_hw_stats */
2412         for (i = 0; i < limit; i++) {
2413                 if (txgbe_get_name_by_id(i, xstats_names[i].name,
2414                         sizeof(xstats_names[i].name))) {
2415                         PMD_INIT_LOG(WARNING, "id value %d isn't valid", i);
2416                         break;
2417                 }
2418         }
2419
2420         return i;
2421 }
2422
2423 static int txgbe_dev_xstats_get_names_by_id(struct rte_eth_dev *dev,
2424         struct rte_eth_xstat_name *xstats_names,
2425         const uint64_t *ids,
2426         unsigned int limit)
2427 {
2428         unsigned int i;
2429
2430         if (ids == NULL)
2431                 return txgbe_dev_xstats_get_names(dev, xstats_names, limit);
2432
2433         for (i = 0; i < limit; i++) {
2434                 if (txgbe_get_name_by_id(ids[i], xstats_names[i].name,
2435                                 sizeof(xstats_names[i].name))) {
2436                         PMD_INIT_LOG(WARNING, "id value %d isn't valid", i);
2437                         return -1;
2438                 }
2439         }
2440
2441         return i;
2442 }
2443
2444 static int
2445 txgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2446                                          unsigned int limit)
2447 {
2448         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2449         struct txgbe_hw_stats *hw_stats = TXGBE_DEV_STATS(dev);
2450         unsigned int i, count;
2451
2452         txgbe_read_stats_registers(hw, hw_stats);
2453
2454         /* If this is a reset xstats is NULL, and we have cleared the
2455          * registers by reading them.
2456          */
2457         count = txgbe_xstats_calc_num(dev);
2458         if (xstats == NULL)
2459                 return count;
2460
2461         limit = min(limit, txgbe_xstats_calc_num(dev));
2462
2463         /* Extended stats from txgbe_hw_stats */
2464         for (i = 0; i < limit; i++) {
2465                 uint32_t offset = 0;
2466
2467                 if (txgbe_get_offset_by_id(i, &offset)) {
2468                         PMD_INIT_LOG(WARNING, "id value %d isn't valid", i);
2469                         break;
2470                 }
2471                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) + offset);
2472                 xstats[i].id = i;
2473         }
2474
2475         return i;
2476 }
2477
2478 static int
2479 txgbe_dev_xstats_get_(struct rte_eth_dev *dev, uint64_t *values,
2480                                          unsigned int limit)
2481 {
2482         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2483         struct txgbe_hw_stats *hw_stats = TXGBE_DEV_STATS(dev);
2484         unsigned int i, count;
2485
2486         txgbe_read_stats_registers(hw, hw_stats);
2487
2488         /* If this is a reset xstats is NULL, and we have cleared the
2489          * registers by reading them.
2490          */
2491         count = txgbe_xstats_calc_num(dev);
2492         if (values == NULL)
2493                 return count;
2494
2495         limit = min(limit, txgbe_xstats_calc_num(dev));
2496
2497         /* Extended stats from txgbe_hw_stats */
2498         for (i = 0; i < limit; i++) {
2499                 uint32_t offset;
2500
2501                 if (txgbe_get_offset_by_id(i, &offset)) {
2502                         PMD_INIT_LOG(WARNING, "id value %d isn't valid", i);
2503                         break;
2504                 }
2505                 values[i] = *(uint64_t *)(((char *)hw_stats) + offset);
2506         }
2507
2508         return i;
2509 }
2510
2511 static int
2512 txgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
2513                 uint64_t *values, unsigned int limit)
2514 {
2515         struct txgbe_hw_stats *hw_stats = TXGBE_DEV_STATS(dev);
2516         unsigned int i;
2517
2518         if (ids == NULL)
2519                 return txgbe_dev_xstats_get_(dev, values, limit);
2520
2521         for (i = 0; i < limit; i++) {
2522                 uint32_t offset;
2523
2524                 if (txgbe_get_offset_by_id(ids[i], &offset)) {
2525                         PMD_INIT_LOG(WARNING, "id value %d isn't valid", i);
2526                         break;
2527                 }
2528                 values[i] = *(uint64_t *)(((char *)hw_stats) + offset);
2529         }
2530
2531         return i;
2532 }
2533
2534 static int
2535 txgbe_dev_xstats_reset(struct rte_eth_dev *dev)
2536 {
2537         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2538         struct txgbe_hw_stats *hw_stats = TXGBE_DEV_STATS(dev);
2539
2540         /* HW registers are cleared on read */
2541         hw->offset_loaded = 0;
2542         txgbe_read_stats_registers(hw, hw_stats);
2543         hw->offset_loaded = 1;
2544
2545         /* Reset software totals */
2546         memset(hw_stats, 0, sizeof(*hw_stats));
2547
2548         return 0;
2549 }
2550
2551 static int
2552 txgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
2553 {
2554         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2555         u32 etrack_id;
2556         int ret;
2557
2558         hw->phy.get_fw_version(hw, &etrack_id);
2559
2560         ret = snprintf(fw_version, fw_size, "0x%08x", etrack_id);
2561         if (ret < 0)
2562                 return -EINVAL;
2563
2564         ret += 1; /* add the size of '\0' */
2565         if (fw_size < (size_t)ret)
2566                 return ret;
2567         else
2568                 return 0;
2569 }
2570
2571 static int
2572 txgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2573 {
2574         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2575         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2576
2577         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
2578         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
2579         dev_info->min_rx_bufsize = 1024;
2580         dev_info->max_rx_pktlen = 15872;
2581         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
2582         dev_info->max_hash_mac_addrs = TXGBE_VMDQ_NUM_UC_MAC;
2583         dev_info->max_vfs = pci_dev->max_vfs;
2584         dev_info->max_vmdq_pools = ETH_64_POOLS;
2585         dev_info->vmdq_queue_num = dev_info->max_rx_queues;
2586         dev_info->rx_queue_offload_capa = txgbe_get_rx_queue_offloads(dev);
2587         dev_info->rx_offload_capa = (txgbe_get_rx_port_offloads(dev) |
2588                                      dev_info->rx_queue_offload_capa);
2589         dev_info->tx_queue_offload_capa = txgbe_get_tx_queue_offloads(dev);
2590         dev_info->tx_offload_capa = txgbe_get_tx_port_offloads(dev);
2591
2592         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2593                 .rx_thresh = {
2594                         .pthresh = TXGBE_DEFAULT_RX_PTHRESH,
2595                         .hthresh = TXGBE_DEFAULT_RX_HTHRESH,
2596                         .wthresh = TXGBE_DEFAULT_RX_WTHRESH,
2597                 },
2598                 .rx_free_thresh = TXGBE_DEFAULT_RX_FREE_THRESH,
2599                 .rx_drop_en = 0,
2600                 .offloads = 0,
2601         };
2602
2603         dev_info->default_txconf = (struct rte_eth_txconf) {
2604                 .tx_thresh = {
2605                         .pthresh = TXGBE_DEFAULT_TX_PTHRESH,
2606                         .hthresh = TXGBE_DEFAULT_TX_HTHRESH,
2607                         .wthresh = TXGBE_DEFAULT_TX_WTHRESH,
2608                 },
2609                 .tx_free_thresh = TXGBE_DEFAULT_TX_FREE_THRESH,
2610                 .offloads = 0,
2611         };
2612
2613         dev_info->rx_desc_lim = rx_desc_lim;
2614         dev_info->tx_desc_lim = tx_desc_lim;
2615
2616         dev_info->hash_key_size = TXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
2617         dev_info->reta_size = ETH_RSS_RETA_SIZE_128;
2618         dev_info->flow_type_rss_offloads = TXGBE_RSS_OFFLOAD_ALL;
2619
2620         dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
2621         dev_info->speed_capa |= ETH_LINK_SPEED_100M;
2622
2623         /* Driver-preferred Rx/Tx parameters */
2624         dev_info->default_rxportconf.burst_size = 32;
2625         dev_info->default_txportconf.burst_size = 32;
2626         dev_info->default_rxportconf.nb_queues = 1;
2627         dev_info->default_txportconf.nb_queues = 1;
2628         dev_info->default_rxportconf.ring_size = 256;
2629         dev_info->default_txportconf.ring_size = 256;
2630
2631         return 0;
2632 }
2633
2634 const uint32_t *
2635 txgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev)
2636 {
2637         if (dev->rx_pkt_burst == txgbe_recv_pkts ||
2638             dev->rx_pkt_burst == txgbe_recv_pkts_lro_single_alloc ||
2639             dev->rx_pkt_burst == txgbe_recv_pkts_lro_bulk_alloc ||
2640             dev->rx_pkt_burst == txgbe_recv_pkts_bulk_alloc)
2641                 return txgbe_get_supported_ptypes();
2642
2643         return NULL;
2644 }
2645
2646 void
2647 txgbe_dev_setup_link_alarm_handler(void *param)
2648 {
2649         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2650         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2651         struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);
2652         u32 speed;
2653         bool autoneg = false;
2654
2655         speed = hw->phy.autoneg_advertised;
2656         if (!speed)
2657                 hw->mac.get_link_capabilities(hw, &speed, &autoneg);
2658
2659         hw->mac.setup_link(hw, speed, true);
2660
2661         intr->flags &= ~TXGBE_FLAG_NEED_LINK_CONFIG;
2662 }
2663
2664 /* return 0 means link status changed, -1 means not changed */
2665 int
2666 txgbe_dev_link_update_share(struct rte_eth_dev *dev,
2667                             int wait_to_complete)
2668 {
2669         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2670         struct rte_eth_link link;
2671         u32 link_speed = TXGBE_LINK_SPEED_UNKNOWN;
2672         struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);
2673         bool link_up;
2674         int err;
2675         int wait = 1;
2676
2677         memset(&link, 0, sizeof(link));
2678         link.link_status = ETH_LINK_DOWN;
2679         link.link_speed = ETH_SPEED_NUM_NONE;
2680         link.link_duplex = ETH_LINK_HALF_DUPLEX;
2681         link.link_autoneg = ETH_LINK_AUTONEG;
2682
2683         hw->mac.get_link_status = true;
2684
2685         if (intr->flags & TXGBE_FLAG_NEED_LINK_CONFIG)
2686                 return rte_eth_linkstatus_set(dev, &link);
2687
2688         /* check if it needs to wait to complete, if lsc interrupt is enabled */
2689         if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
2690                 wait = 0;
2691
2692         err = hw->mac.check_link(hw, &link_speed, &link_up, wait);
2693
2694         if (err != 0) {
2695                 link.link_speed = ETH_SPEED_NUM_100M;
2696                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
2697                 return rte_eth_linkstatus_set(dev, &link);
2698         }
2699
2700         if (link_up == 0) {
2701                 if ((hw->subsystem_device_id & 0xFF) ==
2702                                 TXGBE_DEV_ID_KR_KX_KX4) {
2703                         hw->mac.bp_down_event(hw);
2704                 } else if (hw->phy.media_type == txgbe_media_type_fiber) {
2705                         intr->flags |= TXGBE_FLAG_NEED_LINK_CONFIG;
2706                         rte_eal_alarm_set(10,
2707                                 txgbe_dev_setup_link_alarm_handler, dev);
2708                 }
2709                 return rte_eth_linkstatus_set(dev, &link);
2710         }
2711
2712         intr->flags &= ~TXGBE_FLAG_NEED_LINK_CONFIG;
2713         link.link_status = ETH_LINK_UP;
2714         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2715
2716         switch (link_speed) {
2717         default:
2718         case TXGBE_LINK_SPEED_UNKNOWN:
2719                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
2720                 link.link_speed = ETH_SPEED_NUM_100M;
2721                 break;
2722
2723         case TXGBE_LINK_SPEED_100M_FULL:
2724                 link.link_speed = ETH_SPEED_NUM_100M;
2725                 break;
2726
2727         case TXGBE_LINK_SPEED_1GB_FULL:
2728                 link.link_speed = ETH_SPEED_NUM_1G;
2729                 break;
2730
2731         case TXGBE_LINK_SPEED_2_5GB_FULL:
2732                 link.link_speed = ETH_SPEED_NUM_2_5G;
2733                 break;
2734
2735         case TXGBE_LINK_SPEED_5GB_FULL:
2736                 link.link_speed = ETH_SPEED_NUM_5G;
2737                 break;
2738
2739         case TXGBE_LINK_SPEED_10GB_FULL:
2740                 link.link_speed = ETH_SPEED_NUM_10G;
2741                 break;
2742         }
2743
2744         return rte_eth_linkstatus_set(dev, &link);
2745 }
2746
2747 static int
2748 txgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
2749 {
2750         return txgbe_dev_link_update_share(dev, wait_to_complete);
2751 }
2752
2753 static int
2754 txgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
2755 {
2756         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2757         uint32_t fctrl;
2758
2759         fctrl = rd32(hw, TXGBE_PSRCTL);
2760         fctrl |= (TXGBE_PSRCTL_UCP | TXGBE_PSRCTL_MCP);
2761         wr32(hw, TXGBE_PSRCTL, fctrl);
2762
2763         return 0;
2764 }
2765
2766 static int
2767 txgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
2768 {
2769         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2770         uint32_t fctrl;
2771
2772         fctrl = rd32(hw, TXGBE_PSRCTL);
2773         fctrl &= (~TXGBE_PSRCTL_UCP);
2774         if (dev->data->all_multicast == 1)
2775                 fctrl |= TXGBE_PSRCTL_MCP;
2776         else
2777                 fctrl &= (~TXGBE_PSRCTL_MCP);
2778         wr32(hw, TXGBE_PSRCTL, fctrl);
2779
2780         return 0;
2781 }
2782
2783 static int
2784 txgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
2785 {
2786         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2787         uint32_t fctrl;
2788
2789         fctrl = rd32(hw, TXGBE_PSRCTL);
2790         fctrl |= TXGBE_PSRCTL_MCP;
2791         wr32(hw, TXGBE_PSRCTL, fctrl);
2792
2793         return 0;
2794 }
2795
2796 static int
2797 txgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
2798 {
2799         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2800         uint32_t fctrl;
2801
2802         if (dev->data->promiscuous == 1)
2803                 return 0; /* must remain in all_multicast mode */
2804
2805         fctrl = rd32(hw, TXGBE_PSRCTL);
2806         fctrl &= (~TXGBE_PSRCTL_MCP);
2807         wr32(hw, TXGBE_PSRCTL, fctrl);
2808
2809         return 0;
2810 }
2811
2812 /**
2813  * It clears the interrupt causes and enables the interrupt.
2814  * It will be called once only during nic initialized.
2815  *
2816  * @param dev
2817  *  Pointer to struct rte_eth_dev.
2818  * @param on
2819  *  Enable or Disable.
2820  *
2821  * @return
2822  *  - On success, zero.
2823  *  - On failure, a negative value.
2824  */
2825 static int
2826 txgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on)
2827 {
2828         struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);
2829
2830         txgbe_dev_link_status_print(dev);
2831         if (on)
2832                 intr->mask_misc |= TXGBE_ICRMISC_LSC;
2833         else
2834                 intr->mask_misc &= ~TXGBE_ICRMISC_LSC;
2835
2836         return 0;
2837 }
2838
2839 static int
2840 txgbe_dev_misc_interrupt_setup(struct rte_eth_dev *dev)
2841 {
2842         struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);
2843         u64 mask;
2844
2845         mask = TXGBE_ICR_MASK;
2846         mask &= (1ULL << TXGBE_MISC_VEC_ID);
2847         intr->mask |= mask;
2848         intr->mask_misc |= TXGBE_ICRMISC_GPIO;
2849         intr->mask_misc |= TXGBE_ICRMISC_ANDONE;
2850         return 0;
2851 }
2852
2853 /**
2854  * It clears the interrupt causes and enables the interrupt.
2855  * It will be called once only during nic initialized.
2856  *
2857  * @param dev
2858  *  Pointer to struct rte_eth_dev.
2859  *
2860  * @return
2861  *  - On success, zero.
2862  *  - On failure, a negative value.
2863  */
2864 static int
2865 txgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
2866 {
2867         struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);
2868         u64 mask;
2869
2870         mask = TXGBE_ICR_MASK;
2871         mask &= ~((1ULL << TXGBE_RX_VEC_START) - 1);
2872         intr->mask |= mask;
2873
2874         return 0;
2875 }
2876
2877 /**
2878  * It clears the interrupt causes and enables the interrupt.
2879  * It will be called once only during nic initialized.
2880  *
2881  * @param dev
2882  *  Pointer to struct rte_eth_dev.
2883  *
2884  * @return
2885  *  - On success, zero.
2886  *  - On failure, a negative value.
2887  */
2888 static int
2889 txgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev)
2890 {
2891         struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);
2892
2893         intr->mask_misc |= TXGBE_ICRMISC_LNKSEC;
2894
2895         return 0;
2896 }
2897
2898 /*
2899  * It reads ICR and sets flag (TXGBE_ICRMISC_LSC) for the link_update.
2900  *
2901  * @param dev
2902  *  Pointer to struct rte_eth_dev.
2903  *
2904  * @return
2905  *  - On success, zero.
2906  *  - On failure, a negative value.
2907  */
2908 static int
2909 txgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
2910 {
2911         uint32_t eicr;
2912         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2913         struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);
2914
2915         /* clear all cause mask */
2916         txgbe_disable_intr(hw);
2917
2918         /* read-on-clear nic registers here */
2919         eicr = ((u32 *)hw->isb_mem)[TXGBE_ISB_MISC];
2920         PMD_DRV_LOG(DEBUG, "eicr %x", eicr);
2921
2922         intr->flags = 0;
2923
2924         /* set flag for async link update */
2925         if (eicr & TXGBE_ICRMISC_LSC)
2926                 intr->flags |= TXGBE_FLAG_NEED_LINK_UPDATE;
2927
2928         if (eicr & TXGBE_ICRMISC_ANDONE)
2929                 intr->flags |= TXGBE_FLAG_NEED_AN_CONFIG;
2930
2931         if (eicr & TXGBE_ICRMISC_VFMBX)
2932                 intr->flags |= TXGBE_FLAG_MAILBOX;
2933
2934         if (eicr & TXGBE_ICRMISC_LNKSEC)
2935                 intr->flags |= TXGBE_FLAG_MACSEC;
2936
2937         if (eicr & TXGBE_ICRMISC_GPIO)
2938                 intr->flags |= TXGBE_FLAG_PHY_INTERRUPT;
2939
2940         return 0;
2941 }
2942
2943 /**
2944  * It gets and then prints the link status.
2945  *
2946  * @param dev
2947  *  Pointer to struct rte_eth_dev.
2948  *
2949  * @return
2950  *  - On success, zero.
2951  *  - On failure, a negative value.
2952  */
2953 static void
2954 txgbe_dev_link_status_print(struct rte_eth_dev *dev)
2955 {
2956         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2957         struct rte_eth_link link;
2958
2959         rte_eth_linkstatus_get(dev, &link);
2960
2961         if (link.link_status) {
2962                 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
2963                                         (int)(dev->data->port_id),
2964                                         (unsigned int)link.link_speed,
2965                         link.link_duplex == ETH_LINK_FULL_DUPLEX ?
2966                                         "full-duplex" : "half-duplex");
2967         } else {
2968                 PMD_INIT_LOG(INFO, " Port %d: Link Down",
2969                                 (int)(dev->data->port_id));
2970         }
2971         PMD_INIT_LOG(DEBUG, "PCI Address: " PCI_PRI_FMT,
2972                                 pci_dev->addr.domain,
2973                                 pci_dev->addr.bus,
2974                                 pci_dev->addr.devid,
2975                                 pci_dev->addr.function);
2976 }
2977
2978 /*
2979  * It executes link_update after knowing an interrupt occurred.
2980  *
2981  * @param dev
2982  *  Pointer to struct rte_eth_dev.
2983  *
2984  * @return
2985  *  - On success, zero.
2986  *  - On failure, a negative value.
2987  */
2988 static int
2989 txgbe_dev_interrupt_action(struct rte_eth_dev *dev,
2990                            struct rte_intr_handle *intr_handle)
2991 {
2992         struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);
2993         int64_t timeout;
2994         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2995
2996         PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
2997
2998         if (intr->flags & TXGBE_FLAG_MAILBOX) {
2999                 txgbe_pf_mbx_process(dev);
3000                 intr->flags &= ~TXGBE_FLAG_MAILBOX;
3001         }
3002
3003         if (intr->flags & TXGBE_FLAG_PHY_INTERRUPT) {
3004                 hw->phy.handle_lasi(hw);
3005                 intr->flags &= ~TXGBE_FLAG_PHY_INTERRUPT;
3006         }
3007
3008         if (intr->flags & TXGBE_FLAG_NEED_AN_CONFIG) {
3009                 if (hw->devarg.auto_neg == 1 && hw->devarg.poll == 0) {
3010                         hw->mac.kr_handle(hw);
3011                         intr->flags &= ~TXGBE_FLAG_NEED_AN_CONFIG;
3012                 }
3013         }
3014
3015         if (intr->flags & TXGBE_FLAG_NEED_LINK_UPDATE) {
3016                 struct rte_eth_link link;
3017
3018                 /*get the link status before link update, for predicting later*/
3019                 rte_eth_linkstatus_get(dev, &link);
3020
3021                 txgbe_dev_link_update(dev, 0);
3022
3023                 /* likely to up */
3024                 if (!link.link_status)
3025                         /* handle it 1 sec later, wait it being stable */
3026                         timeout = TXGBE_LINK_UP_CHECK_TIMEOUT;
3027                 /* likely to down */
3028                 else if ((hw->subsystem_device_id & 0xFF) ==
3029                                 TXGBE_DEV_ID_KR_KX_KX4 &&
3030                                 hw->devarg.auto_neg == 1)
3031                         /* handle it 2 sec later for backplane AN73 */
3032                         timeout = 2000;
3033                 else
3034                         /* handle it 4 sec later, wait it being stable */
3035                         timeout = TXGBE_LINK_DOWN_CHECK_TIMEOUT;
3036
3037                 txgbe_dev_link_status_print(dev);
3038                 if (rte_eal_alarm_set(timeout * 1000,
3039                                       txgbe_dev_interrupt_delayed_handler,
3040                                       (void *)dev) < 0) {
3041                         PMD_DRV_LOG(ERR, "Error setting alarm");
3042                 } else {
3043                         /* only disable lsc interrupt */
3044                         intr->mask_misc &= ~TXGBE_ICRMISC_LSC;
3045
3046                         intr->mask_orig = intr->mask;
3047                         /* only disable all misc interrupts */
3048                         intr->mask &= ~(1ULL << TXGBE_MISC_VEC_ID);
3049                 }
3050         }
3051
3052         PMD_DRV_LOG(DEBUG, "enable intr immediately");
3053         txgbe_enable_intr(dev);
3054         rte_intr_enable(intr_handle);
3055
3056         return 0;
3057 }
3058
3059 /**
3060  * Interrupt handler which shall be registered for alarm callback for delayed
3061  * handling specific interrupt to wait for the stable nic state. As the
3062  * NIC interrupt state is not stable for txgbe after link is just down,
3063  * it needs to wait 4 seconds to get the stable status.
3064  *
3065  * @param handle
3066  *  Pointer to interrupt handle.
3067  * @param param
3068  *  The address of parameter (struct rte_eth_dev *) registered before.
3069  *
3070  * @return
3071  *  void
3072  */
3073 static void
3074 txgbe_dev_interrupt_delayed_handler(void *param)
3075 {
3076         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3077         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3078         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3079         struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);
3080         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3081         uint32_t eicr;
3082
3083         txgbe_disable_intr(hw);
3084
3085         eicr = ((u32 *)hw->isb_mem)[TXGBE_ISB_MISC];
3086         if (eicr & TXGBE_ICRMISC_VFMBX)
3087                 txgbe_pf_mbx_process(dev);
3088
3089         if (intr->flags & TXGBE_FLAG_PHY_INTERRUPT) {
3090                 hw->phy.handle_lasi(hw);
3091                 intr->flags &= ~TXGBE_FLAG_PHY_INTERRUPT;
3092         }
3093
3094         if (intr->flags & TXGBE_FLAG_NEED_LINK_UPDATE) {
3095                 txgbe_dev_link_update(dev, 0);
3096                 intr->flags &= ~TXGBE_FLAG_NEED_LINK_UPDATE;
3097                 txgbe_dev_link_status_print(dev);
3098                 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC,
3099                                               NULL);
3100         }
3101
3102         if (intr->flags & TXGBE_FLAG_MACSEC) {
3103                 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_MACSEC,
3104                                               NULL);
3105                 intr->flags &= ~TXGBE_FLAG_MACSEC;
3106         }
3107
3108         /* restore original mask */
3109         intr->mask_misc |= TXGBE_ICRMISC_LSC;
3110
3111         intr->mask = intr->mask_orig;
3112         intr->mask_orig = 0;
3113
3114         PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
3115         txgbe_enable_intr(dev);
3116         rte_intr_enable(intr_handle);
3117 }
3118
3119 /**
3120  * Interrupt handler triggered by NIC  for handling
3121  * specific interrupt.
3122  *
3123  * @param handle
3124  *  Pointer to interrupt handle.
3125  * @param param
3126  *  The address of parameter (struct rte_eth_dev *) registered before.
3127  *
3128  * @return
3129  *  void
3130  */
3131 static void
3132 txgbe_dev_interrupt_handler(void *param)
3133 {
3134         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3135
3136         txgbe_dev_interrupt_get_status(dev);
3137         txgbe_dev_interrupt_action(dev, dev->intr_handle);
3138 }
3139
3140 static int
3141 txgbe_dev_led_on(struct rte_eth_dev *dev)
3142 {
3143         struct txgbe_hw *hw;
3144
3145         hw = TXGBE_DEV_HW(dev);
3146         return txgbe_led_on(hw, 4) == 0 ? 0 : -ENOTSUP;
3147 }
3148
3149 static int
3150 txgbe_dev_led_off(struct rte_eth_dev *dev)
3151 {
3152         struct txgbe_hw *hw;
3153
3154         hw = TXGBE_DEV_HW(dev);
3155         return txgbe_led_off(hw, 4) == 0 ? 0 : -ENOTSUP;
3156 }
3157
3158 static int
3159 txgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3160 {
3161         struct txgbe_hw *hw;
3162         uint32_t mflcn_reg;
3163         uint32_t fccfg_reg;
3164         int rx_pause;
3165         int tx_pause;
3166
3167         hw = TXGBE_DEV_HW(dev);
3168
3169         fc_conf->pause_time = hw->fc.pause_time;
3170         fc_conf->high_water = hw->fc.high_water[0];
3171         fc_conf->low_water = hw->fc.low_water[0];
3172         fc_conf->send_xon = hw->fc.send_xon;
3173         fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
3174
3175         /*
3176          * Return rx_pause status according to actual setting of
3177          * RXFCCFG register.
3178          */
3179         mflcn_reg = rd32(hw, TXGBE_RXFCCFG);
3180         if (mflcn_reg & (TXGBE_RXFCCFG_FC | TXGBE_RXFCCFG_PFC))
3181                 rx_pause = 1;
3182         else
3183                 rx_pause = 0;
3184
3185         /*
3186          * Return tx_pause status according to actual setting of
3187          * TXFCCFG register.
3188          */
3189         fccfg_reg = rd32(hw, TXGBE_TXFCCFG);
3190         if (fccfg_reg & (TXGBE_TXFCCFG_FC | TXGBE_TXFCCFG_PFC))
3191                 tx_pause = 1;
3192         else
3193                 tx_pause = 0;
3194
3195         if (rx_pause && tx_pause)
3196                 fc_conf->mode = RTE_FC_FULL;
3197         else if (rx_pause)
3198                 fc_conf->mode = RTE_FC_RX_PAUSE;
3199         else if (tx_pause)
3200                 fc_conf->mode = RTE_FC_TX_PAUSE;
3201         else
3202                 fc_conf->mode = RTE_FC_NONE;
3203
3204         return 0;
3205 }
3206
3207 static int
3208 txgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3209 {
3210         struct txgbe_hw *hw;
3211         int err;
3212         uint32_t rx_buf_size;
3213         uint32_t max_high_water;
3214         enum txgbe_fc_mode rte_fcmode_2_txgbe_fcmode[] = {
3215                 txgbe_fc_none,
3216                 txgbe_fc_rx_pause,
3217                 txgbe_fc_tx_pause,
3218                 txgbe_fc_full
3219         };
3220
3221         PMD_INIT_FUNC_TRACE();
3222
3223         hw = TXGBE_DEV_HW(dev);
3224         rx_buf_size = rd32(hw, TXGBE_PBRXSIZE(0));
3225         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
3226
3227         /*
3228          * At least reserve one Ethernet frame for watermark
3229          * high_water/low_water in kilo bytes for txgbe
3230          */
3231         max_high_water = (rx_buf_size - RTE_ETHER_MAX_LEN) >> 10;
3232         if (fc_conf->high_water > max_high_water ||
3233             fc_conf->high_water < fc_conf->low_water) {
3234                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
3235                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
3236                 return -EINVAL;
3237         }
3238
3239         hw->fc.requested_mode = rte_fcmode_2_txgbe_fcmode[fc_conf->mode];
3240         hw->fc.pause_time     = fc_conf->pause_time;
3241         hw->fc.high_water[0]  = fc_conf->high_water;
3242         hw->fc.low_water[0]   = fc_conf->low_water;
3243         hw->fc.send_xon       = fc_conf->send_xon;
3244         hw->fc.disable_fc_autoneg = !fc_conf->autoneg;
3245
3246         err = txgbe_fc_enable(hw);
3247
3248         /* Not negotiated is not an error case */
3249         if (err == 0 || err == TXGBE_ERR_FC_NOT_NEGOTIATED) {
3250                 wr32m(hw, TXGBE_MACRXFLT, TXGBE_MACRXFLT_CTL_MASK,
3251                       (fc_conf->mac_ctrl_frame_fwd
3252                        ? TXGBE_MACRXFLT_CTL_NOPS : TXGBE_MACRXFLT_CTL_DROP));
3253                 txgbe_flush(hw);
3254
3255                 return 0;
3256         }
3257
3258         PMD_INIT_LOG(ERR, "txgbe_fc_enable = 0x%x", err);
3259         return -EIO;
3260 }
3261
3262 static int
3263 txgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
3264                 struct rte_eth_pfc_conf *pfc_conf)
3265 {
3266         int err;
3267         uint32_t rx_buf_size;
3268         uint32_t max_high_water;
3269         uint8_t tc_num;
3270         uint8_t  map[TXGBE_DCB_UP_MAX] = { 0 };
3271         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3272         struct txgbe_dcb_config *dcb_config = TXGBE_DEV_DCB_CONFIG(dev);
3273
3274         enum txgbe_fc_mode rte_fcmode_2_txgbe_fcmode[] = {
3275                 txgbe_fc_none,
3276                 txgbe_fc_rx_pause,
3277                 txgbe_fc_tx_pause,
3278                 txgbe_fc_full
3279         };
3280
3281         PMD_INIT_FUNC_TRACE();
3282
3283         txgbe_dcb_unpack_map_cee(dcb_config, TXGBE_DCB_RX_CONFIG, map);
3284         tc_num = map[pfc_conf->priority];
3285         rx_buf_size = rd32(hw, TXGBE_PBRXSIZE(tc_num));
3286         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
3287         /*
3288          * At least reserve one Ethernet frame for watermark
3289          * high_water/low_water in kilo bytes for txgbe
3290          */
3291         max_high_water = (rx_buf_size - RTE_ETHER_MAX_LEN) >> 10;
3292         if (pfc_conf->fc.high_water > max_high_water ||
3293             pfc_conf->fc.high_water <= pfc_conf->fc.low_water) {
3294                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
3295                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
3296                 return -EINVAL;
3297         }
3298
3299         hw->fc.requested_mode = rte_fcmode_2_txgbe_fcmode[pfc_conf->fc.mode];
3300         hw->fc.pause_time = pfc_conf->fc.pause_time;
3301         hw->fc.send_xon = pfc_conf->fc.send_xon;
3302         hw->fc.low_water[tc_num] =  pfc_conf->fc.low_water;
3303         hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
3304
3305         err = txgbe_dcb_pfc_enable(hw, tc_num);
3306
3307         /* Not negotiated is not an error case */
3308         if (err == 0 || err == TXGBE_ERR_FC_NOT_NEGOTIATED)
3309                 return 0;
3310
3311         PMD_INIT_LOG(ERR, "txgbe_dcb_pfc_enable = 0x%x", err);
3312         return -EIO;
3313 }
3314
3315 int
3316 txgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
3317                           struct rte_eth_rss_reta_entry64 *reta_conf,
3318                           uint16_t reta_size)
3319 {
3320         uint8_t i, j, mask;
3321         uint32_t reta;
3322         uint16_t idx, shift;
3323         struct txgbe_adapter *adapter = TXGBE_DEV_ADAPTER(dev);
3324         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3325
3326         PMD_INIT_FUNC_TRACE();
3327
3328         if (!txgbe_rss_update_sp(hw->mac.type)) {
3329                 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this "
3330                         "NIC.");
3331                 return -ENOTSUP;
3332         }
3333
3334         if (reta_size != ETH_RSS_RETA_SIZE_128) {
3335                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3336                         "(%d) doesn't match the number hardware can supported "
3337                         "(%d)", reta_size, ETH_RSS_RETA_SIZE_128);
3338                 return -EINVAL;
3339         }
3340
3341         for (i = 0; i < reta_size; i += 4) {
3342                 idx = i / RTE_RETA_GROUP_SIZE;
3343                 shift = i % RTE_RETA_GROUP_SIZE;
3344                 mask = (uint8_t)RS64(reta_conf[idx].mask, shift, 0xF);
3345                 if (!mask)
3346                         continue;
3347
3348                 reta = rd32at(hw, TXGBE_REG_RSSTBL, i >> 2);
3349                 for (j = 0; j < 4; j++) {
3350                         if (RS8(mask, j, 0x1)) {
3351                                 reta  &= ~(MS32(8 * j, 0xFF));
3352                                 reta |= LS32(reta_conf[idx].reta[shift + j],
3353                                                 8 * j, 0xFF);
3354                         }
3355                 }
3356                 wr32at(hw, TXGBE_REG_RSSTBL, i >> 2, reta);
3357         }
3358         adapter->rss_reta_updated = 1;
3359
3360         return 0;
3361 }
3362
3363 int
3364 txgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
3365                          struct rte_eth_rss_reta_entry64 *reta_conf,
3366                          uint16_t reta_size)
3367 {
3368         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3369         uint8_t i, j, mask;
3370         uint32_t reta;
3371         uint16_t idx, shift;
3372
3373         PMD_INIT_FUNC_TRACE();
3374
3375         if (reta_size != ETH_RSS_RETA_SIZE_128) {
3376                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3377                         "(%d) doesn't match the number hardware can supported "
3378                         "(%d)", reta_size, ETH_RSS_RETA_SIZE_128);
3379                 return -EINVAL;
3380         }
3381
3382         for (i = 0; i < reta_size; i += 4) {
3383                 idx = i / RTE_RETA_GROUP_SIZE;
3384                 shift = i % RTE_RETA_GROUP_SIZE;
3385                 mask = (uint8_t)RS64(reta_conf[idx].mask, shift, 0xF);
3386                 if (!mask)
3387                         continue;
3388
3389                 reta = rd32at(hw, TXGBE_REG_RSSTBL, i >> 2);
3390                 for (j = 0; j < 4; j++) {
3391                         if (RS8(mask, j, 0x1))
3392                                 reta_conf[idx].reta[shift + j] =
3393                                         (uint16_t)RS32(reta, 8 * j, 0xFF);
3394                 }
3395         }
3396
3397         return 0;
3398 }
3399
3400 static int
3401 txgbe_add_rar(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
3402                                 uint32_t index, uint32_t pool)
3403 {
3404         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3405         uint32_t enable_addr = 1;
3406
3407         return txgbe_set_rar(hw, index, mac_addr->addr_bytes,
3408                              pool, enable_addr);
3409 }
3410
3411 static void
3412 txgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
3413 {
3414         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3415
3416         txgbe_clear_rar(hw, index);
3417 }
3418
3419 static int
3420 txgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *addr)
3421 {
3422         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3423
3424         txgbe_remove_rar(dev, 0);
3425         txgbe_add_rar(dev, addr, 0, pci_dev->max_vfs);
3426
3427         return 0;
3428 }
3429
3430 static int
3431 txgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
3432 {
3433         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3434         struct rte_eth_dev_info dev_info;
3435         uint32_t frame_size = mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN;
3436         struct rte_eth_dev_data *dev_data = dev->data;
3437         int ret;
3438
3439         ret = txgbe_dev_info_get(dev, &dev_info);
3440         if (ret != 0)
3441                 return ret;
3442
3443         /* check that mtu is within the allowed range */
3444         if (mtu < RTE_ETHER_MIN_MTU || frame_size > dev_info.max_rx_pktlen)
3445                 return -EINVAL;
3446
3447         /* If device is started, refuse mtu that requires the support of
3448          * scattered packets when this feature has not been enabled before.
3449          */
3450         if (dev_data->dev_started && !dev_data->scattered_rx &&
3451             (frame_size + 2 * TXGBE_VLAN_TAG_SIZE >
3452              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
3453                 PMD_INIT_LOG(ERR, "Stop port first.");
3454                 return -EINVAL;
3455         }
3456
3457         /* update max frame size */
3458         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
3459
3460         if (hw->mode)
3461                 wr32m(hw, TXGBE_FRMSZ, TXGBE_FRMSZ_MAX_MASK,
3462                         TXGBE_FRAME_SIZE_MAX);
3463         else
3464                 wr32m(hw, TXGBE_FRMSZ, TXGBE_FRMSZ_MAX_MASK,
3465                         TXGBE_FRMSZ_MAX(frame_size));
3466
3467         return 0;
3468 }
3469
3470 static uint32_t
3471 txgbe_uta_vector(struct txgbe_hw *hw, struct rte_ether_addr *uc_addr)
3472 {
3473         uint32_t vector = 0;
3474
3475         switch (hw->mac.mc_filter_type) {
3476         case 0:   /* use bits [47:36] of the address */
3477                 vector = ((uc_addr->addr_bytes[4] >> 4) |
3478                         (((uint16_t)uc_addr->addr_bytes[5]) << 4));
3479                 break;
3480         case 1:   /* use bits [46:35] of the address */
3481                 vector = ((uc_addr->addr_bytes[4] >> 3) |
3482                         (((uint16_t)uc_addr->addr_bytes[5]) << 5));
3483                 break;
3484         case 2:   /* use bits [45:34] of the address */
3485                 vector = ((uc_addr->addr_bytes[4] >> 2) |
3486                         (((uint16_t)uc_addr->addr_bytes[5]) << 6));
3487                 break;
3488         case 3:   /* use bits [43:32] of the address */
3489                 vector = ((uc_addr->addr_bytes[4]) |
3490                         (((uint16_t)uc_addr->addr_bytes[5]) << 8));
3491                 break;
3492         default:  /* Invalid mc_filter_type */
3493                 break;
3494         }
3495
3496         /* vector can only be 12-bits or boundary will be exceeded */
3497         vector &= 0xFFF;
3498         return vector;
3499 }
3500
3501 static int
3502 txgbe_uc_hash_table_set(struct rte_eth_dev *dev,
3503                         struct rte_ether_addr *mac_addr, uint8_t on)
3504 {
3505         uint32_t vector;
3506         uint32_t uta_idx;
3507         uint32_t reg_val;
3508         uint32_t uta_mask;
3509         uint32_t psrctl;
3510
3511         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3512         struct txgbe_uta_info *uta_info = TXGBE_DEV_UTA_INFO(dev);
3513
3514         /* The UTA table only exists on pf hardware */
3515         if (hw->mac.type < txgbe_mac_raptor)
3516                 return -ENOTSUP;
3517
3518         vector = txgbe_uta_vector(hw, mac_addr);
3519         uta_idx = (vector >> 5) & 0x7F;
3520         uta_mask = 0x1UL << (vector & 0x1F);
3521
3522         if (!!on == !!(uta_info->uta_shadow[uta_idx] & uta_mask))
3523                 return 0;
3524
3525         reg_val = rd32(hw, TXGBE_UCADDRTBL(uta_idx));
3526         if (on) {
3527                 uta_info->uta_in_use++;
3528                 reg_val |= uta_mask;
3529                 uta_info->uta_shadow[uta_idx] |= uta_mask;
3530         } else {
3531                 uta_info->uta_in_use--;
3532                 reg_val &= ~uta_mask;
3533                 uta_info->uta_shadow[uta_idx] &= ~uta_mask;
3534         }
3535
3536         wr32(hw, TXGBE_UCADDRTBL(uta_idx), reg_val);
3537
3538         psrctl = rd32(hw, TXGBE_PSRCTL);
3539         if (uta_info->uta_in_use > 0)
3540                 psrctl |= TXGBE_PSRCTL_UCHFENA;
3541         else
3542                 psrctl &= ~TXGBE_PSRCTL_UCHFENA;
3543
3544         psrctl &= ~TXGBE_PSRCTL_ADHF12_MASK;
3545         psrctl |= TXGBE_PSRCTL_ADHF12(hw->mac.mc_filter_type);
3546         wr32(hw, TXGBE_PSRCTL, psrctl);
3547
3548         return 0;
3549 }
3550
3551 static int
3552 txgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
3553 {
3554         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3555         struct txgbe_uta_info *uta_info = TXGBE_DEV_UTA_INFO(dev);
3556         uint32_t psrctl;
3557         int i;
3558
3559         /* The UTA table only exists on pf hardware */
3560         if (hw->mac.type < txgbe_mac_raptor)
3561                 return -ENOTSUP;
3562
3563         if (on) {
3564                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
3565                         uta_info->uta_shadow[i] = ~0;
3566                         wr32(hw, TXGBE_UCADDRTBL(i), ~0);
3567                 }
3568         } else {
3569                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
3570                         uta_info->uta_shadow[i] = 0;
3571                         wr32(hw, TXGBE_UCADDRTBL(i), 0);
3572                 }
3573         }
3574
3575         psrctl = rd32(hw, TXGBE_PSRCTL);
3576         if (on)
3577                 psrctl |= TXGBE_PSRCTL_UCHFENA;
3578         else
3579                 psrctl &= ~TXGBE_PSRCTL_UCHFENA;
3580
3581         psrctl &= ~TXGBE_PSRCTL_ADHF12_MASK;
3582         psrctl |= TXGBE_PSRCTL_ADHF12(hw->mac.mc_filter_type);
3583         wr32(hw, TXGBE_PSRCTL, psrctl);
3584
3585         return 0;
3586 }
3587
3588 uint32_t
3589 txgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
3590 {
3591         uint32_t new_val = orig_val;
3592
3593         if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
3594                 new_val |= TXGBE_POOLETHCTL_UTA;
3595         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
3596                 new_val |= TXGBE_POOLETHCTL_MCHA;
3597         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
3598                 new_val |= TXGBE_POOLETHCTL_UCHA;
3599         if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
3600                 new_val |= TXGBE_POOLETHCTL_BCA;
3601         if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
3602                 new_val |= TXGBE_POOLETHCTL_MCP;
3603
3604         return new_val;
3605 }
3606
3607 static int
3608 txgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
3609 {
3610         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3611         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3612         uint32_t mask;
3613         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3614
3615         if (queue_id < 32) {
3616                 mask = rd32(hw, TXGBE_IMS(0));
3617                 mask &= (1 << queue_id);
3618                 wr32(hw, TXGBE_IMS(0), mask);
3619         } else if (queue_id < 64) {
3620                 mask = rd32(hw, TXGBE_IMS(1));
3621                 mask &= (1 << (queue_id - 32));
3622                 wr32(hw, TXGBE_IMS(1), mask);
3623         }
3624         rte_intr_enable(intr_handle);
3625
3626         return 0;
3627 }
3628
3629 static int
3630 txgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
3631 {
3632         uint32_t mask;
3633         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3634
3635         if (queue_id < 32) {
3636                 mask = rd32(hw, TXGBE_IMS(0));
3637                 mask &= ~(1 << queue_id);
3638                 wr32(hw, TXGBE_IMS(0), mask);
3639         } else if (queue_id < 64) {
3640                 mask = rd32(hw, TXGBE_IMS(1));
3641                 mask &= ~(1 << (queue_id - 32));
3642                 wr32(hw, TXGBE_IMS(1), mask);
3643         }
3644
3645         return 0;
3646 }
3647
3648 /**
3649  * set the IVAR registers, mapping interrupt causes to vectors
3650  * @param hw
3651  *  pointer to txgbe_hw struct
3652  * @direction
3653  *  0 for Rx, 1 for Tx, -1 for other causes
3654  * @queue
3655  *  queue to map the corresponding interrupt to
3656  * @msix_vector
3657  *  the vector to map to the corresponding queue
3658  */
3659 void
3660 txgbe_set_ivar_map(struct txgbe_hw *hw, int8_t direction,
3661                    uint8_t queue, uint8_t msix_vector)
3662 {
3663         uint32_t tmp, idx;
3664
3665         if (direction == -1) {
3666                 /* other causes */
3667                 msix_vector |= TXGBE_IVARMISC_VLD;
3668                 idx = 0;
3669                 tmp = rd32(hw, TXGBE_IVARMISC);
3670                 tmp &= ~(0xFF << idx);
3671                 tmp |= (msix_vector << idx);
3672                 wr32(hw, TXGBE_IVARMISC, tmp);
3673         } else {
3674                 /* rx or tx causes */
3675                 /* Workround for ICR lost */
3676                 idx = ((16 * (queue & 1)) + (8 * direction));
3677                 tmp = rd32(hw, TXGBE_IVAR(queue >> 1));
3678                 tmp &= ~(0xFF << idx);
3679                 tmp |= (msix_vector << idx);
3680                 wr32(hw, TXGBE_IVAR(queue >> 1), tmp);
3681         }
3682 }
3683
3684 /**
3685  * Sets up the hardware to properly generate MSI-X interrupts
3686  * @hw
3687  *  board private structure
3688  */
3689 static void
3690 txgbe_configure_msix(struct rte_eth_dev *dev)
3691 {
3692         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3693         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3694         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3695         uint32_t queue_id, base = TXGBE_MISC_VEC_ID;
3696         uint32_t vec = TXGBE_MISC_VEC_ID;
3697         uint32_t gpie;
3698
3699         /* won't configure msix register if no mapping is done
3700          * between intr vector and event fd
3701          * but if misx has been enabled already, need to configure
3702          * auto clean, auto mask and throttling.
3703          */
3704         gpie = rd32(hw, TXGBE_GPIE);
3705         if (!rte_intr_dp_is_en(intr_handle) &&
3706             !(gpie & TXGBE_GPIE_MSIX))
3707                 return;
3708
3709         if (rte_intr_allow_others(intr_handle)) {
3710                 base = TXGBE_RX_VEC_START;
3711                 vec = base;
3712         }
3713
3714         /* setup GPIE for MSI-x mode */
3715         gpie = rd32(hw, TXGBE_GPIE);
3716         gpie |= TXGBE_GPIE_MSIX;
3717         wr32(hw, TXGBE_GPIE, gpie);
3718
3719         /* Populate the IVAR table and set the ITR values to the
3720          * corresponding register.
3721          */
3722         if (rte_intr_dp_is_en(intr_handle)) {
3723                 for (queue_id = 0; queue_id < dev->data->nb_rx_queues;
3724                         queue_id++) {
3725                         /* by default, 1:1 mapping */
3726                         txgbe_set_ivar_map(hw, 0, queue_id, vec);
3727                         intr_handle->intr_vec[queue_id] = vec;
3728                         if (vec < base + intr_handle->nb_efd - 1)
3729                                 vec++;
3730                 }
3731
3732                 txgbe_set_ivar_map(hw, -1, 1, TXGBE_MISC_VEC_ID);
3733         }
3734         wr32(hw, TXGBE_ITR(TXGBE_MISC_VEC_ID),
3735                         TXGBE_ITR_IVAL_10G(TXGBE_QUEUE_ITR_INTERVAL_DEFAULT)
3736                         | TXGBE_ITR_WRDSA);
3737 }
3738
3739 int
3740 txgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
3741                            uint16_t queue_idx, uint16_t tx_rate)
3742 {
3743         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3744         uint32_t bcnrc_val;
3745
3746         if (queue_idx >= hw->mac.max_tx_queues)
3747                 return -EINVAL;
3748
3749         if (tx_rate != 0) {
3750                 bcnrc_val = TXGBE_ARBTXRATE_MAX(tx_rate);
3751                 bcnrc_val |= TXGBE_ARBTXRATE_MIN(tx_rate / 2);
3752         } else {
3753                 bcnrc_val = 0;
3754         }
3755
3756         /*
3757          * Set global transmit compensation time to the MMW_SIZE in ARBTXMMW
3758          * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported.
3759          */
3760         wr32(hw, TXGBE_ARBTXMMW, 0x14);
3761
3762         /* Set ARBTXRATE of queue X */
3763         wr32(hw, TXGBE_ARBPOOLIDX, queue_idx);
3764         wr32(hw, TXGBE_ARBTXRATE, bcnrc_val);
3765         txgbe_flush(hw);
3766
3767         return 0;
3768 }
3769
3770 int
3771 txgbe_syn_filter_set(struct rte_eth_dev *dev,
3772                         struct rte_eth_syn_filter *filter,
3773                         bool add)
3774 {
3775         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3776         struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(dev);
3777         uint32_t syn_info;
3778         uint32_t synqf;
3779
3780         if (filter->queue >= TXGBE_MAX_RX_QUEUE_NUM)
3781                 return -EINVAL;
3782
3783         syn_info = filter_info->syn_info;
3784
3785         if (add) {
3786                 if (syn_info & TXGBE_SYNCLS_ENA)
3787                         return -EINVAL;
3788                 synqf = (uint32_t)TXGBE_SYNCLS_QPID(filter->queue);
3789                 synqf |= TXGBE_SYNCLS_ENA;
3790
3791                 if (filter->hig_pri)
3792                         synqf |= TXGBE_SYNCLS_HIPRIO;
3793                 else
3794                         synqf &= ~TXGBE_SYNCLS_HIPRIO;
3795         } else {
3796                 synqf = rd32(hw, TXGBE_SYNCLS);
3797                 if (!(syn_info & TXGBE_SYNCLS_ENA))
3798                         return -ENOENT;
3799                 synqf &= ~(TXGBE_SYNCLS_QPID_MASK | TXGBE_SYNCLS_ENA);
3800         }
3801
3802         filter_info->syn_info = synqf;
3803         wr32(hw, TXGBE_SYNCLS, synqf);
3804         txgbe_flush(hw);
3805         return 0;
3806 }
3807
3808 static inline enum txgbe_5tuple_protocol
3809 convert_protocol_type(uint8_t protocol_value)
3810 {
3811         if (protocol_value == IPPROTO_TCP)
3812                 return TXGBE_5TF_PROT_TCP;
3813         else if (protocol_value == IPPROTO_UDP)
3814                 return TXGBE_5TF_PROT_UDP;
3815         else if (protocol_value == IPPROTO_SCTP)
3816                 return TXGBE_5TF_PROT_SCTP;
3817         else
3818                 return TXGBE_5TF_PROT_NONE;
3819 }
3820
3821 /* inject a 5-tuple filter to HW */
3822 static inline void
3823 txgbe_inject_5tuple_filter(struct rte_eth_dev *dev,
3824                            struct txgbe_5tuple_filter *filter)
3825 {
3826         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3827         int i;
3828         uint32_t ftqf, sdpqf;
3829         uint32_t l34timir = 0;
3830         uint32_t mask = TXGBE_5TFCTL0_MASK;
3831
3832         i = filter->index;
3833         sdpqf = TXGBE_5TFPORT_DST(be_to_le16(filter->filter_info.dst_port));
3834         sdpqf |= TXGBE_5TFPORT_SRC(be_to_le16(filter->filter_info.src_port));
3835
3836         ftqf = TXGBE_5TFCTL0_PROTO(filter->filter_info.proto);
3837         ftqf |= TXGBE_5TFCTL0_PRI(filter->filter_info.priority);
3838         if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
3839                 mask &= ~TXGBE_5TFCTL0_MSADDR;
3840         if (filter->filter_info.dst_ip_mask == 0)
3841                 mask &= ~TXGBE_5TFCTL0_MDADDR;
3842         if (filter->filter_info.src_port_mask == 0)
3843                 mask &= ~TXGBE_5TFCTL0_MSPORT;
3844         if (filter->filter_info.dst_port_mask == 0)
3845                 mask &= ~TXGBE_5TFCTL0_MDPORT;
3846         if (filter->filter_info.proto_mask == 0)
3847                 mask &= ~TXGBE_5TFCTL0_MPROTO;
3848         ftqf |= mask;
3849         ftqf |= TXGBE_5TFCTL0_MPOOL;
3850         ftqf |= TXGBE_5TFCTL0_ENA;
3851
3852         wr32(hw, TXGBE_5TFDADDR(i), be_to_le32(filter->filter_info.dst_ip));
3853         wr32(hw, TXGBE_5TFSADDR(i), be_to_le32(filter->filter_info.src_ip));
3854         wr32(hw, TXGBE_5TFPORT(i), sdpqf);
3855         wr32(hw, TXGBE_5TFCTL0(i), ftqf);
3856
3857         l34timir |= TXGBE_5TFCTL1_QP(filter->queue);
3858         wr32(hw, TXGBE_5TFCTL1(i), l34timir);
3859 }
3860
3861 /*
3862  * add a 5tuple filter
3863  *
3864  * @param
3865  * dev: Pointer to struct rte_eth_dev.
3866  * index: the index the filter allocates.
3867  * filter: pointer to the filter that will be added.
3868  * rx_queue: the queue id the filter assigned to.
3869  *
3870  * @return
3871  *    - On success, zero.
3872  *    - On failure, a negative value.
3873  */
3874 static int
3875 txgbe_add_5tuple_filter(struct rte_eth_dev *dev,
3876                         struct txgbe_5tuple_filter *filter)
3877 {
3878         struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(dev);
3879         int i, idx, shift;
3880
3881         /*
3882          * look for an unused 5tuple filter index,
3883          * and insert the filter to list.
3884          */
3885         for (i = 0; i < TXGBE_MAX_FTQF_FILTERS; i++) {
3886                 idx = i / (sizeof(uint32_t) * NBBY);
3887                 shift = i % (sizeof(uint32_t) * NBBY);
3888                 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
3889                         filter_info->fivetuple_mask[idx] |= 1 << shift;
3890                         filter->index = i;
3891                         TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
3892                                           filter,
3893                                           entries);
3894                         break;
3895                 }
3896         }
3897         if (i >= TXGBE_MAX_FTQF_FILTERS) {
3898                 PMD_DRV_LOG(ERR, "5tuple filters are full.");
3899                 return -ENOSYS;
3900         }
3901
3902         txgbe_inject_5tuple_filter(dev, filter);
3903
3904         return 0;
3905 }
3906
3907 /*
3908  * remove a 5tuple filter
3909  *
3910  * @param
3911  * dev: Pointer to struct rte_eth_dev.
3912  * filter: the pointer of the filter will be removed.
3913  */
3914 static void
3915 txgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
3916                         struct txgbe_5tuple_filter *filter)
3917 {
3918         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3919         struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(dev);
3920         uint16_t index = filter->index;
3921
3922         filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
3923                                 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
3924         TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
3925         rte_free(filter);
3926
3927         wr32(hw, TXGBE_5TFDADDR(index), 0);
3928         wr32(hw, TXGBE_5TFSADDR(index), 0);
3929         wr32(hw, TXGBE_5TFPORT(index), 0);
3930         wr32(hw, TXGBE_5TFCTL0(index), 0);
3931         wr32(hw, TXGBE_5TFCTL1(index), 0);
3932 }
3933
3934 static inline struct txgbe_5tuple_filter *
3935 txgbe_5tuple_filter_lookup(struct txgbe_5tuple_filter_list *filter_list,
3936                         struct txgbe_5tuple_filter_info *key)
3937 {
3938         struct txgbe_5tuple_filter *it;
3939
3940         TAILQ_FOREACH(it, filter_list, entries) {
3941                 if (memcmp(key, &it->filter_info,
3942                         sizeof(struct txgbe_5tuple_filter_info)) == 0) {
3943                         return it;
3944                 }
3945         }
3946         return NULL;
3947 }
3948
3949 /* translate elements in struct rte_eth_ntuple_filter
3950  * to struct txgbe_5tuple_filter_info
3951  */
3952 static inline int
3953 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
3954                         struct txgbe_5tuple_filter_info *filter_info)
3955 {
3956         if (filter->queue >= TXGBE_MAX_RX_QUEUE_NUM ||
3957                 filter->priority > TXGBE_5TUPLE_MAX_PRI ||
3958                 filter->priority < TXGBE_5TUPLE_MIN_PRI)
3959                 return -EINVAL;
3960
3961         switch (filter->dst_ip_mask) {
3962         case UINT32_MAX:
3963                 filter_info->dst_ip_mask = 0;
3964                 filter_info->dst_ip = filter->dst_ip;
3965                 break;
3966         case 0:
3967                 filter_info->dst_ip_mask = 1;
3968                 break;
3969         default:
3970                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
3971                 return -EINVAL;
3972         }
3973
3974         switch (filter->src_ip_mask) {
3975         case UINT32_MAX:
3976                 filter_info->src_ip_mask = 0;
3977                 filter_info->src_ip = filter->src_ip;
3978                 break;
3979         case 0:
3980                 filter_info->src_ip_mask = 1;
3981                 break;
3982         default:
3983                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
3984                 return -EINVAL;
3985         }
3986
3987         switch (filter->dst_port_mask) {
3988         case UINT16_MAX:
3989                 filter_info->dst_port_mask = 0;
3990                 filter_info->dst_port = filter->dst_port;
3991                 break;
3992         case 0:
3993                 filter_info->dst_port_mask = 1;
3994                 break;
3995         default:
3996                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
3997                 return -EINVAL;
3998         }
3999
4000         switch (filter->src_port_mask) {
4001         case UINT16_MAX:
4002                 filter_info->src_port_mask = 0;
4003                 filter_info->src_port = filter->src_port;
4004                 break;
4005         case 0:
4006                 filter_info->src_port_mask = 1;
4007                 break;
4008         default:
4009                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
4010                 return -EINVAL;
4011         }
4012
4013         switch (filter->proto_mask) {
4014         case UINT8_MAX:
4015                 filter_info->proto_mask = 0;
4016                 filter_info->proto =
4017                         convert_protocol_type(filter->proto);
4018                 break;
4019         case 0:
4020                 filter_info->proto_mask = 1;
4021                 break;
4022         default:
4023                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
4024                 return -EINVAL;
4025         }
4026
4027         filter_info->priority = (uint8_t)filter->priority;
4028         return 0;
4029 }
4030
4031 /*
4032  * add or delete a ntuple filter
4033  *
4034  * @param
4035  * dev: Pointer to struct rte_eth_dev.
4036  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
4037  * add: if true, add filter, if false, remove filter
4038  *
4039  * @return
4040  *    - On success, zero.
4041  *    - On failure, a negative value.
4042  */
4043 int
4044 txgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
4045                         struct rte_eth_ntuple_filter *ntuple_filter,
4046                         bool add)
4047 {
4048         struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(dev);
4049         struct txgbe_5tuple_filter_info filter_5tuple;
4050         struct txgbe_5tuple_filter *filter;
4051         int ret;
4052
4053         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
4054                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
4055                 return -EINVAL;
4056         }
4057
4058         memset(&filter_5tuple, 0, sizeof(struct txgbe_5tuple_filter_info));
4059         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
4060         if (ret < 0)
4061                 return ret;
4062
4063         filter = txgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
4064                                          &filter_5tuple);
4065         if (filter != NULL && add) {
4066                 PMD_DRV_LOG(ERR, "filter exists.");
4067                 return -EEXIST;
4068         }
4069         if (filter == NULL && !add) {
4070                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4071                 return -ENOENT;
4072         }
4073
4074         if (add) {
4075                 filter = rte_zmalloc("txgbe_5tuple_filter",
4076                                 sizeof(struct txgbe_5tuple_filter), 0);
4077                 if (filter == NULL)
4078                         return -ENOMEM;
4079                 rte_memcpy(&filter->filter_info,
4080                                  &filter_5tuple,
4081                                  sizeof(struct txgbe_5tuple_filter_info));
4082                 filter->queue = ntuple_filter->queue;
4083                 ret = txgbe_add_5tuple_filter(dev, filter);
4084                 if (ret < 0) {
4085                         rte_free(filter);
4086                         return ret;
4087                 }
4088         } else {
4089                 txgbe_remove_5tuple_filter(dev, filter);
4090         }
4091
4092         return 0;
4093 }
4094
4095 int
4096 txgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
4097                         struct rte_eth_ethertype_filter *filter,
4098                         bool add)
4099 {
4100         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4101         struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(dev);
4102         uint32_t etqf = 0;
4103         uint32_t etqs = 0;
4104         int ret;
4105         struct txgbe_ethertype_filter ethertype_filter;
4106
4107         if (filter->queue >= TXGBE_MAX_RX_QUEUE_NUM)
4108                 return -EINVAL;
4109
4110         if (filter->ether_type == RTE_ETHER_TYPE_IPV4 ||
4111             filter->ether_type == RTE_ETHER_TYPE_IPV6) {
4112                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
4113                         " ethertype filter.", filter->ether_type);
4114                 return -EINVAL;
4115         }
4116
4117         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
4118                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
4119                 return -EINVAL;
4120         }
4121         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
4122                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
4123                 return -EINVAL;
4124         }
4125
4126         ret = txgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
4127         if (ret >= 0 && add) {
4128                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
4129                             filter->ether_type);
4130                 return -EEXIST;
4131         }
4132         if (ret < 0 && !add) {
4133                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
4134                             filter->ether_type);
4135                 return -ENOENT;
4136         }
4137
4138         if (add) {
4139                 etqf = TXGBE_ETFLT_ENA;
4140                 etqf |= TXGBE_ETFLT_ETID(filter->ether_type);
4141                 etqs |= TXGBE_ETCLS_QPID(filter->queue);
4142                 etqs |= TXGBE_ETCLS_QENA;
4143
4144                 ethertype_filter.ethertype = filter->ether_type;
4145                 ethertype_filter.etqf = etqf;
4146                 ethertype_filter.etqs = etqs;
4147                 ethertype_filter.conf = FALSE;
4148                 ret = txgbe_ethertype_filter_insert(filter_info,
4149                                                     &ethertype_filter);
4150                 if (ret < 0) {
4151                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
4152                         return -ENOSPC;
4153                 }
4154         } else {
4155                 ret = txgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
4156                 if (ret < 0)
4157                         return -ENOSYS;
4158         }
4159         wr32(hw, TXGBE_ETFLT(ret), etqf);
4160         wr32(hw, TXGBE_ETCLS(ret), etqs);
4161         txgbe_flush(hw);
4162
4163         return 0;
4164 }
4165
4166 static int
4167 txgbe_dev_flow_ops_get(__rte_unused struct rte_eth_dev *dev,
4168                        const struct rte_flow_ops **ops)
4169 {
4170         *ops = &txgbe_flow_ops;
4171         return 0;
4172 }
4173
4174 static u8 *
4175 txgbe_dev_addr_list_itr(__rte_unused struct txgbe_hw *hw,
4176                         u8 **mc_addr_ptr, u32 *vmdq)
4177 {
4178         u8 *mc_addr;
4179
4180         *vmdq = 0;
4181         mc_addr = *mc_addr_ptr;
4182         *mc_addr_ptr = (mc_addr + sizeof(struct rte_ether_addr));
4183         return mc_addr;
4184 }
4185
4186 int
4187 txgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
4188                           struct rte_ether_addr *mc_addr_set,
4189                           uint32_t nb_mc_addr)
4190 {
4191         struct txgbe_hw *hw;
4192         u8 *mc_addr_list;
4193
4194         hw = TXGBE_DEV_HW(dev);
4195         mc_addr_list = (u8 *)mc_addr_set;
4196         return hw->mac.update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
4197                                          txgbe_dev_addr_list_itr, TRUE);
4198 }
4199
4200 static uint64_t
4201 txgbe_read_systime_cyclecounter(struct rte_eth_dev *dev)
4202 {
4203         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4204         uint64_t systime_cycles;
4205
4206         systime_cycles = (uint64_t)rd32(hw, TXGBE_TSTIMEL);
4207         systime_cycles |= (uint64_t)rd32(hw, TXGBE_TSTIMEH) << 32;
4208
4209         return systime_cycles;
4210 }
4211
4212 static uint64_t
4213 txgbe_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
4214 {
4215         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4216         uint64_t rx_tstamp_cycles;
4217
4218         /* TSRXSTMPL stores ns and TSRXSTMPH stores seconds. */
4219         rx_tstamp_cycles = (uint64_t)rd32(hw, TXGBE_TSRXSTMPL);
4220         rx_tstamp_cycles |= (uint64_t)rd32(hw, TXGBE_TSRXSTMPH) << 32;
4221
4222         return rx_tstamp_cycles;
4223 }
4224
4225 static uint64_t
4226 txgbe_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
4227 {
4228         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4229         uint64_t tx_tstamp_cycles;
4230
4231         /* TSTXSTMPL stores ns and TSTXSTMPH stores seconds. */
4232         tx_tstamp_cycles = (uint64_t)rd32(hw, TXGBE_TSTXSTMPL);
4233         tx_tstamp_cycles |= (uint64_t)rd32(hw, TXGBE_TSTXSTMPH) << 32;
4234
4235         return tx_tstamp_cycles;
4236 }
4237
4238 static void
4239 txgbe_start_timecounters(struct rte_eth_dev *dev)
4240 {
4241         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4242         struct txgbe_adapter *adapter = TXGBE_DEV_ADAPTER(dev);
4243         struct rte_eth_link link;
4244         uint32_t incval = 0;
4245         uint32_t shift = 0;
4246
4247         /* Get current link speed. */
4248         txgbe_dev_link_update(dev, 1);
4249         rte_eth_linkstatus_get(dev, &link);
4250
4251         switch (link.link_speed) {
4252         case ETH_SPEED_NUM_100M:
4253                 incval = TXGBE_INCVAL_100;
4254                 shift = TXGBE_INCVAL_SHIFT_100;
4255                 break;
4256         case ETH_SPEED_NUM_1G:
4257                 incval = TXGBE_INCVAL_1GB;
4258                 shift = TXGBE_INCVAL_SHIFT_1GB;
4259                 break;
4260         case ETH_SPEED_NUM_10G:
4261         default:
4262                 incval = TXGBE_INCVAL_10GB;
4263                 shift = TXGBE_INCVAL_SHIFT_10GB;
4264                 break;
4265         }
4266
4267         wr32(hw, TXGBE_TSTIMEINC, TXGBE_TSTIMEINC_VP(incval, 2));
4268
4269         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
4270         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
4271         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
4272
4273         adapter->systime_tc.cc_mask = TXGBE_CYCLECOUNTER_MASK;
4274         adapter->systime_tc.cc_shift = shift;
4275         adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
4276
4277         adapter->rx_tstamp_tc.cc_mask = TXGBE_CYCLECOUNTER_MASK;
4278         adapter->rx_tstamp_tc.cc_shift = shift;
4279         adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
4280
4281         adapter->tx_tstamp_tc.cc_mask = TXGBE_CYCLECOUNTER_MASK;
4282         adapter->tx_tstamp_tc.cc_shift = shift;
4283         adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
4284 }
4285
4286 static int
4287 txgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
4288 {
4289         struct txgbe_adapter *adapter = TXGBE_DEV_ADAPTER(dev);
4290
4291         adapter->systime_tc.nsec += delta;
4292         adapter->rx_tstamp_tc.nsec += delta;
4293         adapter->tx_tstamp_tc.nsec += delta;
4294
4295         return 0;
4296 }
4297
4298 static int
4299 txgbe_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
4300 {
4301         uint64_t ns;
4302         struct txgbe_adapter *adapter = TXGBE_DEV_ADAPTER(dev);
4303
4304         ns = rte_timespec_to_ns(ts);
4305         /* Set the timecounters to a new value. */
4306         adapter->systime_tc.nsec = ns;
4307         adapter->rx_tstamp_tc.nsec = ns;
4308         adapter->tx_tstamp_tc.nsec = ns;
4309
4310         return 0;
4311 }
4312
4313 static int
4314 txgbe_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
4315 {
4316         uint64_t ns, systime_cycles;
4317         struct txgbe_adapter *adapter = TXGBE_DEV_ADAPTER(dev);
4318
4319         systime_cycles = txgbe_read_systime_cyclecounter(dev);
4320         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
4321         *ts = rte_ns_to_timespec(ns);
4322
4323         return 0;
4324 }
4325
4326 static int
4327 txgbe_timesync_enable(struct rte_eth_dev *dev)
4328 {
4329         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4330         uint32_t tsync_ctl;
4331
4332         /* Stop the timesync system time. */
4333         wr32(hw, TXGBE_TSTIMEINC, 0x0);
4334         /* Reset the timesync system time value. */
4335         wr32(hw, TXGBE_TSTIMEL, 0x0);
4336         wr32(hw, TXGBE_TSTIMEH, 0x0);
4337
4338         txgbe_start_timecounters(dev);
4339
4340         /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
4341         wr32(hw, TXGBE_ETFLT(TXGBE_ETF_ID_1588),
4342                 RTE_ETHER_TYPE_1588 | TXGBE_ETFLT_ENA | TXGBE_ETFLT_1588);
4343
4344         /* Enable timestamping of received PTP packets. */
4345         tsync_ctl = rd32(hw, TXGBE_TSRXCTL);
4346         tsync_ctl |= TXGBE_TSRXCTL_ENA;
4347         wr32(hw, TXGBE_TSRXCTL, tsync_ctl);
4348
4349         /* Enable timestamping of transmitted PTP packets. */
4350         tsync_ctl = rd32(hw, TXGBE_TSTXCTL);
4351         tsync_ctl |= TXGBE_TSTXCTL_ENA;
4352         wr32(hw, TXGBE_TSTXCTL, tsync_ctl);
4353
4354         txgbe_flush(hw);
4355
4356         return 0;
4357 }
4358
4359 static int
4360 txgbe_timesync_disable(struct rte_eth_dev *dev)
4361 {
4362         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4363         uint32_t tsync_ctl;
4364
4365         /* Disable timestamping of transmitted PTP packets. */
4366         tsync_ctl = rd32(hw, TXGBE_TSTXCTL);
4367         tsync_ctl &= ~TXGBE_TSTXCTL_ENA;
4368         wr32(hw, TXGBE_TSTXCTL, tsync_ctl);
4369
4370         /* Disable timestamping of received PTP packets. */
4371         tsync_ctl = rd32(hw, TXGBE_TSRXCTL);
4372         tsync_ctl &= ~TXGBE_TSRXCTL_ENA;
4373         wr32(hw, TXGBE_TSRXCTL, tsync_ctl);
4374
4375         /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
4376         wr32(hw, TXGBE_ETFLT(TXGBE_ETF_ID_1588), 0);
4377
4378         /* Stop incrementating the System Time registers. */
4379         wr32(hw, TXGBE_TSTIMEINC, 0);
4380
4381         return 0;
4382 }
4383
4384 static int
4385 txgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
4386                                  struct timespec *timestamp,
4387                                  uint32_t flags __rte_unused)
4388 {
4389         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4390         struct txgbe_adapter *adapter = TXGBE_DEV_ADAPTER(dev);
4391         uint32_t tsync_rxctl;
4392         uint64_t rx_tstamp_cycles;
4393         uint64_t ns;
4394
4395         tsync_rxctl = rd32(hw, TXGBE_TSRXCTL);
4396         if ((tsync_rxctl & TXGBE_TSRXCTL_VLD) == 0)
4397                 return -EINVAL;
4398
4399         rx_tstamp_cycles = txgbe_read_rx_tstamp_cyclecounter(dev);
4400         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
4401         *timestamp = rte_ns_to_timespec(ns);
4402
4403         return  0;
4404 }
4405
4406 static int
4407 txgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
4408                                  struct timespec *timestamp)
4409 {
4410         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4411         struct txgbe_adapter *adapter = TXGBE_DEV_ADAPTER(dev);
4412         uint32_t tsync_txctl;
4413         uint64_t tx_tstamp_cycles;
4414         uint64_t ns;
4415
4416         tsync_txctl = rd32(hw, TXGBE_TSTXCTL);
4417         if ((tsync_txctl & TXGBE_TSTXCTL_VLD) == 0)
4418                 return -EINVAL;
4419
4420         tx_tstamp_cycles = txgbe_read_tx_tstamp_cyclecounter(dev);
4421         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
4422         *timestamp = rte_ns_to_timespec(ns);
4423
4424         return 0;
4425 }
4426
4427 static int
4428 txgbe_get_reg_length(struct rte_eth_dev *dev __rte_unused)
4429 {
4430         int count = 0;
4431         int g_ind = 0;
4432         const struct reg_info *reg_group;
4433         const struct reg_info **reg_set = txgbe_regs_others;
4434
4435         while ((reg_group = reg_set[g_ind++]))
4436                 count += txgbe_regs_group_count(reg_group);
4437
4438         return count;
4439 }
4440
4441 static int
4442 txgbe_get_regs(struct rte_eth_dev *dev,
4443               struct rte_dev_reg_info *regs)
4444 {
4445         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4446         uint32_t *data = regs->data;
4447         int g_ind = 0;
4448         int count = 0;
4449         const struct reg_info *reg_group;
4450         const struct reg_info **reg_set = txgbe_regs_others;
4451
4452         if (data == NULL) {
4453                 regs->length = txgbe_get_reg_length(dev);
4454                 regs->width = sizeof(uint32_t);
4455                 return 0;
4456         }
4457
4458         /* Support only full register dump */
4459         if (regs->length == 0 ||
4460             regs->length == (uint32_t)txgbe_get_reg_length(dev)) {
4461                 regs->version = hw->mac.type << 24 |
4462                                 hw->revision_id << 16 |
4463                                 hw->device_id;
4464                 while ((reg_group = reg_set[g_ind++]))
4465                         count += txgbe_read_regs_group(dev, &data[count],
4466                                                       reg_group);
4467                 return 0;
4468         }
4469
4470         return -ENOTSUP;
4471 }
4472
4473 static int
4474 txgbe_get_eeprom_length(struct rte_eth_dev *dev)
4475 {
4476         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4477
4478         /* Return unit is byte count */
4479         return hw->rom.word_size * 2;
4480 }
4481
4482 static int
4483 txgbe_get_eeprom(struct rte_eth_dev *dev,
4484                 struct rte_dev_eeprom_info *in_eeprom)
4485 {
4486         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4487         struct txgbe_rom_info *eeprom = &hw->rom;
4488         uint16_t *data = in_eeprom->data;
4489         int first, length;
4490
4491         first = in_eeprom->offset >> 1;
4492         length = in_eeprom->length >> 1;
4493         if (first > hw->rom.word_size ||
4494             ((first + length) > hw->rom.word_size))
4495                 return -EINVAL;
4496
4497         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
4498
4499         return eeprom->readw_buffer(hw, first, length, data);
4500 }
4501
4502 static int
4503 txgbe_set_eeprom(struct rte_eth_dev *dev,
4504                 struct rte_dev_eeprom_info *in_eeprom)
4505 {
4506         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4507         struct txgbe_rom_info *eeprom = &hw->rom;
4508         uint16_t *data = in_eeprom->data;
4509         int first, length;
4510
4511         first = in_eeprom->offset >> 1;
4512         length = in_eeprom->length >> 1;
4513         if (first > hw->rom.word_size ||
4514             ((first + length) > hw->rom.word_size))
4515                 return -EINVAL;
4516
4517         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
4518
4519         return eeprom->writew_buffer(hw,  first, length, data);
4520 }
4521
4522 static int
4523 txgbe_get_module_info(struct rte_eth_dev *dev,
4524                       struct rte_eth_dev_module_info *modinfo)
4525 {
4526         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4527         uint32_t status;
4528         uint8_t sff8472_rev, addr_mode;
4529         bool page_swap = false;
4530
4531         /* Check whether we support SFF-8472 or not */
4532         status = hw->phy.read_i2c_eeprom(hw,
4533                                              TXGBE_SFF_SFF_8472_COMP,
4534                                              &sff8472_rev);
4535         if (status != 0)
4536                 return -EIO;
4537
4538         /* addressing mode is not supported */
4539         status = hw->phy.read_i2c_eeprom(hw,
4540                                              TXGBE_SFF_SFF_8472_SWAP,
4541                                              &addr_mode);
4542         if (status != 0)
4543                 return -EIO;
4544
4545         if (addr_mode & TXGBE_SFF_ADDRESSING_MODE) {
4546                 PMD_DRV_LOG(ERR,
4547                             "Address change required to access page 0xA2, "
4548                             "but not supported. Please report the module "
4549                             "type to the driver maintainers.");
4550                 page_swap = true;
4551         }
4552
4553         if (sff8472_rev == TXGBE_SFF_SFF_8472_UNSUP || page_swap) {
4554                 /* We have a SFP, but it does not support SFF-8472 */
4555                 modinfo->type = RTE_ETH_MODULE_SFF_8079;
4556                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
4557         } else {
4558                 /* We have a SFP which supports a revision of SFF-8472. */
4559                 modinfo->type = RTE_ETH_MODULE_SFF_8472;
4560                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
4561         }
4562
4563         return 0;
4564 }
4565
4566 static int
4567 txgbe_get_module_eeprom(struct rte_eth_dev *dev,
4568                         struct rte_dev_eeprom_info *info)
4569 {
4570         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4571         uint32_t status = TXGBE_ERR_PHY_ADDR_INVALID;
4572         uint8_t databyte = 0xFF;
4573         uint8_t *data = info->data;
4574         uint32_t i = 0;
4575
4576         if (info->length == 0)
4577                 return -EINVAL;
4578
4579         for (i = info->offset; i < info->offset + info->length; i++) {
4580                 if (i < RTE_ETH_MODULE_SFF_8079_LEN)
4581                         status = hw->phy.read_i2c_eeprom(hw, i, &databyte);
4582                 else
4583                         status = hw->phy.read_i2c_sff8472(hw, i, &databyte);
4584
4585                 if (status != 0)
4586                         return -EIO;
4587
4588                 data[i - info->offset] = databyte;
4589         }
4590
4591         return 0;
4592 }
4593
4594 bool
4595 txgbe_rss_update_sp(enum txgbe_mac_type mac_type)
4596 {
4597         switch (mac_type) {
4598         case txgbe_mac_raptor:
4599         case txgbe_mac_raptor_vf:
4600                 return 1;
4601         default:
4602                 return 0;
4603         }
4604 }
4605
4606 static int
4607 txgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
4608                         struct rte_eth_dcb_info *dcb_info)
4609 {
4610         struct txgbe_dcb_config *dcb_config = TXGBE_DEV_DCB_CONFIG(dev);
4611         struct txgbe_dcb_tc_config *tc;
4612         struct rte_eth_dcb_tc_queue_mapping *tc_queue;
4613         uint8_t nb_tcs;
4614         uint8_t i, j;
4615
4616         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
4617                 dcb_info->nb_tcs = dcb_config->num_tcs.pg_tcs;
4618         else
4619                 dcb_info->nb_tcs = 1;
4620
4621         tc_queue = &dcb_info->tc_queue;
4622         nb_tcs = dcb_info->nb_tcs;
4623
4624         if (dcb_config->vt_mode) { /* vt is enabled */
4625                 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
4626                                 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
4627                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
4628                         dcb_info->prio_tc[i] = vmdq_rx_conf->dcb_tc[i];
4629                 if (RTE_ETH_DEV_SRIOV(dev).active > 0) {
4630                         for (j = 0; j < nb_tcs; j++) {
4631                                 tc_queue->tc_rxq[0][j].base = j;
4632                                 tc_queue->tc_rxq[0][j].nb_queue = 1;
4633                                 tc_queue->tc_txq[0][j].base = j;
4634                                 tc_queue->tc_txq[0][j].nb_queue = 1;
4635                         }
4636                 } else {
4637                         for (i = 0; i < vmdq_rx_conf->nb_queue_pools; i++) {
4638                                 for (j = 0; j < nb_tcs; j++) {
4639                                         tc_queue->tc_rxq[i][j].base =
4640                                                 i * nb_tcs + j;
4641                                         tc_queue->tc_rxq[i][j].nb_queue = 1;
4642                                         tc_queue->tc_txq[i][j].base =
4643                                                 i * nb_tcs + j;
4644                                         tc_queue->tc_txq[i][j].nb_queue = 1;
4645                                 }
4646                         }
4647                 }
4648         } else { /* vt is disabled */
4649                 struct rte_eth_dcb_rx_conf *rx_conf =
4650                                 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
4651                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
4652                         dcb_info->prio_tc[i] = rx_conf->dcb_tc[i];
4653                 if (dcb_info->nb_tcs == ETH_4_TCS) {
4654                         for (i = 0; i < dcb_info->nb_tcs; i++) {
4655                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 32;
4656                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
4657                         }
4658                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
4659                         dcb_info->tc_queue.tc_txq[0][1].base = 64;
4660                         dcb_info->tc_queue.tc_txq[0][2].base = 96;
4661                         dcb_info->tc_queue.tc_txq[0][3].base = 112;
4662                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 64;
4663                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
4664                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
4665                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
4666                 } else if (dcb_info->nb_tcs == ETH_8_TCS) {
4667                         for (i = 0; i < dcb_info->nb_tcs; i++) {
4668                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 16;
4669                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
4670                         }
4671                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
4672                         dcb_info->tc_queue.tc_txq[0][1].base = 32;
4673                         dcb_info->tc_queue.tc_txq[0][2].base = 64;
4674                         dcb_info->tc_queue.tc_txq[0][3].base = 80;
4675                         dcb_info->tc_queue.tc_txq[0][4].base = 96;
4676                         dcb_info->tc_queue.tc_txq[0][5].base = 104;
4677                         dcb_info->tc_queue.tc_txq[0][6].base = 112;
4678                         dcb_info->tc_queue.tc_txq[0][7].base = 120;
4679                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 32;
4680                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
4681                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
4682                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
4683                         dcb_info->tc_queue.tc_txq[0][4].nb_queue = 8;
4684                         dcb_info->tc_queue.tc_txq[0][5].nb_queue = 8;
4685                         dcb_info->tc_queue.tc_txq[0][6].nb_queue = 8;
4686                         dcb_info->tc_queue.tc_txq[0][7].nb_queue = 8;
4687                 }
4688         }
4689         for (i = 0; i < dcb_info->nb_tcs; i++) {
4690                 tc = &dcb_config->tc_config[i];
4691                 dcb_info->tc_bws[i] = tc->path[TXGBE_DCB_TX_CONFIG].bwg_percent;
4692         }
4693         return 0;
4694 }
4695
4696 /* Update e-tag ether type */
4697 static int
4698 txgbe_update_e_tag_eth_type(struct txgbe_hw *hw,
4699                             uint16_t ether_type)
4700 {
4701         uint32_t etag_etype;
4702
4703         etag_etype = rd32(hw, TXGBE_EXTAG);
4704         etag_etype &= ~TXGBE_EXTAG_ETAG_MASK;
4705         etag_etype |= ether_type;
4706         wr32(hw, TXGBE_EXTAG, etag_etype);
4707         txgbe_flush(hw);
4708
4709         return 0;
4710 }
4711
4712 /* Enable e-tag tunnel */
4713 static int
4714 txgbe_e_tag_enable(struct txgbe_hw *hw)
4715 {
4716         uint32_t etag_etype;
4717
4718         etag_etype = rd32(hw, TXGBE_PORTCTL);
4719         etag_etype |= TXGBE_PORTCTL_ETAG;
4720         wr32(hw, TXGBE_PORTCTL, etag_etype);
4721         txgbe_flush(hw);
4722
4723         return 0;
4724 }
4725
4726 static int
4727 txgbe_e_tag_filter_del(struct rte_eth_dev *dev,
4728                        struct txgbe_l2_tunnel_conf  *l2_tunnel)
4729 {
4730         int ret = 0;
4731         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4732         uint32_t i, rar_entries;
4733         uint32_t rar_low, rar_high;
4734
4735         rar_entries = hw->mac.num_rar_entries;
4736
4737         for (i = 1; i < rar_entries; i++) {
4738                 wr32(hw, TXGBE_ETHADDRIDX, i);
4739                 rar_high = rd32(hw, TXGBE_ETHADDRH);
4740                 rar_low  = rd32(hw, TXGBE_ETHADDRL);
4741                 if ((rar_high & TXGBE_ETHADDRH_VLD) &&
4742                     (rar_high & TXGBE_ETHADDRH_ETAG) &&
4743                     (TXGBE_ETHADDRL_ETAG(rar_low) ==
4744                      l2_tunnel->tunnel_id)) {
4745                         wr32(hw, TXGBE_ETHADDRL, 0);
4746                         wr32(hw, TXGBE_ETHADDRH, 0);
4747
4748                         txgbe_clear_vmdq(hw, i, BIT_MASK32);
4749
4750                         return ret;
4751                 }
4752         }
4753
4754         return ret;
4755 }
4756
4757 static int
4758 txgbe_e_tag_filter_add(struct rte_eth_dev *dev,
4759                        struct txgbe_l2_tunnel_conf *l2_tunnel)
4760 {
4761         int ret = 0;
4762         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4763         uint32_t i, rar_entries;
4764         uint32_t rar_low, rar_high;
4765
4766         /* One entry for one tunnel. Try to remove potential existing entry. */
4767         txgbe_e_tag_filter_del(dev, l2_tunnel);
4768
4769         rar_entries = hw->mac.num_rar_entries;
4770
4771         for (i = 1; i < rar_entries; i++) {
4772                 wr32(hw, TXGBE_ETHADDRIDX, i);
4773                 rar_high = rd32(hw, TXGBE_ETHADDRH);
4774                 if (rar_high & TXGBE_ETHADDRH_VLD) {
4775                         continue;
4776                 } else {
4777                         txgbe_set_vmdq(hw, i, l2_tunnel->pool);
4778                         rar_high = TXGBE_ETHADDRH_VLD | TXGBE_ETHADDRH_ETAG;
4779                         rar_low = l2_tunnel->tunnel_id;
4780
4781                         wr32(hw, TXGBE_ETHADDRL, rar_low);
4782                         wr32(hw, TXGBE_ETHADDRH, rar_high);
4783
4784                         return ret;
4785                 }
4786         }
4787
4788         PMD_INIT_LOG(NOTICE, "The table of E-tag forwarding rule is full."
4789                      " Please remove a rule before adding a new one.");
4790         return -EINVAL;
4791 }
4792
4793 static inline struct txgbe_l2_tn_filter *
4794 txgbe_l2_tn_filter_lookup(struct txgbe_l2_tn_info *l2_tn_info,
4795                           struct txgbe_l2_tn_key *key)
4796 {
4797         int ret;
4798
4799         ret = rte_hash_lookup(l2_tn_info->hash_handle, (const void *)key);
4800         if (ret < 0)
4801                 return NULL;
4802
4803         return l2_tn_info->hash_map[ret];
4804 }
4805
4806 static inline int
4807 txgbe_insert_l2_tn_filter(struct txgbe_l2_tn_info *l2_tn_info,
4808                           struct txgbe_l2_tn_filter *l2_tn_filter)
4809 {
4810         int ret;
4811
4812         ret = rte_hash_add_key(l2_tn_info->hash_handle,
4813                                &l2_tn_filter->key);
4814
4815         if (ret < 0) {
4816                 PMD_DRV_LOG(ERR,
4817                             "Failed to insert L2 tunnel filter"
4818                             " to hash table %d!",
4819                             ret);
4820                 return ret;
4821         }
4822
4823         l2_tn_info->hash_map[ret] = l2_tn_filter;
4824
4825         TAILQ_INSERT_TAIL(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
4826
4827         return 0;
4828 }
4829
4830 static inline int
4831 txgbe_remove_l2_tn_filter(struct txgbe_l2_tn_info *l2_tn_info,
4832                           struct txgbe_l2_tn_key *key)
4833 {
4834         int ret;
4835         struct txgbe_l2_tn_filter *l2_tn_filter;
4836
4837         ret = rte_hash_del_key(l2_tn_info->hash_handle, key);
4838
4839         if (ret < 0) {
4840                 PMD_DRV_LOG(ERR,
4841                             "No such L2 tunnel filter to delete %d!",
4842                             ret);
4843                 return ret;
4844         }
4845
4846         l2_tn_filter = l2_tn_info->hash_map[ret];
4847         l2_tn_info->hash_map[ret] = NULL;
4848
4849         TAILQ_REMOVE(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
4850         rte_free(l2_tn_filter);
4851
4852         return 0;
4853 }
4854
4855 /* Add l2 tunnel filter */
4856 int
4857 txgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev,
4858                                struct txgbe_l2_tunnel_conf *l2_tunnel,
4859                                bool restore)
4860 {
4861         int ret;
4862         struct txgbe_l2_tn_info *l2_tn_info = TXGBE_DEV_L2_TN(dev);
4863         struct txgbe_l2_tn_key key;
4864         struct txgbe_l2_tn_filter *node;
4865
4866         if (!restore) {
4867                 key.l2_tn_type = l2_tunnel->l2_tunnel_type;
4868                 key.tn_id = l2_tunnel->tunnel_id;
4869
4870                 node = txgbe_l2_tn_filter_lookup(l2_tn_info, &key);
4871
4872                 if (node) {
4873                         PMD_DRV_LOG(ERR,
4874                                     "The L2 tunnel filter already exists!");
4875                         return -EINVAL;
4876                 }
4877
4878                 node = rte_zmalloc("txgbe_l2_tn",
4879                                    sizeof(struct txgbe_l2_tn_filter),
4880                                    0);
4881                 if (!node)
4882                         return -ENOMEM;
4883
4884                 rte_memcpy(&node->key,
4885                                  &key,
4886                                  sizeof(struct txgbe_l2_tn_key));
4887                 node->pool = l2_tunnel->pool;
4888                 ret = txgbe_insert_l2_tn_filter(l2_tn_info, node);
4889                 if (ret < 0) {
4890                         rte_free(node);
4891                         return ret;
4892                 }
4893         }
4894
4895         switch (l2_tunnel->l2_tunnel_type) {
4896         case RTE_L2_TUNNEL_TYPE_E_TAG:
4897                 ret = txgbe_e_tag_filter_add(dev, l2_tunnel);
4898                 break;
4899         default:
4900                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
4901                 ret = -EINVAL;
4902                 break;
4903         }
4904
4905         if (!restore && ret < 0)
4906                 (void)txgbe_remove_l2_tn_filter(l2_tn_info, &key);
4907
4908         return ret;
4909 }
4910
4911 /* Delete l2 tunnel filter */
4912 int
4913 txgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev,
4914                                struct txgbe_l2_tunnel_conf *l2_tunnel)
4915 {
4916         int ret;
4917         struct txgbe_l2_tn_info *l2_tn_info = TXGBE_DEV_L2_TN(dev);
4918         struct txgbe_l2_tn_key key;
4919
4920         key.l2_tn_type = l2_tunnel->l2_tunnel_type;
4921         key.tn_id = l2_tunnel->tunnel_id;
4922         ret = txgbe_remove_l2_tn_filter(l2_tn_info, &key);
4923         if (ret < 0)
4924                 return ret;
4925
4926         switch (l2_tunnel->l2_tunnel_type) {
4927         case RTE_L2_TUNNEL_TYPE_E_TAG:
4928                 ret = txgbe_e_tag_filter_del(dev, l2_tunnel);
4929                 break;
4930         default:
4931                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
4932                 ret = -EINVAL;
4933                 break;
4934         }
4935
4936         return ret;
4937 }
4938
4939 static int
4940 txgbe_e_tag_forwarding_en_dis(struct rte_eth_dev *dev, bool en)
4941 {
4942         int ret = 0;
4943         uint32_t ctrl;
4944         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4945
4946         ctrl = rd32(hw, TXGBE_POOLCTL);
4947         ctrl &= ~TXGBE_POOLCTL_MODE_MASK;
4948         if (en)
4949                 ctrl |= TXGBE_PSRPOOL_MODE_ETAG;
4950         wr32(hw, TXGBE_POOLCTL, ctrl);
4951
4952         return ret;
4953 }
4954
4955 /* Add UDP tunneling port */
4956 static int
4957 txgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
4958                               struct rte_eth_udp_tunnel *udp_tunnel)
4959 {
4960         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4961         int ret = 0;
4962
4963         if (udp_tunnel == NULL)
4964                 return -EINVAL;
4965
4966         switch (udp_tunnel->prot_type) {
4967         case RTE_TUNNEL_TYPE_VXLAN:
4968                 if (udp_tunnel->udp_port == 0) {
4969                         PMD_DRV_LOG(ERR, "Add VxLAN port 0 is not allowed.");
4970                         ret = -EINVAL;
4971                         break;
4972                 }
4973                 wr32(hw, TXGBE_VXLANPORT, udp_tunnel->udp_port);
4974                 break;
4975         case RTE_TUNNEL_TYPE_GENEVE:
4976                 if (udp_tunnel->udp_port == 0) {
4977                         PMD_DRV_LOG(ERR, "Add Geneve port 0 is not allowed.");
4978                         ret = -EINVAL;
4979                         break;
4980                 }
4981                 wr32(hw, TXGBE_GENEVEPORT, udp_tunnel->udp_port);
4982                 break;
4983         case RTE_TUNNEL_TYPE_TEREDO:
4984                 if (udp_tunnel->udp_port == 0) {
4985                         PMD_DRV_LOG(ERR, "Add Teredo port 0 is not allowed.");
4986                         ret = -EINVAL;
4987                         break;
4988                 }
4989                 wr32(hw, TXGBE_TEREDOPORT, udp_tunnel->udp_port);
4990                 break;
4991         case RTE_TUNNEL_TYPE_VXLAN_GPE:
4992                 if (udp_tunnel->udp_port == 0) {
4993                         PMD_DRV_LOG(ERR, "Add VxLAN port 0 is not allowed.");
4994                         ret = -EINVAL;
4995                         break;
4996                 }
4997                 wr32(hw, TXGBE_VXLANPORTGPE, udp_tunnel->udp_port);
4998                 break;
4999         default:
5000                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
5001                 ret = -EINVAL;
5002                 break;
5003         }
5004
5005         txgbe_flush(hw);
5006
5007         return ret;
5008 }
5009
5010 /* Remove UDP tunneling port */
5011 static int
5012 txgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
5013                               struct rte_eth_udp_tunnel *udp_tunnel)
5014 {
5015         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
5016         int ret = 0;
5017         uint16_t cur_port;
5018
5019         if (udp_tunnel == NULL)
5020                 return -EINVAL;
5021
5022         switch (udp_tunnel->prot_type) {
5023         case RTE_TUNNEL_TYPE_VXLAN:
5024                 cur_port = (uint16_t)rd32(hw, TXGBE_VXLANPORT);
5025                 if (cur_port != udp_tunnel->udp_port) {
5026                         PMD_DRV_LOG(ERR, "Port %u does not exist.",
5027                                         udp_tunnel->udp_port);
5028                         ret = -EINVAL;
5029                         break;
5030                 }
5031                 wr32(hw, TXGBE_VXLANPORT, 0);
5032                 break;
5033         case RTE_TUNNEL_TYPE_GENEVE:
5034                 cur_port = (uint16_t)rd32(hw, TXGBE_GENEVEPORT);
5035                 if (cur_port != udp_tunnel->udp_port) {
5036                         PMD_DRV_LOG(ERR, "Port %u does not exist.",
5037                                         udp_tunnel->udp_port);
5038                         ret = -EINVAL;
5039                         break;
5040                 }
5041                 wr32(hw, TXGBE_GENEVEPORT, 0);
5042                 break;
5043         case RTE_TUNNEL_TYPE_TEREDO:
5044                 cur_port = (uint16_t)rd32(hw, TXGBE_TEREDOPORT);
5045                 if (cur_port != udp_tunnel->udp_port) {
5046                         PMD_DRV_LOG(ERR, "Port %u does not exist.",
5047                                         udp_tunnel->udp_port);
5048                         ret = -EINVAL;
5049                         break;
5050                 }
5051                 wr32(hw, TXGBE_TEREDOPORT, 0);
5052                 break;
5053         case RTE_TUNNEL_TYPE_VXLAN_GPE:
5054                 cur_port = (uint16_t)rd32(hw, TXGBE_VXLANPORTGPE);
5055                 if (cur_port != udp_tunnel->udp_port) {
5056                         PMD_DRV_LOG(ERR, "Port %u does not exist.",
5057                                         udp_tunnel->udp_port);
5058                         ret = -EINVAL;
5059                         break;
5060                 }
5061                 wr32(hw, TXGBE_VXLANPORTGPE, 0);
5062                 break;
5063         default:
5064                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
5065                 ret = -EINVAL;
5066                 break;
5067         }
5068
5069         txgbe_flush(hw);
5070
5071         return ret;
5072 }
5073
5074 /* restore n-tuple filter */
5075 static inline void
5076 txgbe_ntuple_filter_restore(struct rte_eth_dev *dev)
5077 {
5078         struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(dev);
5079         struct txgbe_5tuple_filter *node;
5080
5081         TAILQ_FOREACH(node, &filter_info->fivetuple_list, entries) {
5082                 txgbe_inject_5tuple_filter(dev, node);
5083         }
5084 }
5085
5086 /* restore ethernet type filter */
5087 static inline void
5088 txgbe_ethertype_filter_restore(struct rte_eth_dev *dev)
5089 {
5090         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
5091         struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(dev);
5092         int i;
5093
5094         for (i = 0; i < TXGBE_ETF_ID_MAX; i++) {
5095                 if (filter_info->ethertype_mask & (1 << i)) {
5096                         wr32(hw, TXGBE_ETFLT(i),
5097                                         filter_info->ethertype_filters[i].etqf);
5098                         wr32(hw, TXGBE_ETCLS(i),
5099                                         filter_info->ethertype_filters[i].etqs);
5100                         txgbe_flush(hw);
5101                 }
5102         }
5103 }
5104
5105 /* restore SYN filter */
5106 static inline void
5107 txgbe_syn_filter_restore(struct rte_eth_dev *dev)
5108 {
5109         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
5110         struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(dev);
5111         uint32_t synqf;
5112
5113         synqf = filter_info->syn_info;
5114
5115         if (synqf & TXGBE_SYNCLS_ENA) {
5116                 wr32(hw, TXGBE_SYNCLS, synqf);
5117                 txgbe_flush(hw);
5118         }
5119 }
5120
5121 /* restore L2 tunnel filter */
5122 static inline void
5123 txgbe_l2_tn_filter_restore(struct rte_eth_dev *dev)
5124 {
5125         struct txgbe_l2_tn_info *l2_tn_info = TXGBE_DEV_L2_TN(dev);
5126         struct txgbe_l2_tn_filter *node;
5127         struct txgbe_l2_tunnel_conf l2_tn_conf;
5128
5129         TAILQ_FOREACH(node, &l2_tn_info->l2_tn_list, entries) {
5130                 l2_tn_conf.l2_tunnel_type = node->key.l2_tn_type;
5131                 l2_tn_conf.tunnel_id      = node->key.tn_id;
5132                 l2_tn_conf.pool           = node->pool;
5133                 (void)txgbe_dev_l2_tunnel_filter_add(dev, &l2_tn_conf, TRUE);
5134         }
5135 }
5136
5137 /* restore rss filter */
5138 static inline void
5139 txgbe_rss_filter_restore(struct rte_eth_dev *dev)
5140 {
5141         struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(dev);
5142
5143         if (filter_info->rss_info.conf.queue_num)
5144                 txgbe_config_rss_filter(dev,
5145                         &filter_info->rss_info, TRUE);
5146 }
5147
5148 static int
5149 txgbe_filter_restore(struct rte_eth_dev *dev)
5150 {
5151         txgbe_ntuple_filter_restore(dev);
5152         txgbe_ethertype_filter_restore(dev);
5153         txgbe_syn_filter_restore(dev);
5154         txgbe_fdir_filter_restore(dev);
5155         txgbe_l2_tn_filter_restore(dev);
5156         txgbe_rss_filter_restore(dev);
5157
5158         return 0;
5159 }
5160
5161 static void
5162 txgbe_l2_tunnel_conf(struct rte_eth_dev *dev)
5163 {
5164         struct txgbe_l2_tn_info *l2_tn_info = TXGBE_DEV_L2_TN(dev);
5165         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
5166
5167         if (l2_tn_info->e_tag_en)
5168                 (void)txgbe_e_tag_enable(hw);
5169
5170         if (l2_tn_info->e_tag_fwd_en)
5171                 (void)txgbe_e_tag_forwarding_en_dis(dev, 1);
5172
5173         (void)txgbe_update_e_tag_eth_type(hw, l2_tn_info->e_tag_ether_type);
5174 }
5175
5176 /* remove all the n-tuple filters */
5177 void
5178 txgbe_clear_all_ntuple_filter(struct rte_eth_dev *dev)
5179 {
5180         struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(dev);
5181         struct txgbe_5tuple_filter *p_5tuple;
5182
5183         while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list)))
5184                 txgbe_remove_5tuple_filter(dev, p_5tuple);
5185 }
5186
5187 /* remove all the ether type filters */
5188 void
5189 txgbe_clear_all_ethertype_filter(struct rte_eth_dev *dev)
5190 {
5191         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
5192         struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(dev);
5193         int i;
5194
5195         for (i = 0; i < TXGBE_ETF_ID_MAX; i++) {
5196                 if (filter_info->ethertype_mask & (1 << i) &&
5197                     !filter_info->ethertype_filters[i].conf) {
5198                         (void)txgbe_ethertype_filter_remove(filter_info,
5199                                                             (uint8_t)i);
5200                         wr32(hw, TXGBE_ETFLT(i), 0);
5201                         wr32(hw, TXGBE_ETCLS(i), 0);
5202                         txgbe_flush(hw);
5203                 }
5204         }
5205 }
5206
5207 /* remove the SYN filter */
5208 void
5209 txgbe_clear_syn_filter(struct rte_eth_dev *dev)
5210 {
5211         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
5212         struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(dev);
5213
5214         if (filter_info->syn_info & TXGBE_SYNCLS_ENA) {
5215                 filter_info->syn_info = 0;
5216
5217                 wr32(hw, TXGBE_SYNCLS, 0);
5218                 txgbe_flush(hw);
5219         }
5220 }
5221
5222 /* remove all the L2 tunnel filters */
5223 int
5224 txgbe_clear_all_l2_tn_filter(struct rte_eth_dev *dev)
5225 {
5226         struct txgbe_l2_tn_info *l2_tn_info = TXGBE_DEV_L2_TN(dev);
5227         struct txgbe_l2_tn_filter *l2_tn_filter;
5228         struct txgbe_l2_tunnel_conf l2_tn_conf;
5229         int ret = 0;
5230
5231         while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
5232                 l2_tn_conf.l2_tunnel_type = l2_tn_filter->key.l2_tn_type;
5233                 l2_tn_conf.tunnel_id      = l2_tn_filter->key.tn_id;
5234                 l2_tn_conf.pool           = l2_tn_filter->pool;
5235                 ret = txgbe_dev_l2_tunnel_filter_del(dev, &l2_tn_conf);
5236                 if (ret < 0)
5237                         return ret;
5238         }
5239
5240         return 0;
5241 }
5242
5243 static const struct eth_dev_ops txgbe_eth_dev_ops = {
5244         .dev_configure              = txgbe_dev_configure,
5245         .dev_infos_get              = txgbe_dev_info_get,
5246         .dev_start                  = txgbe_dev_start,
5247         .dev_stop                   = txgbe_dev_stop,
5248         .dev_set_link_up            = txgbe_dev_set_link_up,
5249         .dev_set_link_down          = txgbe_dev_set_link_down,
5250         .dev_close                  = txgbe_dev_close,
5251         .dev_reset                  = txgbe_dev_reset,
5252         .promiscuous_enable         = txgbe_dev_promiscuous_enable,
5253         .promiscuous_disable        = txgbe_dev_promiscuous_disable,
5254         .allmulticast_enable        = txgbe_dev_allmulticast_enable,
5255         .allmulticast_disable       = txgbe_dev_allmulticast_disable,
5256         .link_update                = txgbe_dev_link_update,
5257         .stats_get                  = txgbe_dev_stats_get,
5258         .xstats_get                 = txgbe_dev_xstats_get,
5259         .xstats_get_by_id           = txgbe_dev_xstats_get_by_id,
5260         .stats_reset                = txgbe_dev_stats_reset,
5261         .xstats_reset               = txgbe_dev_xstats_reset,
5262         .xstats_get_names           = txgbe_dev_xstats_get_names,
5263         .xstats_get_names_by_id     = txgbe_dev_xstats_get_names_by_id,
5264         .queue_stats_mapping_set    = txgbe_dev_queue_stats_mapping_set,
5265         .fw_version_get             = txgbe_fw_version_get,
5266         .dev_supported_ptypes_get   = txgbe_dev_supported_ptypes_get,
5267         .mtu_set                    = txgbe_dev_mtu_set,
5268         .vlan_filter_set            = txgbe_vlan_filter_set,
5269         .vlan_tpid_set              = txgbe_vlan_tpid_set,
5270         .vlan_offload_set           = txgbe_vlan_offload_set,
5271         .vlan_strip_queue_set       = txgbe_vlan_strip_queue_set,
5272         .rx_queue_start             = txgbe_dev_rx_queue_start,
5273         .rx_queue_stop              = txgbe_dev_rx_queue_stop,
5274         .tx_queue_start             = txgbe_dev_tx_queue_start,
5275         .tx_queue_stop              = txgbe_dev_tx_queue_stop,
5276         .rx_queue_setup             = txgbe_dev_rx_queue_setup,
5277         .rx_queue_intr_enable       = txgbe_dev_rx_queue_intr_enable,
5278         .rx_queue_intr_disable      = txgbe_dev_rx_queue_intr_disable,
5279         .rx_queue_release           = txgbe_dev_rx_queue_release,
5280         .tx_queue_setup             = txgbe_dev_tx_queue_setup,
5281         .tx_queue_release           = txgbe_dev_tx_queue_release,
5282         .dev_led_on                 = txgbe_dev_led_on,
5283         .dev_led_off                = txgbe_dev_led_off,
5284         .flow_ctrl_get              = txgbe_flow_ctrl_get,
5285         .flow_ctrl_set              = txgbe_flow_ctrl_set,
5286         .priority_flow_ctrl_set     = txgbe_priority_flow_ctrl_set,
5287         .mac_addr_add               = txgbe_add_rar,
5288         .mac_addr_remove            = txgbe_remove_rar,
5289         .mac_addr_set               = txgbe_set_default_mac_addr,
5290         .uc_hash_table_set          = txgbe_uc_hash_table_set,
5291         .uc_all_hash_table_set      = txgbe_uc_all_hash_table_set,
5292         .set_queue_rate_limit       = txgbe_set_queue_rate_limit,
5293         .reta_update                = txgbe_dev_rss_reta_update,
5294         .reta_query                 = txgbe_dev_rss_reta_query,
5295         .rss_hash_update            = txgbe_dev_rss_hash_update,
5296         .rss_hash_conf_get          = txgbe_dev_rss_hash_conf_get,
5297         .flow_ops_get               = txgbe_dev_flow_ops_get,
5298         .set_mc_addr_list           = txgbe_dev_set_mc_addr_list,
5299         .rxq_info_get               = txgbe_rxq_info_get,
5300         .txq_info_get               = txgbe_txq_info_get,
5301         .timesync_enable            = txgbe_timesync_enable,
5302         .timesync_disable           = txgbe_timesync_disable,
5303         .timesync_read_rx_timestamp = txgbe_timesync_read_rx_timestamp,
5304         .timesync_read_tx_timestamp = txgbe_timesync_read_tx_timestamp,
5305         .get_reg                    = txgbe_get_regs,
5306         .get_eeprom_length          = txgbe_get_eeprom_length,
5307         .get_eeprom                 = txgbe_get_eeprom,
5308         .set_eeprom                 = txgbe_set_eeprom,
5309         .get_module_info            = txgbe_get_module_info,
5310         .get_module_eeprom          = txgbe_get_module_eeprom,
5311         .get_dcb_info               = txgbe_dev_get_dcb_info,
5312         .timesync_adjust_time       = txgbe_timesync_adjust_time,
5313         .timesync_read_time         = txgbe_timesync_read_time,
5314         .timesync_write_time        = txgbe_timesync_write_time,
5315         .udp_tunnel_port_add        = txgbe_dev_udp_tunnel_port_add,
5316         .udp_tunnel_port_del        = txgbe_dev_udp_tunnel_port_del,
5317         .tm_ops_get                 = txgbe_tm_ops_get,
5318         .tx_done_cleanup            = txgbe_dev_tx_done_cleanup,
5319 };
5320
5321 RTE_PMD_REGISTER_PCI(net_txgbe, rte_txgbe_pmd);
5322 RTE_PMD_REGISTER_PCI_TABLE(net_txgbe, pci_id_txgbe_map);
5323 RTE_PMD_REGISTER_KMOD_DEP(net_txgbe, "* igb_uio | uio_pci_generic | vfio-pci");
5324 RTE_PMD_REGISTER_PARAM_STRING(net_txgbe,
5325                               TXGBE_DEVARG_BP_AUTO "=<0|1>"
5326                               TXGBE_DEVARG_KR_POLL "=<0|1>"
5327                               TXGBE_DEVARG_KR_PRESENT "=<0|1>"
5328                               TXGBE_DEVARG_KX_SGMII "=<0|1>"
5329                               TXGBE_DEVARG_FFE_SET "=<0-4>"
5330                               TXGBE_DEVARG_FFE_MAIN "=<uint16>"
5331                               TXGBE_DEVARG_FFE_PRE "=<uint16>"
5332                               TXGBE_DEVARG_FFE_POST "=<uint16>");
5333
5334 RTE_LOG_REGISTER(txgbe_logtype_init, pmd.net.txgbe.init, NOTICE);
5335 RTE_LOG_REGISTER(txgbe_logtype_driver, pmd.net.txgbe.driver, NOTICE);
5336 RTE_LOG_REGISTER(txgbe_logtype_bp, pmd.net.txgbe.bp, NOTICE);
5337
5338 #ifdef RTE_LIBRTE_TXGBE_DEBUG_RX
5339         RTE_LOG_REGISTER(txgbe_logtype_rx, pmd.net.txgbe.rx, DEBUG);
5340 #endif
5341 #ifdef RTE_LIBRTE_TXGBE_DEBUG_TX
5342         RTE_LOG_REGISTER(txgbe_logtype_tx, pmd.net.txgbe.tx, DEBUG);
5343 #endif
5344
5345 #ifdef RTE_LIBRTE_TXGBE_DEBUG_TX_FREE
5346         RTE_LOG_REGISTER(txgbe_logtype_tx_free, pmd.net.txgbe.tx_free, DEBUG);
5347 #endif