drivers/net/txgbe/txgbe_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2015-2020 Beijing WangXun Technology Co., Ltd.
   3  * Copyright(c) 2010-2017 Intel Corporation
   4  */
   5
   6 #include <stdio.h>
   7 #include <errno.h>
   8 #include <stdint.h>
   9 #include <string.h>
  10 #include <rte_common.h>
  11 #include <ethdev_pci.h>
  12
  13 #include <rte_interrupts.h>
  14 #include <rte_log.h>
  15 #include <rte_debug.h>
  16 #include <rte_pci.h>
  17 #include <rte_memory.h>
  18 #include <rte_eal.h>
  19 #include <rte_alarm.h>
  20 #include <rte_kvargs.h>
  21
  22 #include "txgbe_logs.h"
  23 #include "base/txgbe.h"
  24 #include "txgbe_ethdev.h"
  25 #include "txgbe_rxtx.h"
  26 #include "txgbe_regs_group.h"
  27
  28 static const struct reg_info txgbe_regs_general[] = {
  29         {TXGBE_RST, 1, 1, "TXGBE_RST"},
  30         {TXGBE_STAT, 1, 1, "TXGBE_STAT"},
  31         {TXGBE_PORTCTL, 1, 1, "TXGBE_PORTCTL"},
  32         {TXGBE_SDP, 1, 1, "TXGBE_SDP"},
  33         {TXGBE_SDPCTL, 1, 1, "TXGBE_SDPCTL"},
  34         {TXGBE_LEDCTL, 1, 1, "TXGBE_LEDCTL"},
  35         {0, 0, 0, ""}
  36 };
  37
  38 static const struct reg_info txgbe_regs_nvm[] = {
  39         {0, 0, 0, ""}
  40 };
  41
  42 static const struct reg_info txgbe_regs_interrupt[] = {
  43         {0, 0, 0, ""}
  44 };
  45
  46 static const struct reg_info txgbe_regs_fctl_others[] = {
  47         {0, 0, 0, ""}
  48 };
  49
  50 static const struct reg_info txgbe_regs_rxdma[] = {
  51         {0, 0, 0, ""}
  52 };
  53
  54 static const struct reg_info txgbe_regs_rx[] = {
  55         {0, 0, 0, ""}
  56 };
  57
  58 static struct reg_info txgbe_regs_tx[] = {
  59         {0, 0, 0, ""}
  60 };
  61
  62 static const struct reg_info txgbe_regs_wakeup[] = {
  63         {0, 0, 0, ""}
  64 };
  65
  66 static const struct reg_info txgbe_regs_dcb[] = {
  67         {0, 0, 0, ""}
  68 };
  69
  70 static const struct reg_info txgbe_regs_mac[] = {
  71         {0, 0, 0, ""}
  72 };
  73
  74 static const struct reg_info txgbe_regs_diagnostic[] = {
  75         {0, 0, 0, ""},
  76 };
  77
  78 /* PF registers */
  79 static const struct reg_info *txgbe_regs_others[] = {
  80                                 txgbe_regs_general,
  81                                 txgbe_regs_nvm,
  82                                 txgbe_regs_interrupt,
  83                                 txgbe_regs_fctl_others,
  84                                 txgbe_regs_rxdma,
  85                                 txgbe_regs_rx,
  86                                 txgbe_regs_tx,
  87                                 txgbe_regs_wakeup,
  88                                 txgbe_regs_dcb,
  89                                 txgbe_regs_mac,
  90                                 txgbe_regs_diagnostic,
  91                                 NULL};
  92
  93 static int txgbe_fdir_filter_init(struct rte_eth_dev *eth_dev);
  94 static int txgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev);
  95 static int txgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev);
  96 static int txgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev);
  97 static int  txgbe_dev_set_link_up(struct rte_eth_dev *dev);
  98 static int  txgbe_dev_set_link_down(struct rte_eth_dev *dev);
  99 static int txgbe_dev_close(struct rte_eth_dev *dev);
 100 static int txgbe_dev_link_update(struct rte_eth_dev *dev,
 101                                 int wait_to_complete);
 102 static int txgbe_dev_stats_reset(struct rte_eth_dev *dev);
 103 static void txgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
 104 static void txgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev,
 105                                         uint16_t queue);
 106
 107 static void txgbe_dev_link_status_print(struct rte_eth_dev *dev);
 108 static int txgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on);
 109 static int txgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev);
 110 static int txgbe_dev_misc_interrupt_setup(struct rte_eth_dev *dev);
 111 static int txgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
 112 static int txgbe_dev_interrupt_get_status(struct rte_eth_dev *dev,
 113                                       struct rte_intr_handle *handle);
 114 static int txgbe_dev_interrupt_action(struct rte_eth_dev *dev,
 115                                       struct rte_intr_handle *handle);
 116 static void txgbe_dev_interrupt_handler(void *param);
 117 static void txgbe_dev_interrupt_delayed_handler(void *param);
 118 static void txgbe_configure_msix(struct rte_eth_dev *dev);
 119
 120 static int txgbe_filter_restore(struct rte_eth_dev *dev);
 121 static void txgbe_l2_tunnel_conf(struct rte_eth_dev *dev);
 122
 123 #define TXGBE_SET_HWSTRIP(h, q) do {\
 124                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 125                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 126                 (h)->bitmap[idx] |= 1 << bit;\
 127         } while (0)
 128
 129 #define TXGBE_CLEAR_HWSTRIP(h, q) do {\
 130                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 131                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 132                 (h)->bitmap[idx] &= ~(1 << bit);\
 133         } while (0)
 134
 135 #define TXGBE_GET_HWSTRIP(h, q, r) do {\
 136                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 137                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 138                 (r) = (h)->bitmap[idx] >> bit & 1;\
 139         } while (0)
 140
 141 /*
 142  * The set of PCI devices this driver supports
 143  */
 144 static const struct rte_pci_id pci_id_txgbe_map[] = {
 145         { RTE_PCI_DEVICE(PCI_VENDOR_ID_WANGXUN, TXGBE_DEV_ID_SP1000) },
 146         { RTE_PCI_DEVICE(PCI_VENDOR_ID_WANGXUN, TXGBE_DEV_ID_WX1820) },
 147         { .vendor_id = 0, /* sentinel */ },
 148 };
 149
 150 static const struct rte_eth_desc_lim rx_desc_lim = {
 151         .nb_max = TXGBE_RING_DESC_MAX,
 152         .nb_min = TXGBE_RING_DESC_MIN,
 153         .nb_align = TXGBE_RXD_ALIGN,
 154 };
 155
 156 static const struct rte_eth_desc_lim tx_desc_lim = {
 157         .nb_max = TXGBE_RING_DESC_MAX,
 158         .nb_min = TXGBE_RING_DESC_MIN,
 159         .nb_align = TXGBE_TXD_ALIGN,
 160         .nb_seg_max = TXGBE_TX_MAX_SEG,
 161         .nb_mtu_seg_max = TXGBE_TX_MAX_SEG,
 162 };
 163
 164 static const struct eth_dev_ops txgbe_eth_dev_ops;
 165
 166 #define HW_XSTAT(m) {#m, offsetof(struct txgbe_hw_stats, m)}
 167 #define HW_XSTAT_NAME(m, n) {n, offsetof(struct txgbe_hw_stats, m)}
 168 static const struct rte_txgbe_xstats_name_off rte_txgbe_stats_strings[] = {
 169         /* MNG RxTx */
 170         HW_XSTAT(mng_bmc2host_packets),
 171         HW_XSTAT(mng_host2bmc_packets),
 172         /* Basic RxTx */
 173         HW_XSTAT(rx_packets),
 174         HW_XSTAT(tx_packets),
 175         HW_XSTAT(rx_bytes),
 176         HW_XSTAT(tx_bytes),
 177         HW_XSTAT(rx_total_bytes),
 178         HW_XSTAT(rx_total_packets),
 179         HW_XSTAT(tx_total_packets),
 180         HW_XSTAT(rx_total_missed_packets),
 181         HW_XSTAT(rx_broadcast_packets),
 182         HW_XSTAT(rx_multicast_packets),
 183         HW_XSTAT(rx_management_packets),
 184         HW_XSTAT(tx_management_packets),
 185         HW_XSTAT(rx_management_dropped),
 186
 187         /* Basic Error */
 188         HW_XSTAT(rx_crc_errors),
 189         HW_XSTAT(rx_illegal_byte_errors),
 190         HW_XSTAT(rx_error_bytes),
 191         HW_XSTAT(rx_mac_short_packet_dropped),
 192         HW_XSTAT(rx_length_errors),
 193         HW_XSTAT(rx_undersize_errors),
 194         HW_XSTAT(rx_fragment_errors),
 195         HW_XSTAT(rx_oversize_errors),
 196         HW_XSTAT(rx_jabber_errors),
 197         HW_XSTAT(rx_l3_l4_xsum_error),
 198         HW_XSTAT(mac_local_errors),
 199         HW_XSTAT(mac_remote_errors),
 200
 201         /* Flow Director */
 202         HW_XSTAT(flow_director_added_filters),
 203         HW_XSTAT(flow_director_removed_filters),
 204         HW_XSTAT(flow_director_filter_add_errors),
 205         HW_XSTAT(flow_director_filter_remove_errors),
 206         HW_XSTAT(flow_director_matched_filters),
 207         HW_XSTAT(flow_director_missed_filters),
 208
 209         /* FCoE */
 210         HW_XSTAT(rx_fcoe_crc_errors),
 211         HW_XSTAT(rx_fcoe_mbuf_allocation_errors),
 212         HW_XSTAT(rx_fcoe_dropped),
 213         HW_XSTAT(rx_fcoe_packets),
 214         HW_XSTAT(tx_fcoe_packets),
 215         HW_XSTAT(rx_fcoe_bytes),
 216         HW_XSTAT(tx_fcoe_bytes),
 217         HW_XSTAT(rx_fcoe_no_ddp),
 218         HW_XSTAT(rx_fcoe_no_ddp_ext_buff),
 219
 220         /* MACSEC */
 221         HW_XSTAT(tx_macsec_pkts_untagged),
 222         HW_XSTAT(tx_macsec_pkts_encrypted),
 223         HW_XSTAT(tx_macsec_pkts_protected),
 224         HW_XSTAT(tx_macsec_octets_encrypted),
 225         HW_XSTAT(tx_macsec_octets_protected),
 226         HW_XSTAT(rx_macsec_pkts_untagged),
 227         HW_XSTAT(rx_macsec_pkts_badtag),
 228         HW_XSTAT(rx_macsec_pkts_nosci),
 229         HW_XSTAT(rx_macsec_pkts_unknownsci),
 230         HW_XSTAT(rx_macsec_octets_decrypted),
 231         HW_XSTAT(rx_macsec_octets_validated),
 232         HW_XSTAT(rx_macsec_sc_pkts_unchecked),
 233         HW_XSTAT(rx_macsec_sc_pkts_delayed),
 234         HW_XSTAT(rx_macsec_sc_pkts_late),
 235         HW_XSTAT(rx_macsec_sa_pkts_ok),
 236         HW_XSTAT(rx_macsec_sa_pkts_invalid),
 237         HW_XSTAT(rx_macsec_sa_pkts_notvalid),
 238         HW_XSTAT(rx_macsec_sa_pkts_unusedsa),
 239         HW_XSTAT(rx_macsec_sa_pkts_notusingsa),
 240
 241         /* MAC RxTx */
 242         HW_XSTAT(rx_size_64_packets),
 243         HW_XSTAT(rx_size_65_to_127_packets),
 244         HW_XSTAT(rx_size_128_to_255_packets),
 245         HW_XSTAT(rx_size_256_to_511_packets),
 246         HW_XSTAT(rx_size_512_to_1023_packets),
 247         HW_XSTAT(rx_size_1024_to_max_packets),
 248         HW_XSTAT(tx_size_64_packets),
 249         HW_XSTAT(tx_size_65_to_127_packets),
 250         HW_XSTAT(tx_size_128_to_255_packets),
 251         HW_XSTAT(tx_size_256_to_511_packets),
 252         HW_XSTAT(tx_size_512_to_1023_packets),
 253         HW_XSTAT(tx_size_1024_to_max_packets),
 254
 255         /* Flow Control */
 256         HW_XSTAT(tx_xon_packets),
 257         HW_XSTAT(rx_xon_packets),
 258         HW_XSTAT(tx_xoff_packets),
 259         HW_XSTAT(rx_xoff_packets),
 260
 261         HW_XSTAT_NAME(tx_xon_packets, "tx_flow_control_xon_packets"),
 262         HW_XSTAT_NAME(rx_xon_packets, "rx_flow_control_xon_packets"),
 263         HW_XSTAT_NAME(tx_xoff_packets, "tx_flow_control_xoff_packets"),
 264         HW_XSTAT_NAME(rx_xoff_packets, "rx_flow_control_xoff_packets"),
 265 };
 266
 267 #define TXGBE_NB_HW_STATS (sizeof(rte_txgbe_stats_strings) / \
 268                            sizeof(rte_txgbe_stats_strings[0]))
 269
 270 /* Per-priority statistics */
 271 #define UP_XSTAT(m) {#m, offsetof(struct txgbe_hw_stats, up[0].m)}
 272 static const struct rte_txgbe_xstats_name_off rte_txgbe_up_strings[] = {
 273         UP_XSTAT(rx_up_packets),
 274         UP_XSTAT(tx_up_packets),
 275         UP_XSTAT(rx_up_bytes),
 276         UP_XSTAT(tx_up_bytes),
 277         UP_XSTAT(rx_up_drop_packets),
 278
 279         UP_XSTAT(tx_up_xon_packets),
 280         UP_XSTAT(rx_up_xon_packets),
 281         UP_XSTAT(tx_up_xoff_packets),
 282         UP_XSTAT(rx_up_xoff_packets),
 283         UP_XSTAT(rx_up_dropped),
 284         UP_XSTAT(rx_up_mbuf_alloc_errors),
 285         UP_XSTAT(tx_up_xon2off_packets),
 286 };
 287
 288 #define TXGBE_NB_UP_STATS (sizeof(rte_txgbe_up_strings) / \
 289                            sizeof(rte_txgbe_up_strings[0]))
 290
 291 /* Per-queue statistics */
 292 #define QP_XSTAT(m) {#m, offsetof(struct txgbe_hw_stats, qp[0].m)}
 293 static const struct rte_txgbe_xstats_name_off rte_txgbe_qp_strings[] = {
 294         QP_XSTAT(rx_qp_packets),
 295         QP_XSTAT(tx_qp_packets),
 296         QP_XSTAT(rx_qp_bytes),
 297         QP_XSTAT(tx_qp_bytes),
 298         QP_XSTAT(rx_qp_mc_packets),
 299 };
 300
 301 #define TXGBE_NB_QP_STATS (sizeof(rte_txgbe_qp_strings) / \
 302                            sizeof(rte_txgbe_qp_strings[0]))
 303
 304 static inline int
 305 txgbe_is_sfp(struct txgbe_hw *hw)
 306 {
 307         switch (hw->phy.type) {
 308         case txgbe_phy_sfp_avago:
 309         case txgbe_phy_sfp_ftl:
 310         case txgbe_phy_sfp_intel:
 311         case txgbe_phy_sfp_unknown:
 312         case txgbe_phy_sfp_tyco_passive:
 313         case txgbe_phy_sfp_unknown_passive:
 314                 return 1;
 315         default:
 316                 return 0;
 317         }
 318 }
 319
 320 static inline int32_t
 321 txgbe_pf_reset_hw(struct txgbe_hw *hw)
 322 {
 323         uint32_t ctrl_ext;
 324         int32_t status;
 325
 326         status = hw->mac.reset_hw(hw);
 327
 328         ctrl_ext = rd32(hw, TXGBE_PORTCTL);
 329         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 330         ctrl_ext |= TXGBE_PORTCTL_RSTDONE;
 331         wr32(hw, TXGBE_PORTCTL, ctrl_ext);
 332         txgbe_flush(hw);
 333
 334         if (status == TXGBE_ERR_SFP_NOT_PRESENT)
 335                 status = 0;
 336         return status;
 337 }
 338
 339 static inline void
 340 txgbe_enable_intr(struct rte_eth_dev *dev)
 341 {
 342         struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);
 343         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
 344
 345         wr32(hw, TXGBE_IENMISC, intr->mask_misc);
 346         wr32(hw, TXGBE_IMC(0), TXGBE_IMC_MASK);
 347         wr32(hw, TXGBE_IMC(1), TXGBE_IMC_MASK);
 348         txgbe_flush(hw);
 349 }
 350
 351 static void
 352 txgbe_disable_intr(struct txgbe_hw *hw)
 353 {
 354         PMD_INIT_FUNC_TRACE();
 355
 356         wr32(hw, TXGBE_IENMISC, ~BIT_MASK32);
 357         wr32(hw, TXGBE_IMS(0), TXGBE_IMC_MASK);
 358         wr32(hw, TXGBE_IMS(1), TXGBE_IMC_MASK);
 359         txgbe_flush(hw);
 360 }
 361
 362 static int
 363 txgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 364                                   uint16_t queue_id,
 365                                   uint8_t stat_idx,
 366                                   uint8_t is_rx)
 367 {
 368         struct txgbe_hw *hw = TXGBE_DEV_HW(eth_dev);
 369         struct txgbe_stat_mappings *stat_mappings =
 370                 TXGBE_DEV_STAT_MAPPINGS(eth_dev);
 371         uint32_t qsmr_mask = 0;
 372         uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
 373         uint32_t q_map;
 374         uint8_t n, offset;
 375
 376         if (hw->mac.type != txgbe_mac_raptor)
 377                 return -ENOSYS;
 378
 379         if (stat_idx & !QMAP_FIELD_RESERVED_BITS_MASK)
 380                 return -EIO;
 381
 382         PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d",
 383                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 384                      queue_id, stat_idx);
 385
 386         n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
 387         if (n >= TXGBE_NB_STAT_MAPPING) {
 388                 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
 389                 return -EIO;
 390         }
 391         offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
 392
 393         /* Now clear any previous stat_idx set */
 394         clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 395         if (!is_rx)
 396                 stat_mappings->tqsm[n] &= ~clearing_mask;
 397         else
 398                 stat_mappings->rqsm[n] &= ~clearing_mask;
 399
 400         q_map = (uint32_t)stat_idx;
 401         q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
 402         qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 403         if (!is_rx)
 404                 stat_mappings->tqsm[n] |= qsmr_mask;
 405         else
 406                 stat_mappings->rqsm[n] |= qsmr_mask;
 407
 408         PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d",
 409                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 410                      queue_id, stat_idx);
 411         PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
 412                      is_rx ? stat_mappings->rqsm[n] : stat_mappings->tqsm[n]);
 413         return 0;
 414 }
 415
 416 static void
 417 txgbe_dcb_init(struct txgbe_hw *hw, struct txgbe_dcb_config *dcb_config)
 418 {
 419         int i;
 420         u8 bwgp;
 421         struct txgbe_dcb_tc_config *tc;
 422
 423         UNREFERENCED_PARAMETER(hw);
 424
 425         dcb_config->num_tcs.pg_tcs = TXGBE_DCB_TC_MAX;
 426         dcb_config->num_tcs.pfc_tcs = TXGBE_DCB_TC_MAX;
 427         bwgp = (u8)(100 / TXGBE_DCB_TC_MAX);
 428         for (i = 0; i < TXGBE_DCB_TC_MAX; i++) {
 429                 tc = &dcb_config->tc_config[i];
 430                 tc->path[TXGBE_DCB_TX_CONFIG].bwg_id = i;
 431                 tc->path[TXGBE_DCB_TX_CONFIG].bwg_percent = bwgp + (i & 1);
 432                 tc->path[TXGBE_DCB_RX_CONFIG].bwg_id = i;
 433                 tc->path[TXGBE_DCB_RX_CONFIG].bwg_percent = bwgp + (i & 1);
 434                 tc->pfc = txgbe_dcb_pfc_disabled;
 435         }
 436
 437         /* Initialize default user to priority mapping, UPx->TC0 */
 438         tc = &dcb_config->tc_config[0];
 439         tc->path[TXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
 440         tc->path[TXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
 441         for (i = 0; i < TXGBE_DCB_BWG_MAX; i++) {
 442                 dcb_config->bw_percentage[i][TXGBE_DCB_TX_CONFIG] = 100;
 443                 dcb_config->bw_percentage[i][TXGBE_DCB_RX_CONFIG] = 100;
 444         }
 445         dcb_config->rx_pba_cfg = txgbe_dcb_pba_equal;
 446         dcb_config->pfc_mode_enable = false;
 447         dcb_config->vt_mode = true;
 448         dcb_config->round_robin_enable = false;
 449         /* support all DCB capabilities */
 450         dcb_config->support.capabilities = 0xFF;
 451 }
 452
 453 /*
 454  * Ensure that all locks are released before first NVM or PHY access
 455  */
 456 static void
 457 txgbe_swfw_lock_reset(struct txgbe_hw *hw)
 458 {
 459         uint16_t mask;
 460
 461         /*
 462          * These ones are more tricky since they are common to all ports; but
 463          * swfw_sync retries last long enough (1s) to be almost sure that if
 464          * lock can not be taken it is due to an improper lock of the
 465          * semaphore.
 466          */
 467         mask = TXGBE_MNGSEM_SWPHY |
 468                TXGBE_MNGSEM_SWMBX |
 469                TXGBE_MNGSEM_SWFLASH;
 470         if (hw->mac.acquire_swfw_sync(hw, mask) < 0)
 471                 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
 472
 473         hw->mac.release_swfw_sync(hw, mask);
 474 }
 475
 476 static int
 477 txgbe_handle_devarg(__rte_unused const char *key, const char *value,
 478                   void *extra_args)
 479 {
 480         uint16_t *n = extra_args;
 481
 482         if (value == NULL || extra_args == NULL)
 483                 return -EINVAL;
 484
 485         *n = (uint16_t)strtoul(value, NULL, 10);
 486         if (*n == USHRT_MAX && errno == ERANGE)
 487                 return -1;
 488
 489         return 0;
 490 }
 491
 492 static void
 493 txgbe_parse_devargs(struct txgbe_hw *hw, struct rte_devargs *devargs)
 494 {
 495         struct rte_kvargs *kvlist;
 496         u16 auto_neg = 1;
 497         u16 poll = 0;
 498         u16 present = 1;
 499         u16 sgmii = 0;
 500         u16 ffe_set = 0;
 501         u16 ffe_main = 27;
 502         u16 ffe_pre = 8;
 503         u16 ffe_post = 44;
 504
 505         if (devargs == NULL)
 506                 goto null;
 507
 508         kvlist = rte_kvargs_parse(devargs->args, txgbe_valid_arguments);
 509         if (kvlist == NULL)
 510                 goto null;
 511
 512         rte_kvargs_process(kvlist, TXGBE_DEVARG_BP_AUTO,
 513                            &txgbe_handle_devarg, &auto_neg);
 514         rte_kvargs_process(kvlist, TXGBE_DEVARG_KR_POLL,
 515                            &txgbe_handle_devarg, &poll);
 516         rte_kvargs_process(kvlist, TXGBE_DEVARG_KR_PRESENT,
 517                            &txgbe_handle_devarg, &present);
 518         rte_kvargs_process(kvlist, TXGBE_DEVARG_KX_SGMII,
 519                            &txgbe_handle_devarg, &sgmii);
 520         rte_kvargs_process(kvlist, TXGBE_DEVARG_FFE_SET,
 521                            &txgbe_handle_devarg, &ffe_set);
 522         rte_kvargs_process(kvlist, TXGBE_DEVARG_FFE_MAIN,
 523                            &txgbe_handle_devarg, &ffe_main);
 524         rte_kvargs_process(kvlist, TXGBE_DEVARG_FFE_PRE,
 525                            &txgbe_handle_devarg, &ffe_pre);
 526         rte_kvargs_process(kvlist, TXGBE_DEVARG_FFE_POST,
 527                            &txgbe_handle_devarg, &ffe_post);
 528         rte_kvargs_free(kvlist);
 529
 530 null:
 531         hw->devarg.auto_neg = auto_neg;
 532         hw->devarg.poll = poll;
 533         hw->devarg.present = present;
 534         hw->devarg.sgmii = sgmii;
 535         hw->phy.ffe_set = ffe_set;
 536         hw->phy.ffe_main = ffe_main;
 537         hw->phy.ffe_pre = ffe_pre;
 538         hw->phy.ffe_post = ffe_post;
 539 }
 540
 541 static int
 542 eth_txgbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params __rte_unused)
 543 {
 544         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
 545         struct txgbe_hw *hw = TXGBE_DEV_HW(eth_dev);
 546         struct txgbe_vfta *shadow_vfta = TXGBE_DEV_VFTA(eth_dev);
 547         struct txgbe_hwstrip *hwstrip = TXGBE_DEV_HWSTRIP(eth_dev);
 548         struct txgbe_dcb_config *dcb_config = TXGBE_DEV_DCB_CONFIG(eth_dev);
 549         struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(eth_dev);
 550         struct txgbe_bw_conf *bw_conf = TXGBE_DEV_BW_CONF(eth_dev);
 551         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 552         const struct rte_memzone *mz;
 553         uint32_t ctrl_ext;
 554         uint16_t csum;
 555         int err, i, ret;
 556
 557         PMD_INIT_FUNC_TRACE();
 558
 559         eth_dev->dev_ops = &txgbe_eth_dev_ops;
 560         eth_dev->rx_queue_count       = txgbe_dev_rx_queue_count;
 561         eth_dev->rx_descriptor_status = txgbe_dev_rx_descriptor_status;
 562         eth_dev->tx_descriptor_status = txgbe_dev_tx_descriptor_status;
 563         eth_dev->rx_pkt_burst = &txgbe_recv_pkts;
 564         eth_dev->tx_pkt_burst = &txgbe_xmit_pkts;
 565         eth_dev->tx_pkt_prepare = &txgbe_prep_pkts;
 566
 567         /*
 568          * For secondary processes, we don't initialise any further as primary
 569          * has already done this work. Only check we don't need a different
 570          * RX and TX function.
 571          */
 572         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
 573                 struct txgbe_tx_queue *txq;
 574                 /* TX queue function in primary, set by last queue initialized
 575                  * Tx queue may not initialized by primary process
 576                  */
 577                 if (eth_dev->data->tx_queues) {
 578                         uint16_t nb_tx_queues = eth_dev->data->nb_tx_queues;
 579                         txq = eth_dev->data->tx_queues[nb_tx_queues - 1];
 580                         txgbe_set_tx_function(eth_dev, txq);
 581                 } else {
 582                         /* Use default TX function if we get here */
 583                         PMD_INIT_LOG(NOTICE, "No TX queues configured yet. "
 584                                      "Using default TX function.");
 585                 }
 586
 587                 txgbe_set_rx_function(eth_dev);
 588
 589                 return 0;
 590         }
 591
 592         rte_eth_copy_pci_info(eth_dev, pci_dev);
 593
 594         /* Vendor and Device ID need to be set before init of shared code */
 595         hw->device_id = pci_dev->id.device_id;
 596         hw->vendor_id = pci_dev->id.vendor_id;
 597         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
 598         hw->allow_unsupported_sfp = 1;
 599
 600         /* Reserve memory for interrupt status block */
 601         mz = rte_eth_dma_zone_reserve(eth_dev, "txgbe_driver", -1,
 602                 16, TXGBE_ALIGN, SOCKET_ID_ANY);
 603         if (mz == NULL)
 604                 return -ENOMEM;
 605
 606         hw->isb_dma = TMZ_PADDR(mz);
 607         hw->isb_mem = TMZ_VADDR(mz);
 608
 609         txgbe_parse_devargs(hw, pci_dev->device.devargs);
 610         /* Initialize the shared code (base driver) */
 611         err = txgbe_init_shared_code(hw);
 612         if (err != 0) {
 613                 PMD_INIT_LOG(ERR, "Shared code init failed: %d", err);
 614                 return -EIO;
 615         }
 616
 617         /* Unlock any pending hardware semaphore */
 618         txgbe_swfw_lock_reset(hw);
 619
 620 #ifdef RTE_LIB_SECURITY
 621         /* Initialize security_ctx only for primary process*/
 622         if (txgbe_ipsec_ctx_create(eth_dev))
 623                 return -ENOMEM;
 624 #endif
 625
 626         /* Initialize DCB configuration*/
 627         memset(dcb_config, 0, sizeof(struct txgbe_dcb_config));
 628         txgbe_dcb_init(hw, dcb_config);
 629
 630         /* Get Hardware Flow Control setting */
 631         hw->fc.requested_mode = txgbe_fc_full;
 632         hw->fc.current_mode = txgbe_fc_full;
 633         hw->fc.pause_time = TXGBE_FC_PAUSE_TIME;
 634         for (i = 0; i < TXGBE_DCB_TC_MAX; i++) {
 635                 hw->fc.low_water[i] = TXGBE_FC_XON_LOTH;
 636                 hw->fc.high_water[i] = TXGBE_FC_XOFF_HITH;
 637         }
 638         hw->fc.send_xon = 1;
 639
 640         err = hw->rom.init_params(hw);
 641         if (err != 0) {
 642                 PMD_INIT_LOG(ERR, "The EEPROM init failed: %d", err);
 643                 return -EIO;
 644         }
 645
 646         /* Make sure we have a good EEPROM before we read from it */
 647         err = hw->rom.validate_checksum(hw, &csum);
 648         if (err != 0) {
 649                 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", err);
 650                 return -EIO;
 651         }
 652
 653         err = hw->mac.init_hw(hw);
 654
 655         /*
 656          * Devices with copper phys will fail to initialise if txgbe_init_hw()
 657          * is called too soon after the kernel driver unbinding/binding occurs.
 658          * The failure occurs in txgbe_identify_phy() for all devices,
 659          * but for non-copper devies, txgbe_identify_sfp_module() is
 660          * also called. See txgbe_identify_phy(). The reason for the
 661          * failure is not known, and only occuts when virtualisation features
 662          * are disabled in the bios. A delay of 200ms  was found to be enough by
 663          * trial-and-error, and is doubled to be safe.
 664          */
 665         if (err && hw->phy.media_type == txgbe_media_type_copper) {
 666                 rte_delay_ms(200);
 667                 err = hw->mac.init_hw(hw);
 668         }
 669
 670         if (err == TXGBE_ERR_SFP_NOT_PRESENT)
 671                 err = 0;
 672
 673         if (err == TXGBE_ERR_EEPROM_VERSION) {
 674                 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
 675                              "LOM.  Please be aware there may be issues associated "
 676                              "with your hardware.");
 677                 PMD_INIT_LOG(ERR, "If you are experiencing problems "
 678                              "please contact your hardware representative "
 679                              "who provided you with this hardware.");
 680         } else if (err == TXGBE_ERR_SFP_NOT_SUPPORTED) {
 681                 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
 682         }
 683         if (err) {
 684                 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", err);
 685                 return -EIO;
 686         }
 687
 688         /* Reset the hw statistics */
 689         txgbe_dev_stats_reset(eth_dev);
 690
 691         /* disable interrupt */
 692         txgbe_disable_intr(hw);
 693
 694         /* Allocate memory for storing MAC addresses */
 695         eth_dev->data->mac_addrs = rte_zmalloc("txgbe", RTE_ETHER_ADDR_LEN *
 696                                                hw->mac.num_rar_entries, 0);
 697         if (eth_dev->data->mac_addrs == NULL) {
 698                 PMD_INIT_LOG(ERR,
 699                              "Failed to allocate %u bytes needed to store "
 700                              "MAC addresses",
 701                              RTE_ETHER_ADDR_LEN * hw->mac.num_rar_entries);
 702                 return -ENOMEM;
 703         }
 704
 705         /* Copy the permanent MAC address */
 706         rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.perm_addr,
 707                         &eth_dev->data->mac_addrs[0]);
 708
 709         /* Allocate memory for storing hash filter MAC addresses */
 710         eth_dev->data->hash_mac_addrs = rte_zmalloc("txgbe",
 711                         RTE_ETHER_ADDR_LEN * TXGBE_VMDQ_NUM_UC_MAC, 0);
 712         if (eth_dev->data->hash_mac_addrs == NULL) {
 713                 PMD_INIT_LOG(ERR,
 714                              "Failed to allocate %d bytes needed to store MAC addresses",
 715                              RTE_ETHER_ADDR_LEN * TXGBE_VMDQ_NUM_UC_MAC);
 716                 return -ENOMEM;
 717         }
 718
 719         /* initialize the vfta */
 720         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
 721
 722         /* initialize the hw strip bitmap*/
 723         memset(hwstrip, 0, sizeof(*hwstrip));
 724
 725         /* initialize PF if max_vfs not zero */
 726         ret = txgbe_pf_host_init(eth_dev);
 727         if (ret) {
 728                 rte_free(eth_dev->data->mac_addrs);
 729                 eth_dev->data->mac_addrs = NULL;
 730                 rte_free(eth_dev->data->hash_mac_addrs);
 731                 eth_dev->data->hash_mac_addrs = NULL;
 732                 return ret;
 733         }
 734
 735         ctrl_ext = rd32(hw, TXGBE_PORTCTL);
 736         /* let hardware know driver is loaded */
 737         ctrl_ext |= TXGBE_PORTCTL_DRVLOAD;
 738         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 739         ctrl_ext |= TXGBE_PORTCTL_RSTDONE;
 740         wr32(hw, TXGBE_PORTCTL, ctrl_ext);
 741         txgbe_flush(hw);
 742
 743         if (txgbe_is_sfp(hw) && hw->phy.sfp_type != txgbe_sfp_type_not_present)
 744                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
 745                              (int)hw->mac.type, (int)hw->phy.type,
 746                              (int)hw->phy.sfp_type);
 747         else
 748                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
 749                              (int)hw->mac.type, (int)hw->phy.type);
 750
 751         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
 752                      eth_dev->data->port_id, pci_dev->id.vendor_id,
 753                      pci_dev->id.device_id);
 754
 755         rte_intr_callback_register(intr_handle,
 756                                    txgbe_dev_interrupt_handler, eth_dev);
 757
 758         /* enable uio/vfio intr/eventfd mapping */
 759         rte_intr_enable(intr_handle);
 760
 761         /* enable support intr */
 762         txgbe_enable_intr(eth_dev);
 763
 764         /* initialize filter info */
 765         memset(filter_info, 0,
 766                sizeof(struct txgbe_filter_info));
 767
 768         /* initialize 5tuple filter list */
 769         TAILQ_INIT(&filter_info->fivetuple_list);
 770
 771         /* initialize flow director filter list & hash */
 772         txgbe_fdir_filter_init(eth_dev);
 773
 774         /* initialize l2 tunnel filter list & hash */
 775         txgbe_l2_tn_filter_init(eth_dev);
 776
 777         /* initialize flow filter lists */
 778         txgbe_filterlist_init();
 779
 780         /* initialize bandwidth configuration info */
 781         memset(bw_conf, 0, sizeof(struct txgbe_bw_conf));
 782
 783         /* initialize Traffic Manager configuration */
 784         txgbe_tm_conf_init(eth_dev);
 785
 786         return 0;
 787 }
 788
 789 static int
 790 eth_txgbe_dev_uninit(struct rte_eth_dev *eth_dev)
 791 {
 792         PMD_INIT_FUNC_TRACE();
 793
 794         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 795                 return 0;
 796
 797         txgbe_dev_close(eth_dev);
 798
 799         return 0;
 800 }
 801
 802 static int txgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev)
 803 {
 804         struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(eth_dev);
 805         struct txgbe_5tuple_filter *p_5tuple;
 806
 807         while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) {
 808                 TAILQ_REMOVE(&filter_info->fivetuple_list,
 809                              p_5tuple,
 810                              entries);
 811                 rte_free(p_5tuple);
 812         }
 813         memset(filter_info->fivetuple_mask, 0,
 814                sizeof(uint32_t) * TXGBE_5TUPLE_ARRAY_SIZE);
 815
 816         return 0;
 817 }
 818
 819 static int txgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev)
 820 {
 821         struct txgbe_hw_fdir_info *fdir_info = TXGBE_DEV_FDIR(eth_dev);
 822         struct txgbe_fdir_filter *fdir_filter;
 823
 824         if (fdir_info->hash_map)
 825                 rte_free(fdir_info->hash_map);
 826         if (fdir_info->hash_handle)
 827                 rte_hash_free(fdir_info->hash_handle);
 828
 829         while ((fdir_filter = TAILQ_FIRST(&fdir_info->fdir_list))) {
 830                 TAILQ_REMOVE(&fdir_info->fdir_list,
 831                              fdir_filter,
 832                              entries);
 833                 rte_free(fdir_filter);
 834         }
 835
 836         return 0;
 837 }
 838
 839 static int txgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev)
 840 {
 841         struct txgbe_l2_tn_info *l2_tn_info = TXGBE_DEV_L2_TN(eth_dev);
 842         struct txgbe_l2_tn_filter *l2_tn_filter;
 843
 844         if (l2_tn_info->hash_map)
 845                 rte_free(l2_tn_info->hash_map);
 846         if (l2_tn_info->hash_handle)
 847                 rte_hash_free(l2_tn_info->hash_handle);
 848
 849         while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
 850                 TAILQ_REMOVE(&l2_tn_info->l2_tn_list,
 851                              l2_tn_filter,
 852                              entries);
 853                 rte_free(l2_tn_filter);
 854         }
 855
 856         return 0;
 857 }
 858
 859 static int txgbe_fdir_filter_init(struct rte_eth_dev *eth_dev)
 860 {
 861         struct txgbe_hw_fdir_info *fdir_info = TXGBE_DEV_FDIR(eth_dev);
 862         char fdir_hash_name[RTE_HASH_NAMESIZE];
 863         struct rte_hash_parameters fdir_hash_params = {
 864                 .name = fdir_hash_name,
 865                 .entries = TXGBE_MAX_FDIR_FILTER_NUM,
 866                 .key_len = sizeof(struct txgbe_atr_input),
 867                 .hash_func = rte_hash_crc,
 868                 .hash_func_init_val = 0,
 869                 .socket_id = rte_socket_id(),
 870         };
 871
 872         TAILQ_INIT(&fdir_info->fdir_list);
 873         snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
 874                  "fdir_%s", TDEV_NAME(eth_dev));
 875         fdir_info->hash_handle = rte_hash_create(&fdir_hash_params);
 876         if (!fdir_info->hash_handle) {
 877                 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
 878                 return -EINVAL;
 879         }
 880         fdir_info->hash_map = rte_zmalloc("txgbe",
 881                                           sizeof(struct txgbe_fdir_filter *) *
 882                                           TXGBE_MAX_FDIR_FILTER_NUM,
 883                                           0);
 884         if (!fdir_info->hash_map) {
 885                 PMD_INIT_LOG(ERR,
 886                              "Failed to allocate memory for fdir hash map!");
 887                 return -ENOMEM;
 888         }
 889         fdir_info->mask_added = FALSE;
 890
 891         return 0;
 892 }
 893
 894 static int txgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev)
 895 {
 896         struct txgbe_l2_tn_info *l2_tn_info = TXGBE_DEV_L2_TN(eth_dev);
 897         char l2_tn_hash_name[RTE_HASH_NAMESIZE];
 898         struct rte_hash_parameters l2_tn_hash_params = {
 899                 .name = l2_tn_hash_name,
 900                 .entries = TXGBE_MAX_L2_TN_FILTER_NUM,
 901                 .key_len = sizeof(struct txgbe_l2_tn_key),
 902                 .hash_func = rte_hash_crc,
 903                 .hash_func_init_val = 0,
 904                 .socket_id = rte_socket_id(),
 905         };
 906
 907         TAILQ_INIT(&l2_tn_info->l2_tn_list);
 908         snprintf(l2_tn_hash_name, RTE_HASH_NAMESIZE,
 909                  "l2_tn_%s", TDEV_NAME(eth_dev));
 910         l2_tn_info->hash_handle = rte_hash_create(&l2_tn_hash_params);
 911         if (!l2_tn_info->hash_handle) {
 912                 PMD_INIT_LOG(ERR, "Failed to create L2 TN hash table!");
 913                 return -EINVAL;
 914         }
 915         l2_tn_info->hash_map = rte_zmalloc("txgbe",
 916                                    sizeof(struct txgbe_l2_tn_filter *) *
 917                                    TXGBE_MAX_L2_TN_FILTER_NUM,
 918                                    0);
 919         if (!l2_tn_info->hash_map) {
 920                 PMD_INIT_LOG(ERR,
 921                         "Failed to allocate memory for L2 TN hash map!");
 922                 return -ENOMEM;
 923         }
 924         l2_tn_info->e_tag_en = FALSE;
 925         l2_tn_info->e_tag_fwd_en = FALSE;
 926         l2_tn_info->e_tag_ether_type = RTE_ETHER_TYPE_ETAG;
 927
 928         return 0;
 929 }
 930
 931 static int
 932 eth_txgbe_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
 933                 struct rte_pci_device *pci_dev)
 934 {
 935         return rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
 936                         sizeof(struct txgbe_adapter),
 937                         eth_dev_pci_specific_init, pci_dev,
 938                         eth_txgbe_dev_init, NULL);
 939 }
 940
 941 static int eth_txgbe_pci_remove(struct rte_pci_device *pci_dev)
 942 {
 943         struct rte_eth_dev *ethdev;
 944
 945         ethdev = rte_eth_dev_allocated(pci_dev->device.name);
 946         if (!ethdev)
 947                 return 0;
 948
 949         return rte_eth_dev_destroy(ethdev, eth_txgbe_dev_uninit);
 950 }
 951
 952 static struct rte_pci_driver rte_txgbe_pmd = {
 953         .id_table = pci_id_txgbe_map,
 954         .drv_flags = RTE_PCI_DRV_NEED_MAPPING |
 955                      RTE_PCI_DRV_INTR_LSC,
 956         .probe = eth_txgbe_pci_probe,
 957         .remove = eth_txgbe_pci_remove,
 958 };
 959
 960 static int
 961 txgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
 962 {
 963         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
 964         struct txgbe_vfta *shadow_vfta = TXGBE_DEV_VFTA(dev);
 965         uint32_t vfta;
 966         uint32_t vid_idx;
 967         uint32_t vid_bit;
 968
 969         vid_idx = (uint32_t)((vlan_id >> 5) & 0x7F);
 970         vid_bit = (uint32_t)(1 << (vlan_id & 0x1F));
 971         vfta = rd32(hw, TXGBE_VLANTBL(vid_idx));
 972         if (on)
 973                 vfta |= vid_bit;
 974         else
 975                 vfta &= ~vid_bit;
 976         wr32(hw, TXGBE_VLANTBL(vid_idx), vfta);
 977
 978         /* update local VFTA copy */
 979         shadow_vfta->vfta[vid_idx] = vfta;
 980
 981         return 0;
 982 }
 983
 984 static void
 985 txgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
 986 {
 987         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
 988         struct txgbe_rx_queue *rxq;
 989         bool restart;
 990         uint32_t rxcfg, rxbal, rxbah;
 991
 992         if (on)
 993                 txgbe_vlan_hw_strip_enable(dev, queue);
 994         else
 995                 txgbe_vlan_hw_strip_disable(dev, queue);
 996
 997         rxq = dev->data->rx_queues[queue];
 998         rxbal = rd32(hw, TXGBE_RXBAL(rxq->reg_idx));
 999         rxbah = rd32(hw, TXGBE_RXBAH(rxq->reg_idx));
1000         rxcfg = rd32(hw, TXGBE_RXCFG(rxq->reg_idx));
1001         if (rxq->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) {
1002                 restart = (rxcfg & TXGBE_RXCFG_ENA) &&
1003                         !(rxcfg & TXGBE_RXCFG_VLAN);
1004                 rxcfg |= TXGBE_RXCFG_VLAN;
1005         } else {
1006                 restart = (rxcfg & TXGBE_RXCFG_ENA) &&
1007                         (rxcfg & TXGBE_RXCFG_VLAN);
1008                 rxcfg &= ~TXGBE_RXCFG_VLAN;
1009         }
1010         rxcfg &= ~TXGBE_RXCFG_ENA;
1011
1012         if (restart) {
1013                 /* set vlan strip for ring */
1014                 txgbe_dev_rx_queue_stop(dev, queue);
1015                 wr32(hw, TXGBE_RXBAL(rxq->reg_idx), rxbal);
1016                 wr32(hw, TXGBE_RXBAH(rxq->reg_idx), rxbah);
1017                 wr32(hw, TXGBE_RXCFG(rxq->reg_idx), rxcfg);
1018                 txgbe_dev_rx_queue_start(dev, queue);
1019         }
1020 }
1021
1022 static int
1023 txgbe_vlan_tpid_set(struct rte_eth_dev *dev,
1024                     enum rte_vlan_type vlan_type,
1025                     uint16_t tpid)
1026 {
1027         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
1028         int ret = 0;
1029         uint32_t portctrl, vlan_ext, qinq;
1030
1031         portctrl = rd32(hw, TXGBE_PORTCTL);
1032
1033         vlan_ext = (portctrl & TXGBE_PORTCTL_VLANEXT);
1034         qinq = vlan_ext && (portctrl & TXGBE_PORTCTL_QINQ);
1035         switch (vlan_type) {
1036         case ETH_VLAN_TYPE_INNER:
1037                 if (vlan_ext) {
1038                         wr32m(hw, TXGBE_VLANCTL,
1039                                 TXGBE_VLANCTL_TPID_MASK,
1040                                 TXGBE_VLANCTL_TPID(tpid));
1041                         wr32m(hw, TXGBE_DMATXCTRL,
1042                                 TXGBE_DMATXCTRL_TPID_MASK,
1043                                 TXGBE_DMATXCTRL_TPID(tpid));
1044                 } else {
1045                         ret = -ENOTSUP;
1046                         PMD_DRV_LOG(ERR, "Inner type is not supported"
1047                                     " by single VLAN");
1048                 }
1049
1050                 if (qinq) {
1051                         wr32m(hw, TXGBE_TAGTPID(0),
1052                                 TXGBE_TAGTPID_LSB_MASK,
1053                                 TXGBE_TAGTPID_LSB(tpid));
1054                 }
1055                 break;
1056         case ETH_VLAN_TYPE_OUTER:
1057                 if (vlan_ext) {
1058                         /* Only the high 16-bits is valid */
1059                         wr32m(hw, TXGBE_EXTAG,
1060                                 TXGBE_EXTAG_VLAN_MASK,
1061                                 TXGBE_EXTAG_VLAN(tpid));
1062                 } else {
1063                         wr32m(hw, TXGBE_VLANCTL,
1064                                 TXGBE_VLANCTL_TPID_MASK,
1065                                 TXGBE_VLANCTL_TPID(tpid));
1066                         wr32m(hw, TXGBE_DMATXCTRL,
1067                                 TXGBE_DMATXCTRL_TPID_MASK,
1068                                 TXGBE_DMATXCTRL_TPID(tpid));
1069                 }
1070
1071                 if (qinq) {
1072                         wr32m(hw, TXGBE_TAGTPID(0),
1073                                 TXGBE_TAGTPID_MSB_MASK,
1074                                 TXGBE_TAGTPID_MSB(tpid));
1075                 }
1076                 break;
1077         default:
1078                 PMD_DRV_LOG(ERR, "Unsupported VLAN type %d", vlan_type);
1079                 return -EINVAL;
1080         }
1081
1082         return ret;
1083 }
1084
1085 void
1086 txgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1087 {
1088         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
1089         uint32_t vlnctrl;
1090
1091         PMD_INIT_FUNC_TRACE();
1092
1093         /* Filter Table Disable */
1094         vlnctrl = rd32(hw, TXGBE_VLANCTL);
1095         vlnctrl &= ~TXGBE_VLANCTL_VFE;
1096         wr32(hw, TXGBE_VLANCTL, vlnctrl);
1097 }
1098
1099 void
1100 txgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1101 {
1102         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
1103         struct txgbe_vfta *shadow_vfta = TXGBE_DEV_VFTA(dev);
1104         uint32_t vlnctrl;
1105         uint16_t i;
1106
1107         PMD_INIT_FUNC_TRACE();
1108
1109         /* Filter Table Enable */
1110         vlnctrl = rd32(hw, TXGBE_VLANCTL);
1111         vlnctrl &= ~TXGBE_VLANCTL_CFIENA;
1112         vlnctrl |= TXGBE_VLANCTL_VFE;
1113         wr32(hw, TXGBE_VLANCTL, vlnctrl);
1114
1115         /* write whatever is in local vfta copy */
1116         for (i = 0; i < TXGBE_VFTA_SIZE; i++)
1117                 wr32(hw, TXGBE_VLANTBL(i), shadow_vfta->vfta[i]);
1118 }
1119
1120 void
1121 txgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1122 {
1123         struct txgbe_hwstrip *hwstrip = TXGBE_DEV_HWSTRIP(dev);
1124         struct txgbe_rx_queue *rxq;
1125
1126         if (queue >= TXGBE_MAX_RX_QUEUE_NUM)
1127                 return;
1128
1129         if (on)
1130                 TXGBE_SET_HWSTRIP(hwstrip, queue);
1131         else
1132                 TXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1133
1134         if (queue >= dev->data->nb_rx_queues)
1135                 return;
1136
1137         rxq = dev->data->rx_queues[queue];
1138
1139         if (on) {
1140                 rxq->vlan_flags = PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
1141                 rxq->offloads |= DEV_RX_OFFLOAD_VLAN_STRIP;
1142         } else {
1143                 rxq->vlan_flags = PKT_RX_VLAN;
1144                 rxq->offloads &= ~DEV_RX_OFFLOAD_VLAN_STRIP;
1145         }
1146 }
1147
1148 static void
1149 txgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
1150 {
1151         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
1152         uint32_t ctrl;
1153
1154         PMD_INIT_FUNC_TRACE();
1155
1156         ctrl = rd32(hw, TXGBE_RXCFG(queue));
1157         ctrl &= ~TXGBE_RXCFG_VLAN;
1158         wr32(hw, TXGBE_RXCFG(queue), ctrl);
1159
1160         /* record those setting for HW strip per queue */
1161         txgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
1162 }
1163
1164 static void
1165 txgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
1166 {
1167         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
1168         uint32_t ctrl;
1169
1170         PMD_INIT_FUNC_TRACE();
1171
1172         ctrl = rd32(hw, TXGBE_RXCFG(queue));
1173         ctrl |= TXGBE_RXCFG_VLAN;
1174         wr32(hw, TXGBE_RXCFG(queue), ctrl);
1175
1176         /* record those setting for HW strip per queue */
1177         txgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
1178 }
1179
1180 static void
1181 txgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
1182 {
1183         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
1184         uint32_t ctrl;
1185
1186         PMD_INIT_FUNC_TRACE();
1187
1188         ctrl = rd32(hw, TXGBE_PORTCTL);
1189         ctrl &= ~TXGBE_PORTCTL_VLANEXT;
1190         wr32(hw, TXGBE_PORTCTL, ctrl);
1191 }
1192
1193 static void
1194 txgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
1195 {
1196         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
1197         uint32_t ctrl;
1198
1199         PMD_INIT_FUNC_TRACE();
1200
1201         ctrl  = rd32(hw, TXGBE_PORTCTL);
1202         ctrl |= TXGBE_PORTCTL_VLANEXT;
1203         wr32(hw, TXGBE_PORTCTL, ctrl);
1204 }
1205
1206 static void
1207 txgbe_qinq_hw_strip_disable(struct rte_eth_dev *dev)
1208 {
1209         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
1210         uint32_t ctrl;
1211
1212         PMD_INIT_FUNC_TRACE();
1213
1214         ctrl = rd32(hw, TXGBE_PORTCTL);
1215         ctrl &= ~TXGBE_PORTCTL_QINQ;
1216         wr32(hw, TXGBE_PORTCTL, ctrl);
1217 }
1218
1219 static void
1220 txgbe_qinq_hw_strip_enable(struct rte_eth_dev *dev)
1221 {
1222         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
1223         uint32_t ctrl;
1224
1225         PMD_INIT_FUNC_TRACE();
1226
1227         ctrl  = rd32(hw, TXGBE_PORTCTL);
1228         ctrl |= TXGBE_PORTCTL_QINQ | TXGBE_PORTCTL_VLANEXT;
1229         wr32(hw, TXGBE_PORTCTL, ctrl);
1230 }
1231
1232 void
1233 txgbe_vlan_hw_strip_config(struct rte_eth_dev *dev)
1234 {
1235         struct txgbe_rx_queue *rxq;
1236         uint16_t i;
1237
1238         PMD_INIT_FUNC_TRACE();
1239
1240         for (i = 0; i < dev->data->nb_rx_queues; i++) {
1241                 rxq = dev->data->rx_queues[i];
1242
1243                 if (rxq->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1244                         txgbe_vlan_strip_queue_set(dev, i, 1);
1245                 else
1246                         txgbe_vlan_strip_queue_set(dev, i, 0);
1247         }
1248 }
1249
1250 void
1251 txgbe_config_vlan_strip_on_all_queues(struct rte_eth_dev *dev, int mask)
1252 {
1253         uint16_t i;
1254         struct rte_eth_rxmode *rxmode;
1255         struct txgbe_rx_queue *rxq;
1256
1257         if (mask & ETH_VLAN_STRIP_MASK) {
1258                 rxmode = &dev->data->dev_conf.rxmode;
1259                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1260                         for (i = 0; i < dev->data->nb_rx_queues; i++) {
1261                                 rxq = dev->data->rx_queues[i];
1262                                 rxq->offloads |= DEV_RX_OFFLOAD_VLAN_STRIP;
1263                         }
1264                 else
1265                         for (i = 0; i < dev->data->nb_rx_queues; i++) {
1266                                 rxq = dev->data->rx_queues[i];
1267                                 rxq->offloads &= ~DEV_RX_OFFLOAD_VLAN_STRIP;
1268                         }
1269         }
1270 }
1271
1272 static int
1273 txgbe_vlan_offload_config(struct rte_eth_dev *dev, int mask)
1274 {
1275         struct rte_eth_rxmode *rxmode;
1276         rxmode = &dev->data->dev_conf.rxmode;
1277
1278         if (mask & ETH_VLAN_STRIP_MASK)
1279                 txgbe_vlan_hw_strip_config(dev);
1280
1281         if (mask & ETH_VLAN_FILTER_MASK) {
1282                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
1283                         txgbe_vlan_hw_filter_enable(dev);
1284                 else
1285                         txgbe_vlan_hw_filter_disable(dev);
1286         }
1287
1288         if (mask & ETH_VLAN_EXTEND_MASK) {
1289                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
1290                         txgbe_vlan_hw_extend_enable(dev);
1291                 else
1292                         txgbe_vlan_hw_extend_disable(dev);
1293         }
1294
1295         if (mask & ETH_QINQ_STRIP_MASK) {
1296                 if (rxmode->offloads & DEV_RX_OFFLOAD_QINQ_STRIP)
1297                         txgbe_qinq_hw_strip_enable(dev);
1298                 else
1299                         txgbe_qinq_hw_strip_disable(dev);
1300         }
1301
1302         return 0;
1303 }
1304
1305 static int
1306 txgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1307 {
1308         txgbe_config_vlan_strip_on_all_queues(dev, mask);
1309
1310         txgbe_vlan_offload_config(dev, mask);
1311
1312         return 0;
1313 }
1314
1315 static void
1316 txgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1317 {
1318         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
1319         /* VLNCTL: enable vlan filtering and allow all vlan tags through */
1320         uint32_t vlanctrl = rd32(hw, TXGBE_VLANCTL);
1321
1322         vlanctrl |= TXGBE_VLANCTL_VFE; /* enable vlan filters */
1323         wr32(hw, TXGBE_VLANCTL, vlanctrl);
1324 }
1325
1326 static int
1327 txgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q)
1328 {
1329         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1330
1331         switch (nb_rx_q) {
1332         case 1:
1333         case 2:
1334                 RTE_ETH_DEV_SRIOV(dev).active = ETH_64_POOLS;
1335                 break;
1336         case 4:
1337                 RTE_ETH_DEV_SRIOV(dev).active = ETH_32_POOLS;
1338                 break;
1339         default:
1340                 return -EINVAL;
1341         }
1342
1343         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool =
1344                 TXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
1345         RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx =
1346                 pci_dev->max_vfs * RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
1347         return 0;
1348 }
1349
1350 static int
1351 txgbe_check_mq_mode(struct rte_eth_dev *dev)
1352 {
1353         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
1354         uint16_t nb_rx_q = dev->data->nb_rx_queues;
1355         uint16_t nb_tx_q = dev->data->nb_tx_queues;
1356
1357         if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
1358                 /* check multi-queue mode */
1359                 switch (dev_conf->rxmode.mq_mode) {
1360                 case ETH_MQ_RX_VMDQ_DCB:
1361                         PMD_INIT_LOG(INFO, "ETH_MQ_RX_VMDQ_DCB mode supported in SRIOV");
1362                         break;
1363                 case ETH_MQ_RX_VMDQ_DCB_RSS:
1364                         /* DCB/RSS VMDQ in SRIOV mode, not implement yet */
1365                         PMD_INIT_LOG(ERR, "SRIOV active,"
1366                                         " unsupported mq_mode rx %d.",
1367                                         dev_conf->rxmode.mq_mode);
1368                         return -EINVAL;
1369                 case ETH_MQ_RX_RSS:
1370                 case ETH_MQ_RX_VMDQ_RSS:
1371                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_RSS;
1372                         if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)
1373                                 if (txgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) {
1374                                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1375                                                 " invalid queue number"
1376                                                 " for VMDQ RSS, allowed"
1377                                                 " value are 1, 2 or 4.");
1378                                         return -EINVAL;
1379                                 }
1380                         break;
1381                 case ETH_MQ_RX_VMDQ_ONLY:
1382                 case ETH_MQ_RX_NONE:
1383                         /* if nothing mq mode configure, use default scheme */
1384                         dev->data->dev_conf.rxmode.mq_mode =
1385                                 ETH_MQ_RX_VMDQ_ONLY;
1386                         break;
1387                 default: /* ETH_MQ_RX_DCB, ETH_MQ_RX_DCB_RSS or ETH_MQ_TX_DCB*/
1388                         /* SRIOV only works in VMDq enable mode */
1389                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1390                                         " wrong mq_mode rx %d.",
1391                                         dev_conf->rxmode.mq_mode);
1392                         return -EINVAL;
1393                 }
1394
1395                 switch (dev_conf->txmode.mq_mode) {
1396                 case ETH_MQ_TX_VMDQ_DCB:
1397                         PMD_INIT_LOG(INFO, "ETH_MQ_TX_VMDQ_DCB mode supported in SRIOV");
1398                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_DCB;
1399                         break;
1400                 default: /* ETH_MQ_TX_VMDQ_ONLY or ETH_MQ_TX_NONE */
1401                         dev->data->dev_conf.txmode.mq_mode =
1402                                 ETH_MQ_TX_VMDQ_ONLY;
1403                         break;
1404                 }
1405
1406                 /* check valid queue number */
1407                 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) ||
1408                     (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) {
1409                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1410                                         " nb_rx_q=%d nb_tx_q=%d queue number"
1411                                         " must be less than or equal to %d.",
1412                                         nb_rx_q, nb_tx_q,
1413                                         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool);
1414                         return -EINVAL;
1415                 }
1416         } else {
1417                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
1418                         PMD_INIT_LOG(ERR, "VMDQ+DCB+RSS mq_mode is"
1419                                           " not supported.");
1420                         return -EINVAL;
1421                 }
1422                 /* check configuration for vmdb+dcb mode */
1423                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB) {
1424                         const struct rte_eth_vmdq_dcb_conf *conf;
1425
1426                         if (nb_rx_q != TXGBE_VMDQ_DCB_NB_QUEUES) {
1427                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.",
1428                                                 TXGBE_VMDQ_DCB_NB_QUEUES);
1429                                 return -EINVAL;
1430                         }
1431                         conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf;
1432                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
1433                                conf->nb_queue_pools == ETH_32_POOLS)) {
1434                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
1435                                                 " nb_queue_pools must be %d or %d.",
1436                                                 ETH_16_POOLS, ETH_32_POOLS);
1437                                 return -EINVAL;
1438                         }
1439                 }
1440                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) {
1441                         const struct rte_eth_vmdq_dcb_tx_conf *conf;
1442
1443                         if (nb_tx_q != TXGBE_VMDQ_DCB_NB_QUEUES) {
1444                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d",
1445                                                  TXGBE_VMDQ_DCB_NB_QUEUES);
1446                                 return -EINVAL;
1447                         }
1448                         conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf;
1449                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
1450                                conf->nb_queue_pools == ETH_32_POOLS)) {
1451                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
1452                                                 " nb_queue_pools != %d and"
1453                                                 " nb_queue_pools != %d.",
1454                                                 ETH_16_POOLS, ETH_32_POOLS);
1455                                 return -EINVAL;
1456                         }
1457                 }
1458
1459                 /* For DCB mode check our configuration before we go further */
1460                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_DCB) {
1461                         const struct rte_eth_dcb_rx_conf *conf;
1462
1463                         conf = &dev_conf->rx_adv_conf.dcb_rx_conf;
1464                         if (!(conf->nb_tcs == ETH_4_TCS ||
1465                                conf->nb_tcs == ETH_8_TCS)) {
1466                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
1467                                                 " and nb_tcs != %d.",
1468                                                 ETH_4_TCS, ETH_8_TCS);
1469                                 return -EINVAL;
1470                         }
1471                 }
1472
1473                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_DCB) {
1474                         const struct rte_eth_dcb_tx_conf *conf;
1475
1476                         conf = &dev_conf->tx_adv_conf.dcb_tx_conf;
1477                         if (!(conf->nb_tcs == ETH_4_TCS ||
1478                                conf->nb_tcs == ETH_8_TCS)) {
1479                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
1480                                                 " and nb_tcs != %d.",
1481                                                 ETH_4_TCS, ETH_8_TCS);
1482                                 return -EINVAL;
1483                         }
1484                 }
1485         }
1486         return 0;
1487 }
1488
1489 static int
1490 txgbe_dev_configure(struct rte_eth_dev *dev)
1491 {
1492         struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);
1493         struct txgbe_adapter *adapter = TXGBE_DEV_ADAPTER(dev);
1494         int ret;
1495
1496         PMD_INIT_FUNC_TRACE();
1497
1498         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
1499                 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
1500
1501         /* multiple queue mode checking */
1502         ret  = txgbe_check_mq_mode(dev);
1503         if (ret != 0) {
1504                 PMD_DRV_LOG(ERR, "txgbe_check_mq_mode fails with %d.",
1505                             ret);
1506                 return ret;
1507         }
1508
1509         /* set flag to update link status after init */
1510         intr->flags |= TXGBE_FLAG_NEED_LINK_UPDATE;
1511
1512         /*
1513          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
1514          * allocation Rx preconditions we will reset it.
1515          */
1516         adapter->rx_bulk_alloc_allowed = true;
1517
1518         return 0;
1519 }
1520
1521 static void
1522 txgbe_dev_phy_intr_setup(struct rte_eth_dev *dev)
1523 {
1524         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
1525         struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);
1526         uint32_t gpie;
1527
1528         gpie = rd32(hw, TXGBE_GPIOINTEN);
1529         gpie |= TXGBE_GPIOBIT_6;
1530         wr32(hw, TXGBE_GPIOINTEN, gpie);
1531         intr->mask_misc |= TXGBE_ICRMISC_GPIO;
1532         intr->mask_misc |= TXGBE_ICRMISC_ANDONE;
1533 }
1534
1535 int
1536 txgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
1537                         uint16_t tx_rate, uint64_t q_msk)
1538 {
1539         struct txgbe_hw *hw;
1540         struct txgbe_vf_info *vfinfo;
1541         struct rte_eth_link link;
1542         uint8_t  nb_q_per_pool;
1543         uint32_t queue_stride;
1544         uint32_t queue_idx, idx = 0, vf_idx;
1545         uint32_t queue_end;
1546         uint16_t total_rate = 0;
1547         struct rte_pci_device *pci_dev;
1548         int ret;
1549
1550         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1551         ret = rte_eth_link_get_nowait(dev->data->port_id, &link);
1552         if (ret < 0)
1553                 return ret;
1554
1555         if (vf >= pci_dev->max_vfs)
1556                 return -EINVAL;
1557
1558         if (tx_rate > link.link_speed)
1559                 return -EINVAL;
1560
1561         if (q_msk == 0)
1562                 return 0;
1563
1564         hw = TXGBE_DEV_HW(dev);
1565         vfinfo = *(TXGBE_DEV_VFDATA(dev));
1566         nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
1567         queue_stride = TXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
1568         queue_idx = vf * queue_stride;
1569         queue_end = queue_idx + nb_q_per_pool - 1;
1570         if (queue_end >= hw->mac.max_tx_queues)
1571                 return -EINVAL;
1572
1573         if (vfinfo) {
1574                 for (vf_idx = 0; vf_idx < pci_dev->max_vfs; vf_idx++) {
1575                         if (vf_idx == vf)
1576                                 continue;
1577                         for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
1578                                 idx++)
1579                                 total_rate += vfinfo[vf_idx].tx_rate[idx];
1580                 }
1581         } else {
1582                 return -EINVAL;
1583         }
1584
1585         /* Store tx_rate for this vf. */
1586         for (idx = 0; idx < nb_q_per_pool; idx++) {
1587                 if (((uint64_t)0x1 << idx) & q_msk) {
1588                         if (vfinfo[vf].tx_rate[idx] != tx_rate)
1589                                 vfinfo[vf].tx_rate[idx] = tx_rate;
1590                         total_rate += tx_rate;
1591                 }
1592         }
1593
1594         if (total_rate > dev->data->dev_link.link_speed) {
1595                 /* Reset stored TX rate of the VF if it causes exceed
1596                  * link speed.
1597                  */
1598                 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
1599                 return -EINVAL;
1600         }
1601
1602         /* Set ARBTXRATE of each queue/pool for vf X  */
1603         for (; queue_idx <= queue_end; queue_idx++) {
1604                 if (0x1 & q_msk)
1605                         txgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
1606                 q_msk = q_msk >> 1;
1607         }
1608
1609         return 0;
1610 }
1611
1612 /*
1613  * Configure device link speed and setup link.
1614  * It returns 0 on success.
1615  */
1616 static int
1617 txgbe_dev_start(struct rte_eth_dev *dev)
1618 {
1619         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
1620         struct txgbe_hw_stats *hw_stats = TXGBE_DEV_STATS(dev);
1621         struct txgbe_vf_info *vfinfo = *TXGBE_DEV_VFDATA(dev);
1622         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1623         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1624         uint32_t intr_vector = 0;
1625         int err;
1626         bool link_up = false, negotiate = 0;
1627         uint32_t speed = 0;
1628         uint32_t allowed_speeds = 0;
1629         int mask = 0;
1630         int status;
1631         uint16_t vf, idx;
1632         uint32_t *link_speeds;
1633         struct txgbe_tm_conf *tm_conf = TXGBE_DEV_TM_CONF(dev);
1634
1635         PMD_INIT_FUNC_TRACE();
1636
1637         /* TXGBE devices don't support:
1638          *    - half duplex (checked afterwards for valid speeds)
1639          *    - fixed speed: TODO implement
1640          */
1641         if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
1642                 PMD_INIT_LOG(ERR,
1643                 "Invalid link_speeds for port %u, fix speed not supported",
1644                                 dev->data->port_id);
1645                 return -EINVAL;
1646         }
1647
1648         /* Stop the link setup handler before resetting the HW. */
1649         rte_eal_alarm_cancel(txgbe_dev_setup_link_alarm_handler, dev);
1650
1651         /* disable uio/vfio intr/eventfd mapping */
1652         rte_intr_disable(intr_handle);
1653
1654         /* stop adapter */
1655         hw->adapter_stopped = 0;
1656         txgbe_stop_hw(hw);
1657
1658         /* reinitialize adapter
1659          * this calls reset and start
1660          */
1661         hw->nb_rx_queues = dev->data->nb_rx_queues;
1662         hw->nb_tx_queues = dev->data->nb_tx_queues;
1663         status = txgbe_pf_reset_hw(hw);
1664         if (status != 0)
1665                 return -1;
1666         hw->mac.start_hw(hw);
1667         hw->mac.get_link_status = true;
1668         hw->dev_start = true;
1669
1670         /* configure PF module if SRIOV enabled */
1671         txgbe_pf_host_configure(dev);
1672
1673         txgbe_dev_phy_intr_setup(dev);
1674
1675         /* check and configure queue intr-vector mapping */
1676         if ((rte_intr_cap_multiple(intr_handle) ||
1677              !RTE_ETH_DEV_SRIOV(dev).active) &&
1678             dev->data->dev_conf.intr_conf.rxq != 0) {
1679                 intr_vector = dev->data->nb_rx_queues;
1680                 if (rte_intr_efd_enable(intr_handle, intr_vector))
1681                         return -1;
1682         }
1683
1684         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1685                 intr_handle->intr_vec =
1686                         rte_zmalloc("intr_vec",
1687                                     dev->data->nb_rx_queues * sizeof(int), 0);
1688                 if (intr_handle->intr_vec == NULL) {
1689                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
1690                                      " intr_vec", dev->data->nb_rx_queues);
1691                         return -ENOMEM;
1692                 }
1693         }
1694
1695         /* confiugre msix for sleep until rx interrupt */
1696         txgbe_configure_msix(dev);
1697
1698         /* initialize transmission unit */
1699         txgbe_dev_tx_init(dev);
1700
1701         /* This can fail when allocating mbufs for descriptor rings */
1702         err = txgbe_dev_rx_init(dev);
1703         if (err) {
1704                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
1705                 goto error;
1706         }
1707
1708         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
1709                 ETH_VLAN_EXTEND_MASK;
1710         err = txgbe_vlan_offload_config(dev, mask);
1711         if (err) {
1712                 PMD_INIT_LOG(ERR, "Unable to set VLAN offload");
1713                 goto error;
1714         }
1715
1716         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1717                 /* Enable vlan filtering for VMDq */
1718                 txgbe_vmdq_vlan_hw_filter_enable(dev);
1719         }
1720
1721         /* Configure DCB hw */
1722         txgbe_configure_pb(dev);
1723         txgbe_configure_port(dev);
1724         txgbe_configure_dcb(dev);
1725
1726         if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
1727                 err = txgbe_fdir_configure(dev);
1728                 if (err)
1729                         goto error;
1730         }
1731
1732         /* Restore vf rate limit */
1733         if (vfinfo != NULL) {
1734                 for (vf = 0; vf < pci_dev->max_vfs; vf++)
1735                         for (idx = 0; idx < TXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
1736                                 if (vfinfo[vf].tx_rate[idx] != 0)
1737                                         txgbe_set_vf_rate_limit(dev, vf,
1738                                                 vfinfo[vf].tx_rate[idx],
1739                                                 1 << idx);
1740         }
1741
1742         err = txgbe_dev_rxtx_start(dev);
1743         if (err < 0) {
1744                 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
1745                 goto error;
1746         }
1747
1748         /* Skip link setup if loopback mode is enabled. */
1749         if (hw->mac.type == txgbe_mac_raptor &&
1750             dev->data->dev_conf.lpbk_mode)
1751                 goto skip_link_setup;
1752
1753         if (txgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
1754                 err = hw->mac.setup_sfp(hw);
1755                 if (err)
1756                         goto error;
1757         }
1758
1759         if (hw->phy.media_type == txgbe_media_type_copper) {
1760                 /* Turn on the copper */
1761                 hw->phy.set_phy_power(hw, true);
1762         } else {
1763                 /* Turn on the laser */
1764                 hw->mac.enable_tx_laser(hw);
1765         }
1766
1767         if ((hw->subsystem_device_id & 0xFF) != TXGBE_DEV_ID_KR_KX_KX4)
1768                 err = hw->mac.check_link(hw, &speed, &link_up, 0);
1769         if (err)
1770                 goto error;
1771         dev->data->dev_link.link_status = link_up;
1772
1773         err = hw->mac.get_link_capabilities(hw, &speed, &negotiate);
1774         if (err)
1775                 goto error;
1776
1777         allowed_speeds = ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
1778                         ETH_LINK_SPEED_10G;
1779
1780         link_speeds = &dev->data->dev_conf.link_speeds;
1781         if (*link_speeds & ~allowed_speeds) {
1782                 PMD_INIT_LOG(ERR, "Invalid link setting");
1783                 goto error;
1784         }
1785
1786         speed = 0x0;
1787         if (*link_speeds == ETH_LINK_SPEED_AUTONEG) {
1788                 speed = (TXGBE_LINK_SPEED_100M_FULL |
1789                          TXGBE_LINK_SPEED_1GB_FULL |
1790                          TXGBE_LINK_SPEED_10GB_FULL);
1791         } else {
1792                 if (*link_speeds & ETH_LINK_SPEED_10G)
1793                         speed |= TXGBE_LINK_SPEED_10GB_FULL;
1794                 if (*link_speeds & ETH_LINK_SPEED_5G)
1795                         speed |= TXGBE_LINK_SPEED_5GB_FULL;
1796                 if (*link_speeds & ETH_LINK_SPEED_2_5G)
1797                         speed |= TXGBE_LINK_SPEED_2_5GB_FULL;
1798                 if (*link_speeds & ETH_LINK_SPEED_1G)
1799                         speed |= TXGBE_LINK_SPEED_1GB_FULL;
1800                 if (*link_speeds & ETH_LINK_SPEED_100M)
1801                         speed |= TXGBE_LINK_SPEED_100M_FULL;
1802         }
1803
1804         err = hw->mac.setup_link(hw, speed, link_up);
1805         if (err)
1806                 goto error;
1807
1808 skip_link_setup:
1809
1810         if (rte_intr_allow_others(intr_handle)) {
1811                 txgbe_dev_misc_interrupt_setup(dev);
1812                 /* check if lsc interrupt is enabled */
1813                 if (dev->data->dev_conf.intr_conf.lsc != 0)
1814                         txgbe_dev_lsc_interrupt_setup(dev, TRUE);
1815                 else
1816                         txgbe_dev_lsc_interrupt_setup(dev, FALSE);
1817                 txgbe_dev_macsec_interrupt_setup(dev);
1818                 txgbe_set_ivar_map(hw, -1, 1, TXGBE_MISC_VEC_ID);
1819         } else {
1820                 rte_intr_callback_unregister(intr_handle,
1821                                              txgbe_dev_interrupt_handler, dev);
1822                 if (dev->data->dev_conf.intr_conf.lsc != 0)
1823                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
1824                                      " no intr multiplex");
1825         }
1826
1827         /* check if rxq interrupt is enabled */
1828         if (dev->data->dev_conf.intr_conf.rxq != 0 &&
1829             rte_intr_dp_is_en(intr_handle))
1830                 txgbe_dev_rxq_interrupt_setup(dev);
1831
1832         /* enable uio/vfio intr/eventfd mapping */
1833         rte_intr_enable(intr_handle);
1834
1835         /* resume enabled intr since hw reset */
1836         txgbe_enable_intr(dev);
1837         txgbe_l2_tunnel_conf(dev);
1838         txgbe_filter_restore(dev);
1839
1840         if (tm_conf->root && !tm_conf->committed)
1841                 PMD_DRV_LOG(WARNING,
1842                             "please call hierarchy_commit() "
1843                             "before starting the port");
1844
1845         /*
1846          * Update link status right before return, because it may
1847          * start link configuration process in a separate thread.
1848          */
1849         txgbe_dev_link_update(dev, 0);
1850
1851         wr32m(hw, TXGBE_LEDCTL, 0xFFFFFFFF, TXGBE_LEDCTL_ORD_MASK);
1852
1853         txgbe_read_stats_registers(hw, hw_stats);
1854         hw->offset_loaded = 1;
1855
1856         return 0;
1857
1858 error:
1859         PMD_INIT_LOG(ERR, "failure in dev start: %d", err);
1860         txgbe_dev_clear_queues(dev);
1861         return -EIO;
1862 }
1863
1864 /*
1865  * Stop device: disable rx and tx functions to allow for reconfiguring.
1866  */
1867 static int
1868 txgbe_dev_stop(struct rte_eth_dev *dev)
1869 {
1870         struct rte_eth_link link;
1871         struct txgbe_adapter *adapter = TXGBE_DEV_ADAPTER(dev);
1872         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
1873         struct txgbe_vf_info *vfinfo = *TXGBE_DEV_VFDATA(dev);
1874         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1875         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1876         int vf;
1877         struct txgbe_tm_conf *tm_conf = TXGBE_DEV_TM_CONF(dev);
1878
1879         if (hw->adapter_stopped)
1880                 return 0;
1881
1882         PMD_INIT_FUNC_TRACE();
1883
1884         rte_eal_alarm_cancel(txgbe_dev_setup_link_alarm_handler, dev);
1885
1886         /* disable interrupts */
1887         txgbe_disable_intr(hw);
1888
1889         /* reset the NIC */
1890         txgbe_pf_reset_hw(hw);
1891         hw->adapter_stopped = 0;
1892
1893         /* stop adapter */
1894         txgbe_stop_hw(hw);
1895
1896         for (vf = 0; vfinfo != NULL && vf < pci_dev->max_vfs; vf++)
1897                 vfinfo[vf].clear_to_send = false;
1898
1899         if (hw->phy.media_type == txgbe_media_type_copper) {
1900                 /* Turn off the copper */
1901                 hw->phy.set_phy_power(hw, false);
1902         } else {
1903                 /* Turn off the laser */
1904                 hw->mac.disable_tx_laser(hw);
1905         }
1906
1907         txgbe_dev_clear_queues(dev);
1908
1909         /* Clear stored conf */
1910         dev->data->scattered_rx = 0;
1911         dev->data->lro = 0;
1912
1913         /* Clear recorded link status */
1914         memset(&link, 0, sizeof(link));
1915         rte_eth_linkstatus_set(dev, &link);
1916
1917         if (!rte_intr_allow_others(intr_handle))
1918                 /* resume to the default handler */
1919                 rte_intr_callback_register(intr_handle,
1920                                            txgbe_dev_interrupt_handler,
1921                                            (void *)dev);
1922
1923         /* Clean datapath event and queue/vec mapping */
1924         rte_intr_efd_disable(intr_handle);
1925         if (intr_handle->intr_vec != NULL) {
1926                 rte_free(intr_handle->intr_vec);
1927                 intr_handle->intr_vec = NULL;
1928         }
1929
1930         /* reset hierarchy commit */
1931         tm_conf->committed = false;
1932
1933         adapter->rss_reta_updated = 0;
1934         wr32m(hw, TXGBE_LEDCTL, 0xFFFFFFFF, TXGBE_LEDCTL_SEL_MASK);
1935
1936         hw->adapter_stopped = true;
1937         dev->data->dev_started = 0;
1938         hw->dev_start = false;
1939
1940         return 0;
1941 }
1942
1943 /*
1944  * Set device link up: enable tx.
1945  */
1946 static int
1947 txgbe_dev_set_link_up(struct rte_eth_dev *dev)
1948 {
1949         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
1950
1951         if (hw->phy.media_type == txgbe_media_type_copper) {
1952                 /* Turn on the copper */
1953                 hw->phy.set_phy_power(hw, true);
1954         } else {
1955                 /* Turn on the laser */
1956                 hw->mac.enable_tx_laser(hw);
1957                 txgbe_dev_link_update(dev, 0);
1958         }
1959
1960         return 0;
1961 }
1962
1963 /*
1964  * Set device link down: disable tx.
1965  */
1966 static int
1967 txgbe_dev_set_link_down(struct rte_eth_dev *dev)
1968 {
1969         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
1970
1971         if (hw->phy.media_type == txgbe_media_type_copper) {
1972                 /* Turn off the copper */
1973                 hw->phy.set_phy_power(hw, false);
1974         } else {
1975                 /* Turn off the laser */
1976                 hw->mac.disable_tx_laser(hw);
1977                 txgbe_dev_link_update(dev, 0);
1978         }
1979
1980         return 0;
1981 }
1982
1983 /*
1984  * Reset and stop device.
1985  */
1986 static int
1987 txgbe_dev_close(struct rte_eth_dev *dev)
1988 {
1989         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
1990         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1991         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1992         int retries = 0;
1993         int ret;
1994
1995         PMD_INIT_FUNC_TRACE();
1996
1997         txgbe_pf_reset_hw(hw);
1998
1999         ret = txgbe_dev_stop(dev);
2000
2001         txgbe_dev_free_queues(dev);
2002
2003         /* reprogram the RAR[0] in case user changed it. */
2004         txgbe_set_rar(hw, 0, hw->mac.addr, 0, true);
2005
2006         /* Unlock any pending hardware semaphore */
2007         txgbe_swfw_lock_reset(hw);
2008
2009         /* disable uio intr before callback unregister */
2010         rte_intr_disable(intr_handle);
2011
2012         do {
2013                 ret = rte_intr_callback_unregister(intr_handle,
2014                                 txgbe_dev_interrupt_handler, dev);
2015                 if (ret >= 0 || ret == -ENOENT) {
2016                         break;
2017                 } else if (ret != -EAGAIN) {
2018                         PMD_INIT_LOG(ERR,
2019                                 "intr callback unregister failed: %d",
2020                                 ret);
2021                 }
2022                 rte_delay_ms(100);
2023         } while (retries++ < (10 + TXGBE_LINK_UP_TIME));
2024
2025         /* cancel the delay handler before remove dev */
2026         rte_eal_alarm_cancel(txgbe_dev_interrupt_delayed_handler, dev);
2027
2028         /* uninitialize PF if max_vfs not zero */
2029         txgbe_pf_host_uninit(dev);
2030
2031         rte_free(dev->data->mac_addrs);
2032         dev->data->mac_addrs = NULL;
2033
2034         rte_free(dev->data->hash_mac_addrs);
2035         dev->data->hash_mac_addrs = NULL;
2036
2037         /* remove all the fdir filters & hash */
2038         txgbe_fdir_filter_uninit(dev);
2039
2040         /* remove all the L2 tunnel filters & hash */
2041         txgbe_l2_tn_filter_uninit(dev);
2042
2043         /* Remove all ntuple filters of the device */
2044         txgbe_ntuple_filter_uninit(dev);
2045
2046         /* clear all the filters list */
2047         txgbe_filterlist_flush();
2048
2049         /* Remove all Traffic Manager configuration */
2050         txgbe_tm_conf_uninit(dev);
2051
2052 #ifdef RTE_LIB_SECURITY
2053         rte_free(dev->security_ctx);
2054 #endif
2055
2056         return ret;
2057 }
2058
2059 /*
2060  * Reset PF device.
2061  */
2062 static int
2063 txgbe_dev_reset(struct rte_eth_dev *dev)
2064 {
2065         int ret;
2066
2067         /* When a DPDK PMD PF begin to reset PF port, it should notify all
2068          * its VF to make them align with it. The detailed notification
2069          * mechanism is PMD specific. As to txgbe PF, it is rather complex.
2070          * To avoid unexpected behavior in VF, currently reset of PF with
2071          * SR-IOV activation is not supported. It might be supported later.
2072          */
2073         if (dev->data->sriov.active)
2074                 return -ENOTSUP;
2075
2076         ret = eth_txgbe_dev_uninit(dev);
2077         if (ret)
2078                 return ret;
2079
2080         ret = eth_txgbe_dev_init(dev, NULL);
2081
2082         return ret;
2083 }
2084
2085 #define UPDATE_QP_COUNTER_32bit(reg, last_counter, counter)     \
2086         {                                                       \
2087                 uint32_t current_counter = rd32(hw, reg);       \
2088                 if (current_counter < last_counter)             \
2089                         current_counter += 0x100000000LL;       \
2090                 if (!hw->offset_loaded)                         \
2091                         last_counter = current_counter;         \
2092                 counter = current_counter - last_counter;       \
2093                 counter &= 0xFFFFFFFFLL;                        \
2094         }
2095
2096 #define UPDATE_QP_COUNTER_36bit(reg_lsb, reg_msb, last_counter, counter) \
2097         {                                                                \
2098                 uint64_t current_counter_lsb = rd32(hw, reg_lsb);        \
2099                 uint64_t current_counter_msb = rd32(hw, reg_msb);        \
2100                 uint64_t current_counter = (current_counter_msb << 32) | \
2101                         current_counter_lsb;                             \
2102                 if (current_counter < last_counter)                      \
2103                         current_counter += 0x1000000000LL;               \
2104                 if (!hw->offset_loaded)                                  \
2105                         last_counter = current_counter;                  \
2106                 counter = current_counter - last_counter;                \
2107                 counter &= 0xFFFFFFFFFLL;                                \
2108         }
2109
2110 void
2111 txgbe_read_stats_registers(struct txgbe_hw *hw,
2112                            struct txgbe_hw_stats *hw_stats)
2113 {
2114         unsigned int i;
2115
2116         /* QP Stats */
2117         for (i = 0; i < hw->nb_rx_queues; i++) {
2118                 UPDATE_QP_COUNTER_32bit(TXGBE_QPRXPKT(i),
2119                         hw->qp_last[i].rx_qp_packets,
2120                         hw_stats->qp[i].rx_qp_packets);
2121                 UPDATE_QP_COUNTER_36bit(TXGBE_QPRXOCTL(i), TXGBE_QPRXOCTH(i),
2122                         hw->qp_last[i].rx_qp_bytes,
2123                         hw_stats->qp[i].rx_qp_bytes);
2124                 UPDATE_QP_COUNTER_32bit(TXGBE_QPRXMPKT(i),
2125                         hw->qp_last[i].rx_qp_mc_packets,
2126                         hw_stats->qp[i].rx_qp_mc_packets);
2127         }
2128
2129         for (i = 0; i < hw->nb_tx_queues; i++) {
2130                 UPDATE_QP_COUNTER_32bit(TXGBE_QPTXPKT(i),
2131                         hw->qp_last[i].tx_qp_packets,
2132                         hw_stats->qp[i].tx_qp_packets);
2133                 UPDATE_QP_COUNTER_36bit(TXGBE_QPTXOCTL(i), TXGBE_QPTXOCTH(i),
2134                         hw->qp_last[i].tx_qp_bytes,
2135                         hw_stats->qp[i].tx_qp_bytes);
2136         }
2137         /* PB Stats */
2138         for (i = 0; i < TXGBE_MAX_UP; i++) {
2139                 hw_stats->up[i].rx_up_xon_packets +=
2140                                 rd32(hw, TXGBE_PBRXUPXON(i));
2141                 hw_stats->up[i].rx_up_xoff_packets +=
2142                                 rd32(hw, TXGBE_PBRXUPXOFF(i));
2143                 hw_stats->up[i].tx_up_xon_packets +=
2144                                 rd32(hw, TXGBE_PBTXUPXON(i));
2145                 hw_stats->up[i].tx_up_xoff_packets +=
2146                                 rd32(hw, TXGBE_PBTXUPXOFF(i));
2147                 hw_stats->up[i].tx_up_xon2off_packets +=
2148                                 rd32(hw, TXGBE_PBTXUPOFF(i));
2149                 hw_stats->up[i].rx_up_dropped +=
2150                                 rd32(hw, TXGBE_PBRXMISS(i));
2151         }
2152         hw_stats->rx_xon_packets += rd32(hw, TXGBE_PBRXLNKXON);
2153         hw_stats->rx_xoff_packets += rd32(hw, TXGBE_PBRXLNKXOFF);
2154         hw_stats->tx_xon_packets += rd32(hw, TXGBE_PBTXLNKXON);
2155         hw_stats->tx_xoff_packets += rd32(hw, TXGBE_PBTXLNKXOFF);
2156
2157         /* DMA Stats */
2158         hw_stats->rx_packets += rd32(hw, TXGBE_DMARXPKT);
2159         hw_stats->tx_packets += rd32(hw, TXGBE_DMATXPKT);
2160
2161         hw_stats->rx_bytes += rd64(hw, TXGBE_DMARXOCTL);
2162         hw_stats->tx_bytes += rd64(hw, TXGBE_DMATXOCTL);
2163         hw_stats->rx_dma_drop += rd32(hw, TXGBE_DMARXDROP);
2164         hw_stats->rx_drop_packets += rd32(hw, TXGBE_PBRXDROP);
2165
2166         /* MAC Stats */
2167         hw_stats->rx_crc_errors += rd64(hw, TXGBE_MACRXERRCRCL);
2168         hw_stats->rx_multicast_packets += rd64(hw, TXGBE_MACRXMPKTL);
2169         hw_stats->tx_multicast_packets += rd64(hw, TXGBE_MACTXMPKTL);
2170
2171         hw_stats->rx_total_packets += rd64(hw, TXGBE_MACRXPKTL);
2172         hw_stats->tx_total_packets += rd64(hw, TXGBE_MACTXPKTL);
2173         hw_stats->rx_total_bytes += rd64(hw, TXGBE_MACRXGBOCTL);
2174
2175         hw_stats->rx_broadcast_packets += rd64(hw, TXGBE_MACRXOCTL);
2176         hw_stats->tx_broadcast_packets += rd32(hw, TXGBE_MACTXOCTL);
2177
2178         hw_stats->rx_size_64_packets += rd64(hw, TXGBE_MACRX1TO64L);
2179         hw_stats->rx_size_65_to_127_packets += rd64(hw, TXGBE_MACRX65TO127L);
2180         hw_stats->rx_size_128_to_255_packets += rd64(hw, TXGBE_MACRX128TO255L);
2181         hw_stats->rx_size_256_to_511_packets += rd64(hw, TXGBE_MACRX256TO511L);
2182         hw_stats->rx_size_512_to_1023_packets +=
2183                         rd64(hw, TXGBE_MACRX512TO1023L);
2184         hw_stats->rx_size_1024_to_max_packets +=
2185                         rd64(hw, TXGBE_MACRX1024TOMAXL);
2186         hw_stats->tx_size_64_packets += rd64(hw, TXGBE_MACTX1TO64L);
2187         hw_stats->tx_size_65_to_127_packets += rd64(hw, TXGBE_MACTX65TO127L);
2188         hw_stats->tx_size_128_to_255_packets += rd64(hw, TXGBE_MACTX128TO255L);
2189         hw_stats->tx_size_256_to_511_packets += rd64(hw, TXGBE_MACTX256TO511L);
2190         hw_stats->tx_size_512_to_1023_packets +=
2191                         rd64(hw, TXGBE_MACTX512TO1023L);
2192         hw_stats->tx_size_1024_to_max_packets +=
2193                         rd64(hw, TXGBE_MACTX1024TOMAXL);
2194
2195         hw_stats->rx_undersize_errors += rd64(hw, TXGBE_MACRXERRLENL);
2196         hw_stats->rx_oversize_errors += rd32(hw, TXGBE_MACRXOVERSIZE);
2197         hw_stats->rx_jabber_errors += rd32(hw, TXGBE_MACRXJABBER);
2198
2199         /* MNG Stats */
2200         hw_stats->mng_bmc2host_packets = rd32(hw, TXGBE_MNGBMC2OS);
2201         hw_stats->mng_host2bmc_packets = rd32(hw, TXGBE_MNGOS2BMC);
2202         hw_stats->rx_management_packets = rd32(hw, TXGBE_DMARXMNG);
2203         hw_stats->tx_management_packets = rd32(hw, TXGBE_DMATXMNG);
2204
2205         /* FCoE Stats */
2206         hw_stats->rx_fcoe_crc_errors += rd32(hw, TXGBE_FCOECRC);
2207         hw_stats->rx_fcoe_mbuf_allocation_errors += rd32(hw, TXGBE_FCOELAST);
2208         hw_stats->rx_fcoe_dropped += rd32(hw, TXGBE_FCOERPDC);
2209         hw_stats->rx_fcoe_packets += rd32(hw, TXGBE_FCOEPRC);
2210         hw_stats->tx_fcoe_packets += rd32(hw, TXGBE_FCOEPTC);
2211         hw_stats->rx_fcoe_bytes += rd32(hw, TXGBE_FCOEDWRC);
2212         hw_stats->tx_fcoe_bytes += rd32(hw, TXGBE_FCOEDWTC);
2213
2214         /* Flow Director Stats */
2215         hw_stats->flow_director_matched_filters += rd32(hw, TXGBE_FDIRMATCH);
2216         hw_stats->flow_director_missed_filters += rd32(hw, TXGBE_FDIRMISS);
2217         hw_stats->flow_director_added_filters +=
2218                 TXGBE_FDIRUSED_ADD(rd32(hw, TXGBE_FDIRUSED));
2219         hw_stats->flow_director_removed_filters +=
2220                 TXGBE_FDIRUSED_REM(rd32(hw, TXGBE_FDIRUSED));
2221         hw_stats->flow_director_filter_add_errors +=
2222                 TXGBE_FDIRFAIL_ADD(rd32(hw, TXGBE_FDIRFAIL));
2223         hw_stats->flow_director_filter_remove_errors +=
2224                 TXGBE_FDIRFAIL_REM(rd32(hw, TXGBE_FDIRFAIL));
2225
2226         /* MACsec Stats */
2227         hw_stats->tx_macsec_pkts_untagged += rd32(hw, TXGBE_LSECTX_UTPKT);
2228         hw_stats->tx_macsec_pkts_encrypted +=
2229                         rd32(hw, TXGBE_LSECTX_ENCPKT);
2230         hw_stats->tx_macsec_pkts_protected +=
2231                         rd32(hw, TXGBE_LSECTX_PROTPKT);
2232         hw_stats->tx_macsec_octets_encrypted +=
2233                         rd32(hw, TXGBE_LSECTX_ENCOCT);
2234         hw_stats->tx_macsec_octets_protected +=
2235                         rd32(hw, TXGBE_LSECTX_PROTOCT);
2236         hw_stats->rx_macsec_pkts_untagged += rd32(hw, TXGBE_LSECRX_UTPKT);
2237         hw_stats->rx_macsec_pkts_badtag += rd32(hw, TXGBE_LSECRX_BTPKT);
2238         hw_stats->rx_macsec_pkts_nosci += rd32(hw, TXGBE_LSECRX_NOSCIPKT);
2239         hw_stats->rx_macsec_pkts_unknownsci += rd32(hw, TXGBE_LSECRX_UNSCIPKT);
2240         hw_stats->rx_macsec_octets_decrypted += rd32(hw, TXGBE_LSECRX_DECOCT);
2241         hw_stats->rx_macsec_octets_validated += rd32(hw, TXGBE_LSECRX_VLDOCT);
2242         hw_stats->rx_macsec_sc_pkts_unchecked +=
2243                         rd32(hw, TXGBE_LSECRX_UNCHKPKT);
2244         hw_stats->rx_macsec_sc_pkts_delayed += rd32(hw, TXGBE_LSECRX_DLYPKT);
2245         hw_stats->rx_macsec_sc_pkts_late += rd32(hw, TXGBE_LSECRX_LATEPKT);
2246         for (i = 0; i < 2; i++) {
2247                 hw_stats->rx_macsec_sa_pkts_ok +=
2248                         rd32(hw, TXGBE_LSECRX_OKPKT(i));
2249                 hw_stats->rx_macsec_sa_pkts_invalid +=
2250                         rd32(hw, TXGBE_LSECRX_INVPKT(i));
2251                 hw_stats->rx_macsec_sa_pkts_notvalid +=
2252                         rd32(hw, TXGBE_LSECRX_BADPKT(i));
2253         }
2254         hw_stats->rx_macsec_sa_pkts_unusedsa +=
2255                         rd32(hw, TXGBE_LSECRX_INVSAPKT);
2256         hw_stats->rx_macsec_sa_pkts_notusingsa +=
2257                         rd32(hw, TXGBE_LSECRX_BADSAPKT);
2258
2259         hw_stats->rx_total_missed_packets = 0;
2260         for (i = 0; i < TXGBE_MAX_UP; i++) {
2261                 hw_stats->rx_total_missed_packets +=
2262                         hw_stats->up[i].rx_up_dropped;
2263         }
2264 }
2265
2266 static int
2267 txgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2268 {
2269         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2270         struct txgbe_hw_stats *hw_stats = TXGBE_DEV_STATS(dev);
2271         struct txgbe_stat_mappings *stat_mappings =
2272                         TXGBE_DEV_STAT_MAPPINGS(dev);
2273         uint32_t i, j;
2274
2275         txgbe_read_stats_registers(hw, hw_stats);
2276
2277         if (stats == NULL)
2278                 return -EINVAL;
2279
2280         /* Fill out the rte_eth_stats statistics structure */
2281         stats->ipackets = hw_stats->rx_packets;
2282         stats->ibytes = hw_stats->rx_bytes;
2283         stats->opackets = hw_stats->tx_packets;
2284         stats->obytes = hw_stats->tx_bytes;
2285
2286         memset(&stats->q_ipackets, 0, sizeof(stats->q_ipackets));
2287         memset(&stats->q_opackets, 0, sizeof(stats->q_opackets));
2288         memset(&stats->q_ibytes, 0, sizeof(stats->q_ibytes));
2289         memset(&stats->q_obytes, 0, sizeof(stats->q_obytes));
2290         memset(&stats->q_errors, 0, sizeof(stats->q_errors));
2291         for (i = 0; i < TXGBE_MAX_QP; i++) {
2292                 uint32_t n = i / NB_QMAP_FIELDS_PER_QSM_REG;
2293                 uint32_t offset = (i % NB_QMAP_FIELDS_PER_QSM_REG) * 8;
2294                 uint32_t q_map;
2295
2296                 q_map = (stat_mappings->rqsm[n] >> offset)
2297                                 & QMAP_FIELD_RESERVED_BITS_MASK;
2298                 j = (q_map < RTE_ETHDEV_QUEUE_STAT_CNTRS
2299                      ? q_map : q_map % RTE_ETHDEV_QUEUE_STAT_CNTRS);
2300                 stats->q_ipackets[j] += hw_stats->qp[i].rx_qp_packets;
2301                 stats->q_ibytes[j] += hw_stats->qp[i].rx_qp_bytes;
2302
2303                 q_map = (stat_mappings->tqsm[n] >> offset)
2304                                 & QMAP_FIELD_RESERVED_BITS_MASK;
2305                 j = (q_map < RTE_ETHDEV_QUEUE_STAT_CNTRS
2306                      ? q_map : q_map % RTE_ETHDEV_QUEUE_STAT_CNTRS);
2307                 stats->q_opackets[j] += hw_stats->qp[i].tx_qp_packets;
2308                 stats->q_obytes[j] += hw_stats->qp[i].tx_qp_bytes;
2309         }
2310
2311         /* Rx Errors */
2312         stats->imissed  = hw_stats->rx_total_missed_packets +
2313                           hw_stats->rx_dma_drop;
2314         stats->ierrors  = hw_stats->rx_crc_errors +
2315                           hw_stats->rx_mac_short_packet_dropped +
2316                           hw_stats->rx_length_errors +
2317                           hw_stats->rx_undersize_errors +
2318                           hw_stats->rx_oversize_errors +
2319                           hw_stats->rx_drop_packets +
2320                           hw_stats->rx_illegal_byte_errors +
2321                           hw_stats->rx_error_bytes +
2322                           hw_stats->rx_fragment_errors +
2323                           hw_stats->rx_fcoe_crc_errors +
2324                           hw_stats->rx_fcoe_mbuf_allocation_errors;
2325
2326         /* Tx Errors */
2327         stats->oerrors  = 0;
2328         return 0;
2329 }
2330
2331 static int
2332 txgbe_dev_stats_reset(struct rte_eth_dev *dev)
2333 {
2334         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2335         struct txgbe_hw_stats *hw_stats = TXGBE_DEV_STATS(dev);
2336
2337         /* HW registers are cleared on read */
2338         hw->offset_loaded = 0;
2339         txgbe_dev_stats_get(dev, NULL);
2340         hw->offset_loaded = 1;
2341
2342         /* Reset software totals */
2343         memset(hw_stats, 0, sizeof(*hw_stats));
2344
2345         return 0;
2346 }
2347
2348 /* This function calculates the number of xstats based on the current config */
2349 static unsigned
2350 txgbe_xstats_calc_num(struct rte_eth_dev *dev)
2351 {
2352         int nb_queues = max(dev->data->nb_rx_queues, dev->data->nb_tx_queues);
2353         return TXGBE_NB_HW_STATS +
2354                TXGBE_NB_UP_STATS * TXGBE_MAX_UP +
2355                TXGBE_NB_QP_STATS * nb_queues;
2356 }
2357
2358 static inline int
2359 txgbe_get_name_by_id(uint32_t id, char *name, uint32_t size)
2360 {
2361         int nb, st;
2362
2363         /* Extended stats from txgbe_hw_stats */
2364         if (id < TXGBE_NB_HW_STATS) {
2365                 snprintf(name, size, "[hw]%s",
2366                         rte_txgbe_stats_strings[id].name);
2367                 return 0;
2368         }
2369         id -= TXGBE_NB_HW_STATS;
2370
2371         /* Priority Stats */
2372         if (id < TXGBE_NB_UP_STATS * TXGBE_MAX_UP) {
2373                 nb = id / TXGBE_NB_UP_STATS;
2374                 st = id % TXGBE_NB_UP_STATS;
2375                 snprintf(name, size, "[p%u]%s", nb,
2376                         rte_txgbe_up_strings[st].name);
2377                 return 0;
2378         }
2379         id -= TXGBE_NB_UP_STATS * TXGBE_MAX_UP;
2380
2381         /* Queue Stats */
2382         if (id < TXGBE_NB_QP_STATS * TXGBE_MAX_QP) {
2383                 nb = id / TXGBE_NB_QP_STATS;
2384                 st = id % TXGBE_NB_QP_STATS;
2385                 snprintf(name, size, "[q%u]%s", nb,
2386                         rte_txgbe_qp_strings[st].name);
2387                 return 0;
2388         }
2389         id -= TXGBE_NB_QP_STATS * TXGBE_MAX_QP;
2390
2391         return -(int)(id + 1);
2392 }
2393
2394 static inline int
2395 txgbe_get_offset_by_id(uint32_t id, uint32_t *offset)
2396 {
2397         int nb, st;
2398
2399         /* Extended stats from txgbe_hw_stats */
2400         if (id < TXGBE_NB_HW_STATS) {
2401                 *offset = rte_txgbe_stats_strings[id].offset;
2402                 return 0;
2403         }
2404         id -= TXGBE_NB_HW_STATS;
2405
2406         /* Priority Stats */
2407         if (id < TXGBE_NB_UP_STATS * TXGBE_MAX_UP) {
2408                 nb = id / TXGBE_NB_UP_STATS;
2409                 st = id % TXGBE_NB_UP_STATS;
2410                 *offset = rte_txgbe_up_strings[st].offset +
2411                         nb * (TXGBE_NB_UP_STATS * sizeof(uint64_t));
2412                 return 0;
2413         }
2414         id -= TXGBE_NB_UP_STATS * TXGBE_MAX_UP;
2415
2416         /* Queue Stats */
2417         if (id < TXGBE_NB_QP_STATS * TXGBE_MAX_QP) {
2418                 nb = id / TXGBE_NB_QP_STATS;
2419                 st = id % TXGBE_NB_QP_STATS;
2420                 *offset = rte_txgbe_qp_strings[st].offset +
2421                         nb * (TXGBE_NB_QP_STATS * sizeof(uint64_t));
2422                 return 0;
2423         }
2424
2425         return -1;
2426 }
2427
2428 static int txgbe_dev_xstats_get_names(struct rte_eth_dev *dev,
2429         struct rte_eth_xstat_name *xstats_names, unsigned int limit)
2430 {
2431         unsigned int i, count;
2432
2433         count = txgbe_xstats_calc_num(dev);
2434         if (xstats_names == NULL)
2435                 return count;
2436
2437         /* Note: limit >= cnt_stats checked upstream
2438          * in rte_eth_xstats_names()
2439          */
2440         limit = min(limit, count);
2441
2442         /* Extended stats from txgbe_hw_stats */
2443         for (i = 0; i < limit; i++) {
2444                 if (txgbe_get_name_by_id(i, xstats_names[i].name,
2445                         sizeof(xstats_names[i].name))) {
2446                         PMD_INIT_LOG(WARNING, "id value %d isn't valid", i);
2447                         break;
2448                 }
2449         }
2450
2451         return i;
2452 }
2453
2454 static int txgbe_dev_xstats_get_names_by_id(struct rte_eth_dev *dev,
2455         const uint64_t *ids,
2456         struct rte_eth_xstat_name *xstats_names,
2457         unsigned int limit)
2458 {
2459         unsigned int i;
2460
2461         if (ids == NULL)
2462                 return txgbe_dev_xstats_get_names(dev, xstats_names, limit);
2463
2464         for (i = 0; i < limit; i++) {
2465                 if (txgbe_get_name_by_id(ids[i], xstats_names[i].name,
2466                                 sizeof(xstats_names[i].name))) {
2467                         PMD_INIT_LOG(WARNING, "id value %d isn't valid", i);
2468                         return -1;
2469                 }
2470         }
2471
2472         return i;
2473 }
2474
2475 static int
2476 txgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2477                                          unsigned int limit)
2478 {
2479         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2480         struct txgbe_hw_stats *hw_stats = TXGBE_DEV_STATS(dev);
2481         unsigned int i, count;
2482
2483         txgbe_read_stats_registers(hw, hw_stats);
2484
2485         /* If this is a reset xstats is NULL, and we have cleared the
2486          * registers by reading them.
2487          */
2488         count = txgbe_xstats_calc_num(dev);
2489         if (xstats == NULL)
2490                 return count;
2491
2492         limit = min(limit, txgbe_xstats_calc_num(dev));
2493
2494         /* Extended stats from txgbe_hw_stats */
2495         for (i = 0; i < limit; i++) {
2496                 uint32_t offset = 0;
2497
2498                 if (txgbe_get_offset_by_id(i, &offset)) {
2499                         PMD_INIT_LOG(WARNING, "id value %d isn't valid", i);
2500                         break;
2501                 }
2502                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) + offset);
2503                 xstats[i].id = i;
2504         }
2505
2506         return i;
2507 }
2508
2509 static int
2510 txgbe_dev_xstats_get_(struct rte_eth_dev *dev, uint64_t *values,
2511                                          unsigned int limit)
2512 {
2513         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2514         struct txgbe_hw_stats *hw_stats = TXGBE_DEV_STATS(dev);
2515         unsigned int i, count;
2516
2517         txgbe_read_stats_registers(hw, hw_stats);
2518
2519         /* If this is a reset xstats is NULL, and we have cleared the
2520          * registers by reading them.
2521          */
2522         count = txgbe_xstats_calc_num(dev);
2523         if (values == NULL)
2524                 return count;
2525
2526         limit = min(limit, txgbe_xstats_calc_num(dev));
2527
2528         /* Extended stats from txgbe_hw_stats */
2529         for (i = 0; i < limit; i++) {
2530                 uint32_t offset;
2531
2532                 if (txgbe_get_offset_by_id(i, &offset)) {
2533                         PMD_INIT_LOG(WARNING, "id value %d isn't valid", i);
2534                         break;
2535                 }
2536                 values[i] = *(uint64_t *)(((char *)hw_stats) + offset);
2537         }
2538
2539         return i;
2540 }
2541
2542 static int
2543 txgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
2544                 uint64_t *values, unsigned int limit)
2545 {
2546         struct txgbe_hw_stats *hw_stats = TXGBE_DEV_STATS(dev);
2547         unsigned int i;
2548
2549         if (ids == NULL)
2550                 return txgbe_dev_xstats_get_(dev, values, limit);
2551
2552         for (i = 0; i < limit; i++) {
2553                 uint32_t offset;
2554
2555                 if (txgbe_get_offset_by_id(ids[i], &offset)) {
2556                         PMD_INIT_LOG(WARNING, "id value %d isn't valid", i);
2557                         break;
2558                 }
2559                 values[i] = *(uint64_t *)(((char *)hw_stats) + offset);
2560         }
2561
2562         return i;
2563 }
2564
2565 static int
2566 txgbe_dev_xstats_reset(struct rte_eth_dev *dev)
2567 {
2568         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2569         struct txgbe_hw_stats *hw_stats = TXGBE_DEV_STATS(dev);
2570
2571         /* HW registers are cleared on read */
2572         hw->offset_loaded = 0;
2573         txgbe_read_stats_registers(hw, hw_stats);
2574         hw->offset_loaded = 1;
2575
2576         /* Reset software totals */
2577         memset(hw_stats, 0, sizeof(*hw_stats));
2578
2579         return 0;
2580 }
2581
2582 static int
2583 txgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
2584 {
2585         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2586         u32 etrack_id;
2587         int ret;
2588
2589         hw->phy.get_fw_version(hw, &etrack_id);
2590
2591         ret = snprintf(fw_version, fw_size, "0x%08x", etrack_id);
2592         if (ret < 0)
2593                 return -EINVAL;
2594
2595         ret += 1; /* add the size of '\0' */
2596         if (fw_size < (size_t)ret)
2597                 return ret;
2598         else
2599                 return 0;
2600 }
2601
2602 static int
2603 txgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2604 {
2605         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2606         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2607
2608         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
2609         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
2610         dev_info->min_rx_bufsize = 1024;
2611         dev_info->max_rx_pktlen = 15872;
2612         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
2613         dev_info->max_hash_mac_addrs = TXGBE_VMDQ_NUM_UC_MAC;
2614         dev_info->max_vfs = pci_dev->max_vfs;
2615         dev_info->max_vmdq_pools = ETH_64_POOLS;
2616         dev_info->vmdq_queue_num = dev_info->max_rx_queues;
2617         dev_info->rx_queue_offload_capa = txgbe_get_rx_queue_offloads(dev);
2618         dev_info->rx_offload_capa = (txgbe_get_rx_port_offloads(dev) |
2619                                      dev_info->rx_queue_offload_capa);
2620         dev_info->tx_queue_offload_capa = txgbe_get_tx_queue_offloads(dev);
2621         dev_info->tx_offload_capa = txgbe_get_tx_port_offloads(dev);
2622
2623         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2624                 .rx_thresh = {
2625                         .pthresh = TXGBE_DEFAULT_RX_PTHRESH,
2626                         .hthresh = TXGBE_DEFAULT_RX_HTHRESH,
2627                         .wthresh = TXGBE_DEFAULT_RX_WTHRESH,
2628                 },
2629                 .rx_free_thresh = TXGBE_DEFAULT_RX_FREE_THRESH,
2630                 .rx_drop_en = 0,
2631                 .offloads = 0,
2632         };
2633
2634         dev_info->default_txconf = (struct rte_eth_txconf) {
2635                 .tx_thresh = {
2636                         .pthresh = TXGBE_DEFAULT_TX_PTHRESH,
2637                         .hthresh = TXGBE_DEFAULT_TX_HTHRESH,
2638                         .wthresh = TXGBE_DEFAULT_TX_WTHRESH,
2639                 },
2640                 .tx_free_thresh = TXGBE_DEFAULT_TX_FREE_THRESH,
2641                 .offloads = 0,
2642         };
2643
2644         dev_info->rx_desc_lim = rx_desc_lim;
2645         dev_info->tx_desc_lim = tx_desc_lim;
2646
2647         dev_info->hash_key_size = TXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
2648         dev_info->reta_size = ETH_RSS_RETA_SIZE_128;
2649         dev_info->flow_type_rss_offloads = TXGBE_RSS_OFFLOAD_ALL;
2650
2651         dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
2652         dev_info->speed_capa |= ETH_LINK_SPEED_100M;
2653
2654         /* Driver-preferred Rx/Tx parameters */
2655         dev_info->default_rxportconf.burst_size = 32;
2656         dev_info->default_txportconf.burst_size = 32;
2657         dev_info->default_rxportconf.nb_queues = 1;
2658         dev_info->default_txportconf.nb_queues = 1;
2659         dev_info->default_rxportconf.ring_size = 256;
2660         dev_info->default_txportconf.ring_size = 256;
2661
2662         return 0;
2663 }
2664
2665 const uint32_t *
2666 txgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev)
2667 {
2668         if (dev->rx_pkt_burst == txgbe_recv_pkts ||
2669             dev->rx_pkt_burst == txgbe_recv_pkts_lro_single_alloc ||
2670             dev->rx_pkt_burst == txgbe_recv_pkts_lro_bulk_alloc ||
2671             dev->rx_pkt_burst == txgbe_recv_pkts_bulk_alloc)
2672                 return txgbe_get_supported_ptypes();
2673
2674         return NULL;
2675 }
2676
2677 void
2678 txgbe_dev_setup_link_alarm_handler(void *param)
2679 {
2680         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2681         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2682         struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);
2683         u32 speed;
2684         bool autoneg = false;
2685
2686         speed = hw->phy.autoneg_advertised;
2687         if (!speed)
2688                 hw->mac.get_link_capabilities(hw, &speed, &autoneg);
2689
2690         hw->mac.setup_link(hw, speed, true);
2691
2692         intr->flags &= ~TXGBE_FLAG_NEED_LINK_CONFIG;
2693 }
2694
2695 /* return 0 means link status changed, -1 means not changed */
2696 int
2697 txgbe_dev_link_update_share(struct rte_eth_dev *dev,
2698                             int wait_to_complete)
2699 {
2700         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2701         struct rte_eth_link link;
2702         u32 link_speed = TXGBE_LINK_SPEED_UNKNOWN;
2703         struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);
2704         bool link_up;
2705         int err;
2706         int wait = 1;
2707
2708         memset(&link, 0, sizeof(link));
2709         link.link_status = ETH_LINK_DOWN;
2710         link.link_speed = ETH_SPEED_NUM_NONE;
2711         link.link_duplex = ETH_LINK_HALF_DUPLEX;
2712         link.link_autoneg = ETH_LINK_AUTONEG;
2713
2714         hw->mac.get_link_status = true;
2715
2716         if (intr->flags & TXGBE_FLAG_NEED_LINK_CONFIG)
2717                 return rte_eth_linkstatus_set(dev, &link);
2718
2719         /* check if it needs to wait to complete, if lsc interrupt is enabled */
2720         if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
2721                 wait = 0;
2722
2723         err = hw->mac.check_link(hw, &link_speed, &link_up, wait);
2724
2725         if (err != 0) {
2726                 link.link_speed = ETH_SPEED_NUM_100M;
2727                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
2728                 return rte_eth_linkstatus_set(dev, &link);
2729         }
2730
2731         if (link_up == 0) {
2732                 if ((hw->subsystem_device_id & 0xFF) ==
2733                                 TXGBE_DEV_ID_KR_KX_KX4) {
2734                         hw->mac.bp_down_event(hw);
2735                 } else if (hw->phy.media_type == txgbe_media_type_fiber) {
2736                         intr->flags |= TXGBE_FLAG_NEED_LINK_CONFIG;
2737                         rte_eal_alarm_set(10,
2738                                 txgbe_dev_setup_link_alarm_handler, dev);
2739                 }
2740                 return rte_eth_linkstatus_set(dev, &link);
2741         } else if (!hw->dev_start) {
2742                 return rte_eth_linkstatus_set(dev, &link);
2743         }
2744
2745         intr->flags &= ~TXGBE_FLAG_NEED_LINK_CONFIG;
2746         link.link_status = ETH_LINK_UP;
2747         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2748
2749         switch (link_speed) {
2750         default:
2751         case TXGBE_LINK_SPEED_UNKNOWN:
2752                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
2753                 link.link_speed = ETH_SPEED_NUM_100M;
2754                 break;
2755
2756         case TXGBE_LINK_SPEED_100M_FULL:
2757                 link.link_speed = ETH_SPEED_NUM_100M;
2758                 break;
2759
2760         case TXGBE_LINK_SPEED_1GB_FULL:
2761                 link.link_speed = ETH_SPEED_NUM_1G;
2762                 break;
2763
2764         case TXGBE_LINK_SPEED_2_5GB_FULL:
2765                 link.link_speed = ETH_SPEED_NUM_2_5G;
2766                 break;
2767
2768         case TXGBE_LINK_SPEED_5GB_FULL:
2769                 link.link_speed = ETH_SPEED_NUM_5G;
2770                 break;
2771
2772         case TXGBE_LINK_SPEED_10GB_FULL:
2773                 link.link_speed = ETH_SPEED_NUM_10G;
2774                 break;
2775         }
2776
2777         return rte_eth_linkstatus_set(dev, &link);
2778 }
2779
2780 static int
2781 txgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
2782 {
2783         return txgbe_dev_link_update_share(dev, wait_to_complete);
2784 }
2785
2786 static int
2787 txgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
2788 {
2789         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2790         uint32_t fctrl;
2791
2792         fctrl = rd32(hw, TXGBE_PSRCTL);
2793         fctrl |= (TXGBE_PSRCTL_UCP | TXGBE_PSRCTL_MCP);
2794         wr32(hw, TXGBE_PSRCTL, fctrl);
2795
2796         return 0;
2797 }
2798
2799 static int
2800 txgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
2801 {
2802         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2803         uint32_t fctrl;
2804
2805         fctrl = rd32(hw, TXGBE_PSRCTL);
2806         fctrl &= (~TXGBE_PSRCTL_UCP);
2807         if (dev->data->all_multicast == 1)
2808                 fctrl |= TXGBE_PSRCTL_MCP;
2809         else
2810                 fctrl &= (~TXGBE_PSRCTL_MCP);
2811         wr32(hw, TXGBE_PSRCTL, fctrl);
2812
2813         return 0;
2814 }
2815
2816 static int
2817 txgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
2818 {
2819         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2820         uint32_t fctrl;
2821
2822         fctrl = rd32(hw, TXGBE_PSRCTL);
2823         fctrl |= TXGBE_PSRCTL_MCP;
2824         wr32(hw, TXGBE_PSRCTL, fctrl);
2825
2826         return 0;
2827 }
2828
2829 static int
2830 txgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
2831 {
2832         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2833         uint32_t fctrl;
2834
2835         if (dev->data->promiscuous == 1)
2836                 return 0; /* must remain in all_multicast mode */
2837
2838         fctrl = rd32(hw, TXGBE_PSRCTL);
2839         fctrl &= (~TXGBE_PSRCTL_MCP);
2840         wr32(hw, TXGBE_PSRCTL, fctrl);
2841
2842         return 0;
2843 }
2844
2845 /**
2846  * It clears the interrupt causes and enables the interrupt.
2847  * It will be called once only during nic initialized.
2848  *
2849  * @param dev
2850  *  Pointer to struct rte_eth_dev.
2851  * @param on
2852  *  Enable or Disable.
2853  *
2854  * @return
2855  *  - On success, zero.
2856  *  - On failure, a negative value.
2857  */
2858 static int
2859 txgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on)
2860 {
2861         struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);
2862
2863         txgbe_dev_link_status_print(dev);
2864         if (on)
2865                 intr->mask_misc |= TXGBE_ICRMISC_LSC;
2866         else
2867                 intr->mask_misc &= ~TXGBE_ICRMISC_LSC;
2868
2869         return 0;
2870 }
2871
2872 static int
2873 txgbe_dev_misc_interrupt_setup(struct rte_eth_dev *dev)
2874 {
2875         struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);
2876         u64 mask;
2877
2878         mask = TXGBE_ICR_MASK;
2879         mask &= (1ULL << TXGBE_MISC_VEC_ID);
2880         intr->mask |= mask;
2881         intr->mask_misc |= TXGBE_ICRMISC_GPIO;
2882         intr->mask_misc |= TXGBE_ICRMISC_ANDONE;
2883         return 0;
2884 }
2885
2886 /**
2887  * It clears the interrupt causes and enables the interrupt.
2888  * It will be called once only during nic initialized.
2889  *
2890  * @param dev
2891  *  Pointer to struct rte_eth_dev.
2892  *
2893  * @return
2894  *  - On success, zero.
2895  *  - On failure, a negative value.
2896  */
2897 static int
2898 txgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
2899 {
2900         struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);
2901         u64 mask;
2902
2903         mask = TXGBE_ICR_MASK;
2904         mask &= ~((1ULL << TXGBE_RX_VEC_START) - 1);
2905         intr->mask |= mask;
2906
2907         return 0;
2908 }
2909
2910 /**
2911  * It clears the interrupt causes and enables the interrupt.
2912  * It will be called once only during nic initialized.
2913  *
2914  * @param dev
2915  *  Pointer to struct rte_eth_dev.
2916  *
2917  * @return
2918  *  - On success, zero.
2919  *  - On failure, a negative value.
2920  */
2921 static int
2922 txgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev)
2923 {
2924         struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);
2925
2926         intr->mask_misc |= TXGBE_ICRMISC_LNKSEC;
2927
2928         return 0;
2929 }
2930
2931 /*
2932  * It reads ICR and sets flag (TXGBE_ICRMISC_LSC) for the link_update.
2933  *
2934  * @param dev
2935  *  Pointer to struct rte_eth_dev.
2936  *
2937  * @return
2938  *  - On success, zero.
2939  *  - On failure, a negative value.
2940  */
2941 static int
2942 txgbe_dev_interrupt_get_status(struct rte_eth_dev *dev,
2943                                 struct rte_intr_handle *intr_handle)
2944 {
2945         uint32_t eicr;
2946         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2947         struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);
2948
2949         if (intr_handle->type != RTE_INTR_HANDLE_UIO &&
2950                         intr_handle->type != RTE_INTR_HANDLE_VFIO_MSIX)
2951                 wr32(hw, TXGBE_PX_INTA, 1);
2952
2953         /* clear all cause mask */
2954         txgbe_disable_intr(hw);
2955
2956         /* read-on-clear nic registers here */
2957         eicr = ((u32 *)hw->isb_mem)[TXGBE_ISB_MISC];
2958         PMD_DRV_LOG(DEBUG, "eicr %x", eicr);
2959
2960         intr->flags = 0;
2961
2962         /* set flag for async link update */
2963         if (eicr & TXGBE_ICRMISC_LSC)
2964                 intr->flags |= TXGBE_FLAG_NEED_LINK_UPDATE;
2965
2966         if (eicr & TXGBE_ICRMISC_ANDONE)
2967                 intr->flags |= TXGBE_FLAG_NEED_AN_CONFIG;
2968
2969         if (eicr & TXGBE_ICRMISC_VFMBX)
2970                 intr->flags |= TXGBE_FLAG_MAILBOX;
2971
2972         if (eicr & TXGBE_ICRMISC_LNKSEC)
2973                 intr->flags |= TXGBE_FLAG_MACSEC;
2974
2975         if (eicr & TXGBE_ICRMISC_GPIO)
2976                 intr->flags |= TXGBE_FLAG_PHY_INTERRUPT;
2977
2978         return 0;
2979 }
2980
2981 /**
2982  * It gets and then prints the link status.
2983  *
2984  * @param dev
2985  *  Pointer to struct rte_eth_dev.
2986  *
2987  * @return
2988  *  - On success, zero.
2989  *  - On failure, a negative value.
2990  */
2991 static void
2992 txgbe_dev_link_status_print(struct rte_eth_dev *dev)
2993 {
2994         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2995         struct rte_eth_link link;
2996
2997         rte_eth_linkstatus_get(dev, &link);
2998
2999         if (link.link_status) {
3000                 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
3001                                         (int)(dev->data->port_id),
3002                                         (unsigned int)link.link_speed,
3003                         link.link_duplex == ETH_LINK_FULL_DUPLEX ?
3004                                         "full-duplex" : "half-duplex");
3005         } else {
3006                 PMD_INIT_LOG(INFO, " Port %d: Link Down",
3007                                 (int)(dev->data->port_id));
3008         }
3009         PMD_INIT_LOG(DEBUG, "PCI Address: " PCI_PRI_FMT,
3010                                 pci_dev->addr.domain,
3011                                 pci_dev->addr.bus,
3012                                 pci_dev->addr.devid,
3013                                 pci_dev->addr.function);
3014 }
3015
3016 /*
3017  * It executes link_update after knowing an interrupt occurred.
3018  *
3019  * @param dev
3020  *  Pointer to struct rte_eth_dev.
3021  *
3022  * @return
3023  *  - On success, zero.
3024  *  - On failure, a negative value.
3025  */
3026 static int
3027 txgbe_dev_interrupt_action(struct rte_eth_dev *dev,
3028                            struct rte_intr_handle *intr_handle)
3029 {
3030         struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);
3031         int64_t timeout;
3032         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3033
3034         PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
3035
3036         if (intr->flags & TXGBE_FLAG_MAILBOX) {
3037                 txgbe_pf_mbx_process(dev);
3038                 intr->flags &= ~TXGBE_FLAG_MAILBOX;
3039         }
3040
3041         if (intr->flags & TXGBE_FLAG_PHY_INTERRUPT) {
3042                 hw->phy.handle_lasi(hw);
3043                 intr->flags &= ~TXGBE_FLAG_PHY_INTERRUPT;
3044         }
3045
3046         if (intr->flags & TXGBE_FLAG_NEED_AN_CONFIG) {
3047                 if (hw->devarg.auto_neg == 1 && hw->devarg.poll == 0) {
3048                         hw->mac.kr_handle(hw);
3049                         intr->flags &= ~TXGBE_FLAG_NEED_AN_CONFIG;
3050                 }
3051         }
3052
3053         if (intr->flags & TXGBE_FLAG_NEED_LINK_UPDATE) {
3054                 struct rte_eth_link link;
3055
3056                 /*get the link status before link update, for predicting later*/
3057                 rte_eth_linkstatus_get(dev, &link);
3058
3059                 txgbe_dev_link_update(dev, 0);
3060
3061                 /* likely to up */
3062                 if (!link.link_status)
3063                         /* handle it 1 sec later, wait it being stable */
3064                         timeout = TXGBE_LINK_UP_CHECK_TIMEOUT;
3065                 /* likely to down */
3066                 else if ((hw->subsystem_device_id & 0xFF) ==
3067                                 TXGBE_DEV_ID_KR_KX_KX4 &&
3068                                 hw->devarg.auto_neg == 1)
3069                         /* handle it 2 sec later for backplane AN73 */
3070                         timeout = 2000;
3071                 else
3072                         /* handle it 4 sec later, wait it being stable */
3073                         timeout = TXGBE_LINK_DOWN_CHECK_TIMEOUT;
3074
3075                 txgbe_dev_link_status_print(dev);
3076                 if (rte_eal_alarm_set(timeout * 1000,
3077                                       txgbe_dev_interrupt_delayed_handler,
3078                                       (void *)dev) < 0) {
3079                         PMD_DRV_LOG(ERR, "Error setting alarm");
3080                 } else {
3081                         /* only disable lsc interrupt */
3082                         intr->mask_misc &= ~TXGBE_ICRMISC_LSC;
3083
3084                         intr->mask_orig = intr->mask;
3085                         /* only disable all misc interrupts */
3086                         intr->mask &= ~(1ULL << TXGBE_MISC_VEC_ID);
3087                 }
3088         }
3089
3090         PMD_DRV_LOG(DEBUG, "enable intr immediately");
3091         txgbe_enable_intr(dev);
3092         rte_intr_enable(intr_handle);
3093
3094         return 0;
3095 }
3096
3097 /**
3098  * Interrupt handler which shall be registered for alarm callback for delayed
3099  * handling specific interrupt to wait for the stable nic state. As the
3100  * NIC interrupt state is not stable for txgbe after link is just down,
3101  * it needs to wait 4 seconds to get the stable status.
3102  *
3103  * @param handle
3104  *  Pointer to interrupt handle.
3105  * @param param
3106  *  The address of parameter (struct rte_eth_dev *) registered before.
3107  *
3108  * @return
3109  *  void
3110  */
3111 static void
3112 txgbe_dev_interrupt_delayed_handler(void *param)
3113 {
3114         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3115         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3116         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3117         struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);
3118         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3119         uint32_t eicr;
3120
3121         txgbe_disable_intr(hw);
3122
3123         eicr = ((u32 *)hw->isb_mem)[TXGBE_ISB_MISC];
3124         if (eicr & TXGBE_ICRMISC_VFMBX)
3125                 txgbe_pf_mbx_process(dev);
3126
3127         if (intr->flags & TXGBE_FLAG_PHY_INTERRUPT) {
3128                 hw->phy.handle_lasi(hw);
3129                 intr->flags &= ~TXGBE_FLAG_PHY_INTERRUPT;
3130         }
3131
3132         if (intr->flags & TXGBE_FLAG_NEED_LINK_UPDATE) {
3133                 txgbe_dev_link_update(dev, 0);
3134                 intr->flags &= ~TXGBE_FLAG_NEED_LINK_UPDATE;
3135                 txgbe_dev_link_status_print(dev);
3136                 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC,
3137                                               NULL);
3138         }
3139
3140         if (intr->flags & TXGBE_FLAG_MACSEC) {
3141                 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_MACSEC,
3142                                               NULL);
3143                 intr->flags &= ~TXGBE_FLAG_MACSEC;
3144         }
3145
3146         /* restore original mask */
3147         intr->mask_misc |= TXGBE_ICRMISC_LSC;
3148
3149         intr->mask = intr->mask_orig;
3150         intr->mask_orig = 0;
3151
3152         PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
3153         txgbe_enable_intr(dev);
3154         rte_intr_enable(intr_handle);
3155 }
3156
3157 /**
3158  * Interrupt handler triggered by NIC  for handling
3159  * specific interrupt.
3160  *
3161  * @param handle
3162  *  Pointer to interrupt handle.
3163  * @param param
3164  *  The address of parameter (struct rte_eth_dev *) registered before.
3165  *
3166  * @return
3167  *  void
3168  */
3169 static void
3170 txgbe_dev_interrupt_handler(void *param)
3171 {
3172         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3173
3174         txgbe_dev_interrupt_get_status(dev, dev->intr_handle);
3175         txgbe_dev_interrupt_action(dev, dev->intr_handle);
3176 }
3177
3178 static int
3179 txgbe_dev_led_on(struct rte_eth_dev *dev)
3180 {
3181         struct txgbe_hw *hw;
3182
3183         hw = TXGBE_DEV_HW(dev);
3184         return txgbe_led_on(hw, 4) == 0 ? 0 : -ENOTSUP;
3185 }
3186
3187 static int
3188 txgbe_dev_led_off(struct rte_eth_dev *dev)
3189 {
3190         struct txgbe_hw *hw;
3191
3192         hw = TXGBE_DEV_HW(dev);
3193         return txgbe_led_off(hw, 4) == 0 ? 0 : -ENOTSUP;
3194 }
3195
3196 static int
3197 txgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3198 {
3199         struct txgbe_hw *hw;
3200         uint32_t mflcn_reg;
3201         uint32_t fccfg_reg;
3202         int rx_pause;
3203         int tx_pause;
3204
3205         hw = TXGBE_DEV_HW(dev);
3206
3207         fc_conf->pause_time = hw->fc.pause_time;
3208         fc_conf->high_water = hw->fc.high_water[0];
3209         fc_conf->low_water = hw->fc.low_water[0];
3210         fc_conf->send_xon = hw->fc.send_xon;
3211         fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
3212
3213         /*
3214          * Return rx_pause status according to actual setting of
3215          * RXFCCFG register.
3216          */
3217         mflcn_reg = rd32(hw, TXGBE_RXFCCFG);
3218         if (mflcn_reg & (TXGBE_RXFCCFG_FC | TXGBE_RXFCCFG_PFC))
3219                 rx_pause = 1;
3220         else
3221                 rx_pause = 0;
3222
3223         /*
3224          * Return tx_pause status according to actual setting of
3225          * TXFCCFG register.
3226          */
3227         fccfg_reg = rd32(hw, TXGBE_TXFCCFG);
3228         if (fccfg_reg & (TXGBE_TXFCCFG_FC | TXGBE_TXFCCFG_PFC))
3229                 tx_pause = 1;
3230         else
3231                 tx_pause = 0;
3232
3233         if (rx_pause && tx_pause)
3234                 fc_conf->mode = RTE_FC_FULL;
3235         else if (rx_pause)
3236                 fc_conf->mode = RTE_FC_RX_PAUSE;
3237         else if (tx_pause)
3238                 fc_conf->mode = RTE_FC_TX_PAUSE;
3239         else
3240                 fc_conf->mode = RTE_FC_NONE;
3241
3242         return 0;
3243 }
3244
3245 static int
3246 txgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3247 {
3248         struct txgbe_hw *hw;
3249         int err;
3250         uint32_t rx_buf_size;
3251         uint32_t max_high_water;
3252         enum txgbe_fc_mode rte_fcmode_2_txgbe_fcmode[] = {
3253                 txgbe_fc_none,
3254                 txgbe_fc_rx_pause,
3255                 txgbe_fc_tx_pause,
3256                 txgbe_fc_full
3257         };
3258
3259         PMD_INIT_FUNC_TRACE();
3260
3261         hw = TXGBE_DEV_HW(dev);
3262         rx_buf_size = rd32(hw, TXGBE_PBRXSIZE(0));
3263         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
3264
3265         /*
3266          * At least reserve one Ethernet frame for watermark
3267          * high_water/low_water in kilo bytes for txgbe
3268          */
3269         max_high_water = (rx_buf_size - RTE_ETHER_MAX_LEN) >> 10;
3270         if (fc_conf->high_water > max_high_water ||
3271             fc_conf->high_water < fc_conf->low_water) {
3272                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
3273                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
3274                 return -EINVAL;
3275         }
3276
3277         hw->fc.requested_mode = rte_fcmode_2_txgbe_fcmode[fc_conf->mode];
3278         hw->fc.pause_time     = fc_conf->pause_time;
3279         hw->fc.high_water[0]  = fc_conf->high_water;
3280         hw->fc.low_water[0]   = fc_conf->low_water;
3281         hw->fc.send_xon       = fc_conf->send_xon;
3282         hw->fc.disable_fc_autoneg = !fc_conf->autoneg;
3283
3284         err = txgbe_fc_enable(hw);
3285
3286         /* Not negotiated is not an error case */
3287         if (err == 0 || err == TXGBE_ERR_FC_NOT_NEGOTIATED) {
3288                 wr32m(hw, TXGBE_MACRXFLT, TXGBE_MACRXFLT_CTL_MASK,
3289                       (fc_conf->mac_ctrl_frame_fwd
3290                        ? TXGBE_MACRXFLT_CTL_NOPS : TXGBE_MACRXFLT_CTL_DROP));
3291                 txgbe_flush(hw);
3292
3293                 return 0;
3294         }
3295
3296         PMD_INIT_LOG(ERR, "txgbe_fc_enable = 0x%x", err);
3297         return -EIO;
3298 }
3299
3300 static int
3301 txgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
3302                 struct rte_eth_pfc_conf *pfc_conf)
3303 {
3304         int err;
3305         uint32_t rx_buf_size;
3306         uint32_t max_high_water;
3307         uint8_t tc_num;
3308         uint8_t  map[TXGBE_DCB_UP_MAX] = { 0 };
3309         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3310         struct txgbe_dcb_config *dcb_config = TXGBE_DEV_DCB_CONFIG(dev);
3311
3312         enum txgbe_fc_mode rte_fcmode_2_txgbe_fcmode[] = {
3313                 txgbe_fc_none,
3314                 txgbe_fc_rx_pause,
3315                 txgbe_fc_tx_pause,
3316                 txgbe_fc_full
3317         };
3318
3319         PMD_INIT_FUNC_TRACE();
3320
3321         txgbe_dcb_unpack_map_cee(dcb_config, TXGBE_DCB_RX_CONFIG, map);
3322         tc_num = map[pfc_conf->priority];
3323         rx_buf_size = rd32(hw, TXGBE_PBRXSIZE(tc_num));
3324         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
3325         /*
3326          * At least reserve one Ethernet frame for watermark
3327          * high_water/low_water in kilo bytes for txgbe
3328          */
3329         max_high_water = (rx_buf_size - RTE_ETHER_MAX_LEN) >> 10;
3330         if (pfc_conf->fc.high_water > max_high_water ||
3331             pfc_conf->fc.high_water <= pfc_conf->fc.low_water) {
3332                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
3333                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
3334                 return -EINVAL;
3335         }
3336
3337         hw->fc.requested_mode = rte_fcmode_2_txgbe_fcmode[pfc_conf->fc.mode];
3338         hw->fc.pause_time = pfc_conf->fc.pause_time;
3339         hw->fc.send_xon = pfc_conf->fc.send_xon;
3340         hw->fc.low_water[tc_num] =  pfc_conf->fc.low_water;
3341         hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
3342
3343         err = txgbe_dcb_pfc_enable(hw, tc_num);
3344
3345         /* Not negotiated is not an error case */
3346         if (err == 0 || err == TXGBE_ERR_FC_NOT_NEGOTIATED)
3347                 return 0;
3348
3349         PMD_INIT_LOG(ERR, "txgbe_dcb_pfc_enable = 0x%x", err);
3350         return -EIO;
3351 }
3352
3353 int
3354 txgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
3355                           struct rte_eth_rss_reta_entry64 *reta_conf,
3356                           uint16_t reta_size)
3357 {
3358         uint8_t i, j, mask;
3359         uint32_t reta;
3360         uint16_t idx, shift;
3361         struct txgbe_adapter *adapter = TXGBE_DEV_ADAPTER(dev);
3362         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3363
3364         PMD_INIT_FUNC_TRACE();
3365
3366         if (!txgbe_rss_update_sp(hw->mac.type)) {
3367                 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this "
3368                         "NIC.");
3369                 return -ENOTSUP;
3370         }
3371
3372         if (reta_size != ETH_RSS_RETA_SIZE_128) {
3373                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3374                         "(%d) doesn't match the number hardware can supported "
3375                         "(%d)", reta_size, ETH_RSS_RETA_SIZE_128);
3376                 return -EINVAL;
3377         }
3378
3379         for (i = 0; i < reta_size; i += 4) {
3380                 idx = i / RTE_RETA_GROUP_SIZE;
3381                 shift = i % RTE_RETA_GROUP_SIZE;
3382                 mask = (uint8_t)RS64(reta_conf[idx].mask, shift, 0xF);
3383                 if (!mask)
3384                         continue;
3385
3386                 reta = rd32at(hw, TXGBE_REG_RSSTBL, i >> 2);
3387                 for (j = 0; j < 4; j++) {
3388                         if (RS8(mask, j, 0x1)) {
3389                                 reta  &= ~(MS32(8 * j, 0xFF));
3390                                 reta |= LS32(reta_conf[idx].reta[shift + j],
3391                                                 8 * j, 0xFF);
3392                         }
3393                 }
3394                 wr32at(hw, TXGBE_REG_RSSTBL, i >> 2, reta);
3395         }
3396         adapter->rss_reta_updated = 1;
3397
3398         return 0;
3399 }
3400
3401 int
3402 txgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
3403                          struct rte_eth_rss_reta_entry64 *reta_conf,
3404                          uint16_t reta_size)
3405 {
3406         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3407         uint8_t i, j, mask;
3408         uint32_t reta;
3409         uint16_t idx, shift;
3410
3411         PMD_INIT_FUNC_TRACE();
3412
3413         if (reta_size != ETH_RSS_RETA_SIZE_128) {
3414                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3415                         "(%d) doesn't match the number hardware can supported "
3416                         "(%d)", reta_size, ETH_RSS_RETA_SIZE_128);
3417                 return -EINVAL;
3418         }
3419
3420         for (i = 0; i < reta_size; i += 4) {
3421                 idx = i / RTE_RETA_GROUP_SIZE;
3422                 shift = i % RTE_RETA_GROUP_SIZE;
3423                 mask = (uint8_t)RS64(reta_conf[idx].mask, shift, 0xF);
3424                 if (!mask)
3425                         continue;
3426
3427                 reta = rd32at(hw, TXGBE_REG_RSSTBL, i >> 2);
3428                 for (j = 0; j < 4; j++) {
3429                         if (RS8(mask, j, 0x1))
3430                                 reta_conf[idx].reta[shift + j] =
3431                                         (uint16_t)RS32(reta, 8 * j, 0xFF);
3432                 }
3433         }
3434
3435         return 0;
3436 }
3437
3438 static int
3439 txgbe_add_rar(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
3440                                 uint32_t index, uint32_t pool)
3441 {
3442         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3443         uint32_t enable_addr = 1;
3444
3445         return txgbe_set_rar(hw, index, mac_addr->addr_bytes,
3446                              pool, enable_addr);
3447 }
3448
3449 static void
3450 txgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
3451 {
3452         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3453
3454         txgbe_clear_rar(hw, index);
3455 }
3456
3457 static int
3458 txgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *addr)
3459 {
3460         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3461
3462         txgbe_remove_rar(dev, 0);
3463         txgbe_add_rar(dev, addr, 0, pci_dev->max_vfs);
3464
3465         return 0;
3466 }
3467
3468 static int
3469 txgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
3470 {
3471         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3472         struct rte_eth_dev_info dev_info;
3473         uint32_t frame_size = mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN;
3474         struct rte_eth_dev_data *dev_data = dev->data;
3475         int ret;
3476
3477         ret = txgbe_dev_info_get(dev, &dev_info);
3478         if (ret != 0)
3479                 return ret;
3480
3481         /* check that mtu is within the allowed range */
3482         if (mtu < RTE_ETHER_MIN_MTU || frame_size > dev_info.max_rx_pktlen)
3483                 return -EINVAL;
3484
3485         /* If device is started, refuse mtu that requires the support of
3486          * scattered packets when this feature has not been enabled before.
3487          */
3488         if (dev_data->dev_started && !dev_data->scattered_rx &&
3489             (frame_size + 2 * TXGBE_VLAN_TAG_SIZE >
3490              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
3491                 PMD_INIT_LOG(ERR, "Stop port first.");
3492                 return -EINVAL;
3493         }
3494
3495         /* update max frame size */
3496         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
3497
3498         if (hw->mode)
3499                 wr32m(hw, TXGBE_FRMSZ, TXGBE_FRMSZ_MAX_MASK,
3500                         TXGBE_FRAME_SIZE_MAX);
3501         else
3502                 wr32m(hw, TXGBE_FRMSZ, TXGBE_FRMSZ_MAX_MASK,
3503                         TXGBE_FRMSZ_MAX(frame_size));
3504
3505         return 0;
3506 }
3507
3508 static uint32_t
3509 txgbe_uta_vector(struct txgbe_hw *hw, struct rte_ether_addr *uc_addr)
3510 {
3511         uint32_t vector = 0;
3512
3513         switch (hw->mac.mc_filter_type) {
3514         case 0:   /* use bits [47:36] of the address */
3515                 vector = ((uc_addr->addr_bytes[4] >> 4) |
3516                         (((uint16_t)uc_addr->addr_bytes[5]) << 4));
3517                 break;
3518         case 1:   /* use bits [46:35] of the address */
3519                 vector = ((uc_addr->addr_bytes[4] >> 3) |
3520                         (((uint16_t)uc_addr->addr_bytes[5]) << 5));
3521                 break;
3522         case 2:   /* use bits [45:34] of the address */
3523                 vector = ((uc_addr->addr_bytes[4] >> 2) |
3524                         (((uint16_t)uc_addr->addr_bytes[5]) << 6));
3525                 break;
3526         case 3:   /* use bits [43:32] of the address */
3527                 vector = ((uc_addr->addr_bytes[4]) |
3528                         (((uint16_t)uc_addr->addr_bytes[5]) << 8));
3529                 break;
3530         default:  /* Invalid mc_filter_type */
3531                 break;
3532         }
3533
3534         /* vector can only be 12-bits or boundary will be exceeded */
3535         vector &= 0xFFF;
3536         return vector;
3537 }
3538
3539 static int
3540 txgbe_uc_hash_table_set(struct rte_eth_dev *dev,
3541                         struct rte_ether_addr *mac_addr, uint8_t on)
3542 {
3543         uint32_t vector;
3544         uint32_t uta_idx;
3545         uint32_t reg_val;
3546         uint32_t uta_mask;
3547         uint32_t psrctl;
3548
3549         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3550         struct txgbe_uta_info *uta_info = TXGBE_DEV_UTA_INFO(dev);
3551
3552         /* The UTA table only exists on pf hardware */
3553         if (hw->mac.type < txgbe_mac_raptor)
3554                 return -ENOTSUP;
3555
3556         vector = txgbe_uta_vector(hw, mac_addr);
3557         uta_idx = (vector >> 5) & 0x7F;
3558         uta_mask = 0x1UL << (vector & 0x1F);
3559
3560         if (!!on == !!(uta_info->uta_shadow[uta_idx] & uta_mask))
3561                 return 0;
3562
3563         reg_val = rd32(hw, TXGBE_UCADDRTBL(uta_idx));
3564         if (on) {
3565                 uta_info->uta_in_use++;
3566                 reg_val |= uta_mask;
3567                 uta_info->uta_shadow[uta_idx] |= uta_mask;
3568         } else {
3569                 uta_info->uta_in_use--;
3570                 reg_val &= ~uta_mask;
3571                 uta_info->uta_shadow[uta_idx] &= ~uta_mask;
3572         }
3573
3574         wr32(hw, TXGBE_UCADDRTBL(uta_idx), reg_val);
3575
3576         psrctl = rd32(hw, TXGBE_PSRCTL);
3577         if (uta_info->uta_in_use > 0)
3578                 psrctl |= TXGBE_PSRCTL_UCHFENA;
3579         else
3580                 psrctl &= ~TXGBE_PSRCTL_UCHFENA;
3581
3582         psrctl &= ~TXGBE_PSRCTL_ADHF12_MASK;
3583         psrctl |= TXGBE_PSRCTL_ADHF12(hw->mac.mc_filter_type);
3584         wr32(hw, TXGBE_PSRCTL, psrctl);
3585
3586         return 0;
3587 }
3588
3589 static int
3590 txgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
3591 {
3592         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3593         struct txgbe_uta_info *uta_info = TXGBE_DEV_UTA_INFO(dev);
3594         uint32_t psrctl;
3595         int i;
3596
3597         /* The UTA table only exists on pf hardware */
3598         if (hw->mac.type < txgbe_mac_raptor)
3599                 return -ENOTSUP;
3600
3601         if (on) {
3602                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
3603                         uta_info->uta_shadow[i] = ~0;
3604                         wr32(hw, TXGBE_UCADDRTBL(i), ~0);
3605                 }
3606         } else {
3607                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
3608                         uta_info->uta_shadow[i] = 0;
3609                         wr32(hw, TXGBE_UCADDRTBL(i), 0);
3610                 }
3611         }
3612
3613         psrctl = rd32(hw, TXGBE_PSRCTL);
3614         if (on)
3615                 psrctl |= TXGBE_PSRCTL_UCHFENA;
3616         else
3617                 psrctl &= ~TXGBE_PSRCTL_UCHFENA;
3618
3619         psrctl &= ~TXGBE_PSRCTL_ADHF12_MASK;
3620         psrctl |= TXGBE_PSRCTL_ADHF12(hw->mac.mc_filter_type);
3621         wr32(hw, TXGBE_PSRCTL, psrctl);
3622
3623         return 0;
3624 }
3625
3626 uint32_t
3627 txgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
3628 {
3629         uint32_t new_val = orig_val;
3630
3631         if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
3632                 new_val |= TXGBE_POOLETHCTL_UTA;
3633         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
3634                 new_val |= TXGBE_POOLETHCTL_MCHA;
3635         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
3636                 new_val |= TXGBE_POOLETHCTL_UCHA;
3637         if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
3638                 new_val |= TXGBE_POOLETHCTL_BCA;
3639         if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
3640                 new_val |= TXGBE_POOLETHCTL_MCP;
3641
3642         return new_val;
3643 }
3644
3645 static int
3646 txgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
3647 {
3648         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3649         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3650         uint32_t mask;
3651         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3652
3653         if (queue_id < 32) {
3654                 mask = rd32(hw, TXGBE_IMS(0));
3655                 mask &= (1 << queue_id);
3656                 wr32(hw, TXGBE_IMS(0), mask);
3657         } else if (queue_id < 64) {
3658                 mask = rd32(hw, TXGBE_IMS(1));
3659                 mask &= (1 << (queue_id - 32));
3660                 wr32(hw, TXGBE_IMS(1), mask);
3661         }
3662         rte_intr_enable(intr_handle);
3663
3664         return 0;
3665 }
3666
3667 static int
3668 txgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
3669 {
3670         uint32_t mask;
3671         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3672
3673         if (queue_id < 32) {
3674                 mask = rd32(hw, TXGBE_IMS(0));
3675                 mask &= ~(1 << queue_id);
3676                 wr32(hw, TXGBE_IMS(0), mask);
3677         } else if (queue_id < 64) {
3678                 mask = rd32(hw, TXGBE_IMS(1));
3679                 mask &= ~(1 << (queue_id - 32));
3680                 wr32(hw, TXGBE_IMS(1), mask);
3681         }
3682
3683         return 0;
3684 }
3685
3686 /**
3687  * set the IVAR registers, mapping interrupt causes to vectors
3688  * @param hw
3689  *  pointer to txgbe_hw struct
3690  * @direction
3691  *  0 for Rx, 1 for Tx, -1 for other causes
3692  * @queue
3693  *  queue to map the corresponding interrupt to
3694  * @msix_vector
3695  *  the vector to map to the corresponding queue
3696  */
3697 void
3698 txgbe_set_ivar_map(struct txgbe_hw *hw, int8_t direction,
3699                    uint8_t queue, uint8_t msix_vector)
3700 {
3701         uint32_t tmp, idx;
3702
3703         if (direction == -1) {
3704                 /* other causes */
3705                 msix_vector |= TXGBE_IVARMISC_VLD;
3706                 idx = 0;
3707                 tmp = rd32(hw, TXGBE_IVARMISC);
3708                 tmp &= ~(0xFF << idx);
3709                 tmp |= (msix_vector << idx);
3710                 wr32(hw, TXGBE_IVARMISC, tmp);
3711         } else {
3712                 /* rx or tx causes */
3713                 /* Workround for ICR lost */
3714                 idx = ((16 * (queue & 1)) + (8 * direction));
3715                 tmp = rd32(hw, TXGBE_IVAR(queue >> 1));
3716                 tmp &= ~(0xFF << idx);
3717                 tmp |= (msix_vector << idx);
3718                 wr32(hw, TXGBE_IVAR(queue >> 1), tmp);
3719         }
3720 }
3721
3722 /**
3723  * Sets up the hardware to properly generate MSI-X interrupts
3724  * @hw
3725  *  board private structure
3726  */
3727 static void
3728 txgbe_configure_msix(struct rte_eth_dev *dev)
3729 {
3730         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3731         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3732         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3733         uint32_t queue_id, base = TXGBE_MISC_VEC_ID;
3734         uint32_t vec = TXGBE_MISC_VEC_ID;
3735         uint32_t gpie;
3736
3737         /* won't configure msix register if no mapping is done
3738          * between intr vector and event fd
3739          * but if misx has been enabled already, need to configure
3740          * auto clean, auto mask and throttling.
3741          */
3742         gpie = rd32(hw, TXGBE_GPIE);
3743         if (!rte_intr_dp_is_en(intr_handle) &&
3744             !(gpie & TXGBE_GPIE_MSIX))
3745                 return;
3746
3747         if (rte_intr_allow_others(intr_handle)) {
3748                 base = TXGBE_RX_VEC_START;
3749                 vec = base;
3750         }
3751
3752         /* setup GPIE for MSI-x mode */
3753         gpie = rd32(hw, TXGBE_GPIE);
3754         gpie |= TXGBE_GPIE_MSIX;
3755         wr32(hw, TXGBE_GPIE, gpie);
3756
3757         /* Populate the IVAR table and set the ITR values to the
3758          * corresponding register.
3759          */
3760         if (rte_intr_dp_is_en(intr_handle)) {
3761                 for (queue_id = 0; queue_id < dev->data->nb_rx_queues;
3762                         queue_id++) {
3763                         /* by default, 1:1 mapping */
3764                         txgbe_set_ivar_map(hw, 0, queue_id, vec);
3765                         intr_handle->intr_vec[queue_id] = vec;
3766                         if (vec < base + intr_handle->nb_efd - 1)
3767                                 vec++;
3768                 }
3769
3770                 txgbe_set_ivar_map(hw, -1, 1, TXGBE_MISC_VEC_ID);
3771         }
3772         wr32(hw, TXGBE_ITR(TXGBE_MISC_VEC_ID),
3773                         TXGBE_ITR_IVAL_10G(TXGBE_QUEUE_ITR_INTERVAL_DEFAULT)
3774                         | TXGBE_ITR_WRDSA);
3775 }
3776
3777 int
3778 txgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
3779                            uint16_t queue_idx, uint16_t tx_rate)
3780 {
3781         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3782         uint32_t bcnrc_val;
3783
3784         if (queue_idx >= hw->mac.max_tx_queues)
3785                 return -EINVAL;
3786
3787         if (tx_rate != 0) {
3788                 bcnrc_val = TXGBE_ARBTXRATE_MAX(tx_rate);
3789                 bcnrc_val |= TXGBE_ARBTXRATE_MIN(tx_rate / 2);
3790         } else {
3791                 bcnrc_val = 0;
3792         }
3793
3794         /*
3795          * Set global transmit compensation time to the MMW_SIZE in ARBTXMMW
3796          * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported.
3797          */
3798         wr32(hw, TXGBE_ARBTXMMW, 0x14);
3799
3800         /* Set ARBTXRATE of queue X */
3801         wr32(hw, TXGBE_ARBPOOLIDX, queue_idx);
3802         wr32(hw, TXGBE_ARBTXRATE, bcnrc_val);
3803         txgbe_flush(hw);
3804
3805         return 0;
3806 }
3807
3808 int
3809 txgbe_syn_filter_set(struct rte_eth_dev *dev,
3810                         struct rte_eth_syn_filter *filter,
3811                         bool add)
3812 {
3813         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3814         struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(dev);
3815         uint32_t syn_info;
3816         uint32_t synqf;
3817
3818         if (filter->queue >= TXGBE_MAX_RX_QUEUE_NUM)
3819                 return -EINVAL;
3820
3821         syn_info = filter_info->syn_info;
3822
3823         if (add) {
3824                 if (syn_info & TXGBE_SYNCLS_ENA)
3825                         return -EINVAL;
3826                 synqf = (uint32_t)TXGBE_SYNCLS_QPID(filter->queue);
3827                 synqf |= TXGBE_SYNCLS_ENA;
3828
3829                 if (filter->hig_pri)
3830                         synqf |= TXGBE_SYNCLS_HIPRIO;
3831                 else
3832                         synqf &= ~TXGBE_SYNCLS_HIPRIO;
3833         } else {
3834                 synqf = rd32(hw, TXGBE_SYNCLS);
3835                 if (!(syn_info & TXGBE_SYNCLS_ENA))
3836                         return -ENOENT;
3837                 synqf &= ~(TXGBE_SYNCLS_QPID_MASK | TXGBE_SYNCLS_ENA);
3838         }
3839
3840         filter_info->syn_info = synqf;
3841         wr32(hw, TXGBE_SYNCLS, synqf);
3842         txgbe_flush(hw);
3843         return 0;
3844 }
3845
3846 static inline enum txgbe_5tuple_protocol
3847 convert_protocol_type(uint8_t protocol_value)
3848 {
3849         if (protocol_value == IPPROTO_TCP)
3850                 return TXGBE_5TF_PROT_TCP;
3851         else if (protocol_value == IPPROTO_UDP)
3852                 return TXGBE_5TF_PROT_UDP;
3853         else if (protocol_value == IPPROTO_SCTP)
3854                 return TXGBE_5TF_PROT_SCTP;
3855         else
3856                 return TXGBE_5TF_PROT_NONE;
3857 }
3858
3859 /* inject a 5-tuple filter to HW */
3860 static inline void
3861 txgbe_inject_5tuple_filter(struct rte_eth_dev *dev,
3862                            struct txgbe_5tuple_filter *filter)
3863 {
3864         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3865         int i;
3866         uint32_t ftqf, sdpqf;
3867         uint32_t l34timir = 0;
3868         uint32_t mask = TXGBE_5TFCTL0_MASK;
3869
3870         i = filter->index;
3871         sdpqf = TXGBE_5TFPORT_DST(be_to_le16(filter->filter_info.dst_port));
3872         sdpqf |= TXGBE_5TFPORT_SRC(be_to_le16(filter->filter_info.src_port));
3873
3874         ftqf = TXGBE_5TFCTL0_PROTO(filter->filter_info.proto);
3875         ftqf |= TXGBE_5TFCTL0_PRI(filter->filter_info.priority);
3876         if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
3877                 mask &= ~TXGBE_5TFCTL0_MSADDR;
3878         if (filter->filter_info.dst_ip_mask == 0)
3879                 mask &= ~TXGBE_5TFCTL0_MDADDR;
3880         if (filter->filter_info.src_port_mask == 0)
3881                 mask &= ~TXGBE_5TFCTL0_MSPORT;
3882         if (filter->filter_info.dst_port_mask == 0)
3883                 mask &= ~TXGBE_5TFCTL0_MDPORT;
3884         if (filter->filter_info.proto_mask == 0)
3885                 mask &= ~TXGBE_5TFCTL0_MPROTO;
3886         ftqf |= mask;
3887         ftqf |= TXGBE_5TFCTL0_MPOOL;
3888         ftqf |= TXGBE_5TFCTL0_ENA;
3889
3890         wr32(hw, TXGBE_5TFDADDR(i), be_to_le32(filter->filter_info.dst_ip));
3891         wr32(hw, TXGBE_5TFSADDR(i), be_to_le32(filter->filter_info.src_ip));
3892         wr32(hw, TXGBE_5TFPORT(i), sdpqf);
3893         wr32(hw, TXGBE_5TFCTL0(i), ftqf);
3894
3895         l34timir |= TXGBE_5TFCTL1_QP(filter->queue);
3896         wr32(hw, TXGBE_5TFCTL1(i), l34timir);
3897 }
3898
3899 /*
3900  * add a 5tuple filter
3901  *
3902  * @param
3903  * dev: Pointer to struct rte_eth_dev.
3904  * index: the index the filter allocates.
3905  * filter: pointer to the filter that will be added.
3906  * rx_queue: the queue id the filter assigned to.
3907  *
3908  * @return
3909  *    - On success, zero.
3910  *    - On failure, a negative value.
3911  */
3912 static int
3913 txgbe_add_5tuple_filter(struct rte_eth_dev *dev,
3914                         struct txgbe_5tuple_filter *filter)
3915 {
3916         struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(dev);
3917         int i, idx, shift;
3918
3919         /*
3920          * look for an unused 5tuple filter index,
3921          * and insert the filter to list.
3922          */
3923         for (i = 0; i < TXGBE_MAX_FTQF_FILTERS; i++) {
3924                 idx = i / (sizeof(uint32_t) * NBBY);
3925                 shift = i % (sizeof(uint32_t) * NBBY);
3926                 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
3927                         filter_info->fivetuple_mask[idx] |= 1 << shift;
3928                         filter->index = i;
3929                         TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
3930                                           filter,
3931                                           entries);
3932                         break;
3933                 }
3934         }
3935         if (i >= TXGBE_MAX_FTQF_FILTERS) {
3936                 PMD_DRV_LOG(ERR, "5tuple filters are full.");
3937                 return -ENOSYS;
3938         }
3939
3940         txgbe_inject_5tuple_filter(dev, filter);
3941
3942         return 0;
3943 }
3944
3945 /*
3946  * remove a 5tuple filter
3947  *
3948  * @param
3949  * dev: Pointer to struct rte_eth_dev.
3950  * filter: the pointer of the filter will be removed.
3951  */
3952 static void
3953 txgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
3954                         struct txgbe_5tuple_filter *filter)
3955 {
3956         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3957         struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(dev);
3958         uint16_t index = filter->index;
3959
3960         filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
3961                                 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
3962         TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
3963         rte_free(filter);
3964
3965         wr32(hw, TXGBE_5TFDADDR(index), 0);
3966         wr32(hw, TXGBE_5TFSADDR(index), 0);
3967         wr32(hw, TXGBE_5TFPORT(index), 0);
3968         wr32(hw, TXGBE_5TFCTL0(index), 0);
3969         wr32(hw, TXGBE_5TFCTL1(index), 0);
3970 }
3971
3972 static inline struct txgbe_5tuple_filter *
3973 txgbe_5tuple_filter_lookup(struct txgbe_5tuple_filter_list *filter_list,
3974                         struct txgbe_5tuple_filter_info *key)
3975 {
3976         struct txgbe_5tuple_filter *it;
3977
3978         TAILQ_FOREACH(it, filter_list, entries) {
3979                 if (memcmp(key, &it->filter_info,
3980                         sizeof(struct txgbe_5tuple_filter_info)) == 0) {
3981                         return it;
3982                 }
3983         }
3984         return NULL;
3985 }
3986
3987 /* translate elements in struct rte_eth_ntuple_filter
3988  * to struct txgbe_5tuple_filter_info
3989  */
3990 static inline int
3991 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
3992                         struct txgbe_5tuple_filter_info *filter_info)
3993 {
3994         if (filter->queue >= TXGBE_MAX_RX_QUEUE_NUM ||
3995                 filter->priority > TXGBE_5TUPLE_MAX_PRI ||
3996                 filter->priority < TXGBE_5TUPLE_MIN_PRI)
3997                 return -EINVAL;
3998
3999         switch (filter->dst_ip_mask) {
4000         case UINT32_MAX:
4001                 filter_info->dst_ip_mask = 0;
4002                 filter_info->dst_ip = filter->dst_ip;
4003                 break;
4004         case 0:
4005                 filter_info->dst_ip_mask = 1;
4006                 break;
4007         default:
4008                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
4009                 return -EINVAL;
4010         }
4011
4012         switch (filter->src_ip_mask) {
4013         case UINT32_MAX:
4014                 filter_info->src_ip_mask = 0;
4015                 filter_info->src_ip = filter->src_ip;
4016                 break;
4017         case 0:
4018                 filter_info->src_ip_mask = 1;
4019                 break;
4020         default:
4021                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
4022                 return -EINVAL;
4023         }
4024
4025         switch (filter->dst_port_mask) {
4026         case UINT16_MAX:
4027                 filter_info->dst_port_mask = 0;
4028                 filter_info->dst_port = filter->dst_port;
4029                 break;
4030         case 0:
4031                 filter_info->dst_port_mask = 1;
4032                 break;
4033         default:
4034                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
4035                 return -EINVAL;
4036         }
4037
4038         switch (filter->src_port_mask) {
4039         case UINT16_MAX:
4040                 filter_info->src_port_mask = 0;
4041                 filter_info->src_port = filter->src_port;
4042                 break;
4043         case 0:
4044                 filter_info->src_port_mask = 1;
4045                 break;
4046         default:
4047                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
4048                 return -EINVAL;
4049         }
4050
4051         switch (filter->proto_mask) {
4052         case UINT8_MAX:
4053                 filter_info->proto_mask = 0;
4054                 filter_info->proto =
4055                         convert_protocol_type(filter->proto);
4056                 break;
4057         case 0:
4058                 filter_info->proto_mask = 1;
4059                 break;
4060         default:
4061                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
4062                 return -EINVAL;
4063         }
4064
4065         filter_info->priority = (uint8_t)filter->priority;
4066         return 0;
4067 }
4068
4069 /*
4070  * add or delete a ntuple filter
4071  *
4072  * @param
4073  * dev: Pointer to struct rte_eth_dev.
4074  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
4075  * add: if true, add filter, if false, remove filter
4076  *
4077  * @return
4078  *    - On success, zero.
4079  *    - On failure, a negative value.
4080  */
4081 int
4082 txgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
4083                         struct rte_eth_ntuple_filter *ntuple_filter,
4084                         bool add)
4085 {
4086         struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(dev);
4087         struct txgbe_5tuple_filter_info filter_5tuple;
4088         struct txgbe_5tuple_filter *filter;
4089         int ret;
4090
4091         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
4092                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
4093                 return -EINVAL;
4094         }
4095
4096         memset(&filter_5tuple, 0, sizeof(struct txgbe_5tuple_filter_info));
4097         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
4098         if (ret < 0)
4099                 return ret;
4100
4101         filter = txgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
4102                                          &filter_5tuple);
4103         if (filter != NULL && add) {
4104                 PMD_DRV_LOG(ERR, "filter exists.");
4105                 return -EEXIST;
4106         }
4107         if (filter == NULL && !add) {
4108                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4109                 return -ENOENT;
4110         }
4111
4112         if (add) {
4113                 filter = rte_zmalloc("txgbe_5tuple_filter",
4114                                 sizeof(struct txgbe_5tuple_filter), 0);
4115                 if (filter == NULL)
4116                         return -ENOMEM;
4117                 rte_memcpy(&filter->filter_info,
4118                                  &filter_5tuple,
4119                                  sizeof(struct txgbe_5tuple_filter_info));
4120                 filter->queue = ntuple_filter->queue;
4121                 ret = txgbe_add_5tuple_filter(dev, filter);
4122                 if (ret < 0) {
4123                         rte_free(filter);
4124                         return ret;
4125                 }
4126         } else {
4127                 txgbe_remove_5tuple_filter(dev, filter);
4128         }
4129
4130         return 0;
4131 }
4132
4133 int
4134 txgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
4135                         struct rte_eth_ethertype_filter *filter,
4136                         bool add)
4137 {
4138         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4139         struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(dev);
4140         uint32_t etqf = 0;
4141         uint32_t etqs = 0;
4142         int ret;
4143         struct txgbe_ethertype_filter ethertype_filter;
4144
4145         if (filter->queue >= TXGBE_MAX_RX_QUEUE_NUM)
4146                 return -EINVAL;
4147
4148         if (filter->ether_type == RTE_ETHER_TYPE_IPV4 ||
4149             filter->ether_type == RTE_ETHER_TYPE_IPV6) {
4150                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
4151                         " ethertype filter.", filter->ether_type);
4152                 return -EINVAL;
4153         }
4154
4155         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
4156                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
4157                 return -EINVAL;
4158         }
4159         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
4160                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
4161                 return -EINVAL;
4162         }
4163
4164         ret = txgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
4165         if (ret >= 0 && add) {
4166                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
4167                             filter->ether_type);
4168                 return -EEXIST;
4169         }
4170         if (ret < 0 && !add) {
4171                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
4172                             filter->ether_type);
4173                 return -ENOENT;
4174         }
4175
4176         if (add) {
4177                 etqf = TXGBE_ETFLT_ENA;
4178                 etqf |= TXGBE_ETFLT_ETID(filter->ether_type);
4179                 etqs |= TXGBE_ETCLS_QPID(filter->queue);
4180                 etqs |= TXGBE_ETCLS_QENA;
4181
4182                 ethertype_filter.ethertype = filter->ether_type;
4183                 ethertype_filter.etqf = etqf;
4184                 ethertype_filter.etqs = etqs;
4185                 ethertype_filter.conf = FALSE;
4186                 ret = txgbe_ethertype_filter_insert(filter_info,
4187                                                     &ethertype_filter);
4188                 if (ret < 0) {
4189                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
4190                         return -ENOSPC;
4191                 }
4192         } else {
4193                 ret = txgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
4194                 if (ret < 0)
4195                         return -ENOSYS;
4196         }
4197         wr32(hw, TXGBE_ETFLT(ret), etqf);
4198         wr32(hw, TXGBE_ETCLS(ret), etqs);
4199         txgbe_flush(hw);
4200
4201         return 0;
4202 }
4203
4204 static int
4205 txgbe_dev_flow_ops_get(__rte_unused struct rte_eth_dev *dev,
4206                        const struct rte_flow_ops **ops)
4207 {
4208         *ops = &txgbe_flow_ops;
4209         return 0;
4210 }
4211
4212 static u8 *
4213 txgbe_dev_addr_list_itr(__rte_unused struct txgbe_hw *hw,
4214                         u8 **mc_addr_ptr, u32 *vmdq)
4215 {
4216         u8 *mc_addr;
4217
4218         *vmdq = 0;
4219         mc_addr = *mc_addr_ptr;
4220         *mc_addr_ptr = (mc_addr + sizeof(struct rte_ether_addr));
4221         return mc_addr;
4222 }
4223
4224 int
4225 txgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
4226                           struct rte_ether_addr *mc_addr_set,
4227                           uint32_t nb_mc_addr)
4228 {
4229         struct txgbe_hw *hw;
4230         u8 *mc_addr_list;
4231
4232         hw = TXGBE_DEV_HW(dev);
4233         mc_addr_list = (u8 *)mc_addr_set;
4234         return hw->mac.update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
4235                                          txgbe_dev_addr_list_itr, TRUE);
4236 }
4237
4238 static uint64_t
4239 txgbe_read_systime_cyclecounter(struct rte_eth_dev *dev)
4240 {
4241         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4242         uint64_t systime_cycles;
4243
4244         systime_cycles = (uint64_t)rd32(hw, TXGBE_TSTIMEL);
4245         systime_cycles |= (uint64_t)rd32(hw, TXGBE_TSTIMEH) << 32;
4246
4247         return systime_cycles;
4248 }
4249
4250 static uint64_t
4251 txgbe_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
4252 {
4253         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4254         uint64_t rx_tstamp_cycles;
4255
4256         /* TSRXSTMPL stores ns and TSRXSTMPH stores seconds. */
4257         rx_tstamp_cycles = (uint64_t)rd32(hw, TXGBE_TSRXSTMPL);
4258         rx_tstamp_cycles |= (uint64_t)rd32(hw, TXGBE_TSRXSTMPH) << 32;
4259
4260         return rx_tstamp_cycles;
4261 }
4262
4263 static uint64_t
4264 txgbe_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
4265 {
4266         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4267         uint64_t tx_tstamp_cycles;
4268
4269         /* TSTXSTMPL stores ns and TSTXSTMPH stores seconds. */
4270         tx_tstamp_cycles = (uint64_t)rd32(hw, TXGBE_TSTXSTMPL);
4271         tx_tstamp_cycles |= (uint64_t)rd32(hw, TXGBE_TSTXSTMPH) << 32;
4272
4273         return tx_tstamp_cycles;
4274 }
4275
4276 static void
4277 txgbe_start_timecounters(struct rte_eth_dev *dev)
4278 {
4279         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4280         struct txgbe_adapter *adapter = TXGBE_DEV_ADAPTER(dev);
4281         struct rte_eth_link link;
4282         uint32_t incval = 0;
4283         uint32_t shift = 0;
4284
4285         /* Get current link speed. */
4286         txgbe_dev_link_update(dev, 1);
4287         rte_eth_linkstatus_get(dev, &link);
4288
4289         switch (link.link_speed) {
4290         case ETH_SPEED_NUM_100M:
4291                 incval = TXGBE_INCVAL_100;
4292                 shift = TXGBE_INCVAL_SHIFT_100;
4293                 break;
4294         case ETH_SPEED_NUM_1G:
4295                 incval = TXGBE_INCVAL_1GB;
4296                 shift = TXGBE_INCVAL_SHIFT_1GB;
4297                 break;
4298         case ETH_SPEED_NUM_10G:
4299         default:
4300                 incval = TXGBE_INCVAL_10GB;
4301                 shift = TXGBE_INCVAL_SHIFT_10GB;
4302                 break;
4303         }
4304
4305         wr32(hw, TXGBE_TSTIMEINC, TXGBE_TSTIMEINC_VP(incval, 2));
4306
4307         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
4308         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
4309         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
4310
4311         adapter->systime_tc.cc_mask = TXGBE_CYCLECOUNTER_MASK;
4312         adapter->systime_tc.cc_shift = shift;
4313         adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
4314
4315         adapter->rx_tstamp_tc.cc_mask = TXGBE_CYCLECOUNTER_MASK;
4316         adapter->rx_tstamp_tc.cc_shift = shift;
4317         adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
4318
4319         adapter->tx_tstamp_tc.cc_mask = TXGBE_CYCLECOUNTER_MASK;
4320         adapter->tx_tstamp_tc.cc_shift = shift;
4321         adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
4322 }
4323
4324 static int
4325 txgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
4326 {
4327         struct txgbe_adapter *adapter = TXGBE_DEV_ADAPTER(dev);
4328
4329         adapter->systime_tc.nsec += delta;
4330         adapter->rx_tstamp_tc.nsec += delta;
4331         adapter->tx_tstamp_tc.nsec += delta;
4332
4333         return 0;
4334 }
4335
4336 static int
4337 txgbe_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
4338 {
4339         uint64_t ns;
4340         struct txgbe_adapter *adapter = TXGBE_DEV_ADAPTER(dev);
4341
4342         ns = rte_timespec_to_ns(ts);
4343         /* Set the timecounters to a new value. */
4344         adapter->systime_tc.nsec = ns;
4345         adapter->rx_tstamp_tc.nsec = ns;
4346         adapter->tx_tstamp_tc.nsec = ns;
4347
4348         return 0;
4349 }
4350
4351 static int
4352 txgbe_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
4353 {
4354         uint64_t ns, systime_cycles;
4355         struct txgbe_adapter *adapter = TXGBE_DEV_ADAPTER(dev);
4356
4357         systime_cycles = txgbe_read_systime_cyclecounter(dev);
4358         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
4359         *ts = rte_ns_to_timespec(ns);
4360
4361         return 0;
4362 }
4363
4364 static int
4365 txgbe_timesync_enable(struct rte_eth_dev *dev)
4366 {
4367         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4368         uint32_t tsync_ctl;
4369
4370         /* Stop the timesync system time. */
4371         wr32(hw, TXGBE_TSTIMEINC, 0x0);
4372         /* Reset the timesync system time value. */
4373         wr32(hw, TXGBE_TSTIMEL, 0x0);
4374         wr32(hw, TXGBE_TSTIMEH, 0x0);
4375
4376         txgbe_start_timecounters(dev);
4377
4378         /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
4379         wr32(hw, TXGBE_ETFLT(TXGBE_ETF_ID_1588),
4380                 RTE_ETHER_TYPE_1588 | TXGBE_ETFLT_ENA | TXGBE_ETFLT_1588);
4381
4382         /* Enable timestamping of received PTP packets. */
4383         tsync_ctl = rd32(hw, TXGBE_TSRXCTL);
4384         tsync_ctl |= TXGBE_TSRXCTL_ENA;
4385         wr32(hw, TXGBE_TSRXCTL, tsync_ctl);
4386
4387         /* Enable timestamping of transmitted PTP packets. */
4388         tsync_ctl = rd32(hw, TXGBE_TSTXCTL);
4389         tsync_ctl |= TXGBE_TSTXCTL_ENA;
4390         wr32(hw, TXGBE_TSTXCTL, tsync_ctl);
4391
4392         txgbe_flush(hw);
4393
4394         return 0;
4395 }
4396
4397 static int
4398 txgbe_timesync_disable(struct rte_eth_dev *dev)
4399 {
4400         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4401         uint32_t tsync_ctl;
4402
4403         /* Disable timestamping of transmitted PTP packets. */
4404         tsync_ctl = rd32(hw, TXGBE_TSTXCTL);
4405         tsync_ctl &= ~TXGBE_TSTXCTL_ENA;
4406         wr32(hw, TXGBE_TSTXCTL, tsync_ctl);
4407
4408         /* Disable timestamping of received PTP packets. */
4409         tsync_ctl = rd32(hw, TXGBE_TSRXCTL);
4410         tsync_ctl &= ~TXGBE_TSRXCTL_ENA;
4411         wr32(hw, TXGBE_TSRXCTL, tsync_ctl);
4412
4413         /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
4414         wr32(hw, TXGBE_ETFLT(TXGBE_ETF_ID_1588), 0);
4415
4416         /* Stop incrementating the System Time registers. */
4417         wr32(hw, TXGBE_TSTIMEINC, 0);
4418
4419         return 0;
4420 }
4421
4422 static int
4423 txgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
4424                                  struct timespec *timestamp,
4425                                  uint32_t flags __rte_unused)
4426 {
4427         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4428         struct txgbe_adapter *adapter = TXGBE_DEV_ADAPTER(dev);
4429         uint32_t tsync_rxctl;
4430         uint64_t rx_tstamp_cycles;
4431         uint64_t ns;
4432
4433         tsync_rxctl = rd32(hw, TXGBE_TSRXCTL);
4434         if ((tsync_rxctl & TXGBE_TSRXCTL_VLD) == 0)
4435                 return -EINVAL;
4436
4437         rx_tstamp_cycles = txgbe_read_rx_tstamp_cyclecounter(dev);
4438         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
4439         *timestamp = rte_ns_to_timespec(ns);
4440
4441         return  0;
4442 }
4443
4444 static int
4445 txgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
4446                                  struct timespec *timestamp)
4447 {
4448         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4449         struct txgbe_adapter *adapter = TXGBE_DEV_ADAPTER(dev);
4450         uint32_t tsync_txctl;
4451         uint64_t tx_tstamp_cycles;
4452         uint64_t ns;
4453
4454         tsync_txctl = rd32(hw, TXGBE_TSTXCTL);
4455         if ((tsync_txctl & TXGBE_TSTXCTL_VLD) == 0)
4456                 return -EINVAL;
4457
4458         tx_tstamp_cycles = txgbe_read_tx_tstamp_cyclecounter(dev);
4459         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
4460         *timestamp = rte_ns_to_timespec(ns);
4461
4462         return 0;
4463 }
4464
4465 static int
4466 txgbe_get_reg_length(struct rte_eth_dev *dev __rte_unused)
4467 {
4468         int count = 0;
4469         int g_ind = 0;
4470         const struct reg_info *reg_group;
4471         const struct reg_info **reg_set = txgbe_regs_others;
4472
4473         while ((reg_group = reg_set[g_ind++]))
4474                 count += txgbe_regs_group_count(reg_group);
4475
4476         return count;
4477 }
4478
4479 static int
4480 txgbe_get_regs(struct rte_eth_dev *dev,
4481               struct rte_dev_reg_info *regs)
4482 {
4483         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4484         uint32_t *data = regs->data;
4485         int g_ind = 0;
4486         int count = 0;
4487         const struct reg_info *reg_group;
4488         const struct reg_info **reg_set = txgbe_regs_others;
4489
4490         if (data == NULL) {
4491                 regs->length = txgbe_get_reg_length(dev);
4492                 regs->width = sizeof(uint32_t);
4493                 return 0;
4494         }
4495
4496         /* Support only full register dump */
4497         if (regs->length == 0 ||
4498             regs->length == (uint32_t)txgbe_get_reg_length(dev)) {
4499                 regs->version = hw->mac.type << 24 |
4500                                 hw->revision_id << 16 |
4501                                 hw->device_id;
4502                 while ((reg_group = reg_set[g_ind++]))
4503                         count += txgbe_read_regs_group(dev, &data[count],
4504                                                       reg_group);
4505                 return 0;
4506         }
4507
4508         return -ENOTSUP;
4509 }
4510
4511 static int
4512 txgbe_get_eeprom_length(struct rte_eth_dev *dev)
4513 {
4514         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4515
4516         /* Return unit is byte count */
4517         return hw->rom.word_size * 2;
4518 }
4519
4520 static int
4521 txgbe_get_eeprom(struct rte_eth_dev *dev,
4522                 struct rte_dev_eeprom_info *in_eeprom)
4523 {
4524         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4525         struct txgbe_rom_info *eeprom = &hw->rom;
4526         uint16_t *data = in_eeprom->data;
4527         int first, length;
4528
4529         first = in_eeprom->offset >> 1;
4530         length = in_eeprom->length >> 1;
4531         if (first > hw->rom.word_size ||
4532             ((first + length) > hw->rom.word_size))
4533                 return -EINVAL;
4534
4535         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
4536
4537         return eeprom->readw_buffer(hw, first, length, data);
4538 }
4539
4540 static int
4541 txgbe_set_eeprom(struct rte_eth_dev *dev,
4542                 struct rte_dev_eeprom_info *in_eeprom)
4543 {
4544         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4545         struct txgbe_rom_info *eeprom = &hw->rom;
4546         uint16_t *data = in_eeprom->data;
4547         int first, length;
4548
4549         first = in_eeprom->offset >> 1;
4550         length = in_eeprom->length >> 1;
4551         if (first > hw->rom.word_size ||
4552             ((first + length) > hw->rom.word_size))
4553                 return -EINVAL;
4554
4555         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
4556
4557         return eeprom->writew_buffer(hw,  first, length, data);
4558 }
4559
4560 static int
4561 txgbe_get_module_info(struct rte_eth_dev *dev,
4562                       struct rte_eth_dev_module_info *modinfo)
4563 {
4564         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4565         uint32_t status;
4566         uint8_t sff8472_rev, addr_mode;
4567         bool page_swap = false;
4568
4569         /* Check whether we support SFF-8472 or not */
4570         status = hw->phy.read_i2c_eeprom(hw,
4571                                              TXGBE_SFF_SFF_8472_COMP,
4572                                              &sff8472_rev);
4573         if (status != 0)
4574                 return -EIO;
4575
4576         /* addressing mode is not supported */
4577         status = hw->phy.read_i2c_eeprom(hw,
4578                                              TXGBE_SFF_SFF_8472_SWAP,
4579                                              &addr_mode);
4580         if (status != 0)
4581                 return -EIO;
4582
4583         if (addr_mode & TXGBE_SFF_ADDRESSING_MODE) {
4584                 PMD_DRV_LOG(ERR,
4585                             "Address change required to access page 0xA2, "
4586                             "but not supported. Please report the module "
4587                             "type to the driver maintainers.");
4588                 page_swap = true;
4589         }
4590
4591         if (sff8472_rev == TXGBE_SFF_SFF_8472_UNSUP || page_swap) {
4592                 /* We have a SFP, but it does not support SFF-8472 */
4593                 modinfo->type = RTE_ETH_MODULE_SFF_8079;
4594                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
4595         } else {
4596                 /* We have a SFP which supports a revision of SFF-8472. */
4597                 modinfo->type = RTE_ETH_MODULE_SFF_8472;
4598                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
4599         }
4600
4601         return 0;
4602 }
4603
4604 static int
4605 txgbe_get_module_eeprom(struct rte_eth_dev *dev,
4606                         struct rte_dev_eeprom_info *info)
4607 {
4608         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4609         uint32_t status = TXGBE_ERR_PHY_ADDR_INVALID;
4610         uint8_t databyte = 0xFF;
4611         uint8_t *data = info->data;
4612         uint32_t i = 0;
4613
4614         if (info->length == 0)
4615                 return -EINVAL;
4616
4617         for (i = info->offset; i < info->offset + info->length; i++) {
4618                 if (i < RTE_ETH_MODULE_SFF_8079_LEN)
4619                         status = hw->phy.read_i2c_eeprom(hw, i, &databyte);
4620                 else
4621                         status = hw->phy.read_i2c_sff8472(hw, i, &databyte);
4622
4623                 if (status != 0)
4624                         return -EIO;
4625
4626                 data[i - info->offset] = databyte;
4627         }
4628
4629         return 0;
4630 }
4631
4632 bool
4633 txgbe_rss_update_sp(enum txgbe_mac_type mac_type)
4634 {
4635         switch (mac_type) {
4636         case txgbe_mac_raptor:
4637         case txgbe_mac_raptor_vf:
4638                 return 1;
4639         default:
4640                 return 0;
4641         }
4642 }
4643
4644 static int
4645 txgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
4646                         struct rte_eth_dcb_info *dcb_info)
4647 {
4648         struct txgbe_dcb_config *dcb_config = TXGBE_DEV_DCB_CONFIG(dev);
4649         struct txgbe_dcb_tc_config *tc;
4650         struct rte_eth_dcb_tc_queue_mapping *tc_queue;
4651         uint8_t nb_tcs;
4652         uint8_t i, j;
4653
4654         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
4655                 dcb_info->nb_tcs = dcb_config->num_tcs.pg_tcs;
4656         else
4657                 dcb_info->nb_tcs = 1;
4658
4659         tc_queue = &dcb_info->tc_queue;
4660         nb_tcs = dcb_info->nb_tcs;
4661
4662         if (dcb_config->vt_mode) { /* vt is enabled */
4663                 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
4664                                 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
4665                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
4666                         dcb_info->prio_tc[i] = vmdq_rx_conf->dcb_tc[i];
4667                 if (RTE_ETH_DEV_SRIOV(dev).active > 0) {
4668                         for (j = 0; j < nb_tcs; j++) {
4669                                 tc_queue->tc_rxq[0][j].base = j;
4670                                 tc_queue->tc_rxq[0][j].nb_queue = 1;
4671                                 tc_queue->tc_txq[0][j].base = j;
4672                                 tc_queue->tc_txq[0][j].nb_queue = 1;
4673                         }
4674                 } else {
4675                         for (i = 0; i < vmdq_rx_conf->nb_queue_pools; i++) {
4676                                 for (j = 0; j < nb_tcs; j++) {
4677                                         tc_queue->tc_rxq[i][j].base =
4678                                                 i * nb_tcs + j;
4679                                         tc_queue->tc_rxq[i][j].nb_queue = 1;
4680                                         tc_queue->tc_txq[i][j].base =
4681                                                 i * nb_tcs + j;
4682                                         tc_queue->tc_txq[i][j].nb_queue = 1;
4683                                 }
4684                         }
4685                 }
4686         } else { /* vt is disabled */
4687                 struct rte_eth_dcb_rx_conf *rx_conf =
4688                                 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
4689                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
4690                         dcb_info->prio_tc[i] = rx_conf->dcb_tc[i];
4691                 if (dcb_info->nb_tcs == ETH_4_TCS) {
4692                         for (i = 0; i < dcb_info->nb_tcs; i++) {
4693                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 32;
4694                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
4695                         }
4696                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
4697                         dcb_info->tc_queue.tc_txq[0][1].base = 64;
4698                         dcb_info->tc_queue.tc_txq[0][2].base = 96;
4699                         dcb_info->tc_queue.tc_txq[0][3].base = 112;
4700                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 64;
4701                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
4702                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
4703                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
4704                 } else if (dcb_info->nb_tcs == ETH_8_TCS) {
4705                         for (i = 0; i < dcb_info->nb_tcs; i++) {
4706                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 16;
4707                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
4708                         }
4709                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
4710                         dcb_info->tc_queue.tc_txq[0][1].base = 32;
4711                         dcb_info->tc_queue.tc_txq[0][2].base = 64;
4712                         dcb_info->tc_queue.tc_txq[0][3].base = 80;
4713                         dcb_info->tc_queue.tc_txq[0][4].base = 96;
4714                         dcb_info->tc_queue.tc_txq[0][5].base = 104;
4715                         dcb_info->tc_queue.tc_txq[0][6].base = 112;
4716                         dcb_info->tc_queue.tc_txq[0][7].base = 120;
4717                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 32;
4718                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
4719                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
4720                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
4721                         dcb_info->tc_queue.tc_txq[0][4].nb_queue = 8;
4722                         dcb_info->tc_queue.tc_txq[0][5].nb_queue = 8;
4723                         dcb_info->tc_queue.tc_txq[0][6].nb_queue = 8;
4724                         dcb_info->tc_queue.tc_txq[0][7].nb_queue = 8;
4725                 }
4726         }
4727         for (i = 0; i < dcb_info->nb_tcs; i++) {
4728                 tc = &dcb_config->tc_config[i];
4729                 dcb_info->tc_bws[i] = tc->path[TXGBE_DCB_TX_CONFIG].bwg_percent;
4730         }
4731         return 0;
4732 }
4733
4734 /* Update e-tag ether type */
4735 static int
4736 txgbe_update_e_tag_eth_type(struct txgbe_hw *hw,
4737                             uint16_t ether_type)
4738 {
4739         uint32_t etag_etype;
4740
4741         etag_etype = rd32(hw, TXGBE_EXTAG);
4742         etag_etype &= ~TXGBE_EXTAG_ETAG_MASK;
4743         etag_etype |= ether_type;
4744         wr32(hw, TXGBE_EXTAG, etag_etype);
4745         txgbe_flush(hw);
4746
4747         return 0;
4748 }
4749
4750 /* Enable e-tag tunnel */
4751 static int
4752 txgbe_e_tag_enable(struct txgbe_hw *hw)
4753 {
4754         uint32_t etag_etype;
4755
4756         etag_etype = rd32(hw, TXGBE_PORTCTL);
4757         etag_etype |= TXGBE_PORTCTL_ETAG;
4758         wr32(hw, TXGBE_PORTCTL, etag_etype);
4759         txgbe_flush(hw);
4760
4761         return 0;
4762 }
4763
4764 static int
4765 txgbe_e_tag_filter_del(struct rte_eth_dev *dev,
4766                        struct txgbe_l2_tunnel_conf  *l2_tunnel)
4767 {
4768         int ret = 0;
4769         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4770         uint32_t i, rar_entries;
4771         uint32_t rar_low, rar_high;
4772
4773         rar_entries = hw->mac.num_rar_entries;
4774
4775         for (i = 1; i < rar_entries; i++) {
4776                 wr32(hw, TXGBE_ETHADDRIDX, i);
4777                 rar_high = rd32(hw, TXGBE_ETHADDRH);
4778                 rar_low  = rd32(hw, TXGBE_ETHADDRL);
4779                 if ((rar_high & TXGBE_ETHADDRH_VLD) &&
4780                     (rar_high & TXGBE_ETHADDRH_ETAG) &&
4781                     (TXGBE_ETHADDRL_ETAG(rar_low) ==
4782                      l2_tunnel->tunnel_id)) {
4783                         wr32(hw, TXGBE_ETHADDRL, 0);
4784                         wr32(hw, TXGBE_ETHADDRH, 0);
4785
4786                         txgbe_clear_vmdq(hw, i, BIT_MASK32);
4787
4788                         return ret;
4789                 }
4790         }
4791
4792         return ret;
4793 }
4794
4795 static int
4796 txgbe_e_tag_filter_add(struct rte_eth_dev *dev,
4797                        struct txgbe_l2_tunnel_conf *l2_tunnel)
4798 {
4799         int ret = 0;
4800         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4801         uint32_t i, rar_entries;
4802         uint32_t rar_low, rar_high;
4803
4804         /* One entry for one tunnel. Try to remove potential existing entry. */
4805         txgbe_e_tag_filter_del(dev, l2_tunnel);
4806
4807         rar_entries = hw->mac.num_rar_entries;
4808
4809         for (i = 1; i < rar_entries; i++) {
4810                 wr32(hw, TXGBE_ETHADDRIDX, i);
4811                 rar_high = rd32(hw, TXGBE_ETHADDRH);
4812                 if (rar_high & TXGBE_ETHADDRH_VLD) {
4813                         continue;
4814                 } else {
4815                         txgbe_set_vmdq(hw, i, l2_tunnel->pool);
4816                         rar_high = TXGBE_ETHADDRH_VLD | TXGBE_ETHADDRH_ETAG;
4817                         rar_low = l2_tunnel->tunnel_id;
4818
4819                         wr32(hw, TXGBE_ETHADDRL, rar_low);
4820                         wr32(hw, TXGBE_ETHADDRH, rar_high);
4821
4822                         return ret;
4823                 }
4824         }
4825
4826         PMD_INIT_LOG(NOTICE, "The table of E-tag forwarding rule is full."
4827                      " Please remove a rule before adding a new one.");
4828         return -EINVAL;
4829 }
4830
4831 static inline struct txgbe_l2_tn_filter *
4832 txgbe_l2_tn_filter_lookup(struct txgbe_l2_tn_info *l2_tn_info,
4833                           struct txgbe_l2_tn_key *key)
4834 {
4835         int ret;
4836
4837         ret = rte_hash_lookup(l2_tn_info->hash_handle, (const void *)key);
4838         if (ret < 0)
4839                 return NULL;
4840
4841         return l2_tn_info->hash_map[ret];
4842 }
4843
4844 static inline int
4845 txgbe_insert_l2_tn_filter(struct txgbe_l2_tn_info *l2_tn_info,
4846                           struct txgbe_l2_tn_filter *l2_tn_filter)
4847 {
4848         int ret;
4849
4850         ret = rte_hash_add_key(l2_tn_info->hash_handle,
4851                                &l2_tn_filter->key);
4852
4853         if (ret < 0) {
4854                 PMD_DRV_LOG(ERR,
4855                             "Failed to insert L2 tunnel filter"
4856                             " to hash table %d!",
4857                             ret);
4858                 return ret;
4859         }
4860
4861         l2_tn_info->hash_map[ret] = l2_tn_filter;
4862
4863         TAILQ_INSERT_TAIL(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
4864
4865         return 0;
4866 }
4867
4868 static inline int
4869 txgbe_remove_l2_tn_filter(struct txgbe_l2_tn_info *l2_tn_info,
4870                           struct txgbe_l2_tn_key *key)
4871 {
4872         int ret;
4873         struct txgbe_l2_tn_filter *l2_tn_filter;
4874
4875         ret = rte_hash_del_key(l2_tn_info->hash_handle, key);
4876
4877         if (ret < 0) {
4878                 PMD_DRV_LOG(ERR,
4879                             "No such L2 tunnel filter to delete %d!",
4880                             ret);
4881                 return ret;
4882         }
4883
4884         l2_tn_filter = l2_tn_info->hash_map[ret];
4885         l2_tn_info->hash_map[ret] = NULL;
4886
4887         TAILQ_REMOVE(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
4888         rte_free(l2_tn_filter);
4889
4890         return 0;
4891 }
4892
4893 /* Add l2 tunnel filter */
4894 int
4895 txgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev,
4896                                struct txgbe_l2_tunnel_conf *l2_tunnel,
4897                                bool restore)
4898 {
4899         int ret;
4900         struct txgbe_l2_tn_info *l2_tn_info = TXGBE_DEV_L2_TN(dev);
4901         struct txgbe_l2_tn_key key;
4902         struct txgbe_l2_tn_filter *node;
4903
4904         if (!restore) {
4905                 key.l2_tn_type = l2_tunnel->l2_tunnel_type;
4906                 key.tn_id = l2_tunnel->tunnel_id;
4907
4908                 node = txgbe_l2_tn_filter_lookup(l2_tn_info, &key);
4909
4910                 if (node) {
4911                         PMD_DRV_LOG(ERR,
4912                                     "The L2 tunnel filter already exists!");
4913                         return -EINVAL;
4914                 }
4915
4916                 node = rte_zmalloc("txgbe_l2_tn",
4917                                    sizeof(struct txgbe_l2_tn_filter),
4918                                    0);
4919                 if (!node)
4920                         return -ENOMEM;
4921
4922                 rte_memcpy(&node->key,
4923                                  &key,
4924                                  sizeof(struct txgbe_l2_tn_key));
4925                 node->pool = l2_tunnel->pool;
4926                 ret = txgbe_insert_l2_tn_filter(l2_tn_info, node);
4927                 if (ret < 0) {
4928                         rte_free(node);
4929                         return ret;
4930                 }
4931         }
4932
4933         switch (l2_tunnel->l2_tunnel_type) {
4934         case RTE_L2_TUNNEL_TYPE_E_TAG:
4935                 ret = txgbe_e_tag_filter_add(dev, l2_tunnel);
4936                 break;
4937         default:
4938                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
4939                 ret = -EINVAL;
4940                 break;
4941         }
4942
4943         if (!restore && ret < 0)
4944                 (void)txgbe_remove_l2_tn_filter(l2_tn_info, &key);
4945
4946         return ret;
4947 }
4948
4949 /* Delete l2 tunnel filter */
4950 int
4951 txgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev,
4952                                struct txgbe_l2_tunnel_conf *l2_tunnel)
4953 {
4954         int ret;
4955         struct txgbe_l2_tn_info *l2_tn_info = TXGBE_DEV_L2_TN(dev);
4956         struct txgbe_l2_tn_key key;
4957
4958         key.l2_tn_type = l2_tunnel->l2_tunnel_type;
4959         key.tn_id = l2_tunnel->tunnel_id;
4960         ret = txgbe_remove_l2_tn_filter(l2_tn_info, &key);
4961         if (ret < 0)
4962                 return ret;
4963
4964         switch (l2_tunnel->l2_tunnel_type) {
4965         case RTE_L2_TUNNEL_TYPE_E_TAG:
4966                 ret = txgbe_e_tag_filter_del(dev, l2_tunnel);
4967                 break;
4968         default:
4969                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
4970                 ret = -EINVAL;
4971                 break;
4972         }
4973
4974         return ret;
4975 }
4976
4977 static int
4978 txgbe_e_tag_forwarding_en_dis(struct rte_eth_dev *dev, bool en)
4979 {
4980         int ret = 0;
4981         uint32_t ctrl;
4982         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4983
4984         ctrl = rd32(hw, TXGBE_POOLCTL);
4985         ctrl &= ~TXGBE_POOLCTL_MODE_MASK;
4986         if (en)
4987                 ctrl |= TXGBE_PSRPOOL_MODE_ETAG;
4988         wr32(hw, TXGBE_POOLCTL, ctrl);
4989
4990         return ret;
4991 }
4992
4993 /* Add UDP tunneling port */
4994 static int
4995 txgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
4996                               struct rte_eth_udp_tunnel *udp_tunnel)
4997 {
4998         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4999         int ret = 0;
5000
5001         if (udp_tunnel == NULL)
5002                 return -EINVAL;
5003
5004         switch (udp_tunnel->prot_type) {
5005         case RTE_TUNNEL_TYPE_VXLAN:
5006                 if (udp_tunnel->udp_port == 0) {
5007                         PMD_DRV_LOG(ERR, "Add VxLAN port 0 is not allowed.");
5008                         ret = -EINVAL;
5009                         break;
5010                 }
5011                 wr32(hw, TXGBE_VXLANPORT, udp_tunnel->udp_port);
5012                 break;
5013         case RTE_TUNNEL_TYPE_GENEVE:
5014                 if (udp_tunnel->udp_port == 0) {
5015                         PMD_DRV_LOG(ERR, "Add Geneve port 0 is not allowed.");
5016                         ret = -EINVAL;
5017                         break;
5018                 }
5019                 wr32(hw, TXGBE_GENEVEPORT, udp_tunnel->udp_port);
5020                 break;
5021         case RTE_TUNNEL_TYPE_TEREDO:
5022                 if (udp_tunnel->udp_port == 0) {
5023                         PMD_DRV_LOG(ERR, "Add Teredo port 0 is not allowed.");
5024                         ret = -EINVAL;
5025                         break;
5026                 }
5027                 wr32(hw, TXGBE_TEREDOPORT, udp_tunnel->udp_port);
5028                 break;
5029         case RTE_TUNNEL_TYPE_VXLAN_GPE:
5030                 if (udp_tunnel->udp_port == 0) {
5031                         PMD_DRV_LOG(ERR, "Add VxLAN port 0 is not allowed.");
5032                         ret = -EINVAL;
5033                         break;
5034                 }
5035                 wr32(hw, TXGBE_VXLANPORTGPE, udp_tunnel->udp_port);
5036                 break;
5037         default:
5038                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
5039                 ret = -EINVAL;
5040                 break;
5041         }
5042
5043         txgbe_flush(hw);
5044
5045         return ret;
5046 }
5047
5048 /* Remove UDP tunneling port */
5049 static int
5050 txgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
5051                               struct rte_eth_udp_tunnel *udp_tunnel)
5052 {
5053         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
5054         int ret = 0;
5055         uint16_t cur_port;
5056
5057         if (udp_tunnel == NULL)
5058                 return -EINVAL;
5059
5060         switch (udp_tunnel->prot_type) {
5061         case RTE_TUNNEL_TYPE_VXLAN:
5062                 cur_port = (uint16_t)rd32(hw, TXGBE_VXLANPORT);
5063                 if (cur_port != udp_tunnel->udp_port) {
5064                         PMD_DRV_LOG(ERR, "Port %u does not exist.",
5065                                         udp_tunnel->udp_port);
5066                         ret = -EINVAL;
5067                         break;
5068                 }
5069                 wr32(hw, TXGBE_VXLANPORT, 0);
5070                 break;
5071         case RTE_TUNNEL_TYPE_GENEVE:
5072                 cur_port = (uint16_t)rd32(hw, TXGBE_GENEVEPORT);
5073                 if (cur_port != udp_tunnel->udp_port) {
5074                         PMD_DRV_LOG(ERR, "Port %u does not exist.",
5075                                         udp_tunnel->udp_port);
5076                         ret = -EINVAL;
5077                         break;
5078                 }
5079                 wr32(hw, TXGBE_GENEVEPORT, 0);
5080                 break;
5081         case RTE_TUNNEL_TYPE_TEREDO:
5082                 cur_port = (uint16_t)rd32(hw, TXGBE_TEREDOPORT);
5083                 if (cur_port != udp_tunnel->udp_port) {
5084                         PMD_DRV_LOG(ERR, "Port %u does not exist.",
5085                                         udp_tunnel->udp_port);
5086                         ret = -EINVAL;
5087                         break;
5088                 }
5089                 wr32(hw, TXGBE_TEREDOPORT, 0);
5090                 break;
5091         case RTE_TUNNEL_TYPE_VXLAN_GPE:
5092                 cur_port = (uint16_t)rd32(hw, TXGBE_VXLANPORTGPE);
5093                 if (cur_port != udp_tunnel->udp_port) {
5094                         PMD_DRV_LOG(ERR, "Port %u does not exist.",
5095                                         udp_tunnel->udp_port);
5096                         ret = -EINVAL;
5097                         break;
5098                 }
5099                 wr32(hw, TXGBE_VXLANPORTGPE, 0);
5100                 break;
5101         default:
5102                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
5103                 ret = -EINVAL;
5104                 break;
5105         }
5106
5107         txgbe_flush(hw);
5108
5109         return ret;
5110 }
5111
5112 /* restore n-tuple filter */
5113 static inline void
5114 txgbe_ntuple_filter_restore(struct rte_eth_dev *dev)
5115 {
5116         struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(dev);
5117         struct txgbe_5tuple_filter *node;
5118
5119         TAILQ_FOREACH(node, &filter_info->fivetuple_list, entries) {
5120                 txgbe_inject_5tuple_filter(dev, node);
5121         }
5122 }
5123
5124 /* restore ethernet type filter */
5125 static inline void
5126 txgbe_ethertype_filter_restore(struct rte_eth_dev *dev)
5127 {
5128         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
5129         struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(dev);
5130         int i;
5131
5132         for (i = 0; i < TXGBE_ETF_ID_MAX; i++) {
5133                 if (filter_info->ethertype_mask & (1 << i)) {
5134                         wr32(hw, TXGBE_ETFLT(i),
5135                                         filter_info->ethertype_filters[i].etqf);
5136                         wr32(hw, TXGBE_ETCLS(i),
5137                                         filter_info->ethertype_filters[i].etqs);
5138                         txgbe_flush(hw);
5139                 }
5140         }
5141 }
5142
5143 /* restore SYN filter */
5144 static inline void
5145 txgbe_syn_filter_restore(struct rte_eth_dev *dev)
5146 {
5147         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
5148         struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(dev);
5149         uint32_t synqf;
5150
5151         synqf = filter_info->syn_info;
5152
5153         if (synqf & TXGBE_SYNCLS_ENA) {
5154                 wr32(hw, TXGBE_SYNCLS, synqf);
5155                 txgbe_flush(hw);
5156         }
5157 }
5158
5159 /* restore L2 tunnel filter */
5160 static inline void
5161 txgbe_l2_tn_filter_restore(struct rte_eth_dev *dev)
5162 {
5163         struct txgbe_l2_tn_info *l2_tn_info = TXGBE_DEV_L2_TN(dev);
5164         struct txgbe_l2_tn_filter *node;
5165         struct txgbe_l2_tunnel_conf l2_tn_conf;
5166
5167         TAILQ_FOREACH(node, &l2_tn_info->l2_tn_list, entries) {
5168                 l2_tn_conf.l2_tunnel_type = node->key.l2_tn_type;
5169                 l2_tn_conf.tunnel_id      = node->key.tn_id;
5170                 l2_tn_conf.pool           = node->pool;
5171                 (void)txgbe_dev_l2_tunnel_filter_add(dev, &l2_tn_conf, TRUE);
5172         }
5173 }
5174
5175 /* restore rss filter */
5176 static inline void
5177 txgbe_rss_filter_restore(struct rte_eth_dev *dev)
5178 {
5179         struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(dev);
5180
5181         if (filter_info->rss_info.conf.queue_num)
5182                 txgbe_config_rss_filter(dev,
5183                         &filter_info->rss_info, TRUE);
5184 }
5185
5186 static int
5187 txgbe_filter_restore(struct rte_eth_dev *dev)
5188 {
5189         txgbe_ntuple_filter_restore(dev);
5190         txgbe_ethertype_filter_restore(dev);
5191         txgbe_syn_filter_restore(dev);
5192         txgbe_fdir_filter_restore(dev);
5193         txgbe_l2_tn_filter_restore(dev);
5194         txgbe_rss_filter_restore(dev);
5195
5196         return 0;
5197 }
5198
5199 static void
5200 txgbe_l2_tunnel_conf(struct rte_eth_dev *dev)
5201 {
5202         struct txgbe_l2_tn_info *l2_tn_info = TXGBE_DEV_L2_TN(dev);
5203         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
5204
5205         if (l2_tn_info->e_tag_en)
5206                 (void)txgbe_e_tag_enable(hw);
5207
5208         if (l2_tn_info->e_tag_fwd_en)
5209                 (void)txgbe_e_tag_forwarding_en_dis(dev, 1);
5210
5211         (void)txgbe_update_e_tag_eth_type(hw, l2_tn_info->e_tag_ether_type);
5212 }
5213
5214 /* remove all the n-tuple filters */
5215 void
5216 txgbe_clear_all_ntuple_filter(struct rte_eth_dev *dev)
5217 {
5218         struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(dev);
5219         struct txgbe_5tuple_filter *p_5tuple;
5220
5221         while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list)))
5222                 txgbe_remove_5tuple_filter(dev, p_5tuple);
5223 }
5224
5225 /* remove all the ether type filters */
5226 void
5227 txgbe_clear_all_ethertype_filter(struct rte_eth_dev *dev)
5228 {
5229         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
5230         struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(dev);
5231         int i;
5232
5233         for (i = 0; i < TXGBE_ETF_ID_MAX; i++) {
5234                 if (filter_info->ethertype_mask & (1 << i) &&
5235                     !filter_info->ethertype_filters[i].conf) {
5236                         (void)txgbe_ethertype_filter_remove(filter_info,
5237                                                             (uint8_t)i);
5238                         wr32(hw, TXGBE_ETFLT(i), 0);
5239                         wr32(hw, TXGBE_ETCLS(i), 0);
5240                         txgbe_flush(hw);
5241                 }
5242         }
5243 }
5244
5245 /* remove the SYN filter */
5246 void
5247 txgbe_clear_syn_filter(struct rte_eth_dev *dev)
5248 {
5249         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
5250         struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(dev);
5251
5252         if (filter_info->syn_info & TXGBE_SYNCLS_ENA) {
5253                 filter_info->syn_info = 0;
5254
5255                 wr32(hw, TXGBE_SYNCLS, 0);
5256                 txgbe_flush(hw);
5257         }
5258 }
5259
5260 /* remove all the L2 tunnel filters */
5261 int
5262 txgbe_clear_all_l2_tn_filter(struct rte_eth_dev *dev)
5263 {
5264         struct txgbe_l2_tn_info *l2_tn_info = TXGBE_DEV_L2_TN(dev);
5265         struct txgbe_l2_tn_filter *l2_tn_filter;
5266         struct txgbe_l2_tunnel_conf l2_tn_conf;
5267         int ret = 0;
5268
5269         while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
5270                 l2_tn_conf.l2_tunnel_type = l2_tn_filter->key.l2_tn_type;
5271                 l2_tn_conf.tunnel_id      = l2_tn_filter->key.tn_id;
5272                 l2_tn_conf.pool           = l2_tn_filter->pool;
5273                 ret = txgbe_dev_l2_tunnel_filter_del(dev, &l2_tn_conf);
5274                 if (ret < 0)
5275                         return ret;
5276         }
5277
5278         return 0;
5279 }
5280
5281 static const struct eth_dev_ops txgbe_eth_dev_ops = {
5282         .dev_configure              = txgbe_dev_configure,
5283         .dev_infos_get              = txgbe_dev_info_get,
5284         .dev_start                  = txgbe_dev_start,
5285         .dev_stop                   = txgbe_dev_stop,
5286         .dev_set_link_up            = txgbe_dev_set_link_up,
5287         .dev_set_link_down          = txgbe_dev_set_link_down,
5288         .dev_close                  = txgbe_dev_close,
5289         .dev_reset                  = txgbe_dev_reset,
5290         .promiscuous_enable         = txgbe_dev_promiscuous_enable,
5291         .promiscuous_disable        = txgbe_dev_promiscuous_disable,
5292         .allmulticast_enable        = txgbe_dev_allmulticast_enable,
5293         .allmulticast_disable       = txgbe_dev_allmulticast_disable,
5294         .link_update                = txgbe_dev_link_update,
5295         .stats_get                  = txgbe_dev_stats_get,
5296         .xstats_get                 = txgbe_dev_xstats_get,
5297         .xstats_get_by_id           = txgbe_dev_xstats_get_by_id,
5298         .stats_reset                = txgbe_dev_stats_reset,
5299         .xstats_reset               = txgbe_dev_xstats_reset,
5300         .xstats_get_names           = txgbe_dev_xstats_get_names,
5301         .xstats_get_names_by_id     = txgbe_dev_xstats_get_names_by_id,
5302         .queue_stats_mapping_set    = txgbe_dev_queue_stats_mapping_set,
5303         .fw_version_get             = txgbe_fw_version_get,
5304         .dev_supported_ptypes_get   = txgbe_dev_supported_ptypes_get,
5305         .mtu_set                    = txgbe_dev_mtu_set,
5306         .vlan_filter_set            = txgbe_vlan_filter_set,
5307         .vlan_tpid_set              = txgbe_vlan_tpid_set,
5308         .vlan_offload_set           = txgbe_vlan_offload_set,
5309         .vlan_strip_queue_set       = txgbe_vlan_strip_queue_set,
5310         .rx_queue_start             = txgbe_dev_rx_queue_start,
5311         .rx_queue_stop              = txgbe_dev_rx_queue_stop,
5312         .tx_queue_start             = txgbe_dev_tx_queue_start,
5313         .tx_queue_stop              = txgbe_dev_tx_queue_stop,
5314         .rx_queue_setup             = txgbe_dev_rx_queue_setup,
5315         .rx_queue_intr_enable       = txgbe_dev_rx_queue_intr_enable,
5316         .rx_queue_intr_disable      = txgbe_dev_rx_queue_intr_disable,
5317         .rx_queue_release           = txgbe_dev_rx_queue_release,
5318         .tx_queue_setup             = txgbe_dev_tx_queue_setup,
5319         .tx_queue_release           = txgbe_dev_tx_queue_release,
5320         .dev_led_on                 = txgbe_dev_led_on,
5321         .dev_led_off                = txgbe_dev_led_off,
5322         .flow_ctrl_get              = txgbe_flow_ctrl_get,
5323         .flow_ctrl_set              = txgbe_flow_ctrl_set,
5324         .priority_flow_ctrl_set     = txgbe_priority_flow_ctrl_set,
5325         .mac_addr_add               = txgbe_add_rar,
5326         .mac_addr_remove            = txgbe_remove_rar,
5327         .mac_addr_set               = txgbe_set_default_mac_addr,
5328         .uc_hash_table_set          = txgbe_uc_hash_table_set,
5329         .uc_all_hash_table_set      = txgbe_uc_all_hash_table_set,
5330         .set_queue_rate_limit       = txgbe_set_queue_rate_limit,
5331         .reta_update                = txgbe_dev_rss_reta_update,
5332         .reta_query                 = txgbe_dev_rss_reta_query,
5333         .rss_hash_update            = txgbe_dev_rss_hash_update,
5334         .rss_hash_conf_get          = txgbe_dev_rss_hash_conf_get,
5335         .flow_ops_get               = txgbe_dev_flow_ops_get,
5336         .set_mc_addr_list           = txgbe_dev_set_mc_addr_list,
5337         .rxq_info_get               = txgbe_rxq_info_get,
5338         .txq_info_get               = txgbe_txq_info_get,
5339         .timesync_enable            = txgbe_timesync_enable,
5340         .timesync_disable           = txgbe_timesync_disable,
5341         .timesync_read_rx_timestamp = txgbe_timesync_read_rx_timestamp,
5342         .timesync_read_tx_timestamp = txgbe_timesync_read_tx_timestamp,
5343         .get_reg                    = txgbe_get_regs,
5344         .get_eeprom_length          = txgbe_get_eeprom_length,
5345         .get_eeprom                 = txgbe_get_eeprom,
5346         .set_eeprom                 = txgbe_set_eeprom,
5347         .get_module_info            = txgbe_get_module_info,
5348         .get_module_eeprom          = txgbe_get_module_eeprom,
5349         .get_dcb_info               = txgbe_dev_get_dcb_info,
5350         .timesync_adjust_time       = txgbe_timesync_adjust_time,
5351         .timesync_read_time         = txgbe_timesync_read_time,
5352         .timesync_write_time        = txgbe_timesync_write_time,
5353         .udp_tunnel_port_add        = txgbe_dev_udp_tunnel_port_add,
5354         .udp_tunnel_port_del        = txgbe_dev_udp_tunnel_port_del,
5355         .tm_ops_get                 = txgbe_tm_ops_get,
5356         .tx_done_cleanup            = txgbe_dev_tx_done_cleanup,
5357 };
5358
5359 RTE_PMD_REGISTER_PCI(net_txgbe, rte_txgbe_pmd);
5360 RTE_PMD_REGISTER_PCI_TABLE(net_txgbe, pci_id_txgbe_map);
5361 RTE_PMD_REGISTER_KMOD_DEP(net_txgbe, "* igb_uio | uio_pci_generic | vfio-pci");
5362 RTE_PMD_REGISTER_PARAM_STRING(net_txgbe,
5363                               TXGBE_DEVARG_BP_AUTO "=<0|1>"
5364                               TXGBE_DEVARG_KR_POLL "=<0|1>"
5365                               TXGBE_DEVARG_KR_PRESENT "=<0|1>"
5366                               TXGBE_DEVARG_KX_SGMII "=<0|1>"
5367                               TXGBE_DEVARG_FFE_SET "=<0-4>"
5368                               TXGBE_DEVARG_FFE_MAIN "=<uint16>"
5369                               TXGBE_DEVARG_FFE_PRE "=<uint16>"
5370                               TXGBE_DEVARG_FFE_POST "=<uint16>");
5371
5372 RTE_LOG_REGISTER_SUFFIX(txgbe_logtype_init, init, NOTICE);
5373 RTE_LOG_REGISTER_SUFFIX(txgbe_logtype_driver, driver, NOTICE);
5374 RTE_LOG_REGISTER_SUFFIX(txgbe_logtype_bp, bp, NOTICE);
5375
5376 #ifdef RTE_LIBRTE_TXGBE_DEBUG_RX
5377         RTE_LOG_REGISTER_SUFFIX(txgbe_logtype_rx, rx, DEBUG);
5378 #endif
5379 #ifdef RTE_LIBRTE_TXGBE_DEBUG_TX
5380         RTE_LOG_REGISTER_SUFFIX(txgbe_logtype_tx, tx, DEBUG);
5381 #endif
5382
5383 #ifdef RTE_LIBRTE_TXGBE_DEBUG_TX_FREE
5384         RTE_LOG_REGISTER_SUFFIX(txgbe_logtype_tx_free, tx_free, DEBUG);
5385 #endif