drivers/net/txgbe/txgbe_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2015-2020
   3  */
   4
   5 #include <stdio.h>
   6 #include <errno.h>
   7 #include <stdint.h>
   8 #include <string.h>
   9 #include <rte_common.h>
  10 #include <rte_ethdev_pci.h>
  11
  12 #include <rte_interrupts.h>
  13 #include <rte_log.h>
  14 #include <rte_debug.h>
  15 #include <rte_pci.h>
  16 #include <rte_memory.h>
  17 #include <rte_eal.h>
  18 #include <rte_alarm.h>
  19
  20 #include "txgbe_logs.h"
  21 #include "base/txgbe.h"
  22 #include "txgbe_ethdev.h"
  23 #include "txgbe_rxtx.h"
  24 #include "txgbe_regs_group.h"
  25
  26 static const struct reg_info txgbe_regs_general[] = {
  27         {TXGBE_RST, 1, 1, "TXGBE_RST"},
  28         {TXGBE_STAT, 1, 1, "TXGBE_STAT"},
  29         {TXGBE_PORTCTL, 1, 1, "TXGBE_PORTCTL"},
  30         {TXGBE_SDP, 1, 1, "TXGBE_SDP"},
  31         {TXGBE_SDPCTL, 1, 1, "TXGBE_SDPCTL"},
  32         {TXGBE_LEDCTL, 1, 1, "TXGBE_LEDCTL"},
  33         {0, 0, 0, ""}
  34 };
  35
  36 static const struct reg_info txgbe_regs_nvm[] = {
  37         {0, 0, 0, ""}
  38 };
  39
  40 static const struct reg_info txgbe_regs_interrupt[] = {
  41         {0, 0, 0, ""}
  42 };
  43
  44 static const struct reg_info txgbe_regs_fctl_others[] = {
  45         {0, 0, 0, ""}
  46 };
  47
  48 static const struct reg_info txgbe_regs_rxdma[] = {
  49         {0, 0, 0, ""}
  50 };
  51
  52 static const struct reg_info txgbe_regs_rx[] = {
  53         {0, 0, 0, ""}
  54 };
  55
  56 static struct reg_info txgbe_regs_tx[] = {
  57         {0, 0, 0, ""}
  58 };
  59
  60 static const struct reg_info txgbe_regs_wakeup[] = {
  61         {0, 0, 0, ""}
  62 };
  63
  64 static const struct reg_info txgbe_regs_dcb[] = {
  65         {0, 0, 0, ""}
  66 };
  67
  68 static const struct reg_info txgbe_regs_mac[] = {
  69         {0, 0, 0, ""}
  70 };
  71
  72 static const struct reg_info txgbe_regs_diagnostic[] = {
  73         {0, 0, 0, ""},
  74 };
  75
  76 /* PF registers */
  77 static const struct reg_info *txgbe_regs_others[] = {
  78                                 txgbe_regs_general,
  79                                 txgbe_regs_nvm,
  80                                 txgbe_regs_interrupt,
  81                                 txgbe_regs_fctl_others,
  82                                 txgbe_regs_rxdma,
  83                                 txgbe_regs_rx,
  84                                 txgbe_regs_tx,
  85                                 txgbe_regs_wakeup,
  86                                 txgbe_regs_dcb,
  87                                 txgbe_regs_mac,
  88                                 txgbe_regs_diagnostic,
  89                                 NULL};
  90
  91 static int  txgbe_dev_set_link_up(struct rte_eth_dev *dev);
  92 static int  txgbe_dev_set_link_down(struct rte_eth_dev *dev);
  93 static int txgbe_dev_close(struct rte_eth_dev *dev);
  94 static int txgbe_dev_link_update(struct rte_eth_dev *dev,
  95                                 int wait_to_complete);
  96 static int txgbe_dev_stats_reset(struct rte_eth_dev *dev);
  97 static void txgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
  98 static void txgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev,
  99                                         uint16_t queue);
 100
 101 static void txgbe_dev_link_status_print(struct rte_eth_dev *dev);
 102 static int txgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on);
 103 static int txgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev);
 104 static int txgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
 105 static int txgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
 106 static int txgbe_dev_interrupt_action(struct rte_eth_dev *dev,
 107                                       struct rte_intr_handle *handle);
 108 static void txgbe_dev_interrupt_handler(void *param);
 109 static void txgbe_dev_interrupt_delayed_handler(void *param);
 110 static void txgbe_configure_msix(struct rte_eth_dev *dev);
 111
 112 #define TXGBE_SET_HWSTRIP(h, q) do {\
 113                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 114                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 115                 (h)->bitmap[idx] |= 1 << bit;\
 116         } while (0)
 117
 118 #define TXGBE_CLEAR_HWSTRIP(h, q) do {\
 119                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 120                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 121                 (h)->bitmap[idx] &= ~(1 << bit);\
 122         } while (0)
 123
 124 #define TXGBE_GET_HWSTRIP(h, q, r) do {\
 125                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 126                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 127                 (r) = (h)->bitmap[idx] >> bit & 1;\
 128         } while (0)
 129
 130 /*
 131  * The set of PCI devices this driver supports
 132  */
 133 static const struct rte_pci_id pci_id_txgbe_map[] = {
 134         { RTE_PCI_DEVICE(PCI_VENDOR_ID_WANGXUN, TXGBE_DEV_ID_RAPTOR_SFP) },
 135         { RTE_PCI_DEVICE(PCI_VENDOR_ID_WANGXUN, TXGBE_DEV_ID_WX1820_SFP) },
 136         { .vendor_id = 0, /* sentinel */ },
 137 };
 138
 139 static const struct rte_eth_desc_lim rx_desc_lim = {
 140         .nb_max = TXGBE_RING_DESC_MAX,
 141         .nb_min = TXGBE_RING_DESC_MIN,
 142         .nb_align = TXGBE_RXD_ALIGN,
 143 };
 144
 145 static const struct rte_eth_desc_lim tx_desc_lim = {
 146         .nb_max = TXGBE_RING_DESC_MAX,
 147         .nb_min = TXGBE_RING_DESC_MIN,
 148         .nb_align = TXGBE_TXD_ALIGN,
 149         .nb_seg_max = TXGBE_TX_MAX_SEG,
 150         .nb_mtu_seg_max = TXGBE_TX_MAX_SEG,
 151 };
 152
 153 static const struct eth_dev_ops txgbe_eth_dev_ops;
 154
 155 #define HW_XSTAT(m) {#m, offsetof(struct txgbe_hw_stats, m)}
 156 #define HW_XSTAT_NAME(m, n) {n, offsetof(struct txgbe_hw_stats, m)}
 157 static const struct rte_txgbe_xstats_name_off rte_txgbe_stats_strings[] = {
 158         /* MNG RxTx */
 159         HW_XSTAT(mng_bmc2host_packets),
 160         HW_XSTAT(mng_host2bmc_packets),
 161         /* Basic RxTx */
 162         HW_XSTAT(rx_packets),
 163         HW_XSTAT(tx_packets),
 164         HW_XSTAT(rx_bytes),
 165         HW_XSTAT(tx_bytes),
 166         HW_XSTAT(rx_total_bytes),
 167         HW_XSTAT(rx_total_packets),
 168         HW_XSTAT(tx_total_packets),
 169         HW_XSTAT(rx_total_missed_packets),
 170         HW_XSTAT(rx_broadcast_packets),
 171         HW_XSTAT(rx_multicast_packets),
 172         HW_XSTAT(rx_management_packets),
 173         HW_XSTAT(tx_management_packets),
 174         HW_XSTAT(rx_management_dropped),
 175
 176         /* Basic Error */
 177         HW_XSTAT(rx_crc_errors),
 178         HW_XSTAT(rx_illegal_byte_errors),
 179         HW_XSTAT(rx_error_bytes),
 180         HW_XSTAT(rx_mac_short_packet_dropped),
 181         HW_XSTAT(rx_length_errors),
 182         HW_XSTAT(rx_undersize_errors),
 183         HW_XSTAT(rx_fragment_errors),
 184         HW_XSTAT(rx_oversize_errors),
 185         HW_XSTAT(rx_jabber_errors),
 186         HW_XSTAT(rx_l3_l4_xsum_error),
 187         HW_XSTAT(mac_local_errors),
 188         HW_XSTAT(mac_remote_errors),
 189
 190         /* Flow Director */
 191         HW_XSTAT(flow_director_added_filters),
 192         HW_XSTAT(flow_director_removed_filters),
 193         HW_XSTAT(flow_director_filter_add_errors),
 194         HW_XSTAT(flow_director_filter_remove_errors),
 195         HW_XSTAT(flow_director_matched_filters),
 196         HW_XSTAT(flow_director_missed_filters),
 197
 198         /* FCoE */
 199         HW_XSTAT(rx_fcoe_crc_errors),
 200         HW_XSTAT(rx_fcoe_mbuf_allocation_errors),
 201         HW_XSTAT(rx_fcoe_dropped),
 202         HW_XSTAT(rx_fcoe_packets),
 203         HW_XSTAT(tx_fcoe_packets),
 204         HW_XSTAT(rx_fcoe_bytes),
 205         HW_XSTAT(tx_fcoe_bytes),
 206         HW_XSTAT(rx_fcoe_no_ddp),
 207         HW_XSTAT(rx_fcoe_no_ddp_ext_buff),
 208
 209         /* MACSEC */
 210         HW_XSTAT(tx_macsec_pkts_untagged),
 211         HW_XSTAT(tx_macsec_pkts_encrypted),
 212         HW_XSTAT(tx_macsec_pkts_protected),
 213         HW_XSTAT(tx_macsec_octets_encrypted),
 214         HW_XSTAT(tx_macsec_octets_protected),
 215         HW_XSTAT(rx_macsec_pkts_untagged),
 216         HW_XSTAT(rx_macsec_pkts_badtag),
 217         HW_XSTAT(rx_macsec_pkts_nosci),
 218         HW_XSTAT(rx_macsec_pkts_unknownsci),
 219         HW_XSTAT(rx_macsec_octets_decrypted),
 220         HW_XSTAT(rx_macsec_octets_validated),
 221         HW_XSTAT(rx_macsec_sc_pkts_unchecked),
 222         HW_XSTAT(rx_macsec_sc_pkts_delayed),
 223         HW_XSTAT(rx_macsec_sc_pkts_late),
 224         HW_XSTAT(rx_macsec_sa_pkts_ok),
 225         HW_XSTAT(rx_macsec_sa_pkts_invalid),
 226         HW_XSTAT(rx_macsec_sa_pkts_notvalid),
 227         HW_XSTAT(rx_macsec_sa_pkts_unusedsa),
 228         HW_XSTAT(rx_macsec_sa_pkts_notusingsa),
 229
 230         /* MAC RxTx */
 231         HW_XSTAT(rx_size_64_packets),
 232         HW_XSTAT(rx_size_65_to_127_packets),
 233         HW_XSTAT(rx_size_128_to_255_packets),
 234         HW_XSTAT(rx_size_256_to_511_packets),
 235         HW_XSTAT(rx_size_512_to_1023_packets),
 236         HW_XSTAT(rx_size_1024_to_max_packets),
 237         HW_XSTAT(tx_size_64_packets),
 238         HW_XSTAT(tx_size_65_to_127_packets),
 239         HW_XSTAT(tx_size_128_to_255_packets),
 240         HW_XSTAT(tx_size_256_to_511_packets),
 241         HW_XSTAT(tx_size_512_to_1023_packets),
 242         HW_XSTAT(tx_size_1024_to_max_packets),
 243
 244         /* Flow Control */
 245         HW_XSTAT(tx_xon_packets),
 246         HW_XSTAT(rx_xon_packets),
 247         HW_XSTAT(tx_xoff_packets),
 248         HW_XSTAT(rx_xoff_packets),
 249
 250         HW_XSTAT_NAME(tx_xon_packets, "tx_flow_control_xon_packets"),
 251         HW_XSTAT_NAME(rx_xon_packets, "rx_flow_control_xon_packets"),
 252         HW_XSTAT_NAME(tx_xoff_packets, "tx_flow_control_xoff_packets"),
 253         HW_XSTAT_NAME(rx_xoff_packets, "rx_flow_control_xoff_packets"),
 254 };
 255
 256 #define TXGBE_NB_HW_STATS (sizeof(rte_txgbe_stats_strings) / \
 257                            sizeof(rte_txgbe_stats_strings[0]))
 258
 259 /* Per-priority statistics */
 260 #define UP_XSTAT(m) {#m, offsetof(struct txgbe_hw_stats, up[0].m)}
 261 static const struct rte_txgbe_xstats_name_off rte_txgbe_up_strings[] = {
 262         UP_XSTAT(rx_up_packets),
 263         UP_XSTAT(tx_up_packets),
 264         UP_XSTAT(rx_up_bytes),
 265         UP_XSTAT(tx_up_bytes),
 266         UP_XSTAT(rx_up_drop_packets),
 267
 268         UP_XSTAT(tx_up_xon_packets),
 269         UP_XSTAT(rx_up_xon_packets),
 270         UP_XSTAT(tx_up_xoff_packets),
 271         UP_XSTAT(rx_up_xoff_packets),
 272         UP_XSTAT(rx_up_dropped),
 273         UP_XSTAT(rx_up_mbuf_alloc_errors),
 274         UP_XSTAT(tx_up_xon2off_packets),
 275 };
 276
 277 #define TXGBE_NB_UP_STATS (sizeof(rte_txgbe_up_strings) / \
 278                            sizeof(rte_txgbe_up_strings[0]))
 279
 280 /* Per-queue statistics */
 281 #define QP_XSTAT(m) {#m, offsetof(struct txgbe_hw_stats, qp[0].m)}
 282 static const struct rte_txgbe_xstats_name_off rte_txgbe_qp_strings[] = {
 283         QP_XSTAT(rx_qp_packets),
 284         QP_XSTAT(tx_qp_packets),
 285         QP_XSTAT(rx_qp_bytes),
 286         QP_XSTAT(tx_qp_bytes),
 287         QP_XSTAT(rx_qp_mc_packets),
 288 };
 289
 290 #define TXGBE_NB_QP_STATS (sizeof(rte_txgbe_qp_strings) / \
 291                            sizeof(rte_txgbe_qp_strings[0]))
 292
 293 static inline int
 294 txgbe_is_sfp(struct txgbe_hw *hw)
 295 {
 296         switch (hw->phy.type) {
 297         case txgbe_phy_sfp_avago:
 298         case txgbe_phy_sfp_ftl:
 299         case txgbe_phy_sfp_intel:
 300         case txgbe_phy_sfp_unknown:
 301         case txgbe_phy_sfp_tyco_passive:
 302         case txgbe_phy_sfp_unknown_passive:
 303                 return 1;
 304         default:
 305                 return 0;
 306         }
 307 }
 308
 309 static inline int32_t
 310 txgbe_pf_reset_hw(struct txgbe_hw *hw)
 311 {
 312         uint32_t ctrl_ext;
 313         int32_t status;
 314
 315         status = hw->mac.reset_hw(hw);
 316
 317         ctrl_ext = rd32(hw, TXGBE_PORTCTL);
 318         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 319         ctrl_ext |= TXGBE_PORTCTL_RSTDONE;
 320         wr32(hw, TXGBE_PORTCTL, ctrl_ext);
 321         txgbe_flush(hw);
 322
 323         if (status == TXGBE_ERR_SFP_NOT_PRESENT)
 324                 status = 0;
 325         return status;
 326 }
 327
 328 static inline void
 329 txgbe_enable_intr(struct rte_eth_dev *dev)
 330 {
 331         struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);
 332         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
 333
 334         wr32(hw, TXGBE_IENMISC, intr->mask_misc);
 335         wr32(hw, TXGBE_IMC(0), TXGBE_IMC_MASK);
 336         wr32(hw, TXGBE_IMC(1), TXGBE_IMC_MASK);
 337         txgbe_flush(hw);
 338 }
 339
 340 static void
 341 txgbe_disable_intr(struct txgbe_hw *hw)
 342 {
 343         PMD_INIT_FUNC_TRACE();
 344
 345         wr32(hw, TXGBE_IENMISC, ~BIT_MASK32);
 346         wr32(hw, TXGBE_IMS(0), TXGBE_IMC_MASK);
 347         wr32(hw, TXGBE_IMS(1), TXGBE_IMC_MASK);
 348         txgbe_flush(hw);
 349 }
 350
 351 static int
 352 txgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 353                                   uint16_t queue_id,
 354                                   uint8_t stat_idx,
 355                                   uint8_t is_rx)
 356 {
 357         struct txgbe_hw *hw = TXGBE_DEV_HW(eth_dev);
 358         struct txgbe_stat_mappings *stat_mappings =
 359                 TXGBE_DEV_STAT_MAPPINGS(eth_dev);
 360         uint32_t qsmr_mask = 0;
 361         uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
 362         uint32_t q_map;
 363         uint8_t n, offset;
 364
 365         if (hw->mac.type != txgbe_mac_raptor)
 366                 return -ENOSYS;
 367
 368         if (stat_idx & !QMAP_FIELD_RESERVED_BITS_MASK)
 369                 return -EIO;
 370
 371         PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d",
 372                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 373                      queue_id, stat_idx);
 374
 375         n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
 376         if (n >= TXGBE_NB_STAT_MAPPING) {
 377                 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
 378                 return -EIO;
 379         }
 380         offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
 381
 382         /* Now clear any previous stat_idx set */
 383         clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 384         if (!is_rx)
 385                 stat_mappings->tqsm[n] &= ~clearing_mask;
 386         else
 387                 stat_mappings->rqsm[n] &= ~clearing_mask;
 388
 389         q_map = (uint32_t)stat_idx;
 390         q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
 391         qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 392         if (!is_rx)
 393                 stat_mappings->tqsm[n] |= qsmr_mask;
 394         else
 395                 stat_mappings->rqsm[n] |= qsmr_mask;
 396
 397         PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d",
 398                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 399                      queue_id, stat_idx);
 400         PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
 401                      is_rx ? stat_mappings->rqsm[n] : stat_mappings->tqsm[n]);
 402         return 0;
 403 }
 404
 405 static void
 406 txgbe_dcb_init(struct txgbe_hw *hw, struct txgbe_dcb_config *dcb_config)
 407 {
 408         int i;
 409         u8 bwgp;
 410         struct txgbe_dcb_tc_config *tc;
 411
 412         UNREFERENCED_PARAMETER(hw);
 413
 414         dcb_config->num_tcs.pg_tcs = TXGBE_DCB_TC_MAX;
 415         dcb_config->num_tcs.pfc_tcs = TXGBE_DCB_TC_MAX;
 416         bwgp = (u8)(100 / TXGBE_DCB_TC_MAX);
 417         for (i = 0; i < TXGBE_DCB_TC_MAX; i++) {
 418                 tc = &dcb_config->tc_config[i];
 419                 tc->path[TXGBE_DCB_TX_CONFIG].bwg_id = i;
 420                 tc->path[TXGBE_DCB_TX_CONFIG].bwg_percent = bwgp + (i & 1);
 421                 tc->path[TXGBE_DCB_RX_CONFIG].bwg_id = i;
 422                 tc->path[TXGBE_DCB_RX_CONFIG].bwg_percent = bwgp + (i & 1);
 423                 tc->pfc = txgbe_dcb_pfc_disabled;
 424         }
 425
 426         /* Initialize default user to priority mapping, UPx->TC0 */
 427         tc = &dcb_config->tc_config[0];
 428         tc->path[TXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
 429         tc->path[TXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
 430         for (i = 0; i < TXGBE_DCB_BWG_MAX; i++) {
 431                 dcb_config->bw_percentage[i][TXGBE_DCB_TX_CONFIG] = 100;
 432                 dcb_config->bw_percentage[i][TXGBE_DCB_RX_CONFIG] = 100;
 433         }
 434         dcb_config->rx_pba_cfg = txgbe_dcb_pba_equal;
 435         dcb_config->pfc_mode_enable = false;
 436         dcb_config->vt_mode = true;
 437         dcb_config->round_robin_enable = false;
 438         /* support all DCB capabilities */
 439         dcb_config->support.capabilities = 0xFF;
 440 }
 441
 442 /*
 443  * Ensure that all locks are released before first NVM or PHY access
 444  */
 445 static void
 446 txgbe_swfw_lock_reset(struct txgbe_hw *hw)
 447 {
 448         uint16_t mask;
 449
 450         /*
 451          * These ones are more tricky since they are common to all ports; but
 452          * swfw_sync retries last long enough (1s) to be almost sure that if
 453          * lock can not be taken it is due to an improper lock of the
 454          * semaphore.
 455          */
 456         mask = TXGBE_MNGSEM_SWPHY |
 457                TXGBE_MNGSEM_SWMBX |
 458                TXGBE_MNGSEM_SWFLASH;
 459         if (hw->mac.acquire_swfw_sync(hw, mask) < 0)
 460                 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
 461
 462         hw->mac.release_swfw_sync(hw, mask);
 463 }
 464
 465 static int
 466 eth_txgbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params __rte_unused)
 467 {
 468         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
 469         struct txgbe_hw *hw = TXGBE_DEV_HW(eth_dev);
 470         struct txgbe_vfta *shadow_vfta = TXGBE_DEV_VFTA(eth_dev);
 471         struct txgbe_hwstrip *hwstrip = TXGBE_DEV_HWSTRIP(eth_dev);
 472         struct txgbe_dcb_config *dcb_config = TXGBE_DEV_DCB_CONFIG(eth_dev);
 473         struct txgbe_bw_conf *bw_conf = TXGBE_DEV_BW_CONF(eth_dev);
 474         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 475         const struct rte_memzone *mz;
 476         uint32_t ctrl_ext;
 477         uint16_t csum;
 478         int err, i;
 479
 480         PMD_INIT_FUNC_TRACE();
 481
 482         eth_dev->dev_ops = &txgbe_eth_dev_ops;
 483         eth_dev->rx_pkt_burst = &txgbe_recv_pkts;
 484         eth_dev->tx_pkt_burst = &txgbe_xmit_pkts;
 485         eth_dev->tx_pkt_prepare = &txgbe_prep_pkts;
 486
 487         /*
 488          * For secondary processes, we don't initialise any further as primary
 489          * has already done this work. Only check we don't need a different
 490          * RX and TX function.
 491          */
 492         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
 493                 struct txgbe_tx_queue *txq;
 494                 /* TX queue function in primary, set by last queue initialized
 495                  * Tx queue may not initialized by primary process
 496                  */
 497                 if (eth_dev->data->tx_queues) {
 498                         uint16_t nb_tx_queues = eth_dev->data->nb_tx_queues;
 499                         txq = eth_dev->data->tx_queues[nb_tx_queues - 1];
 500                         txgbe_set_tx_function(eth_dev, txq);
 501                 } else {
 502                         /* Use default TX function if we get here */
 503                         PMD_INIT_LOG(NOTICE, "No TX queues configured yet. "
 504                                      "Using default TX function.");
 505                 }
 506
 507                 txgbe_set_rx_function(eth_dev);
 508
 509                 return 0;
 510         }
 511
 512         rte_eth_copy_pci_info(eth_dev, pci_dev);
 513
 514         /* Vendor and Device ID need to be set before init of shared code */
 515         hw->device_id = pci_dev->id.device_id;
 516         hw->vendor_id = pci_dev->id.vendor_id;
 517         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
 518         hw->allow_unsupported_sfp = 1;
 519
 520         /* Reserve memory for interrupt status block */
 521         mz = rte_eth_dma_zone_reserve(eth_dev, "txgbe_driver", -1,
 522                 16, TXGBE_ALIGN, SOCKET_ID_ANY);
 523         if (mz == NULL)
 524                 return -ENOMEM;
 525
 526         hw->isb_dma = TMZ_PADDR(mz);
 527         hw->isb_mem = TMZ_VADDR(mz);
 528
 529         /* Initialize the shared code (base driver) */
 530         err = txgbe_init_shared_code(hw);
 531         if (err != 0) {
 532                 PMD_INIT_LOG(ERR, "Shared code init failed: %d", err);
 533                 return -EIO;
 534         }
 535
 536         /* Unlock any pending hardware semaphore */
 537         txgbe_swfw_lock_reset(hw);
 538
 539         /* Initialize DCB configuration*/
 540         memset(dcb_config, 0, sizeof(struct txgbe_dcb_config));
 541         txgbe_dcb_init(hw, dcb_config);
 542
 543         /* Get Hardware Flow Control setting */
 544         hw->fc.requested_mode = txgbe_fc_full;
 545         hw->fc.current_mode = txgbe_fc_full;
 546         hw->fc.pause_time = TXGBE_FC_PAUSE_TIME;
 547         for (i = 0; i < TXGBE_DCB_TC_MAX; i++) {
 548                 hw->fc.low_water[i] = TXGBE_FC_XON_LOTH;
 549                 hw->fc.high_water[i] = TXGBE_FC_XOFF_HITH;
 550         }
 551         hw->fc.send_xon = 1;
 552
 553         err = hw->rom.init_params(hw);
 554         if (err != 0) {
 555                 PMD_INIT_LOG(ERR, "The EEPROM init failed: %d", err);
 556                 return -EIO;
 557         }
 558
 559         /* Make sure we have a good EEPROM before we read from it */
 560         err = hw->rom.validate_checksum(hw, &csum);
 561         if (err != 0) {
 562                 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", err);
 563                 return -EIO;
 564         }
 565
 566         err = hw->mac.init_hw(hw);
 567
 568         /*
 569          * Devices with copper phys will fail to initialise if txgbe_init_hw()
 570          * is called too soon after the kernel driver unbinding/binding occurs.
 571          * The failure occurs in txgbe_identify_phy() for all devices,
 572          * but for non-copper devies, txgbe_identify_sfp_module() is
 573          * also called. See txgbe_identify_phy(). The reason for the
 574          * failure is not known, and only occuts when virtualisation features
 575          * are disabled in the bios. A delay of 200ms  was found to be enough by
 576          * trial-and-error, and is doubled to be safe.
 577          */
 578         if (err && hw->phy.media_type == txgbe_media_type_copper) {
 579                 rte_delay_ms(200);
 580                 err = hw->mac.init_hw(hw);
 581         }
 582
 583         if (err == TXGBE_ERR_SFP_NOT_PRESENT)
 584                 err = 0;
 585
 586         if (err == TXGBE_ERR_EEPROM_VERSION) {
 587                 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
 588                              "LOM.  Please be aware there may be issues associated "
 589                              "with your hardware.");
 590                 PMD_INIT_LOG(ERR, "If you are experiencing problems "
 591                              "please contact your hardware representative "
 592                              "who provided you with this hardware.");
 593         } else if (err == TXGBE_ERR_SFP_NOT_SUPPORTED) {
 594                 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
 595         }
 596         if (err) {
 597                 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", err);
 598                 return -EIO;
 599         }
 600
 601         /* Reset the hw statistics */
 602         txgbe_dev_stats_reset(eth_dev);
 603
 604         /* disable interrupt */
 605         txgbe_disable_intr(hw);
 606
 607         /* Allocate memory for storing MAC addresses */
 608         eth_dev->data->mac_addrs = rte_zmalloc("txgbe", RTE_ETHER_ADDR_LEN *
 609                                                hw->mac.num_rar_entries, 0);
 610         if (eth_dev->data->mac_addrs == NULL) {
 611                 PMD_INIT_LOG(ERR,
 612                              "Failed to allocate %u bytes needed to store "
 613                              "MAC addresses",
 614                              RTE_ETHER_ADDR_LEN * hw->mac.num_rar_entries);
 615                 return -ENOMEM;
 616         }
 617
 618         /* Copy the permanent MAC address */
 619         rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.perm_addr,
 620                         &eth_dev->data->mac_addrs[0]);
 621
 622         /* Allocate memory for storing hash filter MAC addresses */
 623         eth_dev->data->hash_mac_addrs = rte_zmalloc("txgbe",
 624                         RTE_ETHER_ADDR_LEN * TXGBE_VMDQ_NUM_UC_MAC, 0);
 625         if (eth_dev->data->hash_mac_addrs == NULL) {
 626                 PMD_INIT_LOG(ERR,
 627                              "Failed to allocate %d bytes needed to store MAC addresses",
 628                              RTE_ETHER_ADDR_LEN * TXGBE_VMDQ_NUM_UC_MAC);
 629                 return -ENOMEM;
 630         }
 631
 632         /* initialize the vfta */
 633         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
 634
 635         /* initialize the hw strip bitmap*/
 636         memset(hwstrip, 0, sizeof(*hwstrip));
 637
 638         /* initialize PF if max_vfs not zero */
 639         txgbe_pf_host_init(eth_dev);
 640
 641         ctrl_ext = rd32(hw, TXGBE_PORTCTL);
 642         /* let hardware know driver is loaded */
 643         ctrl_ext |= TXGBE_PORTCTL_DRVLOAD;
 644         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 645         ctrl_ext |= TXGBE_PORTCTL_RSTDONE;
 646         wr32(hw, TXGBE_PORTCTL, ctrl_ext);
 647         txgbe_flush(hw);
 648
 649         if (txgbe_is_sfp(hw) && hw->phy.sfp_type != txgbe_sfp_type_not_present)
 650                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
 651                              (int)hw->mac.type, (int)hw->phy.type,
 652                              (int)hw->phy.sfp_type);
 653         else
 654                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
 655                              (int)hw->mac.type, (int)hw->phy.type);
 656
 657         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
 658                      eth_dev->data->port_id, pci_dev->id.vendor_id,
 659                      pci_dev->id.device_id);
 660
 661         rte_intr_callback_register(intr_handle,
 662                                    txgbe_dev_interrupt_handler, eth_dev);
 663
 664         /* enable uio/vfio intr/eventfd mapping */
 665         rte_intr_enable(intr_handle);
 666
 667         /* enable support intr */
 668         txgbe_enable_intr(eth_dev);
 669
 670         /* initialize bandwidth configuration info */
 671         memset(bw_conf, 0, sizeof(struct txgbe_bw_conf));
 672
 673         return 0;
 674 }
 675
 676 static int
 677 eth_txgbe_dev_uninit(struct rte_eth_dev *eth_dev)
 678 {
 679         PMD_INIT_FUNC_TRACE();
 680
 681         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 682                 return 0;
 683
 684         txgbe_dev_close(eth_dev);
 685
 686         return 0;
 687 }
 688
 689 static int
 690 eth_txgbe_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
 691                 struct rte_pci_device *pci_dev)
 692 {
 693         struct rte_eth_dev *pf_ethdev;
 694         struct rte_eth_devargs eth_da;
 695         int retval;
 696
 697         if (pci_dev->device.devargs) {
 698                 retval = rte_eth_devargs_parse(pci_dev->device.devargs->args,
 699                                 &eth_da);
 700                 if (retval)
 701                         return retval;
 702         } else {
 703                 memset(&eth_da, 0, sizeof(eth_da));
 704         }
 705
 706         retval = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
 707                         sizeof(struct txgbe_adapter),
 708                         eth_dev_pci_specific_init, pci_dev,
 709                         eth_txgbe_dev_init, NULL);
 710
 711         if (retval || eth_da.nb_representor_ports < 1)
 712                 return retval;
 713
 714         pf_ethdev = rte_eth_dev_allocated(pci_dev->device.name);
 715         if (pf_ethdev == NULL)
 716                 return -ENODEV;
 717
 718         return 0;
 719 }
 720
 721 static int eth_txgbe_pci_remove(struct rte_pci_device *pci_dev)
 722 {
 723         struct rte_eth_dev *ethdev;
 724
 725         ethdev = rte_eth_dev_allocated(pci_dev->device.name);
 726         if (!ethdev)
 727                 return -ENODEV;
 728
 729         return rte_eth_dev_destroy(ethdev, eth_txgbe_dev_uninit);
 730 }
 731
 732 static struct rte_pci_driver rte_txgbe_pmd = {
 733         .id_table = pci_id_txgbe_map,
 734         .drv_flags = RTE_PCI_DRV_NEED_MAPPING |
 735                      RTE_PCI_DRV_INTR_LSC,
 736         .probe = eth_txgbe_pci_probe,
 737         .remove = eth_txgbe_pci_remove,
 738 };
 739
 740 static int
 741 txgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
 742 {
 743         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
 744         struct txgbe_vfta *shadow_vfta = TXGBE_DEV_VFTA(dev);
 745         uint32_t vfta;
 746         uint32_t vid_idx;
 747         uint32_t vid_bit;
 748
 749         vid_idx = (uint32_t)((vlan_id >> 5) & 0x7F);
 750         vid_bit = (uint32_t)(1 << (vlan_id & 0x1F));
 751         vfta = rd32(hw, TXGBE_VLANTBL(vid_idx));
 752         if (on)
 753                 vfta |= vid_bit;
 754         else
 755                 vfta &= ~vid_bit;
 756         wr32(hw, TXGBE_VLANTBL(vid_idx), vfta);
 757
 758         /* update local VFTA copy */
 759         shadow_vfta->vfta[vid_idx] = vfta;
 760
 761         return 0;
 762 }
 763
 764 static void
 765 txgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
 766 {
 767         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
 768         struct txgbe_rx_queue *rxq;
 769         bool restart;
 770         uint32_t rxcfg, rxbal, rxbah;
 771
 772         if (on)
 773                 txgbe_vlan_hw_strip_enable(dev, queue);
 774         else
 775                 txgbe_vlan_hw_strip_disable(dev, queue);
 776
 777         rxq = dev->data->rx_queues[queue];
 778         rxbal = rd32(hw, TXGBE_RXBAL(rxq->reg_idx));
 779         rxbah = rd32(hw, TXGBE_RXBAH(rxq->reg_idx));
 780         rxcfg = rd32(hw, TXGBE_RXCFG(rxq->reg_idx));
 781         if (rxq->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) {
 782                 restart = (rxcfg & TXGBE_RXCFG_ENA) &&
 783                         !(rxcfg & TXGBE_RXCFG_VLAN);
 784                 rxcfg |= TXGBE_RXCFG_VLAN;
 785         } else {
 786                 restart = (rxcfg & TXGBE_RXCFG_ENA) &&
 787                         (rxcfg & TXGBE_RXCFG_VLAN);
 788                 rxcfg &= ~TXGBE_RXCFG_VLAN;
 789         }
 790         rxcfg &= ~TXGBE_RXCFG_ENA;
 791
 792         if (restart) {
 793                 /* set vlan strip for ring */
 794                 txgbe_dev_rx_queue_stop(dev, queue);
 795                 wr32(hw, TXGBE_RXBAL(rxq->reg_idx), rxbal);
 796                 wr32(hw, TXGBE_RXBAH(rxq->reg_idx), rxbah);
 797                 wr32(hw, TXGBE_RXCFG(rxq->reg_idx), rxcfg);
 798                 txgbe_dev_rx_queue_start(dev, queue);
 799         }
 800 }
 801
 802 static int
 803 txgbe_vlan_tpid_set(struct rte_eth_dev *dev,
 804                     enum rte_vlan_type vlan_type,
 805                     uint16_t tpid)
 806 {
 807         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
 808         int ret = 0;
 809         uint32_t portctrl, vlan_ext, qinq;
 810
 811         portctrl = rd32(hw, TXGBE_PORTCTL);
 812
 813         vlan_ext = (portctrl & TXGBE_PORTCTL_VLANEXT);
 814         qinq = vlan_ext && (portctrl & TXGBE_PORTCTL_QINQ);
 815         switch (vlan_type) {
 816         case ETH_VLAN_TYPE_INNER:
 817                 if (vlan_ext) {
 818                         wr32m(hw, TXGBE_VLANCTL,
 819                                 TXGBE_VLANCTL_TPID_MASK,
 820                                 TXGBE_VLANCTL_TPID(tpid));
 821                         wr32m(hw, TXGBE_DMATXCTRL,
 822                                 TXGBE_DMATXCTRL_TPID_MASK,
 823                                 TXGBE_DMATXCTRL_TPID(tpid));
 824                 } else {
 825                         ret = -ENOTSUP;
 826                         PMD_DRV_LOG(ERR, "Inner type is not supported"
 827                                     " by single VLAN");
 828                 }
 829
 830                 if (qinq) {
 831                         wr32m(hw, TXGBE_TAGTPID(0),
 832                                 TXGBE_TAGTPID_LSB_MASK,
 833                                 TXGBE_TAGTPID_LSB(tpid));
 834                 }
 835                 break;
 836         case ETH_VLAN_TYPE_OUTER:
 837                 if (vlan_ext) {
 838                         /* Only the high 16-bits is valid */
 839                         wr32m(hw, TXGBE_EXTAG,
 840                                 TXGBE_EXTAG_VLAN_MASK,
 841                                 TXGBE_EXTAG_VLAN(tpid));
 842                 } else {
 843                         wr32m(hw, TXGBE_VLANCTL,
 844                                 TXGBE_VLANCTL_TPID_MASK,
 845                                 TXGBE_VLANCTL_TPID(tpid));
 846                         wr32m(hw, TXGBE_DMATXCTRL,
 847                                 TXGBE_DMATXCTRL_TPID_MASK,
 848                                 TXGBE_DMATXCTRL_TPID(tpid));
 849                 }
 850
 851                 if (qinq) {
 852                         wr32m(hw, TXGBE_TAGTPID(0),
 853                                 TXGBE_TAGTPID_MSB_MASK,
 854                                 TXGBE_TAGTPID_MSB(tpid));
 855                 }
 856                 break;
 857         default:
 858                 PMD_DRV_LOG(ERR, "Unsupported VLAN type %d", vlan_type);
 859                 return -EINVAL;
 860         }
 861
 862         return ret;
 863 }
 864
 865 void
 866 txgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
 867 {
 868         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
 869         uint32_t vlnctrl;
 870
 871         PMD_INIT_FUNC_TRACE();
 872
 873         /* Filter Table Disable */
 874         vlnctrl = rd32(hw, TXGBE_VLANCTL);
 875         vlnctrl &= ~TXGBE_VLANCTL_VFE;
 876         wr32(hw, TXGBE_VLANCTL, vlnctrl);
 877 }
 878
 879 void
 880 txgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
 881 {
 882         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
 883         struct txgbe_vfta *shadow_vfta = TXGBE_DEV_VFTA(dev);
 884         uint32_t vlnctrl;
 885         uint16_t i;
 886
 887         PMD_INIT_FUNC_TRACE();
 888
 889         /* Filter Table Enable */
 890         vlnctrl = rd32(hw, TXGBE_VLANCTL);
 891         vlnctrl &= ~TXGBE_VLANCTL_CFIENA;
 892         vlnctrl |= TXGBE_VLANCTL_VFE;
 893         wr32(hw, TXGBE_VLANCTL, vlnctrl);
 894
 895         /* write whatever is in local vfta copy */
 896         for (i = 0; i < TXGBE_VFTA_SIZE; i++)
 897                 wr32(hw, TXGBE_VLANTBL(i), shadow_vfta->vfta[i]);
 898 }
 899
 900 void
 901 txgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
 902 {
 903         struct txgbe_hwstrip *hwstrip = TXGBE_DEV_HWSTRIP(dev);
 904         struct txgbe_rx_queue *rxq;
 905
 906         if (queue >= TXGBE_MAX_RX_QUEUE_NUM)
 907                 return;
 908
 909         if (on)
 910                 TXGBE_SET_HWSTRIP(hwstrip, queue);
 911         else
 912                 TXGBE_CLEAR_HWSTRIP(hwstrip, queue);
 913
 914         if (queue >= dev->data->nb_rx_queues)
 915                 return;
 916
 917         rxq = dev->data->rx_queues[queue];
 918
 919         if (on) {
 920                 rxq->vlan_flags = PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
 921                 rxq->offloads |= DEV_RX_OFFLOAD_VLAN_STRIP;
 922         } else {
 923                 rxq->vlan_flags = PKT_RX_VLAN;
 924                 rxq->offloads &= ~DEV_RX_OFFLOAD_VLAN_STRIP;
 925         }
 926 }
 927
 928 static void
 929 txgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
 930 {
 931         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
 932         uint32_t ctrl;
 933
 934         PMD_INIT_FUNC_TRACE();
 935
 936         ctrl = rd32(hw, TXGBE_RXCFG(queue));
 937         ctrl &= ~TXGBE_RXCFG_VLAN;
 938         wr32(hw, TXGBE_RXCFG(queue), ctrl);
 939
 940         /* record those setting for HW strip per queue */
 941         txgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
 942 }
 943
 944 static void
 945 txgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
 946 {
 947         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
 948         uint32_t ctrl;
 949
 950         PMD_INIT_FUNC_TRACE();
 951
 952         ctrl = rd32(hw, TXGBE_RXCFG(queue));
 953         ctrl |= TXGBE_RXCFG_VLAN;
 954         wr32(hw, TXGBE_RXCFG(queue), ctrl);
 955
 956         /* record those setting for HW strip per queue */
 957         txgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
 958 }
 959
 960 static void
 961 txgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
 962 {
 963         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
 964         uint32_t ctrl;
 965
 966         PMD_INIT_FUNC_TRACE();
 967
 968         ctrl = rd32(hw, TXGBE_PORTCTL);
 969         ctrl &= ~TXGBE_PORTCTL_VLANEXT;
 970         ctrl &= ~TXGBE_PORTCTL_QINQ;
 971         wr32(hw, TXGBE_PORTCTL, ctrl);
 972 }
 973
 974 static void
 975 txgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
 976 {
 977         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
 978         struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
 979         struct rte_eth_txmode *txmode = &dev->data->dev_conf.txmode;
 980         uint32_t ctrl;
 981
 982         PMD_INIT_FUNC_TRACE();
 983
 984         ctrl  = rd32(hw, TXGBE_PORTCTL);
 985         ctrl |= TXGBE_PORTCTL_VLANEXT;
 986         if (rxmode->offloads & DEV_RX_OFFLOAD_QINQ_STRIP ||
 987             txmode->offloads & DEV_TX_OFFLOAD_QINQ_INSERT)
 988                 ctrl |= TXGBE_PORTCTL_QINQ;
 989         wr32(hw, TXGBE_PORTCTL, ctrl);
 990 }
 991
 992 void
 993 txgbe_vlan_hw_strip_config(struct rte_eth_dev *dev)
 994 {
 995         struct txgbe_rx_queue *rxq;
 996         uint16_t i;
 997
 998         PMD_INIT_FUNC_TRACE();
 999
1000         for (i = 0; i < dev->data->nb_rx_queues; i++) {
1001                 rxq = dev->data->rx_queues[i];
1002
1003                 if (rxq->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1004                         txgbe_vlan_strip_queue_set(dev, i, 1);
1005                 else
1006                         txgbe_vlan_strip_queue_set(dev, i, 0);
1007         }
1008 }
1009
1010 void
1011 txgbe_config_vlan_strip_on_all_queues(struct rte_eth_dev *dev, int mask)
1012 {
1013         uint16_t i;
1014         struct rte_eth_rxmode *rxmode;
1015         struct txgbe_rx_queue *rxq;
1016
1017         if (mask & ETH_VLAN_STRIP_MASK) {
1018                 rxmode = &dev->data->dev_conf.rxmode;
1019                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1020                         for (i = 0; i < dev->data->nb_rx_queues; i++) {
1021                                 rxq = dev->data->rx_queues[i];
1022                                 rxq->offloads |= DEV_RX_OFFLOAD_VLAN_STRIP;
1023                         }
1024                 else
1025                         for (i = 0; i < dev->data->nb_rx_queues; i++) {
1026                                 rxq = dev->data->rx_queues[i];
1027                                 rxq->offloads &= ~DEV_RX_OFFLOAD_VLAN_STRIP;
1028                         }
1029         }
1030 }
1031
1032 static int
1033 txgbe_vlan_offload_config(struct rte_eth_dev *dev, int mask)
1034 {
1035         struct rte_eth_rxmode *rxmode;
1036         rxmode = &dev->data->dev_conf.rxmode;
1037
1038         if (mask & ETH_VLAN_STRIP_MASK)
1039                 txgbe_vlan_hw_strip_config(dev);
1040
1041         if (mask & ETH_VLAN_FILTER_MASK) {
1042                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
1043                         txgbe_vlan_hw_filter_enable(dev);
1044                 else
1045                         txgbe_vlan_hw_filter_disable(dev);
1046         }
1047
1048         if (mask & ETH_VLAN_EXTEND_MASK) {
1049                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
1050                         txgbe_vlan_hw_extend_enable(dev);
1051                 else
1052                         txgbe_vlan_hw_extend_disable(dev);
1053         }
1054
1055         return 0;
1056 }
1057
1058 static int
1059 txgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1060 {
1061         txgbe_config_vlan_strip_on_all_queues(dev, mask);
1062
1063         txgbe_vlan_offload_config(dev, mask);
1064
1065         return 0;
1066 }
1067
1068 static void
1069 txgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1070 {
1071         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
1072         /* VLNCTL: enable vlan filtering and allow all vlan tags through */
1073         uint32_t vlanctrl = rd32(hw, TXGBE_VLANCTL);
1074
1075         vlanctrl |= TXGBE_VLANCTL_VFE; /* enable vlan filters */
1076         wr32(hw, TXGBE_VLANCTL, vlanctrl);
1077 }
1078
1079 static int
1080 txgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q)
1081 {
1082         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1083
1084         switch (nb_rx_q) {
1085         case 1:
1086         case 2:
1087                 RTE_ETH_DEV_SRIOV(dev).active = ETH_64_POOLS;
1088                 break;
1089         case 4:
1090                 RTE_ETH_DEV_SRIOV(dev).active = ETH_32_POOLS;
1091                 break;
1092         default:
1093                 return -EINVAL;
1094         }
1095
1096         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool =
1097                 TXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
1098         RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx =
1099                 pci_dev->max_vfs * RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
1100         return 0;
1101 }
1102
1103 static int
1104 txgbe_check_mq_mode(struct rte_eth_dev *dev)
1105 {
1106         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
1107         uint16_t nb_rx_q = dev->data->nb_rx_queues;
1108         uint16_t nb_tx_q = dev->data->nb_tx_queues;
1109
1110         if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
1111                 /* check multi-queue mode */
1112                 switch (dev_conf->rxmode.mq_mode) {
1113                 case ETH_MQ_RX_VMDQ_DCB:
1114                         PMD_INIT_LOG(INFO, "ETH_MQ_RX_VMDQ_DCB mode supported in SRIOV");
1115                         break;
1116                 case ETH_MQ_RX_VMDQ_DCB_RSS:
1117                         /* DCB/RSS VMDQ in SRIOV mode, not implement yet */
1118                         PMD_INIT_LOG(ERR, "SRIOV active,"
1119                                         " unsupported mq_mode rx %d.",
1120                                         dev_conf->rxmode.mq_mode);
1121                         return -EINVAL;
1122                 case ETH_MQ_RX_RSS:
1123                 case ETH_MQ_RX_VMDQ_RSS:
1124                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_RSS;
1125                         if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)
1126                                 if (txgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) {
1127                                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1128                                                 " invalid queue number"
1129                                                 " for VMDQ RSS, allowed"
1130                                                 " value are 1, 2 or 4.");
1131                                         return -EINVAL;
1132                                 }
1133                         break;
1134                 case ETH_MQ_RX_VMDQ_ONLY:
1135                 case ETH_MQ_RX_NONE:
1136                         /* if nothing mq mode configure, use default scheme */
1137                         dev->data->dev_conf.rxmode.mq_mode =
1138                                 ETH_MQ_RX_VMDQ_ONLY;
1139                         break;
1140                 default: /* ETH_MQ_RX_DCB, ETH_MQ_RX_DCB_RSS or ETH_MQ_TX_DCB*/
1141                         /* SRIOV only works in VMDq enable mode */
1142                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1143                                         " wrong mq_mode rx %d.",
1144                                         dev_conf->rxmode.mq_mode);
1145                         return -EINVAL;
1146                 }
1147
1148                 switch (dev_conf->txmode.mq_mode) {
1149                 case ETH_MQ_TX_VMDQ_DCB:
1150                         PMD_INIT_LOG(INFO, "ETH_MQ_TX_VMDQ_DCB mode supported in SRIOV");
1151                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_DCB;
1152                         break;
1153                 default: /* ETH_MQ_TX_VMDQ_ONLY or ETH_MQ_TX_NONE */
1154                         dev->data->dev_conf.txmode.mq_mode =
1155                                 ETH_MQ_TX_VMDQ_ONLY;
1156                         break;
1157                 }
1158
1159                 /* check valid queue number */
1160                 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) ||
1161                     (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) {
1162                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1163                                         " nb_rx_q=%d nb_tx_q=%d queue number"
1164                                         " must be less than or equal to %d.",
1165                                         nb_rx_q, nb_tx_q,
1166                                         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool);
1167                         return -EINVAL;
1168                 }
1169         } else {
1170                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
1171                         PMD_INIT_LOG(ERR, "VMDQ+DCB+RSS mq_mode is"
1172                                           " not supported.");
1173                         return -EINVAL;
1174                 }
1175                 /* check configuration for vmdb+dcb mode */
1176                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB) {
1177                         const struct rte_eth_vmdq_dcb_conf *conf;
1178
1179                         if (nb_rx_q != TXGBE_VMDQ_DCB_NB_QUEUES) {
1180                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.",
1181                                                 TXGBE_VMDQ_DCB_NB_QUEUES);
1182                                 return -EINVAL;
1183                         }
1184                         conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf;
1185                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
1186                                conf->nb_queue_pools == ETH_32_POOLS)) {
1187                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
1188                                                 " nb_queue_pools must be %d or %d.",
1189                                                 ETH_16_POOLS, ETH_32_POOLS);
1190                                 return -EINVAL;
1191                         }
1192                 }
1193                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) {
1194                         const struct rte_eth_vmdq_dcb_tx_conf *conf;
1195
1196                         if (nb_tx_q != TXGBE_VMDQ_DCB_NB_QUEUES) {
1197                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d",
1198                                                  TXGBE_VMDQ_DCB_NB_QUEUES);
1199                                 return -EINVAL;
1200                         }
1201                         conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf;
1202                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
1203                                conf->nb_queue_pools == ETH_32_POOLS)) {
1204                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
1205                                                 " nb_queue_pools != %d and"
1206                                                 " nb_queue_pools != %d.",
1207                                                 ETH_16_POOLS, ETH_32_POOLS);
1208                                 return -EINVAL;
1209                         }
1210                 }
1211
1212                 /* For DCB mode check our configuration before we go further */
1213                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_DCB) {
1214                         const struct rte_eth_dcb_rx_conf *conf;
1215
1216                         conf = &dev_conf->rx_adv_conf.dcb_rx_conf;
1217                         if (!(conf->nb_tcs == ETH_4_TCS ||
1218                                conf->nb_tcs == ETH_8_TCS)) {
1219                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
1220                                                 " and nb_tcs != %d.",
1221                                                 ETH_4_TCS, ETH_8_TCS);
1222                                 return -EINVAL;
1223                         }
1224                 }
1225
1226                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_DCB) {
1227                         const struct rte_eth_dcb_tx_conf *conf;
1228
1229                         conf = &dev_conf->tx_adv_conf.dcb_tx_conf;
1230                         if (!(conf->nb_tcs == ETH_4_TCS ||
1231                                conf->nb_tcs == ETH_8_TCS)) {
1232                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
1233                                                 " and nb_tcs != %d.",
1234                                                 ETH_4_TCS, ETH_8_TCS);
1235                                 return -EINVAL;
1236                         }
1237                 }
1238         }
1239         return 0;
1240 }
1241
1242 static int
1243 txgbe_dev_configure(struct rte_eth_dev *dev)
1244 {
1245         struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);
1246         struct txgbe_adapter *adapter = TXGBE_DEV_ADAPTER(dev);
1247         int ret;
1248
1249         PMD_INIT_FUNC_TRACE();
1250
1251         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
1252                 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
1253
1254         /* multiple queue mode checking */
1255         ret  = txgbe_check_mq_mode(dev);
1256         if (ret != 0) {
1257                 PMD_DRV_LOG(ERR, "txgbe_check_mq_mode fails with %d.",
1258                             ret);
1259                 return ret;
1260         }
1261
1262         /* set flag to update link status after init */
1263         intr->flags |= TXGBE_FLAG_NEED_LINK_UPDATE;
1264
1265         /*
1266          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
1267          * allocation Rx preconditions we will reset it.
1268          */
1269         adapter->rx_bulk_alloc_allowed = true;
1270
1271         return 0;
1272 }
1273
1274 static void
1275 txgbe_dev_phy_intr_setup(struct rte_eth_dev *dev)
1276 {
1277         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
1278         struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);
1279         uint32_t gpie;
1280
1281         gpie = rd32(hw, TXGBE_GPIOINTEN);
1282         gpie |= TXGBE_GPIOBIT_6;
1283         wr32(hw, TXGBE_GPIOINTEN, gpie);
1284         intr->mask_misc |= TXGBE_ICRMISC_GPIO;
1285 }
1286
1287 int
1288 txgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
1289                         uint16_t tx_rate, uint64_t q_msk)
1290 {
1291         struct txgbe_hw *hw;
1292         struct txgbe_vf_info *vfinfo;
1293         struct rte_eth_link link;
1294         uint8_t  nb_q_per_pool;
1295         uint32_t queue_stride;
1296         uint32_t queue_idx, idx = 0, vf_idx;
1297         uint32_t queue_end;
1298         uint16_t total_rate = 0;
1299         struct rte_pci_device *pci_dev;
1300         int ret;
1301
1302         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1303         ret = rte_eth_link_get_nowait(dev->data->port_id, &link);
1304         if (ret < 0)
1305                 return ret;
1306
1307         if (vf >= pci_dev->max_vfs)
1308                 return -EINVAL;
1309
1310         if (tx_rate > link.link_speed)
1311                 return -EINVAL;
1312
1313         if (q_msk == 0)
1314                 return 0;
1315
1316         hw = TXGBE_DEV_HW(dev);
1317         vfinfo = *(TXGBE_DEV_VFDATA(dev));
1318         nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
1319         queue_stride = TXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
1320         queue_idx = vf * queue_stride;
1321         queue_end = queue_idx + nb_q_per_pool - 1;
1322         if (queue_end >= hw->mac.max_tx_queues)
1323                 return -EINVAL;
1324
1325         if (vfinfo) {
1326                 for (vf_idx = 0; vf_idx < pci_dev->max_vfs; vf_idx++) {
1327                         if (vf_idx == vf)
1328                                 continue;
1329                         for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
1330                                 idx++)
1331                                 total_rate += vfinfo[vf_idx].tx_rate[idx];
1332                 }
1333         } else {
1334                 return -EINVAL;
1335         }
1336
1337         /* Store tx_rate for this vf. */
1338         for (idx = 0; idx < nb_q_per_pool; idx++) {
1339                 if (((uint64_t)0x1 << idx) & q_msk) {
1340                         if (vfinfo[vf].tx_rate[idx] != tx_rate)
1341                                 vfinfo[vf].tx_rate[idx] = tx_rate;
1342                         total_rate += tx_rate;
1343                 }
1344         }
1345
1346         if (total_rate > dev->data->dev_link.link_speed) {
1347                 /* Reset stored TX rate of the VF if it causes exceed
1348                  * link speed.
1349                  */
1350                 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
1351                 return -EINVAL;
1352         }
1353
1354         /* Set ARBTXRATE of each queue/pool for vf X  */
1355         for (; queue_idx <= queue_end; queue_idx++) {
1356                 if (0x1 & q_msk)
1357                         txgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
1358                 q_msk = q_msk >> 1;
1359         }
1360
1361         return 0;
1362 }
1363
1364 /*
1365  * Configure device link speed and setup link.
1366  * It returns 0 on success.
1367  */
1368 static int
1369 txgbe_dev_start(struct rte_eth_dev *dev)
1370 {
1371         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
1372         struct txgbe_hw_stats *hw_stats = TXGBE_DEV_STATS(dev);
1373         struct txgbe_vf_info *vfinfo = *TXGBE_DEV_VFDATA(dev);
1374         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1375         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1376         uint32_t intr_vector = 0;
1377         int err;
1378         bool link_up = false, negotiate = 0;
1379         uint32_t speed = 0;
1380         uint32_t allowed_speeds = 0;
1381         int mask = 0;
1382         int status;
1383         uint16_t vf, idx;
1384         uint32_t *link_speeds;
1385
1386         PMD_INIT_FUNC_TRACE();
1387
1388         /* TXGBE devices don't support:
1389          *    - half duplex (checked afterwards for valid speeds)
1390          *    - fixed speed: TODO implement
1391          */
1392         if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
1393                 PMD_INIT_LOG(ERR,
1394                 "Invalid link_speeds for port %u, fix speed not supported",
1395                                 dev->data->port_id);
1396                 return -EINVAL;
1397         }
1398
1399         /* Stop the link setup handler before resetting the HW. */
1400         rte_eal_alarm_cancel(txgbe_dev_setup_link_alarm_handler, dev);
1401
1402         /* disable uio/vfio intr/eventfd mapping */
1403         rte_intr_disable(intr_handle);
1404
1405         /* stop adapter */
1406         hw->adapter_stopped = 0;
1407         txgbe_stop_hw(hw);
1408
1409         /* reinitialize adapter
1410          * this calls reset and start
1411          */
1412         hw->nb_rx_queues = dev->data->nb_rx_queues;
1413         hw->nb_tx_queues = dev->data->nb_tx_queues;
1414         status = txgbe_pf_reset_hw(hw);
1415         if (status != 0)
1416                 return -1;
1417         hw->mac.start_hw(hw);
1418         hw->mac.get_link_status = true;
1419
1420         /* configure PF module if SRIOV enabled */
1421         txgbe_pf_host_configure(dev);
1422
1423         txgbe_dev_phy_intr_setup(dev);
1424
1425         /* check and configure queue intr-vector mapping */
1426         if ((rte_intr_cap_multiple(intr_handle) ||
1427              !RTE_ETH_DEV_SRIOV(dev).active) &&
1428             dev->data->dev_conf.intr_conf.rxq != 0) {
1429                 intr_vector = dev->data->nb_rx_queues;
1430                 if (rte_intr_efd_enable(intr_handle, intr_vector))
1431                         return -1;
1432         }
1433
1434         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1435                 intr_handle->intr_vec =
1436                         rte_zmalloc("intr_vec",
1437                                     dev->data->nb_rx_queues * sizeof(int), 0);
1438                 if (intr_handle->intr_vec == NULL) {
1439                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
1440                                      " intr_vec", dev->data->nb_rx_queues);
1441                         return -ENOMEM;
1442                 }
1443         }
1444
1445         /* confiugre msix for sleep until rx interrupt */
1446         txgbe_configure_msix(dev);
1447
1448         /* initialize transmission unit */
1449         txgbe_dev_tx_init(dev);
1450
1451         /* This can fail when allocating mbufs for descriptor rings */
1452         err = txgbe_dev_rx_init(dev);
1453         if (err) {
1454                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
1455                 goto error;
1456         }
1457
1458         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
1459                 ETH_VLAN_EXTEND_MASK;
1460         err = txgbe_vlan_offload_config(dev, mask);
1461         if (err) {
1462                 PMD_INIT_LOG(ERR, "Unable to set VLAN offload");
1463                 goto error;
1464         }
1465
1466         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1467                 /* Enable vlan filtering for VMDq */
1468                 txgbe_vmdq_vlan_hw_filter_enable(dev);
1469         }
1470
1471         /* Configure DCB hw */
1472         txgbe_configure_pb(dev);
1473         txgbe_configure_port(dev);
1474         txgbe_configure_dcb(dev);
1475
1476         /* Restore vf rate limit */
1477         if (vfinfo != NULL) {
1478                 for (vf = 0; vf < pci_dev->max_vfs; vf++)
1479                         for (idx = 0; idx < TXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
1480                                 if (vfinfo[vf].tx_rate[idx] != 0)
1481                                         txgbe_set_vf_rate_limit(dev, vf,
1482                                                 vfinfo[vf].tx_rate[idx],
1483                                                 1 << idx);
1484         }
1485
1486         err = txgbe_dev_rxtx_start(dev);
1487         if (err < 0) {
1488                 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
1489                 goto error;
1490         }
1491
1492         /* Skip link setup if loopback mode is enabled. */
1493         if (hw->mac.type == txgbe_mac_raptor &&
1494             dev->data->dev_conf.lpbk_mode)
1495                 goto skip_link_setup;
1496
1497         if (txgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
1498                 err = hw->mac.setup_sfp(hw);
1499                 if (err)
1500                         goto error;
1501         }
1502
1503         if (hw->phy.media_type == txgbe_media_type_copper) {
1504                 /* Turn on the copper */
1505                 hw->phy.set_phy_power(hw, true);
1506         } else {
1507                 /* Turn on the laser */
1508                 hw->mac.enable_tx_laser(hw);
1509         }
1510
1511         err = hw->mac.check_link(hw, &speed, &link_up, 0);
1512         if (err)
1513                 goto error;
1514         dev->data->dev_link.link_status = link_up;
1515
1516         err = hw->mac.get_link_capabilities(hw, &speed, &negotiate);
1517         if (err)
1518                 goto error;
1519
1520         allowed_speeds = ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
1521                         ETH_LINK_SPEED_10G;
1522
1523         link_speeds = &dev->data->dev_conf.link_speeds;
1524         if (*link_speeds & ~allowed_speeds) {
1525                 PMD_INIT_LOG(ERR, "Invalid link setting");
1526                 goto error;
1527         }
1528
1529         speed = 0x0;
1530         if (*link_speeds == ETH_LINK_SPEED_AUTONEG) {
1531                 speed = (TXGBE_LINK_SPEED_100M_FULL |
1532                          TXGBE_LINK_SPEED_1GB_FULL |
1533                          TXGBE_LINK_SPEED_10GB_FULL);
1534         } else {
1535                 if (*link_speeds & ETH_LINK_SPEED_10G)
1536                         speed |= TXGBE_LINK_SPEED_10GB_FULL;
1537                 if (*link_speeds & ETH_LINK_SPEED_5G)
1538                         speed |= TXGBE_LINK_SPEED_5GB_FULL;
1539                 if (*link_speeds & ETH_LINK_SPEED_2_5G)
1540                         speed |= TXGBE_LINK_SPEED_2_5GB_FULL;
1541                 if (*link_speeds & ETH_LINK_SPEED_1G)
1542                         speed |= TXGBE_LINK_SPEED_1GB_FULL;
1543                 if (*link_speeds & ETH_LINK_SPEED_100M)
1544                         speed |= TXGBE_LINK_SPEED_100M_FULL;
1545         }
1546
1547         err = hw->mac.setup_link(hw, speed, link_up);
1548         if (err)
1549                 goto error;
1550
1551 skip_link_setup:
1552
1553         if (rte_intr_allow_others(intr_handle)) {
1554                 /* check if lsc interrupt is enabled */
1555                 if (dev->data->dev_conf.intr_conf.lsc != 0)
1556                         txgbe_dev_lsc_interrupt_setup(dev, TRUE);
1557                 else
1558                         txgbe_dev_lsc_interrupt_setup(dev, FALSE);
1559                 txgbe_dev_macsec_interrupt_setup(dev);
1560                 txgbe_set_ivar_map(hw, -1, 1, TXGBE_MISC_VEC_ID);
1561         } else {
1562                 rte_intr_callback_unregister(intr_handle,
1563                                              txgbe_dev_interrupt_handler, dev);
1564                 if (dev->data->dev_conf.intr_conf.lsc != 0)
1565                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
1566                                      " no intr multiplex");
1567         }
1568
1569         /* check if rxq interrupt is enabled */
1570         if (dev->data->dev_conf.intr_conf.rxq != 0 &&
1571             rte_intr_dp_is_en(intr_handle))
1572                 txgbe_dev_rxq_interrupt_setup(dev);
1573
1574         /* enable uio/vfio intr/eventfd mapping */
1575         rte_intr_enable(intr_handle);
1576
1577         /* resume enabled intr since hw reset */
1578         txgbe_enable_intr(dev);
1579
1580         /*
1581          * Update link status right before return, because it may
1582          * start link configuration process in a separate thread.
1583          */
1584         txgbe_dev_link_update(dev, 0);
1585
1586         wr32m(hw, TXGBE_LEDCTL, 0xFFFFFFFF, TXGBE_LEDCTL_ORD_MASK);
1587
1588         txgbe_read_stats_registers(hw, hw_stats);
1589         hw->offset_loaded = 1;
1590
1591         return 0;
1592
1593 error:
1594         PMD_INIT_LOG(ERR, "failure in dev start: %d", err);
1595         txgbe_dev_clear_queues(dev);
1596         return -EIO;
1597 }
1598
1599 /*
1600  * Stop device: disable rx and tx functions to allow for reconfiguring.
1601  */
1602 static int
1603 txgbe_dev_stop(struct rte_eth_dev *dev)
1604 {
1605         struct rte_eth_link link;
1606         struct txgbe_adapter *adapter = TXGBE_DEV_ADAPTER(dev);
1607         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
1608         struct txgbe_vf_info *vfinfo = *TXGBE_DEV_VFDATA(dev);
1609         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1610         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1611         int vf;
1612
1613         if (hw->adapter_stopped)
1614                 return 0;
1615
1616         PMD_INIT_FUNC_TRACE();
1617
1618         rte_eal_alarm_cancel(txgbe_dev_setup_link_alarm_handler, dev);
1619
1620         /* disable interrupts */
1621         txgbe_disable_intr(hw);
1622
1623         /* reset the NIC */
1624         txgbe_pf_reset_hw(hw);
1625         hw->adapter_stopped = 0;
1626
1627         /* stop adapter */
1628         txgbe_stop_hw(hw);
1629
1630         for (vf = 0; vfinfo != NULL && vf < pci_dev->max_vfs; vf++)
1631                 vfinfo[vf].clear_to_send = false;
1632
1633         if (hw->phy.media_type == txgbe_media_type_copper) {
1634                 /* Turn off the copper */
1635                 hw->phy.set_phy_power(hw, false);
1636         } else {
1637                 /* Turn off the laser */
1638                 hw->mac.disable_tx_laser(hw);
1639         }
1640
1641         txgbe_dev_clear_queues(dev);
1642
1643         /* Clear stored conf */
1644         dev->data->scattered_rx = 0;
1645         dev->data->lro = 0;
1646
1647         /* Clear recorded link status */
1648         memset(&link, 0, sizeof(link));
1649         rte_eth_linkstatus_set(dev, &link);
1650
1651         if (!rte_intr_allow_others(intr_handle))
1652                 /* resume to the default handler */
1653                 rte_intr_callback_register(intr_handle,
1654                                            txgbe_dev_interrupt_handler,
1655                                            (void *)dev);
1656
1657         /* Clean datapath event and queue/vec mapping */
1658         rte_intr_efd_disable(intr_handle);
1659         if (intr_handle->intr_vec != NULL) {
1660                 rte_free(intr_handle->intr_vec);
1661                 intr_handle->intr_vec = NULL;
1662         }
1663
1664         adapter->rss_reta_updated = 0;
1665         wr32m(hw, TXGBE_LEDCTL, 0xFFFFFFFF, TXGBE_LEDCTL_SEL_MASK);
1666
1667         hw->adapter_stopped = true;
1668         dev->data->dev_started = 0;
1669
1670         return 0;
1671 }
1672
1673 /*
1674  * Set device link up: enable tx.
1675  */
1676 static int
1677 txgbe_dev_set_link_up(struct rte_eth_dev *dev)
1678 {
1679         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
1680
1681         if (hw->phy.media_type == txgbe_media_type_copper) {
1682                 /* Turn on the copper */
1683                 hw->phy.set_phy_power(hw, true);
1684         } else {
1685                 /* Turn on the laser */
1686                 hw->mac.enable_tx_laser(hw);
1687                 txgbe_dev_link_update(dev, 0);
1688         }
1689
1690         return 0;
1691 }
1692
1693 /*
1694  * Set device link down: disable tx.
1695  */
1696 static int
1697 txgbe_dev_set_link_down(struct rte_eth_dev *dev)
1698 {
1699         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
1700
1701         if (hw->phy.media_type == txgbe_media_type_copper) {
1702                 /* Turn off the copper */
1703                 hw->phy.set_phy_power(hw, false);
1704         } else {
1705                 /* Turn off the laser */
1706                 hw->mac.disable_tx_laser(hw);
1707                 txgbe_dev_link_update(dev, 0);
1708         }
1709
1710         return 0;
1711 }
1712
1713 /*
1714  * Reset and stop device.
1715  */
1716 static int
1717 txgbe_dev_close(struct rte_eth_dev *dev)
1718 {
1719         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
1720         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1721         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1722         int retries = 0;
1723         int ret;
1724
1725         PMD_INIT_FUNC_TRACE();
1726
1727         txgbe_pf_reset_hw(hw);
1728
1729         ret = txgbe_dev_stop(dev);
1730
1731         txgbe_dev_free_queues(dev);
1732
1733         /* reprogram the RAR[0] in case user changed it. */
1734         txgbe_set_rar(hw, 0, hw->mac.addr, 0, true);
1735
1736         /* Unlock any pending hardware semaphore */
1737         txgbe_swfw_lock_reset(hw);
1738
1739         /* disable uio intr before callback unregister */
1740         rte_intr_disable(intr_handle);
1741
1742         do {
1743                 ret = rte_intr_callback_unregister(intr_handle,
1744                                 txgbe_dev_interrupt_handler, dev);
1745                 if (ret >= 0 || ret == -ENOENT) {
1746                         break;
1747                 } else if (ret != -EAGAIN) {
1748                         PMD_INIT_LOG(ERR,
1749                                 "intr callback unregister failed: %d",
1750                                 ret);
1751                 }
1752                 rte_delay_ms(100);
1753         } while (retries++ < (10 + TXGBE_LINK_UP_TIME));
1754
1755         /* cancel the delay handler before remove dev */
1756         rte_eal_alarm_cancel(txgbe_dev_interrupt_delayed_handler, dev);
1757
1758         /* uninitialize PF if max_vfs not zero */
1759         txgbe_pf_host_uninit(dev);
1760
1761         rte_free(dev->data->mac_addrs);
1762         dev->data->mac_addrs = NULL;
1763
1764         rte_free(dev->data->hash_mac_addrs);
1765         dev->data->hash_mac_addrs = NULL;
1766
1767         return ret;
1768 }
1769
1770 /*
1771  * Reset PF device.
1772  */
1773 static int
1774 txgbe_dev_reset(struct rte_eth_dev *dev)
1775 {
1776         int ret;
1777
1778         /* When a DPDK PMD PF begin to reset PF port, it should notify all
1779          * its VF to make them align with it. The detailed notification
1780          * mechanism is PMD specific. As to txgbe PF, it is rather complex.
1781          * To avoid unexpected behavior in VF, currently reset of PF with
1782          * SR-IOV activation is not supported. It might be supported later.
1783          */
1784         if (dev->data->sriov.active)
1785                 return -ENOTSUP;
1786
1787         ret = eth_txgbe_dev_uninit(dev);
1788         if (ret)
1789                 return ret;
1790
1791         ret = eth_txgbe_dev_init(dev, NULL);
1792
1793         return ret;
1794 }
1795
1796 #define UPDATE_QP_COUNTER_32bit(reg, last_counter, counter)     \
1797         {                                                       \
1798                 uint32_t current_counter = rd32(hw, reg);       \
1799                 if (current_counter < last_counter)             \
1800                         current_counter += 0x100000000LL;       \
1801                 if (!hw->offset_loaded)                         \
1802                         last_counter = current_counter;         \
1803                 counter = current_counter - last_counter;       \
1804                 counter &= 0xFFFFFFFFLL;                        \
1805         }
1806
1807 #define UPDATE_QP_COUNTER_36bit(reg_lsb, reg_msb, last_counter, counter) \
1808         {                                                                \
1809                 uint64_t current_counter_lsb = rd32(hw, reg_lsb);        \
1810                 uint64_t current_counter_msb = rd32(hw, reg_msb);        \
1811                 uint64_t current_counter = (current_counter_msb << 32) | \
1812                         current_counter_lsb;                             \
1813                 if (current_counter < last_counter)                      \
1814                         current_counter += 0x1000000000LL;               \
1815                 if (!hw->offset_loaded)                                  \
1816                         last_counter = current_counter;                  \
1817                 counter = current_counter - last_counter;                \
1818                 counter &= 0xFFFFFFFFFLL;                                \
1819         }
1820
1821 void
1822 txgbe_read_stats_registers(struct txgbe_hw *hw,
1823                            struct txgbe_hw_stats *hw_stats)
1824 {
1825         unsigned int i;
1826
1827         /* QP Stats */
1828         for (i = 0; i < hw->nb_rx_queues; i++) {
1829                 UPDATE_QP_COUNTER_32bit(TXGBE_QPRXPKT(i),
1830                         hw->qp_last[i].rx_qp_packets,
1831                         hw_stats->qp[i].rx_qp_packets);
1832                 UPDATE_QP_COUNTER_36bit(TXGBE_QPRXOCTL(i), TXGBE_QPRXOCTH(i),
1833                         hw->qp_last[i].rx_qp_bytes,
1834                         hw_stats->qp[i].rx_qp_bytes);
1835                 UPDATE_QP_COUNTER_32bit(TXGBE_QPRXMPKT(i),
1836                         hw->qp_last[i].rx_qp_mc_packets,
1837                         hw_stats->qp[i].rx_qp_mc_packets);
1838         }
1839
1840         for (i = 0; i < hw->nb_tx_queues; i++) {
1841                 UPDATE_QP_COUNTER_32bit(TXGBE_QPTXPKT(i),
1842                         hw->qp_last[i].tx_qp_packets,
1843                         hw_stats->qp[i].tx_qp_packets);
1844                 UPDATE_QP_COUNTER_36bit(TXGBE_QPTXOCTL(i), TXGBE_QPTXOCTH(i),
1845                         hw->qp_last[i].tx_qp_bytes,
1846                         hw_stats->qp[i].tx_qp_bytes);
1847         }
1848         /* PB Stats */
1849         for (i = 0; i < TXGBE_MAX_UP; i++) {
1850                 hw_stats->up[i].rx_up_xon_packets +=
1851                                 rd32(hw, TXGBE_PBRXUPXON(i));
1852                 hw_stats->up[i].rx_up_xoff_packets +=
1853                                 rd32(hw, TXGBE_PBRXUPXOFF(i));
1854                 hw_stats->up[i].tx_up_xon_packets +=
1855                                 rd32(hw, TXGBE_PBTXUPXON(i));
1856                 hw_stats->up[i].tx_up_xoff_packets +=
1857                                 rd32(hw, TXGBE_PBTXUPXOFF(i));
1858                 hw_stats->up[i].tx_up_xon2off_packets +=
1859                                 rd32(hw, TXGBE_PBTXUPOFF(i));
1860                 hw_stats->up[i].rx_up_dropped +=
1861                                 rd32(hw, TXGBE_PBRXMISS(i));
1862         }
1863         hw_stats->rx_xon_packets += rd32(hw, TXGBE_PBRXLNKXON);
1864         hw_stats->rx_xoff_packets += rd32(hw, TXGBE_PBRXLNKXOFF);
1865         hw_stats->tx_xon_packets += rd32(hw, TXGBE_PBTXLNKXON);
1866         hw_stats->tx_xoff_packets += rd32(hw, TXGBE_PBTXLNKXOFF);
1867
1868         /* DMA Stats */
1869         hw_stats->rx_packets += rd32(hw, TXGBE_DMARXPKT);
1870         hw_stats->tx_packets += rd32(hw, TXGBE_DMATXPKT);
1871
1872         hw_stats->rx_bytes += rd64(hw, TXGBE_DMARXOCTL);
1873         hw_stats->tx_bytes += rd64(hw, TXGBE_DMATXOCTL);
1874         hw_stats->rx_drop_packets += rd32(hw, TXGBE_PBRXDROP);
1875
1876         /* MAC Stats */
1877         hw_stats->rx_crc_errors += rd64(hw, TXGBE_MACRXERRCRCL);
1878         hw_stats->rx_multicast_packets += rd64(hw, TXGBE_MACRXMPKTL);
1879         hw_stats->tx_multicast_packets += rd64(hw, TXGBE_MACTXMPKTL);
1880
1881         hw_stats->rx_total_packets += rd64(hw, TXGBE_MACRXPKTL);
1882         hw_stats->tx_total_packets += rd64(hw, TXGBE_MACTXPKTL);
1883         hw_stats->rx_total_bytes += rd64(hw, TXGBE_MACRXGBOCTL);
1884
1885         hw_stats->rx_broadcast_packets += rd64(hw, TXGBE_MACRXOCTL);
1886         hw_stats->tx_broadcast_packets += rd32(hw, TXGBE_MACTXOCTL);
1887
1888         hw_stats->rx_size_64_packets += rd64(hw, TXGBE_MACRX1TO64L);
1889         hw_stats->rx_size_65_to_127_packets += rd64(hw, TXGBE_MACRX65TO127L);
1890         hw_stats->rx_size_128_to_255_packets += rd64(hw, TXGBE_MACRX128TO255L);
1891         hw_stats->rx_size_256_to_511_packets += rd64(hw, TXGBE_MACRX256TO511L);
1892         hw_stats->rx_size_512_to_1023_packets +=
1893                         rd64(hw, TXGBE_MACRX512TO1023L);
1894         hw_stats->rx_size_1024_to_max_packets +=
1895                         rd64(hw, TXGBE_MACRX1024TOMAXL);
1896         hw_stats->tx_size_64_packets += rd64(hw, TXGBE_MACTX1TO64L);
1897         hw_stats->tx_size_65_to_127_packets += rd64(hw, TXGBE_MACTX65TO127L);
1898         hw_stats->tx_size_128_to_255_packets += rd64(hw, TXGBE_MACTX128TO255L);
1899         hw_stats->tx_size_256_to_511_packets += rd64(hw, TXGBE_MACTX256TO511L);
1900         hw_stats->tx_size_512_to_1023_packets +=
1901                         rd64(hw, TXGBE_MACTX512TO1023L);
1902         hw_stats->tx_size_1024_to_max_packets +=
1903                         rd64(hw, TXGBE_MACTX1024TOMAXL);
1904
1905         hw_stats->rx_undersize_errors += rd64(hw, TXGBE_MACRXERRLENL);
1906         hw_stats->rx_oversize_errors += rd32(hw, TXGBE_MACRXOVERSIZE);
1907         hw_stats->rx_jabber_errors += rd32(hw, TXGBE_MACRXJABBER);
1908
1909         /* MNG Stats */
1910         hw_stats->mng_bmc2host_packets = rd32(hw, TXGBE_MNGBMC2OS);
1911         hw_stats->mng_host2bmc_packets = rd32(hw, TXGBE_MNGOS2BMC);
1912         hw_stats->rx_management_packets = rd32(hw, TXGBE_DMARXMNG);
1913         hw_stats->tx_management_packets = rd32(hw, TXGBE_DMATXMNG);
1914
1915         /* FCoE Stats */
1916         hw_stats->rx_fcoe_crc_errors += rd32(hw, TXGBE_FCOECRC);
1917         hw_stats->rx_fcoe_mbuf_allocation_errors += rd32(hw, TXGBE_FCOELAST);
1918         hw_stats->rx_fcoe_dropped += rd32(hw, TXGBE_FCOERPDC);
1919         hw_stats->rx_fcoe_packets += rd32(hw, TXGBE_FCOEPRC);
1920         hw_stats->tx_fcoe_packets += rd32(hw, TXGBE_FCOEPTC);
1921         hw_stats->rx_fcoe_bytes += rd32(hw, TXGBE_FCOEDWRC);
1922         hw_stats->tx_fcoe_bytes += rd32(hw, TXGBE_FCOEDWTC);
1923
1924         /* Flow Director Stats */
1925         hw_stats->flow_director_matched_filters += rd32(hw, TXGBE_FDIRMATCH);
1926         hw_stats->flow_director_missed_filters += rd32(hw, TXGBE_FDIRMISS);
1927         hw_stats->flow_director_added_filters +=
1928                 TXGBE_FDIRUSED_ADD(rd32(hw, TXGBE_FDIRUSED));
1929         hw_stats->flow_director_removed_filters +=
1930                 TXGBE_FDIRUSED_REM(rd32(hw, TXGBE_FDIRUSED));
1931         hw_stats->flow_director_filter_add_errors +=
1932                 TXGBE_FDIRFAIL_ADD(rd32(hw, TXGBE_FDIRFAIL));
1933         hw_stats->flow_director_filter_remove_errors +=
1934                 TXGBE_FDIRFAIL_REM(rd32(hw, TXGBE_FDIRFAIL));
1935
1936         /* MACsec Stats */
1937         hw_stats->tx_macsec_pkts_untagged += rd32(hw, TXGBE_LSECTX_UTPKT);
1938         hw_stats->tx_macsec_pkts_encrypted +=
1939                         rd32(hw, TXGBE_LSECTX_ENCPKT);
1940         hw_stats->tx_macsec_pkts_protected +=
1941                         rd32(hw, TXGBE_LSECTX_PROTPKT);
1942         hw_stats->tx_macsec_octets_encrypted +=
1943                         rd32(hw, TXGBE_LSECTX_ENCOCT);
1944         hw_stats->tx_macsec_octets_protected +=
1945                         rd32(hw, TXGBE_LSECTX_PROTOCT);
1946         hw_stats->rx_macsec_pkts_untagged += rd32(hw, TXGBE_LSECRX_UTPKT);
1947         hw_stats->rx_macsec_pkts_badtag += rd32(hw, TXGBE_LSECRX_BTPKT);
1948         hw_stats->rx_macsec_pkts_nosci += rd32(hw, TXGBE_LSECRX_NOSCIPKT);
1949         hw_stats->rx_macsec_pkts_unknownsci += rd32(hw, TXGBE_LSECRX_UNSCIPKT);
1950         hw_stats->rx_macsec_octets_decrypted += rd32(hw, TXGBE_LSECRX_DECOCT);
1951         hw_stats->rx_macsec_octets_validated += rd32(hw, TXGBE_LSECRX_VLDOCT);
1952         hw_stats->rx_macsec_sc_pkts_unchecked +=
1953                         rd32(hw, TXGBE_LSECRX_UNCHKPKT);
1954         hw_stats->rx_macsec_sc_pkts_delayed += rd32(hw, TXGBE_LSECRX_DLYPKT);
1955         hw_stats->rx_macsec_sc_pkts_late += rd32(hw, TXGBE_LSECRX_LATEPKT);
1956         for (i = 0; i < 2; i++) {
1957                 hw_stats->rx_macsec_sa_pkts_ok +=
1958                         rd32(hw, TXGBE_LSECRX_OKPKT(i));
1959                 hw_stats->rx_macsec_sa_pkts_invalid +=
1960                         rd32(hw, TXGBE_LSECRX_INVPKT(i));
1961                 hw_stats->rx_macsec_sa_pkts_notvalid +=
1962                         rd32(hw, TXGBE_LSECRX_BADPKT(i));
1963         }
1964         hw_stats->rx_macsec_sa_pkts_unusedsa +=
1965                         rd32(hw, TXGBE_LSECRX_INVSAPKT);
1966         hw_stats->rx_macsec_sa_pkts_notusingsa +=
1967                         rd32(hw, TXGBE_LSECRX_BADSAPKT);
1968
1969         hw_stats->rx_total_missed_packets = 0;
1970         for (i = 0; i < TXGBE_MAX_UP; i++) {
1971                 hw_stats->rx_total_missed_packets +=
1972                         hw_stats->up[i].rx_up_dropped;
1973         }
1974 }
1975
1976 static int
1977 txgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1978 {
1979         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
1980         struct txgbe_hw_stats *hw_stats = TXGBE_DEV_STATS(dev);
1981         struct txgbe_stat_mappings *stat_mappings =
1982                         TXGBE_DEV_STAT_MAPPINGS(dev);
1983         uint32_t i, j;
1984
1985         txgbe_read_stats_registers(hw, hw_stats);
1986
1987         if (stats == NULL)
1988                 return -EINVAL;
1989
1990         /* Fill out the rte_eth_stats statistics structure */
1991         stats->ipackets = hw_stats->rx_packets;
1992         stats->ibytes = hw_stats->rx_bytes;
1993         stats->opackets = hw_stats->tx_packets;
1994         stats->obytes = hw_stats->tx_bytes;
1995
1996         memset(&stats->q_ipackets, 0, sizeof(stats->q_ipackets));
1997         memset(&stats->q_opackets, 0, sizeof(stats->q_opackets));
1998         memset(&stats->q_ibytes, 0, sizeof(stats->q_ibytes));
1999         memset(&stats->q_obytes, 0, sizeof(stats->q_obytes));
2000         memset(&stats->q_errors, 0, sizeof(stats->q_errors));
2001         for (i = 0; i < TXGBE_MAX_QP; i++) {
2002                 uint32_t n = i / NB_QMAP_FIELDS_PER_QSM_REG;
2003                 uint32_t offset = (i % NB_QMAP_FIELDS_PER_QSM_REG) * 8;
2004                 uint32_t q_map;
2005
2006                 q_map = (stat_mappings->rqsm[n] >> offset)
2007                                 & QMAP_FIELD_RESERVED_BITS_MASK;
2008                 j = (q_map < RTE_ETHDEV_QUEUE_STAT_CNTRS
2009                      ? q_map : q_map % RTE_ETHDEV_QUEUE_STAT_CNTRS);
2010                 stats->q_ipackets[j] += hw_stats->qp[i].rx_qp_packets;
2011                 stats->q_ibytes[j] += hw_stats->qp[i].rx_qp_bytes;
2012
2013                 q_map = (stat_mappings->tqsm[n] >> offset)
2014                                 & QMAP_FIELD_RESERVED_BITS_MASK;
2015                 j = (q_map < RTE_ETHDEV_QUEUE_STAT_CNTRS
2016                      ? q_map : q_map % RTE_ETHDEV_QUEUE_STAT_CNTRS);
2017                 stats->q_opackets[j] += hw_stats->qp[i].tx_qp_packets;
2018                 stats->q_obytes[j] += hw_stats->qp[i].tx_qp_bytes;
2019         }
2020
2021         /* Rx Errors */
2022         stats->imissed  = hw_stats->rx_total_missed_packets;
2023         stats->ierrors  = hw_stats->rx_crc_errors +
2024                           hw_stats->rx_mac_short_packet_dropped +
2025                           hw_stats->rx_length_errors +
2026                           hw_stats->rx_undersize_errors +
2027                           hw_stats->rx_oversize_errors +
2028                           hw_stats->rx_drop_packets +
2029                           hw_stats->rx_illegal_byte_errors +
2030                           hw_stats->rx_error_bytes +
2031                           hw_stats->rx_fragment_errors +
2032                           hw_stats->rx_fcoe_crc_errors +
2033                           hw_stats->rx_fcoe_mbuf_allocation_errors;
2034
2035         /* Tx Errors */
2036         stats->oerrors  = 0;
2037         return 0;
2038 }
2039
2040 static int
2041 txgbe_dev_stats_reset(struct rte_eth_dev *dev)
2042 {
2043         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2044         struct txgbe_hw_stats *hw_stats = TXGBE_DEV_STATS(dev);
2045
2046         /* HW registers are cleared on read */
2047         hw->offset_loaded = 0;
2048         txgbe_dev_stats_get(dev, NULL);
2049         hw->offset_loaded = 1;
2050
2051         /* Reset software totals */
2052         memset(hw_stats, 0, sizeof(*hw_stats));
2053
2054         return 0;
2055 }
2056
2057 /* This function calculates the number of xstats based on the current config */
2058 static unsigned
2059 txgbe_xstats_calc_num(struct rte_eth_dev *dev)
2060 {
2061         int nb_queues = max(dev->data->nb_rx_queues, dev->data->nb_tx_queues);
2062         return TXGBE_NB_HW_STATS +
2063                TXGBE_NB_UP_STATS * TXGBE_MAX_UP +
2064                TXGBE_NB_QP_STATS * nb_queues;
2065 }
2066
2067 static inline int
2068 txgbe_get_name_by_id(uint32_t id, char *name, uint32_t size)
2069 {
2070         int nb, st;
2071
2072         /* Extended stats from txgbe_hw_stats */
2073         if (id < TXGBE_NB_HW_STATS) {
2074                 snprintf(name, size, "[hw]%s",
2075                         rte_txgbe_stats_strings[id].name);
2076                 return 0;
2077         }
2078         id -= TXGBE_NB_HW_STATS;
2079
2080         /* Priority Stats */
2081         if (id < TXGBE_NB_UP_STATS * TXGBE_MAX_UP) {
2082                 nb = id / TXGBE_NB_UP_STATS;
2083                 st = id % TXGBE_NB_UP_STATS;
2084                 snprintf(name, size, "[p%u]%s", nb,
2085                         rte_txgbe_up_strings[st].name);
2086                 return 0;
2087         }
2088         id -= TXGBE_NB_UP_STATS * TXGBE_MAX_UP;
2089
2090         /* Queue Stats */
2091         if (id < TXGBE_NB_QP_STATS * TXGBE_MAX_QP) {
2092                 nb = id / TXGBE_NB_QP_STATS;
2093                 st = id % TXGBE_NB_QP_STATS;
2094                 snprintf(name, size, "[q%u]%s", nb,
2095                         rte_txgbe_qp_strings[st].name);
2096                 return 0;
2097         }
2098         id -= TXGBE_NB_QP_STATS * TXGBE_MAX_QP;
2099
2100         return -(int)(id + 1);
2101 }
2102
2103 static inline int
2104 txgbe_get_offset_by_id(uint32_t id, uint32_t *offset)
2105 {
2106         int nb, st;
2107
2108         /* Extended stats from txgbe_hw_stats */
2109         if (id < TXGBE_NB_HW_STATS) {
2110                 *offset = rte_txgbe_stats_strings[id].offset;
2111                 return 0;
2112         }
2113         id -= TXGBE_NB_HW_STATS;
2114
2115         /* Priority Stats */
2116         if (id < TXGBE_NB_UP_STATS * TXGBE_MAX_UP) {
2117                 nb = id / TXGBE_NB_UP_STATS;
2118                 st = id % TXGBE_NB_UP_STATS;
2119                 *offset = rte_txgbe_up_strings[st].offset +
2120                         nb * (TXGBE_NB_UP_STATS * sizeof(uint64_t));
2121                 return 0;
2122         }
2123         id -= TXGBE_NB_UP_STATS * TXGBE_MAX_UP;
2124
2125         /* Queue Stats */
2126         if (id < TXGBE_NB_QP_STATS * TXGBE_MAX_QP) {
2127                 nb = id / TXGBE_NB_QP_STATS;
2128                 st = id % TXGBE_NB_QP_STATS;
2129                 *offset = rte_txgbe_qp_strings[st].offset +
2130                         nb * (TXGBE_NB_QP_STATS * sizeof(uint64_t));
2131                 return 0;
2132         }
2133         id -= TXGBE_NB_QP_STATS * TXGBE_MAX_QP;
2134
2135         return -(int)(id + 1);
2136 }
2137
2138 static int txgbe_dev_xstats_get_names(struct rte_eth_dev *dev,
2139         struct rte_eth_xstat_name *xstats_names, unsigned int limit)
2140 {
2141         unsigned int i, count;
2142
2143         count = txgbe_xstats_calc_num(dev);
2144         if (xstats_names == NULL)
2145                 return count;
2146
2147         /* Note: limit >= cnt_stats checked upstream
2148          * in rte_eth_xstats_names()
2149          */
2150         limit = min(limit, count);
2151
2152         /* Extended stats from txgbe_hw_stats */
2153         for (i = 0; i < limit; i++) {
2154                 if (txgbe_get_name_by_id(i, xstats_names[i].name,
2155                         sizeof(xstats_names[i].name))) {
2156                         PMD_INIT_LOG(WARNING, "id value %d isn't valid", i);
2157                         break;
2158                 }
2159         }
2160
2161         return i;
2162 }
2163
2164 static int txgbe_dev_xstats_get_names_by_id(struct rte_eth_dev *dev,
2165         struct rte_eth_xstat_name *xstats_names,
2166         const uint64_t *ids,
2167         unsigned int limit)
2168 {
2169         unsigned int i;
2170
2171         if (ids == NULL)
2172                 return txgbe_dev_xstats_get_names(dev, xstats_names, limit);
2173
2174         for (i = 0; i < limit; i++) {
2175                 if (txgbe_get_name_by_id(ids[i], xstats_names[i].name,
2176                                 sizeof(xstats_names[i].name))) {
2177                         PMD_INIT_LOG(WARNING, "id value %d isn't valid", i);
2178                         return -1;
2179                 }
2180         }
2181
2182         return i;
2183 }
2184
2185 static int
2186 txgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2187                                          unsigned int limit)
2188 {
2189         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2190         struct txgbe_hw_stats *hw_stats = TXGBE_DEV_STATS(dev);
2191         unsigned int i, count;
2192
2193         txgbe_read_stats_registers(hw, hw_stats);
2194
2195         /* If this is a reset xstats is NULL, and we have cleared the
2196          * registers by reading them.
2197          */
2198         count = txgbe_xstats_calc_num(dev);
2199         if (xstats == NULL)
2200                 return count;
2201
2202         limit = min(limit, txgbe_xstats_calc_num(dev));
2203
2204         /* Extended stats from txgbe_hw_stats */
2205         for (i = 0; i < limit; i++) {
2206                 uint32_t offset = 0;
2207
2208                 if (txgbe_get_offset_by_id(i, &offset)) {
2209                         PMD_INIT_LOG(WARNING, "id value %d isn't valid", i);
2210                         break;
2211                 }
2212                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) + offset);
2213                 xstats[i].id = i;
2214         }
2215
2216         return i;
2217 }
2218
2219 static int
2220 txgbe_dev_xstats_get_(struct rte_eth_dev *dev, uint64_t *values,
2221                                          unsigned int limit)
2222 {
2223         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2224         struct txgbe_hw_stats *hw_stats = TXGBE_DEV_STATS(dev);
2225         unsigned int i, count;
2226
2227         txgbe_read_stats_registers(hw, hw_stats);
2228
2229         /* If this is a reset xstats is NULL, and we have cleared the
2230          * registers by reading them.
2231          */
2232         count = txgbe_xstats_calc_num(dev);
2233         if (values == NULL)
2234                 return count;
2235
2236         limit = min(limit, txgbe_xstats_calc_num(dev));
2237
2238         /* Extended stats from txgbe_hw_stats */
2239         for (i = 0; i < limit; i++) {
2240                 uint32_t offset;
2241
2242                 if (txgbe_get_offset_by_id(i, &offset)) {
2243                         PMD_INIT_LOG(WARNING, "id value %d isn't valid", i);
2244                         break;
2245                 }
2246                 values[i] = *(uint64_t *)(((char *)hw_stats) + offset);
2247         }
2248
2249         return i;
2250 }
2251
2252 static int
2253 txgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
2254                 uint64_t *values, unsigned int limit)
2255 {
2256         struct txgbe_hw_stats *hw_stats = TXGBE_DEV_STATS(dev);
2257         unsigned int i;
2258
2259         if (ids == NULL)
2260                 return txgbe_dev_xstats_get_(dev, values, limit);
2261
2262         for (i = 0; i < limit; i++) {
2263                 uint32_t offset;
2264
2265                 if (txgbe_get_offset_by_id(ids[i], &offset)) {
2266                         PMD_INIT_LOG(WARNING, "id value %d isn't valid", i);
2267                         break;
2268                 }
2269                 values[i] = *(uint64_t *)(((char *)hw_stats) + offset);
2270         }
2271
2272         return i;
2273 }
2274
2275 static int
2276 txgbe_dev_xstats_reset(struct rte_eth_dev *dev)
2277 {
2278         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2279         struct txgbe_hw_stats *hw_stats = TXGBE_DEV_STATS(dev);
2280
2281         /* HW registers are cleared on read */
2282         hw->offset_loaded = 0;
2283         txgbe_read_stats_registers(hw, hw_stats);
2284         hw->offset_loaded = 1;
2285
2286         /* Reset software totals */
2287         memset(hw_stats, 0, sizeof(*hw_stats));
2288
2289         return 0;
2290 }
2291
2292 static int
2293 txgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
2294 {
2295         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2296         u16 eeprom_verh, eeprom_verl;
2297         u32 etrack_id;
2298         int ret;
2299
2300         hw->rom.readw_sw(hw, TXGBE_EEPROM_VERSION_H, &eeprom_verh);
2301         hw->rom.readw_sw(hw, TXGBE_EEPROM_VERSION_L, &eeprom_verl);
2302
2303         etrack_id = (eeprom_verh << 16) | eeprom_verl;
2304         ret = snprintf(fw_version, fw_size, "0x%08x", etrack_id);
2305
2306         ret += 1; /* add the size of '\0' */
2307         if (fw_size < (u32)ret)
2308                 return ret;
2309         else
2310                 return 0;
2311 }
2312
2313 static int
2314 txgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2315 {
2316         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2317         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2318
2319         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
2320         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
2321         dev_info->min_rx_bufsize = 1024;
2322         dev_info->max_rx_pktlen = 15872;
2323         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
2324         dev_info->max_hash_mac_addrs = TXGBE_VMDQ_NUM_UC_MAC;
2325         dev_info->max_vfs = pci_dev->max_vfs;
2326         dev_info->max_vmdq_pools = ETH_64_POOLS;
2327         dev_info->vmdq_queue_num = dev_info->max_rx_queues;
2328         dev_info->rx_queue_offload_capa = txgbe_get_rx_queue_offloads(dev);
2329         dev_info->rx_offload_capa = (txgbe_get_rx_port_offloads(dev) |
2330                                      dev_info->rx_queue_offload_capa);
2331         dev_info->tx_queue_offload_capa = txgbe_get_tx_queue_offloads(dev);
2332         dev_info->tx_offload_capa = txgbe_get_tx_port_offloads(dev);
2333
2334         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2335                 .rx_thresh = {
2336                         .pthresh = TXGBE_DEFAULT_RX_PTHRESH,
2337                         .hthresh = TXGBE_DEFAULT_RX_HTHRESH,
2338                         .wthresh = TXGBE_DEFAULT_RX_WTHRESH,
2339                 },
2340                 .rx_free_thresh = TXGBE_DEFAULT_RX_FREE_THRESH,
2341                 .rx_drop_en = 0,
2342                 .offloads = 0,
2343         };
2344
2345         dev_info->default_txconf = (struct rte_eth_txconf) {
2346                 .tx_thresh = {
2347                         .pthresh = TXGBE_DEFAULT_TX_PTHRESH,
2348                         .hthresh = TXGBE_DEFAULT_TX_HTHRESH,
2349                         .wthresh = TXGBE_DEFAULT_TX_WTHRESH,
2350                 },
2351                 .tx_free_thresh = TXGBE_DEFAULT_TX_FREE_THRESH,
2352                 .offloads = 0,
2353         };
2354
2355         dev_info->rx_desc_lim = rx_desc_lim;
2356         dev_info->tx_desc_lim = tx_desc_lim;
2357
2358         dev_info->hash_key_size = TXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
2359         dev_info->reta_size = ETH_RSS_RETA_SIZE_128;
2360         dev_info->flow_type_rss_offloads = TXGBE_RSS_OFFLOAD_ALL;
2361
2362         dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
2363         dev_info->speed_capa |= ETH_LINK_SPEED_100M;
2364
2365         /* Driver-preferred Rx/Tx parameters */
2366         dev_info->default_rxportconf.burst_size = 32;
2367         dev_info->default_txportconf.burst_size = 32;
2368         dev_info->default_rxportconf.nb_queues = 1;
2369         dev_info->default_txportconf.nb_queues = 1;
2370         dev_info->default_rxportconf.ring_size = 256;
2371         dev_info->default_txportconf.ring_size = 256;
2372
2373         return 0;
2374 }
2375
2376 const uint32_t *
2377 txgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev)
2378 {
2379         if (dev->rx_pkt_burst == txgbe_recv_pkts ||
2380             dev->rx_pkt_burst == txgbe_recv_pkts_lro_single_alloc ||
2381             dev->rx_pkt_burst == txgbe_recv_pkts_lro_bulk_alloc ||
2382             dev->rx_pkt_burst == txgbe_recv_pkts_bulk_alloc)
2383                 return txgbe_get_supported_ptypes();
2384
2385         return NULL;
2386 }
2387
2388 void
2389 txgbe_dev_setup_link_alarm_handler(void *param)
2390 {
2391         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2392         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2393         struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);
2394         u32 speed;
2395         bool autoneg = false;
2396
2397         speed = hw->phy.autoneg_advertised;
2398         if (!speed)
2399                 hw->mac.get_link_capabilities(hw, &speed, &autoneg);
2400
2401         hw->mac.setup_link(hw, speed, true);
2402
2403         intr->flags &= ~TXGBE_FLAG_NEED_LINK_CONFIG;
2404 }
2405
2406 /* return 0 means link status changed, -1 means not changed */
2407 int
2408 txgbe_dev_link_update_share(struct rte_eth_dev *dev,
2409                             int wait_to_complete)
2410 {
2411         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2412         struct rte_eth_link link;
2413         u32 link_speed = TXGBE_LINK_SPEED_UNKNOWN;
2414         struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);
2415         bool link_up;
2416         int err;
2417         int wait = 1;
2418
2419         memset(&link, 0, sizeof(link));
2420         link.link_status = ETH_LINK_DOWN;
2421         link.link_speed = ETH_SPEED_NUM_NONE;
2422         link.link_duplex = ETH_LINK_HALF_DUPLEX;
2423         link.link_autoneg = ETH_LINK_AUTONEG;
2424
2425         hw->mac.get_link_status = true;
2426
2427         if (intr->flags & TXGBE_FLAG_NEED_LINK_CONFIG)
2428                 return rte_eth_linkstatus_set(dev, &link);
2429
2430         /* check if it needs to wait to complete, if lsc interrupt is enabled */
2431         if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
2432                 wait = 0;
2433
2434         err = hw->mac.check_link(hw, &link_speed, &link_up, wait);
2435
2436         if (err != 0) {
2437                 link.link_speed = ETH_SPEED_NUM_100M;
2438                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
2439                 return rte_eth_linkstatus_set(dev, &link);
2440         }
2441
2442         if (link_up == 0) {
2443                 if (hw->phy.media_type == txgbe_media_type_fiber) {
2444                         intr->flags |= TXGBE_FLAG_NEED_LINK_CONFIG;
2445                         rte_eal_alarm_set(10,
2446                                 txgbe_dev_setup_link_alarm_handler, dev);
2447                 }
2448                 return rte_eth_linkstatus_set(dev, &link);
2449         }
2450
2451         intr->flags &= ~TXGBE_FLAG_NEED_LINK_CONFIG;
2452         link.link_status = ETH_LINK_UP;
2453         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2454
2455         switch (link_speed) {
2456         default:
2457         case TXGBE_LINK_SPEED_UNKNOWN:
2458                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
2459                 link.link_speed = ETH_SPEED_NUM_100M;
2460                 break;
2461
2462         case TXGBE_LINK_SPEED_100M_FULL:
2463                 link.link_speed = ETH_SPEED_NUM_100M;
2464                 break;
2465
2466         case TXGBE_LINK_SPEED_1GB_FULL:
2467                 link.link_speed = ETH_SPEED_NUM_1G;
2468                 break;
2469
2470         case TXGBE_LINK_SPEED_2_5GB_FULL:
2471                 link.link_speed = ETH_SPEED_NUM_2_5G;
2472                 break;
2473
2474         case TXGBE_LINK_SPEED_5GB_FULL:
2475                 link.link_speed = ETH_SPEED_NUM_5G;
2476                 break;
2477
2478         case TXGBE_LINK_SPEED_10GB_FULL:
2479                 link.link_speed = ETH_SPEED_NUM_10G;
2480                 break;
2481         }
2482
2483         return rte_eth_linkstatus_set(dev, &link);
2484 }
2485
2486 static int
2487 txgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
2488 {
2489         return txgbe_dev_link_update_share(dev, wait_to_complete);
2490 }
2491
2492 static int
2493 txgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
2494 {
2495         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2496         uint32_t fctrl;
2497
2498         fctrl = rd32(hw, TXGBE_PSRCTL);
2499         fctrl |= (TXGBE_PSRCTL_UCP | TXGBE_PSRCTL_MCP);
2500         wr32(hw, TXGBE_PSRCTL, fctrl);
2501
2502         return 0;
2503 }
2504
2505 static int
2506 txgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
2507 {
2508         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2509         uint32_t fctrl;
2510
2511         fctrl = rd32(hw, TXGBE_PSRCTL);
2512         fctrl &= (~TXGBE_PSRCTL_UCP);
2513         if (dev->data->all_multicast == 1)
2514                 fctrl |= TXGBE_PSRCTL_MCP;
2515         else
2516                 fctrl &= (~TXGBE_PSRCTL_MCP);
2517         wr32(hw, TXGBE_PSRCTL, fctrl);
2518
2519         return 0;
2520 }
2521
2522 static int
2523 txgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
2524 {
2525         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2526         uint32_t fctrl;
2527
2528         fctrl = rd32(hw, TXGBE_PSRCTL);
2529         fctrl |= TXGBE_PSRCTL_MCP;
2530         wr32(hw, TXGBE_PSRCTL, fctrl);
2531
2532         return 0;
2533 }
2534
2535 static int
2536 txgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
2537 {
2538         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2539         uint32_t fctrl;
2540
2541         if (dev->data->promiscuous == 1)
2542                 return 0; /* must remain in all_multicast mode */
2543
2544         fctrl = rd32(hw, TXGBE_PSRCTL);
2545         fctrl &= (~TXGBE_PSRCTL_MCP);
2546         wr32(hw, TXGBE_PSRCTL, fctrl);
2547
2548         return 0;
2549 }
2550
2551 /**
2552  * It clears the interrupt causes and enables the interrupt.
2553  * It will be called once only during nic initialized.
2554  *
2555  * @param dev
2556  *  Pointer to struct rte_eth_dev.
2557  * @param on
2558  *  Enable or Disable.
2559  *
2560  * @return
2561  *  - On success, zero.
2562  *  - On failure, a negative value.
2563  */
2564 static int
2565 txgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on)
2566 {
2567         struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);
2568
2569         txgbe_dev_link_status_print(dev);
2570         if (on)
2571                 intr->mask_misc |= TXGBE_ICRMISC_LSC;
2572         else
2573                 intr->mask_misc &= ~TXGBE_ICRMISC_LSC;
2574
2575         return 0;
2576 }
2577
2578 /**
2579  * It clears the interrupt causes and enables the interrupt.
2580  * It will be called once only during nic initialized.
2581  *
2582  * @param dev
2583  *  Pointer to struct rte_eth_dev.
2584  *
2585  * @return
2586  *  - On success, zero.
2587  *  - On failure, a negative value.
2588  */
2589 static int
2590 txgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
2591 {
2592         struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);
2593
2594         intr->mask[0] |= TXGBE_ICR_MASK;
2595         intr->mask[1] |= TXGBE_ICR_MASK;
2596
2597         return 0;
2598 }
2599
2600 /**
2601  * It clears the interrupt causes and enables the interrupt.
2602  * It will be called once only during nic initialized.
2603  *
2604  * @param dev
2605  *  Pointer to struct rte_eth_dev.
2606  *
2607  * @return
2608  *  - On success, zero.
2609  *  - On failure, a negative value.
2610  */
2611 static int
2612 txgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev)
2613 {
2614         struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);
2615
2616         intr->mask_misc |= TXGBE_ICRMISC_LNKSEC;
2617
2618         return 0;
2619 }
2620
2621 /*
2622  * It reads ICR and sets flag (TXGBE_ICRMISC_LSC) for the link_update.
2623  *
2624  * @param dev
2625  *  Pointer to struct rte_eth_dev.
2626  *
2627  * @return
2628  *  - On success, zero.
2629  *  - On failure, a negative value.
2630  */
2631 static int
2632 txgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
2633 {
2634         uint32_t eicr;
2635         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2636         struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);
2637
2638         /* clear all cause mask */
2639         txgbe_disable_intr(hw);
2640
2641         /* read-on-clear nic registers here */
2642         eicr = ((u32 *)hw->isb_mem)[TXGBE_ISB_MISC];
2643         PMD_DRV_LOG(DEBUG, "eicr %x", eicr);
2644
2645         intr->flags = 0;
2646
2647         /* set flag for async link update */
2648         if (eicr & TXGBE_ICRMISC_LSC)
2649                 intr->flags |= TXGBE_FLAG_NEED_LINK_UPDATE;
2650
2651         if (eicr & TXGBE_ICRMISC_VFMBX)
2652                 intr->flags |= TXGBE_FLAG_MAILBOX;
2653
2654         if (eicr & TXGBE_ICRMISC_LNKSEC)
2655                 intr->flags |= TXGBE_FLAG_MACSEC;
2656
2657         if (eicr & TXGBE_ICRMISC_GPIO)
2658                 intr->flags |= TXGBE_FLAG_PHY_INTERRUPT;
2659
2660         return 0;
2661 }
2662
2663 /**
2664  * It gets and then prints the link status.
2665  *
2666  * @param dev
2667  *  Pointer to struct rte_eth_dev.
2668  *
2669  * @return
2670  *  - On success, zero.
2671  *  - On failure, a negative value.
2672  */
2673 static void
2674 txgbe_dev_link_status_print(struct rte_eth_dev *dev)
2675 {
2676         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2677         struct rte_eth_link link;
2678
2679         rte_eth_linkstatus_get(dev, &link);
2680
2681         if (link.link_status) {
2682                 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
2683                                         (int)(dev->data->port_id),
2684                                         (unsigned int)link.link_speed,
2685                         link.link_duplex == ETH_LINK_FULL_DUPLEX ?
2686                                         "full-duplex" : "half-duplex");
2687         } else {
2688                 PMD_INIT_LOG(INFO, " Port %d: Link Down",
2689                                 (int)(dev->data->port_id));
2690         }
2691         PMD_INIT_LOG(DEBUG, "PCI Address: " PCI_PRI_FMT,
2692                                 pci_dev->addr.domain,
2693                                 pci_dev->addr.bus,
2694                                 pci_dev->addr.devid,
2695                                 pci_dev->addr.function);
2696 }
2697
2698 /*
2699  * It executes link_update after knowing an interrupt occurred.
2700  *
2701  * @param dev
2702  *  Pointer to struct rte_eth_dev.
2703  *
2704  * @return
2705  *  - On success, zero.
2706  *  - On failure, a negative value.
2707  */
2708 static int
2709 txgbe_dev_interrupt_action(struct rte_eth_dev *dev,
2710                            struct rte_intr_handle *intr_handle)
2711 {
2712         struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);
2713         int64_t timeout;
2714         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2715
2716         PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
2717
2718         if (intr->flags & TXGBE_FLAG_MAILBOX) {
2719                 txgbe_pf_mbx_process(dev);
2720                 intr->flags &= ~TXGBE_FLAG_MAILBOX;
2721         }
2722
2723         if (intr->flags & TXGBE_FLAG_PHY_INTERRUPT) {
2724                 hw->phy.handle_lasi(hw);
2725                 intr->flags &= ~TXGBE_FLAG_PHY_INTERRUPT;
2726         }
2727
2728         if (intr->flags & TXGBE_FLAG_NEED_LINK_UPDATE) {
2729                 struct rte_eth_link link;
2730
2731                 /*get the link status before link update, for predicting later*/
2732                 rte_eth_linkstatus_get(dev, &link);
2733
2734                 txgbe_dev_link_update(dev, 0);
2735
2736                 /* likely to up */
2737                 if (!link.link_status)
2738                         /* handle it 1 sec later, wait it being stable */
2739                         timeout = TXGBE_LINK_UP_CHECK_TIMEOUT;
2740                 /* likely to down */
2741                 else
2742                         /* handle it 4 sec later, wait it being stable */
2743                         timeout = TXGBE_LINK_DOWN_CHECK_TIMEOUT;
2744
2745                 txgbe_dev_link_status_print(dev);
2746                 if (rte_eal_alarm_set(timeout * 1000,
2747                                       txgbe_dev_interrupt_delayed_handler,
2748                                       (void *)dev) < 0) {
2749                         PMD_DRV_LOG(ERR, "Error setting alarm");
2750                 } else {
2751                         /* remember original mask */
2752                         intr->mask_misc_orig = intr->mask_misc;
2753                         /* only disable lsc interrupt */
2754                         intr->mask_misc &= ~TXGBE_ICRMISC_LSC;
2755                 }
2756         }
2757
2758         PMD_DRV_LOG(DEBUG, "enable intr immediately");
2759         txgbe_enable_intr(dev);
2760         rte_intr_enable(intr_handle);
2761
2762         return 0;
2763 }
2764
2765 /**
2766  * Interrupt handler which shall be registered for alarm callback for delayed
2767  * handling specific interrupt to wait for the stable nic state. As the
2768  * NIC interrupt state is not stable for txgbe after link is just down,
2769  * it needs to wait 4 seconds to get the stable status.
2770  *
2771  * @param handle
2772  *  Pointer to interrupt handle.
2773  * @param param
2774  *  The address of parameter (struct rte_eth_dev *) registered before.
2775  *
2776  * @return
2777  *  void
2778  */
2779 static void
2780 txgbe_dev_interrupt_delayed_handler(void *param)
2781 {
2782         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2783         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2784         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2785         struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);
2786         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2787         uint32_t eicr;
2788
2789         txgbe_disable_intr(hw);
2790
2791         eicr = ((u32 *)hw->isb_mem)[TXGBE_ISB_MISC];
2792         if (eicr & TXGBE_ICRMISC_VFMBX)
2793                 txgbe_pf_mbx_process(dev);
2794
2795         if (intr->flags & TXGBE_FLAG_PHY_INTERRUPT) {
2796                 hw->phy.handle_lasi(hw);
2797                 intr->flags &= ~TXGBE_FLAG_PHY_INTERRUPT;
2798         }
2799
2800         if (intr->flags & TXGBE_FLAG_NEED_LINK_UPDATE) {
2801                 txgbe_dev_link_update(dev, 0);
2802                 intr->flags &= ~TXGBE_FLAG_NEED_LINK_UPDATE;
2803                 txgbe_dev_link_status_print(dev);
2804                 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC,
2805                                               NULL);
2806         }
2807
2808         if (intr->flags & TXGBE_FLAG_MACSEC) {
2809                 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_MACSEC,
2810                                               NULL);
2811                 intr->flags &= ~TXGBE_FLAG_MACSEC;
2812         }
2813
2814         /* restore original mask */
2815         intr->mask_misc = intr->mask_misc_orig;
2816         intr->mask_misc_orig = 0;
2817
2818         PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
2819         txgbe_enable_intr(dev);
2820         rte_intr_enable(intr_handle);
2821 }
2822
2823 /**
2824  * Interrupt handler triggered by NIC  for handling
2825  * specific interrupt.
2826  *
2827  * @param handle
2828  *  Pointer to interrupt handle.
2829  * @param param
2830  *  The address of parameter (struct rte_eth_dev *) registered before.
2831  *
2832  * @return
2833  *  void
2834  */
2835 static void
2836 txgbe_dev_interrupt_handler(void *param)
2837 {
2838         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2839
2840         txgbe_dev_interrupt_get_status(dev);
2841         txgbe_dev_interrupt_action(dev, dev->intr_handle);
2842 }
2843
2844 static int
2845 txgbe_dev_led_on(struct rte_eth_dev *dev)
2846 {
2847         struct txgbe_hw *hw;
2848
2849         hw = TXGBE_DEV_HW(dev);
2850         return txgbe_led_on(hw, 4) == 0 ? 0 : -ENOTSUP;
2851 }
2852
2853 static int
2854 txgbe_dev_led_off(struct rte_eth_dev *dev)
2855 {
2856         struct txgbe_hw *hw;
2857
2858         hw = TXGBE_DEV_HW(dev);
2859         return txgbe_led_off(hw, 4) == 0 ? 0 : -ENOTSUP;
2860 }
2861
2862 static int
2863 txgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2864 {
2865         struct txgbe_hw *hw;
2866         uint32_t mflcn_reg;
2867         uint32_t fccfg_reg;
2868         int rx_pause;
2869         int tx_pause;
2870
2871         hw = TXGBE_DEV_HW(dev);
2872
2873         fc_conf->pause_time = hw->fc.pause_time;
2874         fc_conf->high_water = hw->fc.high_water[0];
2875         fc_conf->low_water = hw->fc.low_water[0];
2876         fc_conf->send_xon = hw->fc.send_xon;
2877         fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
2878
2879         /*
2880          * Return rx_pause status according to actual setting of
2881          * RXFCCFG register.
2882          */
2883         mflcn_reg = rd32(hw, TXGBE_RXFCCFG);
2884         if (mflcn_reg & (TXGBE_RXFCCFG_FC | TXGBE_RXFCCFG_PFC))
2885                 rx_pause = 1;
2886         else
2887                 rx_pause = 0;
2888
2889         /*
2890          * Return tx_pause status according to actual setting of
2891          * TXFCCFG register.
2892          */
2893         fccfg_reg = rd32(hw, TXGBE_TXFCCFG);
2894         if (fccfg_reg & (TXGBE_TXFCCFG_FC | TXGBE_TXFCCFG_PFC))
2895                 tx_pause = 1;
2896         else
2897                 tx_pause = 0;
2898
2899         if (rx_pause && tx_pause)
2900                 fc_conf->mode = RTE_FC_FULL;
2901         else if (rx_pause)
2902                 fc_conf->mode = RTE_FC_RX_PAUSE;
2903         else if (tx_pause)
2904                 fc_conf->mode = RTE_FC_TX_PAUSE;
2905         else
2906                 fc_conf->mode = RTE_FC_NONE;
2907
2908         return 0;
2909 }
2910
2911 static int
2912 txgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2913 {
2914         struct txgbe_hw *hw;
2915         int err;
2916         uint32_t rx_buf_size;
2917         uint32_t max_high_water;
2918         enum txgbe_fc_mode rte_fcmode_2_txgbe_fcmode[] = {
2919                 txgbe_fc_none,
2920                 txgbe_fc_rx_pause,
2921                 txgbe_fc_tx_pause,
2922                 txgbe_fc_full
2923         };
2924
2925         PMD_INIT_FUNC_TRACE();
2926
2927         hw = TXGBE_DEV_HW(dev);
2928         rx_buf_size = rd32(hw, TXGBE_PBRXSIZE(0));
2929         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
2930
2931         /*
2932          * At least reserve one Ethernet frame for watermark
2933          * high_water/low_water in kilo bytes for txgbe
2934          */
2935         max_high_water = (rx_buf_size - RTE_ETHER_MAX_LEN) >> 10;
2936         if (fc_conf->high_water > max_high_water ||
2937             fc_conf->high_water < fc_conf->low_water) {
2938                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
2939                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
2940                 return -EINVAL;
2941         }
2942
2943         hw->fc.requested_mode = rte_fcmode_2_txgbe_fcmode[fc_conf->mode];
2944         hw->fc.pause_time     = fc_conf->pause_time;
2945         hw->fc.high_water[0]  = fc_conf->high_water;
2946         hw->fc.low_water[0]   = fc_conf->low_water;
2947         hw->fc.send_xon       = fc_conf->send_xon;
2948         hw->fc.disable_fc_autoneg = !fc_conf->autoneg;
2949
2950         err = txgbe_fc_enable(hw);
2951
2952         /* Not negotiated is not an error case */
2953         if (err == 0 || err == TXGBE_ERR_FC_NOT_NEGOTIATED) {
2954                 wr32m(hw, TXGBE_MACRXFLT, TXGBE_MACRXFLT_CTL_MASK,
2955                       (fc_conf->mac_ctrl_frame_fwd
2956                        ? TXGBE_MACRXFLT_CTL_NOPS : TXGBE_MACRXFLT_CTL_DROP));
2957                 txgbe_flush(hw);
2958
2959                 return 0;
2960         }
2961
2962         PMD_INIT_LOG(ERR, "txgbe_fc_enable = 0x%x", err);
2963         return -EIO;
2964 }
2965
2966 static int
2967 txgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
2968                 struct rte_eth_pfc_conf *pfc_conf)
2969 {
2970         int err;
2971         uint32_t rx_buf_size;
2972         uint32_t max_high_water;
2973         uint8_t tc_num;
2974         uint8_t  map[TXGBE_DCB_UP_MAX] = { 0 };
2975         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2976         struct txgbe_dcb_config *dcb_config = TXGBE_DEV_DCB_CONFIG(dev);
2977
2978         enum txgbe_fc_mode rte_fcmode_2_txgbe_fcmode[] = {
2979                 txgbe_fc_none,
2980                 txgbe_fc_rx_pause,
2981                 txgbe_fc_tx_pause,
2982                 txgbe_fc_full
2983         };
2984
2985         PMD_INIT_FUNC_TRACE();
2986
2987         txgbe_dcb_unpack_map_cee(dcb_config, TXGBE_DCB_RX_CONFIG, map);
2988         tc_num = map[pfc_conf->priority];
2989         rx_buf_size = rd32(hw, TXGBE_PBRXSIZE(tc_num));
2990         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
2991         /*
2992          * At least reserve one Ethernet frame for watermark
2993          * high_water/low_water in kilo bytes for txgbe
2994          */
2995         max_high_water = (rx_buf_size - RTE_ETHER_MAX_LEN) >> 10;
2996         if (pfc_conf->fc.high_water > max_high_water ||
2997             pfc_conf->fc.high_water <= pfc_conf->fc.low_water) {
2998                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
2999                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
3000                 return -EINVAL;
3001         }
3002
3003         hw->fc.requested_mode = rte_fcmode_2_txgbe_fcmode[pfc_conf->fc.mode];
3004         hw->fc.pause_time = pfc_conf->fc.pause_time;
3005         hw->fc.send_xon = pfc_conf->fc.send_xon;
3006         hw->fc.low_water[tc_num] =  pfc_conf->fc.low_water;
3007         hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
3008
3009         err = txgbe_dcb_pfc_enable(hw, tc_num);
3010
3011         /* Not negotiated is not an error case */
3012         if (err == 0 || err == TXGBE_ERR_FC_NOT_NEGOTIATED)
3013                 return 0;
3014
3015         PMD_INIT_LOG(ERR, "txgbe_dcb_pfc_enable = 0x%x", err);
3016         return -EIO;
3017 }
3018
3019 int
3020 txgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
3021                           struct rte_eth_rss_reta_entry64 *reta_conf,
3022                           uint16_t reta_size)
3023 {
3024         uint8_t i, j, mask;
3025         uint32_t reta;
3026         uint16_t idx, shift;
3027         struct txgbe_adapter *adapter = TXGBE_DEV_ADAPTER(dev);
3028         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3029
3030         PMD_INIT_FUNC_TRACE();
3031
3032         if (!txgbe_rss_update_sp(hw->mac.type)) {
3033                 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this "
3034                         "NIC.");
3035                 return -ENOTSUP;
3036         }
3037
3038         if (reta_size != ETH_RSS_RETA_SIZE_128) {
3039                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3040                         "(%d) doesn't match the number hardware can supported "
3041                         "(%d)", reta_size, ETH_RSS_RETA_SIZE_128);
3042                 return -EINVAL;
3043         }
3044
3045         for (i = 0; i < reta_size; i += 4) {
3046                 idx = i / RTE_RETA_GROUP_SIZE;
3047                 shift = i % RTE_RETA_GROUP_SIZE;
3048                 mask = (uint8_t)RS64(reta_conf[idx].mask, shift, 0xF);
3049                 if (!mask)
3050                         continue;
3051
3052                 reta = rd32a(hw, TXGBE_REG_RSSTBL, i >> 2);
3053                 for (j = 0; j < 4; j++) {
3054                         if (RS8(mask, j, 0x1)) {
3055                                 reta  &= ~(MS32(8 * j, 0xFF));
3056                                 reta |= LS32(reta_conf[idx].reta[shift + j],
3057                                                 8 * j, 0xFF);
3058                         }
3059                 }
3060                 wr32a(hw, TXGBE_REG_RSSTBL, i >> 2, reta);
3061         }
3062         adapter->rss_reta_updated = 1;
3063
3064         return 0;
3065 }
3066
3067 int
3068 txgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
3069                          struct rte_eth_rss_reta_entry64 *reta_conf,
3070                          uint16_t reta_size)
3071 {
3072         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3073         uint8_t i, j, mask;
3074         uint32_t reta;
3075         uint16_t idx, shift;
3076
3077         PMD_INIT_FUNC_TRACE();
3078
3079         if (reta_size != ETH_RSS_RETA_SIZE_128) {
3080                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3081                         "(%d) doesn't match the number hardware can supported "
3082                         "(%d)", reta_size, ETH_RSS_RETA_SIZE_128);
3083                 return -EINVAL;
3084         }
3085
3086         for (i = 0; i < reta_size; i += 4) {
3087                 idx = i / RTE_RETA_GROUP_SIZE;
3088                 shift = i % RTE_RETA_GROUP_SIZE;
3089                 mask = (uint8_t)RS64(reta_conf[idx].mask, shift, 0xF);
3090                 if (!mask)
3091                         continue;
3092
3093                 reta = rd32a(hw, TXGBE_REG_RSSTBL, i >> 2);
3094                 for (j = 0; j < 4; j++) {
3095                         if (RS8(mask, j, 0x1))
3096                                 reta_conf[idx].reta[shift + j] =
3097                                         (uint16_t)RS32(reta, 8 * j, 0xFF);
3098                 }
3099         }
3100
3101         return 0;
3102 }
3103
3104 static int
3105 txgbe_add_rar(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
3106                                 uint32_t index, uint32_t pool)
3107 {
3108         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3109         uint32_t enable_addr = 1;
3110
3111         return txgbe_set_rar(hw, index, mac_addr->addr_bytes,
3112                              pool, enable_addr);
3113 }
3114
3115 static void
3116 txgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
3117 {
3118         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3119
3120         txgbe_clear_rar(hw, index);
3121 }
3122
3123 static int
3124 txgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *addr)
3125 {
3126         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3127
3128         txgbe_remove_rar(dev, 0);
3129         txgbe_add_rar(dev, addr, 0, pci_dev->max_vfs);
3130
3131         return 0;
3132 }
3133
3134 static int
3135 txgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
3136 {
3137         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3138         struct rte_eth_dev_info dev_info;
3139         uint32_t frame_size = mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN;
3140         struct rte_eth_dev_data *dev_data = dev->data;
3141         int ret;
3142
3143         ret = txgbe_dev_info_get(dev, &dev_info);
3144         if (ret != 0)
3145                 return ret;
3146
3147         /* check that mtu is within the allowed range */
3148         if (mtu < RTE_ETHER_MIN_MTU || frame_size > dev_info.max_rx_pktlen)
3149                 return -EINVAL;
3150
3151         /* If device is started, refuse mtu that requires the support of
3152          * scattered packets when this feature has not been enabled before.
3153          */
3154         if (dev_data->dev_started && !dev_data->scattered_rx &&
3155             (frame_size + 2 * TXGBE_VLAN_TAG_SIZE >
3156              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
3157                 PMD_INIT_LOG(ERR, "Stop port first.");
3158                 return -EINVAL;
3159         }
3160
3161         /* update max frame size */
3162         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
3163
3164         if (hw->mode)
3165                 wr32m(hw, TXGBE_FRMSZ, TXGBE_FRMSZ_MAX_MASK,
3166                         TXGBE_FRAME_SIZE_MAX);
3167         else
3168                 wr32m(hw, TXGBE_FRMSZ, TXGBE_FRMSZ_MAX_MASK,
3169                         TXGBE_FRMSZ_MAX(frame_size));
3170
3171         return 0;
3172 }
3173
3174 static uint32_t
3175 txgbe_uta_vector(struct txgbe_hw *hw, struct rte_ether_addr *uc_addr)
3176 {
3177         uint32_t vector = 0;
3178
3179         switch (hw->mac.mc_filter_type) {
3180         case 0:   /* use bits [47:36] of the address */
3181                 vector = ((uc_addr->addr_bytes[4] >> 4) |
3182                         (((uint16_t)uc_addr->addr_bytes[5]) << 4));
3183                 break;
3184         case 1:   /* use bits [46:35] of the address */
3185                 vector = ((uc_addr->addr_bytes[4] >> 3) |
3186                         (((uint16_t)uc_addr->addr_bytes[5]) << 5));
3187                 break;
3188         case 2:   /* use bits [45:34] of the address */
3189                 vector = ((uc_addr->addr_bytes[4] >> 2) |
3190                         (((uint16_t)uc_addr->addr_bytes[5]) << 6));
3191                 break;
3192         case 3:   /* use bits [43:32] of the address */
3193                 vector = ((uc_addr->addr_bytes[4]) |
3194                         (((uint16_t)uc_addr->addr_bytes[5]) << 8));
3195                 break;
3196         default:  /* Invalid mc_filter_type */
3197                 break;
3198         }
3199
3200         /* vector can only be 12-bits or boundary will be exceeded */
3201         vector &= 0xFFF;
3202         return vector;
3203 }
3204
3205 static int
3206 txgbe_uc_hash_table_set(struct rte_eth_dev *dev,
3207                         struct rte_ether_addr *mac_addr, uint8_t on)
3208 {
3209         uint32_t vector;
3210         uint32_t uta_idx;
3211         uint32_t reg_val;
3212         uint32_t uta_mask;
3213         uint32_t psrctl;
3214
3215         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3216         struct txgbe_uta_info *uta_info = TXGBE_DEV_UTA_INFO(dev);
3217
3218         /* The UTA table only exists on pf hardware */
3219         if (hw->mac.type < txgbe_mac_raptor)
3220                 return -ENOTSUP;
3221
3222         vector = txgbe_uta_vector(hw, mac_addr);
3223         uta_idx = (vector >> 5) & 0x7F;
3224         uta_mask = 0x1UL << (vector & 0x1F);
3225
3226         if (!!on == !!(uta_info->uta_shadow[uta_idx] & uta_mask))
3227                 return 0;
3228
3229         reg_val = rd32(hw, TXGBE_UCADDRTBL(uta_idx));
3230         if (on) {
3231                 uta_info->uta_in_use++;
3232                 reg_val |= uta_mask;
3233                 uta_info->uta_shadow[uta_idx] |= uta_mask;
3234         } else {
3235                 uta_info->uta_in_use--;
3236                 reg_val &= ~uta_mask;
3237                 uta_info->uta_shadow[uta_idx] &= ~uta_mask;
3238         }
3239
3240         wr32(hw, TXGBE_UCADDRTBL(uta_idx), reg_val);
3241
3242         psrctl = rd32(hw, TXGBE_PSRCTL);
3243         if (uta_info->uta_in_use > 0)
3244                 psrctl |= TXGBE_PSRCTL_UCHFENA;
3245         else
3246                 psrctl &= ~TXGBE_PSRCTL_UCHFENA;
3247
3248         psrctl &= ~TXGBE_PSRCTL_ADHF12_MASK;
3249         psrctl |= TXGBE_PSRCTL_ADHF12(hw->mac.mc_filter_type);
3250         wr32(hw, TXGBE_PSRCTL, psrctl);
3251
3252         return 0;
3253 }
3254
3255 static int
3256 txgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
3257 {
3258         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3259         struct txgbe_uta_info *uta_info = TXGBE_DEV_UTA_INFO(dev);
3260         uint32_t psrctl;
3261         int i;
3262
3263         /* The UTA table only exists on pf hardware */
3264         if (hw->mac.type < txgbe_mac_raptor)
3265                 return -ENOTSUP;
3266
3267         if (on) {
3268                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
3269                         uta_info->uta_shadow[i] = ~0;
3270                         wr32(hw, TXGBE_UCADDRTBL(i), ~0);
3271                 }
3272         } else {
3273                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
3274                         uta_info->uta_shadow[i] = 0;
3275                         wr32(hw, TXGBE_UCADDRTBL(i), 0);
3276                 }
3277         }
3278
3279         psrctl = rd32(hw, TXGBE_PSRCTL);
3280         if (on)
3281                 psrctl |= TXGBE_PSRCTL_UCHFENA;
3282         else
3283                 psrctl &= ~TXGBE_PSRCTL_UCHFENA;
3284
3285         psrctl &= ~TXGBE_PSRCTL_ADHF12_MASK;
3286         psrctl |= TXGBE_PSRCTL_ADHF12(hw->mac.mc_filter_type);
3287         wr32(hw, TXGBE_PSRCTL, psrctl);
3288
3289         return 0;
3290 }
3291
3292 uint32_t
3293 txgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
3294 {
3295         uint32_t new_val = orig_val;
3296
3297         if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
3298                 new_val |= TXGBE_POOLETHCTL_UTA;
3299         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
3300                 new_val |= TXGBE_POOLETHCTL_MCHA;
3301         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
3302                 new_val |= TXGBE_POOLETHCTL_UCHA;
3303         if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
3304                 new_val |= TXGBE_POOLETHCTL_BCA;
3305         if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
3306                 new_val |= TXGBE_POOLETHCTL_MCP;
3307
3308         return new_val;
3309 }
3310
3311 static int
3312 txgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
3313 {
3314         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3315         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3316         uint32_t mask;
3317         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3318
3319         if (queue_id < 32) {
3320                 mask = rd32(hw, TXGBE_IMS(0));
3321                 mask &= (1 << queue_id);
3322                 wr32(hw, TXGBE_IMS(0), mask);
3323         } else if (queue_id < 64) {
3324                 mask = rd32(hw, TXGBE_IMS(1));
3325                 mask &= (1 << (queue_id - 32));
3326                 wr32(hw, TXGBE_IMS(1), mask);
3327         }
3328         rte_intr_enable(intr_handle);
3329
3330         return 0;
3331 }
3332
3333 static int
3334 txgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
3335 {
3336         uint32_t mask;
3337         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3338
3339         if (queue_id < 32) {
3340                 mask = rd32(hw, TXGBE_IMS(0));
3341                 mask &= ~(1 << queue_id);
3342                 wr32(hw, TXGBE_IMS(0), mask);
3343         } else if (queue_id < 64) {
3344                 mask = rd32(hw, TXGBE_IMS(1));
3345                 mask &= ~(1 << (queue_id - 32));
3346                 wr32(hw, TXGBE_IMS(1), mask);
3347         }
3348
3349         return 0;
3350 }
3351
3352 /**
3353  * set the IVAR registers, mapping interrupt causes to vectors
3354  * @param hw
3355  *  pointer to txgbe_hw struct
3356  * @direction
3357  *  0 for Rx, 1 for Tx, -1 for other causes
3358  * @queue
3359  *  queue to map the corresponding interrupt to
3360  * @msix_vector
3361  *  the vector to map to the corresponding queue
3362  */
3363 void
3364 txgbe_set_ivar_map(struct txgbe_hw *hw, int8_t direction,
3365                    uint8_t queue, uint8_t msix_vector)
3366 {
3367         uint32_t tmp, idx;
3368
3369         if (direction == -1) {
3370                 /* other causes */
3371                 msix_vector |= TXGBE_IVARMISC_VLD;
3372                 idx = 0;
3373                 tmp = rd32(hw, TXGBE_IVARMISC);
3374                 tmp &= ~(0xFF << idx);
3375                 tmp |= (msix_vector << idx);
3376                 wr32(hw, TXGBE_IVARMISC, tmp);
3377         } else {
3378                 /* rx or tx causes */
3379                 /* Workround for ICR lost */
3380                 idx = ((16 * (queue & 1)) + (8 * direction));
3381                 tmp = rd32(hw, TXGBE_IVAR(queue >> 1));
3382                 tmp &= ~(0xFF << idx);
3383                 tmp |= (msix_vector << idx);
3384                 wr32(hw, TXGBE_IVAR(queue >> 1), tmp);
3385         }
3386 }
3387
3388 /**
3389  * Sets up the hardware to properly generate MSI-X interrupts
3390  * @hw
3391  *  board private structure
3392  */
3393 static void
3394 txgbe_configure_msix(struct rte_eth_dev *dev)
3395 {
3396         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3397         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3398         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3399         uint32_t queue_id, base = TXGBE_MISC_VEC_ID;
3400         uint32_t vec = TXGBE_MISC_VEC_ID;
3401         uint32_t gpie;
3402
3403         /* won't configure msix register if no mapping is done
3404          * between intr vector and event fd
3405          * but if misx has been enabled already, need to configure
3406          * auto clean, auto mask and throttling.
3407          */
3408         gpie = rd32(hw, TXGBE_GPIE);
3409         if (!rte_intr_dp_is_en(intr_handle) &&
3410             !(gpie & TXGBE_GPIE_MSIX))
3411                 return;
3412
3413         if (rte_intr_allow_others(intr_handle)) {
3414                 base = TXGBE_RX_VEC_START;
3415                 vec = base;
3416         }
3417
3418         /* setup GPIE for MSI-x mode */
3419         gpie = rd32(hw, TXGBE_GPIE);
3420         gpie |= TXGBE_GPIE_MSIX;
3421         wr32(hw, TXGBE_GPIE, gpie);
3422
3423         /* Populate the IVAR table and set the ITR values to the
3424          * corresponding register.
3425          */
3426         if (rte_intr_dp_is_en(intr_handle)) {
3427                 for (queue_id = 0; queue_id < dev->data->nb_rx_queues;
3428                         queue_id++) {
3429                         /* by default, 1:1 mapping */
3430                         txgbe_set_ivar_map(hw, 0, queue_id, vec);
3431                         intr_handle->intr_vec[queue_id] = vec;
3432                         if (vec < base + intr_handle->nb_efd - 1)
3433                                 vec++;
3434                 }
3435
3436                 txgbe_set_ivar_map(hw, -1, 1, TXGBE_MISC_VEC_ID);
3437         }
3438         wr32(hw, TXGBE_ITR(TXGBE_MISC_VEC_ID),
3439                         TXGBE_ITR_IVAL_10G(TXGBE_QUEUE_ITR_INTERVAL_DEFAULT)
3440                         | TXGBE_ITR_WRDSA);
3441 }
3442
3443 int
3444 txgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
3445                            uint16_t queue_idx, uint16_t tx_rate)
3446 {
3447         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3448         uint32_t bcnrc_val;
3449
3450         if (queue_idx >= hw->mac.max_tx_queues)
3451                 return -EINVAL;
3452
3453         if (tx_rate != 0) {
3454                 bcnrc_val = TXGBE_ARBTXRATE_MAX(tx_rate);
3455                 bcnrc_val |= TXGBE_ARBTXRATE_MIN(tx_rate / 2);
3456         } else {
3457                 bcnrc_val = 0;
3458         }
3459
3460         /*
3461          * Set global transmit compensation time to the MMW_SIZE in ARBTXMMW
3462          * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported.
3463          */
3464         wr32(hw, TXGBE_ARBTXMMW, 0x14);
3465
3466         /* Set ARBTXRATE of queue X */
3467         wr32(hw, TXGBE_ARBPOOLIDX, queue_idx);
3468         wr32(hw, TXGBE_ARBTXRATE, bcnrc_val);
3469         txgbe_flush(hw);
3470
3471         return 0;
3472 }
3473
3474 static u8 *
3475 txgbe_dev_addr_list_itr(__rte_unused struct txgbe_hw *hw,
3476                         u8 **mc_addr_ptr, u32 *vmdq)
3477 {
3478         u8 *mc_addr;
3479
3480         *vmdq = 0;
3481         mc_addr = *mc_addr_ptr;
3482         *mc_addr_ptr = (mc_addr + sizeof(struct rte_ether_addr));
3483         return mc_addr;
3484 }
3485
3486 int
3487 txgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
3488                           struct rte_ether_addr *mc_addr_set,
3489                           uint32_t nb_mc_addr)
3490 {
3491         struct txgbe_hw *hw;
3492         u8 *mc_addr_list;
3493
3494         hw = TXGBE_DEV_HW(dev);
3495         mc_addr_list = (u8 *)mc_addr_set;
3496         return txgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
3497                                          txgbe_dev_addr_list_itr, TRUE);
3498 }
3499
3500 static uint64_t
3501 txgbe_read_systime_cyclecounter(struct rte_eth_dev *dev)
3502 {
3503         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3504         uint64_t systime_cycles;
3505
3506         systime_cycles = (uint64_t)rd32(hw, TXGBE_TSTIMEL);
3507         systime_cycles |= (uint64_t)rd32(hw, TXGBE_TSTIMEH) << 32;
3508
3509         return systime_cycles;
3510 }
3511
3512 static uint64_t
3513 txgbe_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
3514 {
3515         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3516         uint64_t rx_tstamp_cycles;
3517
3518         /* TSRXSTMPL stores ns and TSRXSTMPH stores seconds. */
3519         rx_tstamp_cycles = (uint64_t)rd32(hw, TXGBE_TSRXSTMPL);
3520         rx_tstamp_cycles |= (uint64_t)rd32(hw, TXGBE_TSRXSTMPH) << 32;
3521
3522         return rx_tstamp_cycles;
3523 }
3524
3525 static uint64_t
3526 txgbe_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
3527 {
3528         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3529         uint64_t tx_tstamp_cycles;
3530
3531         /* TSTXSTMPL stores ns and TSTXSTMPH stores seconds. */
3532         tx_tstamp_cycles = (uint64_t)rd32(hw, TXGBE_TSTXSTMPL);
3533         tx_tstamp_cycles |= (uint64_t)rd32(hw, TXGBE_TSTXSTMPH) << 32;
3534
3535         return tx_tstamp_cycles;
3536 }
3537
3538 static void
3539 txgbe_start_timecounters(struct rte_eth_dev *dev)
3540 {
3541         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3542         struct txgbe_adapter *adapter = TXGBE_DEV_ADAPTER(dev);
3543         struct rte_eth_link link;
3544         uint32_t incval = 0;
3545         uint32_t shift = 0;
3546
3547         /* Get current link speed. */
3548         txgbe_dev_link_update(dev, 1);
3549         rte_eth_linkstatus_get(dev, &link);
3550
3551         switch (link.link_speed) {
3552         case ETH_SPEED_NUM_100M:
3553                 incval = TXGBE_INCVAL_100;
3554                 shift = TXGBE_INCVAL_SHIFT_100;
3555                 break;
3556         case ETH_SPEED_NUM_1G:
3557                 incval = TXGBE_INCVAL_1GB;
3558                 shift = TXGBE_INCVAL_SHIFT_1GB;
3559                 break;
3560         case ETH_SPEED_NUM_10G:
3561         default:
3562                 incval = TXGBE_INCVAL_10GB;
3563                 shift = TXGBE_INCVAL_SHIFT_10GB;
3564                 break;
3565         }
3566
3567         wr32(hw, TXGBE_TSTIMEINC, TXGBE_TSTIMEINC_VP(incval, 2));
3568
3569         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
3570         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3571         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
3572
3573         adapter->systime_tc.cc_mask = TXGBE_CYCLECOUNTER_MASK;
3574         adapter->systime_tc.cc_shift = shift;
3575         adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
3576
3577         adapter->rx_tstamp_tc.cc_mask = TXGBE_CYCLECOUNTER_MASK;
3578         adapter->rx_tstamp_tc.cc_shift = shift;
3579         adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3580
3581         adapter->tx_tstamp_tc.cc_mask = TXGBE_CYCLECOUNTER_MASK;
3582         adapter->tx_tstamp_tc.cc_shift = shift;
3583         adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
3584 }
3585
3586 static int
3587 txgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
3588 {
3589         struct txgbe_adapter *adapter = TXGBE_DEV_ADAPTER(dev);
3590
3591         adapter->systime_tc.nsec += delta;
3592         adapter->rx_tstamp_tc.nsec += delta;
3593         adapter->tx_tstamp_tc.nsec += delta;
3594
3595         return 0;
3596 }
3597
3598 static int
3599 txgbe_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
3600 {
3601         uint64_t ns;
3602         struct txgbe_adapter *adapter = TXGBE_DEV_ADAPTER(dev);
3603
3604         ns = rte_timespec_to_ns(ts);
3605         /* Set the timecounters to a new value. */
3606         adapter->systime_tc.nsec = ns;
3607         adapter->rx_tstamp_tc.nsec = ns;
3608         adapter->tx_tstamp_tc.nsec = ns;
3609
3610         return 0;
3611 }
3612
3613 static int
3614 txgbe_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
3615 {
3616         uint64_t ns, systime_cycles;
3617         struct txgbe_adapter *adapter = TXGBE_DEV_ADAPTER(dev);
3618
3619         systime_cycles = txgbe_read_systime_cyclecounter(dev);
3620         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
3621         *ts = rte_ns_to_timespec(ns);
3622
3623         return 0;
3624 }
3625
3626 static int
3627 txgbe_timesync_enable(struct rte_eth_dev *dev)
3628 {
3629         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3630         uint32_t tsync_ctl;
3631
3632         /* Stop the timesync system time. */
3633         wr32(hw, TXGBE_TSTIMEINC, 0x0);
3634         /* Reset the timesync system time value. */
3635         wr32(hw, TXGBE_TSTIMEL, 0x0);
3636         wr32(hw, TXGBE_TSTIMEH, 0x0);
3637
3638         txgbe_start_timecounters(dev);
3639
3640         /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
3641         wr32(hw, TXGBE_ETFLT(TXGBE_ETF_ID_1588),
3642                 RTE_ETHER_TYPE_1588 | TXGBE_ETFLT_ENA | TXGBE_ETFLT_1588);
3643
3644         /* Enable timestamping of received PTP packets. */
3645         tsync_ctl = rd32(hw, TXGBE_TSRXCTL);
3646         tsync_ctl |= TXGBE_TSRXCTL_ENA;
3647         wr32(hw, TXGBE_TSRXCTL, tsync_ctl);
3648
3649         /* Enable timestamping of transmitted PTP packets. */
3650         tsync_ctl = rd32(hw, TXGBE_TSTXCTL);
3651         tsync_ctl |= TXGBE_TSTXCTL_ENA;
3652         wr32(hw, TXGBE_TSTXCTL, tsync_ctl);
3653
3654         txgbe_flush(hw);
3655
3656         return 0;
3657 }
3658
3659 static int
3660 txgbe_timesync_disable(struct rte_eth_dev *dev)
3661 {
3662         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3663         uint32_t tsync_ctl;
3664
3665         /* Disable timestamping of transmitted PTP packets. */
3666         tsync_ctl = rd32(hw, TXGBE_TSTXCTL);
3667         tsync_ctl &= ~TXGBE_TSTXCTL_ENA;
3668         wr32(hw, TXGBE_TSTXCTL, tsync_ctl);
3669
3670         /* Disable timestamping of received PTP packets. */
3671         tsync_ctl = rd32(hw, TXGBE_TSRXCTL);
3672         tsync_ctl &= ~TXGBE_TSRXCTL_ENA;
3673         wr32(hw, TXGBE_TSRXCTL, tsync_ctl);
3674
3675         /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
3676         wr32(hw, TXGBE_ETFLT(TXGBE_ETF_ID_1588), 0);
3677
3678         /* Stop incrementating the System Time registers. */
3679         wr32(hw, TXGBE_TSTIMEINC, 0);
3680
3681         return 0;
3682 }
3683
3684 static int
3685 txgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
3686                                  struct timespec *timestamp,
3687                                  uint32_t flags __rte_unused)
3688 {
3689         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3690         struct txgbe_adapter *adapter = TXGBE_DEV_ADAPTER(dev);
3691         uint32_t tsync_rxctl;
3692         uint64_t rx_tstamp_cycles;
3693         uint64_t ns;
3694
3695         tsync_rxctl = rd32(hw, TXGBE_TSRXCTL);
3696         if ((tsync_rxctl & TXGBE_TSRXCTL_VLD) == 0)
3697                 return -EINVAL;
3698
3699         rx_tstamp_cycles = txgbe_read_rx_tstamp_cyclecounter(dev);
3700         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
3701         *timestamp = rte_ns_to_timespec(ns);
3702
3703         return  0;
3704 }
3705
3706 static int
3707 txgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
3708                                  struct timespec *timestamp)
3709 {
3710         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3711         struct txgbe_adapter *adapter = TXGBE_DEV_ADAPTER(dev);
3712         uint32_t tsync_txctl;
3713         uint64_t tx_tstamp_cycles;
3714         uint64_t ns;
3715
3716         tsync_txctl = rd32(hw, TXGBE_TSTXCTL);
3717         if ((tsync_txctl & TXGBE_TSTXCTL_VLD) == 0)
3718                 return -EINVAL;
3719
3720         tx_tstamp_cycles = txgbe_read_tx_tstamp_cyclecounter(dev);
3721         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
3722         *timestamp = rte_ns_to_timespec(ns);
3723
3724         return 0;
3725 }
3726
3727 static int
3728 txgbe_get_reg_length(struct rte_eth_dev *dev __rte_unused)
3729 {
3730         int count = 0;
3731         int g_ind = 0;
3732         const struct reg_info *reg_group;
3733         const struct reg_info **reg_set = txgbe_regs_others;
3734
3735         while ((reg_group = reg_set[g_ind++]))
3736                 count += txgbe_regs_group_count(reg_group);
3737
3738         return count;
3739 }
3740
3741 static int
3742 txgbe_get_regs(struct rte_eth_dev *dev,
3743               struct rte_dev_reg_info *regs)
3744 {
3745         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3746         uint32_t *data = regs->data;
3747         int g_ind = 0;
3748         int count = 0;
3749         const struct reg_info *reg_group;
3750         const struct reg_info **reg_set = txgbe_regs_others;
3751
3752         if (data == NULL) {
3753                 regs->length = txgbe_get_reg_length(dev);
3754                 regs->width = sizeof(uint32_t);
3755                 return 0;
3756         }
3757
3758         /* Support only full register dump */
3759         if (regs->length == 0 ||
3760             regs->length == (uint32_t)txgbe_get_reg_length(dev)) {
3761                 regs->version = hw->mac.type << 24 |
3762                                 hw->revision_id << 16 |
3763                                 hw->device_id;
3764                 while ((reg_group = reg_set[g_ind++]))
3765                         count += txgbe_read_regs_group(dev, &data[count],
3766                                                       reg_group);
3767                 return 0;
3768         }
3769
3770         return -ENOTSUP;
3771 }
3772
3773 static int
3774 txgbe_get_eeprom_length(struct rte_eth_dev *dev)
3775 {
3776         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3777
3778         /* Return unit is byte count */
3779         return hw->rom.word_size * 2;
3780 }
3781
3782 static int
3783 txgbe_get_eeprom(struct rte_eth_dev *dev,
3784                 struct rte_dev_eeprom_info *in_eeprom)
3785 {
3786         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3787         struct txgbe_rom_info *eeprom = &hw->rom;
3788         uint16_t *data = in_eeprom->data;
3789         int first, length;
3790
3791         first = in_eeprom->offset >> 1;
3792         length = in_eeprom->length >> 1;
3793         if (first > hw->rom.word_size ||
3794             ((first + length) > hw->rom.word_size))
3795                 return -EINVAL;
3796
3797         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
3798
3799         return eeprom->readw_buffer(hw, first, length, data);
3800 }
3801
3802 static int
3803 txgbe_set_eeprom(struct rte_eth_dev *dev,
3804                 struct rte_dev_eeprom_info *in_eeprom)
3805 {
3806         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3807         struct txgbe_rom_info *eeprom = &hw->rom;
3808         uint16_t *data = in_eeprom->data;
3809         int first, length;
3810
3811         first = in_eeprom->offset >> 1;
3812         length = in_eeprom->length >> 1;
3813         if (first > hw->rom.word_size ||
3814             ((first + length) > hw->rom.word_size))
3815                 return -EINVAL;
3816
3817         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
3818
3819         return eeprom->writew_buffer(hw,  first, length, data);
3820 }
3821
3822 static int
3823 txgbe_get_module_info(struct rte_eth_dev *dev,
3824                       struct rte_eth_dev_module_info *modinfo)
3825 {
3826         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3827         uint32_t status;
3828         uint8_t sff8472_rev, addr_mode;
3829         bool page_swap = false;
3830
3831         /* Check whether we support SFF-8472 or not */
3832         status = hw->phy.read_i2c_eeprom(hw,
3833                                              TXGBE_SFF_SFF_8472_COMP,
3834                                              &sff8472_rev);
3835         if (status != 0)
3836                 return -EIO;
3837
3838         /* addressing mode is not supported */
3839         status = hw->phy.read_i2c_eeprom(hw,
3840                                              TXGBE_SFF_SFF_8472_SWAP,
3841                                              &addr_mode);
3842         if (status != 0)
3843                 return -EIO;
3844
3845         if (addr_mode & TXGBE_SFF_ADDRESSING_MODE) {
3846                 PMD_DRV_LOG(ERR,
3847                             "Address change required to access page 0xA2, "
3848                             "but not supported. Please report the module "
3849                             "type to the driver maintainers.");
3850                 page_swap = true;
3851         }
3852
3853         if (sff8472_rev == TXGBE_SFF_SFF_8472_UNSUP || page_swap) {
3854                 /* We have a SFP, but it does not support SFF-8472 */
3855                 modinfo->type = RTE_ETH_MODULE_SFF_8079;
3856                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
3857         } else {
3858                 /* We have a SFP which supports a revision of SFF-8472. */
3859                 modinfo->type = RTE_ETH_MODULE_SFF_8472;
3860                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
3861         }
3862
3863         return 0;
3864 }
3865
3866 static int
3867 txgbe_get_module_eeprom(struct rte_eth_dev *dev,
3868                         struct rte_dev_eeprom_info *info)
3869 {
3870         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3871         uint32_t status = TXGBE_ERR_PHY_ADDR_INVALID;
3872         uint8_t databyte = 0xFF;
3873         uint8_t *data = info->data;
3874         uint32_t i = 0;
3875
3876         if (info->length == 0)
3877                 return -EINVAL;
3878
3879         for (i = info->offset; i < info->offset + info->length; i++) {
3880                 if (i < RTE_ETH_MODULE_SFF_8079_LEN)
3881                         status = hw->phy.read_i2c_eeprom(hw, i, &databyte);
3882                 else
3883                         status = hw->phy.read_i2c_sff8472(hw, i, &databyte);
3884
3885                 if (status != 0)
3886                         return -EIO;
3887
3888                 data[i - info->offset] = databyte;
3889         }
3890
3891         return 0;
3892 }
3893
3894 bool
3895 txgbe_rss_update_sp(enum txgbe_mac_type mac_type)
3896 {
3897         switch (mac_type) {
3898         case txgbe_mac_raptor:
3899                 return 1;
3900         default:
3901                 return 0;
3902         }
3903 }
3904
3905 static int
3906 txgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
3907                         struct rte_eth_dcb_info *dcb_info)
3908 {
3909         struct txgbe_dcb_config *dcb_config = TXGBE_DEV_DCB_CONFIG(dev);
3910         struct txgbe_dcb_tc_config *tc;
3911         struct rte_eth_dcb_tc_queue_mapping *tc_queue;
3912         uint8_t nb_tcs;
3913         uint8_t i, j;
3914
3915         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
3916                 dcb_info->nb_tcs = dcb_config->num_tcs.pg_tcs;
3917         else
3918                 dcb_info->nb_tcs = 1;
3919
3920         tc_queue = &dcb_info->tc_queue;
3921         nb_tcs = dcb_info->nb_tcs;
3922
3923         if (dcb_config->vt_mode) { /* vt is enabled */
3924                 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
3925                                 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
3926                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
3927                         dcb_info->prio_tc[i] = vmdq_rx_conf->dcb_tc[i];
3928                 if (RTE_ETH_DEV_SRIOV(dev).active > 0) {
3929                         for (j = 0; j < nb_tcs; j++) {
3930                                 tc_queue->tc_rxq[0][j].base = j;
3931                                 tc_queue->tc_rxq[0][j].nb_queue = 1;
3932                                 tc_queue->tc_txq[0][j].base = j;
3933                                 tc_queue->tc_txq[0][j].nb_queue = 1;
3934                         }
3935                 } else {
3936                         for (i = 0; i < vmdq_rx_conf->nb_queue_pools; i++) {
3937                                 for (j = 0; j < nb_tcs; j++) {
3938                                         tc_queue->tc_rxq[i][j].base =
3939                                                 i * nb_tcs + j;
3940                                         tc_queue->tc_rxq[i][j].nb_queue = 1;
3941                                         tc_queue->tc_txq[i][j].base =
3942                                                 i * nb_tcs + j;
3943                                         tc_queue->tc_txq[i][j].nb_queue = 1;
3944                                 }
3945                         }
3946                 }
3947         } else { /* vt is disabled */
3948                 struct rte_eth_dcb_rx_conf *rx_conf =
3949                                 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
3950                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
3951                         dcb_info->prio_tc[i] = rx_conf->dcb_tc[i];
3952                 if (dcb_info->nb_tcs == ETH_4_TCS) {
3953                         for (i = 0; i < dcb_info->nb_tcs; i++) {
3954                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 32;
3955                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
3956                         }
3957                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
3958                         dcb_info->tc_queue.tc_txq[0][1].base = 64;
3959                         dcb_info->tc_queue.tc_txq[0][2].base = 96;
3960                         dcb_info->tc_queue.tc_txq[0][3].base = 112;
3961                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 64;
3962                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
3963                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
3964                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
3965                 } else if (dcb_info->nb_tcs == ETH_8_TCS) {
3966                         for (i = 0; i < dcb_info->nb_tcs; i++) {
3967                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 16;
3968                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
3969                         }
3970                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
3971                         dcb_info->tc_queue.tc_txq[0][1].base = 32;
3972                         dcb_info->tc_queue.tc_txq[0][2].base = 64;
3973                         dcb_info->tc_queue.tc_txq[0][3].base = 80;
3974                         dcb_info->tc_queue.tc_txq[0][4].base = 96;
3975                         dcb_info->tc_queue.tc_txq[0][5].base = 104;
3976                         dcb_info->tc_queue.tc_txq[0][6].base = 112;
3977                         dcb_info->tc_queue.tc_txq[0][7].base = 120;
3978                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 32;
3979                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
3980                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
3981                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
3982                         dcb_info->tc_queue.tc_txq[0][4].nb_queue = 8;
3983                         dcb_info->tc_queue.tc_txq[0][5].nb_queue = 8;
3984                         dcb_info->tc_queue.tc_txq[0][6].nb_queue = 8;
3985                         dcb_info->tc_queue.tc_txq[0][7].nb_queue = 8;
3986                 }
3987         }
3988         for (i = 0; i < dcb_info->nb_tcs; i++) {
3989                 tc = &dcb_config->tc_config[i];
3990                 dcb_info->tc_bws[i] = tc->path[TXGBE_DCB_TX_CONFIG].bwg_percent;
3991         }
3992         return 0;
3993 }
3994
3995 static const struct eth_dev_ops txgbe_eth_dev_ops = {
3996         .dev_configure              = txgbe_dev_configure,
3997         .dev_infos_get              = txgbe_dev_info_get,
3998         .dev_start                  = txgbe_dev_start,
3999         .dev_stop                   = txgbe_dev_stop,
4000         .dev_set_link_up            = txgbe_dev_set_link_up,
4001         .dev_set_link_down          = txgbe_dev_set_link_down,
4002         .dev_close                  = txgbe_dev_close,
4003         .dev_reset                  = txgbe_dev_reset,
4004         .promiscuous_enable         = txgbe_dev_promiscuous_enable,
4005         .promiscuous_disable        = txgbe_dev_promiscuous_disable,
4006         .allmulticast_enable        = txgbe_dev_allmulticast_enable,
4007         .allmulticast_disable       = txgbe_dev_allmulticast_disable,
4008         .link_update                = txgbe_dev_link_update,
4009         .stats_get                  = txgbe_dev_stats_get,
4010         .xstats_get                 = txgbe_dev_xstats_get,
4011         .xstats_get_by_id           = txgbe_dev_xstats_get_by_id,
4012         .stats_reset                = txgbe_dev_stats_reset,
4013         .xstats_reset               = txgbe_dev_xstats_reset,
4014         .xstats_get_names           = txgbe_dev_xstats_get_names,
4015         .xstats_get_names_by_id     = txgbe_dev_xstats_get_names_by_id,
4016         .queue_stats_mapping_set    = txgbe_dev_queue_stats_mapping_set,
4017         .fw_version_get             = txgbe_fw_version_get,
4018         .dev_supported_ptypes_get   = txgbe_dev_supported_ptypes_get,
4019         .mtu_set                    = txgbe_dev_mtu_set,
4020         .vlan_filter_set            = txgbe_vlan_filter_set,
4021         .vlan_tpid_set              = txgbe_vlan_tpid_set,
4022         .vlan_offload_set           = txgbe_vlan_offload_set,
4023         .vlan_strip_queue_set       = txgbe_vlan_strip_queue_set,
4024         .rx_queue_start             = txgbe_dev_rx_queue_start,
4025         .rx_queue_stop              = txgbe_dev_rx_queue_stop,
4026         .tx_queue_start             = txgbe_dev_tx_queue_start,
4027         .tx_queue_stop              = txgbe_dev_tx_queue_stop,
4028         .rx_queue_setup             = txgbe_dev_rx_queue_setup,
4029         .rx_queue_intr_enable       = txgbe_dev_rx_queue_intr_enable,
4030         .rx_queue_intr_disable      = txgbe_dev_rx_queue_intr_disable,
4031         .rx_queue_release           = txgbe_dev_rx_queue_release,
4032         .tx_queue_setup             = txgbe_dev_tx_queue_setup,
4033         .tx_queue_release           = txgbe_dev_tx_queue_release,
4034         .dev_led_on                 = txgbe_dev_led_on,
4035         .dev_led_off                = txgbe_dev_led_off,
4036         .flow_ctrl_get              = txgbe_flow_ctrl_get,
4037         .flow_ctrl_set              = txgbe_flow_ctrl_set,
4038         .priority_flow_ctrl_set     = txgbe_priority_flow_ctrl_set,
4039         .mac_addr_add               = txgbe_add_rar,
4040         .mac_addr_remove            = txgbe_remove_rar,
4041         .mac_addr_set               = txgbe_set_default_mac_addr,
4042         .uc_hash_table_set          = txgbe_uc_hash_table_set,
4043         .uc_all_hash_table_set      = txgbe_uc_all_hash_table_set,
4044         .set_queue_rate_limit       = txgbe_set_queue_rate_limit,
4045         .reta_update                = txgbe_dev_rss_reta_update,
4046         .reta_query                 = txgbe_dev_rss_reta_query,
4047         .rss_hash_update            = txgbe_dev_rss_hash_update,
4048         .rss_hash_conf_get          = txgbe_dev_rss_hash_conf_get,
4049         .set_mc_addr_list           = txgbe_dev_set_mc_addr_list,
4050         .rxq_info_get               = txgbe_rxq_info_get,
4051         .txq_info_get               = txgbe_txq_info_get,
4052         .timesync_enable            = txgbe_timesync_enable,
4053         .timesync_disable           = txgbe_timesync_disable,
4054         .timesync_read_rx_timestamp = txgbe_timesync_read_rx_timestamp,
4055         .timesync_read_tx_timestamp = txgbe_timesync_read_tx_timestamp,
4056         .get_reg                    = txgbe_get_regs,
4057         .get_eeprom_length          = txgbe_get_eeprom_length,
4058         .get_eeprom                 = txgbe_get_eeprom,
4059         .set_eeprom                 = txgbe_set_eeprom,
4060         .get_module_info            = txgbe_get_module_info,
4061         .get_module_eeprom          = txgbe_get_module_eeprom,
4062         .get_dcb_info               = txgbe_dev_get_dcb_info,
4063         .timesync_adjust_time       = txgbe_timesync_adjust_time,
4064         .timesync_read_time         = txgbe_timesync_read_time,
4065         .timesync_write_time        = txgbe_timesync_write_time,
4066 };
4067
4068 RTE_PMD_REGISTER_PCI(net_txgbe, rte_txgbe_pmd);
4069 RTE_PMD_REGISTER_PCI_TABLE(net_txgbe, pci_id_txgbe_map);
4070 RTE_PMD_REGISTER_KMOD_DEP(net_txgbe, "* igb_uio | uio_pci_generic | vfio-pci");
4071
4072 RTE_LOG_REGISTER(txgbe_logtype_init, pmd.net.txgbe.init, NOTICE);
4073 RTE_LOG_REGISTER(txgbe_logtype_driver, pmd.net.txgbe.driver, NOTICE);
4074
4075 #ifdef RTE_LIBRTE_TXGBE_DEBUG_RX
4076         RTE_LOG_REGISTER(txgbe_logtype_rx, pmd.net.txgbe.rx, DEBUG);
4077 #endif
4078 #ifdef RTE_LIBRTE_TXGBE_DEBUG_TX
4079         RTE_LOG_REGISTER(txgbe_logtype_tx, pmd.net.txgbe.tx, DEBUG);
4080 #endif
4081
4082 #ifdef RTE_LIBRTE_TXGBE_DEBUG_TX_FREE
4083         RTE_LOG_REGISTER(txgbe_logtype_tx_free, pmd.net.txgbe.tx_free, DEBUG);
4084 #endif