drivers/net/txgbe/txgbe_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2015-2020
   3  */
   4
   5 #include <stdio.h>
   6 #include <errno.h>
   7 #include <stdint.h>
   8 #include <string.h>
   9 #include <rte_common.h>
  10 #include <rte_ethdev_pci.h>
  11
  12 #include <rte_interrupts.h>
  13 #include <rte_log.h>
  14 #include <rte_debug.h>
  15 #include <rte_pci.h>
  16 #include <rte_memory.h>
  17 #include <rte_eal.h>
  18 #include <rte_alarm.h>
  19
  20 #include "txgbe_logs.h"
  21 #include "base/txgbe.h"
  22 #include "txgbe_ethdev.h"
  23 #include "txgbe_rxtx.h"
  24 #include "txgbe_regs_group.h"
  25
  26 static const struct reg_info txgbe_regs_general[] = {
  27         {TXGBE_RST, 1, 1, "TXGBE_RST"},
  28         {TXGBE_STAT, 1, 1, "TXGBE_STAT"},
  29         {TXGBE_PORTCTL, 1, 1, "TXGBE_PORTCTL"},
  30         {TXGBE_SDP, 1, 1, "TXGBE_SDP"},
  31         {TXGBE_SDPCTL, 1, 1, "TXGBE_SDPCTL"},
  32         {TXGBE_LEDCTL, 1, 1, "TXGBE_LEDCTL"},
  33         {0, 0, 0, ""}
  34 };
  35
  36 static const struct reg_info txgbe_regs_nvm[] = {
  37         {0, 0, 0, ""}
  38 };
  39
  40 static const struct reg_info txgbe_regs_interrupt[] = {
  41         {0, 0, 0, ""}
  42 };
  43
  44 static const struct reg_info txgbe_regs_fctl_others[] = {
  45         {0, 0, 0, ""}
  46 };
  47
  48 static const struct reg_info txgbe_regs_rxdma[] = {
  49         {0, 0, 0, ""}
  50 };
  51
  52 static const struct reg_info txgbe_regs_rx[] = {
  53         {0, 0, 0, ""}
  54 };
  55
  56 static struct reg_info txgbe_regs_tx[] = {
  57         {0, 0, 0, ""}
  58 };
  59
  60 static const struct reg_info txgbe_regs_wakeup[] = {
  61         {0, 0, 0, ""}
  62 };
  63
  64 static const struct reg_info txgbe_regs_dcb[] = {
  65         {0, 0, 0, ""}
  66 };
  67
  68 static const struct reg_info txgbe_regs_mac[] = {
  69         {0, 0, 0, ""}
  70 };
  71
  72 static const struct reg_info txgbe_regs_diagnostic[] = {
  73         {0, 0, 0, ""},
  74 };
  75
  76 /* PF registers */
  77 static const struct reg_info *txgbe_regs_others[] = {
  78                                 txgbe_regs_general,
  79                                 txgbe_regs_nvm,
  80                                 txgbe_regs_interrupt,
  81                                 txgbe_regs_fctl_others,
  82                                 txgbe_regs_rxdma,
  83                                 txgbe_regs_rx,
  84                                 txgbe_regs_tx,
  85                                 txgbe_regs_wakeup,
  86                                 txgbe_regs_dcb,
  87                                 txgbe_regs_mac,
  88                                 txgbe_regs_diagnostic,
  89                                 NULL};
  90
  91 static int txgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev);
  92 static int txgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev);
  93 static int  txgbe_dev_set_link_up(struct rte_eth_dev *dev);
  94 static int  txgbe_dev_set_link_down(struct rte_eth_dev *dev);
  95 static int txgbe_dev_close(struct rte_eth_dev *dev);
  96 static int txgbe_dev_link_update(struct rte_eth_dev *dev,
  97                                 int wait_to_complete);
  98 static int txgbe_dev_stats_reset(struct rte_eth_dev *dev);
  99 static void txgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
 100 static void txgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev,
 101                                         uint16_t queue);
 102
 103 static void txgbe_dev_link_status_print(struct rte_eth_dev *dev);
 104 static int txgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on);
 105 static int txgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev);
 106 static int txgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
 107 static int txgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
 108 static int txgbe_dev_interrupt_action(struct rte_eth_dev *dev,
 109                                       struct rte_intr_handle *handle);
 110 static void txgbe_dev_interrupt_handler(void *param);
 111 static void txgbe_dev_interrupt_delayed_handler(void *param);
 112 static void txgbe_configure_msix(struct rte_eth_dev *dev);
 113
 114 static int txgbe_filter_restore(struct rte_eth_dev *dev);
 115 static void txgbe_l2_tunnel_conf(struct rte_eth_dev *dev);
 116
 117 #define TXGBE_SET_HWSTRIP(h, q) do {\
 118                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 119                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 120                 (h)->bitmap[idx] |= 1 << bit;\
 121         } while (0)
 122
 123 #define TXGBE_CLEAR_HWSTRIP(h, q) do {\
 124                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 125                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 126                 (h)->bitmap[idx] &= ~(1 << bit);\
 127         } while (0)
 128
 129 #define TXGBE_GET_HWSTRIP(h, q, r) do {\
 130                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 131                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 132                 (r) = (h)->bitmap[idx] >> bit & 1;\
 133         } while (0)
 134
 135 /*
 136  * The set of PCI devices this driver supports
 137  */
 138 static const struct rte_pci_id pci_id_txgbe_map[] = {
 139         { RTE_PCI_DEVICE(PCI_VENDOR_ID_WANGXUN, TXGBE_DEV_ID_RAPTOR_SFP) },
 140         { RTE_PCI_DEVICE(PCI_VENDOR_ID_WANGXUN, TXGBE_DEV_ID_WX1820_SFP) },
 141         { .vendor_id = 0, /* sentinel */ },
 142 };
 143
 144 static const struct rte_eth_desc_lim rx_desc_lim = {
 145         .nb_max = TXGBE_RING_DESC_MAX,
 146         .nb_min = TXGBE_RING_DESC_MIN,
 147         .nb_align = TXGBE_RXD_ALIGN,
 148 };
 149
 150 static const struct rte_eth_desc_lim tx_desc_lim = {
 151         .nb_max = TXGBE_RING_DESC_MAX,
 152         .nb_min = TXGBE_RING_DESC_MIN,
 153         .nb_align = TXGBE_TXD_ALIGN,
 154         .nb_seg_max = TXGBE_TX_MAX_SEG,
 155         .nb_mtu_seg_max = TXGBE_TX_MAX_SEG,
 156 };
 157
 158 static const struct eth_dev_ops txgbe_eth_dev_ops;
 159
 160 #define HW_XSTAT(m) {#m, offsetof(struct txgbe_hw_stats, m)}
 161 #define HW_XSTAT_NAME(m, n) {n, offsetof(struct txgbe_hw_stats, m)}
 162 static const struct rte_txgbe_xstats_name_off rte_txgbe_stats_strings[] = {
 163         /* MNG RxTx */
 164         HW_XSTAT(mng_bmc2host_packets),
 165         HW_XSTAT(mng_host2bmc_packets),
 166         /* Basic RxTx */
 167         HW_XSTAT(rx_packets),
 168         HW_XSTAT(tx_packets),
 169         HW_XSTAT(rx_bytes),
 170         HW_XSTAT(tx_bytes),
 171         HW_XSTAT(rx_total_bytes),
 172         HW_XSTAT(rx_total_packets),
 173         HW_XSTAT(tx_total_packets),
 174         HW_XSTAT(rx_total_missed_packets),
 175         HW_XSTAT(rx_broadcast_packets),
 176         HW_XSTAT(rx_multicast_packets),
 177         HW_XSTAT(rx_management_packets),
 178         HW_XSTAT(tx_management_packets),
 179         HW_XSTAT(rx_management_dropped),
 180
 181         /* Basic Error */
 182         HW_XSTAT(rx_crc_errors),
 183         HW_XSTAT(rx_illegal_byte_errors),
 184         HW_XSTAT(rx_error_bytes),
 185         HW_XSTAT(rx_mac_short_packet_dropped),
 186         HW_XSTAT(rx_length_errors),
 187         HW_XSTAT(rx_undersize_errors),
 188         HW_XSTAT(rx_fragment_errors),
 189         HW_XSTAT(rx_oversize_errors),
 190         HW_XSTAT(rx_jabber_errors),
 191         HW_XSTAT(rx_l3_l4_xsum_error),
 192         HW_XSTAT(mac_local_errors),
 193         HW_XSTAT(mac_remote_errors),
 194
 195         /* Flow Director */
 196         HW_XSTAT(flow_director_added_filters),
 197         HW_XSTAT(flow_director_removed_filters),
 198         HW_XSTAT(flow_director_filter_add_errors),
 199         HW_XSTAT(flow_director_filter_remove_errors),
 200         HW_XSTAT(flow_director_matched_filters),
 201         HW_XSTAT(flow_director_missed_filters),
 202
 203         /* FCoE */
 204         HW_XSTAT(rx_fcoe_crc_errors),
 205         HW_XSTAT(rx_fcoe_mbuf_allocation_errors),
 206         HW_XSTAT(rx_fcoe_dropped),
 207         HW_XSTAT(rx_fcoe_packets),
 208         HW_XSTAT(tx_fcoe_packets),
 209         HW_XSTAT(rx_fcoe_bytes),
 210         HW_XSTAT(tx_fcoe_bytes),
 211         HW_XSTAT(rx_fcoe_no_ddp),
 212         HW_XSTAT(rx_fcoe_no_ddp_ext_buff),
 213
 214         /* MACSEC */
 215         HW_XSTAT(tx_macsec_pkts_untagged),
 216         HW_XSTAT(tx_macsec_pkts_encrypted),
 217         HW_XSTAT(tx_macsec_pkts_protected),
 218         HW_XSTAT(tx_macsec_octets_encrypted),
 219         HW_XSTAT(tx_macsec_octets_protected),
 220         HW_XSTAT(rx_macsec_pkts_untagged),
 221         HW_XSTAT(rx_macsec_pkts_badtag),
 222         HW_XSTAT(rx_macsec_pkts_nosci),
 223         HW_XSTAT(rx_macsec_pkts_unknownsci),
 224         HW_XSTAT(rx_macsec_octets_decrypted),
 225         HW_XSTAT(rx_macsec_octets_validated),
 226         HW_XSTAT(rx_macsec_sc_pkts_unchecked),
 227         HW_XSTAT(rx_macsec_sc_pkts_delayed),
 228         HW_XSTAT(rx_macsec_sc_pkts_late),
 229         HW_XSTAT(rx_macsec_sa_pkts_ok),
 230         HW_XSTAT(rx_macsec_sa_pkts_invalid),
 231         HW_XSTAT(rx_macsec_sa_pkts_notvalid),
 232         HW_XSTAT(rx_macsec_sa_pkts_unusedsa),
 233         HW_XSTAT(rx_macsec_sa_pkts_notusingsa),
 234
 235         /* MAC RxTx */
 236         HW_XSTAT(rx_size_64_packets),
 237         HW_XSTAT(rx_size_65_to_127_packets),
 238         HW_XSTAT(rx_size_128_to_255_packets),
 239         HW_XSTAT(rx_size_256_to_511_packets),
 240         HW_XSTAT(rx_size_512_to_1023_packets),
 241         HW_XSTAT(rx_size_1024_to_max_packets),
 242         HW_XSTAT(tx_size_64_packets),
 243         HW_XSTAT(tx_size_65_to_127_packets),
 244         HW_XSTAT(tx_size_128_to_255_packets),
 245         HW_XSTAT(tx_size_256_to_511_packets),
 246         HW_XSTAT(tx_size_512_to_1023_packets),
 247         HW_XSTAT(tx_size_1024_to_max_packets),
 248
 249         /* Flow Control */
 250         HW_XSTAT(tx_xon_packets),
 251         HW_XSTAT(rx_xon_packets),
 252         HW_XSTAT(tx_xoff_packets),
 253         HW_XSTAT(rx_xoff_packets),
 254
 255         HW_XSTAT_NAME(tx_xon_packets, "tx_flow_control_xon_packets"),
 256         HW_XSTAT_NAME(rx_xon_packets, "rx_flow_control_xon_packets"),
 257         HW_XSTAT_NAME(tx_xoff_packets, "tx_flow_control_xoff_packets"),
 258         HW_XSTAT_NAME(rx_xoff_packets, "rx_flow_control_xoff_packets"),
 259 };
 260
 261 #define TXGBE_NB_HW_STATS (sizeof(rte_txgbe_stats_strings) / \
 262                            sizeof(rte_txgbe_stats_strings[0]))
 263
 264 /* Per-priority statistics */
 265 #define UP_XSTAT(m) {#m, offsetof(struct txgbe_hw_stats, up[0].m)}
 266 static const struct rte_txgbe_xstats_name_off rte_txgbe_up_strings[] = {
 267         UP_XSTAT(rx_up_packets),
 268         UP_XSTAT(tx_up_packets),
 269         UP_XSTAT(rx_up_bytes),
 270         UP_XSTAT(tx_up_bytes),
 271         UP_XSTAT(rx_up_drop_packets),
 272
 273         UP_XSTAT(tx_up_xon_packets),
 274         UP_XSTAT(rx_up_xon_packets),
 275         UP_XSTAT(tx_up_xoff_packets),
 276         UP_XSTAT(rx_up_xoff_packets),
 277         UP_XSTAT(rx_up_dropped),
 278         UP_XSTAT(rx_up_mbuf_alloc_errors),
 279         UP_XSTAT(tx_up_xon2off_packets),
 280 };
 281
 282 #define TXGBE_NB_UP_STATS (sizeof(rte_txgbe_up_strings) / \
 283                            sizeof(rte_txgbe_up_strings[0]))
 284
 285 /* Per-queue statistics */
 286 #define QP_XSTAT(m) {#m, offsetof(struct txgbe_hw_stats, qp[0].m)}
 287 static const struct rte_txgbe_xstats_name_off rte_txgbe_qp_strings[] = {
 288         QP_XSTAT(rx_qp_packets),
 289         QP_XSTAT(tx_qp_packets),
 290         QP_XSTAT(rx_qp_bytes),
 291         QP_XSTAT(tx_qp_bytes),
 292         QP_XSTAT(rx_qp_mc_packets),
 293 };
 294
 295 #define TXGBE_NB_QP_STATS (sizeof(rte_txgbe_qp_strings) / \
 296                            sizeof(rte_txgbe_qp_strings[0]))
 297
 298 static inline int
 299 txgbe_is_sfp(struct txgbe_hw *hw)
 300 {
 301         switch (hw->phy.type) {
 302         case txgbe_phy_sfp_avago:
 303         case txgbe_phy_sfp_ftl:
 304         case txgbe_phy_sfp_intel:
 305         case txgbe_phy_sfp_unknown:
 306         case txgbe_phy_sfp_tyco_passive:
 307         case txgbe_phy_sfp_unknown_passive:
 308                 return 1;
 309         default:
 310                 return 0;
 311         }
 312 }
 313
 314 static inline int32_t
 315 txgbe_pf_reset_hw(struct txgbe_hw *hw)
 316 {
 317         uint32_t ctrl_ext;
 318         int32_t status;
 319
 320         status = hw->mac.reset_hw(hw);
 321
 322         ctrl_ext = rd32(hw, TXGBE_PORTCTL);
 323         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 324         ctrl_ext |= TXGBE_PORTCTL_RSTDONE;
 325         wr32(hw, TXGBE_PORTCTL, ctrl_ext);
 326         txgbe_flush(hw);
 327
 328         if (status == TXGBE_ERR_SFP_NOT_PRESENT)
 329                 status = 0;
 330         return status;
 331 }
 332
 333 static inline void
 334 txgbe_enable_intr(struct rte_eth_dev *dev)
 335 {
 336         struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);
 337         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
 338
 339         wr32(hw, TXGBE_IENMISC, intr->mask_misc);
 340         wr32(hw, TXGBE_IMC(0), TXGBE_IMC_MASK);
 341         wr32(hw, TXGBE_IMC(1), TXGBE_IMC_MASK);
 342         txgbe_flush(hw);
 343 }
 344
 345 static void
 346 txgbe_disable_intr(struct txgbe_hw *hw)
 347 {
 348         PMD_INIT_FUNC_TRACE();
 349
 350         wr32(hw, TXGBE_IENMISC, ~BIT_MASK32);
 351         wr32(hw, TXGBE_IMS(0), TXGBE_IMC_MASK);
 352         wr32(hw, TXGBE_IMS(1), TXGBE_IMC_MASK);
 353         txgbe_flush(hw);
 354 }
 355
 356 static int
 357 txgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 358                                   uint16_t queue_id,
 359                                   uint8_t stat_idx,
 360                                   uint8_t is_rx)
 361 {
 362         struct txgbe_hw *hw = TXGBE_DEV_HW(eth_dev);
 363         struct txgbe_stat_mappings *stat_mappings =
 364                 TXGBE_DEV_STAT_MAPPINGS(eth_dev);
 365         uint32_t qsmr_mask = 0;
 366         uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
 367         uint32_t q_map;
 368         uint8_t n, offset;
 369
 370         if (hw->mac.type != txgbe_mac_raptor)
 371                 return -ENOSYS;
 372
 373         if (stat_idx & !QMAP_FIELD_RESERVED_BITS_MASK)
 374                 return -EIO;
 375
 376         PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d",
 377                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 378                      queue_id, stat_idx);
 379
 380         n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
 381         if (n >= TXGBE_NB_STAT_MAPPING) {
 382                 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
 383                 return -EIO;
 384         }
 385         offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
 386
 387         /* Now clear any previous stat_idx set */
 388         clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 389         if (!is_rx)
 390                 stat_mappings->tqsm[n] &= ~clearing_mask;
 391         else
 392                 stat_mappings->rqsm[n] &= ~clearing_mask;
 393
 394         q_map = (uint32_t)stat_idx;
 395         q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
 396         qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 397         if (!is_rx)
 398                 stat_mappings->tqsm[n] |= qsmr_mask;
 399         else
 400                 stat_mappings->rqsm[n] |= qsmr_mask;
 401
 402         PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d",
 403                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 404                      queue_id, stat_idx);
 405         PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
 406                      is_rx ? stat_mappings->rqsm[n] : stat_mappings->tqsm[n]);
 407         return 0;
 408 }
 409
 410 static void
 411 txgbe_dcb_init(struct txgbe_hw *hw, struct txgbe_dcb_config *dcb_config)
 412 {
 413         int i;
 414         u8 bwgp;
 415         struct txgbe_dcb_tc_config *tc;
 416
 417         UNREFERENCED_PARAMETER(hw);
 418
 419         dcb_config->num_tcs.pg_tcs = TXGBE_DCB_TC_MAX;
 420         dcb_config->num_tcs.pfc_tcs = TXGBE_DCB_TC_MAX;
 421         bwgp = (u8)(100 / TXGBE_DCB_TC_MAX);
 422         for (i = 0; i < TXGBE_DCB_TC_MAX; i++) {
 423                 tc = &dcb_config->tc_config[i];
 424                 tc->path[TXGBE_DCB_TX_CONFIG].bwg_id = i;
 425                 tc->path[TXGBE_DCB_TX_CONFIG].bwg_percent = bwgp + (i & 1);
 426                 tc->path[TXGBE_DCB_RX_CONFIG].bwg_id = i;
 427                 tc->path[TXGBE_DCB_RX_CONFIG].bwg_percent = bwgp + (i & 1);
 428                 tc->pfc = txgbe_dcb_pfc_disabled;
 429         }
 430
 431         /* Initialize default user to priority mapping, UPx->TC0 */
 432         tc = &dcb_config->tc_config[0];
 433         tc->path[TXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
 434         tc->path[TXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
 435         for (i = 0; i < TXGBE_DCB_BWG_MAX; i++) {
 436                 dcb_config->bw_percentage[i][TXGBE_DCB_TX_CONFIG] = 100;
 437                 dcb_config->bw_percentage[i][TXGBE_DCB_RX_CONFIG] = 100;
 438         }
 439         dcb_config->rx_pba_cfg = txgbe_dcb_pba_equal;
 440         dcb_config->pfc_mode_enable = false;
 441         dcb_config->vt_mode = true;
 442         dcb_config->round_robin_enable = false;
 443         /* support all DCB capabilities */
 444         dcb_config->support.capabilities = 0xFF;
 445 }
 446
 447 /*
 448  * Ensure that all locks are released before first NVM or PHY access
 449  */
 450 static void
 451 txgbe_swfw_lock_reset(struct txgbe_hw *hw)
 452 {
 453         uint16_t mask;
 454
 455         /*
 456          * These ones are more tricky since they are common to all ports; but
 457          * swfw_sync retries last long enough (1s) to be almost sure that if
 458          * lock can not be taken it is due to an improper lock of the
 459          * semaphore.
 460          */
 461         mask = TXGBE_MNGSEM_SWPHY |
 462                TXGBE_MNGSEM_SWMBX |
 463                TXGBE_MNGSEM_SWFLASH;
 464         if (hw->mac.acquire_swfw_sync(hw, mask) < 0)
 465                 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
 466
 467         hw->mac.release_swfw_sync(hw, mask);
 468 }
 469
 470 static int
 471 eth_txgbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params __rte_unused)
 472 {
 473         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
 474         struct txgbe_hw *hw = TXGBE_DEV_HW(eth_dev);
 475         struct txgbe_vfta *shadow_vfta = TXGBE_DEV_VFTA(eth_dev);
 476         struct txgbe_hwstrip *hwstrip = TXGBE_DEV_HWSTRIP(eth_dev);
 477         struct txgbe_dcb_config *dcb_config = TXGBE_DEV_DCB_CONFIG(eth_dev);
 478         struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(eth_dev);
 479         struct txgbe_bw_conf *bw_conf = TXGBE_DEV_BW_CONF(eth_dev);
 480         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 481         const struct rte_memzone *mz;
 482         uint32_t ctrl_ext;
 483         uint16_t csum;
 484         int err, i, ret;
 485
 486         PMD_INIT_FUNC_TRACE();
 487
 488         eth_dev->dev_ops = &txgbe_eth_dev_ops;
 489         eth_dev->rx_queue_count       = txgbe_dev_rx_queue_count;
 490         eth_dev->rx_descriptor_status = txgbe_dev_rx_descriptor_status;
 491         eth_dev->tx_descriptor_status = txgbe_dev_tx_descriptor_status;
 492         eth_dev->rx_pkt_burst = &txgbe_recv_pkts;
 493         eth_dev->tx_pkt_burst = &txgbe_xmit_pkts;
 494         eth_dev->tx_pkt_prepare = &txgbe_prep_pkts;
 495
 496         /*
 497          * For secondary processes, we don't initialise any further as primary
 498          * has already done this work. Only check we don't need a different
 499          * RX and TX function.
 500          */
 501         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
 502                 struct txgbe_tx_queue *txq;
 503                 /* TX queue function in primary, set by last queue initialized
 504                  * Tx queue may not initialized by primary process
 505                  */
 506                 if (eth_dev->data->tx_queues) {
 507                         uint16_t nb_tx_queues = eth_dev->data->nb_tx_queues;
 508                         txq = eth_dev->data->tx_queues[nb_tx_queues - 1];
 509                         txgbe_set_tx_function(eth_dev, txq);
 510                 } else {
 511                         /* Use default TX function if we get here */
 512                         PMD_INIT_LOG(NOTICE, "No TX queues configured yet. "
 513                                      "Using default TX function.");
 514                 }
 515
 516                 txgbe_set_rx_function(eth_dev);
 517
 518                 return 0;
 519         }
 520
 521         rte_eth_copy_pci_info(eth_dev, pci_dev);
 522
 523         /* Vendor and Device ID need to be set before init of shared code */
 524         hw->device_id = pci_dev->id.device_id;
 525         hw->vendor_id = pci_dev->id.vendor_id;
 526         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
 527         hw->allow_unsupported_sfp = 1;
 528
 529         /* Reserve memory for interrupt status block */
 530         mz = rte_eth_dma_zone_reserve(eth_dev, "txgbe_driver", -1,
 531                 16, TXGBE_ALIGN, SOCKET_ID_ANY);
 532         if (mz == NULL)
 533                 return -ENOMEM;
 534
 535         hw->isb_dma = TMZ_PADDR(mz);
 536         hw->isb_mem = TMZ_VADDR(mz);
 537
 538         /* Initialize the shared code (base driver) */
 539         err = txgbe_init_shared_code(hw);
 540         if (err != 0) {
 541                 PMD_INIT_LOG(ERR, "Shared code init failed: %d", err);
 542                 return -EIO;
 543         }
 544
 545         /* Unlock any pending hardware semaphore */
 546         txgbe_swfw_lock_reset(hw);
 547
 548         /* Initialize DCB configuration*/
 549         memset(dcb_config, 0, sizeof(struct txgbe_dcb_config));
 550         txgbe_dcb_init(hw, dcb_config);
 551
 552         /* Get Hardware Flow Control setting */
 553         hw->fc.requested_mode = txgbe_fc_full;
 554         hw->fc.current_mode = txgbe_fc_full;
 555         hw->fc.pause_time = TXGBE_FC_PAUSE_TIME;
 556         for (i = 0; i < TXGBE_DCB_TC_MAX; i++) {
 557                 hw->fc.low_water[i] = TXGBE_FC_XON_LOTH;
 558                 hw->fc.high_water[i] = TXGBE_FC_XOFF_HITH;
 559         }
 560         hw->fc.send_xon = 1;
 561
 562         err = hw->rom.init_params(hw);
 563         if (err != 0) {
 564                 PMD_INIT_LOG(ERR, "The EEPROM init failed: %d", err);
 565                 return -EIO;
 566         }
 567
 568         /* Make sure we have a good EEPROM before we read from it */
 569         err = hw->rom.validate_checksum(hw, &csum);
 570         if (err != 0) {
 571                 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", err);
 572                 return -EIO;
 573         }
 574
 575         err = hw->mac.init_hw(hw);
 576
 577         /*
 578          * Devices with copper phys will fail to initialise if txgbe_init_hw()
 579          * is called too soon after the kernel driver unbinding/binding occurs.
 580          * The failure occurs in txgbe_identify_phy() for all devices,
 581          * but for non-copper devies, txgbe_identify_sfp_module() is
 582          * also called. See txgbe_identify_phy(). The reason for the
 583          * failure is not known, and only occuts when virtualisation features
 584          * are disabled in the bios. A delay of 200ms  was found to be enough by
 585          * trial-and-error, and is doubled to be safe.
 586          */
 587         if (err && hw->phy.media_type == txgbe_media_type_copper) {
 588                 rte_delay_ms(200);
 589                 err = hw->mac.init_hw(hw);
 590         }
 591
 592         if (err == TXGBE_ERR_SFP_NOT_PRESENT)
 593                 err = 0;
 594
 595         if (err == TXGBE_ERR_EEPROM_VERSION) {
 596                 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
 597                              "LOM.  Please be aware there may be issues associated "
 598                              "with your hardware.");
 599                 PMD_INIT_LOG(ERR, "If you are experiencing problems "
 600                              "please contact your hardware representative "
 601                              "who provided you with this hardware.");
 602         } else if (err == TXGBE_ERR_SFP_NOT_SUPPORTED) {
 603                 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
 604         }
 605         if (err) {
 606                 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", err);
 607                 return -EIO;
 608         }
 609
 610         /* Reset the hw statistics */
 611         txgbe_dev_stats_reset(eth_dev);
 612
 613         /* disable interrupt */
 614         txgbe_disable_intr(hw);
 615
 616         /* Allocate memory for storing MAC addresses */
 617         eth_dev->data->mac_addrs = rte_zmalloc("txgbe", RTE_ETHER_ADDR_LEN *
 618                                                hw->mac.num_rar_entries, 0);
 619         if (eth_dev->data->mac_addrs == NULL) {
 620                 PMD_INIT_LOG(ERR,
 621                              "Failed to allocate %u bytes needed to store "
 622                              "MAC addresses",
 623                              RTE_ETHER_ADDR_LEN * hw->mac.num_rar_entries);
 624                 return -ENOMEM;
 625         }
 626
 627         /* Copy the permanent MAC address */
 628         rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.perm_addr,
 629                         &eth_dev->data->mac_addrs[0]);
 630
 631         /* Allocate memory for storing hash filter MAC addresses */
 632         eth_dev->data->hash_mac_addrs = rte_zmalloc("txgbe",
 633                         RTE_ETHER_ADDR_LEN * TXGBE_VMDQ_NUM_UC_MAC, 0);
 634         if (eth_dev->data->hash_mac_addrs == NULL) {
 635                 PMD_INIT_LOG(ERR,
 636                              "Failed to allocate %d bytes needed to store MAC addresses",
 637                              RTE_ETHER_ADDR_LEN * TXGBE_VMDQ_NUM_UC_MAC);
 638                 return -ENOMEM;
 639         }
 640
 641         /* initialize the vfta */
 642         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
 643
 644         /* initialize the hw strip bitmap*/
 645         memset(hwstrip, 0, sizeof(*hwstrip));
 646
 647         /* initialize PF if max_vfs not zero */
 648         ret = txgbe_pf_host_init(eth_dev);
 649         if (ret) {
 650                 rte_free(eth_dev->data->mac_addrs);
 651                 eth_dev->data->mac_addrs = NULL;
 652                 rte_free(eth_dev->data->hash_mac_addrs);
 653                 eth_dev->data->hash_mac_addrs = NULL;
 654                 return ret;
 655         }
 656
 657         ctrl_ext = rd32(hw, TXGBE_PORTCTL);
 658         /* let hardware know driver is loaded */
 659         ctrl_ext |= TXGBE_PORTCTL_DRVLOAD;
 660         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 661         ctrl_ext |= TXGBE_PORTCTL_RSTDONE;
 662         wr32(hw, TXGBE_PORTCTL, ctrl_ext);
 663         txgbe_flush(hw);
 664
 665         if (txgbe_is_sfp(hw) && hw->phy.sfp_type != txgbe_sfp_type_not_present)
 666                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
 667                              (int)hw->mac.type, (int)hw->phy.type,
 668                              (int)hw->phy.sfp_type);
 669         else
 670                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
 671                              (int)hw->mac.type, (int)hw->phy.type);
 672
 673         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
 674                      eth_dev->data->port_id, pci_dev->id.vendor_id,
 675                      pci_dev->id.device_id);
 676
 677         rte_intr_callback_register(intr_handle,
 678                                    txgbe_dev_interrupt_handler, eth_dev);
 679
 680         /* enable uio/vfio intr/eventfd mapping */
 681         rte_intr_enable(intr_handle);
 682
 683         /* enable support intr */
 684         txgbe_enable_intr(eth_dev);
 685
 686         /* initialize filter info */
 687         memset(filter_info, 0,
 688                sizeof(struct txgbe_filter_info));
 689
 690         /* initialize 5tuple filter list */
 691         TAILQ_INIT(&filter_info->fivetuple_list);
 692
 693         /* initialize l2 tunnel filter list & hash */
 694         txgbe_l2_tn_filter_init(eth_dev);
 695
 696         /* initialize bandwidth configuration info */
 697         memset(bw_conf, 0, sizeof(struct txgbe_bw_conf));
 698
 699         return 0;
 700 }
 701
 702 static int
 703 eth_txgbe_dev_uninit(struct rte_eth_dev *eth_dev)
 704 {
 705         PMD_INIT_FUNC_TRACE();
 706
 707         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 708                 return 0;
 709
 710         txgbe_dev_close(eth_dev);
 711
 712         return 0;
 713 }
 714
 715 static int txgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev)
 716 {
 717         struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(eth_dev);
 718         struct txgbe_5tuple_filter *p_5tuple;
 719
 720         while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) {
 721                 TAILQ_REMOVE(&filter_info->fivetuple_list,
 722                              p_5tuple,
 723                              entries);
 724                 rte_free(p_5tuple);
 725         }
 726         memset(filter_info->fivetuple_mask, 0,
 727                sizeof(uint32_t) * TXGBE_5TUPLE_ARRAY_SIZE);
 728
 729         return 0;
 730 }
 731
 732 static int txgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev)
 733 {
 734         struct txgbe_l2_tn_info *l2_tn_info = TXGBE_DEV_L2_TN(eth_dev);
 735         struct txgbe_l2_tn_filter *l2_tn_filter;
 736
 737         if (l2_tn_info->hash_map)
 738                 rte_free(l2_tn_info->hash_map);
 739         if (l2_tn_info->hash_handle)
 740                 rte_hash_free(l2_tn_info->hash_handle);
 741
 742         while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
 743                 TAILQ_REMOVE(&l2_tn_info->l2_tn_list,
 744                              l2_tn_filter,
 745                              entries);
 746                 rte_free(l2_tn_filter);
 747         }
 748
 749         return 0;
 750 }
 751
 752 static int txgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev)
 753 {
 754         struct txgbe_l2_tn_info *l2_tn_info = TXGBE_DEV_L2_TN(eth_dev);
 755         char l2_tn_hash_name[RTE_HASH_NAMESIZE];
 756         struct rte_hash_parameters l2_tn_hash_params = {
 757                 .name = l2_tn_hash_name,
 758                 .entries = TXGBE_MAX_L2_TN_FILTER_NUM,
 759                 .key_len = sizeof(struct txgbe_l2_tn_key),
 760                 .hash_func = rte_hash_crc,
 761                 .hash_func_init_val = 0,
 762                 .socket_id = rte_socket_id(),
 763         };
 764
 765         TAILQ_INIT(&l2_tn_info->l2_tn_list);
 766         snprintf(l2_tn_hash_name, RTE_HASH_NAMESIZE,
 767                  "l2_tn_%s", TDEV_NAME(eth_dev));
 768         l2_tn_info->hash_handle = rte_hash_create(&l2_tn_hash_params);
 769         if (!l2_tn_info->hash_handle) {
 770                 PMD_INIT_LOG(ERR, "Failed to create L2 TN hash table!");
 771                 return -EINVAL;
 772         }
 773         l2_tn_info->hash_map = rte_zmalloc("txgbe",
 774                                    sizeof(struct txgbe_l2_tn_filter *) *
 775                                    TXGBE_MAX_L2_TN_FILTER_NUM,
 776                                    0);
 777         if (!l2_tn_info->hash_map) {
 778                 PMD_INIT_LOG(ERR,
 779                         "Failed to allocate memory for L2 TN hash map!");
 780                 return -ENOMEM;
 781         }
 782         l2_tn_info->e_tag_en = FALSE;
 783         l2_tn_info->e_tag_fwd_en = FALSE;
 784         l2_tn_info->e_tag_ether_type = RTE_ETHER_TYPE_ETAG;
 785
 786         return 0;
 787 }
 788
 789 static int
 790 eth_txgbe_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
 791                 struct rte_pci_device *pci_dev)
 792 {
 793         struct rte_eth_dev *pf_ethdev;
 794         struct rte_eth_devargs eth_da;
 795         int retval;
 796
 797         if (pci_dev->device.devargs) {
 798                 retval = rte_eth_devargs_parse(pci_dev->device.devargs->args,
 799                                 &eth_da);
 800                 if (retval)
 801                         return retval;
 802         } else {
 803                 memset(&eth_da, 0, sizeof(eth_da));
 804         }
 805
 806         retval = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
 807                         sizeof(struct txgbe_adapter),
 808                         eth_dev_pci_specific_init, pci_dev,
 809                         eth_txgbe_dev_init, NULL);
 810
 811         if (retval || eth_da.nb_representor_ports < 1)
 812                 return retval;
 813
 814         pf_ethdev = rte_eth_dev_allocated(pci_dev->device.name);
 815         if (pf_ethdev == NULL)
 816                 return -ENODEV;
 817
 818         return 0;
 819 }
 820
 821 static int eth_txgbe_pci_remove(struct rte_pci_device *pci_dev)
 822 {
 823         struct rte_eth_dev *ethdev;
 824
 825         ethdev = rte_eth_dev_allocated(pci_dev->device.name);
 826         if (!ethdev)
 827                 return -ENODEV;
 828
 829         return rte_eth_dev_destroy(ethdev, eth_txgbe_dev_uninit);
 830 }
 831
 832 static struct rte_pci_driver rte_txgbe_pmd = {
 833         .id_table = pci_id_txgbe_map,
 834         .drv_flags = RTE_PCI_DRV_NEED_MAPPING |
 835                      RTE_PCI_DRV_INTR_LSC,
 836         .probe = eth_txgbe_pci_probe,
 837         .remove = eth_txgbe_pci_remove,
 838 };
 839
 840 static int
 841 txgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
 842 {
 843         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
 844         struct txgbe_vfta *shadow_vfta = TXGBE_DEV_VFTA(dev);
 845         uint32_t vfta;
 846         uint32_t vid_idx;
 847         uint32_t vid_bit;
 848
 849         vid_idx = (uint32_t)((vlan_id >> 5) & 0x7F);
 850         vid_bit = (uint32_t)(1 << (vlan_id & 0x1F));
 851         vfta = rd32(hw, TXGBE_VLANTBL(vid_idx));
 852         if (on)
 853                 vfta |= vid_bit;
 854         else
 855                 vfta &= ~vid_bit;
 856         wr32(hw, TXGBE_VLANTBL(vid_idx), vfta);
 857
 858         /* update local VFTA copy */
 859         shadow_vfta->vfta[vid_idx] = vfta;
 860
 861         return 0;
 862 }
 863
 864 static void
 865 txgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
 866 {
 867         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
 868         struct txgbe_rx_queue *rxq;
 869         bool restart;
 870         uint32_t rxcfg, rxbal, rxbah;
 871
 872         if (on)
 873                 txgbe_vlan_hw_strip_enable(dev, queue);
 874         else
 875                 txgbe_vlan_hw_strip_disable(dev, queue);
 876
 877         rxq = dev->data->rx_queues[queue];
 878         rxbal = rd32(hw, TXGBE_RXBAL(rxq->reg_idx));
 879         rxbah = rd32(hw, TXGBE_RXBAH(rxq->reg_idx));
 880         rxcfg = rd32(hw, TXGBE_RXCFG(rxq->reg_idx));
 881         if (rxq->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) {
 882                 restart = (rxcfg & TXGBE_RXCFG_ENA) &&
 883                         !(rxcfg & TXGBE_RXCFG_VLAN);
 884                 rxcfg |= TXGBE_RXCFG_VLAN;
 885         } else {
 886                 restart = (rxcfg & TXGBE_RXCFG_ENA) &&
 887                         (rxcfg & TXGBE_RXCFG_VLAN);
 888                 rxcfg &= ~TXGBE_RXCFG_VLAN;
 889         }
 890         rxcfg &= ~TXGBE_RXCFG_ENA;
 891
 892         if (restart) {
 893                 /* set vlan strip for ring */
 894                 txgbe_dev_rx_queue_stop(dev, queue);
 895                 wr32(hw, TXGBE_RXBAL(rxq->reg_idx), rxbal);
 896                 wr32(hw, TXGBE_RXBAH(rxq->reg_idx), rxbah);
 897                 wr32(hw, TXGBE_RXCFG(rxq->reg_idx), rxcfg);
 898                 txgbe_dev_rx_queue_start(dev, queue);
 899         }
 900 }
 901
 902 static int
 903 txgbe_vlan_tpid_set(struct rte_eth_dev *dev,
 904                     enum rte_vlan_type vlan_type,
 905                     uint16_t tpid)
 906 {
 907         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
 908         int ret = 0;
 909         uint32_t portctrl, vlan_ext, qinq;
 910
 911         portctrl = rd32(hw, TXGBE_PORTCTL);
 912
 913         vlan_ext = (portctrl & TXGBE_PORTCTL_VLANEXT);
 914         qinq = vlan_ext && (portctrl & TXGBE_PORTCTL_QINQ);
 915         switch (vlan_type) {
 916         case ETH_VLAN_TYPE_INNER:
 917                 if (vlan_ext) {
 918                         wr32m(hw, TXGBE_VLANCTL,
 919                                 TXGBE_VLANCTL_TPID_MASK,
 920                                 TXGBE_VLANCTL_TPID(tpid));
 921                         wr32m(hw, TXGBE_DMATXCTRL,
 922                                 TXGBE_DMATXCTRL_TPID_MASK,
 923                                 TXGBE_DMATXCTRL_TPID(tpid));
 924                 } else {
 925                         ret = -ENOTSUP;
 926                         PMD_DRV_LOG(ERR, "Inner type is not supported"
 927                                     " by single VLAN");
 928                 }
 929
 930                 if (qinq) {
 931                         wr32m(hw, TXGBE_TAGTPID(0),
 932                                 TXGBE_TAGTPID_LSB_MASK,
 933                                 TXGBE_TAGTPID_LSB(tpid));
 934                 }
 935                 break;
 936         case ETH_VLAN_TYPE_OUTER:
 937                 if (vlan_ext) {
 938                         /* Only the high 16-bits is valid */
 939                         wr32m(hw, TXGBE_EXTAG,
 940                                 TXGBE_EXTAG_VLAN_MASK,
 941                                 TXGBE_EXTAG_VLAN(tpid));
 942                 } else {
 943                         wr32m(hw, TXGBE_VLANCTL,
 944                                 TXGBE_VLANCTL_TPID_MASK,
 945                                 TXGBE_VLANCTL_TPID(tpid));
 946                         wr32m(hw, TXGBE_DMATXCTRL,
 947                                 TXGBE_DMATXCTRL_TPID_MASK,
 948                                 TXGBE_DMATXCTRL_TPID(tpid));
 949                 }
 950
 951                 if (qinq) {
 952                         wr32m(hw, TXGBE_TAGTPID(0),
 953                                 TXGBE_TAGTPID_MSB_MASK,
 954                                 TXGBE_TAGTPID_MSB(tpid));
 955                 }
 956                 break;
 957         default:
 958                 PMD_DRV_LOG(ERR, "Unsupported VLAN type %d", vlan_type);
 959                 return -EINVAL;
 960         }
 961
 962         return ret;
 963 }
 964
 965 void
 966 txgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
 967 {
 968         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
 969         uint32_t vlnctrl;
 970
 971         PMD_INIT_FUNC_TRACE();
 972
 973         /* Filter Table Disable */
 974         vlnctrl = rd32(hw, TXGBE_VLANCTL);
 975         vlnctrl &= ~TXGBE_VLANCTL_VFE;
 976         wr32(hw, TXGBE_VLANCTL, vlnctrl);
 977 }
 978
 979 void
 980 txgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
 981 {
 982         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
 983         struct txgbe_vfta *shadow_vfta = TXGBE_DEV_VFTA(dev);
 984         uint32_t vlnctrl;
 985         uint16_t i;
 986
 987         PMD_INIT_FUNC_TRACE();
 988
 989         /* Filter Table Enable */
 990         vlnctrl = rd32(hw, TXGBE_VLANCTL);
 991         vlnctrl &= ~TXGBE_VLANCTL_CFIENA;
 992         vlnctrl |= TXGBE_VLANCTL_VFE;
 993         wr32(hw, TXGBE_VLANCTL, vlnctrl);
 994
 995         /* write whatever is in local vfta copy */
 996         for (i = 0; i < TXGBE_VFTA_SIZE; i++)
 997                 wr32(hw, TXGBE_VLANTBL(i), shadow_vfta->vfta[i]);
 998 }
 999
1000 void
1001 txgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1002 {
1003         struct txgbe_hwstrip *hwstrip = TXGBE_DEV_HWSTRIP(dev);
1004         struct txgbe_rx_queue *rxq;
1005
1006         if (queue >= TXGBE_MAX_RX_QUEUE_NUM)
1007                 return;
1008
1009         if (on)
1010                 TXGBE_SET_HWSTRIP(hwstrip, queue);
1011         else
1012                 TXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1013
1014         if (queue >= dev->data->nb_rx_queues)
1015                 return;
1016
1017         rxq = dev->data->rx_queues[queue];
1018
1019         if (on) {
1020                 rxq->vlan_flags = PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
1021                 rxq->offloads |= DEV_RX_OFFLOAD_VLAN_STRIP;
1022         } else {
1023                 rxq->vlan_flags = PKT_RX_VLAN;
1024                 rxq->offloads &= ~DEV_RX_OFFLOAD_VLAN_STRIP;
1025         }
1026 }
1027
1028 static void
1029 txgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
1030 {
1031         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
1032         uint32_t ctrl;
1033
1034         PMD_INIT_FUNC_TRACE();
1035
1036         ctrl = rd32(hw, TXGBE_RXCFG(queue));
1037         ctrl &= ~TXGBE_RXCFG_VLAN;
1038         wr32(hw, TXGBE_RXCFG(queue), ctrl);
1039
1040         /* record those setting for HW strip per queue */
1041         txgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
1042 }
1043
1044 static void
1045 txgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
1046 {
1047         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
1048         uint32_t ctrl;
1049
1050         PMD_INIT_FUNC_TRACE();
1051
1052         ctrl = rd32(hw, TXGBE_RXCFG(queue));
1053         ctrl |= TXGBE_RXCFG_VLAN;
1054         wr32(hw, TXGBE_RXCFG(queue), ctrl);
1055
1056         /* record those setting for HW strip per queue */
1057         txgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
1058 }
1059
1060 static void
1061 txgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
1062 {
1063         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
1064         uint32_t ctrl;
1065
1066         PMD_INIT_FUNC_TRACE();
1067
1068         ctrl = rd32(hw, TXGBE_PORTCTL);
1069         ctrl &= ~TXGBE_PORTCTL_VLANEXT;
1070         ctrl &= ~TXGBE_PORTCTL_QINQ;
1071         wr32(hw, TXGBE_PORTCTL, ctrl);
1072 }
1073
1074 static void
1075 txgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
1076 {
1077         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
1078         struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
1079         struct rte_eth_txmode *txmode = &dev->data->dev_conf.txmode;
1080         uint32_t ctrl;
1081
1082         PMD_INIT_FUNC_TRACE();
1083
1084         ctrl  = rd32(hw, TXGBE_PORTCTL);
1085         ctrl |= TXGBE_PORTCTL_VLANEXT;
1086         if (rxmode->offloads & DEV_RX_OFFLOAD_QINQ_STRIP ||
1087             txmode->offloads & DEV_TX_OFFLOAD_QINQ_INSERT)
1088                 ctrl |= TXGBE_PORTCTL_QINQ;
1089         wr32(hw, TXGBE_PORTCTL, ctrl);
1090 }
1091
1092 void
1093 txgbe_vlan_hw_strip_config(struct rte_eth_dev *dev)
1094 {
1095         struct txgbe_rx_queue *rxq;
1096         uint16_t i;
1097
1098         PMD_INIT_FUNC_TRACE();
1099
1100         for (i = 0; i < dev->data->nb_rx_queues; i++) {
1101                 rxq = dev->data->rx_queues[i];
1102
1103                 if (rxq->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1104                         txgbe_vlan_strip_queue_set(dev, i, 1);
1105                 else
1106                         txgbe_vlan_strip_queue_set(dev, i, 0);
1107         }
1108 }
1109
1110 void
1111 txgbe_config_vlan_strip_on_all_queues(struct rte_eth_dev *dev, int mask)
1112 {
1113         uint16_t i;
1114         struct rte_eth_rxmode *rxmode;
1115         struct txgbe_rx_queue *rxq;
1116
1117         if (mask & ETH_VLAN_STRIP_MASK) {
1118                 rxmode = &dev->data->dev_conf.rxmode;
1119                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1120                         for (i = 0; i < dev->data->nb_rx_queues; i++) {
1121                                 rxq = dev->data->rx_queues[i];
1122                                 rxq->offloads |= DEV_RX_OFFLOAD_VLAN_STRIP;
1123                         }
1124                 else
1125                         for (i = 0; i < dev->data->nb_rx_queues; i++) {
1126                                 rxq = dev->data->rx_queues[i];
1127                                 rxq->offloads &= ~DEV_RX_OFFLOAD_VLAN_STRIP;
1128                         }
1129         }
1130 }
1131
1132 static int
1133 txgbe_vlan_offload_config(struct rte_eth_dev *dev, int mask)
1134 {
1135         struct rte_eth_rxmode *rxmode;
1136         rxmode = &dev->data->dev_conf.rxmode;
1137
1138         if (mask & ETH_VLAN_STRIP_MASK)
1139                 txgbe_vlan_hw_strip_config(dev);
1140
1141         if (mask & ETH_VLAN_FILTER_MASK) {
1142                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
1143                         txgbe_vlan_hw_filter_enable(dev);
1144                 else
1145                         txgbe_vlan_hw_filter_disable(dev);
1146         }
1147
1148         if (mask & ETH_VLAN_EXTEND_MASK) {
1149                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
1150                         txgbe_vlan_hw_extend_enable(dev);
1151                 else
1152                         txgbe_vlan_hw_extend_disable(dev);
1153         }
1154
1155         return 0;
1156 }
1157
1158 static int
1159 txgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1160 {
1161         txgbe_config_vlan_strip_on_all_queues(dev, mask);
1162
1163         txgbe_vlan_offload_config(dev, mask);
1164
1165         return 0;
1166 }
1167
1168 static void
1169 txgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1170 {
1171         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
1172         /* VLNCTL: enable vlan filtering and allow all vlan tags through */
1173         uint32_t vlanctrl = rd32(hw, TXGBE_VLANCTL);
1174
1175         vlanctrl |= TXGBE_VLANCTL_VFE; /* enable vlan filters */
1176         wr32(hw, TXGBE_VLANCTL, vlanctrl);
1177 }
1178
1179 static int
1180 txgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q)
1181 {
1182         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1183
1184         switch (nb_rx_q) {
1185         case 1:
1186         case 2:
1187                 RTE_ETH_DEV_SRIOV(dev).active = ETH_64_POOLS;
1188                 break;
1189         case 4:
1190                 RTE_ETH_DEV_SRIOV(dev).active = ETH_32_POOLS;
1191                 break;
1192         default:
1193                 return -EINVAL;
1194         }
1195
1196         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool =
1197                 TXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
1198         RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx =
1199                 pci_dev->max_vfs * RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
1200         return 0;
1201 }
1202
1203 static int
1204 txgbe_check_mq_mode(struct rte_eth_dev *dev)
1205 {
1206         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
1207         uint16_t nb_rx_q = dev->data->nb_rx_queues;
1208         uint16_t nb_tx_q = dev->data->nb_tx_queues;
1209
1210         if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
1211                 /* check multi-queue mode */
1212                 switch (dev_conf->rxmode.mq_mode) {
1213                 case ETH_MQ_RX_VMDQ_DCB:
1214                         PMD_INIT_LOG(INFO, "ETH_MQ_RX_VMDQ_DCB mode supported in SRIOV");
1215                         break;
1216                 case ETH_MQ_RX_VMDQ_DCB_RSS:
1217                         /* DCB/RSS VMDQ in SRIOV mode, not implement yet */
1218                         PMD_INIT_LOG(ERR, "SRIOV active,"
1219                                         " unsupported mq_mode rx %d.",
1220                                         dev_conf->rxmode.mq_mode);
1221                         return -EINVAL;
1222                 case ETH_MQ_RX_RSS:
1223                 case ETH_MQ_RX_VMDQ_RSS:
1224                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_RSS;
1225                         if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)
1226                                 if (txgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) {
1227                                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1228                                                 " invalid queue number"
1229                                                 " for VMDQ RSS, allowed"
1230                                                 " value are 1, 2 or 4.");
1231                                         return -EINVAL;
1232                                 }
1233                         break;
1234                 case ETH_MQ_RX_VMDQ_ONLY:
1235                 case ETH_MQ_RX_NONE:
1236                         /* if nothing mq mode configure, use default scheme */
1237                         dev->data->dev_conf.rxmode.mq_mode =
1238                                 ETH_MQ_RX_VMDQ_ONLY;
1239                         break;
1240                 default: /* ETH_MQ_RX_DCB, ETH_MQ_RX_DCB_RSS or ETH_MQ_TX_DCB*/
1241                         /* SRIOV only works in VMDq enable mode */
1242                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1243                                         " wrong mq_mode rx %d.",
1244                                         dev_conf->rxmode.mq_mode);
1245                         return -EINVAL;
1246                 }
1247
1248                 switch (dev_conf->txmode.mq_mode) {
1249                 case ETH_MQ_TX_VMDQ_DCB:
1250                         PMD_INIT_LOG(INFO, "ETH_MQ_TX_VMDQ_DCB mode supported in SRIOV");
1251                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_DCB;
1252                         break;
1253                 default: /* ETH_MQ_TX_VMDQ_ONLY or ETH_MQ_TX_NONE */
1254                         dev->data->dev_conf.txmode.mq_mode =
1255                                 ETH_MQ_TX_VMDQ_ONLY;
1256                         break;
1257                 }
1258
1259                 /* check valid queue number */
1260                 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) ||
1261                     (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) {
1262                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1263                                         " nb_rx_q=%d nb_tx_q=%d queue number"
1264                                         " must be less than or equal to %d.",
1265                                         nb_rx_q, nb_tx_q,
1266                                         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool);
1267                         return -EINVAL;
1268                 }
1269         } else {
1270                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
1271                         PMD_INIT_LOG(ERR, "VMDQ+DCB+RSS mq_mode is"
1272                                           " not supported.");
1273                         return -EINVAL;
1274                 }
1275                 /* check configuration for vmdb+dcb mode */
1276                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB) {
1277                         const struct rte_eth_vmdq_dcb_conf *conf;
1278
1279                         if (nb_rx_q != TXGBE_VMDQ_DCB_NB_QUEUES) {
1280                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.",
1281                                                 TXGBE_VMDQ_DCB_NB_QUEUES);
1282                                 return -EINVAL;
1283                         }
1284                         conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf;
1285                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
1286                                conf->nb_queue_pools == ETH_32_POOLS)) {
1287                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
1288                                                 " nb_queue_pools must be %d or %d.",
1289                                                 ETH_16_POOLS, ETH_32_POOLS);
1290                                 return -EINVAL;
1291                         }
1292                 }
1293                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) {
1294                         const struct rte_eth_vmdq_dcb_tx_conf *conf;
1295
1296                         if (nb_tx_q != TXGBE_VMDQ_DCB_NB_QUEUES) {
1297                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d",
1298                                                  TXGBE_VMDQ_DCB_NB_QUEUES);
1299                                 return -EINVAL;
1300                         }
1301                         conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf;
1302                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
1303                                conf->nb_queue_pools == ETH_32_POOLS)) {
1304                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
1305                                                 " nb_queue_pools != %d and"
1306                                                 " nb_queue_pools != %d.",
1307                                                 ETH_16_POOLS, ETH_32_POOLS);
1308                                 return -EINVAL;
1309                         }
1310                 }
1311
1312                 /* For DCB mode check our configuration before we go further */
1313                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_DCB) {
1314                         const struct rte_eth_dcb_rx_conf *conf;
1315
1316                         conf = &dev_conf->rx_adv_conf.dcb_rx_conf;
1317                         if (!(conf->nb_tcs == ETH_4_TCS ||
1318                                conf->nb_tcs == ETH_8_TCS)) {
1319                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
1320                                                 " and nb_tcs != %d.",
1321                                                 ETH_4_TCS, ETH_8_TCS);
1322                                 return -EINVAL;
1323                         }
1324                 }
1325
1326                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_DCB) {
1327                         const struct rte_eth_dcb_tx_conf *conf;
1328
1329                         conf = &dev_conf->tx_adv_conf.dcb_tx_conf;
1330                         if (!(conf->nb_tcs == ETH_4_TCS ||
1331                                conf->nb_tcs == ETH_8_TCS)) {
1332                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
1333                                                 " and nb_tcs != %d.",
1334                                                 ETH_4_TCS, ETH_8_TCS);
1335                                 return -EINVAL;
1336                         }
1337                 }
1338         }
1339         return 0;
1340 }
1341
1342 static int
1343 txgbe_dev_configure(struct rte_eth_dev *dev)
1344 {
1345         struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);
1346         struct txgbe_adapter *adapter = TXGBE_DEV_ADAPTER(dev);
1347         int ret;
1348
1349         PMD_INIT_FUNC_TRACE();
1350
1351         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
1352                 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
1353
1354         /* multiple queue mode checking */
1355         ret  = txgbe_check_mq_mode(dev);
1356         if (ret != 0) {
1357                 PMD_DRV_LOG(ERR, "txgbe_check_mq_mode fails with %d.",
1358                             ret);
1359                 return ret;
1360         }
1361
1362         /* set flag to update link status after init */
1363         intr->flags |= TXGBE_FLAG_NEED_LINK_UPDATE;
1364
1365         /*
1366          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
1367          * allocation Rx preconditions we will reset it.
1368          */
1369         adapter->rx_bulk_alloc_allowed = true;
1370
1371         return 0;
1372 }
1373
1374 static void
1375 txgbe_dev_phy_intr_setup(struct rte_eth_dev *dev)
1376 {
1377         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
1378         struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);
1379         uint32_t gpie;
1380
1381         gpie = rd32(hw, TXGBE_GPIOINTEN);
1382         gpie |= TXGBE_GPIOBIT_6;
1383         wr32(hw, TXGBE_GPIOINTEN, gpie);
1384         intr->mask_misc |= TXGBE_ICRMISC_GPIO;
1385 }
1386
1387 int
1388 txgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
1389                         uint16_t tx_rate, uint64_t q_msk)
1390 {
1391         struct txgbe_hw *hw;
1392         struct txgbe_vf_info *vfinfo;
1393         struct rte_eth_link link;
1394         uint8_t  nb_q_per_pool;
1395         uint32_t queue_stride;
1396         uint32_t queue_idx, idx = 0, vf_idx;
1397         uint32_t queue_end;
1398         uint16_t total_rate = 0;
1399         struct rte_pci_device *pci_dev;
1400         int ret;
1401
1402         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1403         ret = rte_eth_link_get_nowait(dev->data->port_id, &link);
1404         if (ret < 0)
1405                 return ret;
1406
1407         if (vf >= pci_dev->max_vfs)
1408                 return -EINVAL;
1409
1410         if (tx_rate > link.link_speed)
1411                 return -EINVAL;
1412
1413         if (q_msk == 0)
1414                 return 0;
1415
1416         hw = TXGBE_DEV_HW(dev);
1417         vfinfo = *(TXGBE_DEV_VFDATA(dev));
1418         nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
1419         queue_stride = TXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
1420         queue_idx = vf * queue_stride;
1421         queue_end = queue_idx + nb_q_per_pool - 1;
1422         if (queue_end >= hw->mac.max_tx_queues)
1423                 return -EINVAL;
1424
1425         if (vfinfo) {
1426                 for (vf_idx = 0; vf_idx < pci_dev->max_vfs; vf_idx++) {
1427                         if (vf_idx == vf)
1428                                 continue;
1429                         for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
1430                                 idx++)
1431                                 total_rate += vfinfo[vf_idx].tx_rate[idx];
1432                 }
1433         } else {
1434                 return -EINVAL;
1435         }
1436
1437         /* Store tx_rate for this vf. */
1438         for (idx = 0; idx < nb_q_per_pool; idx++) {
1439                 if (((uint64_t)0x1 << idx) & q_msk) {
1440                         if (vfinfo[vf].tx_rate[idx] != tx_rate)
1441                                 vfinfo[vf].tx_rate[idx] = tx_rate;
1442                         total_rate += tx_rate;
1443                 }
1444         }
1445
1446         if (total_rate > dev->data->dev_link.link_speed) {
1447                 /* Reset stored TX rate of the VF if it causes exceed
1448                  * link speed.
1449                  */
1450                 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
1451                 return -EINVAL;
1452         }
1453
1454         /* Set ARBTXRATE of each queue/pool for vf X  */
1455         for (; queue_idx <= queue_end; queue_idx++) {
1456                 if (0x1 & q_msk)
1457                         txgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
1458                 q_msk = q_msk >> 1;
1459         }
1460
1461         return 0;
1462 }
1463
1464 /*
1465  * Configure device link speed and setup link.
1466  * It returns 0 on success.
1467  */
1468 static int
1469 txgbe_dev_start(struct rte_eth_dev *dev)
1470 {
1471         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
1472         struct txgbe_hw_stats *hw_stats = TXGBE_DEV_STATS(dev);
1473         struct txgbe_vf_info *vfinfo = *TXGBE_DEV_VFDATA(dev);
1474         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1475         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1476         uint32_t intr_vector = 0;
1477         int err;
1478         bool link_up = false, negotiate = 0;
1479         uint32_t speed = 0;
1480         uint32_t allowed_speeds = 0;
1481         int mask = 0;
1482         int status;
1483         uint16_t vf, idx;
1484         uint32_t *link_speeds;
1485
1486         PMD_INIT_FUNC_TRACE();
1487
1488         /* TXGBE devices don't support:
1489          *    - half duplex (checked afterwards for valid speeds)
1490          *    - fixed speed: TODO implement
1491          */
1492         if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
1493                 PMD_INIT_LOG(ERR,
1494                 "Invalid link_speeds for port %u, fix speed not supported",
1495                                 dev->data->port_id);
1496                 return -EINVAL;
1497         }
1498
1499         /* Stop the link setup handler before resetting the HW. */
1500         rte_eal_alarm_cancel(txgbe_dev_setup_link_alarm_handler, dev);
1501
1502         /* disable uio/vfio intr/eventfd mapping */
1503         rte_intr_disable(intr_handle);
1504
1505         /* stop adapter */
1506         hw->adapter_stopped = 0;
1507         txgbe_stop_hw(hw);
1508
1509         /* reinitialize adapter
1510          * this calls reset and start
1511          */
1512         hw->nb_rx_queues = dev->data->nb_rx_queues;
1513         hw->nb_tx_queues = dev->data->nb_tx_queues;
1514         status = txgbe_pf_reset_hw(hw);
1515         if (status != 0)
1516                 return -1;
1517         hw->mac.start_hw(hw);
1518         hw->mac.get_link_status = true;
1519
1520         /* configure PF module if SRIOV enabled */
1521         txgbe_pf_host_configure(dev);
1522
1523         txgbe_dev_phy_intr_setup(dev);
1524
1525         /* check and configure queue intr-vector mapping */
1526         if ((rte_intr_cap_multiple(intr_handle) ||
1527              !RTE_ETH_DEV_SRIOV(dev).active) &&
1528             dev->data->dev_conf.intr_conf.rxq != 0) {
1529                 intr_vector = dev->data->nb_rx_queues;
1530                 if (rte_intr_efd_enable(intr_handle, intr_vector))
1531                         return -1;
1532         }
1533
1534         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1535                 intr_handle->intr_vec =
1536                         rte_zmalloc("intr_vec",
1537                                     dev->data->nb_rx_queues * sizeof(int), 0);
1538                 if (intr_handle->intr_vec == NULL) {
1539                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
1540                                      " intr_vec", dev->data->nb_rx_queues);
1541                         return -ENOMEM;
1542                 }
1543         }
1544
1545         /* confiugre msix for sleep until rx interrupt */
1546         txgbe_configure_msix(dev);
1547
1548         /* initialize transmission unit */
1549         txgbe_dev_tx_init(dev);
1550
1551         /* This can fail when allocating mbufs for descriptor rings */
1552         err = txgbe_dev_rx_init(dev);
1553         if (err) {
1554                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
1555                 goto error;
1556         }
1557
1558         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
1559                 ETH_VLAN_EXTEND_MASK;
1560         err = txgbe_vlan_offload_config(dev, mask);
1561         if (err) {
1562                 PMD_INIT_LOG(ERR, "Unable to set VLAN offload");
1563                 goto error;
1564         }
1565
1566         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1567                 /* Enable vlan filtering for VMDq */
1568                 txgbe_vmdq_vlan_hw_filter_enable(dev);
1569         }
1570
1571         /* Configure DCB hw */
1572         txgbe_configure_pb(dev);
1573         txgbe_configure_port(dev);
1574         txgbe_configure_dcb(dev);
1575
1576         /* Restore vf rate limit */
1577         if (vfinfo != NULL) {
1578                 for (vf = 0; vf < pci_dev->max_vfs; vf++)
1579                         for (idx = 0; idx < TXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
1580                                 if (vfinfo[vf].tx_rate[idx] != 0)
1581                                         txgbe_set_vf_rate_limit(dev, vf,
1582                                                 vfinfo[vf].tx_rate[idx],
1583                                                 1 << idx);
1584         }
1585
1586         err = txgbe_dev_rxtx_start(dev);
1587         if (err < 0) {
1588                 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
1589                 goto error;
1590         }
1591
1592         /* Skip link setup if loopback mode is enabled. */
1593         if (hw->mac.type == txgbe_mac_raptor &&
1594             dev->data->dev_conf.lpbk_mode)
1595                 goto skip_link_setup;
1596
1597         if (txgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
1598                 err = hw->mac.setup_sfp(hw);
1599                 if (err)
1600                         goto error;
1601         }
1602
1603         if (hw->phy.media_type == txgbe_media_type_copper) {
1604                 /* Turn on the copper */
1605                 hw->phy.set_phy_power(hw, true);
1606         } else {
1607                 /* Turn on the laser */
1608                 hw->mac.enable_tx_laser(hw);
1609         }
1610
1611         err = hw->mac.check_link(hw, &speed, &link_up, 0);
1612         if (err)
1613                 goto error;
1614         dev->data->dev_link.link_status = link_up;
1615
1616         err = hw->mac.get_link_capabilities(hw, &speed, &negotiate);
1617         if (err)
1618                 goto error;
1619
1620         allowed_speeds = ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
1621                         ETH_LINK_SPEED_10G;
1622
1623         link_speeds = &dev->data->dev_conf.link_speeds;
1624         if (*link_speeds & ~allowed_speeds) {
1625                 PMD_INIT_LOG(ERR, "Invalid link setting");
1626                 goto error;
1627         }
1628
1629         speed = 0x0;
1630         if (*link_speeds == ETH_LINK_SPEED_AUTONEG) {
1631                 speed = (TXGBE_LINK_SPEED_100M_FULL |
1632                          TXGBE_LINK_SPEED_1GB_FULL |
1633                          TXGBE_LINK_SPEED_10GB_FULL);
1634         } else {
1635                 if (*link_speeds & ETH_LINK_SPEED_10G)
1636                         speed |= TXGBE_LINK_SPEED_10GB_FULL;
1637                 if (*link_speeds & ETH_LINK_SPEED_5G)
1638                         speed |= TXGBE_LINK_SPEED_5GB_FULL;
1639                 if (*link_speeds & ETH_LINK_SPEED_2_5G)
1640                         speed |= TXGBE_LINK_SPEED_2_5GB_FULL;
1641                 if (*link_speeds & ETH_LINK_SPEED_1G)
1642                         speed |= TXGBE_LINK_SPEED_1GB_FULL;
1643                 if (*link_speeds & ETH_LINK_SPEED_100M)
1644                         speed |= TXGBE_LINK_SPEED_100M_FULL;
1645         }
1646
1647         err = hw->mac.setup_link(hw, speed, link_up);
1648         if (err)
1649                 goto error;
1650
1651 skip_link_setup:
1652
1653         if (rte_intr_allow_others(intr_handle)) {
1654                 /* check if lsc interrupt is enabled */
1655                 if (dev->data->dev_conf.intr_conf.lsc != 0)
1656                         txgbe_dev_lsc_interrupt_setup(dev, TRUE);
1657                 else
1658                         txgbe_dev_lsc_interrupt_setup(dev, FALSE);
1659                 txgbe_dev_macsec_interrupt_setup(dev);
1660                 txgbe_set_ivar_map(hw, -1, 1, TXGBE_MISC_VEC_ID);
1661         } else {
1662                 rte_intr_callback_unregister(intr_handle,
1663                                              txgbe_dev_interrupt_handler, dev);
1664                 if (dev->data->dev_conf.intr_conf.lsc != 0)
1665                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
1666                                      " no intr multiplex");
1667         }
1668
1669         /* check if rxq interrupt is enabled */
1670         if (dev->data->dev_conf.intr_conf.rxq != 0 &&
1671             rte_intr_dp_is_en(intr_handle))
1672                 txgbe_dev_rxq_interrupt_setup(dev);
1673
1674         /* enable uio/vfio intr/eventfd mapping */
1675         rte_intr_enable(intr_handle);
1676
1677         /* resume enabled intr since hw reset */
1678         txgbe_enable_intr(dev);
1679         txgbe_l2_tunnel_conf(dev);
1680         txgbe_filter_restore(dev);
1681
1682         /*
1683          * Update link status right before return, because it may
1684          * start link configuration process in a separate thread.
1685          */
1686         txgbe_dev_link_update(dev, 0);
1687
1688         wr32m(hw, TXGBE_LEDCTL, 0xFFFFFFFF, TXGBE_LEDCTL_ORD_MASK);
1689
1690         txgbe_read_stats_registers(hw, hw_stats);
1691         hw->offset_loaded = 1;
1692
1693         return 0;
1694
1695 error:
1696         PMD_INIT_LOG(ERR, "failure in dev start: %d", err);
1697         txgbe_dev_clear_queues(dev);
1698         return -EIO;
1699 }
1700
1701 /*
1702  * Stop device: disable rx and tx functions to allow for reconfiguring.
1703  */
1704 static int
1705 txgbe_dev_stop(struct rte_eth_dev *dev)
1706 {
1707         struct rte_eth_link link;
1708         struct txgbe_adapter *adapter = TXGBE_DEV_ADAPTER(dev);
1709         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
1710         struct txgbe_vf_info *vfinfo = *TXGBE_DEV_VFDATA(dev);
1711         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1712         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1713         int vf;
1714
1715         if (hw->adapter_stopped)
1716                 return 0;
1717
1718         PMD_INIT_FUNC_TRACE();
1719
1720         rte_eal_alarm_cancel(txgbe_dev_setup_link_alarm_handler, dev);
1721
1722         /* disable interrupts */
1723         txgbe_disable_intr(hw);
1724
1725         /* reset the NIC */
1726         txgbe_pf_reset_hw(hw);
1727         hw->adapter_stopped = 0;
1728
1729         /* stop adapter */
1730         txgbe_stop_hw(hw);
1731
1732         for (vf = 0; vfinfo != NULL && vf < pci_dev->max_vfs; vf++)
1733                 vfinfo[vf].clear_to_send = false;
1734
1735         if (hw->phy.media_type == txgbe_media_type_copper) {
1736                 /* Turn off the copper */
1737                 hw->phy.set_phy_power(hw, false);
1738         } else {
1739                 /* Turn off the laser */
1740                 hw->mac.disable_tx_laser(hw);
1741         }
1742
1743         txgbe_dev_clear_queues(dev);
1744
1745         /* Clear stored conf */
1746         dev->data->scattered_rx = 0;
1747         dev->data->lro = 0;
1748
1749         /* Clear recorded link status */
1750         memset(&link, 0, sizeof(link));
1751         rte_eth_linkstatus_set(dev, &link);
1752
1753         if (!rte_intr_allow_others(intr_handle))
1754                 /* resume to the default handler */
1755                 rte_intr_callback_register(intr_handle,
1756                                            txgbe_dev_interrupt_handler,
1757                                            (void *)dev);
1758
1759         /* Clean datapath event and queue/vec mapping */
1760         rte_intr_efd_disable(intr_handle);
1761         if (intr_handle->intr_vec != NULL) {
1762                 rte_free(intr_handle->intr_vec);
1763                 intr_handle->intr_vec = NULL;
1764         }
1765
1766         adapter->rss_reta_updated = 0;
1767         wr32m(hw, TXGBE_LEDCTL, 0xFFFFFFFF, TXGBE_LEDCTL_SEL_MASK);
1768
1769         hw->adapter_stopped = true;
1770         dev->data->dev_started = 0;
1771
1772         return 0;
1773 }
1774
1775 /*
1776  * Set device link up: enable tx.
1777  */
1778 static int
1779 txgbe_dev_set_link_up(struct rte_eth_dev *dev)
1780 {
1781         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
1782
1783         if (hw->phy.media_type == txgbe_media_type_copper) {
1784                 /* Turn on the copper */
1785                 hw->phy.set_phy_power(hw, true);
1786         } else {
1787                 /* Turn on the laser */
1788                 hw->mac.enable_tx_laser(hw);
1789                 txgbe_dev_link_update(dev, 0);
1790         }
1791
1792         return 0;
1793 }
1794
1795 /*
1796  * Set device link down: disable tx.
1797  */
1798 static int
1799 txgbe_dev_set_link_down(struct rte_eth_dev *dev)
1800 {
1801         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
1802
1803         if (hw->phy.media_type == txgbe_media_type_copper) {
1804                 /* Turn off the copper */
1805                 hw->phy.set_phy_power(hw, false);
1806         } else {
1807                 /* Turn off the laser */
1808                 hw->mac.disable_tx_laser(hw);
1809                 txgbe_dev_link_update(dev, 0);
1810         }
1811
1812         return 0;
1813 }
1814
1815 /*
1816  * Reset and stop device.
1817  */
1818 static int
1819 txgbe_dev_close(struct rte_eth_dev *dev)
1820 {
1821         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
1822         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1823         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1824         int retries = 0;
1825         int ret;
1826
1827         PMD_INIT_FUNC_TRACE();
1828
1829         txgbe_pf_reset_hw(hw);
1830
1831         ret = txgbe_dev_stop(dev);
1832
1833         txgbe_dev_free_queues(dev);
1834
1835         /* reprogram the RAR[0] in case user changed it. */
1836         txgbe_set_rar(hw, 0, hw->mac.addr, 0, true);
1837
1838         /* Unlock any pending hardware semaphore */
1839         txgbe_swfw_lock_reset(hw);
1840
1841         /* disable uio intr before callback unregister */
1842         rte_intr_disable(intr_handle);
1843
1844         do {
1845                 ret = rte_intr_callback_unregister(intr_handle,
1846                                 txgbe_dev_interrupt_handler, dev);
1847                 if (ret >= 0 || ret == -ENOENT) {
1848                         break;
1849                 } else if (ret != -EAGAIN) {
1850                         PMD_INIT_LOG(ERR,
1851                                 "intr callback unregister failed: %d",
1852                                 ret);
1853                 }
1854                 rte_delay_ms(100);
1855         } while (retries++ < (10 + TXGBE_LINK_UP_TIME));
1856
1857         /* cancel the delay handler before remove dev */
1858         rte_eal_alarm_cancel(txgbe_dev_interrupt_delayed_handler, dev);
1859
1860         /* uninitialize PF if max_vfs not zero */
1861         txgbe_pf_host_uninit(dev);
1862
1863         rte_free(dev->data->mac_addrs);
1864         dev->data->mac_addrs = NULL;
1865
1866         rte_free(dev->data->hash_mac_addrs);
1867         dev->data->hash_mac_addrs = NULL;
1868
1869         /* remove all the L2 tunnel filters & hash */
1870         txgbe_l2_tn_filter_uninit(dev);
1871
1872         /* Remove all ntuple filters of the device */
1873         txgbe_ntuple_filter_uninit(dev);
1874
1875         return ret;
1876 }
1877
1878 /*
1879  * Reset PF device.
1880  */
1881 static int
1882 txgbe_dev_reset(struct rte_eth_dev *dev)
1883 {
1884         int ret;
1885
1886         /* When a DPDK PMD PF begin to reset PF port, it should notify all
1887          * its VF to make them align with it. The detailed notification
1888          * mechanism is PMD specific. As to txgbe PF, it is rather complex.
1889          * To avoid unexpected behavior in VF, currently reset of PF with
1890          * SR-IOV activation is not supported. It might be supported later.
1891          */
1892         if (dev->data->sriov.active)
1893                 return -ENOTSUP;
1894
1895         ret = eth_txgbe_dev_uninit(dev);
1896         if (ret)
1897                 return ret;
1898
1899         ret = eth_txgbe_dev_init(dev, NULL);
1900
1901         return ret;
1902 }
1903
1904 #define UPDATE_QP_COUNTER_32bit(reg, last_counter, counter)     \
1905         {                                                       \
1906                 uint32_t current_counter = rd32(hw, reg);       \
1907                 if (current_counter < last_counter)             \
1908                         current_counter += 0x100000000LL;       \
1909                 if (!hw->offset_loaded)                         \
1910                         last_counter = current_counter;         \
1911                 counter = current_counter - last_counter;       \
1912                 counter &= 0xFFFFFFFFLL;                        \
1913         }
1914
1915 #define UPDATE_QP_COUNTER_36bit(reg_lsb, reg_msb, last_counter, counter) \
1916         {                                                                \
1917                 uint64_t current_counter_lsb = rd32(hw, reg_lsb);        \
1918                 uint64_t current_counter_msb = rd32(hw, reg_msb);        \
1919                 uint64_t current_counter = (current_counter_msb << 32) | \
1920                         current_counter_lsb;                             \
1921                 if (current_counter < last_counter)                      \
1922                         current_counter += 0x1000000000LL;               \
1923                 if (!hw->offset_loaded)                                  \
1924                         last_counter = current_counter;                  \
1925                 counter = current_counter - last_counter;                \
1926                 counter &= 0xFFFFFFFFFLL;                                \
1927         }
1928
1929 void
1930 txgbe_read_stats_registers(struct txgbe_hw *hw,
1931                            struct txgbe_hw_stats *hw_stats)
1932 {
1933         unsigned int i;
1934
1935         /* QP Stats */
1936         for (i = 0; i < hw->nb_rx_queues; i++) {
1937                 UPDATE_QP_COUNTER_32bit(TXGBE_QPRXPKT(i),
1938                         hw->qp_last[i].rx_qp_packets,
1939                         hw_stats->qp[i].rx_qp_packets);
1940                 UPDATE_QP_COUNTER_36bit(TXGBE_QPRXOCTL(i), TXGBE_QPRXOCTH(i),
1941                         hw->qp_last[i].rx_qp_bytes,
1942                         hw_stats->qp[i].rx_qp_bytes);
1943                 UPDATE_QP_COUNTER_32bit(TXGBE_QPRXMPKT(i),
1944                         hw->qp_last[i].rx_qp_mc_packets,
1945                         hw_stats->qp[i].rx_qp_mc_packets);
1946         }
1947
1948         for (i = 0; i < hw->nb_tx_queues; i++) {
1949                 UPDATE_QP_COUNTER_32bit(TXGBE_QPTXPKT(i),
1950                         hw->qp_last[i].tx_qp_packets,
1951                         hw_stats->qp[i].tx_qp_packets);
1952                 UPDATE_QP_COUNTER_36bit(TXGBE_QPTXOCTL(i), TXGBE_QPTXOCTH(i),
1953                         hw->qp_last[i].tx_qp_bytes,
1954                         hw_stats->qp[i].tx_qp_bytes);
1955         }
1956         /* PB Stats */
1957         for (i = 0; i < TXGBE_MAX_UP; i++) {
1958                 hw_stats->up[i].rx_up_xon_packets +=
1959                                 rd32(hw, TXGBE_PBRXUPXON(i));
1960                 hw_stats->up[i].rx_up_xoff_packets +=
1961                                 rd32(hw, TXGBE_PBRXUPXOFF(i));
1962                 hw_stats->up[i].tx_up_xon_packets +=
1963                                 rd32(hw, TXGBE_PBTXUPXON(i));
1964                 hw_stats->up[i].tx_up_xoff_packets +=
1965                                 rd32(hw, TXGBE_PBTXUPXOFF(i));
1966                 hw_stats->up[i].tx_up_xon2off_packets +=
1967                                 rd32(hw, TXGBE_PBTXUPOFF(i));
1968                 hw_stats->up[i].rx_up_dropped +=
1969                                 rd32(hw, TXGBE_PBRXMISS(i));
1970         }
1971         hw_stats->rx_xon_packets += rd32(hw, TXGBE_PBRXLNKXON);
1972         hw_stats->rx_xoff_packets += rd32(hw, TXGBE_PBRXLNKXOFF);
1973         hw_stats->tx_xon_packets += rd32(hw, TXGBE_PBTXLNKXON);
1974         hw_stats->tx_xoff_packets += rd32(hw, TXGBE_PBTXLNKXOFF);
1975
1976         /* DMA Stats */
1977         hw_stats->rx_packets += rd32(hw, TXGBE_DMARXPKT);
1978         hw_stats->tx_packets += rd32(hw, TXGBE_DMATXPKT);
1979
1980         hw_stats->rx_bytes += rd64(hw, TXGBE_DMARXOCTL);
1981         hw_stats->tx_bytes += rd64(hw, TXGBE_DMATXOCTL);
1982         hw_stats->rx_drop_packets += rd32(hw, TXGBE_PBRXDROP);
1983
1984         /* MAC Stats */
1985         hw_stats->rx_crc_errors += rd64(hw, TXGBE_MACRXERRCRCL);
1986         hw_stats->rx_multicast_packets += rd64(hw, TXGBE_MACRXMPKTL);
1987         hw_stats->tx_multicast_packets += rd64(hw, TXGBE_MACTXMPKTL);
1988
1989         hw_stats->rx_total_packets += rd64(hw, TXGBE_MACRXPKTL);
1990         hw_stats->tx_total_packets += rd64(hw, TXGBE_MACTXPKTL);
1991         hw_stats->rx_total_bytes += rd64(hw, TXGBE_MACRXGBOCTL);
1992
1993         hw_stats->rx_broadcast_packets += rd64(hw, TXGBE_MACRXOCTL);
1994         hw_stats->tx_broadcast_packets += rd32(hw, TXGBE_MACTXOCTL);
1995
1996         hw_stats->rx_size_64_packets += rd64(hw, TXGBE_MACRX1TO64L);
1997         hw_stats->rx_size_65_to_127_packets += rd64(hw, TXGBE_MACRX65TO127L);
1998         hw_stats->rx_size_128_to_255_packets += rd64(hw, TXGBE_MACRX128TO255L);
1999         hw_stats->rx_size_256_to_511_packets += rd64(hw, TXGBE_MACRX256TO511L);
2000         hw_stats->rx_size_512_to_1023_packets +=
2001                         rd64(hw, TXGBE_MACRX512TO1023L);
2002         hw_stats->rx_size_1024_to_max_packets +=
2003                         rd64(hw, TXGBE_MACRX1024TOMAXL);
2004         hw_stats->tx_size_64_packets += rd64(hw, TXGBE_MACTX1TO64L);
2005         hw_stats->tx_size_65_to_127_packets += rd64(hw, TXGBE_MACTX65TO127L);
2006         hw_stats->tx_size_128_to_255_packets += rd64(hw, TXGBE_MACTX128TO255L);
2007         hw_stats->tx_size_256_to_511_packets += rd64(hw, TXGBE_MACTX256TO511L);
2008         hw_stats->tx_size_512_to_1023_packets +=
2009                         rd64(hw, TXGBE_MACTX512TO1023L);
2010         hw_stats->tx_size_1024_to_max_packets +=
2011                         rd64(hw, TXGBE_MACTX1024TOMAXL);
2012
2013         hw_stats->rx_undersize_errors += rd64(hw, TXGBE_MACRXERRLENL);
2014         hw_stats->rx_oversize_errors += rd32(hw, TXGBE_MACRXOVERSIZE);
2015         hw_stats->rx_jabber_errors += rd32(hw, TXGBE_MACRXJABBER);
2016
2017         /* MNG Stats */
2018         hw_stats->mng_bmc2host_packets = rd32(hw, TXGBE_MNGBMC2OS);
2019         hw_stats->mng_host2bmc_packets = rd32(hw, TXGBE_MNGOS2BMC);
2020         hw_stats->rx_management_packets = rd32(hw, TXGBE_DMARXMNG);
2021         hw_stats->tx_management_packets = rd32(hw, TXGBE_DMATXMNG);
2022
2023         /* FCoE Stats */
2024         hw_stats->rx_fcoe_crc_errors += rd32(hw, TXGBE_FCOECRC);
2025         hw_stats->rx_fcoe_mbuf_allocation_errors += rd32(hw, TXGBE_FCOELAST);
2026         hw_stats->rx_fcoe_dropped += rd32(hw, TXGBE_FCOERPDC);
2027         hw_stats->rx_fcoe_packets += rd32(hw, TXGBE_FCOEPRC);
2028         hw_stats->tx_fcoe_packets += rd32(hw, TXGBE_FCOEPTC);
2029         hw_stats->rx_fcoe_bytes += rd32(hw, TXGBE_FCOEDWRC);
2030         hw_stats->tx_fcoe_bytes += rd32(hw, TXGBE_FCOEDWTC);
2031
2032         /* Flow Director Stats */
2033         hw_stats->flow_director_matched_filters += rd32(hw, TXGBE_FDIRMATCH);
2034         hw_stats->flow_director_missed_filters += rd32(hw, TXGBE_FDIRMISS);
2035         hw_stats->flow_director_added_filters +=
2036                 TXGBE_FDIRUSED_ADD(rd32(hw, TXGBE_FDIRUSED));
2037         hw_stats->flow_director_removed_filters +=
2038                 TXGBE_FDIRUSED_REM(rd32(hw, TXGBE_FDIRUSED));
2039         hw_stats->flow_director_filter_add_errors +=
2040                 TXGBE_FDIRFAIL_ADD(rd32(hw, TXGBE_FDIRFAIL));
2041         hw_stats->flow_director_filter_remove_errors +=
2042                 TXGBE_FDIRFAIL_REM(rd32(hw, TXGBE_FDIRFAIL));
2043
2044         /* MACsec Stats */
2045         hw_stats->tx_macsec_pkts_untagged += rd32(hw, TXGBE_LSECTX_UTPKT);
2046         hw_stats->tx_macsec_pkts_encrypted +=
2047                         rd32(hw, TXGBE_LSECTX_ENCPKT);
2048         hw_stats->tx_macsec_pkts_protected +=
2049                         rd32(hw, TXGBE_LSECTX_PROTPKT);
2050         hw_stats->tx_macsec_octets_encrypted +=
2051                         rd32(hw, TXGBE_LSECTX_ENCOCT);
2052         hw_stats->tx_macsec_octets_protected +=
2053                         rd32(hw, TXGBE_LSECTX_PROTOCT);
2054         hw_stats->rx_macsec_pkts_untagged += rd32(hw, TXGBE_LSECRX_UTPKT);
2055         hw_stats->rx_macsec_pkts_badtag += rd32(hw, TXGBE_LSECRX_BTPKT);
2056         hw_stats->rx_macsec_pkts_nosci += rd32(hw, TXGBE_LSECRX_NOSCIPKT);
2057         hw_stats->rx_macsec_pkts_unknownsci += rd32(hw, TXGBE_LSECRX_UNSCIPKT);
2058         hw_stats->rx_macsec_octets_decrypted += rd32(hw, TXGBE_LSECRX_DECOCT);
2059         hw_stats->rx_macsec_octets_validated += rd32(hw, TXGBE_LSECRX_VLDOCT);
2060         hw_stats->rx_macsec_sc_pkts_unchecked +=
2061                         rd32(hw, TXGBE_LSECRX_UNCHKPKT);
2062         hw_stats->rx_macsec_sc_pkts_delayed += rd32(hw, TXGBE_LSECRX_DLYPKT);
2063         hw_stats->rx_macsec_sc_pkts_late += rd32(hw, TXGBE_LSECRX_LATEPKT);
2064         for (i = 0; i < 2; i++) {
2065                 hw_stats->rx_macsec_sa_pkts_ok +=
2066                         rd32(hw, TXGBE_LSECRX_OKPKT(i));
2067                 hw_stats->rx_macsec_sa_pkts_invalid +=
2068                         rd32(hw, TXGBE_LSECRX_INVPKT(i));
2069                 hw_stats->rx_macsec_sa_pkts_notvalid +=
2070                         rd32(hw, TXGBE_LSECRX_BADPKT(i));
2071         }
2072         hw_stats->rx_macsec_sa_pkts_unusedsa +=
2073                         rd32(hw, TXGBE_LSECRX_INVSAPKT);
2074         hw_stats->rx_macsec_sa_pkts_notusingsa +=
2075                         rd32(hw, TXGBE_LSECRX_BADSAPKT);
2076
2077         hw_stats->rx_total_missed_packets = 0;
2078         for (i = 0; i < TXGBE_MAX_UP; i++) {
2079                 hw_stats->rx_total_missed_packets +=
2080                         hw_stats->up[i].rx_up_dropped;
2081         }
2082 }
2083
2084 static int
2085 txgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2086 {
2087         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2088         struct txgbe_hw_stats *hw_stats = TXGBE_DEV_STATS(dev);
2089         struct txgbe_stat_mappings *stat_mappings =
2090                         TXGBE_DEV_STAT_MAPPINGS(dev);
2091         uint32_t i, j;
2092
2093         txgbe_read_stats_registers(hw, hw_stats);
2094
2095         if (stats == NULL)
2096                 return -EINVAL;
2097
2098         /* Fill out the rte_eth_stats statistics structure */
2099         stats->ipackets = hw_stats->rx_packets;
2100         stats->ibytes = hw_stats->rx_bytes;
2101         stats->opackets = hw_stats->tx_packets;
2102         stats->obytes = hw_stats->tx_bytes;
2103
2104         memset(&stats->q_ipackets, 0, sizeof(stats->q_ipackets));
2105         memset(&stats->q_opackets, 0, sizeof(stats->q_opackets));
2106         memset(&stats->q_ibytes, 0, sizeof(stats->q_ibytes));
2107         memset(&stats->q_obytes, 0, sizeof(stats->q_obytes));
2108         memset(&stats->q_errors, 0, sizeof(stats->q_errors));
2109         for (i = 0; i < TXGBE_MAX_QP; i++) {
2110                 uint32_t n = i / NB_QMAP_FIELDS_PER_QSM_REG;
2111                 uint32_t offset = (i % NB_QMAP_FIELDS_PER_QSM_REG) * 8;
2112                 uint32_t q_map;
2113
2114                 q_map = (stat_mappings->rqsm[n] >> offset)
2115                                 & QMAP_FIELD_RESERVED_BITS_MASK;
2116                 j = (q_map < RTE_ETHDEV_QUEUE_STAT_CNTRS
2117                      ? q_map : q_map % RTE_ETHDEV_QUEUE_STAT_CNTRS);
2118                 stats->q_ipackets[j] += hw_stats->qp[i].rx_qp_packets;
2119                 stats->q_ibytes[j] += hw_stats->qp[i].rx_qp_bytes;
2120
2121                 q_map = (stat_mappings->tqsm[n] >> offset)
2122                                 & QMAP_FIELD_RESERVED_BITS_MASK;
2123                 j = (q_map < RTE_ETHDEV_QUEUE_STAT_CNTRS
2124                      ? q_map : q_map % RTE_ETHDEV_QUEUE_STAT_CNTRS);
2125                 stats->q_opackets[j] += hw_stats->qp[i].tx_qp_packets;
2126                 stats->q_obytes[j] += hw_stats->qp[i].tx_qp_bytes;
2127         }
2128
2129         /* Rx Errors */
2130         stats->imissed  = hw_stats->rx_total_missed_packets;
2131         stats->ierrors  = hw_stats->rx_crc_errors +
2132                           hw_stats->rx_mac_short_packet_dropped +
2133                           hw_stats->rx_length_errors +
2134                           hw_stats->rx_undersize_errors +
2135                           hw_stats->rx_oversize_errors +
2136                           hw_stats->rx_drop_packets +
2137                           hw_stats->rx_illegal_byte_errors +
2138                           hw_stats->rx_error_bytes +
2139                           hw_stats->rx_fragment_errors +
2140                           hw_stats->rx_fcoe_crc_errors +
2141                           hw_stats->rx_fcoe_mbuf_allocation_errors;
2142
2143         /* Tx Errors */
2144         stats->oerrors  = 0;
2145         return 0;
2146 }
2147
2148 static int
2149 txgbe_dev_stats_reset(struct rte_eth_dev *dev)
2150 {
2151         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2152         struct txgbe_hw_stats *hw_stats = TXGBE_DEV_STATS(dev);
2153
2154         /* HW registers are cleared on read */
2155         hw->offset_loaded = 0;
2156         txgbe_dev_stats_get(dev, NULL);
2157         hw->offset_loaded = 1;
2158
2159         /* Reset software totals */
2160         memset(hw_stats, 0, sizeof(*hw_stats));
2161
2162         return 0;
2163 }
2164
2165 /* This function calculates the number of xstats based on the current config */
2166 static unsigned
2167 txgbe_xstats_calc_num(struct rte_eth_dev *dev)
2168 {
2169         int nb_queues = max(dev->data->nb_rx_queues, dev->data->nb_tx_queues);
2170         return TXGBE_NB_HW_STATS +
2171                TXGBE_NB_UP_STATS * TXGBE_MAX_UP +
2172                TXGBE_NB_QP_STATS * nb_queues;
2173 }
2174
2175 static inline int
2176 txgbe_get_name_by_id(uint32_t id, char *name, uint32_t size)
2177 {
2178         int nb, st;
2179
2180         /* Extended stats from txgbe_hw_stats */
2181         if (id < TXGBE_NB_HW_STATS) {
2182                 snprintf(name, size, "[hw]%s",
2183                         rte_txgbe_stats_strings[id].name);
2184                 return 0;
2185         }
2186         id -= TXGBE_NB_HW_STATS;
2187
2188         /* Priority Stats */
2189         if (id < TXGBE_NB_UP_STATS * TXGBE_MAX_UP) {
2190                 nb = id / TXGBE_NB_UP_STATS;
2191                 st = id % TXGBE_NB_UP_STATS;
2192                 snprintf(name, size, "[p%u]%s", nb,
2193                         rte_txgbe_up_strings[st].name);
2194                 return 0;
2195         }
2196         id -= TXGBE_NB_UP_STATS * TXGBE_MAX_UP;
2197
2198         /* Queue Stats */
2199         if (id < TXGBE_NB_QP_STATS * TXGBE_MAX_QP) {
2200                 nb = id / TXGBE_NB_QP_STATS;
2201                 st = id % TXGBE_NB_QP_STATS;
2202                 snprintf(name, size, "[q%u]%s", nb,
2203                         rte_txgbe_qp_strings[st].name);
2204                 return 0;
2205         }
2206         id -= TXGBE_NB_QP_STATS * TXGBE_MAX_QP;
2207
2208         return -(int)(id + 1);
2209 }
2210
2211 static inline int
2212 txgbe_get_offset_by_id(uint32_t id, uint32_t *offset)
2213 {
2214         int nb, st;
2215
2216         /* Extended stats from txgbe_hw_stats */
2217         if (id < TXGBE_NB_HW_STATS) {
2218                 *offset = rte_txgbe_stats_strings[id].offset;
2219                 return 0;
2220         }
2221         id -= TXGBE_NB_HW_STATS;
2222
2223         /* Priority Stats */
2224         if (id < TXGBE_NB_UP_STATS * TXGBE_MAX_UP) {
2225                 nb = id / TXGBE_NB_UP_STATS;
2226                 st = id % TXGBE_NB_UP_STATS;
2227                 *offset = rte_txgbe_up_strings[st].offset +
2228                         nb * (TXGBE_NB_UP_STATS * sizeof(uint64_t));
2229                 return 0;
2230         }
2231         id -= TXGBE_NB_UP_STATS * TXGBE_MAX_UP;
2232
2233         /* Queue Stats */
2234         if (id < TXGBE_NB_QP_STATS * TXGBE_MAX_QP) {
2235                 nb = id / TXGBE_NB_QP_STATS;
2236                 st = id % TXGBE_NB_QP_STATS;
2237                 *offset = rte_txgbe_qp_strings[st].offset +
2238                         nb * (TXGBE_NB_QP_STATS * sizeof(uint64_t));
2239                 return 0;
2240         }
2241
2242         return -1;
2243 }
2244
2245 static int txgbe_dev_xstats_get_names(struct rte_eth_dev *dev,
2246         struct rte_eth_xstat_name *xstats_names, unsigned int limit)
2247 {
2248         unsigned int i, count;
2249
2250         count = txgbe_xstats_calc_num(dev);
2251         if (xstats_names == NULL)
2252                 return count;
2253
2254         /* Note: limit >= cnt_stats checked upstream
2255          * in rte_eth_xstats_names()
2256          */
2257         limit = min(limit, count);
2258
2259         /* Extended stats from txgbe_hw_stats */
2260         for (i = 0; i < limit; i++) {
2261                 if (txgbe_get_name_by_id(i, xstats_names[i].name,
2262                         sizeof(xstats_names[i].name))) {
2263                         PMD_INIT_LOG(WARNING, "id value %d isn't valid", i);
2264                         break;
2265                 }
2266         }
2267
2268         return i;
2269 }
2270
2271 static int txgbe_dev_xstats_get_names_by_id(struct rte_eth_dev *dev,
2272         struct rte_eth_xstat_name *xstats_names,
2273         const uint64_t *ids,
2274         unsigned int limit)
2275 {
2276         unsigned int i;
2277
2278         if (ids == NULL)
2279                 return txgbe_dev_xstats_get_names(dev, xstats_names, limit);
2280
2281         for (i = 0; i < limit; i++) {
2282                 if (txgbe_get_name_by_id(ids[i], xstats_names[i].name,
2283                                 sizeof(xstats_names[i].name))) {
2284                         PMD_INIT_LOG(WARNING, "id value %d isn't valid", i);
2285                         return -1;
2286                 }
2287         }
2288
2289         return i;
2290 }
2291
2292 static int
2293 txgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2294                                          unsigned int limit)
2295 {
2296         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2297         struct txgbe_hw_stats *hw_stats = TXGBE_DEV_STATS(dev);
2298         unsigned int i, count;
2299
2300         txgbe_read_stats_registers(hw, hw_stats);
2301
2302         /* If this is a reset xstats is NULL, and we have cleared the
2303          * registers by reading them.
2304          */
2305         count = txgbe_xstats_calc_num(dev);
2306         if (xstats == NULL)
2307                 return count;
2308
2309         limit = min(limit, txgbe_xstats_calc_num(dev));
2310
2311         /* Extended stats from txgbe_hw_stats */
2312         for (i = 0; i < limit; i++) {
2313                 uint32_t offset = 0;
2314
2315                 if (txgbe_get_offset_by_id(i, &offset)) {
2316                         PMD_INIT_LOG(WARNING, "id value %d isn't valid", i);
2317                         break;
2318                 }
2319                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) + offset);
2320                 xstats[i].id = i;
2321         }
2322
2323         return i;
2324 }
2325
2326 static int
2327 txgbe_dev_xstats_get_(struct rte_eth_dev *dev, uint64_t *values,
2328                                          unsigned int limit)
2329 {
2330         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2331         struct txgbe_hw_stats *hw_stats = TXGBE_DEV_STATS(dev);
2332         unsigned int i, count;
2333
2334         txgbe_read_stats_registers(hw, hw_stats);
2335
2336         /* If this is a reset xstats is NULL, and we have cleared the
2337          * registers by reading them.
2338          */
2339         count = txgbe_xstats_calc_num(dev);
2340         if (values == NULL)
2341                 return count;
2342
2343         limit = min(limit, txgbe_xstats_calc_num(dev));
2344
2345         /* Extended stats from txgbe_hw_stats */
2346         for (i = 0; i < limit; i++) {
2347                 uint32_t offset;
2348
2349                 if (txgbe_get_offset_by_id(i, &offset)) {
2350                         PMD_INIT_LOG(WARNING, "id value %d isn't valid", i);
2351                         break;
2352                 }
2353                 values[i] = *(uint64_t *)(((char *)hw_stats) + offset);
2354         }
2355
2356         return i;
2357 }
2358
2359 static int
2360 txgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
2361                 uint64_t *values, unsigned int limit)
2362 {
2363         struct txgbe_hw_stats *hw_stats = TXGBE_DEV_STATS(dev);
2364         unsigned int i;
2365
2366         if (ids == NULL)
2367                 return txgbe_dev_xstats_get_(dev, values, limit);
2368
2369         for (i = 0; i < limit; i++) {
2370                 uint32_t offset;
2371
2372                 if (txgbe_get_offset_by_id(ids[i], &offset)) {
2373                         PMD_INIT_LOG(WARNING, "id value %d isn't valid", i);
2374                         break;
2375                 }
2376                 values[i] = *(uint64_t *)(((char *)hw_stats) + offset);
2377         }
2378
2379         return i;
2380 }
2381
2382 static int
2383 txgbe_dev_xstats_reset(struct rte_eth_dev *dev)
2384 {
2385         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2386         struct txgbe_hw_stats *hw_stats = TXGBE_DEV_STATS(dev);
2387
2388         /* HW registers are cleared on read */
2389         hw->offset_loaded = 0;
2390         txgbe_read_stats_registers(hw, hw_stats);
2391         hw->offset_loaded = 1;
2392
2393         /* Reset software totals */
2394         memset(hw_stats, 0, sizeof(*hw_stats));
2395
2396         return 0;
2397 }
2398
2399 static int
2400 txgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
2401 {
2402         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2403         u16 eeprom_verh, eeprom_verl;
2404         u32 etrack_id;
2405         int ret;
2406
2407         hw->rom.readw_sw(hw, TXGBE_EEPROM_VERSION_H, &eeprom_verh);
2408         hw->rom.readw_sw(hw, TXGBE_EEPROM_VERSION_L, &eeprom_verl);
2409
2410         etrack_id = (eeprom_verh << 16) | eeprom_verl;
2411         ret = snprintf(fw_version, fw_size, "0x%08x", etrack_id);
2412
2413         ret += 1; /* add the size of '\0' */
2414         if (fw_size < (u32)ret)
2415                 return ret;
2416         else
2417                 return 0;
2418 }
2419
2420 static int
2421 txgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2422 {
2423         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2424         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2425
2426         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
2427         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
2428         dev_info->min_rx_bufsize = 1024;
2429         dev_info->max_rx_pktlen = 15872;
2430         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
2431         dev_info->max_hash_mac_addrs = TXGBE_VMDQ_NUM_UC_MAC;
2432         dev_info->max_vfs = pci_dev->max_vfs;
2433         dev_info->max_vmdq_pools = ETH_64_POOLS;
2434         dev_info->vmdq_queue_num = dev_info->max_rx_queues;
2435         dev_info->rx_queue_offload_capa = txgbe_get_rx_queue_offloads(dev);
2436         dev_info->rx_offload_capa = (txgbe_get_rx_port_offloads(dev) |
2437                                      dev_info->rx_queue_offload_capa);
2438         dev_info->tx_queue_offload_capa = txgbe_get_tx_queue_offloads(dev);
2439         dev_info->tx_offload_capa = txgbe_get_tx_port_offloads(dev);
2440
2441         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2442                 .rx_thresh = {
2443                         .pthresh = TXGBE_DEFAULT_RX_PTHRESH,
2444                         .hthresh = TXGBE_DEFAULT_RX_HTHRESH,
2445                         .wthresh = TXGBE_DEFAULT_RX_WTHRESH,
2446                 },
2447                 .rx_free_thresh = TXGBE_DEFAULT_RX_FREE_THRESH,
2448                 .rx_drop_en = 0,
2449                 .offloads = 0,
2450         };
2451
2452         dev_info->default_txconf = (struct rte_eth_txconf) {
2453                 .tx_thresh = {
2454                         .pthresh = TXGBE_DEFAULT_TX_PTHRESH,
2455                         .hthresh = TXGBE_DEFAULT_TX_HTHRESH,
2456                         .wthresh = TXGBE_DEFAULT_TX_WTHRESH,
2457                 },
2458                 .tx_free_thresh = TXGBE_DEFAULT_TX_FREE_THRESH,
2459                 .offloads = 0,
2460         };
2461
2462         dev_info->rx_desc_lim = rx_desc_lim;
2463         dev_info->tx_desc_lim = tx_desc_lim;
2464
2465         dev_info->hash_key_size = TXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
2466         dev_info->reta_size = ETH_RSS_RETA_SIZE_128;
2467         dev_info->flow_type_rss_offloads = TXGBE_RSS_OFFLOAD_ALL;
2468
2469         dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
2470         dev_info->speed_capa |= ETH_LINK_SPEED_100M;
2471
2472         /* Driver-preferred Rx/Tx parameters */
2473         dev_info->default_rxportconf.burst_size = 32;
2474         dev_info->default_txportconf.burst_size = 32;
2475         dev_info->default_rxportconf.nb_queues = 1;
2476         dev_info->default_txportconf.nb_queues = 1;
2477         dev_info->default_rxportconf.ring_size = 256;
2478         dev_info->default_txportconf.ring_size = 256;
2479
2480         return 0;
2481 }
2482
2483 const uint32_t *
2484 txgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev)
2485 {
2486         if (dev->rx_pkt_burst == txgbe_recv_pkts ||
2487             dev->rx_pkt_burst == txgbe_recv_pkts_lro_single_alloc ||
2488             dev->rx_pkt_burst == txgbe_recv_pkts_lro_bulk_alloc ||
2489             dev->rx_pkt_burst == txgbe_recv_pkts_bulk_alloc)
2490                 return txgbe_get_supported_ptypes();
2491
2492         return NULL;
2493 }
2494
2495 void
2496 txgbe_dev_setup_link_alarm_handler(void *param)
2497 {
2498         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2499         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2500         struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);
2501         u32 speed;
2502         bool autoneg = false;
2503
2504         speed = hw->phy.autoneg_advertised;
2505         if (!speed)
2506                 hw->mac.get_link_capabilities(hw, &speed, &autoneg);
2507
2508         hw->mac.setup_link(hw, speed, true);
2509
2510         intr->flags &= ~TXGBE_FLAG_NEED_LINK_CONFIG;
2511 }
2512
2513 /* return 0 means link status changed, -1 means not changed */
2514 int
2515 txgbe_dev_link_update_share(struct rte_eth_dev *dev,
2516                             int wait_to_complete)
2517 {
2518         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2519         struct rte_eth_link link;
2520         u32 link_speed = TXGBE_LINK_SPEED_UNKNOWN;
2521         struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);
2522         bool link_up;
2523         int err;
2524         int wait = 1;
2525
2526         memset(&link, 0, sizeof(link));
2527         link.link_status = ETH_LINK_DOWN;
2528         link.link_speed = ETH_SPEED_NUM_NONE;
2529         link.link_duplex = ETH_LINK_HALF_DUPLEX;
2530         link.link_autoneg = ETH_LINK_AUTONEG;
2531
2532         hw->mac.get_link_status = true;
2533
2534         if (intr->flags & TXGBE_FLAG_NEED_LINK_CONFIG)
2535                 return rte_eth_linkstatus_set(dev, &link);
2536
2537         /* check if it needs to wait to complete, if lsc interrupt is enabled */
2538         if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
2539                 wait = 0;
2540
2541         err = hw->mac.check_link(hw, &link_speed, &link_up, wait);
2542
2543         if (err != 0) {
2544                 link.link_speed = ETH_SPEED_NUM_100M;
2545                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
2546                 return rte_eth_linkstatus_set(dev, &link);
2547         }
2548
2549         if (link_up == 0) {
2550                 if (hw->phy.media_type == txgbe_media_type_fiber) {
2551                         intr->flags |= TXGBE_FLAG_NEED_LINK_CONFIG;
2552                         rte_eal_alarm_set(10,
2553                                 txgbe_dev_setup_link_alarm_handler, dev);
2554                 }
2555                 return rte_eth_linkstatus_set(dev, &link);
2556         }
2557
2558         intr->flags &= ~TXGBE_FLAG_NEED_LINK_CONFIG;
2559         link.link_status = ETH_LINK_UP;
2560         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2561
2562         switch (link_speed) {
2563         default:
2564         case TXGBE_LINK_SPEED_UNKNOWN:
2565                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
2566                 link.link_speed = ETH_SPEED_NUM_100M;
2567                 break;
2568
2569         case TXGBE_LINK_SPEED_100M_FULL:
2570                 link.link_speed = ETH_SPEED_NUM_100M;
2571                 break;
2572
2573         case TXGBE_LINK_SPEED_1GB_FULL:
2574                 link.link_speed = ETH_SPEED_NUM_1G;
2575                 break;
2576
2577         case TXGBE_LINK_SPEED_2_5GB_FULL:
2578                 link.link_speed = ETH_SPEED_NUM_2_5G;
2579                 break;
2580
2581         case TXGBE_LINK_SPEED_5GB_FULL:
2582                 link.link_speed = ETH_SPEED_NUM_5G;
2583                 break;
2584
2585         case TXGBE_LINK_SPEED_10GB_FULL:
2586                 link.link_speed = ETH_SPEED_NUM_10G;
2587                 break;
2588         }
2589
2590         return rte_eth_linkstatus_set(dev, &link);
2591 }
2592
2593 static int
2594 txgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
2595 {
2596         return txgbe_dev_link_update_share(dev, wait_to_complete);
2597 }
2598
2599 static int
2600 txgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
2601 {
2602         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2603         uint32_t fctrl;
2604
2605         fctrl = rd32(hw, TXGBE_PSRCTL);
2606         fctrl |= (TXGBE_PSRCTL_UCP | TXGBE_PSRCTL_MCP);
2607         wr32(hw, TXGBE_PSRCTL, fctrl);
2608
2609         return 0;
2610 }
2611
2612 static int
2613 txgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
2614 {
2615         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2616         uint32_t fctrl;
2617
2618         fctrl = rd32(hw, TXGBE_PSRCTL);
2619         fctrl &= (~TXGBE_PSRCTL_UCP);
2620         if (dev->data->all_multicast == 1)
2621                 fctrl |= TXGBE_PSRCTL_MCP;
2622         else
2623                 fctrl &= (~TXGBE_PSRCTL_MCP);
2624         wr32(hw, TXGBE_PSRCTL, fctrl);
2625
2626         return 0;
2627 }
2628
2629 static int
2630 txgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
2631 {
2632         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2633         uint32_t fctrl;
2634
2635         fctrl = rd32(hw, TXGBE_PSRCTL);
2636         fctrl |= TXGBE_PSRCTL_MCP;
2637         wr32(hw, TXGBE_PSRCTL, fctrl);
2638
2639         return 0;
2640 }
2641
2642 static int
2643 txgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
2644 {
2645         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2646         uint32_t fctrl;
2647
2648         if (dev->data->promiscuous == 1)
2649                 return 0; /* must remain in all_multicast mode */
2650
2651         fctrl = rd32(hw, TXGBE_PSRCTL);
2652         fctrl &= (~TXGBE_PSRCTL_MCP);
2653         wr32(hw, TXGBE_PSRCTL, fctrl);
2654
2655         return 0;
2656 }
2657
2658 /**
2659  * It clears the interrupt causes and enables the interrupt.
2660  * It will be called once only during nic initialized.
2661  *
2662  * @param dev
2663  *  Pointer to struct rte_eth_dev.
2664  * @param on
2665  *  Enable or Disable.
2666  *
2667  * @return
2668  *  - On success, zero.
2669  *  - On failure, a negative value.
2670  */
2671 static int
2672 txgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on)
2673 {
2674         struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);
2675
2676         txgbe_dev_link_status_print(dev);
2677         if (on)
2678                 intr->mask_misc |= TXGBE_ICRMISC_LSC;
2679         else
2680                 intr->mask_misc &= ~TXGBE_ICRMISC_LSC;
2681
2682         return 0;
2683 }
2684
2685 /**
2686  * It clears the interrupt causes and enables the interrupt.
2687  * It will be called once only during nic initialized.
2688  *
2689  * @param dev
2690  *  Pointer to struct rte_eth_dev.
2691  *
2692  * @return
2693  *  - On success, zero.
2694  *  - On failure, a negative value.
2695  */
2696 static int
2697 txgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
2698 {
2699         struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);
2700
2701         intr->mask[0] |= TXGBE_ICR_MASK;
2702         intr->mask[1] |= TXGBE_ICR_MASK;
2703
2704         return 0;
2705 }
2706
2707 /**
2708  * It clears the interrupt causes and enables the interrupt.
2709  * It will be called once only during nic initialized.
2710  *
2711  * @param dev
2712  *  Pointer to struct rte_eth_dev.
2713  *
2714  * @return
2715  *  - On success, zero.
2716  *  - On failure, a negative value.
2717  */
2718 static int
2719 txgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev)
2720 {
2721         struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);
2722
2723         intr->mask_misc |= TXGBE_ICRMISC_LNKSEC;
2724
2725         return 0;
2726 }
2727
2728 /*
2729  * It reads ICR and sets flag (TXGBE_ICRMISC_LSC) for the link_update.
2730  *
2731  * @param dev
2732  *  Pointer to struct rte_eth_dev.
2733  *
2734  * @return
2735  *  - On success, zero.
2736  *  - On failure, a negative value.
2737  */
2738 static int
2739 txgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
2740 {
2741         uint32_t eicr;
2742         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2743         struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);
2744
2745         /* clear all cause mask */
2746         txgbe_disable_intr(hw);
2747
2748         /* read-on-clear nic registers here */
2749         eicr = ((u32 *)hw->isb_mem)[TXGBE_ISB_MISC];
2750         PMD_DRV_LOG(DEBUG, "eicr %x", eicr);
2751
2752         intr->flags = 0;
2753
2754         /* set flag for async link update */
2755         if (eicr & TXGBE_ICRMISC_LSC)
2756                 intr->flags |= TXGBE_FLAG_NEED_LINK_UPDATE;
2757
2758         if (eicr & TXGBE_ICRMISC_VFMBX)
2759                 intr->flags |= TXGBE_FLAG_MAILBOX;
2760
2761         if (eicr & TXGBE_ICRMISC_LNKSEC)
2762                 intr->flags |= TXGBE_FLAG_MACSEC;
2763
2764         if (eicr & TXGBE_ICRMISC_GPIO)
2765                 intr->flags |= TXGBE_FLAG_PHY_INTERRUPT;
2766
2767         return 0;
2768 }
2769
2770 /**
2771  * It gets and then prints the link status.
2772  *
2773  * @param dev
2774  *  Pointer to struct rte_eth_dev.
2775  *
2776  * @return
2777  *  - On success, zero.
2778  *  - On failure, a negative value.
2779  */
2780 static void
2781 txgbe_dev_link_status_print(struct rte_eth_dev *dev)
2782 {
2783         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2784         struct rte_eth_link link;
2785
2786         rte_eth_linkstatus_get(dev, &link);
2787
2788         if (link.link_status) {
2789                 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
2790                                         (int)(dev->data->port_id),
2791                                         (unsigned int)link.link_speed,
2792                         link.link_duplex == ETH_LINK_FULL_DUPLEX ?
2793                                         "full-duplex" : "half-duplex");
2794         } else {
2795                 PMD_INIT_LOG(INFO, " Port %d: Link Down",
2796                                 (int)(dev->data->port_id));
2797         }
2798         PMD_INIT_LOG(DEBUG, "PCI Address: " PCI_PRI_FMT,
2799                                 pci_dev->addr.domain,
2800                                 pci_dev->addr.bus,
2801                                 pci_dev->addr.devid,
2802                                 pci_dev->addr.function);
2803 }
2804
2805 /*
2806  * It executes link_update after knowing an interrupt occurred.
2807  *
2808  * @param dev
2809  *  Pointer to struct rte_eth_dev.
2810  *
2811  * @return
2812  *  - On success, zero.
2813  *  - On failure, a negative value.
2814  */
2815 static int
2816 txgbe_dev_interrupt_action(struct rte_eth_dev *dev,
2817                            struct rte_intr_handle *intr_handle)
2818 {
2819         struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);
2820         int64_t timeout;
2821         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2822
2823         PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
2824
2825         if (intr->flags & TXGBE_FLAG_MAILBOX) {
2826                 txgbe_pf_mbx_process(dev);
2827                 intr->flags &= ~TXGBE_FLAG_MAILBOX;
2828         }
2829
2830         if (intr->flags & TXGBE_FLAG_PHY_INTERRUPT) {
2831                 hw->phy.handle_lasi(hw);
2832                 intr->flags &= ~TXGBE_FLAG_PHY_INTERRUPT;
2833         }
2834
2835         if (intr->flags & TXGBE_FLAG_NEED_LINK_UPDATE) {
2836                 struct rte_eth_link link;
2837
2838                 /*get the link status before link update, for predicting later*/
2839                 rte_eth_linkstatus_get(dev, &link);
2840
2841                 txgbe_dev_link_update(dev, 0);
2842
2843                 /* likely to up */
2844                 if (!link.link_status)
2845                         /* handle it 1 sec later, wait it being stable */
2846                         timeout = TXGBE_LINK_UP_CHECK_TIMEOUT;
2847                 /* likely to down */
2848                 else
2849                         /* handle it 4 sec later, wait it being stable */
2850                         timeout = TXGBE_LINK_DOWN_CHECK_TIMEOUT;
2851
2852                 txgbe_dev_link_status_print(dev);
2853                 if (rte_eal_alarm_set(timeout * 1000,
2854                                       txgbe_dev_interrupt_delayed_handler,
2855                                       (void *)dev) < 0) {
2856                         PMD_DRV_LOG(ERR, "Error setting alarm");
2857                 } else {
2858                         /* remember original mask */
2859                         intr->mask_misc_orig = intr->mask_misc;
2860                         /* only disable lsc interrupt */
2861                         intr->mask_misc &= ~TXGBE_ICRMISC_LSC;
2862                 }
2863         }
2864
2865         PMD_DRV_LOG(DEBUG, "enable intr immediately");
2866         txgbe_enable_intr(dev);
2867         rte_intr_enable(intr_handle);
2868
2869         return 0;
2870 }
2871
2872 /**
2873  * Interrupt handler which shall be registered for alarm callback for delayed
2874  * handling specific interrupt to wait for the stable nic state. As the
2875  * NIC interrupt state is not stable for txgbe after link is just down,
2876  * it needs to wait 4 seconds to get the stable status.
2877  *
2878  * @param handle
2879  *  Pointer to interrupt handle.
2880  * @param param
2881  *  The address of parameter (struct rte_eth_dev *) registered before.
2882  *
2883  * @return
2884  *  void
2885  */
2886 static void
2887 txgbe_dev_interrupt_delayed_handler(void *param)
2888 {
2889         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2890         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2891         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2892         struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);
2893         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2894         uint32_t eicr;
2895
2896         txgbe_disable_intr(hw);
2897
2898         eicr = ((u32 *)hw->isb_mem)[TXGBE_ISB_MISC];
2899         if (eicr & TXGBE_ICRMISC_VFMBX)
2900                 txgbe_pf_mbx_process(dev);
2901
2902         if (intr->flags & TXGBE_FLAG_PHY_INTERRUPT) {
2903                 hw->phy.handle_lasi(hw);
2904                 intr->flags &= ~TXGBE_FLAG_PHY_INTERRUPT;
2905         }
2906
2907         if (intr->flags & TXGBE_FLAG_NEED_LINK_UPDATE) {
2908                 txgbe_dev_link_update(dev, 0);
2909                 intr->flags &= ~TXGBE_FLAG_NEED_LINK_UPDATE;
2910                 txgbe_dev_link_status_print(dev);
2911                 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC,
2912                                               NULL);
2913         }
2914
2915         if (intr->flags & TXGBE_FLAG_MACSEC) {
2916                 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_MACSEC,
2917                                               NULL);
2918                 intr->flags &= ~TXGBE_FLAG_MACSEC;
2919         }
2920
2921         /* restore original mask */
2922         intr->mask_misc = intr->mask_misc_orig;
2923         intr->mask_misc_orig = 0;
2924
2925         PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
2926         txgbe_enable_intr(dev);
2927         rte_intr_enable(intr_handle);
2928 }
2929
2930 /**
2931  * Interrupt handler triggered by NIC  for handling
2932  * specific interrupt.
2933  *
2934  * @param handle
2935  *  Pointer to interrupt handle.
2936  * @param param
2937  *  The address of parameter (struct rte_eth_dev *) registered before.
2938  *
2939  * @return
2940  *  void
2941  */
2942 static void
2943 txgbe_dev_interrupt_handler(void *param)
2944 {
2945         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2946
2947         txgbe_dev_interrupt_get_status(dev);
2948         txgbe_dev_interrupt_action(dev, dev->intr_handle);
2949 }
2950
2951 static int
2952 txgbe_dev_led_on(struct rte_eth_dev *dev)
2953 {
2954         struct txgbe_hw *hw;
2955
2956         hw = TXGBE_DEV_HW(dev);
2957         return txgbe_led_on(hw, 4) == 0 ? 0 : -ENOTSUP;
2958 }
2959
2960 static int
2961 txgbe_dev_led_off(struct rte_eth_dev *dev)
2962 {
2963         struct txgbe_hw *hw;
2964
2965         hw = TXGBE_DEV_HW(dev);
2966         return txgbe_led_off(hw, 4) == 0 ? 0 : -ENOTSUP;
2967 }
2968
2969 static int
2970 txgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2971 {
2972         struct txgbe_hw *hw;
2973         uint32_t mflcn_reg;
2974         uint32_t fccfg_reg;
2975         int rx_pause;
2976         int tx_pause;
2977
2978         hw = TXGBE_DEV_HW(dev);
2979
2980         fc_conf->pause_time = hw->fc.pause_time;
2981         fc_conf->high_water = hw->fc.high_water[0];
2982         fc_conf->low_water = hw->fc.low_water[0];
2983         fc_conf->send_xon = hw->fc.send_xon;
2984         fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
2985
2986         /*
2987          * Return rx_pause status according to actual setting of
2988          * RXFCCFG register.
2989          */
2990         mflcn_reg = rd32(hw, TXGBE_RXFCCFG);
2991         if (mflcn_reg & (TXGBE_RXFCCFG_FC | TXGBE_RXFCCFG_PFC))
2992                 rx_pause = 1;
2993         else
2994                 rx_pause = 0;
2995
2996         /*
2997          * Return tx_pause status according to actual setting of
2998          * TXFCCFG register.
2999          */
3000         fccfg_reg = rd32(hw, TXGBE_TXFCCFG);
3001         if (fccfg_reg & (TXGBE_TXFCCFG_FC | TXGBE_TXFCCFG_PFC))
3002                 tx_pause = 1;
3003         else
3004                 tx_pause = 0;
3005
3006         if (rx_pause && tx_pause)
3007                 fc_conf->mode = RTE_FC_FULL;
3008         else if (rx_pause)
3009                 fc_conf->mode = RTE_FC_RX_PAUSE;
3010         else if (tx_pause)
3011                 fc_conf->mode = RTE_FC_TX_PAUSE;
3012         else
3013                 fc_conf->mode = RTE_FC_NONE;
3014
3015         return 0;
3016 }
3017
3018 static int
3019 txgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3020 {
3021         struct txgbe_hw *hw;
3022         int err;
3023         uint32_t rx_buf_size;
3024         uint32_t max_high_water;
3025         enum txgbe_fc_mode rte_fcmode_2_txgbe_fcmode[] = {
3026                 txgbe_fc_none,
3027                 txgbe_fc_rx_pause,
3028                 txgbe_fc_tx_pause,
3029                 txgbe_fc_full
3030         };
3031
3032         PMD_INIT_FUNC_TRACE();
3033
3034         hw = TXGBE_DEV_HW(dev);
3035         rx_buf_size = rd32(hw, TXGBE_PBRXSIZE(0));
3036         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
3037
3038         /*
3039          * At least reserve one Ethernet frame for watermark
3040          * high_water/low_water in kilo bytes for txgbe
3041          */
3042         max_high_water = (rx_buf_size - RTE_ETHER_MAX_LEN) >> 10;
3043         if (fc_conf->high_water > max_high_water ||
3044             fc_conf->high_water < fc_conf->low_water) {
3045                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
3046                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
3047                 return -EINVAL;
3048         }
3049
3050         hw->fc.requested_mode = rte_fcmode_2_txgbe_fcmode[fc_conf->mode];
3051         hw->fc.pause_time     = fc_conf->pause_time;
3052         hw->fc.high_water[0]  = fc_conf->high_water;
3053         hw->fc.low_water[0]   = fc_conf->low_water;
3054         hw->fc.send_xon       = fc_conf->send_xon;
3055         hw->fc.disable_fc_autoneg = !fc_conf->autoneg;
3056
3057         err = txgbe_fc_enable(hw);
3058
3059         /* Not negotiated is not an error case */
3060         if (err == 0 || err == TXGBE_ERR_FC_NOT_NEGOTIATED) {
3061                 wr32m(hw, TXGBE_MACRXFLT, TXGBE_MACRXFLT_CTL_MASK,
3062                       (fc_conf->mac_ctrl_frame_fwd
3063                        ? TXGBE_MACRXFLT_CTL_NOPS : TXGBE_MACRXFLT_CTL_DROP));
3064                 txgbe_flush(hw);
3065
3066                 return 0;
3067         }
3068
3069         PMD_INIT_LOG(ERR, "txgbe_fc_enable = 0x%x", err);
3070         return -EIO;
3071 }
3072
3073 static int
3074 txgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
3075                 struct rte_eth_pfc_conf *pfc_conf)
3076 {
3077         int err;
3078         uint32_t rx_buf_size;
3079         uint32_t max_high_water;
3080         uint8_t tc_num;
3081         uint8_t  map[TXGBE_DCB_UP_MAX] = { 0 };
3082         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3083         struct txgbe_dcb_config *dcb_config = TXGBE_DEV_DCB_CONFIG(dev);
3084
3085         enum txgbe_fc_mode rte_fcmode_2_txgbe_fcmode[] = {
3086                 txgbe_fc_none,
3087                 txgbe_fc_rx_pause,
3088                 txgbe_fc_tx_pause,
3089                 txgbe_fc_full
3090         };
3091
3092         PMD_INIT_FUNC_TRACE();
3093
3094         txgbe_dcb_unpack_map_cee(dcb_config, TXGBE_DCB_RX_CONFIG, map);
3095         tc_num = map[pfc_conf->priority];
3096         rx_buf_size = rd32(hw, TXGBE_PBRXSIZE(tc_num));
3097         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
3098         /*
3099          * At least reserve one Ethernet frame for watermark
3100          * high_water/low_water in kilo bytes for txgbe
3101          */
3102         max_high_water = (rx_buf_size - RTE_ETHER_MAX_LEN) >> 10;
3103         if (pfc_conf->fc.high_water > max_high_water ||
3104             pfc_conf->fc.high_water <= pfc_conf->fc.low_water) {
3105                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
3106                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
3107                 return -EINVAL;
3108         }
3109
3110         hw->fc.requested_mode = rte_fcmode_2_txgbe_fcmode[pfc_conf->fc.mode];
3111         hw->fc.pause_time = pfc_conf->fc.pause_time;
3112         hw->fc.send_xon = pfc_conf->fc.send_xon;
3113         hw->fc.low_water[tc_num] =  pfc_conf->fc.low_water;
3114         hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
3115
3116         err = txgbe_dcb_pfc_enable(hw, tc_num);
3117
3118         /* Not negotiated is not an error case */
3119         if (err == 0 || err == TXGBE_ERR_FC_NOT_NEGOTIATED)
3120                 return 0;
3121
3122         PMD_INIT_LOG(ERR, "txgbe_dcb_pfc_enable = 0x%x", err);
3123         return -EIO;
3124 }
3125
3126 int
3127 txgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
3128                           struct rte_eth_rss_reta_entry64 *reta_conf,
3129                           uint16_t reta_size)
3130 {
3131         uint8_t i, j, mask;
3132         uint32_t reta;
3133         uint16_t idx, shift;
3134         struct txgbe_adapter *adapter = TXGBE_DEV_ADAPTER(dev);
3135         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3136
3137         PMD_INIT_FUNC_TRACE();
3138
3139         if (!txgbe_rss_update_sp(hw->mac.type)) {
3140                 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this "
3141                         "NIC.");
3142                 return -ENOTSUP;
3143         }
3144
3145         if (reta_size != ETH_RSS_RETA_SIZE_128) {
3146                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3147                         "(%d) doesn't match the number hardware can supported "
3148                         "(%d)", reta_size, ETH_RSS_RETA_SIZE_128);
3149                 return -EINVAL;
3150         }
3151
3152         for (i = 0; i < reta_size; i += 4) {
3153                 idx = i / RTE_RETA_GROUP_SIZE;
3154                 shift = i % RTE_RETA_GROUP_SIZE;
3155                 mask = (uint8_t)RS64(reta_conf[idx].mask, shift, 0xF);
3156                 if (!mask)
3157                         continue;
3158
3159                 reta = rd32a(hw, TXGBE_REG_RSSTBL, i >> 2);
3160                 for (j = 0; j < 4; j++) {
3161                         if (RS8(mask, j, 0x1)) {
3162                                 reta  &= ~(MS32(8 * j, 0xFF));
3163                                 reta |= LS32(reta_conf[idx].reta[shift + j],
3164                                                 8 * j, 0xFF);
3165                         }
3166                 }
3167                 wr32a(hw, TXGBE_REG_RSSTBL, i >> 2, reta);
3168         }
3169         adapter->rss_reta_updated = 1;
3170
3171         return 0;
3172 }
3173
3174 int
3175 txgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
3176                          struct rte_eth_rss_reta_entry64 *reta_conf,
3177                          uint16_t reta_size)
3178 {
3179         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3180         uint8_t i, j, mask;
3181         uint32_t reta;
3182         uint16_t idx, shift;
3183
3184         PMD_INIT_FUNC_TRACE();
3185
3186         if (reta_size != ETH_RSS_RETA_SIZE_128) {
3187                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3188                         "(%d) doesn't match the number hardware can supported "
3189                         "(%d)", reta_size, ETH_RSS_RETA_SIZE_128);
3190                 return -EINVAL;
3191         }
3192
3193         for (i = 0; i < reta_size; i += 4) {
3194                 idx = i / RTE_RETA_GROUP_SIZE;
3195                 shift = i % RTE_RETA_GROUP_SIZE;
3196                 mask = (uint8_t)RS64(reta_conf[idx].mask, shift, 0xF);
3197                 if (!mask)
3198                         continue;
3199
3200                 reta = rd32a(hw, TXGBE_REG_RSSTBL, i >> 2);
3201                 for (j = 0; j < 4; j++) {
3202                         if (RS8(mask, j, 0x1))
3203                                 reta_conf[idx].reta[shift + j] =
3204                                         (uint16_t)RS32(reta, 8 * j, 0xFF);
3205                 }
3206         }
3207
3208         return 0;
3209 }
3210
3211 static int
3212 txgbe_add_rar(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
3213                                 uint32_t index, uint32_t pool)
3214 {
3215         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3216         uint32_t enable_addr = 1;
3217
3218         return txgbe_set_rar(hw, index, mac_addr->addr_bytes,
3219                              pool, enable_addr);
3220 }
3221
3222 static void
3223 txgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
3224 {
3225         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3226
3227         txgbe_clear_rar(hw, index);
3228 }
3229
3230 static int
3231 txgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *addr)
3232 {
3233         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3234
3235         txgbe_remove_rar(dev, 0);
3236         txgbe_add_rar(dev, addr, 0, pci_dev->max_vfs);
3237
3238         return 0;
3239 }
3240
3241 static int
3242 txgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
3243 {
3244         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3245         struct rte_eth_dev_info dev_info;
3246         uint32_t frame_size = mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN;
3247         struct rte_eth_dev_data *dev_data = dev->data;
3248         int ret;
3249
3250         ret = txgbe_dev_info_get(dev, &dev_info);
3251         if (ret != 0)
3252                 return ret;
3253
3254         /* check that mtu is within the allowed range */
3255         if (mtu < RTE_ETHER_MIN_MTU || frame_size > dev_info.max_rx_pktlen)
3256                 return -EINVAL;
3257
3258         /* If device is started, refuse mtu that requires the support of
3259          * scattered packets when this feature has not been enabled before.
3260          */
3261         if (dev_data->dev_started && !dev_data->scattered_rx &&
3262             (frame_size + 2 * TXGBE_VLAN_TAG_SIZE >
3263              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
3264                 PMD_INIT_LOG(ERR, "Stop port first.");
3265                 return -EINVAL;
3266         }
3267
3268         /* update max frame size */
3269         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
3270
3271         if (hw->mode)
3272                 wr32m(hw, TXGBE_FRMSZ, TXGBE_FRMSZ_MAX_MASK,
3273                         TXGBE_FRAME_SIZE_MAX);
3274         else
3275                 wr32m(hw, TXGBE_FRMSZ, TXGBE_FRMSZ_MAX_MASK,
3276                         TXGBE_FRMSZ_MAX(frame_size));
3277
3278         return 0;
3279 }
3280
3281 static uint32_t
3282 txgbe_uta_vector(struct txgbe_hw *hw, struct rte_ether_addr *uc_addr)
3283 {
3284         uint32_t vector = 0;
3285
3286         switch (hw->mac.mc_filter_type) {
3287         case 0:   /* use bits [47:36] of the address */
3288                 vector = ((uc_addr->addr_bytes[4] >> 4) |
3289                         (((uint16_t)uc_addr->addr_bytes[5]) << 4));
3290                 break;
3291         case 1:   /* use bits [46:35] of the address */
3292                 vector = ((uc_addr->addr_bytes[4] >> 3) |
3293                         (((uint16_t)uc_addr->addr_bytes[5]) << 5));
3294                 break;
3295         case 2:   /* use bits [45:34] of the address */
3296                 vector = ((uc_addr->addr_bytes[4] >> 2) |
3297                         (((uint16_t)uc_addr->addr_bytes[5]) << 6));
3298                 break;
3299         case 3:   /* use bits [43:32] of the address */
3300                 vector = ((uc_addr->addr_bytes[4]) |
3301                         (((uint16_t)uc_addr->addr_bytes[5]) << 8));
3302                 break;
3303         default:  /* Invalid mc_filter_type */
3304                 break;
3305         }
3306
3307         /* vector can only be 12-bits or boundary will be exceeded */
3308         vector &= 0xFFF;
3309         return vector;
3310 }
3311
3312 static int
3313 txgbe_uc_hash_table_set(struct rte_eth_dev *dev,
3314                         struct rte_ether_addr *mac_addr, uint8_t on)
3315 {
3316         uint32_t vector;
3317         uint32_t uta_idx;
3318         uint32_t reg_val;
3319         uint32_t uta_mask;
3320         uint32_t psrctl;
3321
3322         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3323         struct txgbe_uta_info *uta_info = TXGBE_DEV_UTA_INFO(dev);
3324
3325         /* The UTA table only exists on pf hardware */
3326         if (hw->mac.type < txgbe_mac_raptor)
3327                 return -ENOTSUP;
3328
3329         vector = txgbe_uta_vector(hw, mac_addr);
3330         uta_idx = (vector >> 5) & 0x7F;
3331         uta_mask = 0x1UL << (vector & 0x1F);
3332
3333         if (!!on == !!(uta_info->uta_shadow[uta_idx] & uta_mask))
3334                 return 0;
3335
3336         reg_val = rd32(hw, TXGBE_UCADDRTBL(uta_idx));
3337         if (on) {
3338                 uta_info->uta_in_use++;
3339                 reg_val |= uta_mask;
3340                 uta_info->uta_shadow[uta_idx] |= uta_mask;
3341         } else {
3342                 uta_info->uta_in_use--;
3343                 reg_val &= ~uta_mask;
3344                 uta_info->uta_shadow[uta_idx] &= ~uta_mask;
3345         }
3346
3347         wr32(hw, TXGBE_UCADDRTBL(uta_idx), reg_val);
3348
3349         psrctl = rd32(hw, TXGBE_PSRCTL);
3350         if (uta_info->uta_in_use > 0)
3351                 psrctl |= TXGBE_PSRCTL_UCHFENA;
3352         else
3353                 psrctl &= ~TXGBE_PSRCTL_UCHFENA;
3354
3355         psrctl &= ~TXGBE_PSRCTL_ADHF12_MASK;
3356         psrctl |= TXGBE_PSRCTL_ADHF12(hw->mac.mc_filter_type);
3357         wr32(hw, TXGBE_PSRCTL, psrctl);
3358
3359         return 0;
3360 }
3361
3362 static int
3363 txgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
3364 {
3365         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3366         struct txgbe_uta_info *uta_info = TXGBE_DEV_UTA_INFO(dev);
3367         uint32_t psrctl;
3368         int i;
3369
3370         /* The UTA table only exists on pf hardware */
3371         if (hw->mac.type < txgbe_mac_raptor)
3372                 return -ENOTSUP;
3373
3374         if (on) {
3375                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
3376                         uta_info->uta_shadow[i] = ~0;
3377                         wr32(hw, TXGBE_UCADDRTBL(i), ~0);
3378                 }
3379         } else {
3380                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
3381                         uta_info->uta_shadow[i] = 0;
3382                         wr32(hw, TXGBE_UCADDRTBL(i), 0);
3383                 }
3384         }
3385
3386         psrctl = rd32(hw, TXGBE_PSRCTL);
3387         if (on)
3388                 psrctl |= TXGBE_PSRCTL_UCHFENA;
3389         else
3390                 psrctl &= ~TXGBE_PSRCTL_UCHFENA;
3391
3392         psrctl &= ~TXGBE_PSRCTL_ADHF12_MASK;
3393         psrctl |= TXGBE_PSRCTL_ADHF12(hw->mac.mc_filter_type);
3394         wr32(hw, TXGBE_PSRCTL, psrctl);
3395
3396         return 0;
3397 }
3398
3399 uint32_t
3400 txgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
3401 {
3402         uint32_t new_val = orig_val;
3403
3404         if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
3405                 new_val |= TXGBE_POOLETHCTL_UTA;
3406         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
3407                 new_val |= TXGBE_POOLETHCTL_MCHA;
3408         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
3409                 new_val |= TXGBE_POOLETHCTL_UCHA;
3410         if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
3411                 new_val |= TXGBE_POOLETHCTL_BCA;
3412         if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
3413                 new_val |= TXGBE_POOLETHCTL_MCP;
3414
3415         return new_val;
3416 }
3417
3418 static int
3419 txgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
3420 {
3421         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3422         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3423         uint32_t mask;
3424         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3425
3426         if (queue_id < 32) {
3427                 mask = rd32(hw, TXGBE_IMS(0));
3428                 mask &= (1 << queue_id);
3429                 wr32(hw, TXGBE_IMS(0), mask);
3430         } else if (queue_id < 64) {
3431                 mask = rd32(hw, TXGBE_IMS(1));
3432                 mask &= (1 << (queue_id - 32));
3433                 wr32(hw, TXGBE_IMS(1), mask);
3434         }
3435         rte_intr_enable(intr_handle);
3436
3437         return 0;
3438 }
3439
3440 static int
3441 txgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
3442 {
3443         uint32_t mask;
3444         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3445
3446         if (queue_id < 32) {
3447                 mask = rd32(hw, TXGBE_IMS(0));
3448                 mask &= ~(1 << queue_id);
3449                 wr32(hw, TXGBE_IMS(0), mask);
3450         } else if (queue_id < 64) {
3451                 mask = rd32(hw, TXGBE_IMS(1));
3452                 mask &= ~(1 << (queue_id - 32));
3453                 wr32(hw, TXGBE_IMS(1), mask);
3454         }
3455
3456         return 0;
3457 }
3458
3459 /**
3460  * set the IVAR registers, mapping interrupt causes to vectors
3461  * @param hw
3462  *  pointer to txgbe_hw struct
3463  * @direction
3464  *  0 for Rx, 1 for Tx, -1 for other causes
3465  * @queue
3466  *  queue to map the corresponding interrupt to
3467  * @msix_vector
3468  *  the vector to map to the corresponding queue
3469  */
3470 void
3471 txgbe_set_ivar_map(struct txgbe_hw *hw, int8_t direction,
3472                    uint8_t queue, uint8_t msix_vector)
3473 {
3474         uint32_t tmp, idx;
3475
3476         if (direction == -1) {
3477                 /* other causes */
3478                 msix_vector |= TXGBE_IVARMISC_VLD;
3479                 idx = 0;
3480                 tmp = rd32(hw, TXGBE_IVARMISC);
3481                 tmp &= ~(0xFF << idx);
3482                 tmp |= (msix_vector << idx);
3483                 wr32(hw, TXGBE_IVARMISC, tmp);
3484         } else {
3485                 /* rx or tx causes */
3486                 /* Workround for ICR lost */
3487                 idx = ((16 * (queue & 1)) + (8 * direction));
3488                 tmp = rd32(hw, TXGBE_IVAR(queue >> 1));
3489                 tmp &= ~(0xFF << idx);
3490                 tmp |= (msix_vector << idx);
3491                 wr32(hw, TXGBE_IVAR(queue >> 1), tmp);
3492         }
3493 }
3494
3495 /**
3496  * Sets up the hardware to properly generate MSI-X interrupts
3497  * @hw
3498  *  board private structure
3499  */
3500 static void
3501 txgbe_configure_msix(struct rte_eth_dev *dev)
3502 {
3503         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3504         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3505         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3506         uint32_t queue_id, base = TXGBE_MISC_VEC_ID;
3507         uint32_t vec = TXGBE_MISC_VEC_ID;
3508         uint32_t gpie;
3509
3510         /* won't configure msix register if no mapping is done
3511          * between intr vector and event fd
3512          * but if misx has been enabled already, need to configure
3513          * auto clean, auto mask and throttling.
3514          */
3515         gpie = rd32(hw, TXGBE_GPIE);
3516         if (!rte_intr_dp_is_en(intr_handle) &&
3517             !(gpie & TXGBE_GPIE_MSIX))
3518                 return;
3519
3520         if (rte_intr_allow_others(intr_handle)) {
3521                 base = TXGBE_RX_VEC_START;
3522                 vec = base;
3523         }
3524
3525         /* setup GPIE for MSI-x mode */
3526         gpie = rd32(hw, TXGBE_GPIE);
3527         gpie |= TXGBE_GPIE_MSIX;
3528         wr32(hw, TXGBE_GPIE, gpie);
3529
3530         /* Populate the IVAR table and set the ITR values to the
3531          * corresponding register.
3532          */
3533         if (rte_intr_dp_is_en(intr_handle)) {
3534                 for (queue_id = 0; queue_id < dev->data->nb_rx_queues;
3535                         queue_id++) {
3536                         /* by default, 1:1 mapping */
3537                         txgbe_set_ivar_map(hw, 0, queue_id, vec);
3538                         intr_handle->intr_vec[queue_id] = vec;
3539                         if (vec < base + intr_handle->nb_efd - 1)
3540                                 vec++;
3541                 }
3542
3543                 txgbe_set_ivar_map(hw, -1, 1, TXGBE_MISC_VEC_ID);
3544         }
3545         wr32(hw, TXGBE_ITR(TXGBE_MISC_VEC_ID),
3546                         TXGBE_ITR_IVAL_10G(TXGBE_QUEUE_ITR_INTERVAL_DEFAULT)
3547                         | TXGBE_ITR_WRDSA);
3548 }
3549
3550 int
3551 txgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
3552                            uint16_t queue_idx, uint16_t tx_rate)
3553 {
3554         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3555         uint32_t bcnrc_val;
3556
3557         if (queue_idx >= hw->mac.max_tx_queues)
3558                 return -EINVAL;
3559
3560         if (tx_rate != 0) {
3561                 bcnrc_val = TXGBE_ARBTXRATE_MAX(tx_rate);
3562                 bcnrc_val |= TXGBE_ARBTXRATE_MIN(tx_rate / 2);
3563         } else {
3564                 bcnrc_val = 0;
3565         }
3566
3567         /*
3568          * Set global transmit compensation time to the MMW_SIZE in ARBTXMMW
3569          * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported.
3570          */
3571         wr32(hw, TXGBE_ARBTXMMW, 0x14);
3572
3573         /* Set ARBTXRATE of queue X */
3574         wr32(hw, TXGBE_ARBPOOLIDX, queue_idx);
3575         wr32(hw, TXGBE_ARBTXRATE, bcnrc_val);
3576         txgbe_flush(hw);
3577
3578         return 0;
3579 }
3580
3581 int
3582 txgbe_syn_filter_set(struct rte_eth_dev *dev,
3583                         struct rte_eth_syn_filter *filter,
3584                         bool add)
3585 {
3586         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3587         struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(dev);
3588         uint32_t syn_info;
3589         uint32_t synqf;
3590
3591         if (filter->queue >= TXGBE_MAX_RX_QUEUE_NUM)
3592                 return -EINVAL;
3593
3594         syn_info = filter_info->syn_info;
3595
3596         if (add) {
3597                 if (syn_info & TXGBE_SYNCLS_ENA)
3598                         return -EINVAL;
3599                 synqf = (uint32_t)TXGBE_SYNCLS_QPID(filter->queue);
3600                 synqf |= TXGBE_SYNCLS_ENA;
3601
3602                 if (filter->hig_pri)
3603                         synqf |= TXGBE_SYNCLS_HIPRIO;
3604                 else
3605                         synqf &= ~TXGBE_SYNCLS_HIPRIO;
3606         } else {
3607                 synqf = rd32(hw, TXGBE_SYNCLS);
3608                 if (!(syn_info & TXGBE_SYNCLS_ENA))
3609                         return -ENOENT;
3610                 synqf &= ~(TXGBE_SYNCLS_QPID_MASK | TXGBE_SYNCLS_ENA);
3611         }
3612
3613         filter_info->syn_info = synqf;
3614         wr32(hw, TXGBE_SYNCLS, synqf);
3615         txgbe_flush(hw);
3616         return 0;
3617 }
3618
3619 static inline enum txgbe_5tuple_protocol
3620 convert_protocol_type(uint8_t protocol_value)
3621 {
3622         if (protocol_value == IPPROTO_TCP)
3623                 return TXGBE_5TF_PROT_TCP;
3624         else if (protocol_value == IPPROTO_UDP)
3625                 return TXGBE_5TF_PROT_UDP;
3626         else if (protocol_value == IPPROTO_SCTP)
3627                 return TXGBE_5TF_PROT_SCTP;
3628         else
3629                 return TXGBE_5TF_PROT_NONE;
3630 }
3631
3632 /* inject a 5-tuple filter to HW */
3633 static inline void
3634 txgbe_inject_5tuple_filter(struct rte_eth_dev *dev,
3635                            struct txgbe_5tuple_filter *filter)
3636 {
3637         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3638         int i;
3639         uint32_t ftqf, sdpqf;
3640         uint32_t l34timir = 0;
3641         uint32_t mask = TXGBE_5TFCTL0_MASK;
3642
3643         i = filter->index;
3644         sdpqf = TXGBE_5TFPORT_DST(be_to_le16(filter->filter_info.dst_port));
3645         sdpqf |= TXGBE_5TFPORT_SRC(be_to_le16(filter->filter_info.src_port));
3646
3647         ftqf = TXGBE_5TFCTL0_PROTO(filter->filter_info.proto);
3648         ftqf |= TXGBE_5TFCTL0_PRI(filter->filter_info.priority);
3649         if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
3650                 mask &= ~TXGBE_5TFCTL0_MSADDR;
3651         if (filter->filter_info.dst_ip_mask == 0)
3652                 mask &= ~TXGBE_5TFCTL0_MDADDR;
3653         if (filter->filter_info.src_port_mask == 0)
3654                 mask &= ~TXGBE_5TFCTL0_MSPORT;
3655         if (filter->filter_info.dst_port_mask == 0)
3656                 mask &= ~TXGBE_5TFCTL0_MDPORT;
3657         if (filter->filter_info.proto_mask == 0)
3658                 mask &= ~TXGBE_5TFCTL0_MPROTO;
3659         ftqf |= mask;
3660         ftqf |= TXGBE_5TFCTL0_MPOOL;
3661         ftqf |= TXGBE_5TFCTL0_ENA;
3662
3663         wr32(hw, TXGBE_5TFDADDR(i), be_to_le32(filter->filter_info.dst_ip));
3664         wr32(hw, TXGBE_5TFSADDR(i), be_to_le32(filter->filter_info.src_ip));
3665         wr32(hw, TXGBE_5TFPORT(i), sdpqf);
3666         wr32(hw, TXGBE_5TFCTL0(i), ftqf);
3667
3668         l34timir |= TXGBE_5TFCTL1_QP(filter->queue);
3669         wr32(hw, TXGBE_5TFCTL1(i), l34timir);
3670 }
3671
3672 /*
3673  * add a 5tuple filter
3674  *
3675  * @param
3676  * dev: Pointer to struct rte_eth_dev.
3677  * index: the index the filter allocates.
3678  * filter: pointer to the filter that will be added.
3679  * rx_queue: the queue id the filter assigned to.
3680  *
3681  * @return
3682  *    - On success, zero.
3683  *    - On failure, a negative value.
3684  */
3685 static int
3686 txgbe_add_5tuple_filter(struct rte_eth_dev *dev,
3687                         struct txgbe_5tuple_filter *filter)
3688 {
3689         struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(dev);
3690         int i, idx, shift;
3691
3692         /*
3693          * look for an unused 5tuple filter index,
3694          * and insert the filter to list.
3695          */
3696         for (i = 0; i < TXGBE_MAX_FTQF_FILTERS; i++) {
3697                 idx = i / (sizeof(uint32_t) * NBBY);
3698                 shift = i % (sizeof(uint32_t) * NBBY);
3699                 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
3700                         filter_info->fivetuple_mask[idx] |= 1 << shift;
3701                         filter->index = i;
3702                         TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
3703                                           filter,
3704                                           entries);
3705                         break;
3706                 }
3707         }
3708         if (i >= TXGBE_MAX_FTQF_FILTERS) {
3709                 PMD_DRV_LOG(ERR, "5tuple filters are full.");
3710                 return -ENOSYS;
3711         }
3712
3713         txgbe_inject_5tuple_filter(dev, filter);
3714
3715         return 0;
3716 }
3717
3718 /*
3719  * remove a 5tuple filter
3720  *
3721  * @param
3722  * dev: Pointer to struct rte_eth_dev.
3723  * filter: the pointer of the filter will be removed.
3724  */
3725 static void
3726 txgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
3727                         struct txgbe_5tuple_filter *filter)
3728 {
3729         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3730         struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(dev);
3731         uint16_t index = filter->index;
3732
3733         filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
3734                                 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
3735         TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
3736         rte_free(filter);
3737
3738         wr32(hw, TXGBE_5TFDADDR(index), 0);
3739         wr32(hw, TXGBE_5TFSADDR(index), 0);
3740         wr32(hw, TXGBE_5TFPORT(index), 0);
3741         wr32(hw, TXGBE_5TFCTL0(index), 0);
3742         wr32(hw, TXGBE_5TFCTL1(index), 0);
3743 }
3744
3745 static inline struct txgbe_5tuple_filter *
3746 txgbe_5tuple_filter_lookup(struct txgbe_5tuple_filter_list *filter_list,
3747                         struct txgbe_5tuple_filter_info *key)
3748 {
3749         struct txgbe_5tuple_filter *it;
3750
3751         TAILQ_FOREACH(it, filter_list, entries) {
3752                 if (memcmp(key, &it->filter_info,
3753                         sizeof(struct txgbe_5tuple_filter_info)) == 0) {
3754                         return it;
3755                 }
3756         }
3757         return NULL;
3758 }
3759
3760 /* translate elements in struct rte_eth_ntuple_filter
3761  * to struct txgbe_5tuple_filter_info
3762  */
3763 static inline int
3764 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
3765                         struct txgbe_5tuple_filter_info *filter_info)
3766 {
3767         if (filter->queue >= TXGBE_MAX_RX_QUEUE_NUM ||
3768                 filter->priority > TXGBE_5TUPLE_MAX_PRI ||
3769                 filter->priority < TXGBE_5TUPLE_MIN_PRI)
3770                 return -EINVAL;
3771
3772         switch (filter->dst_ip_mask) {
3773         case UINT32_MAX:
3774                 filter_info->dst_ip_mask = 0;
3775                 filter_info->dst_ip = filter->dst_ip;
3776                 break;
3777         case 0:
3778                 filter_info->dst_ip_mask = 1;
3779                 break;
3780         default:
3781                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
3782                 return -EINVAL;
3783         }
3784
3785         switch (filter->src_ip_mask) {
3786         case UINT32_MAX:
3787                 filter_info->src_ip_mask = 0;
3788                 filter_info->src_ip = filter->src_ip;
3789                 break;
3790         case 0:
3791                 filter_info->src_ip_mask = 1;
3792                 break;
3793         default:
3794                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
3795                 return -EINVAL;
3796         }
3797
3798         switch (filter->dst_port_mask) {
3799         case UINT16_MAX:
3800                 filter_info->dst_port_mask = 0;
3801                 filter_info->dst_port = filter->dst_port;
3802                 break;
3803         case 0:
3804                 filter_info->dst_port_mask = 1;
3805                 break;
3806         default:
3807                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
3808                 return -EINVAL;
3809         }
3810
3811         switch (filter->src_port_mask) {
3812         case UINT16_MAX:
3813                 filter_info->src_port_mask = 0;
3814                 filter_info->src_port = filter->src_port;
3815                 break;
3816         case 0:
3817                 filter_info->src_port_mask = 1;
3818                 break;
3819         default:
3820                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
3821                 return -EINVAL;
3822         }
3823
3824         switch (filter->proto_mask) {
3825         case UINT8_MAX:
3826                 filter_info->proto_mask = 0;
3827                 filter_info->proto =
3828                         convert_protocol_type(filter->proto);
3829                 break;
3830         case 0:
3831                 filter_info->proto_mask = 1;
3832                 break;
3833         default:
3834                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
3835                 return -EINVAL;
3836         }
3837
3838         filter_info->priority = (uint8_t)filter->priority;
3839         return 0;
3840 }
3841
3842 /*
3843  * add or delete a ntuple filter
3844  *
3845  * @param
3846  * dev: Pointer to struct rte_eth_dev.
3847  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
3848  * add: if true, add filter, if false, remove filter
3849  *
3850  * @return
3851  *    - On success, zero.
3852  *    - On failure, a negative value.
3853  */
3854 int
3855 txgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
3856                         struct rte_eth_ntuple_filter *ntuple_filter,
3857                         bool add)
3858 {
3859         struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(dev);
3860         struct txgbe_5tuple_filter_info filter_5tuple;
3861         struct txgbe_5tuple_filter *filter;
3862         int ret;
3863
3864         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
3865                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
3866                 return -EINVAL;
3867         }
3868
3869         memset(&filter_5tuple, 0, sizeof(struct txgbe_5tuple_filter_info));
3870         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
3871         if (ret < 0)
3872                 return ret;
3873
3874         filter = txgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
3875                                          &filter_5tuple);
3876         if (filter != NULL && add) {
3877                 PMD_DRV_LOG(ERR, "filter exists.");
3878                 return -EEXIST;
3879         }
3880         if (filter == NULL && !add) {
3881                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3882                 return -ENOENT;
3883         }
3884
3885         if (add) {
3886                 filter = rte_zmalloc("txgbe_5tuple_filter",
3887                                 sizeof(struct txgbe_5tuple_filter), 0);
3888                 if (filter == NULL)
3889                         return -ENOMEM;
3890                 rte_memcpy(&filter->filter_info,
3891                                  &filter_5tuple,
3892                                  sizeof(struct txgbe_5tuple_filter_info));
3893                 filter->queue = ntuple_filter->queue;
3894                 ret = txgbe_add_5tuple_filter(dev, filter);
3895                 if (ret < 0) {
3896                         rte_free(filter);
3897                         return ret;
3898                 }
3899         } else {
3900                 txgbe_remove_5tuple_filter(dev, filter);
3901         }
3902
3903         return 0;
3904 }
3905
3906 int
3907 txgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
3908                         struct rte_eth_ethertype_filter *filter,
3909                         bool add)
3910 {
3911         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3912         struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(dev);
3913         uint32_t etqf = 0;
3914         uint32_t etqs = 0;
3915         int ret;
3916         struct txgbe_ethertype_filter ethertype_filter;
3917
3918         if (filter->queue >= TXGBE_MAX_RX_QUEUE_NUM)
3919                 return -EINVAL;
3920
3921         if (filter->ether_type == RTE_ETHER_TYPE_IPV4 ||
3922             filter->ether_type == RTE_ETHER_TYPE_IPV6) {
3923                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
3924                         " ethertype filter.", filter->ether_type);
3925                 return -EINVAL;
3926         }
3927
3928         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
3929                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
3930                 return -EINVAL;
3931         }
3932         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
3933                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
3934                 return -EINVAL;
3935         }
3936
3937         ret = txgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
3938         if (ret >= 0 && add) {
3939                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
3940                             filter->ether_type);
3941                 return -EEXIST;
3942         }
3943         if (ret < 0 && !add) {
3944                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
3945                             filter->ether_type);
3946                 return -ENOENT;
3947         }
3948
3949         if (add) {
3950                 etqf = TXGBE_ETFLT_ENA;
3951                 etqf |= TXGBE_ETFLT_ETID(filter->ether_type);
3952                 etqs |= TXGBE_ETCLS_QPID(filter->queue);
3953                 etqs |= TXGBE_ETCLS_QENA;
3954
3955                 ethertype_filter.ethertype = filter->ether_type;
3956                 ethertype_filter.etqf = etqf;
3957                 ethertype_filter.etqs = etqs;
3958                 ethertype_filter.conf = FALSE;
3959                 ret = txgbe_ethertype_filter_insert(filter_info,
3960                                                     &ethertype_filter);
3961                 if (ret < 0) {
3962                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
3963                         return -ENOSPC;
3964                 }
3965         } else {
3966                 ret = txgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
3967                 if (ret < 0)
3968                         return -ENOSYS;
3969         }
3970         wr32(hw, TXGBE_ETFLT(ret), etqf);
3971         wr32(hw, TXGBE_ETCLS(ret), etqs);
3972         txgbe_flush(hw);
3973
3974         return 0;
3975 }
3976
3977 static int
3978 txgbe_dev_filter_ctrl(__rte_unused struct rte_eth_dev *dev,
3979                      enum rte_filter_type filter_type,
3980                      enum rte_filter_op filter_op,
3981                      void *arg)
3982 {
3983         int ret = 0;
3984
3985         switch (filter_type) {
3986         case RTE_ETH_FILTER_GENERIC:
3987                 if (filter_op != RTE_ETH_FILTER_GET)
3988                         return -EINVAL;
3989                 *(const void **)arg = &txgbe_flow_ops;
3990                 break;
3991         default:
3992                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
3993                                                         filter_type);
3994                 ret = -EINVAL;
3995                 break;
3996         }
3997
3998         return ret;
3999 }
4000
4001 static u8 *
4002 txgbe_dev_addr_list_itr(__rte_unused struct txgbe_hw *hw,
4003                         u8 **mc_addr_ptr, u32 *vmdq)
4004 {
4005         u8 *mc_addr;
4006
4007         *vmdq = 0;
4008         mc_addr = *mc_addr_ptr;
4009         *mc_addr_ptr = (mc_addr + sizeof(struct rte_ether_addr));
4010         return mc_addr;
4011 }
4012
4013 int
4014 txgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
4015                           struct rte_ether_addr *mc_addr_set,
4016                           uint32_t nb_mc_addr)
4017 {
4018         struct txgbe_hw *hw;
4019         u8 *mc_addr_list;
4020
4021         hw = TXGBE_DEV_HW(dev);
4022         mc_addr_list = (u8 *)mc_addr_set;
4023         return txgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
4024                                          txgbe_dev_addr_list_itr, TRUE);
4025 }
4026
4027 static uint64_t
4028 txgbe_read_systime_cyclecounter(struct rte_eth_dev *dev)
4029 {
4030         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4031         uint64_t systime_cycles;
4032
4033         systime_cycles = (uint64_t)rd32(hw, TXGBE_TSTIMEL);
4034         systime_cycles |= (uint64_t)rd32(hw, TXGBE_TSTIMEH) << 32;
4035
4036         return systime_cycles;
4037 }
4038
4039 static uint64_t
4040 txgbe_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
4041 {
4042         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4043         uint64_t rx_tstamp_cycles;
4044
4045         /* TSRXSTMPL stores ns and TSRXSTMPH stores seconds. */
4046         rx_tstamp_cycles = (uint64_t)rd32(hw, TXGBE_TSRXSTMPL);
4047         rx_tstamp_cycles |= (uint64_t)rd32(hw, TXGBE_TSRXSTMPH) << 32;
4048
4049         return rx_tstamp_cycles;
4050 }
4051
4052 static uint64_t
4053 txgbe_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
4054 {
4055         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4056         uint64_t tx_tstamp_cycles;
4057
4058         /* TSTXSTMPL stores ns and TSTXSTMPH stores seconds. */
4059         tx_tstamp_cycles = (uint64_t)rd32(hw, TXGBE_TSTXSTMPL);
4060         tx_tstamp_cycles |= (uint64_t)rd32(hw, TXGBE_TSTXSTMPH) << 32;
4061
4062         return tx_tstamp_cycles;
4063 }
4064
4065 static void
4066 txgbe_start_timecounters(struct rte_eth_dev *dev)
4067 {
4068         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4069         struct txgbe_adapter *adapter = TXGBE_DEV_ADAPTER(dev);
4070         struct rte_eth_link link;
4071         uint32_t incval = 0;
4072         uint32_t shift = 0;
4073
4074         /* Get current link speed. */
4075         txgbe_dev_link_update(dev, 1);
4076         rte_eth_linkstatus_get(dev, &link);
4077
4078         switch (link.link_speed) {
4079         case ETH_SPEED_NUM_100M:
4080                 incval = TXGBE_INCVAL_100;
4081                 shift = TXGBE_INCVAL_SHIFT_100;
4082                 break;
4083         case ETH_SPEED_NUM_1G:
4084                 incval = TXGBE_INCVAL_1GB;
4085                 shift = TXGBE_INCVAL_SHIFT_1GB;
4086                 break;
4087         case ETH_SPEED_NUM_10G:
4088         default:
4089                 incval = TXGBE_INCVAL_10GB;
4090                 shift = TXGBE_INCVAL_SHIFT_10GB;
4091                 break;
4092         }
4093
4094         wr32(hw, TXGBE_TSTIMEINC, TXGBE_TSTIMEINC_VP(incval, 2));
4095
4096         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
4097         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
4098         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
4099
4100         adapter->systime_tc.cc_mask = TXGBE_CYCLECOUNTER_MASK;
4101         adapter->systime_tc.cc_shift = shift;
4102         adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
4103
4104         adapter->rx_tstamp_tc.cc_mask = TXGBE_CYCLECOUNTER_MASK;
4105         adapter->rx_tstamp_tc.cc_shift = shift;
4106         adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
4107
4108         adapter->tx_tstamp_tc.cc_mask = TXGBE_CYCLECOUNTER_MASK;
4109         adapter->tx_tstamp_tc.cc_shift = shift;
4110         adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
4111 }
4112
4113 static int
4114 txgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
4115 {
4116         struct txgbe_adapter *adapter = TXGBE_DEV_ADAPTER(dev);
4117
4118         adapter->systime_tc.nsec += delta;
4119         adapter->rx_tstamp_tc.nsec += delta;
4120         adapter->tx_tstamp_tc.nsec += delta;
4121
4122         return 0;
4123 }
4124
4125 static int
4126 txgbe_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
4127 {
4128         uint64_t ns;
4129         struct txgbe_adapter *adapter = TXGBE_DEV_ADAPTER(dev);
4130
4131         ns = rte_timespec_to_ns(ts);
4132         /* Set the timecounters to a new value. */
4133         adapter->systime_tc.nsec = ns;
4134         adapter->rx_tstamp_tc.nsec = ns;
4135         adapter->tx_tstamp_tc.nsec = ns;
4136
4137         return 0;
4138 }
4139
4140 static int
4141 txgbe_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
4142 {
4143         uint64_t ns, systime_cycles;
4144         struct txgbe_adapter *adapter = TXGBE_DEV_ADAPTER(dev);
4145
4146         systime_cycles = txgbe_read_systime_cyclecounter(dev);
4147         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
4148         *ts = rte_ns_to_timespec(ns);
4149
4150         return 0;
4151 }
4152
4153 static int
4154 txgbe_timesync_enable(struct rte_eth_dev *dev)
4155 {
4156         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4157         uint32_t tsync_ctl;
4158
4159         /* Stop the timesync system time. */
4160         wr32(hw, TXGBE_TSTIMEINC, 0x0);
4161         /* Reset the timesync system time value. */
4162         wr32(hw, TXGBE_TSTIMEL, 0x0);
4163         wr32(hw, TXGBE_TSTIMEH, 0x0);
4164
4165         txgbe_start_timecounters(dev);
4166
4167         /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
4168         wr32(hw, TXGBE_ETFLT(TXGBE_ETF_ID_1588),
4169                 RTE_ETHER_TYPE_1588 | TXGBE_ETFLT_ENA | TXGBE_ETFLT_1588);
4170
4171         /* Enable timestamping of received PTP packets. */
4172         tsync_ctl = rd32(hw, TXGBE_TSRXCTL);
4173         tsync_ctl |= TXGBE_TSRXCTL_ENA;
4174         wr32(hw, TXGBE_TSRXCTL, tsync_ctl);
4175
4176         /* Enable timestamping of transmitted PTP packets. */
4177         tsync_ctl = rd32(hw, TXGBE_TSTXCTL);
4178         tsync_ctl |= TXGBE_TSTXCTL_ENA;
4179         wr32(hw, TXGBE_TSTXCTL, tsync_ctl);
4180
4181         txgbe_flush(hw);
4182
4183         return 0;
4184 }
4185
4186 static int
4187 txgbe_timesync_disable(struct rte_eth_dev *dev)
4188 {
4189         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4190         uint32_t tsync_ctl;
4191
4192         /* Disable timestamping of transmitted PTP packets. */
4193         tsync_ctl = rd32(hw, TXGBE_TSTXCTL);
4194         tsync_ctl &= ~TXGBE_TSTXCTL_ENA;
4195         wr32(hw, TXGBE_TSTXCTL, tsync_ctl);
4196
4197         /* Disable timestamping of received PTP packets. */
4198         tsync_ctl = rd32(hw, TXGBE_TSRXCTL);
4199         tsync_ctl &= ~TXGBE_TSRXCTL_ENA;
4200         wr32(hw, TXGBE_TSRXCTL, tsync_ctl);
4201
4202         /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
4203         wr32(hw, TXGBE_ETFLT(TXGBE_ETF_ID_1588), 0);
4204
4205         /* Stop incrementating the System Time registers. */
4206         wr32(hw, TXGBE_TSTIMEINC, 0);
4207
4208         return 0;
4209 }
4210
4211 static int
4212 txgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
4213                                  struct timespec *timestamp,
4214                                  uint32_t flags __rte_unused)
4215 {
4216         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4217         struct txgbe_adapter *adapter = TXGBE_DEV_ADAPTER(dev);
4218         uint32_t tsync_rxctl;
4219         uint64_t rx_tstamp_cycles;
4220         uint64_t ns;
4221
4222         tsync_rxctl = rd32(hw, TXGBE_TSRXCTL);
4223         if ((tsync_rxctl & TXGBE_TSRXCTL_VLD) == 0)
4224                 return -EINVAL;
4225
4226         rx_tstamp_cycles = txgbe_read_rx_tstamp_cyclecounter(dev);
4227         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
4228         *timestamp = rte_ns_to_timespec(ns);
4229
4230         return  0;
4231 }
4232
4233 static int
4234 txgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
4235                                  struct timespec *timestamp)
4236 {
4237         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4238         struct txgbe_adapter *adapter = TXGBE_DEV_ADAPTER(dev);
4239         uint32_t tsync_txctl;
4240         uint64_t tx_tstamp_cycles;
4241         uint64_t ns;
4242
4243         tsync_txctl = rd32(hw, TXGBE_TSTXCTL);
4244         if ((tsync_txctl & TXGBE_TSTXCTL_VLD) == 0)
4245                 return -EINVAL;
4246
4247         tx_tstamp_cycles = txgbe_read_tx_tstamp_cyclecounter(dev);
4248         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
4249         *timestamp = rte_ns_to_timespec(ns);
4250
4251         return 0;
4252 }
4253
4254 static int
4255 txgbe_get_reg_length(struct rte_eth_dev *dev __rte_unused)
4256 {
4257         int count = 0;
4258         int g_ind = 0;
4259         const struct reg_info *reg_group;
4260         const struct reg_info **reg_set = txgbe_regs_others;
4261
4262         while ((reg_group = reg_set[g_ind++]))
4263                 count += txgbe_regs_group_count(reg_group);
4264
4265         return count;
4266 }
4267
4268 static int
4269 txgbe_get_regs(struct rte_eth_dev *dev,
4270               struct rte_dev_reg_info *regs)
4271 {
4272         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4273         uint32_t *data = regs->data;
4274         int g_ind = 0;
4275         int count = 0;
4276         const struct reg_info *reg_group;
4277         const struct reg_info **reg_set = txgbe_regs_others;
4278
4279         if (data == NULL) {
4280                 regs->length = txgbe_get_reg_length(dev);
4281                 regs->width = sizeof(uint32_t);
4282                 return 0;
4283         }
4284
4285         /* Support only full register dump */
4286         if (regs->length == 0 ||
4287             regs->length == (uint32_t)txgbe_get_reg_length(dev)) {
4288                 regs->version = hw->mac.type << 24 |
4289                                 hw->revision_id << 16 |
4290                                 hw->device_id;
4291                 while ((reg_group = reg_set[g_ind++]))
4292                         count += txgbe_read_regs_group(dev, &data[count],
4293                                                       reg_group);
4294                 return 0;
4295         }
4296
4297         return -ENOTSUP;
4298 }
4299
4300 static int
4301 txgbe_get_eeprom_length(struct rte_eth_dev *dev)
4302 {
4303         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4304
4305         /* Return unit is byte count */
4306         return hw->rom.word_size * 2;
4307 }
4308
4309 static int
4310 txgbe_get_eeprom(struct rte_eth_dev *dev,
4311                 struct rte_dev_eeprom_info *in_eeprom)
4312 {
4313         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4314         struct txgbe_rom_info *eeprom = &hw->rom;
4315         uint16_t *data = in_eeprom->data;
4316         int first, length;
4317
4318         first = in_eeprom->offset >> 1;
4319         length = in_eeprom->length >> 1;
4320         if (first > hw->rom.word_size ||
4321             ((first + length) > hw->rom.word_size))
4322                 return -EINVAL;
4323
4324         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
4325
4326         return eeprom->readw_buffer(hw, first, length, data);
4327 }
4328
4329 static int
4330 txgbe_set_eeprom(struct rte_eth_dev *dev,
4331                 struct rte_dev_eeprom_info *in_eeprom)
4332 {
4333         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4334         struct txgbe_rom_info *eeprom = &hw->rom;
4335         uint16_t *data = in_eeprom->data;
4336         int first, length;
4337
4338         first = in_eeprom->offset >> 1;
4339         length = in_eeprom->length >> 1;
4340         if (first > hw->rom.word_size ||
4341             ((first + length) > hw->rom.word_size))
4342                 return -EINVAL;
4343
4344         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
4345
4346         return eeprom->writew_buffer(hw,  first, length, data);
4347 }
4348
4349 static int
4350 txgbe_get_module_info(struct rte_eth_dev *dev,
4351                       struct rte_eth_dev_module_info *modinfo)
4352 {
4353         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4354         uint32_t status;
4355         uint8_t sff8472_rev, addr_mode;
4356         bool page_swap = false;
4357
4358         /* Check whether we support SFF-8472 or not */
4359         status = hw->phy.read_i2c_eeprom(hw,
4360                                              TXGBE_SFF_SFF_8472_COMP,
4361                                              &sff8472_rev);
4362         if (status != 0)
4363                 return -EIO;
4364
4365         /* addressing mode is not supported */
4366         status = hw->phy.read_i2c_eeprom(hw,
4367                                              TXGBE_SFF_SFF_8472_SWAP,
4368                                              &addr_mode);
4369         if (status != 0)
4370                 return -EIO;
4371
4372         if (addr_mode & TXGBE_SFF_ADDRESSING_MODE) {
4373                 PMD_DRV_LOG(ERR,
4374                             "Address change required to access page 0xA2, "
4375                             "but not supported. Please report the module "
4376                             "type to the driver maintainers.");
4377                 page_swap = true;
4378         }
4379
4380         if (sff8472_rev == TXGBE_SFF_SFF_8472_UNSUP || page_swap) {
4381                 /* We have a SFP, but it does not support SFF-8472 */
4382                 modinfo->type = RTE_ETH_MODULE_SFF_8079;
4383                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
4384         } else {
4385                 /* We have a SFP which supports a revision of SFF-8472. */
4386                 modinfo->type = RTE_ETH_MODULE_SFF_8472;
4387                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
4388         }
4389
4390         return 0;
4391 }
4392
4393 static int
4394 txgbe_get_module_eeprom(struct rte_eth_dev *dev,
4395                         struct rte_dev_eeprom_info *info)
4396 {
4397         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4398         uint32_t status = TXGBE_ERR_PHY_ADDR_INVALID;
4399         uint8_t databyte = 0xFF;
4400         uint8_t *data = info->data;
4401         uint32_t i = 0;
4402
4403         if (info->length == 0)
4404                 return -EINVAL;
4405
4406         for (i = info->offset; i < info->offset + info->length; i++) {
4407                 if (i < RTE_ETH_MODULE_SFF_8079_LEN)
4408                         status = hw->phy.read_i2c_eeprom(hw, i, &databyte);
4409                 else
4410                         status = hw->phy.read_i2c_sff8472(hw, i, &databyte);
4411
4412                 if (status != 0)
4413                         return -EIO;
4414
4415                 data[i - info->offset] = databyte;
4416         }
4417
4418         return 0;
4419 }
4420
4421 bool
4422 txgbe_rss_update_sp(enum txgbe_mac_type mac_type)
4423 {
4424         switch (mac_type) {
4425         case txgbe_mac_raptor:
4426                 return 1;
4427         default:
4428                 return 0;
4429         }
4430 }
4431
4432 static int
4433 txgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
4434                         struct rte_eth_dcb_info *dcb_info)
4435 {
4436         struct txgbe_dcb_config *dcb_config = TXGBE_DEV_DCB_CONFIG(dev);
4437         struct txgbe_dcb_tc_config *tc;
4438         struct rte_eth_dcb_tc_queue_mapping *tc_queue;
4439         uint8_t nb_tcs;
4440         uint8_t i, j;
4441
4442         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
4443                 dcb_info->nb_tcs = dcb_config->num_tcs.pg_tcs;
4444         else
4445                 dcb_info->nb_tcs = 1;
4446
4447         tc_queue = &dcb_info->tc_queue;
4448         nb_tcs = dcb_info->nb_tcs;
4449
4450         if (dcb_config->vt_mode) { /* vt is enabled */
4451                 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
4452                                 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
4453                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
4454                         dcb_info->prio_tc[i] = vmdq_rx_conf->dcb_tc[i];
4455                 if (RTE_ETH_DEV_SRIOV(dev).active > 0) {
4456                         for (j = 0; j < nb_tcs; j++) {
4457                                 tc_queue->tc_rxq[0][j].base = j;
4458                                 tc_queue->tc_rxq[0][j].nb_queue = 1;
4459                                 tc_queue->tc_txq[0][j].base = j;
4460                                 tc_queue->tc_txq[0][j].nb_queue = 1;
4461                         }
4462                 } else {
4463                         for (i = 0; i < vmdq_rx_conf->nb_queue_pools; i++) {
4464                                 for (j = 0; j < nb_tcs; j++) {
4465                                         tc_queue->tc_rxq[i][j].base =
4466                                                 i * nb_tcs + j;
4467                                         tc_queue->tc_rxq[i][j].nb_queue = 1;
4468                                         tc_queue->tc_txq[i][j].base =
4469                                                 i * nb_tcs + j;
4470                                         tc_queue->tc_txq[i][j].nb_queue = 1;
4471                                 }
4472                         }
4473                 }
4474         } else { /* vt is disabled */
4475                 struct rte_eth_dcb_rx_conf *rx_conf =
4476                                 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
4477                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
4478                         dcb_info->prio_tc[i] = rx_conf->dcb_tc[i];
4479                 if (dcb_info->nb_tcs == ETH_4_TCS) {
4480                         for (i = 0; i < dcb_info->nb_tcs; i++) {
4481                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 32;
4482                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
4483                         }
4484                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
4485                         dcb_info->tc_queue.tc_txq[0][1].base = 64;
4486                         dcb_info->tc_queue.tc_txq[0][2].base = 96;
4487                         dcb_info->tc_queue.tc_txq[0][3].base = 112;
4488                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 64;
4489                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
4490                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
4491                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
4492                 } else if (dcb_info->nb_tcs == ETH_8_TCS) {
4493                         for (i = 0; i < dcb_info->nb_tcs; i++) {
4494                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 16;
4495                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
4496                         }
4497                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
4498                         dcb_info->tc_queue.tc_txq[0][1].base = 32;
4499                         dcb_info->tc_queue.tc_txq[0][2].base = 64;
4500                         dcb_info->tc_queue.tc_txq[0][3].base = 80;
4501                         dcb_info->tc_queue.tc_txq[0][4].base = 96;
4502                         dcb_info->tc_queue.tc_txq[0][5].base = 104;
4503                         dcb_info->tc_queue.tc_txq[0][6].base = 112;
4504                         dcb_info->tc_queue.tc_txq[0][7].base = 120;
4505                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 32;
4506                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
4507                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
4508                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
4509                         dcb_info->tc_queue.tc_txq[0][4].nb_queue = 8;
4510                         dcb_info->tc_queue.tc_txq[0][5].nb_queue = 8;
4511                         dcb_info->tc_queue.tc_txq[0][6].nb_queue = 8;
4512                         dcb_info->tc_queue.tc_txq[0][7].nb_queue = 8;
4513                 }
4514         }
4515         for (i = 0; i < dcb_info->nb_tcs; i++) {
4516                 tc = &dcb_config->tc_config[i];
4517                 dcb_info->tc_bws[i] = tc->path[TXGBE_DCB_TX_CONFIG].bwg_percent;
4518         }
4519         return 0;
4520 }
4521
4522 /* Update e-tag ether type */
4523 static int
4524 txgbe_update_e_tag_eth_type(struct txgbe_hw *hw,
4525                             uint16_t ether_type)
4526 {
4527         uint32_t etag_etype;
4528
4529         etag_etype = rd32(hw, TXGBE_EXTAG);
4530         etag_etype &= ~TXGBE_EXTAG_ETAG_MASK;
4531         etag_etype |= ether_type;
4532         wr32(hw, TXGBE_EXTAG, etag_etype);
4533         txgbe_flush(hw);
4534
4535         return 0;
4536 }
4537
4538 /* Enable e-tag tunnel */
4539 static int
4540 txgbe_e_tag_enable(struct txgbe_hw *hw)
4541 {
4542         uint32_t etag_etype;
4543
4544         etag_etype = rd32(hw, TXGBE_PORTCTL);
4545         etag_etype |= TXGBE_PORTCTL_ETAG;
4546         wr32(hw, TXGBE_PORTCTL, etag_etype);
4547         txgbe_flush(hw);
4548
4549         return 0;
4550 }
4551
4552 static int
4553 txgbe_e_tag_forwarding_en_dis(struct rte_eth_dev *dev, bool en)
4554 {
4555         int ret = 0;
4556         uint32_t ctrl;
4557         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4558
4559         ctrl = rd32(hw, TXGBE_POOLCTL);
4560         ctrl &= ~TXGBE_POOLCTL_MODE_MASK;
4561         if (en)
4562                 ctrl |= TXGBE_PSRPOOL_MODE_ETAG;
4563         wr32(hw, TXGBE_POOLCTL, ctrl);
4564
4565         return ret;
4566 }
4567
4568 /* restore n-tuple filter */
4569 static inline void
4570 txgbe_ntuple_filter_restore(struct rte_eth_dev *dev)
4571 {
4572         struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(dev);
4573         struct txgbe_5tuple_filter *node;
4574
4575         TAILQ_FOREACH(node, &filter_info->fivetuple_list, entries) {
4576                 txgbe_inject_5tuple_filter(dev, node);
4577         }
4578 }
4579
4580 /* restore ethernet type filter */
4581 static inline void
4582 txgbe_ethertype_filter_restore(struct rte_eth_dev *dev)
4583 {
4584         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4585         struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(dev);
4586         int i;
4587
4588         for (i = 0; i < TXGBE_ETF_ID_MAX; i++) {
4589                 if (filter_info->ethertype_mask & (1 << i)) {
4590                         wr32(hw, TXGBE_ETFLT(i),
4591                                         filter_info->ethertype_filters[i].etqf);
4592                         wr32(hw, TXGBE_ETCLS(i),
4593                                         filter_info->ethertype_filters[i].etqs);
4594                         txgbe_flush(hw);
4595                 }
4596         }
4597 }
4598
4599 /* restore SYN filter */
4600 static inline void
4601 txgbe_syn_filter_restore(struct rte_eth_dev *dev)
4602 {
4603         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4604         struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(dev);
4605         uint32_t synqf;
4606
4607         synqf = filter_info->syn_info;
4608
4609         if (synqf & TXGBE_SYNCLS_ENA) {
4610                 wr32(hw, TXGBE_SYNCLS, synqf);
4611                 txgbe_flush(hw);
4612         }
4613 }
4614
4615 static int
4616 txgbe_filter_restore(struct rte_eth_dev *dev)
4617 {
4618         txgbe_ntuple_filter_restore(dev);
4619         txgbe_ethertype_filter_restore(dev);
4620         txgbe_syn_filter_restore(dev);
4621
4622         return 0;
4623 }
4624
4625 static void
4626 txgbe_l2_tunnel_conf(struct rte_eth_dev *dev)
4627 {
4628         struct txgbe_l2_tn_info *l2_tn_info = TXGBE_DEV_L2_TN(dev);
4629         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4630
4631         if (l2_tn_info->e_tag_en)
4632                 (void)txgbe_e_tag_enable(hw);
4633
4634         if (l2_tn_info->e_tag_fwd_en)
4635                 (void)txgbe_e_tag_forwarding_en_dis(dev, 1);
4636
4637         (void)txgbe_update_e_tag_eth_type(hw, l2_tn_info->e_tag_ether_type);
4638 }
4639
4640 static const struct eth_dev_ops txgbe_eth_dev_ops = {
4641         .dev_configure              = txgbe_dev_configure,
4642         .dev_infos_get              = txgbe_dev_info_get,
4643         .dev_start                  = txgbe_dev_start,
4644         .dev_stop                   = txgbe_dev_stop,
4645         .dev_set_link_up            = txgbe_dev_set_link_up,
4646         .dev_set_link_down          = txgbe_dev_set_link_down,
4647         .dev_close                  = txgbe_dev_close,
4648         .dev_reset                  = txgbe_dev_reset,
4649         .promiscuous_enable         = txgbe_dev_promiscuous_enable,
4650         .promiscuous_disable        = txgbe_dev_promiscuous_disable,
4651         .allmulticast_enable        = txgbe_dev_allmulticast_enable,
4652         .allmulticast_disable       = txgbe_dev_allmulticast_disable,
4653         .link_update                = txgbe_dev_link_update,
4654         .stats_get                  = txgbe_dev_stats_get,
4655         .xstats_get                 = txgbe_dev_xstats_get,
4656         .xstats_get_by_id           = txgbe_dev_xstats_get_by_id,
4657         .stats_reset                = txgbe_dev_stats_reset,
4658         .xstats_reset               = txgbe_dev_xstats_reset,
4659         .xstats_get_names           = txgbe_dev_xstats_get_names,
4660         .xstats_get_names_by_id     = txgbe_dev_xstats_get_names_by_id,
4661         .queue_stats_mapping_set    = txgbe_dev_queue_stats_mapping_set,
4662         .fw_version_get             = txgbe_fw_version_get,
4663         .dev_supported_ptypes_get   = txgbe_dev_supported_ptypes_get,
4664         .mtu_set                    = txgbe_dev_mtu_set,
4665         .vlan_filter_set            = txgbe_vlan_filter_set,
4666         .vlan_tpid_set              = txgbe_vlan_tpid_set,
4667         .vlan_offload_set           = txgbe_vlan_offload_set,
4668         .vlan_strip_queue_set       = txgbe_vlan_strip_queue_set,
4669         .rx_queue_start             = txgbe_dev_rx_queue_start,
4670         .rx_queue_stop              = txgbe_dev_rx_queue_stop,
4671         .tx_queue_start             = txgbe_dev_tx_queue_start,
4672         .tx_queue_stop              = txgbe_dev_tx_queue_stop,
4673         .rx_queue_setup             = txgbe_dev_rx_queue_setup,
4674         .rx_queue_intr_enable       = txgbe_dev_rx_queue_intr_enable,
4675         .rx_queue_intr_disable      = txgbe_dev_rx_queue_intr_disable,
4676         .rx_queue_release           = txgbe_dev_rx_queue_release,
4677         .tx_queue_setup             = txgbe_dev_tx_queue_setup,
4678         .tx_queue_release           = txgbe_dev_tx_queue_release,
4679         .dev_led_on                 = txgbe_dev_led_on,
4680         .dev_led_off                = txgbe_dev_led_off,
4681         .flow_ctrl_get              = txgbe_flow_ctrl_get,
4682         .flow_ctrl_set              = txgbe_flow_ctrl_set,
4683         .priority_flow_ctrl_set     = txgbe_priority_flow_ctrl_set,
4684         .mac_addr_add               = txgbe_add_rar,
4685         .mac_addr_remove            = txgbe_remove_rar,
4686         .mac_addr_set               = txgbe_set_default_mac_addr,
4687         .uc_hash_table_set          = txgbe_uc_hash_table_set,
4688         .uc_all_hash_table_set      = txgbe_uc_all_hash_table_set,
4689         .set_queue_rate_limit       = txgbe_set_queue_rate_limit,
4690         .reta_update                = txgbe_dev_rss_reta_update,
4691         .reta_query                 = txgbe_dev_rss_reta_query,
4692         .rss_hash_update            = txgbe_dev_rss_hash_update,
4693         .rss_hash_conf_get          = txgbe_dev_rss_hash_conf_get,
4694         .filter_ctrl                = txgbe_dev_filter_ctrl,
4695         .set_mc_addr_list           = txgbe_dev_set_mc_addr_list,
4696         .rxq_info_get               = txgbe_rxq_info_get,
4697         .txq_info_get               = txgbe_txq_info_get,
4698         .timesync_enable            = txgbe_timesync_enable,
4699         .timesync_disable           = txgbe_timesync_disable,
4700         .timesync_read_rx_timestamp = txgbe_timesync_read_rx_timestamp,
4701         .timesync_read_tx_timestamp = txgbe_timesync_read_tx_timestamp,
4702         .get_reg                    = txgbe_get_regs,
4703         .get_eeprom_length          = txgbe_get_eeprom_length,
4704         .get_eeprom                 = txgbe_get_eeprom,
4705         .set_eeprom                 = txgbe_set_eeprom,
4706         .get_module_info            = txgbe_get_module_info,
4707         .get_module_eeprom          = txgbe_get_module_eeprom,
4708         .get_dcb_info               = txgbe_dev_get_dcb_info,
4709         .timesync_adjust_time       = txgbe_timesync_adjust_time,
4710         .timesync_read_time         = txgbe_timesync_read_time,
4711         .timesync_write_time        = txgbe_timesync_write_time,
4712         .tx_done_cleanup            = txgbe_dev_tx_done_cleanup,
4713 };
4714
4715 RTE_PMD_REGISTER_PCI(net_txgbe, rte_txgbe_pmd);
4716 RTE_PMD_REGISTER_PCI_TABLE(net_txgbe, pci_id_txgbe_map);
4717 RTE_PMD_REGISTER_KMOD_DEP(net_txgbe, "* igb_uio | uio_pci_generic | vfio-pci");
4718
4719 RTE_LOG_REGISTER(txgbe_logtype_init, pmd.net.txgbe.init, NOTICE);
4720 RTE_LOG_REGISTER(txgbe_logtype_driver, pmd.net.txgbe.driver, NOTICE);
4721
4722 #ifdef RTE_LIBRTE_TXGBE_DEBUG_RX
4723         RTE_LOG_REGISTER(txgbe_logtype_rx, pmd.net.txgbe.rx, DEBUG);
4724 #endif
4725 #ifdef RTE_LIBRTE_TXGBE_DEBUG_TX
4726         RTE_LOG_REGISTER(txgbe_logtype_tx, pmd.net.txgbe.tx, DEBUG);
4727 #endif
4728
4729 #ifdef RTE_LIBRTE_TXGBE_DEBUG_TX_FREE
4730         RTE_LOG_REGISTER(txgbe_logtype_tx_free, pmd.net.txgbe.tx_free, DEBUG);
4731 #endif