1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2015-2020
9 #include <rte_common.h>
10 #include <rte_ethdev_pci.h>
12 #include <rte_interrupts.h>
14 #include <rte_debug.h>
16 #include <rte_memory.h>
18 #include <rte_alarm.h>
20 #include "txgbe_logs.h"
21 #include "base/txgbe.h"
22 #include "txgbe_ethdev.h"
23 #include "txgbe_rxtx.h"
24 #include "txgbe_regs_group.h"
26 static const struct reg_info txgbe_regs_general[] = {
27 {TXGBE_RST, 1, 1, "TXGBE_RST"},
28 {TXGBE_STAT, 1, 1, "TXGBE_STAT"},
29 {TXGBE_PORTCTL, 1, 1, "TXGBE_PORTCTL"},
30 {TXGBE_SDP, 1, 1, "TXGBE_SDP"},
31 {TXGBE_SDPCTL, 1, 1, "TXGBE_SDPCTL"},
32 {TXGBE_LEDCTL, 1, 1, "TXGBE_LEDCTL"},
36 static const struct reg_info txgbe_regs_nvm[] = {
40 static const struct reg_info txgbe_regs_interrupt[] = {
44 static const struct reg_info txgbe_regs_fctl_others[] = {
48 static const struct reg_info txgbe_regs_rxdma[] = {
52 static const struct reg_info txgbe_regs_rx[] = {
56 static struct reg_info txgbe_regs_tx[] = {
60 static const struct reg_info txgbe_regs_wakeup[] = {
64 static const struct reg_info txgbe_regs_dcb[] = {
68 static const struct reg_info txgbe_regs_mac[] = {
72 static const struct reg_info txgbe_regs_diagnostic[] = {
77 static const struct reg_info *txgbe_regs_others[] = {
81 txgbe_regs_fctl_others,
88 txgbe_regs_diagnostic,
91 static int txgbe_dev_set_link_up(struct rte_eth_dev *dev);
92 static int txgbe_dev_set_link_down(struct rte_eth_dev *dev);
93 static int txgbe_dev_close(struct rte_eth_dev *dev);
94 static int txgbe_dev_link_update(struct rte_eth_dev *dev,
95 int wait_to_complete);
96 static int txgbe_dev_stats_reset(struct rte_eth_dev *dev);
97 static void txgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
98 static void txgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev,
101 static void txgbe_dev_link_status_print(struct rte_eth_dev *dev);
102 static int txgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on);
103 static int txgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev);
104 static int txgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
105 static int txgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
106 static int txgbe_dev_interrupt_action(struct rte_eth_dev *dev,
107 struct rte_intr_handle *handle);
108 static void txgbe_dev_interrupt_handler(void *param);
109 static void txgbe_dev_interrupt_delayed_handler(void *param);
110 static void txgbe_configure_msix(struct rte_eth_dev *dev);
112 static int txgbe_filter_restore(struct rte_eth_dev *dev);
114 #define TXGBE_SET_HWSTRIP(h, q) do {\
115 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
116 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
117 (h)->bitmap[idx] |= 1 << bit;\
120 #define TXGBE_CLEAR_HWSTRIP(h, q) do {\
121 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
122 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
123 (h)->bitmap[idx] &= ~(1 << bit);\
126 #define TXGBE_GET_HWSTRIP(h, q, r) do {\
127 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
128 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
129 (r) = (h)->bitmap[idx] >> bit & 1;\
133 * The set of PCI devices this driver supports
135 static const struct rte_pci_id pci_id_txgbe_map[] = {
136 { RTE_PCI_DEVICE(PCI_VENDOR_ID_WANGXUN, TXGBE_DEV_ID_RAPTOR_SFP) },
137 { RTE_PCI_DEVICE(PCI_VENDOR_ID_WANGXUN, TXGBE_DEV_ID_WX1820_SFP) },
138 { .vendor_id = 0, /* sentinel */ },
141 static const struct rte_eth_desc_lim rx_desc_lim = {
142 .nb_max = TXGBE_RING_DESC_MAX,
143 .nb_min = TXGBE_RING_DESC_MIN,
144 .nb_align = TXGBE_RXD_ALIGN,
147 static const struct rte_eth_desc_lim tx_desc_lim = {
148 .nb_max = TXGBE_RING_DESC_MAX,
149 .nb_min = TXGBE_RING_DESC_MIN,
150 .nb_align = TXGBE_TXD_ALIGN,
151 .nb_seg_max = TXGBE_TX_MAX_SEG,
152 .nb_mtu_seg_max = TXGBE_TX_MAX_SEG,
155 static const struct eth_dev_ops txgbe_eth_dev_ops;
157 #define HW_XSTAT(m) {#m, offsetof(struct txgbe_hw_stats, m)}
158 #define HW_XSTAT_NAME(m, n) {n, offsetof(struct txgbe_hw_stats, m)}
159 static const struct rte_txgbe_xstats_name_off rte_txgbe_stats_strings[] = {
161 HW_XSTAT(mng_bmc2host_packets),
162 HW_XSTAT(mng_host2bmc_packets),
164 HW_XSTAT(rx_packets),
165 HW_XSTAT(tx_packets),
168 HW_XSTAT(rx_total_bytes),
169 HW_XSTAT(rx_total_packets),
170 HW_XSTAT(tx_total_packets),
171 HW_XSTAT(rx_total_missed_packets),
172 HW_XSTAT(rx_broadcast_packets),
173 HW_XSTAT(rx_multicast_packets),
174 HW_XSTAT(rx_management_packets),
175 HW_XSTAT(tx_management_packets),
176 HW_XSTAT(rx_management_dropped),
179 HW_XSTAT(rx_crc_errors),
180 HW_XSTAT(rx_illegal_byte_errors),
181 HW_XSTAT(rx_error_bytes),
182 HW_XSTAT(rx_mac_short_packet_dropped),
183 HW_XSTAT(rx_length_errors),
184 HW_XSTAT(rx_undersize_errors),
185 HW_XSTAT(rx_fragment_errors),
186 HW_XSTAT(rx_oversize_errors),
187 HW_XSTAT(rx_jabber_errors),
188 HW_XSTAT(rx_l3_l4_xsum_error),
189 HW_XSTAT(mac_local_errors),
190 HW_XSTAT(mac_remote_errors),
193 HW_XSTAT(flow_director_added_filters),
194 HW_XSTAT(flow_director_removed_filters),
195 HW_XSTAT(flow_director_filter_add_errors),
196 HW_XSTAT(flow_director_filter_remove_errors),
197 HW_XSTAT(flow_director_matched_filters),
198 HW_XSTAT(flow_director_missed_filters),
201 HW_XSTAT(rx_fcoe_crc_errors),
202 HW_XSTAT(rx_fcoe_mbuf_allocation_errors),
203 HW_XSTAT(rx_fcoe_dropped),
204 HW_XSTAT(rx_fcoe_packets),
205 HW_XSTAT(tx_fcoe_packets),
206 HW_XSTAT(rx_fcoe_bytes),
207 HW_XSTAT(tx_fcoe_bytes),
208 HW_XSTAT(rx_fcoe_no_ddp),
209 HW_XSTAT(rx_fcoe_no_ddp_ext_buff),
212 HW_XSTAT(tx_macsec_pkts_untagged),
213 HW_XSTAT(tx_macsec_pkts_encrypted),
214 HW_XSTAT(tx_macsec_pkts_protected),
215 HW_XSTAT(tx_macsec_octets_encrypted),
216 HW_XSTAT(tx_macsec_octets_protected),
217 HW_XSTAT(rx_macsec_pkts_untagged),
218 HW_XSTAT(rx_macsec_pkts_badtag),
219 HW_XSTAT(rx_macsec_pkts_nosci),
220 HW_XSTAT(rx_macsec_pkts_unknownsci),
221 HW_XSTAT(rx_macsec_octets_decrypted),
222 HW_XSTAT(rx_macsec_octets_validated),
223 HW_XSTAT(rx_macsec_sc_pkts_unchecked),
224 HW_XSTAT(rx_macsec_sc_pkts_delayed),
225 HW_XSTAT(rx_macsec_sc_pkts_late),
226 HW_XSTAT(rx_macsec_sa_pkts_ok),
227 HW_XSTAT(rx_macsec_sa_pkts_invalid),
228 HW_XSTAT(rx_macsec_sa_pkts_notvalid),
229 HW_XSTAT(rx_macsec_sa_pkts_unusedsa),
230 HW_XSTAT(rx_macsec_sa_pkts_notusingsa),
233 HW_XSTAT(rx_size_64_packets),
234 HW_XSTAT(rx_size_65_to_127_packets),
235 HW_XSTAT(rx_size_128_to_255_packets),
236 HW_XSTAT(rx_size_256_to_511_packets),
237 HW_XSTAT(rx_size_512_to_1023_packets),
238 HW_XSTAT(rx_size_1024_to_max_packets),
239 HW_XSTAT(tx_size_64_packets),
240 HW_XSTAT(tx_size_65_to_127_packets),
241 HW_XSTAT(tx_size_128_to_255_packets),
242 HW_XSTAT(tx_size_256_to_511_packets),
243 HW_XSTAT(tx_size_512_to_1023_packets),
244 HW_XSTAT(tx_size_1024_to_max_packets),
247 HW_XSTAT(tx_xon_packets),
248 HW_XSTAT(rx_xon_packets),
249 HW_XSTAT(tx_xoff_packets),
250 HW_XSTAT(rx_xoff_packets),
252 HW_XSTAT_NAME(tx_xon_packets, "tx_flow_control_xon_packets"),
253 HW_XSTAT_NAME(rx_xon_packets, "rx_flow_control_xon_packets"),
254 HW_XSTAT_NAME(tx_xoff_packets, "tx_flow_control_xoff_packets"),
255 HW_XSTAT_NAME(rx_xoff_packets, "rx_flow_control_xoff_packets"),
258 #define TXGBE_NB_HW_STATS (sizeof(rte_txgbe_stats_strings) / \
259 sizeof(rte_txgbe_stats_strings[0]))
261 /* Per-priority statistics */
262 #define UP_XSTAT(m) {#m, offsetof(struct txgbe_hw_stats, up[0].m)}
263 static const struct rte_txgbe_xstats_name_off rte_txgbe_up_strings[] = {
264 UP_XSTAT(rx_up_packets),
265 UP_XSTAT(tx_up_packets),
266 UP_XSTAT(rx_up_bytes),
267 UP_XSTAT(tx_up_bytes),
268 UP_XSTAT(rx_up_drop_packets),
270 UP_XSTAT(tx_up_xon_packets),
271 UP_XSTAT(rx_up_xon_packets),
272 UP_XSTAT(tx_up_xoff_packets),
273 UP_XSTAT(rx_up_xoff_packets),
274 UP_XSTAT(rx_up_dropped),
275 UP_XSTAT(rx_up_mbuf_alloc_errors),
276 UP_XSTAT(tx_up_xon2off_packets),
279 #define TXGBE_NB_UP_STATS (sizeof(rte_txgbe_up_strings) / \
280 sizeof(rte_txgbe_up_strings[0]))
282 /* Per-queue statistics */
283 #define QP_XSTAT(m) {#m, offsetof(struct txgbe_hw_stats, qp[0].m)}
284 static const struct rte_txgbe_xstats_name_off rte_txgbe_qp_strings[] = {
285 QP_XSTAT(rx_qp_packets),
286 QP_XSTAT(tx_qp_packets),
287 QP_XSTAT(rx_qp_bytes),
288 QP_XSTAT(tx_qp_bytes),
289 QP_XSTAT(rx_qp_mc_packets),
292 #define TXGBE_NB_QP_STATS (sizeof(rte_txgbe_qp_strings) / \
293 sizeof(rte_txgbe_qp_strings[0]))
296 txgbe_is_sfp(struct txgbe_hw *hw)
298 switch (hw->phy.type) {
299 case txgbe_phy_sfp_avago:
300 case txgbe_phy_sfp_ftl:
301 case txgbe_phy_sfp_intel:
302 case txgbe_phy_sfp_unknown:
303 case txgbe_phy_sfp_tyco_passive:
304 case txgbe_phy_sfp_unknown_passive:
311 static inline int32_t
312 txgbe_pf_reset_hw(struct txgbe_hw *hw)
317 status = hw->mac.reset_hw(hw);
319 ctrl_ext = rd32(hw, TXGBE_PORTCTL);
320 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
321 ctrl_ext |= TXGBE_PORTCTL_RSTDONE;
322 wr32(hw, TXGBE_PORTCTL, ctrl_ext);
325 if (status == TXGBE_ERR_SFP_NOT_PRESENT)
331 txgbe_enable_intr(struct rte_eth_dev *dev)
333 struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);
334 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
336 wr32(hw, TXGBE_IENMISC, intr->mask_misc);
337 wr32(hw, TXGBE_IMC(0), TXGBE_IMC_MASK);
338 wr32(hw, TXGBE_IMC(1), TXGBE_IMC_MASK);
343 txgbe_disable_intr(struct txgbe_hw *hw)
345 PMD_INIT_FUNC_TRACE();
347 wr32(hw, TXGBE_IENMISC, ~BIT_MASK32);
348 wr32(hw, TXGBE_IMS(0), TXGBE_IMC_MASK);
349 wr32(hw, TXGBE_IMS(1), TXGBE_IMC_MASK);
354 txgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
359 struct txgbe_hw *hw = TXGBE_DEV_HW(eth_dev);
360 struct txgbe_stat_mappings *stat_mappings =
361 TXGBE_DEV_STAT_MAPPINGS(eth_dev);
362 uint32_t qsmr_mask = 0;
363 uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
367 if (hw->mac.type != txgbe_mac_raptor)
370 if (stat_idx & !QMAP_FIELD_RESERVED_BITS_MASK)
373 PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d",
374 (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
377 n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
378 if (n >= TXGBE_NB_STAT_MAPPING) {
379 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
382 offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
384 /* Now clear any previous stat_idx set */
385 clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
387 stat_mappings->tqsm[n] &= ~clearing_mask;
389 stat_mappings->rqsm[n] &= ~clearing_mask;
391 q_map = (uint32_t)stat_idx;
392 q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
393 qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
395 stat_mappings->tqsm[n] |= qsmr_mask;
397 stat_mappings->rqsm[n] |= qsmr_mask;
399 PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d",
400 (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
402 PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
403 is_rx ? stat_mappings->rqsm[n] : stat_mappings->tqsm[n]);
408 txgbe_dcb_init(struct txgbe_hw *hw, struct txgbe_dcb_config *dcb_config)
412 struct txgbe_dcb_tc_config *tc;
414 UNREFERENCED_PARAMETER(hw);
416 dcb_config->num_tcs.pg_tcs = TXGBE_DCB_TC_MAX;
417 dcb_config->num_tcs.pfc_tcs = TXGBE_DCB_TC_MAX;
418 bwgp = (u8)(100 / TXGBE_DCB_TC_MAX);
419 for (i = 0; i < TXGBE_DCB_TC_MAX; i++) {
420 tc = &dcb_config->tc_config[i];
421 tc->path[TXGBE_DCB_TX_CONFIG].bwg_id = i;
422 tc->path[TXGBE_DCB_TX_CONFIG].bwg_percent = bwgp + (i & 1);
423 tc->path[TXGBE_DCB_RX_CONFIG].bwg_id = i;
424 tc->path[TXGBE_DCB_RX_CONFIG].bwg_percent = bwgp + (i & 1);
425 tc->pfc = txgbe_dcb_pfc_disabled;
428 /* Initialize default user to priority mapping, UPx->TC0 */
429 tc = &dcb_config->tc_config[0];
430 tc->path[TXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
431 tc->path[TXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
432 for (i = 0; i < TXGBE_DCB_BWG_MAX; i++) {
433 dcb_config->bw_percentage[i][TXGBE_DCB_TX_CONFIG] = 100;
434 dcb_config->bw_percentage[i][TXGBE_DCB_RX_CONFIG] = 100;
436 dcb_config->rx_pba_cfg = txgbe_dcb_pba_equal;
437 dcb_config->pfc_mode_enable = false;
438 dcb_config->vt_mode = true;
439 dcb_config->round_robin_enable = false;
440 /* support all DCB capabilities */
441 dcb_config->support.capabilities = 0xFF;
445 * Ensure that all locks are released before first NVM or PHY access
448 txgbe_swfw_lock_reset(struct txgbe_hw *hw)
453 * These ones are more tricky since they are common to all ports; but
454 * swfw_sync retries last long enough (1s) to be almost sure that if
455 * lock can not be taken it is due to an improper lock of the
458 mask = TXGBE_MNGSEM_SWPHY |
460 TXGBE_MNGSEM_SWFLASH;
461 if (hw->mac.acquire_swfw_sync(hw, mask) < 0)
462 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
464 hw->mac.release_swfw_sync(hw, mask);
468 eth_txgbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params __rte_unused)
470 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
471 struct txgbe_hw *hw = TXGBE_DEV_HW(eth_dev);
472 struct txgbe_vfta *shadow_vfta = TXGBE_DEV_VFTA(eth_dev);
473 struct txgbe_hwstrip *hwstrip = TXGBE_DEV_HWSTRIP(eth_dev);
474 struct txgbe_dcb_config *dcb_config = TXGBE_DEV_DCB_CONFIG(eth_dev);
475 struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(eth_dev);
476 struct txgbe_bw_conf *bw_conf = TXGBE_DEV_BW_CONF(eth_dev);
477 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
478 const struct rte_memzone *mz;
483 PMD_INIT_FUNC_TRACE();
485 eth_dev->dev_ops = &txgbe_eth_dev_ops;
486 eth_dev->rx_queue_count = txgbe_dev_rx_queue_count;
487 eth_dev->rx_descriptor_status = txgbe_dev_rx_descriptor_status;
488 eth_dev->tx_descriptor_status = txgbe_dev_tx_descriptor_status;
489 eth_dev->rx_pkt_burst = &txgbe_recv_pkts;
490 eth_dev->tx_pkt_burst = &txgbe_xmit_pkts;
491 eth_dev->tx_pkt_prepare = &txgbe_prep_pkts;
494 * For secondary processes, we don't initialise any further as primary
495 * has already done this work. Only check we don't need a different
496 * RX and TX function.
498 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
499 struct txgbe_tx_queue *txq;
500 /* TX queue function in primary, set by last queue initialized
501 * Tx queue may not initialized by primary process
503 if (eth_dev->data->tx_queues) {
504 uint16_t nb_tx_queues = eth_dev->data->nb_tx_queues;
505 txq = eth_dev->data->tx_queues[nb_tx_queues - 1];
506 txgbe_set_tx_function(eth_dev, txq);
508 /* Use default TX function if we get here */
509 PMD_INIT_LOG(NOTICE, "No TX queues configured yet. "
510 "Using default TX function.");
513 txgbe_set_rx_function(eth_dev);
518 rte_eth_copy_pci_info(eth_dev, pci_dev);
520 /* Vendor and Device ID need to be set before init of shared code */
521 hw->device_id = pci_dev->id.device_id;
522 hw->vendor_id = pci_dev->id.vendor_id;
523 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
524 hw->allow_unsupported_sfp = 1;
526 /* Reserve memory for interrupt status block */
527 mz = rte_eth_dma_zone_reserve(eth_dev, "txgbe_driver", -1,
528 16, TXGBE_ALIGN, SOCKET_ID_ANY);
532 hw->isb_dma = TMZ_PADDR(mz);
533 hw->isb_mem = TMZ_VADDR(mz);
535 /* Initialize the shared code (base driver) */
536 err = txgbe_init_shared_code(hw);
538 PMD_INIT_LOG(ERR, "Shared code init failed: %d", err);
542 /* Unlock any pending hardware semaphore */
543 txgbe_swfw_lock_reset(hw);
545 /* Initialize DCB configuration*/
546 memset(dcb_config, 0, sizeof(struct txgbe_dcb_config));
547 txgbe_dcb_init(hw, dcb_config);
549 /* Get Hardware Flow Control setting */
550 hw->fc.requested_mode = txgbe_fc_full;
551 hw->fc.current_mode = txgbe_fc_full;
552 hw->fc.pause_time = TXGBE_FC_PAUSE_TIME;
553 for (i = 0; i < TXGBE_DCB_TC_MAX; i++) {
554 hw->fc.low_water[i] = TXGBE_FC_XON_LOTH;
555 hw->fc.high_water[i] = TXGBE_FC_XOFF_HITH;
559 err = hw->rom.init_params(hw);
561 PMD_INIT_LOG(ERR, "The EEPROM init failed: %d", err);
565 /* Make sure we have a good EEPROM before we read from it */
566 err = hw->rom.validate_checksum(hw, &csum);
568 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", err);
572 err = hw->mac.init_hw(hw);
575 * Devices with copper phys will fail to initialise if txgbe_init_hw()
576 * is called too soon after the kernel driver unbinding/binding occurs.
577 * The failure occurs in txgbe_identify_phy() for all devices,
578 * but for non-copper devies, txgbe_identify_sfp_module() is
579 * also called. See txgbe_identify_phy(). The reason for the
580 * failure is not known, and only occuts when virtualisation features
581 * are disabled in the bios. A delay of 200ms was found to be enough by
582 * trial-and-error, and is doubled to be safe.
584 if (err && hw->phy.media_type == txgbe_media_type_copper) {
586 err = hw->mac.init_hw(hw);
589 if (err == TXGBE_ERR_SFP_NOT_PRESENT)
592 if (err == TXGBE_ERR_EEPROM_VERSION) {
593 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
594 "LOM. Please be aware there may be issues associated "
595 "with your hardware.");
596 PMD_INIT_LOG(ERR, "If you are experiencing problems "
597 "please contact your hardware representative "
598 "who provided you with this hardware.");
599 } else if (err == TXGBE_ERR_SFP_NOT_SUPPORTED) {
600 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
603 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", err);
607 /* Reset the hw statistics */
608 txgbe_dev_stats_reset(eth_dev);
610 /* disable interrupt */
611 txgbe_disable_intr(hw);
613 /* Allocate memory for storing MAC addresses */
614 eth_dev->data->mac_addrs = rte_zmalloc("txgbe", RTE_ETHER_ADDR_LEN *
615 hw->mac.num_rar_entries, 0);
616 if (eth_dev->data->mac_addrs == NULL) {
618 "Failed to allocate %u bytes needed to store "
620 RTE_ETHER_ADDR_LEN * hw->mac.num_rar_entries);
624 /* Copy the permanent MAC address */
625 rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.perm_addr,
626 ð_dev->data->mac_addrs[0]);
628 /* Allocate memory for storing hash filter MAC addresses */
629 eth_dev->data->hash_mac_addrs = rte_zmalloc("txgbe",
630 RTE_ETHER_ADDR_LEN * TXGBE_VMDQ_NUM_UC_MAC, 0);
631 if (eth_dev->data->hash_mac_addrs == NULL) {
633 "Failed to allocate %d bytes needed to store MAC addresses",
634 RTE_ETHER_ADDR_LEN * TXGBE_VMDQ_NUM_UC_MAC);
638 /* initialize the vfta */
639 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
641 /* initialize the hw strip bitmap*/
642 memset(hwstrip, 0, sizeof(*hwstrip));
644 /* initialize PF if max_vfs not zero */
645 ret = txgbe_pf_host_init(eth_dev);
647 rte_free(eth_dev->data->mac_addrs);
648 eth_dev->data->mac_addrs = NULL;
649 rte_free(eth_dev->data->hash_mac_addrs);
650 eth_dev->data->hash_mac_addrs = NULL;
654 ctrl_ext = rd32(hw, TXGBE_PORTCTL);
655 /* let hardware know driver is loaded */
656 ctrl_ext |= TXGBE_PORTCTL_DRVLOAD;
657 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
658 ctrl_ext |= TXGBE_PORTCTL_RSTDONE;
659 wr32(hw, TXGBE_PORTCTL, ctrl_ext);
662 if (txgbe_is_sfp(hw) && hw->phy.sfp_type != txgbe_sfp_type_not_present)
663 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
664 (int)hw->mac.type, (int)hw->phy.type,
665 (int)hw->phy.sfp_type);
667 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
668 (int)hw->mac.type, (int)hw->phy.type);
670 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
671 eth_dev->data->port_id, pci_dev->id.vendor_id,
672 pci_dev->id.device_id);
674 rte_intr_callback_register(intr_handle,
675 txgbe_dev_interrupt_handler, eth_dev);
677 /* enable uio/vfio intr/eventfd mapping */
678 rte_intr_enable(intr_handle);
680 /* enable support intr */
681 txgbe_enable_intr(eth_dev);
683 /* initialize filter info */
684 memset(filter_info, 0,
685 sizeof(struct txgbe_filter_info));
687 /* initialize 5tuple filter list */
688 TAILQ_INIT(&filter_info->fivetuple_list);
690 /* initialize bandwidth configuration info */
691 memset(bw_conf, 0, sizeof(struct txgbe_bw_conf));
697 eth_txgbe_dev_uninit(struct rte_eth_dev *eth_dev)
699 PMD_INIT_FUNC_TRACE();
701 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
704 txgbe_dev_close(eth_dev);
709 static int txgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev)
711 struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(eth_dev);
712 struct txgbe_5tuple_filter *p_5tuple;
714 while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) {
715 TAILQ_REMOVE(&filter_info->fivetuple_list,
720 memset(filter_info->fivetuple_mask, 0,
721 sizeof(uint32_t) * TXGBE_5TUPLE_ARRAY_SIZE);
727 eth_txgbe_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
728 struct rte_pci_device *pci_dev)
730 struct rte_eth_dev *pf_ethdev;
731 struct rte_eth_devargs eth_da;
734 if (pci_dev->device.devargs) {
735 retval = rte_eth_devargs_parse(pci_dev->device.devargs->args,
740 memset(ð_da, 0, sizeof(eth_da));
743 retval = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
744 sizeof(struct txgbe_adapter),
745 eth_dev_pci_specific_init, pci_dev,
746 eth_txgbe_dev_init, NULL);
748 if (retval || eth_da.nb_representor_ports < 1)
751 pf_ethdev = rte_eth_dev_allocated(pci_dev->device.name);
752 if (pf_ethdev == NULL)
758 static int eth_txgbe_pci_remove(struct rte_pci_device *pci_dev)
760 struct rte_eth_dev *ethdev;
762 ethdev = rte_eth_dev_allocated(pci_dev->device.name);
766 return rte_eth_dev_destroy(ethdev, eth_txgbe_dev_uninit);
769 static struct rte_pci_driver rte_txgbe_pmd = {
770 .id_table = pci_id_txgbe_map,
771 .drv_flags = RTE_PCI_DRV_NEED_MAPPING |
772 RTE_PCI_DRV_INTR_LSC,
773 .probe = eth_txgbe_pci_probe,
774 .remove = eth_txgbe_pci_remove,
778 txgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
780 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
781 struct txgbe_vfta *shadow_vfta = TXGBE_DEV_VFTA(dev);
786 vid_idx = (uint32_t)((vlan_id >> 5) & 0x7F);
787 vid_bit = (uint32_t)(1 << (vlan_id & 0x1F));
788 vfta = rd32(hw, TXGBE_VLANTBL(vid_idx));
793 wr32(hw, TXGBE_VLANTBL(vid_idx), vfta);
795 /* update local VFTA copy */
796 shadow_vfta->vfta[vid_idx] = vfta;
802 txgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
804 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
805 struct txgbe_rx_queue *rxq;
807 uint32_t rxcfg, rxbal, rxbah;
810 txgbe_vlan_hw_strip_enable(dev, queue);
812 txgbe_vlan_hw_strip_disable(dev, queue);
814 rxq = dev->data->rx_queues[queue];
815 rxbal = rd32(hw, TXGBE_RXBAL(rxq->reg_idx));
816 rxbah = rd32(hw, TXGBE_RXBAH(rxq->reg_idx));
817 rxcfg = rd32(hw, TXGBE_RXCFG(rxq->reg_idx));
818 if (rxq->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) {
819 restart = (rxcfg & TXGBE_RXCFG_ENA) &&
820 !(rxcfg & TXGBE_RXCFG_VLAN);
821 rxcfg |= TXGBE_RXCFG_VLAN;
823 restart = (rxcfg & TXGBE_RXCFG_ENA) &&
824 (rxcfg & TXGBE_RXCFG_VLAN);
825 rxcfg &= ~TXGBE_RXCFG_VLAN;
827 rxcfg &= ~TXGBE_RXCFG_ENA;
830 /* set vlan strip for ring */
831 txgbe_dev_rx_queue_stop(dev, queue);
832 wr32(hw, TXGBE_RXBAL(rxq->reg_idx), rxbal);
833 wr32(hw, TXGBE_RXBAH(rxq->reg_idx), rxbah);
834 wr32(hw, TXGBE_RXCFG(rxq->reg_idx), rxcfg);
835 txgbe_dev_rx_queue_start(dev, queue);
840 txgbe_vlan_tpid_set(struct rte_eth_dev *dev,
841 enum rte_vlan_type vlan_type,
844 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
846 uint32_t portctrl, vlan_ext, qinq;
848 portctrl = rd32(hw, TXGBE_PORTCTL);
850 vlan_ext = (portctrl & TXGBE_PORTCTL_VLANEXT);
851 qinq = vlan_ext && (portctrl & TXGBE_PORTCTL_QINQ);
853 case ETH_VLAN_TYPE_INNER:
855 wr32m(hw, TXGBE_VLANCTL,
856 TXGBE_VLANCTL_TPID_MASK,
857 TXGBE_VLANCTL_TPID(tpid));
858 wr32m(hw, TXGBE_DMATXCTRL,
859 TXGBE_DMATXCTRL_TPID_MASK,
860 TXGBE_DMATXCTRL_TPID(tpid));
863 PMD_DRV_LOG(ERR, "Inner type is not supported"
868 wr32m(hw, TXGBE_TAGTPID(0),
869 TXGBE_TAGTPID_LSB_MASK,
870 TXGBE_TAGTPID_LSB(tpid));
873 case ETH_VLAN_TYPE_OUTER:
875 /* Only the high 16-bits is valid */
876 wr32m(hw, TXGBE_EXTAG,
877 TXGBE_EXTAG_VLAN_MASK,
878 TXGBE_EXTAG_VLAN(tpid));
880 wr32m(hw, TXGBE_VLANCTL,
881 TXGBE_VLANCTL_TPID_MASK,
882 TXGBE_VLANCTL_TPID(tpid));
883 wr32m(hw, TXGBE_DMATXCTRL,
884 TXGBE_DMATXCTRL_TPID_MASK,
885 TXGBE_DMATXCTRL_TPID(tpid));
889 wr32m(hw, TXGBE_TAGTPID(0),
890 TXGBE_TAGTPID_MSB_MASK,
891 TXGBE_TAGTPID_MSB(tpid));
895 PMD_DRV_LOG(ERR, "Unsupported VLAN type %d", vlan_type);
903 txgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
905 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
908 PMD_INIT_FUNC_TRACE();
910 /* Filter Table Disable */
911 vlnctrl = rd32(hw, TXGBE_VLANCTL);
912 vlnctrl &= ~TXGBE_VLANCTL_VFE;
913 wr32(hw, TXGBE_VLANCTL, vlnctrl);
917 txgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
919 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
920 struct txgbe_vfta *shadow_vfta = TXGBE_DEV_VFTA(dev);
924 PMD_INIT_FUNC_TRACE();
926 /* Filter Table Enable */
927 vlnctrl = rd32(hw, TXGBE_VLANCTL);
928 vlnctrl &= ~TXGBE_VLANCTL_CFIENA;
929 vlnctrl |= TXGBE_VLANCTL_VFE;
930 wr32(hw, TXGBE_VLANCTL, vlnctrl);
932 /* write whatever is in local vfta copy */
933 for (i = 0; i < TXGBE_VFTA_SIZE; i++)
934 wr32(hw, TXGBE_VLANTBL(i), shadow_vfta->vfta[i]);
938 txgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
940 struct txgbe_hwstrip *hwstrip = TXGBE_DEV_HWSTRIP(dev);
941 struct txgbe_rx_queue *rxq;
943 if (queue >= TXGBE_MAX_RX_QUEUE_NUM)
947 TXGBE_SET_HWSTRIP(hwstrip, queue);
949 TXGBE_CLEAR_HWSTRIP(hwstrip, queue);
951 if (queue >= dev->data->nb_rx_queues)
954 rxq = dev->data->rx_queues[queue];
957 rxq->vlan_flags = PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
958 rxq->offloads |= DEV_RX_OFFLOAD_VLAN_STRIP;
960 rxq->vlan_flags = PKT_RX_VLAN;
961 rxq->offloads &= ~DEV_RX_OFFLOAD_VLAN_STRIP;
966 txgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
968 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
971 PMD_INIT_FUNC_TRACE();
973 ctrl = rd32(hw, TXGBE_RXCFG(queue));
974 ctrl &= ~TXGBE_RXCFG_VLAN;
975 wr32(hw, TXGBE_RXCFG(queue), ctrl);
977 /* record those setting for HW strip per queue */
978 txgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
982 txgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
984 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
987 PMD_INIT_FUNC_TRACE();
989 ctrl = rd32(hw, TXGBE_RXCFG(queue));
990 ctrl |= TXGBE_RXCFG_VLAN;
991 wr32(hw, TXGBE_RXCFG(queue), ctrl);
993 /* record those setting for HW strip per queue */
994 txgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
998 txgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
1000 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
1003 PMD_INIT_FUNC_TRACE();
1005 ctrl = rd32(hw, TXGBE_PORTCTL);
1006 ctrl &= ~TXGBE_PORTCTL_VLANEXT;
1007 ctrl &= ~TXGBE_PORTCTL_QINQ;
1008 wr32(hw, TXGBE_PORTCTL, ctrl);
1012 txgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
1014 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
1015 struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
1016 struct rte_eth_txmode *txmode = &dev->data->dev_conf.txmode;
1019 PMD_INIT_FUNC_TRACE();
1021 ctrl = rd32(hw, TXGBE_PORTCTL);
1022 ctrl |= TXGBE_PORTCTL_VLANEXT;
1023 if (rxmode->offloads & DEV_RX_OFFLOAD_QINQ_STRIP ||
1024 txmode->offloads & DEV_TX_OFFLOAD_QINQ_INSERT)
1025 ctrl |= TXGBE_PORTCTL_QINQ;
1026 wr32(hw, TXGBE_PORTCTL, ctrl);
1030 txgbe_vlan_hw_strip_config(struct rte_eth_dev *dev)
1032 struct txgbe_rx_queue *rxq;
1035 PMD_INIT_FUNC_TRACE();
1037 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1038 rxq = dev->data->rx_queues[i];
1040 if (rxq->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1041 txgbe_vlan_strip_queue_set(dev, i, 1);
1043 txgbe_vlan_strip_queue_set(dev, i, 0);
1048 txgbe_config_vlan_strip_on_all_queues(struct rte_eth_dev *dev, int mask)
1051 struct rte_eth_rxmode *rxmode;
1052 struct txgbe_rx_queue *rxq;
1054 if (mask & ETH_VLAN_STRIP_MASK) {
1055 rxmode = &dev->data->dev_conf.rxmode;
1056 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1057 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1058 rxq = dev->data->rx_queues[i];
1059 rxq->offloads |= DEV_RX_OFFLOAD_VLAN_STRIP;
1062 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1063 rxq = dev->data->rx_queues[i];
1064 rxq->offloads &= ~DEV_RX_OFFLOAD_VLAN_STRIP;
1070 txgbe_vlan_offload_config(struct rte_eth_dev *dev, int mask)
1072 struct rte_eth_rxmode *rxmode;
1073 rxmode = &dev->data->dev_conf.rxmode;
1075 if (mask & ETH_VLAN_STRIP_MASK)
1076 txgbe_vlan_hw_strip_config(dev);
1078 if (mask & ETH_VLAN_FILTER_MASK) {
1079 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
1080 txgbe_vlan_hw_filter_enable(dev);
1082 txgbe_vlan_hw_filter_disable(dev);
1085 if (mask & ETH_VLAN_EXTEND_MASK) {
1086 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
1087 txgbe_vlan_hw_extend_enable(dev);
1089 txgbe_vlan_hw_extend_disable(dev);
1096 txgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1098 txgbe_config_vlan_strip_on_all_queues(dev, mask);
1100 txgbe_vlan_offload_config(dev, mask);
1106 txgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1108 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
1109 /* VLNCTL: enable vlan filtering and allow all vlan tags through */
1110 uint32_t vlanctrl = rd32(hw, TXGBE_VLANCTL);
1112 vlanctrl |= TXGBE_VLANCTL_VFE; /* enable vlan filters */
1113 wr32(hw, TXGBE_VLANCTL, vlanctrl);
1117 txgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q)
1119 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1124 RTE_ETH_DEV_SRIOV(dev).active = ETH_64_POOLS;
1127 RTE_ETH_DEV_SRIOV(dev).active = ETH_32_POOLS;
1133 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool =
1134 TXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
1135 RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx =
1136 pci_dev->max_vfs * RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
1141 txgbe_check_mq_mode(struct rte_eth_dev *dev)
1143 struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
1144 uint16_t nb_rx_q = dev->data->nb_rx_queues;
1145 uint16_t nb_tx_q = dev->data->nb_tx_queues;
1147 if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
1148 /* check multi-queue mode */
1149 switch (dev_conf->rxmode.mq_mode) {
1150 case ETH_MQ_RX_VMDQ_DCB:
1151 PMD_INIT_LOG(INFO, "ETH_MQ_RX_VMDQ_DCB mode supported in SRIOV");
1153 case ETH_MQ_RX_VMDQ_DCB_RSS:
1154 /* DCB/RSS VMDQ in SRIOV mode, not implement yet */
1155 PMD_INIT_LOG(ERR, "SRIOV active,"
1156 " unsupported mq_mode rx %d.",
1157 dev_conf->rxmode.mq_mode);
1160 case ETH_MQ_RX_VMDQ_RSS:
1161 dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_RSS;
1162 if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)
1163 if (txgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) {
1164 PMD_INIT_LOG(ERR, "SRIOV is active,"
1165 " invalid queue number"
1166 " for VMDQ RSS, allowed"
1167 " value are 1, 2 or 4.");
1171 case ETH_MQ_RX_VMDQ_ONLY:
1172 case ETH_MQ_RX_NONE:
1173 /* if nothing mq mode configure, use default scheme */
1174 dev->data->dev_conf.rxmode.mq_mode =
1175 ETH_MQ_RX_VMDQ_ONLY;
1177 default: /* ETH_MQ_RX_DCB, ETH_MQ_RX_DCB_RSS or ETH_MQ_TX_DCB*/
1178 /* SRIOV only works in VMDq enable mode */
1179 PMD_INIT_LOG(ERR, "SRIOV is active,"
1180 " wrong mq_mode rx %d.",
1181 dev_conf->rxmode.mq_mode);
1185 switch (dev_conf->txmode.mq_mode) {
1186 case ETH_MQ_TX_VMDQ_DCB:
1187 PMD_INIT_LOG(INFO, "ETH_MQ_TX_VMDQ_DCB mode supported in SRIOV");
1188 dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_DCB;
1190 default: /* ETH_MQ_TX_VMDQ_ONLY or ETH_MQ_TX_NONE */
1191 dev->data->dev_conf.txmode.mq_mode =
1192 ETH_MQ_TX_VMDQ_ONLY;
1196 /* check valid queue number */
1197 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) ||
1198 (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) {
1199 PMD_INIT_LOG(ERR, "SRIOV is active,"
1200 " nb_rx_q=%d nb_tx_q=%d queue number"
1201 " must be less than or equal to %d.",
1203 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool);
1207 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
1208 PMD_INIT_LOG(ERR, "VMDQ+DCB+RSS mq_mode is"
1212 /* check configuration for vmdb+dcb mode */
1213 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB) {
1214 const struct rte_eth_vmdq_dcb_conf *conf;
1216 if (nb_rx_q != TXGBE_VMDQ_DCB_NB_QUEUES) {
1217 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.",
1218 TXGBE_VMDQ_DCB_NB_QUEUES);
1221 conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf;
1222 if (!(conf->nb_queue_pools == ETH_16_POOLS ||
1223 conf->nb_queue_pools == ETH_32_POOLS)) {
1224 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
1225 " nb_queue_pools must be %d or %d.",
1226 ETH_16_POOLS, ETH_32_POOLS);
1230 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) {
1231 const struct rte_eth_vmdq_dcb_tx_conf *conf;
1233 if (nb_tx_q != TXGBE_VMDQ_DCB_NB_QUEUES) {
1234 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d",
1235 TXGBE_VMDQ_DCB_NB_QUEUES);
1238 conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf;
1239 if (!(conf->nb_queue_pools == ETH_16_POOLS ||
1240 conf->nb_queue_pools == ETH_32_POOLS)) {
1241 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
1242 " nb_queue_pools != %d and"
1243 " nb_queue_pools != %d.",
1244 ETH_16_POOLS, ETH_32_POOLS);
1249 /* For DCB mode check our configuration before we go further */
1250 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_DCB) {
1251 const struct rte_eth_dcb_rx_conf *conf;
1253 conf = &dev_conf->rx_adv_conf.dcb_rx_conf;
1254 if (!(conf->nb_tcs == ETH_4_TCS ||
1255 conf->nb_tcs == ETH_8_TCS)) {
1256 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
1257 " and nb_tcs != %d.",
1258 ETH_4_TCS, ETH_8_TCS);
1263 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_DCB) {
1264 const struct rte_eth_dcb_tx_conf *conf;
1266 conf = &dev_conf->tx_adv_conf.dcb_tx_conf;
1267 if (!(conf->nb_tcs == ETH_4_TCS ||
1268 conf->nb_tcs == ETH_8_TCS)) {
1269 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
1270 " and nb_tcs != %d.",
1271 ETH_4_TCS, ETH_8_TCS);
1280 txgbe_dev_configure(struct rte_eth_dev *dev)
1282 struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);
1283 struct txgbe_adapter *adapter = TXGBE_DEV_ADAPTER(dev);
1286 PMD_INIT_FUNC_TRACE();
1288 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
1289 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
1291 /* multiple queue mode checking */
1292 ret = txgbe_check_mq_mode(dev);
1294 PMD_DRV_LOG(ERR, "txgbe_check_mq_mode fails with %d.",
1299 /* set flag to update link status after init */
1300 intr->flags |= TXGBE_FLAG_NEED_LINK_UPDATE;
1303 * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
1304 * allocation Rx preconditions we will reset it.
1306 adapter->rx_bulk_alloc_allowed = true;
1312 txgbe_dev_phy_intr_setup(struct rte_eth_dev *dev)
1314 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
1315 struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);
1318 gpie = rd32(hw, TXGBE_GPIOINTEN);
1319 gpie |= TXGBE_GPIOBIT_6;
1320 wr32(hw, TXGBE_GPIOINTEN, gpie);
1321 intr->mask_misc |= TXGBE_ICRMISC_GPIO;
1325 txgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
1326 uint16_t tx_rate, uint64_t q_msk)
1328 struct txgbe_hw *hw;
1329 struct txgbe_vf_info *vfinfo;
1330 struct rte_eth_link link;
1331 uint8_t nb_q_per_pool;
1332 uint32_t queue_stride;
1333 uint32_t queue_idx, idx = 0, vf_idx;
1335 uint16_t total_rate = 0;
1336 struct rte_pci_device *pci_dev;
1339 pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1340 ret = rte_eth_link_get_nowait(dev->data->port_id, &link);
1344 if (vf >= pci_dev->max_vfs)
1347 if (tx_rate > link.link_speed)
1353 hw = TXGBE_DEV_HW(dev);
1354 vfinfo = *(TXGBE_DEV_VFDATA(dev));
1355 nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
1356 queue_stride = TXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
1357 queue_idx = vf * queue_stride;
1358 queue_end = queue_idx + nb_q_per_pool - 1;
1359 if (queue_end >= hw->mac.max_tx_queues)
1363 for (vf_idx = 0; vf_idx < pci_dev->max_vfs; vf_idx++) {
1366 for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
1368 total_rate += vfinfo[vf_idx].tx_rate[idx];
1374 /* Store tx_rate for this vf. */
1375 for (idx = 0; idx < nb_q_per_pool; idx++) {
1376 if (((uint64_t)0x1 << idx) & q_msk) {
1377 if (vfinfo[vf].tx_rate[idx] != tx_rate)
1378 vfinfo[vf].tx_rate[idx] = tx_rate;
1379 total_rate += tx_rate;
1383 if (total_rate > dev->data->dev_link.link_speed) {
1384 /* Reset stored TX rate of the VF if it causes exceed
1387 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
1391 /* Set ARBTXRATE of each queue/pool for vf X */
1392 for (; queue_idx <= queue_end; queue_idx++) {
1394 txgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
1402 * Configure device link speed and setup link.
1403 * It returns 0 on success.
1406 txgbe_dev_start(struct rte_eth_dev *dev)
1408 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
1409 struct txgbe_hw_stats *hw_stats = TXGBE_DEV_STATS(dev);
1410 struct txgbe_vf_info *vfinfo = *TXGBE_DEV_VFDATA(dev);
1411 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1412 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1413 uint32_t intr_vector = 0;
1415 bool link_up = false, negotiate = 0;
1417 uint32_t allowed_speeds = 0;
1421 uint32_t *link_speeds;
1423 PMD_INIT_FUNC_TRACE();
1425 /* TXGBE devices don't support:
1426 * - half duplex (checked afterwards for valid speeds)
1427 * - fixed speed: TODO implement
1429 if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
1431 "Invalid link_speeds for port %u, fix speed not supported",
1432 dev->data->port_id);
1436 /* Stop the link setup handler before resetting the HW. */
1437 rte_eal_alarm_cancel(txgbe_dev_setup_link_alarm_handler, dev);
1439 /* disable uio/vfio intr/eventfd mapping */
1440 rte_intr_disable(intr_handle);
1443 hw->adapter_stopped = 0;
1446 /* reinitialize adapter
1447 * this calls reset and start
1449 hw->nb_rx_queues = dev->data->nb_rx_queues;
1450 hw->nb_tx_queues = dev->data->nb_tx_queues;
1451 status = txgbe_pf_reset_hw(hw);
1454 hw->mac.start_hw(hw);
1455 hw->mac.get_link_status = true;
1457 /* configure PF module if SRIOV enabled */
1458 txgbe_pf_host_configure(dev);
1460 txgbe_dev_phy_intr_setup(dev);
1462 /* check and configure queue intr-vector mapping */
1463 if ((rte_intr_cap_multiple(intr_handle) ||
1464 !RTE_ETH_DEV_SRIOV(dev).active) &&
1465 dev->data->dev_conf.intr_conf.rxq != 0) {
1466 intr_vector = dev->data->nb_rx_queues;
1467 if (rte_intr_efd_enable(intr_handle, intr_vector))
1471 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1472 intr_handle->intr_vec =
1473 rte_zmalloc("intr_vec",
1474 dev->data->nb_rx_queues * sizeof(int), 0);
1475 if (intr_handle->intr_vec == NULL) {
1476 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
1477 " intr_vec", dev->data->nb_rx_queues);
1482 /* confiugre msix for sleep until rx interrupt */
1483 txgbe_configure_msix(dev);
1485 /* initialize transmission unit */
1486 txgbe_dev_tx_init(dev);
1488 /* This can fail when allocating mbufs for descriptor rings */
1489 err = txgbe_dev_rx_init(dev);
1491 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
1495 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
1496 ETH_VLAN_EXTEND_MASK;
1497 err = txgbe_vlan_offload_config(dev, mask);
1499 PMD_INIT_LOG(ERR, "Unable to set VLAN offload");
1503 if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1504 /* Enable vlan filtering for VMDq */
1505 txgbe_vmdq_vlan_hw_filter_enable(dev);
1508 /* Configure DCB hw */
1509 txgbe_configure_pb(dev);
1510 txgbe_configure_port(dev);
1511 txgbe_configure_dcb(dev);
1513 /* Restore vf rate limit */
1514 if (vfinfo != NULL) {
1515 for (vf = 0; vf < pci_dev->max_vfs; vf++)
1516 for (idx = 0; idx < TXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
1517 if (vfinfo[vf].tx_rate[idx] != 0)
1518 txgbe_set_vf_rate_limit(dev, vf,
1519 vfinfo[vf].tx_rate[idx],
1523 err = txgbe_dev_rxtx_start(dev);
1525 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
1529 /* Skip link setup if loopback mode is enabled. */
1530 if (hw->mac.type == txgbe_mac_raptor &&
1531 dev->data->dev_conf.lpbk_mode)
1532 goto skip_link_setup;
1534 if (txgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
1535 err = hw->mac.setup_sfp(hw);
1540 if (hw->phy.media_type == txgbe_media_type_copper) {
1541 /* Turn on the copper */
1542 hw->phy.set_phy_power(hw, true);
1544 /* Turn on the laser */
1545 hw->mac.enable_tx_laser(hw);
1548 err = hw->mac.check_link(hw, &speed, &link_up, 0);
1551 dev->data->dev_link.link_status = link_up;
1553 err = hw->mac.get_link_capabilities(hw, &speed, &negotiate);
1557 allowed_speeds = ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
1560 link_speeds = &dev->data->dev_conf.link_speeds;
1561 if (*link_speeds & ~allowed_speeds) {
1562 PMD_INIT_LOG(ERR, "Invalid link setting");
1567 if (*link_speeds == ETH_LINK_SPEED_AUTONEG) {
1568 speed = (TXGBE_LINK_SPEED_100M_FULL |
1569 TXGBE_LINK_SPEED_1GB_FULL |
1570 TXGBE_LINK_SPEED_10GB_FULL);
1572 if (*link_speeds & ETH_LINK_SPEED_10G)
1573 speed |= TXGBE_LINK_SPEED_10GB_FULL;
1574 if (*link_speeds & ETH_LINK_SPEED_5G)
1575 speed |= TXGBE_LINK_SPEED_5GB_FULL;
1576 if (*link_speeds & ETH_LINK_SPEED_2_5G)
1577 speed |= TXGBE_LINK_SPEED_2_5GB_FULL;
1578 if (*link_speeds & ETH_LINK_SPEED_1G)
1579 speed |= TXGBE_LINK_SPEED_1GB_FULL;
1580 if (*link_speeds & ETH_LINK_SPEED_100M)
1581 speed |= TXGBE_LINK_SPEED_100M_FULL;
1584 err = hw->mac.setup_link(hw, speed, link_up);
1590 if (rte_intr_allow_others(intr_handle)) {
1591 /* check if lsc interrupt is enabled */
1592 if (dev->data->dev_conf.intr_conf.lsc != 0)
1593 txgbe_dev_lsc_interrupt_setup(dev, TRUE);
1595 txgbe_dev_lsc_interrupt_setup(dev, FALSE);
1596 txgbe_dev_macsec_interrupt_setup(dev);
1597 txgbe_set_ivar_map(hw, -1, 1, TXGBE_MISC_VEC_ID);
1599 rte_intr_callback_unregister(intr_handle,
1600 txgbe_dev_interrupt_handler, dev);
1601 if (dev->data->dev_conf.intr_conf.lsc != 0)
1602 PMD_INIT_LOG(INFO, "lsc won't enable because of"
1603 " no intr multiplex");
1606 /* check if rxq interrupt is enabled */
1607 if (dev->data->dev_conf.intr_conf.rxq != 0 &&
1608 rte_intr_dp_is_en(intr_handle))
1609 txgbe_dev_rxq_interrupt_setup(dev);
1611 /* enable uio/vfio intr/eventfd mapping */
1612 rte_intr_enable(intr_handle);
1614 /* resume enabled intr since hw reset */
1615 txgbe_enable_intr(dev);
1616 txgbe_filter_restore(dev);
1619 * Update link status right before return, because it may
1620 * start link configuration process in a separate thread.
1622 txgbe_dev_link_update(dev, 0);
1624 wr32m(hw, TXGBE_LEDCTL, 0xFFFFFFFF, TXGBE_LEDCTL_ORD_MASK);
1626 txgbe_read_stats_registers(hw, hw_stats);
1627 hw->offset_loaded = 1;
1632 PMD_INIT_LOG(ERR, "failure in dev start: %d", err);
1633 txgbe_dev_clear_queues(dev);
1638 * Stop device: disable rx and tx functions to allow for reconfiguring.
1641 txgbe_dev_stop(struct rte_eth_dev *dev)
1643 struct rte_eth_link link;
1644 struct txgbe_adapter *adapter = TXGBE_DEV_ADAPTER(dev);
1645 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
1646 struct txgbe_vf_info *vfinfo = *TXGBE_DEV_VFDATA(dev);
1647 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1648 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1651 if (hw->adapter_stopped)
1654 PMD_INIT_FUNC_TRACE();
1656 rte_eal_alarm_cancel(txgbe_dev_setup_link_alarm_handler, dev);
1658 /* disable interrupts */
1659 txgbe_disable_intr(hw);
1662 txgbe_pf_reset_hw(hw);
1663 hw->adapter_stopped = 0;
1668 for (vf = 0; vfinfo != NULL && vf < pci_dev->max_vfs; vf++)
1669 vfinfo[vf].clear_to_send = false;
1671 if (hw->phy.media_type == txgbe_media_type_copper) {
1672 /* Turn off the copper */
1673 hw->phy.set_phy_power(hw, false);
1675 /* Turn off the laser */
1676 hw->mac.disable_tx_laser(hw);
1679 txgbe_dev_clear_queues(dev);
1681 /* Clear stored conf */
1682 dev->data->scattered_rx = 0;
1685 /* Clear recorded link status */
1686 memset(&link, 0, sizeof(link));
1687 rte_eth_linkstatus_set(dev, &link);
1689 if (!rte_intr_allow_others(intr_handle))
1690 /* resume to the default handler */
1691 rte_intr_callback_register(intr_handle,
1692 txgbe_dev_interrupt_handler,
1695 /* Clean datapath event and queue/vec mapping */
1696 rte_intr_efd_disable(intr_handle);
1697 if (intr_handle->intr_vec != NULL) {
1698 rte_free(intr_handle->intr_vec);
1699 intr_handle->intr_vec = NULL;
1702 adapter->rss_reta_updated = 0;
1703 wr32m(hw, TXGBE_LEDCTL, 0xFFFFFFFF, TXGBE_LEDCTL_SEL_MASK);
1705 hw->adapter_stopped = true;
1706 dev->data->dev_started = 0;
1712 * Set device link up: enable tx.
1715 txgbe_dev_set_link_up(struct rte_eth_dev *dev)
1717 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
1719 if (hw->phy.media_type == txgbe_media_type_copper) {
1720 /* Turn on the copper */
1721 hw->phy.set_phy_power(hw, true);
1723 /* Turn on the laser */
1724 hw->mac.enable_tx_laser(hw);
1725 txgbe_dev_link_update(dev, 0);
1732 * Set device link down: disable tx.
1735 txgbe_dev_set_link_down(struct rte_eth_dev *dev)
1737 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
1739 if (hw->phy.media_type == txgbe_media_type_copper) {
1740 /* Turn off the copper */
1741 hw->phy.set_phy_power(hw, false);
1743 /* Turn off the laser */
1744 hw->mac.disable_tx_laser(hw);
1745 txgbe_dev_link_update(dev, 0);
1752 * Reset and stop device.
1755 txgbe_dev_close(struct rte_eth_dev *dev)
1757 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
1758 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1759 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1763 PMD_INIT_FUNC_TRACE();
1765 txgbe_pf_reset_hw(hw);
1767 ret = txgbe_dev_stop(dev);
1769 txgbe_dev_free_queues(dev);
1771 /* reprogram the RAR[0] in case user changed it. */
1772 txgbe_set_rar(hw, 0, hw->mac.addr, 0, true);
1774 /* Unlock any pending hardware semaphore */
1775 txgbe_swfw_lock_reset(hw);
1777 /* disable uio intr before callback unregister */
1778 rte_intr_disable(intr_handle);
1781 ret = rte_intr_callback_unregister(intr_handle,
1782 txgbe_dev_interrupt_handler, dev);
1783 if (ret >= 0 || ret == -ENOENT) {
1785 } else if (ret != -EAGAIN) {
1787 "intr callback unregister failed: %d",
1791 } while (retries++ < (10 + TXGBE_LINK_UP_TIME));
1793 /* cancel the delay handler before remove dev */
1794 rte_eal_alarm_cancel(txgbe_dev_interrupt_delayed_handler, dev);
1796 /* uninitialize PF if max_vfs not zero */
1797 txgbe_pf_host_uninit(dev);
1799 rte_free(dev->data->mac_addrs);
1800 dev->data->mac_addrs = NULL;
1802 rte_free(dev->data->hash_mac_addrs);
1803 dev->data->hash_mac_addrs = NULL;
1805 /* Remove all ntuple filters of the device */
1806 txgbe_ntuple_filter_uninit(dev);
1815 txgbe_dev_reset(struct rte_eth_dev *dev)
1819 /* When a DPDK PMD PF begin to reset PF port, it should notify all
1820 * its VF to make them align with it. The detailed notification
1821 * mechanism is PMD specific. As to txgbe PF, it is rather complex.
1822 * To avoid unexpected behavior in VF, currently reset of PF with
1823 * SR-IOV activation is not supported. It might be supported later.
1825 if (dev->data->sriov.active)
1828 ret = eth_txgbe_dev_uninit(dev);
1832 ret = eth_txgbe_dev_init(dev, NULL);
1837 #define UPDATE_QP_COUNTER_32bit(reg, last_counter, counter) \
1839 uint32_t current_counter = rd32(hw, reg); \
1840 if (current_counter < last_counter) \
1841 current_counter += 0x100000000LL; \
1842 if (!hw->offset_loaded) \
1843 last_counter = current_counter; \
1844 counter = current_counter - last_counter; \
1845 counter &= 0xFFFFFFFFLL; \
1848 #define UPDATE_QP_COUNTER_36bit(reg_lsb, reg_msb, last_counter, counter) \
1850 uint64_t current_counter_lsb = rd32(hw, reg_lsb); \
1851 uint64_t current_counter_msb = rd32(hw, reg_msb); \
1852 uint64_t current_counter = (current_counter_msb << 32) | \
1853 current_counter_lsb; \
1854 if (current_counter < last_counter) \
1855 current_counter += 0x1000000000LL; \
1856 if (!hw->offset_loaded) \
1857 last_counter = current_counter; \
1858 counter = current_counter - last_counter; \
1859 counter &= 0xFFFFFFFFFLL; \
1863 txgbe_read_stats_registers(struct txgbe_hw *hw,
1864 struct txgbe_hw_stats *hw_stats)
1869 for (i = 0; i < hw->nb_rx_queues; i++) {
1870 UPDATE_QP_COUNTER_32bit(TXGBE_QPRXPKT(i),
1871 hw->qp_last[i].rx_qp_packets,
1872 hw_stats->qp[i].rx_qp_packets);
1873 UPDATE_QP_COUNTER_36bit(TXGBE_QPRXOCTL(i), TXGBE_QPRXOCTH(i),
1874 hw->qp_last[i].rx_qp_bytes,
1875 hw_stats->qp[i].rx_qp_bytes);
1876 UPDATE_QP_COUNTER_32bit(TXGBE_QPRXMPKT(i),
1877 hw->qp_last[i].rx_qp_mc_packets,
1878 hw_stats->qp[i].rx_qp_mc_packets);
1881 for (i = 0; i < hw->nb_tx_queues; i++) {
1882 UPDATE_QP_COUNTER_32bit(TXGBE_QPTXPKT(i),
1883 hw->qp_last[i].tx_qp_packets,
1884 hw_stats->qp[i].tx_qp_packets);
1885 UPDATE_QP_COUNTER_36bit(TXGBE_QPTXOCTL(i), TXGBE_QPTXOCTH(i),
1886 hw->qp_last[i].tx_qp_bytes,
1887 hw_stats->qp[i].tx_qp_bytes);
1890 for (i = 0; i < TXGBE_MAX_UP; i++) {
1891 hw_stats->up[i].rx_up_xon_packets +=
1892 rd32(hw, TXGBE_PBRXUPXON(i));
1893 hw_stats->up[i].rx_up_xoff_packets +=
1894 rd32(hw, TXGBE_PBRXUPXOFF(i));
1895 hw_stats->up[i].tx_up_xon_packets +=
1896 rd32(hw, TXGBE_PBTXUPXON(i));
1897 hw_stats->up[i].tx_up_xoff_packets +=
1898 rd32(hw, TXGBE_PBTXUPXOFF(i));
1899 hw_stats->up[i].tx_up_xon2off_packets +=
1900 rd32(hw, TXGBE_PBTXUPOFF(i));
1901 hw_stats->up[i].rx_up_dropped +=
1902 rd32(hw, TXGBE_PBRXMISS(i));
1904 hw_stats->rx_xon_packets += rd32(hw, TXGBE_PBRXLNKXON);
1905 hw_stats->rx_xoff_packets += rd32(hw, TXGBE_PBRXLNKXOFF);
1906 hw_stats->tx_xon_packets += rd32(hw, TXGBE_PBTXLNKXON);
1907 hw_stats->tx_xoff_packets += rd32(hw, TXGBE_PBTXLNKXOFF);
1910 hw_stats->rx_packets += rd32(hw, TXGBE_DMARXPKT);
1911 hw_stats->tx_packets += rd32(hw, TXGBE_DMATXPKT);
1913 hw_stats->rx_bytes += rd64(hw, TXGBE_DMARXOCTL);
1914 hw_stats->tx_bytes += rd64(hw, TXGBE_DMATXOCTL);
1915 hw_stats->rx_drop_packets += rd32(hw, TXGBE_PBRXDROP);
1918 hw_stats->rx_crc_errors += rd64(hw, TXGBE_MACRXERRCRCL);
1919 hw_stats->rx_multicast_packets += rd64(hw, TXGBE_MACRXMPKTL);
1920 hw_stats->tx_multicast_packets += rd64(hw, TXGBE_MACTXMPKTL);
1922 hw_stats->rx_total_packets += rd64(hw, TXGBE_MACRXPKTL);
1923 hw_stats->tx_total_packets += rd64(hw, TXGBE_MACTXPKTL);
1924 hw_stats->rx_total_bytes += rd64(hw, TXGBE_MACRXGBOCTL);
1926 hw_stats->rx_broadcast_packets += rd64(hw, TXGBE_MACRXOCTL);
1927 hw_stats->tx_broadcast_packets += rd32(hw, TXGBE_MACTXOCTL);
1929 hw_stats->rx_size_64_packets += rd64(hw, TXGBE_MACRX1TO64L);
1930 hw_stats->rx_size_65_to_127_packets += rd64(hw, TXGBE_MACRX65TO127L);
1931 hw_stats->rx_size_128_to_255_packets += rd64(hw, TXGBE_MACRX128TO255L);
1932 hw_stats->rx_size_256_to_511_packets += rd64(hw, TXGBE_MACRX256TO511L);
1933 hw_stats->rx_size_512_to_1023_packets +=
1934 rd64(hw, TXGBE_MACRX512TO1023L);
1935 hw_stats->rx_size_1024_to_max_packets +=
1936 rd64(hw, TXGBE_MACRX1024TOMAXL);
1937 hw_stats->tx_size_64_packets += rd64(hw, TXGBE_MACTX1TO64L);
1938 hw_stats->tx_size_65_to_127_packets += rd64(hw, TXGBE_MACTX65TO127L);
1939 hw_stats->tx_size_128_to_255_packets += rd64(hw, TXGBE_MACTX128TO255L);
1940 hw_stats->tx_size_256_to_511_packets += rd64(hw, TXGBE_MACTX256TO511L);
1941 hw_stats->tx_size_512_to_1023_packets +=
1942 rd64(hw, TXGBE_MACTX512TO1023L);
1943 hw_stats->tx_size_1024_to_max_packets +=
1944 rd64(hw, TXGBE_MACTX1024TOMAXL);
1946 hw_stats->rx_undersize_errors += rd64(hw, TXGBE_MACRXERRLENL);
1947 hw_stats->rx_oversize_errors += rd32(hw, TXGBE_MACRXOVERSIZE);
1948 hw_stats->rx_jabber_errors += rd32(hw, TXGBE_MACRXJABBER);
1951 hw_stats->mng_bmc2host_packets = rd32(hw, TXGBE_MNGBMC2OS);
1952 hw_stats->mng_host2bmc_packets = rd32(hw, TXGBE_MNGOS2BMC);
1953 hw_stats->rx_management_packets = rd32(hw, TXGBE_DMARXMNG);
1954 hw_stats->tx_management_packets = rd32(hw, TXGBE_DMATXMNG);
1957 hw_stats->rx_fcoe_crc_errors += rd32(hw, TXGBE_FCOECRC);
1958 hw_stats->rx_fcoe_mbuf_allocation_errors += rd32(hw, TXGBE_FCOELAST);
1959 hw_stats->rx_fcoe_dropped += rd32(hw, TXGBE_FCOERPDC);
1960 hw_stats->rx_fcoe_packets += rd32(hw, TXGBE_FCOEPRC);
1961 hw_stats->tx_fcoe_packets += rd32(hw, TXGBE_FCOEPTC);
1962 hw_stats->rx_fcoe_bytes += rd32(hw, TXGBE_FCOEDWRC);
1963 hw_stats->tx_fcoe_bytes += rd32(hw, TXGBE_FCOEDWTC);
1965 /* Flow Director Stats */
1966 hw_stats->flow_director_matched_filters += rd32(hw, TXGBE_FDIRMATCH);
1967 hw_stats->flow_director_missed_filters += rd32(hw, TXGBE_FDIRMISS);
1968 hw_stats->flow_director_added_filters +=
1969 TXGBE_FDIRUSED_ADD(rd32(hw, TXGBE_FDIRUSED));
1970 hw_stats->flow_director_removed_filters +=
1971 TXGBE_FDIRUSED_REM(rd32(hw, TXGBE_FDIRUSED));
1972 hw_stats->flow_director_filter_add_errors +=
1973 TXGBE_FDIRFAIL_ADD(rd32(hw, TXGBE_FDIRFAIL));
1974 hw_stats->flow_director_filter_remove_errors +=
1975 TXGBE_FDIRFAIL_REM(rd32(hw, TXGBE_FDIRFAIL));
1978 hw_stats->tx_macsec_pkts_untagged += rd32(hw, TXGBE_LSECTX_UTPKT);
1979 hw_stats->tx_macsec_pkts_encrypted +=
1980 rd32(hw, TXGBE_LSECTX_ENCPKT);
1981 hw_stats->tx_macsec_pkts_protected +=
1982 rd32(hw, TXGBE_LSECTX_PROTPKT);
1983 hw_stats->tx_macsec_octets_encrypted +=
1984 rd32(hw, TXGBE_LSECTX_ENCOCT);
1985 hw_stats->tx_macsec_octets_protected +=
1986 rd32(hw, TXGBE_LSECTX_PROTOCT);
1987 hw_stats->rx_macsec_pkts_untagged += rd32(hw, TXGBE_LSECRX_UTPKT);
1988 hw_stats->rx_macsec_pkts_badtag += rd32(hw, TXGBE_LSECRX_BTPKT);
1989 hw_stats->rx_macsec_pkts_nosci += rd32(hw, TXGBE_LSECRX_NOSCIPKT);
1990 hw_stats->rx_macsec_pkts_unknownsci += rd32(hw, TXGBE_LSECRX_UNSCIPKT);
1991 hw_stats->rx_macsec_octets_decrypted += rd32(hw, TXGBE_LSECRX_DECOCT);
1992 hw_stats->rx_macsec_octets_validated += rd32(hw, TXGBE_LSECRX_VLDOCT);
1993 hw_stats->rx_macsec_sc_pkts_unchecked +=
1994 rd32(hw, TXGBE_LSECRX_UNCHKPKT);
1995 hw_stats->rx_macsec_sc_pkts_delayed += rd32(hw, TXGBE_LSECRX_DLYPKT);
1996 hw_stats->rx_macsec_sc_pkts_late += rd32(hw, TXGBE_LSECRX_LATEPKT);
1997 for (i = 0; i < 2; i++) {
1998 hw_stats->rx_macsec_sa_pkts_ok +=
1999 rd32(hw, TXGBE_LSECRX_OKPKT(i));
2000 hw_stats->rx_macsec_sa_pkts_invalid +=
2001 rd32(hw, TXGBE_LSECRX_INVPKT(i));
2002 hw_stats->rx_macsec_sa_pkts_notvalid +=
2003 rd32(hw, TXGBE_LSECRX_BADPKT(i));
2005 hw_stats->rx_macsec_sa_pkts_unusedsa +=
2006 rd32(hw, TXGBE_LSECRX_INVSAPKT);
2007 hw_stats->rx_macsec_sa_pkts_notusingsa +=
2008 rd32(hw, TXGBE_LSECRX_BADSAPKT);
2010 hw_stats->rx_total_missed_packets = 0;
2011 for (i = 0; i < TXGBE_MAX_UP; i++) {
2012 hw_stats->rx_total_missed_packets +=
2013 hw_stats->up[i].rx_up_dropped;
2018 txgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2020 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2021 struct txgbe_hw_stats *hw_stats = TXGBE_DEV_STATS(dev);
2022 struct txgbe_stat_mappings *stat_mappings =
2023 TXGBE_DEV_STAT_MAPPINGS(dev);
2026 txgbe_read_stats_registers(hw, hw_stats);
2031 /* Fill out the rte_eth_stats statistics structure */
2032 stats->ipackets = hw_stats->rx_packets;
2033 stats->ibytes = hw_stats->rx_bytes;
2034 stats->opackets = hw_stats->tx_packets;
2035 stats->obytes = hw_stats->tx_bytes;
2037 memset(&stats->q_ipackets, 0, sizeof(stats->q_ipackets));
2038 memset(&stats->q_opackets, 0, sizeof(stats->q_opackets));
2039 memset(&stats->q_ibytes, 0, sizeof(stats->q_ibytes));
2040 memset(&stats->q_obytes, 0, sizeof(stats->q_obytes));
2041 memset(&stats->q_errors, 0, sizeof(stats->q_errors));
2042 for (i = 0; i < TXGBE_MAX_QP; i++) {
2043 uint32_t n = i / NB_QMAP_FIELDS_PER_QSM_REG;
2044 uint32_t offset = (i % NB_QMAP_FIELDS_PER_QSM_REG) * 8;
2047 q_map = (stat_mappings->rqsm[n] >> offset)
2048 & QMAP_FIELD_RESERVED_BITS_MASK;
2049 j = (q_map < RTE_ETHDEV_QUEUE_STAT_CNTRS
2050 ? q_map : q_map % RTE_ETHDEV_QUEUE_STAT_CNTRS);
2051 stats->q_ipackets[j] += hw_stats->qp[i].rx_qp_packets;
2052 stats->q_ibytes[j] += hw_stats->qp[i].rx_qp_bytes;
2054 q_map = (stat_mappings->tqsm[n] >> offset)
2055 & QMAP_FIELD_RESERVED_BITS_MASK;
2056 j = (q_map < RTE_ETHDEV_QUEUE_STAT_CNTRS
2057 ? q_map : q_map % RTE_ETHDEV_QUEUE_STAT_CNTRS);
2058 stats->q_opackets[j] += hw_stats->qp[i].tx_qp_packets;
2059 stats->q_obytes[j] += hw_stats->qp[i].tx_qp_bytes;
2063 stats->imissed = hw_stats->rx_total_missed_packets;
2064 stats->ierrors = hw_stats->rx_crc_errors +
2065 hw_stats->rx_mac_short_packet_dropped +
2066 hw_stats->rx_length_errors +
2067 hw_stats->rx_undersize_errors +
2068 hw_stats->rx_oversize_errors +
2069 hw_stats->rx_drop_packets +
2070 hw_stats->rx_illegal_byte_errors +
2071 hw_stats->rx_error_bytes +
2072 hw_stats->rx_fragment_errors +
2073 hw_stats->rx_fcoe_crc_errors +
2074 hw_stats->rx_fcoe_mbuf_allocation_errors;
2082 txgbe_dev_stats_reset(struct rte_eth_dev *dev)
2084 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2085 struct txgbe_hw_stats *hw_stats = TXGBE_DEV_STATS(dev);
2087 /* HW registers are cleared on read */
2088 hw->offset_loaded = 0;
2089 txgbe_dev_stats_get(dev, NULL);
2090 hw->offset_loaded = 1;
2092 /* Reset software totals */
2093 memset(hw_stats, 0, sizeof(*hw_stats));
2098 /* This function calculates the number of xstats based on the current config */
2100 txgbe_xstats_calc_num(struct rte_eth_dev *dev)
2102 int nb_queues = max(dev->data->nb_rx_queues, dev->data->nb_tx_queues);
2103 return TXGBE_NB_HW_STATS +
2104 TXGBE_NB_UP_STATS * TXGBE_MAX_UP +
2105 TXGBE_NB_QP_STATS * nb_queues;
2109 txgbe_get_name_by_id(uint32_t id, char *name, uint32_t size)
2113 /* Extended stats from txgbe_hw_stats */
2114 if (id < TXGBE_NB_HW_STATS) {
2115 snprintf(name, size, "[hw]%s",
2116 rte_txgbe_stats_strings[id].name);
2119 id -= TXGBE_NB_HW_STATS;
2121 /* Priority Stats */
2122 if (id < TXGBE_NB_UP_STATS * TXGBE_MAX_UP) {
2123 nb = id / TXGBE_NB_UP_STATS;
2124 st = id % TXGBE_NB_UP_STATS;
2125 snprintf(name, size, "[p%u]%s", nb,
2126 rte_txgbe_up_strings[st].name);
2129 id -= TXGBE_NB_UP_STATS * TXGBE_MAX_UP;
2132 if (id < TXGBE_NB_QP_STATS * TXGBE_MAX_QP) {
2133 nb = id / TXGBE_NB_QP_STATS;
2134 st = id % TXGBE_NB_QP_STATS;
2135 snprintf(name, size, "[q%u]%s", nb,
2136 rte_txgbe_qp_strings[st].name);
2139 id -= TXGBE_NB_QP_STATS * TXGBE_MAX_QP;
2141 return -(int)(id + 1);
2145 txgbe_get_offset_by_id(uint32_t id, uint32_t *offset)
2149 /* Extended stats from txgbe_hw_stats */
2150 if (id < TXGBE_NB_HW_STATS) {
2151 *offset = rte_txgbe_stats_strings[id].offset;
2154 id -= TXGBE_NB_HW_STATS;
2156 /* Priority Stats */
2157 if (id < TXGBE_NB_UP_STATS * TXGBE_MAX_UP) {
2158 nb = id / TXGBE_NB_UP_STATS;
2159 st = id % TXGBE_NB_UP_STATS;
2160 *offset = rte_txgbe_up_strings[st].offset +
2161 nb * (TXGBE_NB_UP_STATS * sizeof(uint64_t));
2164 id -= TXGBE_NB_UP_STATS * TXGBE_MAX_UP;
2167 if (id < TXGBE_NB_QP_STATS * TXGBE_MAX_QP) {
2168 nb = id / TXGBE_NB_QP_STATS;
2169 st = id % TXGBE_NB_QP_STATS;
2170 *offset = rte_txgbe_qp_strings[st].offset +
2171 nb * (TXGBE_NB_QP_STATS * sizeof(uint64_t));
2178 static int txgbe_dev_xstats_get_names(struct rte_eth_dev *dev,
2179 struct rte_eth_xstat_name *xstats_names, unsigned int limit)
2181 unsigned int i, count;
2183 count = txgbe_xstats_calc_num(dev);
2184 if (xstats_names == NULL)
2187 /* Note: limit >= cnt_stats checked upstream
2188 * in rte_eth_xstats_names()
2190 limit = min(limit, count);
2192 /* Extended stats from txgbe_hw_stats */
2193 for (i = 0; i < limit; i++) {
2194 if (txgbe_get_name_by_id(i, xstats_names[i].name,
2195 sizeof(xstats_names[i].name))) {
2196 PMD_INIT_LOG(WARNING, "id value %d isn't valid", i);
2204 static int txgbe_dev_xstats_get_names_by_id(struct rte_eth_dev *dev,
2205 struct rte_eth_xstat_name *xstats_names,
2206 const uint64_t *ids,
2212 return txgbe_dev_xstats_get_names(dev, xstats_names, limit);
2214 for (i = 0; i < limit; i++) {
2215 if (txgbe_get_name_by_id(ids[i], xstats_names[i].name,
2216 sizeof(xstats_names[i].name))) {
2217 PMD_INIT_LOG(WARNING, "id value %d isn't valid", i);
2226 txgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2229 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2230 struct txgbe_hw_stats *hw_stats = TXGBE_DEV_STATS(dev);
2231 unsigned int i, count;
2233 txgbe_read_stats_registers(hw, hw_stats);
2235 /* If this is a reset xstats is NULL, and we have cleared the
2236 * registers by reading them.
2238 count = txgbe_xstats_calc_num(dev);
2242 limit = min(limit, txgbe_xstats_calc_num(dev));
2244 /* Extended stats from txgbe_hw_stats */
2245 for (i = 0; i < limit; i++) {
2246 uint32_t offset = 0;
2248 if (txgbe_get_offset_by_id(i, &offset)) {
2249 PMD_INIT_LOG(WARNING, "id value %d isn't valid", i);
2252 xstats[i].value = *(uint64_t *)(((char *)hw_stats) + offset);
2260 txgbe_dev_xstats_get_(struct rte_eth_dev *dev, uint64_t *values,
2263 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2264 struct txgbe_hw_stats *hw_stats = TXGBE_DEV_STATS(dev);
2265 unsigned int i, count;
2267 txgbe_read_stats_registers(hw, hw_stats);
2269 /* If this is a reset xstats is NULL, and we have cleared the
2270 * registers by reading them.
2272 count = txgbe_xstats_calc_num(dev);
2276 limit = min(limit, txgbe_xstats_calc_num(dev));
2278 /* Extended stats from txgbe_hw_stats */
2279 for (i = 0; i < limit; i++) {
2282 if (txgbe_get_offset_by_id(i, &offset)) {
2283 PMD_INIT_LOG(WARNING, "id value %d isn't valid", i);
2286 values[i] = *(uint64_t *)(((char *)hw_stats) + offset);
2293 txgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
2294 uint64_t *values, unsigned int limit)
2296 struct txgbe_hw_stats *hw_stats = TXGBE_DEV_STATS(dev);
2300 return txgbe_dev_xstats_get_(dev, values, limit);
2302 for (i = 0; i < limit; i++) {
2305 if (txgbe_get_offset_by_id(ids[i], &offset)) {
2306 PMD_INIT_LOG(WARNING, "id value %d isn't valid", i);
2309 values[i] = *(uint64_t *)(((char *)hw_stats) + offset);
2316 txgbe_dev_xstats_reset(struct rte_eth_dev *dev)
2318 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2319 struct txgbe_hw_stats *hw_stats = TXGBE_DEV_STATS(dev);
2321 /* HW registers are cleared on read */
2322 hw->offset_loaded = 0;
2323 txgbe_read_stats_registers(hw, hw_stats);
2324 hw->offset_loaded = 1;
2326 /* Reset software totals */
2327 memset(hw_stats, 0, sizeof(*hw_stats));
2333 txgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
2335 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2336 u16 eeprom_verh, eeprom_verl;
2340 hw->rom.readw_sw(hw, TXGBE_EEPROM_VERSION_H, &eeprom_verh);
2341 hw->rom.readw_sw(hw, TXGBE_EEPROM_VERSION_L, &eeprom_verl);
2343 etrack_id = (eeprom_verh << 16) | eeprom_verl;
2344 ret = snprintf(fw_version, fw_size, "0x%08x", etrack_id);
2346 ret += 1; /* add the size of '\0' */
2347 if (fw_size < (u32)ret)
2354 txgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2356 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2357 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2359 dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
2360 dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
2361 dev_info->min_rx_bufsize = 1024;
2362 dev_info->max_rx_pktlen = 15872;
2363 dev_info->max_mac_addrs = hw->mac.num_rar_entries;
2364 dev_info->max_hash_mac_addrs = TXGBE_VMDQ_NUM_UC_MAC;
2365 dev_info->max_vfs = pci_dev->max_vfs;
2366 dev_info->max_vmdq_pools = ETH_64_POOLS;
2367 dev_info->vmdq_queue_num = dev_info->max_rx_queues;
2368 dev_info->rx_queue_offload_capa = txgbe_get_rx_queue_offloads(dev);
2369 dev_info->rx_offload_capa = (txgbe_get_rx_port_offloads(dev) |
2370 dev_info->rx_queue_offload_capa);
2371 dev_info->tx_queue_offload_capa = txgbe_get_tx_queue_offloads(dev);
2372 dev_info->tx_offload_capa = txgbe_get_tx_port_offloads(dev);
2374 dev_info->default_rxconf = (struct rte_eth_rxconf) {
2376 .pthresh = TXGBE_DEFAULT_RX_PTHRESH,
2377 .hthresh = TXGBE_DEFAULT_RX_HTHRESH,
2378 .wthresh = TXGBE_DEFAULT_RX_WTHRESH,
2380 .rx_free_thresh = TXGBE_DEFAULT_RX_FREE_THRESH,
2385 dev_info->default_txconf = (struct rte_eth_txconf) {
2387 .pthresh = TXGBE_DEFAULT_TX_PTHRESH,
2388 .hthresh = TXGBE_DEFAULT_TX_HTHRESH,
2389 .wthresh = TXGBE_DEFAULT_TX_WTHRESH,
2391 .tx_free_thresh = TXGBE_DEFAULT_TX_FREE_THRESH,
2395 dev_info->rx_desc_lim = rx_desc_lim;
2396 dev_info->tx_desc_lim = tx_desc_lim;
2398 dev_info->hash_key_size = TXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
2399 dev_info->reta_size = ETH_RSS_RETA_SIZE_128;
2400 dev_info->flow_type_rss_offloads = TXGBE_RSS_OFFLOAD_ALL;
2402 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
2403 dev_info->speed_capa |= ETH_LINK_SPEED_100M;
2405 /* Driver-preferred Rx/Tx parameters */
2406 dev_info->default_rxportconf.burst_size = 32;
2407 dev_info->default_txportconf.burst_size = 32;
2408 dev_info->default_rxportconf.nb_queues = 1;
2409 dev_info->default_txportconf.nb_queues = 1;
2410 dev_info->default_rxportconf.ring_size = 256;
2411 dev_info->default_txportconf.ring_size = 256;
2417 txgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev)
2419 if (dev->rx_pkt_burst == txgbe_recv_pkts ||
2420 dev->rx_pkt_burst == txgbe_recv_pkts_lro_single_alloc ||
2421 dev->rx_pkt_burst == txgbe_recv_pkts_lro_bulk_alloc ||
2422 dev->rx_pkt_burst == txgbe_recv_pkts_bulk_alloc)
2423 return txgbe_get_supported_ptypes();
2429 txgbe_dev_setup_link_alarm_handler(void *param)
2431 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2432 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2433 struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);
2435 bool autoneg = false;
2437 speed = hw->phy.autoneg_advertised;
2439 hw->mac.get_link_capabilities(hw, &speed, &autoneg);
2441 hw->mac.setup_link(hw, speed, true);
2443 intr->flags &= ~TXGBE_FLAG_NEED_LINK_CONFIG;
2446 /* return 0 means link status changed, -1 means not changed */
2448 txgbe_dev_link_update_share(struct rte_eth_dev *dev,
2449 int wait_to_complete)
2451 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2452 struct rte_eth_link link;
2453 u32 link_speed = TXGBE_LINK_SPEED_UNKNOWN;
2454 struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);
2459 memset(&link, 0, sizeof(link));
2460 link.link_status = ETH_LINK_DOWN;
2461 link.link_speed = ETH_SPEED_NUM_NONE;
2462 link.link_duplex = ETH_LINK_HALF_DUPLEX;
2463 link.link_autoneg = ETH_LINK_AUTONEG;
2465 hw->mac.get_link_status = true;
2467 if (intr->flags & TXGBE_FLAG_NEED_LINK_CONFIG)
2468 return rte_eth_linkstatus_set(dev, &link);
2470 /* check if it needs to wait to complete, if lsc interrupt is enabled */
2471 if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
2474 err = hw->mac.check_link(hw, &link_speed, &link_up, wait);
2477 link.link_speed = ETH_SPEED_NUM_100M;
2478 link.link_duplex = ETH_LINK_FULL_DUPLEX;
2479 return rte_eth_linkstatus_set(dev, &link);
2483 if (hw->phy.media_type == txgbe_media_type_fiber) {
2484 intr->flags |= TXGBE_FLAG_NEED_LINK_CONFIG;
2485 rte_eal_alarm_set(10,
2486 txgbe_dev_setup_link_alarm_handler, dev);
2488 return rte_eth_linkstatus_set(dev, &link);
2491 intr->flags &= ~TXGBE_FLAG_NEED_LINK_CONFIG;
2492 link.link_status = ETH_LINK_UP;
2493 link.link_duplex = ETH_LINK_FULL_DUPLEX;
2495 switch (link_speed) {
2497 case TXGBE_LINK_SPEED_UNKNOWN:
2498 link.link_duplex = ETH_LINK_FULL_DUPLEX;
2499 link.link_speed = ETH_SPEED_NUM_100M;
2502 case TXGBE_LINK_SPEED_100M_FULL:
2503 link.link_speed = ETH_SPEED_NUM_100M;
2506 case TXGBE_LINK_SPEED_1GB_FULL:
2507 link.link_speed = ETH_SPEED_NUM_1G;
2510 case TXGBE_LINK_SPEED_2_5GB_FULL:
2511 link.link_speed = ETH_SPEED_NUM_2_5G;
2514 case TXGBE_LINK_SPEED_5GB_FULL:
2515 link.link_speed = ETH_SPEED_NUM_5G;
2518 case TXGBE_LINK_SPEED_10GB_FULL:
2519 link.link_speed = ETH_SPEED_NUM_10G;
2523 return rte_eth_linkstatus_set(dev, &link);
2527 txgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
2529 return txgbe_dev_link_update_share(dev, wait_to_complete);
2533 txgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
2535 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2538 fctrl = rd32(hw, TXGBE_PSRCTL);
2539 fctrl |= (TXGBE_PSRCTL_UCP | TXGBE_PSRCTL_MCP);
2540 wr32(hw, TXGBE_PSRCTL, fctrl);
2546 txgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
2548 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2551 fctrl = rd32(hw, TXGBE_PSRCTL);
2552 fctrl &= (~TXGBE_PSRCTL_UCP);
2553 if (dev->data->all_multicast == 1)
2554 fctrl |= TXGBE_PSRCTL_MCP;
2556 fctrl &= (~TXGBE_PSRCTL_MCP);
2557 wr32(hw, TXGBE_PSRCTL, fctrl);
2563 txgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
2565 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2568 fctrl = rd32(hw, TXGBE_PSRCTL);
2569 fctrl |= TXGBE_PSRCTL_MCP;
2570 wr32(hw, TXGBE_PSRCTL, fctrl);
2576 txgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
2578 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2581 if (dev->data->promiscuous == 1)
2582 return 0; /* must remain in all_multicast mode */
2584 fctrl = rd32(hw, TXGBE_PSRCTL);
2585 fctrl &= (~TXGBE_PSRCTL_MCP);
2586 wr32(hw, TXGBE_PSRCTL, fctrl);
2592 * It clears the interrupt causes and enables the interrupt.
2593 * It will be called once only during nic initialized.
2596 * Pointer to struct rte_eth_dev.
2598 * Enable or Disable.
2601 * - On success, zero.
2602 * - On failure, a negative value.
2605 txgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on)
2607 struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);
2609 txgbe_dev_link_status_print(dev);
2611 intr->mask_misc |= TXGBE_ICRMISC_LSC;
2613 intr->mask_misc &= ~TXGBE_ICRMISC_LSC;
2619 * It clears the interrupt causes and enables the interrupt.
2620 * It will be called once only during nic initialized.
2623 * Pointer to struct rte_eth_dev.
2626 * - On success, zero.
2627 * - On failure, a negative value.
2630 txgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
2632 struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);
2634 intr->mask[0] |= TXGBE_ICR_MASK;
2635 intr->mask[1] |= TXGBE_ICR_MASK;
2641 * It clears the interrupt causes and enables the interrupt.
2642 * It will be called once only during nic initialized.
2645 * Pointer to struct rte_eth_dev.
2648 * - On success, zero.
2649 * - On failure, a negative value.
2652 txgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev)
2654 struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);
2656 intr->mask_misc |= TXGBE_ICRMISC_LNKSEC;
2662 * It reads ICR and sets flag (TXGBE_ICRMISC_LSC) for the link_update.
2665 * Pointer to struct rte_eth_dev.
2668 * - On success, zero.
2669 * - On failure, a negative value.
2672 txgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
2675 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2676 struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);
2678 /* clear all cause mask */
2679 txgbe_disable_intr(hw);
2681 /* read-on-clear nic registers here */
2682 eicr = ((u32 *)hw->isb_mem)[TXGBE_ISB_MISC];
2683 PMD_DRV_LOG(DEBUG, "eicr %x", eicr);
2687 /* set flag for async link update */
2688 if (eicr & TXGBE_ICRMISC_LSC)
2689 intr->flags |= TXGBE_FLAG_NEED_LINK_UPDATE;
2691 if (eicr & TXGBE_ICRMISC_VFMBX)
2692 intr->flags |= TXGBE_FLAG_MAILBOX;
2694 if (eicr & TXGBE_ICRMISC_LNKSEC)
2695 intr->flags |= TXGBE_FLAG_MACSEC;
2697 if (eicr & TXGBE_ICRMISC_GPIO)
2698 intr->flags |= TXGBE_FLAG_PHY_INTERRUPT;
2704 * It gets and then prints the link status.
2707 * Pointer to struct rte_eth_dev.
2710 * - On success, zero.
2711 * - On failure, a negative value.
2714 txgbe_dev_link_status_print(struct rte_eth_dev *dev)
2716 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2717 struct rte_eth_link link;
2719 rte_eth_linkstatus_get(dev, &link);
2721 if (link.link_status) {
2722 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
2723 (int)(dev->data->port_id),
2724 (unsigned int)link.link_speed,
2725 link.link_duplex == ETH_LINK_FULL_DUPLEX ?
2726 "full-duplex" : "half-duplex");
2728 PMD_INIT_LOG(INFO, " Port %d: Link Down",
2729 (int)(dev->data->port_id));
2731 PMD_INIT_LOG(DEBUG, "PCI Address: " PCI_PRI_FMT,
2732 pci_dev->addr.domain,
2734 pci_dev->addr.devid,
2735 pci_dev->addr.function);
2739 * It executes link_update after knowing an interrupt occurred.
2742 * Pointer to struct rte_eth_dev.
2745 * - On success, zero.
2746 * - On failure, a negative value.
2749 txgbe_dev_interrupt_action(struct rte_eth_dev *dev,
2750 struct rte_intr_handle *intr_handle)
2752 struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);
2754 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2756 PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
2758 if (intr->flags & TXGBE_FLAG_MAILBOX) {
2759 txgbe_pf_mbx_process(dev);
2760 intr->flags &= ~TXGBE_FLAG_MAILBOX;
2763 if (intr->flags & TXGBE_FLAG_PHY_INTERRUPT) {
2764 hw->phy.handle_lasi(hw);
2765 intr->flags &= ~TXGBE_FLAG_PHY_INTERRUPT;
2768 if (intr->flags & TXGBE_FLAG_NEED_LINK_UPDATE) {
2769 struct rte_eth_link link;
2771 /*get the link status before link update, for predicting later*/
2772 rte_eth_linkstatus_get(dev, &link);
2774 txgbe_dev_link_update(dev, 0);
2777 if (!link.link_status)
2778 /* handle it 1 sec later, wait it being stable */
2779 timeout = TXGBE_LINK_UP_CHECK_TIMEOUT;
2780 /* likely to down */
2782 /* handle it 4 sec later, wait it being stable */
2783 timeout = TXGBE_LINK_DOWN_CHECK_TIMEOUT;
2785 txgbe_dev_link_status_print(dev);
2786 if (rte_eal_alarm_set(timeout * 1000,
2787 txgbe_dev_interrupt_delayed_handler,
2789 PMD_DRV_LOG(ERR, "Error setting alarm");
2791 /* remember original mask */
2792 intr->mask_misc_orig = intr->mask_misc;
2793 /* only disable lsc interrupt */
2794 intr->mask_misc &= ~TXGBE_ICRMISC_LSC;
2798 PMD_DRV_LOG(DEBUG, "enable intr immediately");
2799 txgbe_enable_intr(dev);
2800 rte_intr_enable(intr_handle);
2806 * Interrupt handler which shall be registered for alarm callback for delayed
2807 * handling specific interrupt to wait for the stable nic state. As the
2808 * NIC interrupt state is not stable for txgbe after link is just down,
2809 * it needs to wait 4 seconds to get the stable status.
2812 * Pointer to interrupt handle.
2814 * The address of parameter (struct rte_eth_dev *) registered before.
2820 txgbe_dev_interrupt_delayed_handler(void *param)
2822 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2823 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2824 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2825 struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);
2826 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2829 txgbe_disable_intr(hw);
2831 eicr = ((u32 *)hw->isb_mem)[TXGBE_ISB_MISC];
2832 if (eicr & TXGBE_ICRMISC_VFMBX)
2833 txgbe_pf_mbx_process(dev);
2835 if (intr->flags & TXGBE_FLAG_PHY_INTERRUPT) {
2836 hw->phy.handle_lasi(hw);
2837 intr->flags &= ~TXGBE_FLAG_PHY_INTERRUPT;
2840 if (intr->flags & TXGBE_FLAG_NEED_LINK_UPDATE) {
2841 txgbe_dev_link_update(dev, 0);
2842 intr->flags &= ~TXGBE_FLAG_NEED_LINK_UPDATE;
2843 txgbe_dev_link_status_print(dev);
2844 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC,
2848 if (intr->flags & TXGBE_FLAG_MACSEC) {
2849 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_MACSEC,
2851 intr->flags &= ~TXGBE_FLAG_MACSEC;
2854 /* restore original mask */
2855 intr->mask_misc = intr->mask_misc_orig;
2856 intr->mask_misc_orig = 0;
2858 PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
2859 txgbe_enable_intr(dev);
2860 rte_intr_enable(intr_handle);
2864 * Interrupt handler triggered by NIC for handling
2865 * specific interrupt.
2868 * Pointer to interrupt handle.
2870 * The address of parameter (struct rte_eth_dev *) registered before.
2876 txgbe_dev_interrupt_handler(void *param)
2878 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2880 txgbe_dev_interrupt_get_status(dev);
2881 txgbe_dev_interrupt_action(dev, dev->intr_handle);
2885 txgbe_dev_led_on(struct rte_eth_dev *dev)
2887 struct txgbe_hw *hw;
2889 hw = TXGBE_DEV_HW(dev);
2890 return txgbe_led_on(hw, 4) == 0 ? 0 : -ENOTSUP;
2894 txgbe_dev_led_off(struct rte_eth_dev *dev)
2896 struct txgbe_hw *hw;
2898 hw = TXGBE_DEV_HW(dev);
2899 return txgbe_led_off(hw, 4) == 0 ? 0 : -ENOTSUP;
2903 txgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2905 struct txgbe_hw *hw;
2911 hw = TXGBE_DEV_HW(dev);
2913 fc_conf->pause_time = hw->fc.pause_time;
2914 fc_conf->high_water = hw->fc.high_water[0];
2915 fc_conf->low_water = hw->fc.low_water[0];
2916 fc_conf->send_xon = hw->fc.send_xon;
2917 fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
2920 * Return rx_pause status according to actual setting of
2923 mflcn_reg = rd32(hw, TXGBE_RXFCCFG);
2924 if (mflcn_reg & (TXGBE_RXFCCFG_FC | TXGBE_RXFCCFG_PFC))
2930 * Return tx_pause status according to actual setting of
2933 fccfg_reg = rd32(hw, TXGBE_TXFCCFG);
2934 if (fccfg_reg & (TXGBE_TXFCCFG_FC | TXGBE_TXFCCFG_PFC))
2939 if (rx_pause && tx_pause)
2940 fc_conf->mode = RTE_FC_FULL;
2942 fc_conf->mode = RTE_FC_RX_PAUSE;
2944 fc_conf->mode = RTE_FC_TX_PAUSE;
2946 fc_conf->mode = RTE_FC_NONE;
2952 txgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2954 struct txgbe_hw *hw;
2956 uint32_t rx_buf_size;
2957 uint32_t max_high_water;
2958 enum txgbe_fc_mode rte_fcmode_2_txgbe_fcmode[] = {
2965 PMD_INIT_FUNC_TRACE();
2967 hw = TXGBE_DEV_HW(dev);
2968 rx_buf_size = rd32(hw, TXGBE_PBRXSIZE(0));
2969 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
2972 * At least reserve one Ethernet frame for watermark
2973 * high_water/low_water in kilo bytes for txgbe
2975 max_high_water = (rx_buf_size - RTE_ETHER_MAX_LEN) >> 10;
2976 if (fc_conf->high_water > max_high_water ||
2977 fc_conf->high_water < fc_conf->low_water) {
2978 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
2979 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
2983 hw->fc.requested_mode = rte_fcmode_2_txgbe_fcmode[fc_conf->mode];
2984 hw->fc.pause_time = fc_conf->pause_time;
2985 hw->fc.high_water[0] = fc_conf->high_water;
2986 hw->fc.low_water[0] = fc_conf->low_water;
2987 hw->fc.send_xon = fc_conf->send_xon;
2988 hw->fc.disable_fc_autoneg = !fc_conf->autoneg;
2990 err = txgbe_fc_enable(hw);
2992 /* Not negotiated is not an error case */
2993 if (err == 0 || err == TXGBE_ERR_FC_NOT_NEGOTIATED) {
2994 wr32m(hw, TXGBE_MACRXFLT, TXGBE_MACRXFLT_CTL_MASK,
2995 (fc_conf->mac_ctrl_frame_fwd
2996 ? TXGBE_MACRXFLT_CTL_NOPS : TXGBE_MACRXFLT_CTL_DROP));
3002 PMD_INIT_LOG(ERR, "txgbe_fc_enable = 0x%x", err);
3007 txgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
3008 struct rte_eth_pfc_conf *pfc_conf)
3011 uint32_t rx_buf_size;
3012 uint32_t max_high_water;
3014 uint8_t map[TXGBE_DCB_UP_MAX] = { 0 };
3015 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3016 struct txgbe_dcb_config *dcb_config = TXGBE_DEV_DCB_CONFIG(dev);
3018 enum txgbe_fc_mode rte_fcmode_2_txgbe_fcmode[] = {
3025 PMD_INIT_FUNC_TRACE();
3027 txgbe_dcb_unpack_map_cee(dcb_config, TXGBE_DCB_RX_CONFIG, map);
3028 tc_num = map[pfc_conf->priority];
3029 rx_buf_size = rd32(hw, TXGBE_PBRXSIZE(tc_num));
3030 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
3032 * At least reserve one Ethernet frame for watermark
3033 * high_water/low_water in kilo bytes for txgbe
3035 max_high_water = (rx_buf_size - RTE_ETHER_MAX_LEN) >> 10;
3036 if (pfc_conf->fc.high_water > max_high_water ||
3037 pfc_conf->fc.high_water <= pfc_conf->fc.low_water) {
3038 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
3039 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
3043 hw->fc.requested_mode = rte_fcmode_2_txgbe_fcmode[pfc_conf->fc.mode];
3044 hw->fc.pause_time = pfc_conf->fc.pause_time;
3045 hw->fc.send_xon = pfc_conf->fc.send_xon;
3046 hw->fc.low_water[tc_num] = pfc_conf->fc.low_water;
3047 hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
3049 err = txgbe_dcb_pfc_enable(hw, tc_num);
3051 /* Not negotiated is not an error case */
3052 if (err == 0 || err == TXGBE_ERR_FC_NOT_NEGOTIATED)
3055 PMD_INIT_LOG(ERR, "txgbe_dcb_pfc_enable = 0x%x", err);
3060 txgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
3061 struct rte_eth_rss_reta_entry64 *reta_conf,
3066 uint16_t idx, shift;
3067 struct txgbe_adapter *adapter = TXGBE_DEV_ADAPTER(dev);
3068 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3070 PMD_INIT_FUNC_TRACE();
3072 if (!txgbe_rss_update_sp(hw->mac.type)) {
3073 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this "
3078 if (reta_size != ETH_RSS_RETA_SIZE_128) {
3079 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3080 "(%d) doesn't match the number hardware can supported "
3081 "(%d)", reta_size, ETH_RSS_RETA_SIZE_128);
3085 for (i = 0; i < reta_size; i += 4) {
3086 idx = i / RTE_RETA_GROUP_SIZE;
3087 shift = i % RTE_RETA_GROUP_SIZE;
3088 mask = (uint8_t)RS64(reta_conf[idx].mask, shift, 0xF);
3092 reta = rd32a(hw, TXGBE_REG_RSSTBL, i >> 2);
3093 for (j = 0; j < 4; j++) {
3094 if (RS8(mask, j, 0x1)) {
3095 reta &= ~(MS32(8 * j, 0xFF));
3096 reta |= LS32(reta_conf[idx].reta[shift + j],
3100 wr32a(hw, TXGBE_REG_RSSTBL, i >> 2, reta);
3102 adapter->rss_reta_updated = 1;
3108 txgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
3109 struct rte_eth_rss_reta_entry64 *reta_conf,
3112 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3115 uint16_t idx, shift;
3117 PMD_INIT_FUNC_TRACE();
3119 if (reta_size != ETH_RSS_RETA_SIZE_128) {
3120 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3121 "(%d) doesn't match the number hardware can supported "
3122 "(%d)", reta_size, ETH_RSS_RETA_SIZE_128);
3126 for (i = 0; i < reta_size; i += 4) {
3127 idx = i / RTE_RETA_GROUP_SIZE;
3128 shift = i % RTE_RETA_GROUP_SIZE;
3129 mask = (uint8_t)RS64(reta_conf[idx].mask, shift, 0xF);
3133 reta = rd32a(hw, TXGBE_REG_RSSTBL, i >> 2);
3134 for (j = 0; j < 4; j++) {
3135 if (RS8(mask, j, 0x1))
3136 reta_conf[idx].reta[shift + j] =
3137 (uint16_t)RS32(reta, 8 * j, 0xFF);
3145 txgbe_add_rar(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
3146 uint32_t index, uint32_t pool)
3148 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3149 uint32_t enable_addr = 1;
3151 return txgbe_set_rar(hw, index, mac_addr->addr_bytes,
3156 txgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
3158 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3160 txgbe_clear_rar(hw, index);
3164 txgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *addr)
3166 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3168 txgbe_remove_rar(dev, 0);
3169 txgbe_add_rar(dev, addr, 0, pci_dev->max_vfs);
3175 txgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
3177 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3178 struct rte_eth_dev_info dev_info;
3179 uint32_t frame_size = mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN;
3180 struct rte_eth_dev_data *dev_data = dev->data;
3183 ret = txgbe_dev_info_get(dev, &dev_info);
3187 /* check that mtu is within the allowed range */
3188 if (mtu < RTE_ETHER_MIN_MTU || frame_size > dev_info.max_rx_pktlen)
3191 /* If device is started, refuse mtu that requires the support of
3192 * scattered packets when this feature has not been enabled before.
3194 if (dev_data->dev_started && !dev_data->scattered_rx &&
3195 (frame_size + 2 * TXGBE_VLAN_TAG_SIZE >
3196 dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
3197 PMD_INIT_LOG(ERR, "Stop port first.");
3201 /* update max frame size */
3202 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
3205 wr32m(hw, TXGBE_FRMSZ, TXGBE_FRMSZ_MAX_MASK,
3206 TXGBE_FRAME_SIZE_MAX);
3208 wr32m(hw, TXGBE_FRMSZ, TXGBE_FRMSZ_MAX_MASK,
3209 TXGBE_FRMSZ_MAX(frame_size));
3215 txgbe_uta_vector(struct txgbe_hw *hw, struct rte_ether_addr *uc_addr)
3217 uint32_t vector = 0;
3219 switch (hw->mac.mc_filter_type) {
3220 case 0: /* use bits [47:36] of the address */
3221 vector = ((uc_addr->addr_bytes[4] >> 4) |
3222 (((uint16_t)uc_addr->addr_bytes[5]) << 4));
3224 case 1: /* use bits [46:35] of the address */
3225 vector = ((uc_addr->addr_bytes[4] >> 3) |
3226 (((uint16_t)uc_addr->addr_bytes[5]) << 5));
3228 case 2: /* use bits [45:34] of the address */
3229 vector = ((uc_addr->addr_bytes[4] >> 2) |
3230 (((uint16_t)uc_addr->addr_bytes[5]) << 6));
3232 case 3: /* use bits [43:32] of the address */
3233 vector = ((uc_addr->addr_bytes[4]) |
3234 (((uint16_t)uc_addr->addr_bytes[5]) << 8));
3236 default: /* Invalid mc_filter_type */
3240 /* vector can only be 12-bits or boundary will be exceeded */
3246 txgbe_uc_hash_table_set(struct rte_eth_dev *dev,
3247 struct rte_ether_addr *mac_addr, uint8_t on)
3255 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3256 struct txgbe_uta_info *uta_info = TXGBE_DEV_UTA_INFO(dev);
3258 /* The UTA table only exists on pf hardware */
3259 if (hw->mac.type < txgbe_mac_raptor)
3262 vector = txgbe_uta_vector(hw, mac_addr);
3263 uta_idx = (vector >> 5) & 0x7F;
3264 uta_mask = 0x1UL << (vector & 0x1F);
3266 if (!!on == !!(uta_info->uta_shadow[uta_idx] & uta_mask))
3269 reg_val = rd32(hw, TXGBE_UCADDRTBL(uta_idx));
3271 uta_info->uta_in_use++;
3272 reg_val |= uta_mask;
3273 uta_info->uta_shadow[uta_idx] |= uta_mask;
3275 uta_info->uta_in_use--;
3276 reg_val &= ~uta_mask;
3277 uta_info->uta_shadow[uta_idx] &= ~uta_mask;
3280 wr32(hw, TXGBE_UCADDRTBL(uta_idx), reg_val);
3282 psrctl = rd32(hw, TXGBE_PSRCTL);
3283 if (uta_info->uta_in_use > 0)
3284 psrctl |= TXGBE_PSRCTL_UCHFENA;
3286 psrctl &= ~TXGBE_PSRCTL_UCHFENA;
3288 psrctl &= ~TXGBE_PSRCTL_ADHF12_MASK;
3289 psrctl |= TXGBE_PSRCTL_ADHF12(hw->mac.mc_filter_type);
3290 wr32(hw, TXGBE_PSRCTL, psrctl);
3296 txgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
3298 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3299 struct txgbe_uta_info *uta_info = TXGBE_DEV_UTA_INFO(dev);
3303 /* The UTA table only exists on pf hardware */
3304 if (hw->mac.type < txgbe_mac_raptor)
3308 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
3309 uta_info->uta_shadow[i] = ~0;
3310 wr32(hw, TXGBE_UCADDRTBL(i), ~0);
3313 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
3314 uta_info->uta_shadow[i] = 0;
3315 wr32(hw, TXGBE_UCADDRTBL(i), 0);
3319 psrctl = rd32(hw, TXGBE_PSRCTL);
3321 psrctl |= TXGBE_PSRCTL_UCHFENA;
3323 psrctl &= ~TXGBE_PSRCTL_UCHFENA;
3325 psrctl &= ~TXGBE_PSRCTL_ADHF12_MASK;
3326 psrctl |= TXGBE_PSRCTL_ADHF12(hw->mac.mc_filter_type);
3327 wr32(hw, TXGBE_PSRCTL, psrctl);
3333 txgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
3335 uint32_t new_val = orig_val;
3337 if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
3338 new_val |= TXGBE_POOLETHCTL_UTA;
3339 if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
3340 new_val |= TXGBE_POOLETHCTL_MCHA;
3341 if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
3342 new_val |= TXGBE_POOLETHCTL_UCHA;
3343 if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
3344 new_val |= TXGBE_POOLETHCTL_BCA;
3345 if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
3346 new_val |= TXGBE_POOLETHCTL_MCP;
3352 txgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
3354 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3355 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3357 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3359 if (queue_id < 32) {
3360 mask = rd32(hw, TXGBE_IMS(0));
3361 mask &= (1 << queue_id);
3362 wr32(hw, TXGBE_IMS(0), mask);
3363 } else if (queue_id < 64) {
3364 mask = rd32(hw, TXGBE_IMS(1));
3365 mask &= (1 << (queue_id - 32));
3366 wr32(hw, TXGBE_IMS(1), mask);
3368 rte_intr_enable(intr_handle);
3374 txgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
3377 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3379 if (queue_id < 32) {
3380 mask = rd32(hw, TXGBE_IMS(0));
3381 mask &= ~(1 << queue_id);
3382 wr32(hw, TXGBE_IMS(0), mask);
3383 } else if (queue_id < 64) {
3384 mask = rd32(hw, TXGBE_IMS(1));
3385 mask &= ~(1 << (queue_id - 32));
3386 wr32(hw, TXGBE_IMS(1), mask);
3393 * set the IVAR registers, mapping interrupt causes to vectors
3395 * pointer to txgbe_hw struct
3397 * 0 for Rx, 1 for Tx, -1 for other causes
3399 * queue to map the corresponding interrupt to
3401 * the vector to map to the corresponding queue
3404 txgbe_set_ivar_map(struct txgbe_hw *hw, int8_t direction,
3405 uint8_t queue, uint8_t msix_vector)
3409 if (direction == -1) {
3411 msix_vector |= TXGBE_IVARMISC_VLD;
3413 tmp = rd32(hw, TXGBE_IVARMISC);
3414 tmp &= ~(0xFF << idx);
3415 tmp |= (msix_vector << idx);
3416 wr32(hw, TXGBE_IVARMISC, tmp);
3418 /* rx or tx causes */
3419 /* Workround for ICR lost */
3420 idx = ((16 * (queue & 1)) + (8 * direction));
3421 tmp = rd32(hw, TXGBE_IVAR(queue >> 1));
3422 tmp &= ~(0xFF << idx);
3423 tmp |= (msix_vector << idx);
3424 wr32(hw, TXGBE_IVAR(queue >> 1), tmp);
3429 * Sets up the hardware to properly generate MSI-X interrupts
3431 * board private structure
3434 txgbe_configure_msix(struct rte_eth_dev *dev)
3436 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3437 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3438 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3439 uint32_t queue_id, base = TXGBE_MISC_VEC_ID;
3440 uint32_t vec = TXGBE_MISC_VEC_ID;
3443 /* won't configure msix register if no mapping is done
3444 * between intr vector and event fd
3445 * but if misx has been enabled already, need to configure
3446 * auto clean, auto mask and throttling.
3448 gpie = rd32(hw, TXGBE_GPIE);
3449 if (!rte_intr_dp_is_en(intr_handle) &&
3450 !(gpie & TXGBE_GPIE_MSIX))
3453 if (rte_intr_allow_others(intr_handle)) {
3454 base = TXGBE_RX_VEC_START;
3458 /* setup GPIE for MSI-x mode */
3459 gpie = rd32(hw, TXGBE_GPIE);
3460 gpie |= TXGBE_GPIE_MSIX;
3461 wr32(hw, TXGBE_GPIE, gpie);
3463 /* Populate the IVAR table and set the ITR values to the
3464 * corresponding register.
3466 if (rte_intr_dp_is_en(intr_handle)) {
3467 for (queue_id = 0; queue_id < dev->data->nb_rx_queues;
3469 /* by default, 1:1 mapping */
3470 txgbe_set_ivar_map(hw, 0, queue_id, vec);
3471 intr_handle->intr_vec[queue_id] = vec;
3472 if (vec < base + intr_handle->nb_efd - 1)
3476 txgbe_set_ivar_map(hw, -1, 1, TXGBE_MISC_VEC_ID);
3478 wr32(hw, TXGBE_ITR(TXGBE_MISC_VEC_ID),
3479 TXGBE_ITR_IVAL_10G(TXGBE_QUEUE_ITR_INTERVAL_DEFAULT)
3484 txgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
3485 uint16_t queue_idx, uint16_t tx_rate)
3487 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3490 if (queue_idx >= hw->mac.max_tx_queues)
3494 bcnrc_val = TXGBE_ARBTXRATE_MAX(tx_rate);
3495 bcnrc_val |= TXGBE_ARBTXRATE_MIN(tx_rate / 2);
3501 * Set global transmit compensation time to the MMW_SIZE in ARBTXMMW
3502 * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported.
3504 wr32(hw, TXGBE_ARBTXMMW, 0x14);
3506 /* Set ARBTXRATE of queue X */
3507 wr32(hw, TXGBE_ARBPOOLIDX, queue_idx);
3508 wr32(hw, TXGBE_ARBTXRATE, bcnrc_val);
3515 txgbe_syn_filter_set(struct rte_eth_dev *dev,
3516 struct rte_eth_syn_filter *filter,
3519 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3520 struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(dev);
3524 if (filter->queue >= TXGBE_MAX_RX_QUEUE_NUM)
3527 syn_info = filter_info->syn_info;
3530 if (syn_info & TXGBE_SYNCLS_ENA)
3532 synqf = (uint32_t)TXGBE_SYNCLS_QPID(filter->queue);
3533 synqf |= TXGBE_SYNCLS_ENA;
3535 if (filter->hig_pri)
3536 synqf |= TXGBE_SYNCLS_HIPRIO;
3538 synqf &= ~TXGBE_SYNCLS_HIPRIO;
3540 synqf = rd32(hw, TXGBE_SYNCLS);
3541 if (!(syn_info & TXGBE_SYNCLS_ENA))
3543 synqf &= ~(TXGBE_SYNCLS_QPID_MASK | TXGBE_SYNCLS_ENA);
3546 filter_info->syn_info = synqf;
3547 wr32(hw, TXGBE_SYNCLS, synqf);
3552 static inline enum txgbe_5tuple_protocol
3553 convert_protocol_type(uint8_t protocol_value)
3555 if (protocol_value == IPPROTO_TCP)
3556 return TXGBE_5TF_PROT_TCP;
3557 else if (protocol_value == IPPROTO_UDP)
3558 return TXGBE_5TF_PROT_UDP;
3559 else if (protocol_value == IPPROTO_SCTP)
3560 return TXGBE_5TF_PROT_SCTP;
3562 return TXGBE_5TF_PROT_NONE;
3565 /* inject a 5-tuple filter to HW */
3567 txgbe_inject_5tuple_filter(struct rte_eth_dev *dev,
3568 struct txgbe_5tuple_filter *filter)
3570 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3572 uint32_t ftqf, sdpqf;
3573 uint32_t l34timir = 0;
3574 uint32_t mask = TXGBE_5TFCTL0_MASK;
3577 sdpqf = TXGBE_5TFPORT_DST(be_to_le16(filter->filter_info.dst_port));
3578 sdpqf |= TXGBE_5TFPORT_SRC(be_to_le16(filter->filter_info.src_port));
3580 ftqf = TXGBE_5TFCTL0_PROTO(filter->filter_info.proto);
3581 ftqf |= TXGBE_5TFCTL0_PRI(filter->filter_info.priority);
3582 if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
3583 mask &= ~TXGBE_5TFCTL0_MSADDR;
3584 if (filter->filter_info.dst_ip_mask == 0)
3585 mask &= ~TXGBE_5TFCTL0_MDADDR;
3586 if (filter->filter_info.src_port_mask == 0)
3587 mask &= ~TXGBE_5TFCTL0_MSPORT;
3588 if (filter->filter_info.dst_port_mask == 0)
3589 mask &= ~TXGBE_5TFCTL0_MDPORT;
3590 if (filter->filter_info.proto_mask == 0)
3591 mask &= ~TXGBE_5TFCTL0_MPROTO;
3593 ftqf |= TXGBE_5TFCTL0_MPOOL;
3594 ftqf |= TXGBE_5TFCTL0_ENA;
3596 wr32(hw, TXGBE_5TFDADDR(i), be_to_le32(filter->filter_info.dst_ip));
3597 wr32(hw, TXGBE_5TFSADDR(i), be_to_le32(filter->filter_info.src_ip));
3598 wr32(hw, TXGBE_5TFPORT(i), sdpqf);
3599 wr32(hw, TXGBE_5TFCTL0(i), ftqf);
3601 l34timir |= TXGBE_5TFCTL1_QP(filter->queue);
3602 wr32(hw, TXGBE_5TFCTL1(i), l34timir);
3606 * add a 5tuple filter
3609 * dev: Pointer to struct rte_eth_dev.
3610 * index: the index the filter allocates.
3611 * filter: pointer to the filter that will be added.
3612 * rx_queue: the queue id the filter assigned to.
3615 * - On success, zero.
3616 * - On failure, a negative value.
3619 txgbe_add_5tuple_filter(struct rte_eth_dev *dev,
3620 struct txgbe_5tuple_filter *filter)
3622 struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(dev);
3626 * look for an unused 5tuple filter index,
3627 * and insert the filter to list.
3629 for (i = 0; i < TXGBE_MAX_FTQF_FILTERS; i++) {
3630 idx = i / (sizeof(uint32_t) * NBBY);
3631 shift = i % (sizeof(uint32_t) * NBBY);
3632 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
3633 filter_info->fivetuple_mask[idx] |= 1 << shift;
3635 TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
3641 if (i >= TXGBE_MAX_FTQF_FILTERS) {
3642 PMD_DRV_LOG(ERR, "5tuple filters are full.");
3646 txgbe_inject_5tuple_filter(dev, filter);
3652 * remove a 5tuple filter
3655 * dev: Pointer to struct rte_eth_dev.
3656 * filter: the pointer of the filter will be removed.
3659 txgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
3660 struct txgbe_5tuple_filter *filter)
3662 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3663 struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(dev);
3664 uint16_t index = filter->index;
3666 filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
3667 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
3668 TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
3671 wr32(hw, TXGBE_5TFDADDR(index), 0);
3672 wr32(hw, TXGBE_5TFSADDR(index), 0);
3673 wr32(hw, TXGBE_5TFPORT(index), 0);
3674 wr32(hw, TXGBE_5TFCTL0(index), 0);
3675 wr32(hw, TXGBE_5TFCTL1(index), 0);
3678 static inline struct txgbe_5tuple_filter *
3679 txgbe_5tuple_filter_lookup(struct txgbe_5tuple_filter_list *filter_list,
3680 struct txgbe_5tuple_filter_info *key)
3682 struct txgbe_5tuple_filter *it;
3684 TAILQ_FOREACH(it, filter_list, entries) {
3685 if (memcmp(key, &it->filter_info,
3686 sizeof(struct txgbe_5tuple_filter_info)) == 0) {
3693 /* translate elements in struct rte_eth_ntuple_filter
3694 * to struct txgbe_5tuple_filter_info
3697 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
3698 struct txgbe_5tuple_filter_info *filter_info)
3700 if (filter->queue >= TXGBE_MAX_RX_QUEUE_NUM ||
3701 filter->priority > TXGBE_5TUPLE_MAX_PRI ||
3702 filter->priority < TXGBE_5TUPLE_MIN_PRI)
3705 switch (filter->dst_ip_mask) {
3707 filter_info->dst_ip_mask = 0;
3708 filter_info->dst_ip = filter->dst_ip;
3711 filter_info->dst_ip_mask = 1;
3714 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
3718 switch (filter->src_ip_mask) {
3720 filter_info->src_ip_mask = 0;
3721 filter_info->src_ip = filter->src_ip;
3724 filter_info->src_ip_mask = 1;
3727 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
3731 switch (filter->dst_port_mask) {
3733 filter_info->dst_port_mask = 0;
3734 filter_info->dst_port = filter->dst_port;
3737 filter_info->dst_port_mask = 1;
3740 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
3744 switch (filter->src_port_mask) {
3746 filter_info->src_port_mask = 0;
3747 filter_info->src_port = filter->src_port;
3750 filter_info->src_port_mask = 1;
3753 PMD_DRV_LOG(ERR, "invalid src_port mask.");
3757 switch (filter->proto_mask) {
3759 filter_info->proto_mask = 0;
3760 filter_info->proto =
3761 convert_protocol_type(filter->proto);
3764 filter_info->proto_mask = 1;
3767 PMD_DRV_LOG(ERR, "invalid protocol mask.");
3771 filter_info->priority = (uint8_t)filter->priority;
3776 * add or delete a ntuple filter
3779 * dev: Pointer to struct rte_eth_dev.
3780 * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
3781 * add: if true, add filter, if false, remove filter
3784 * - On success, zero.
3785 * - On failure, a negative value.
3788 txgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
3789 struct rte_eth_ntuple_filter *ntuple_filter,
3792 struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(dev);
3793 struct txgbe_5tuple_filter_info filter_5tuple;
3794 struct txgbe_5tuple_filter *filter;
3797 if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
3798 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
3802 memset(&filter_5tuple, 0, sizeof(struct txgbe_5tuple_filter_info));
3803 ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
3807 filter = txgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
3809 if (filter != NULL && add) {
3810 PMD_DRV_LOG(ERR, "filter exists.");
3813 if (filter == NULL && !add) {
3814 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3819 filter = rte_zmalloc("txgbe_5tuple_filter",
3820 sizeof(struct txgbe_5tuple_filter), 0);
3823 rte_memcpy(&filter->filter_info,
3825 sizeof(struct txgbe_5tuple_filter_info));
3826 filter->queue = ntuple_filter->queue;
3827 ret = txgbe_add_5tuple_filter(dev, filter);
3833 txgbe_remove_5tuple_filter(dev, filter);
3840 txgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
3841 struct rte_eth_ethertype_filter *filter,
3844 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3845 struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(dev);
3849 struct txgbe_ethertype_filter ethertype_filter;
3851 if (filter->queue >= TXGBE_MAX_RX_QUEUE_NUM)
3854 if (filter->ether_type == RTE_ETHER_TYPE_IPV4 ||
3855 filter->ether_type == RTE_ETHER_TYPE_IPV6) {
3856 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
3857 " ethertype filter.", filter->ether_type);
3861 if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
3862 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
3865 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
3866 PMD_DRV_LOG(ERR, "drop option is unsupported.");
3870 ret = txgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
3871 if (ret >= 0 && add) {
3872 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
3873 filter->ether_type);
3876 if (ret < 0 && !add) {
3877 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
3878 filter->ether_type);
3883 etqf = TXGBE_ETFLT_ENA;
3884 etqf |= TXGBE_ETFLT_ETID(filter->ether_type);
3885 etqs |= TXGBE_ETCLS_QPID(filter->queue);
3886 etqs |= TXGBE_ETCLS_QENA;
3888 ethertype_filter.ethertype = filter->ether_type;
3889 ethertype_filter.etqf = etqf;
3890 ethertype_filter.etqs = etqs;
3891 ethertype_filter.conf = FALSE;
3892 ret = txgbe_ethertype_filter_insert(filter_info,
3895 PMD_DRV_LOG(ERR, "ethertype filters are full.");
3899 ret = txgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
3903 wr32(hw, TXGBE_ETFLT(ret), etqf);
3904 wr32(hw, TXGBE_ETCLS(ret), etqs);
3911 txgbe_dev_filter_ctrl(__rte_unused struct rte_eth_dev *dev,
3912 enum rte_filter_type filter_type,
3913 enum rte_filter_op filter_op,
3918 switch (filter_type) {
3919 case RTE_ETH_FILTER_GENERIC:
3920 if (filter_op != RTE_ETH_FILTER_GET)
3922 *(const void **)arg = &txgbe_flow_ops;
3925 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
3935 txgbe_dev_addr_list_itr(__rte_unused struct txgbe_hw *hw,
3936 u8 **mc_addr_ptr, u32 *vmdq)
3941 mc_addr = *mc_addr_ptr;
3942 *mc_addr_ptr = (mc_addr + sizeof(struct rte_ether_addr));
3947 txgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
3948 struct rte_ether_addr *mc_addr_set,
3949 uint32_t nb_mc_addr)
3951 struct txgbe_hw *hw;
3954 hw = TXGBE_DEV_HW(dev);
3955 mc_addr_list = (u8 *)mc_addr_set;
3956 return txgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
3957 txgbe_dev_addr_list_itr, TRUE);
3961 txgbe_read_systime_cyclecounter(struct rte_eth_dev *dev)
3963 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3964 uint64_t systime_cycles;
3966 systime_cycles = (uint64_t)rd32(hw, TXGBE_TSTIMEL);
3967 systime_cycles |= (uint64_t)rd32(hw, TXGBE_TSTIMEH) << 32;
3969 return systime_cycles;
3973 txgbe_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
3975 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3976 uint64_t rx_tstamp_cycles;
3978 /* TSRXSTMPL stores ns and TSRXSTMPH stores seconds. */
3979 rx_tstamp_cycles = (uint64_t)rd32(hw, TXGBE_TSRXSTMPL);
3980 rx_tstamp_cycles |= (uint64_t)rd32(hw, TXGBE_TSRXSTMPH) << 32;
3982 return rx_tstamp_cycles;
3986 txgbe_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
3988 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3989 uint64_t tx_tstamp_cycles;
3991 /* TSTXSTMPL stores ns and TSTXSTMPH stores seconds. */
3992 tx_tstamp_cycles = (uint64_t)rd32(hw, TXGBE_TSTXSTMPL);
3993 tx_tstamp_cycles |= (uint64_t)rd32(hw, TXGBE_TSTXSTMPH) << 32;
3995 return tx_tstamp_cycles;
3999 txgbe_start_timecounters(struct rte_eth_dev *dev)
4001 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4002 struct txgbe_adapter *adapter = TXGBE_DEV_ADAPTER(dev);
4003 struct rte_eth_link link;
4004 uint32_t incval = 0;
4007 /* Get current link speed. */
4008 txgbe_dev_link_update(dev, 1);
4009 rte_eth_linkstatus_get(dev, &link);
4011 switch (link.link_speed) {
4012 case ETH_SPEED_NUM_100M:
4013 incval = TXGBE_INCVAL_100;
4014 shift = TXGBE_INCVAL_SHIFT_100;
4016 case ETH_SPEED_NUM_1G:
4017 incval = TXGBE_INCVAL_1GB;
4018 shift = TXGBE_INCVAL_SHIFT_1GB;
4020 case ETH_SPEED_NUM_10G:
4022 incval = TXGBE_INCVAL_10GB;
4023 shift = TXGBE_INCVAL_SHIFT_10GB;
4027 wr32(hw, TXGBE_TSTIMEINC, TXGBE_TSTIMEINC_VP(incval, 2));
4029 memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
4030 memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
4031 memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
4033 adapter->systime_tc.cc_mask = TXGBE_CYCLECOUNTER_MASK;
4034 adapter->systime_tc.cc_shift = shift;
4035 adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
4037 adapter->rx_tstamp_tc.cc_mask = TXGBE_CYCLECOUNTER_MASK;
4038 adapter->rx_tstamp_tc.cc_shift = shift;
4039 adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
4041 adapter->tx_tstamp_tc.cc_mask = TXGBE_CYCLECOUNTER_MASK;
4042 adapter->tx_tstamp_tc.cc_shift = shift;
4043 adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
4047 txgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
4049 struct txgbe_adapter *adapter = TXGBE_DEV_ADAPTER(dev);
4051 adapter->systime_tc.nsec += delta;
4052 adapter->rx_tstamp_tc.nsec += delta;
4053 adapter->tx_tstamp_tc.nsec += delta;
4059 txgbe_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
4062 struct txgbe_adapter *adapter = TXGBE_DEV_ADAPTER(dev);
4064 ns = rte_timespec_to_ns(ts);
4065 /* Set the timecounters to a new value. */
4066 adapter->systime_tc.nsec = ns;
4067 adapter->rx_tstamp_tc.nsec = ns;
4068 adapter->tx_tstamp_tc.nsec = ns;
4074 txgbe_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
4076 uint64_t ns, systime_cycles;
4077 struct txgbe_adapter *adapter = TXGBE_DEV_ADAPTER(dev);
4079 systime_cycles = txgbe_read_systime_cyclecounter(dev);
4080 ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
4081 *ts = rte_ns_to_timespec(ns);
4087 txgbe_timesync_enable(struct rte_eth_dev *dev)
4089 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4092 /* Stop the timesync system time. */
4093 wr32(hw, TXGBE_TSTIMEINC, 0x0);
4094 /* Reset the timesync system time value. */
4095 wr32(hw, TXGBE_TSTIMEL, 0x0);
4096 wr32(hw, TXGBE_TSTIMEH, 0x0);
4098 txgbe_start_timecounters(dev);
4100 /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
4101 wr32(hw, TXGBE_ETFLT(TXGBE_ETF_ID_1588),
4102 RTE_ETHER_TYPE_1588 | TXGBE_ETFLT_ENA | TXGBE_ETFLT_1588);
4104 /* Enable timestamping of received PTP packets. */
4105 tsync_ctl = rd32(hw, TXGBE_TSRXCTL);
4106 tsync_ctl |= TXGBE_TSRXCTL_ENA;
4107 wr32(hw, TXGBE_TSRXCTL, tsync_ctl);
4109 /* Enable timestamping of transmitted PTP packets. */
4110 tsync_ctl = rd32(hw, TXGBE_TSTXCTL);
4111 tsync_ctl |= TXGBE_TSTXCTL_ENA;
4112 wr32(hw, TXGBE_TSTXCTL, tsync_ctl);
4120 txgbe_timesync_disable(struct rte_eth_dev *dev)
4122 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4125 /* Disable timestamping of transmitted PTP packets. */
4126 tsync_ctl = rd32(hw, TXGBE_TSTXCTL);
4127 tsync_ctl &= ~TXGBE_TSTXCTL_ENA;
4128 wr32(hw, TXGBE_TSTXCTL, tsync_ctl);
4130 /* Disable timestamping of received PTP packets. */
4131 tsync_ctl = rd32(hw, TXGBE_TSRXCTL);
4132 tsync_ctl &= ~TXGBE_TSRXCTL_ENA;
4133 wr32(hw, TXGBE_TSRXCTL, tsync_ctl);
4135 /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
4136 wr32(hw, TXGBE_ETFLT(TXGBE_ETF_ID_1588), 0);
4138 /* Stop incrementating the System Time registers. */
4139 wr32(hw, TXGBE_TSTIMEINC, 0);
4145 txgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
4146 struct timespec *timestamp,
4147 uint32_t flags __rte_unused)
4149 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4150 struct txgbe_adapter *adapter = TXGBE_DEV_ADAPTER(dev);
4151 uint32_t tsync_rxctl;
4152 uint64_t rx_tstamp_cycles;
4155 tsync_rxctl = rd32(hw, TXGBE_TSRXCTL);
4156 if ((tsync_rxctl & TXGBE_TSRXCTL_VLD) == 0)
4159 rx_tstamp_cycles = txgbe_read_rx_tstamp_cyclecounter(dev);
4160 ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
4161 *timestamp = rte_ns_to_timespec(ns);
4167 txgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
4168 struct timespec *timestamp)
4170 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4171 struct txgbe_adapter *adapter = TXGBE_DEV_ADAPTER(dev);
4172 uint32_t tsync_txctl;
4173 uint64_t tx_tstamp_cycles;
4176 tsync_txctl = rd32(hw, TXGBE_TSTXCTL);
4177 if ((tsync_txctl & TXGBE_TSTXCTL_VLD) == 0)
4180 tx_tstamp_cycles = txgbe_read_tx_tstamp_cyclecounter(dev);
4181 ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
4182 *timestamp = rte_ns_to_timespec(ns);
4188 txgbe_get_reg_length(struct rte_eth_dev *dev __rte_unused)
4192 const struct reg_info *reg_group;
4193 const struct reg_info **reg_set = txgbe_regs_others;
4195 while ((reg_group = reg_set[g_ind++]))
4196 count += txgbe_regs_group_count(reg_group);
4202 txgbe_get_regs(struct rte_eth_dev *dev,
4203 struct rte_dev_reg_info *regs)
4205 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4206 uint32_t *data = regs->data;
4209 const struct reg_info *reg_group;
4210 const struct reg_info **reg_set = txgbe_regs_others;
4213 regs->length = txgbe_get_reg_length(dev);
4214 regs->width = sizeof(uint32_t);
4218 /* Support only full register dump */
4219 if (regs->length == 0 ||
4220 regs->length == (uint32_t)txgbe_get_reg_length(dev)) {
4221 regs->version = hw->mac.type << 24 |
4222 hw->revision_id << 16 |
4224 while ((reg_group = reg_set[g_ind++]))
4225 count += txgbe_read_regs_group(dev, &data[count],
4234 txgbe_get_eeprom_length(struct rte_eth_dev *dev)
4236 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4238 /* Return unit is byte count */
4239 return hw->rom.word_size * 2;
4243 txgbe_get_eeprom(struct rte_eth_dev *dev,
4244 struct rte_dev_eeprom_info *in_eeprom)
4246 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4247 struct txgbe_rom_info *eeprom = &hw->rom;
4248 uint16_t *data = in_eeprom->data;
4251 first = in_eeprom->offset >> 1;
4252 length = in_eeprom->length >> 1;
4253 if (first > hw->rom.word_size ||
4254 ((first + length) > hw->rom.word_size))
4257 in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
4259 return eeprom->readw_buffer(hw, first, length, data);
4263 txgbe_set_eeprom(struct rte_eth_dev *dev,
4264 struct rte_dev_eeprom_info *in_eeprom)
4266 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4267 struct txgbe_rom_info *eeprom = &hw->rom;
4268 uint16_t *data = in_eeprom->data;
4271 first = in_eeprom->offset >> 1;
4272 length = in_eeprom->length >> 1;
4273 if (first > hw->rom.word_size ||
4274 ((first + length) > hw->rom.word_size))
4277 in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
4279 return eeprom->writew_buffer(hw, first, length, data);
4283 txgbe_get_module_info(struct rte_eth_dev *dev,
4284 struct rte_eth_dev_module_info *modinfo)
4286 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4288 uint8_t sff8472_rev, addr_mode;
4289 bool page_swap = false;
4291 /* Check whether we support SFF-8472 or not */
4292 status = hw->phy.read_i2c_eeprom(hw,
4293 TXGBE_SFF_SFF_8472_COMP,
4298 /* addressing mode is not supported */
4299 status = hw->phy.read_i2c_eeprom(hw,
4300 TXGBE_SFF_SFF_8472_SWAP,
4305 if (addr_mode & TXGBE_SFF_ADDRESSING_MODE) {
4307 "Address change required to access page 0xA2, "
4308 "but not supported. Please report the module "
4309 "type to the driver maintainers.");
4313 if (sff8472_rev == TXGBE_SFF_SFF_8472_UNSUP || page_swap) {
4314 /* We have a SFP, but it does not support SFF-8472 */
4315 modinfo->type = RTE_ETH_MODULE_SFF_8079;
4316 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
4318 /* We have a SFP which supports a revision of SFF-8472. */
4319 modinfo->type = RTE_ETH_MODULE_SFF_8472;
4320 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
4327 txgbe_get_module_eeprom(struct rte_eth_dev *dev,
4328 struct rte_dev_eeprom_info *info)
4330 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4331 uint32_t status = TXGBE_ERR_PHY_ADDR_INVALID;
4332 uint8_t databyte = 0xFF;
4333 uint8_t *data = info->data;
4336 if (info->length == 0)
4339 for (i = info->offset; i < info->offset + info->length; i++) {
4340 if (i < RTE_ETH_MODULE_SFF_8079_LEN)
4341 status = hw->phy.read_i2c_eeprom(hw, i, &databyte);
4343 status = hw->phy.read_i2c_sff8472(hw, i, &databyte);
4348 data[i - info->offset] = databyte;
4355 txgbe_rss_update_sp(enum txgbe_mac_type mac_type)
4358 case txgbe_mac_raptor:
4366 txgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
4367 struct rte_eth_dcb_info *dcb_info)
4369 struct txgbe_dcb_config *dcb_config = TXGBE_DEV_DCB_CONFIG(dev);
4370 struct txgbe_dcb_tc_config *tc;
4371 struct rte_eth_dcb_tc_queue_mapping *tc_queue;
4375 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
4376 dcb_info->nb_tcs = dcb_config->num_tcs.pg_tcs;
4378 dcb_info->nb_tcs = 1;
4380 tc_queue = &dcb_info->tc_queue;
4381 nb_tcs = dcb_info->nb_tcs;
4383 if (dcb_config->vt_mode) { /* vt is enabled */
4384 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
4385 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
4386 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
4387 dcb_info->prio_tc[i] = vmdq_rx_conf->dcb_tc[i];
4388 if (RTE_ETH_DEV_SRIOV(dev).active > 0) {
4389 for (j = 0; j < nb_tcs; j++) {
4390 tc_queue->tc_rxq[0][j].base = j;
4391 tc_queue->tc_rxq[0][j].nb_queue = 1;
4392 tc_queue->tc_txq[0][j].base = j;
4393 tc_queue->tc_txq[0][j].nb_queue = 1;
4396 for (i = 0; i < vmdq_rx_conf->nb_queue_pools; i++) {
4397 for (j = 0; j < nb_tcs; j++) {
4398 tc_queue->tc_rxq[i][j].base =
4400 tc_queue->tc_rxq[i][j].nb_queue = 1;
4401 tc_queue->tc_txq[i][j].base =
4403 tc_queue->tc_txq[i][j].nb_queue = 1;
4407 } else { /* vt is disabled */
4408 struct rte_eth_dcb_rx_conf *rx_conf =
4409 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
4410 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
4411 dcb_info->prio_tc[i] = rx_conf->dcb_tc[i];
4412 if (dcb_info->nb_tcs == ETH_4_TCS) {
4413 for (i = 0; i < dcb_info->nb_tcs; i++) {
4414 dcb_info->tc_queue.tc_rxq[0][i].base = i * 32;
4415 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
4417 dcb_info->tc_queue.tc_txq[0][0].base = 0;
4418 dcb_info->tc_queue.tc_txq[0][1].base = 64;
4419 dcb_info->tc_queue.tc_txq[0][2].base = 96;
4420 dcb_info->tc_queue.tc_txq[0][3].base = 112;
4421 dcb_info->tc_queue.tc_txq[0][0].nb_queue = 64;
4422 dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
4423 dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
4424 dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
4425 } else if (dcb_info->nb_tcs == ETH_8_TCS) {
4426 for (i = 0; i < dcb_info->nb_tcs; i++) {
4427 dcb_info->tc_queue.tc_rxq[0][i].base = i * 16;
4428 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
4430 dcb_info->tc_queue.tc_txq[0][0].base = 0;
4431 dcb_info->tc_queue.tc_txq[0][1].base = 32;
4432 dcb_info->tc_queue.tc_txq[0][2].base = 64;
4433 dcb_info->tc_queue.tc_txq[0][3].base = 80;
4434 dcb_info->tc_queue.tc_txq[0][4].base = 96;
4435 dcb_info->tc_queue.tc_txq[0][5].base = 104;
4436 dcb_info->tc_queue.tc_txq[0][6].base = 112;
4437 dcb_info->tc_queue.tc_txq[0][7].base = 120;
4438 dcb_info->tc_queue.tc_txq[0][0].nb_queue = 32;
4439 dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
4440 dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
4441 dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
4442 dcb_info->tc_queue.tc_txq[0][4].nb_queue = 8;
4443 dcb_info->tc_queue.tc_txq[0][5].nb_queue = 8;
4444 dcb_info->tc_queue.tc_txq[0][6].nb_queue = 8;
4445 dcb_info->tc_queue.tc_txq[0][7].nb_queue = 8;
4448 for (i = 0; i < dcb_info->nb_tcs; i++) {
4449 tc = &dcb_config->tc_config[i];
4450 dcb_info->tc_bws[i] = tc->path[TXGBE_DCB_TX_CONFIG].bwg_percent;
4455 /* restore n-tuple filter */
4457 txgbe_ntuple_filter_restore(struct rte_eth_dev *dev)
4459 struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(dev);
4460 struct txgbe_5tuple_filter *node;
4462 TAILQ_FOREACH(node, &filter_info->fivetuple_list, entries) {
4463 txgbe_inject_5tuple_filter(dev, node);
4467 /* restore ethernet type filter */
4469 txgbe_ethertype_filter_restore(struct rte_eth_dev *dev)
4471 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4472 struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(dev);
4475 for (i = 0; i < TXGBE_ETF_ID_MAX; i++) {
4476 if (filter_info->ethertype_mask & (1 << i)) {
4477 wr32(hw, TXGBE_ETFLT(i),
4478 filter_info->ethertype_filters[i].etqf);
4479 wr32(hw, TXGBE_ETCLS(i),
4480 filter_info->ethertype_filters[i].etqs);
4486 /* restore SYN filter */
4488 txgbe_syn_filter_restore(struct rte_eth_dev *dev)
4490 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4491 struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(dev);
4494 synqf = filter_info->syn_info;
4496 if (synqf & TXGBE_SYNCLS_ENA) {
4497 wr32(hw, TXGBE_SYNCLS, synqf);
4503 txgbe_filter_restore(struct rte_eth_dev *dev)
4505 txgbe_ntuple_filter_restore(dev);
4506 txgbe_ethertype_filter_restore(dev);
4507 txgbe_syn_filter_restore(dev);
4512 static const struct eth_dev_ops txgbe_eth_dev_ops = {
4513 .dev_configure = txgbe_dev_configure,
4514 .dev_infos_get = txgbe_dev_info_get,
4515 .dev_start = txgbe_dev_start,
4516 .dev_stop = txgbe_dev_stop,
4517 .dev_set_link_up = txgbe_dev_set_link_up,
4518 .dev_set_link_down = txgbe_dev_set_link_down,
4519 .dev_close = txgbe_dev_close,
4520 .dev_reset = txgbe_dev_reset,
4521 .promiscuous_enable = txgbe_dev_promiscuous_enable,
4522 .promiscuous_disable = txgbe_dev_promiscuous_disable,
4523 .allmulticast_enable = txgbe_dev_allmulticast_enable,
4524 .allmulticast_disable = txgbe_dev_allmulticast_disable,
4525 .link_update = txgbe_dev_link_update,
4526 .stats_get = txgbe_dev_stats_get,
4527 .xstats_get = txgbe_dev_xstats_get,
4528 .xstats_get_by_id = txgbe_dev_xstats_get_by_id,
4529 .stats_reset = txgbe_dev_stats_reset,
4530 .xstats_reset = txgbe_dev_xstats_reset,
4531 .xstats_get_names = txgbe_dev_xstats_get_names,
4532 .xstats_get_names_by_id = txgbe_dev_xstats_get_names_by_id,
4533 .queue_stats_mapping_set = txgbe_dev_queue_stats_mapping_set,
4534 .fw_version_get = txgbe_fw_version_get,
4535 .dev_supported_ptypes_get = txgbe_dev_supported_ptypes_get,
4536 .mtu_set = txgbe_dev_mtu_set,
4537 .vlan_filter_set = txgbe_vlan_filter_set,
4538 .vlan_tpid_set = txgbe_vlan_tpid_set,
4539 .vlan_offload_set = txgbe_vlan_offload_set,
4540 .vlan_strip_queue_set = txgbe_vlan_strip_queue_set,
4541 .rx_queue_start = txgbe_dev_rx_queue_start,
4542 .rx_queue_stop = txgbe_dev_rx_queue_stop,
4543 .tx_queue_start = txgbe_dev_tx_queue_start,
4544 .tx_queue_stop = txgbe_dev_tx_queue_stop,
4545 .rx_queue_setup = txgbe_dev_rx_queue_setup,
4546 .rx_queue_intr_enable = txgbe_dev_rx_queue_intr_enable,
4547 .rx_queue_intr_disable = txgbe_dev_rx_queue_intr_disable,
4548 .rx_queue_release = txgbe_dev_rx_queue_release,
4549 .tx_queue_setup = txgbe_dev_tx_queue_setup,
4550 .tx_queue_release = txgbe_dev_tx_queue_release,
4551 .dev_led_on = txgbe_dev_led_on,
4552 .dev_led_off = txgbe_dev_led_off,
4553 .flow_ctrl_get = txgbe_flow_ctrl_get,
4554 .flow_ctrl_set = txgbe_flow_ctrl_set,
4555 .priority_flow_ctrl_set = txgbe_priority_flow_ctrl_set,
4556 .mac_addr_add = txgbe_add_rar,
4557 .mac_addr_remove = txgbe_remove_rar,
4558 .mac_addr_set = txgbe_set_default_mac_addr,
4559 .uc_hash_table_set = txgbe_uc_hash_table_set,
4560 .uc_all_hash_table_set = txgbe_uc_all_hash_table_set,
4561 .set_queue_rate_limit = txgbe_set_queue_rate_limit,
4562 .reta_update = txgbe_dev_rss_reta_update,
4563 .reta_query = txgbe_dev_rss_reta_query,
4564 .rss_hash_update = txgbe_dev_rss_hash_update,
4565 .rss_hash_conf_get = txgbe_dev_rss_hash_conf_get,
4566 .filter_ctrl = txgbe_dev_filter_ctrl,
4567 .set_mc_addr_list = txgbe_dev_set_mc_addr_list,
4568 .rxq_info_get = txgbe_rxq_info_get,
4569 .txq_info_get = txgbe_txq_info_get,
4570 .timesync_enable = txgbe_timesync_enable,
4571 .timesync_disable = txgbe_timesync_disable,
4572 .timesync_read_rx_timestamp = txgbe_timesync_read_rx_timestamp,
4573 .timesync_read_tx_timestamp = txgbe_timesync_read_tx_timestamp,
4574 .get_reg = txgbe_get_regs,
4575 .get_eeprom_length = txgbe_get_eeprom_length,
4576 .get_eeprom = txgbe_get_eeprom,
4577 .set_eeprom = txgbe_set_eeprom,
4578 .get_module_info = txgbe_get_module_info,
4579 .get_module_eeprom = txgbe_get_module_eeprom,
4580 .get_dcb_info = txgbe_dev_get_dcb_info,
4581 .timesync_adjust_time = txgbe_timesync_adjust_time,
4582 .timesync_read_time = txgbe_timesync_read_time,
4583 .timesync_write_time = txgbe_timesync_write_time,
4584 .tx_done_cleanup = txgbe_dev_tx_done_cleanup,
4587 RTE_PMD_REGISTER_PCI(net_txgbe, rte_txgbe_pmd);
4588 RTE_PMD_REGISTER_PCI_TABLE(net_txgbe, pci_id_txgbe_map);
4589 RTE_PMD_REGISTER_KMOD_DEP(net_txgbe, "* igb_uio | uio_pci_generic | vfio-pci");
4591 RTE_LOG_REGISTER(txgbe_logtype_init, pmd.net.txgbe.init, NOTICE);
4592 RTE_LOG_REGISTER(txgbe_logtype_driver, pmd.net.txgbe.driver, NOTICE);
4594 #ifdef RTE_LIBRTE_TXGBE_DEBUG_RX
4595 RTE_LOG_REGISTER(txgbe_logtype_rx, pmd.net.txgbe.rx, DEBUG);
4597 #ifdef RTE_LIBRTE_TXGBE_DEBUG_TX
4598 RTE_LOG_REGISTER(txgbe_logtype_tx, pmd.net.txgbe.tx, DEBUG);
4601 #ifdef RTE_LIBRTE_TXGBE_DEBUG_TX_FREE
4602 RTE_LOG_REGISTER(txgbe_logtype_tx_free, pmd.net.txgbe.tx_free, DEBUG);