drivers/net/txgbe/txgbe_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2015-2020
   3  */
   4
   5 #include <stdio.h>
   6 #include <errno.h>
   7 #include <stdint.h>
   8 #include <string.h>
   9 #include <rte_common.h>
  10 #include <rte_ethdev_pci.h>
  11
  12 #include <rte_interrupts.h>
  13 #include <rte_log.h>
  14 #include <rte_debug.h>
  15 #include <rte_pci.h>
  16 #include <rte_memory.h>
  17 #include <rte_eal.h>
  18 #include <rte_alarm.h>
  19
  20 #include "txgbe_logs.h"
  21 #include "base/txgbe.h"
  22 #include "txgbe_ethdev.h"
  23 #include "txgbe_rxtx.h"
  24 #include "txgbe_regs_group.h"
  25
  26 static const struct reg_info txgbe_regs_general[] = {
  27         {TXGBE_RST, 1, 1, "TXGBE_RST"},
  28         {TXGBE_STAT, 1, 1, "TXGBE_STAT"},
  29         {TXGBE_PORTCTL, 1, 1, "TXGBE_PORTCTL"},
  30         {TXGBE_SDP, 1, 1, "TXGBE_SDP"},
  31         {TXGBE_SDPCTL, 1, 1, "TXGBE_SDPCTL"},
  32         {TXGBE_LEDCTL, 1, 1, "TXGBE_LEDCTL"},
  33         {0, 0, 0, ""}
  34 };
  35
  36 static const struct reg_info txgbe_regs_nvm[] = {
  37         {0, 0, 0, ""}
  38 };
  39
  40 static const struct reg_info txgbe_regs_interrupt[] = {
  41         {0, 0, 0, ""}
  42 };
  43
  44 static const struct reg_info txgbe_regs_fctl_others[] = {
  45         {0, 0, 0, ""}
  46 };
  47
  48 static const struct reg_info txgbe_regs_rxdma[] = {
  49         {0, 0, 0, ""}
  50 };
  51
  52 static const struct reg_info txgbe_regs_rx[] = {
  53         {0, 0, 0, ""}
  54 };
  55
  56 static struct reg_info txgbe_regs_tx[] = {
  57         {0, 0, 0, ""}
  58 };
  59
  60 static const struct reg_info txgbe_regs_wakeup[] = {
  61         {0, 0, 0, ""}
  62 };
  63
  64 static const struct reg_info txgbe_regs_dcb[] = {
  65         {0, 0, 0, ""}
  66 };
  67
  68 static const struct reg_info txgbe_regs_mac[] = {
  69         {0, 0, 0, ""}
  70 };
  71
  72 static const struct reg_info txgbe_regs_diagnostic[] = {
  73         {0, 0, 0, ""},
  74 };
  75
  76 /* PF registers */
  77 static const struct reg_info *txgbe_regs_others[] = {
  78                                 txgbe_regs_general,
  79                                 txgbe_regs_nvm,
  80                                 txgbe_regs_interrupt,
  81                                 txgbe_regs_fctl_others,
  82                                 txgbe_regs_rxdma,
  83                                 txgbe_regs_rx,
  84                                 txgbe_regs_tx,
  85                                 txgbe_regs_wakeup,
  86                                 txgbe_regs_dcb,
  87                                 txgbe_regs_mac,
  88                                 txgbe_regs_diagnostic,
  89                                 NULL};
  90
  91 static int txgbe_fdir_filter_init(struct rte_eth_dev *eth_dev);
  92 static int txgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev);
  93 static int txgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev);
  94 static int txgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev);
  95 static int  txgbe_dev_set_link_up(struct rte_eth_dev *dev);
  96 static int  txgbe_dev_set_link_down(struct rte_eth_dev *dev);
  97 static int txgbe_dev_close(struct rte_eth_dev *dev);
  98 static int txgbe_dev_link_update(struct rte_eth_dev *dev,
  99                                 int wait_to_complete);
 100 static int txgbe_dev_stats_reset(struct rte_eth_dev *dev);
 101 static void txgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
 102 static void txgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev,
 103                                         uint16_t queue);
 104
 105 static void txgbe_dev_link_status_print(struct rte_eth_dev *dev);
 106 static int txgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on);
 107 static int txgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev);
 108 static int txgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
 109 static int txgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
 110 static int txgbe_dev_interrupt_action(struct rte_eth_dev *dev,
 111                                       struct rte_intr_handle *handle);
 112 static void txgbe_dev_interrupt_handler(void *param);
 113 static void txgbe_dev_interrupt_delayed_handler(void *param);
 114 static void txgbe_configure_msix(struct rte_eth_dev *dev);
 115
 116 static int txgbe_filter_restore(struct rte_eth_dev *dev);
 117 static void txgbe_l2_tunnel_conf(struct rte_eth_dev *dev);
 118
 119 #define TXGBE_SET_HWSTRIP(h, q) do {\
 120                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 121                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 122                 (h)->bitmap[idx] |= 1 << bit;\
 123         } while (0)
 124
 125 #define TXGBE_CLEAR_HWSTRIP(h, q) do {\
 126                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 127                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 128                 (h)->bitmap[idx] &= ~(1 << bit);\
 129         } while (0)
 130
 131 #define TXGBE_GET_HWSTRIP(h, q, r) do {\
 132                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 133                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 134                 (r) = (h)->bitmap[idx] >> bit & 1;\
 135         } while (0)
 136
 137 /*
 138  * The set of PCI devices this driver supports
 139  */
 140 static const struct rte_pci_id pci_id_txgbe_map[] = {
 141         { RTE_PCI_DEVICE(PCI_VENDOR_ID_WANGXUN, TXGBE_DEV_ID_RAPTOR_SFP) },
 142         { RTE_PCI_DEVICE(PCI_VENDOR_ID_WANGXUN, TXGBE_DEV_ID_WX1820_SFP) },
 143         { .vendor_id = 0, /* sentinel */ },
 144 };
 145
 146 static const struct rte_eth_desc_lim rx_desc_lim = {
 147         .nb_max = TXGBE_RING_DESC_MAX,
 148         .nb_min = TXGBE_RING_DESC_MIN,
 149         .nb_align = TXGBE_RXD_ALIGN,
 150 };
 151
 152 static const struct rte_eth_desc_lim tx_desc_lim = {
 153         .nb_max = TXGBE_RING_DESC_MAX,
 154         .nb_min = TXGBE_RING_DESC_MIN,
 155         .nb_align = TXGBE_TXD_ALIGN,
 156         .nb_seg_max = TXGBE_TX_MAX_SEG,
 157         .nb_mtu_seg_max = TXGBE_TX_MAX_SEG,
 158 };
 159
 160 static const struct eth_dev_ops txgbe_eth_dev_ops;
 161
 162 #define HW_XSTAT(m) {#m, offsetof(struct txgbe_hw_stats, m)}
 163 #define HW_XSTAT_NAME(m, n) {n, offsetof(struct txgbe_hw_stats, m)}
 164 static const struct rte_txgbe_xstats_name_off rte_txgbe_stats_strings[] = {
 165         /* MNG RxTx */
 166         HW_XSTAT(mng_bmc2host_packets),
 167         HW_XSTAT(mng_host2bmc_packets),
 168         /* Basic RxTx */
 169         HW_XSTAT(rx_packets),
 170         HW_XSTAT(tx_packets),
 171         HW_XSTAT(rx_bytes),
 172         HW_XSTAT(tx_bytes),
 173         HW_XSTAT(rx_total_bytes),
 174         HW_XSTAT(rx_total_packets),
 175         HW_XSTAT(tx_total_packets),
 176         HW_XSTAT(rx_total_missed_packets),
 177         HW_XSTAT(rx_broadcast_packets),
 178         HW_XSTAT(rx_multicast_packets),
 179         HW_XSTAT(rx_management_packets),
 180         HW_XSTAT(tx_management_packets),
 181         HW_XSTAT(rx_management_dropped),
 182
 183         /* Basic Error */
 184         HW_XSTAT(rx_crc_errors),
 185         HW_XSTAT(rx_illegal_byte_errors),
 186         HW_XSTAT(rx_error_bytes),
 187         HW_XSTAT(rx_mac_short_packet_dropped),
 188         HW_XSTAT(rx_length_errors),
 189         HW_XSTAT(rx_undersize_errors),
 190         HW_XSTAT(rx_fragment_errors),
 191         HW_XSTAT(rx_oversize_errors),
 192         HW_XSTAT(rx_jabber_errors),
 193         HW_XSTAT(rx_l3_l4_xsum_error),
 194         HW_XSTAT(mac_local_errors),
 195         HW_XSTAT(mac_remote_errors),
 196
 197         /* Flow Director */
 198         HW_XSTAT(flow_director_added_filters),
 199         HW_XSTAT(flow_director_removed_filters),
 200         HW_XSTAT(flow_director_filter_add_errors),
 201         HW_XSTAT(flow_director_filter_remove_errors),
 202         HW_XSTAT(flow_director_matched_filters),
 203         HW_XSTAT(flow_director_missed_filters),
 204
 205         /* FCoE */
 206         HW_XSTAT(rx_fcoe_crc_errors),
 207         HW_XSTAT(rx_fcoe_mbuf_allocation_errors),
 208         HW_XSTAT(rx_fcoe_dropped),
 209         HW_XSTAT(rx_fcoe_packets),
 210         HW_XSTAT(tx_fcoe_packets),
 211         HW_XSTAT(rx_fcoe_bytes),
 212         HW_XSTAT(tx_fcoe_bytes),
 213         HW_XSTAT(rx_fcoe_no_ddp),
 214         HW_XSTAT(rx_fcoe_no_ddp_ext_buff),
 215
 216         /* MACSEC */
 217         HW_XSTAT(tx_macsec_pkts_untagged),
 218         HW_XSTAT(tx_macsec_pkts_encrypted),
 219         HW_XSTAT(tx_macsec_pkts_protected),
 220         HW_XSTAT(tx_macsec_octets_encrypted),
 221         HW_XSTAT(tx_macsec_octets_protected),
 222         HW_XSTAT(rx_macsec_pkts_untagged),
 223         HW_XSTAT(rx_macsec_pkts_badtag),
 224         HW_XSTAT(rx_macsec_pkts_nosci),
 225         HW_XSTAT(rx_macsec_pkts_unknownsci),
 226         HW_XSTAT(rx_macsec_octets_decrypted),
 227         HW_XSTAT(rx_macsec_octets_validated),
 228         HW_XSTAT(rx_macsec_sc_pkts_unchecked),
 229         HW_XSTAT(rx_macsec_sc_pkts_delayed),
 230         HW_XSTAT(rx_macsec_sc_pkts_late),
 231         HW_XSTAT(rx_macsec_sa_pkts_ok),
 232         HW_XSTAT(rx_macsec_sa_pkts_invalid),
 233         HW_XSTAT(rx_macsec_sa_pkts_notvalid),
 234         HW_XSTAT(rx_macsec_sa_pkts_unusedsa),
 235         HW_XSTAT(rx_macsec_sa_pkts_notusingsa),
 236
 237         /* MAC RxTx */
 238         HW_XSTAT(rx_size_64_packets),
 239         HW_XSTAT(rx_size_65_to_127_packets),
 240         HW_XSTAT(rx_size_128_to_255_packets),
 241         HW_XSTAT(rx_size_256_to_511_packets),
 242         HW_XSTAT(rx_size_512_to_1023_packets),
 243         HW_XSTAT(rx_size_1024_to_max_packets),
 244         HW_XSTAT(tx_size_64_packets),
 245         HW_XSTAT(tx_size_65_to_127_packets),
 246         HW_XSTAT(tx_size_128_to_255_packets),
 247         HW_XSTAT(tx_size_256_to_511_packets),
 248         HW_XSTAT(tx_size_512_to_1023_packets),
 249         HW_XSTAT(tx_size_1024_to_max_packets),
 250
 251         /* Flow Control */
 252         HW_XSTAT(tx_xon_packets),
 253         HW_XSTAT(rx_xon_packets),
 254         HW_XSTAT(tx_xoff_packets),
 255         HW_XSTAT(rx_xoff_packets),
 256
 257         HW_XSTAT_NAME(tx_xon_packets, "tx_flow_control_xon_packets"),
 258         HW_XSTAT_NAME(rx_xon_packets, "rx_flow_control_xon_packets"),
 259         HW_XSTAT_NAME(tx_xoff_packets, "tx_flow_control_xoff_packets"),
 260         HW_XSTAT_NAME(rx_xoff_packets, "rx_flow_control_xoff_packets"),
 261 };
 262
 263 #define TXGBE_NB_HW_STATS (sizeof(rte_txgbe_stats_strings) / \
 264                            sizeof(rte_txgbe_stats_strings[0]))
 265
 266 /* Per-priority statistics */
 267 #define UP_XSTAT(m) {#m, offsetof(struct txgbe_hw_stats, up[0].m)}
 268 static const struct rte_txgbe_xstats_name_off rte_txgbe_up_strings[] = {
 269         UP_XSTAT(rx_up_packets),
 270         UP_XSTAT(tx_up_packets),
 271         UP_XSTAT(rx_up_bytes),
 272         UP_XSTAT(tx_up_bytes),
 273         UP_XSTAT(rx_up_drop_packets),
 274
 275         UP_XSTAT(tx_up_xon_packets),
 276         UP_XSTAT(rx_up_xon_packets),
 277         UP_XSTAT(tx_up_xoff_packets),
 278         UP_XSTAT(rx_up_xoff_packets),
 279         UP_XSTAT(rx_up_dropped),
 280         UP_XSTAT(rx_up_mbuf_alloc_errors),
 281         UP_XSTAT(tx_up_xon2off_packets),
 282 };
 283
 284 #define TXGBE_NB_UP_STATS (sizeof(rte_txgbe_up_strings) / \
 285                            sizeof(rte_txgbe_up_strings[0]))
 286
 287 /* Per-queue statistics */
 288 #define QP_XSTAT(m) {#m, offsetof(struct txgbe_hw_stats, qp[0].m)}
 289 static const struct rte_txgbe_xstats_name_off rte_txgbe_qp_strings[] = {
 290         QP_XSTAT(rx_qp_packets),
 291         QP_XSTAT(tx_qp_packets),
 292         QP_XSTAT(rx_qp_bytes),
 293         QP_XSTAT(tx_qp_bytes),
 294         QP_XSTAT(rx_qp_mc_packets),
 295 };
 296
 297 #define TXGBE_NB_QP_STATS (sizeof(rte_txgbe_qp_strings) / \
 298                            sizeof(rte_txgbe_qp_strings[0]))
 299
 300 static inline int
 301 txgbe_is_sfp(struct txgbe_hw *hw)
 302 {
 303         switch (hw->phy.type) {
 304         case txgbe_phy_sfp_avago:
 305         case txgbe_phy_sfp_ftl:
 306         case txgbe_phy_sfp_intel:
 307         case txgbe_phy_sfp_unknown:
 308         case txgbe_phy_sfp_tyco_passive:
 309         case txgbe_phy_sfp_unknown_passive:
 310                 return 1;
 311         default:
 312                 return 0;
 313         }
 314 }
 315
 316 static inline int32_t
 317 txgbe_pf_reset_hw(struct txgbe_hw *hw)
 318 {
 319         uint32_t ctrl_ext;
 320         int32_t status;
 321
 322         status = hw->mac.reset_hw(hw);
 323
 324         ctrl_ext = rd32(hw, TXGBE_PORTCTL);
 325         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 326         ctrl_ext |= TXGBE_PORTCTL_RSTDONE;
 327         wr32(hw, TXGBE_PORTCTL, ctrl_ext);
 328         txgbe_flush(hw);
 329
 330         if (status == TXGBE_ERR_SFP_NOT_PRESENT)
 331                 status = 0;
 332         return status;
 333 }
 334
 335 static inline void
 336 txgbe_enable_intr(struct rte_eth_dev *dev)
 337 {
 338         struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);
 339         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
 340
 341         wr32(hw, TXGBE_IENMISC, intr->mask_misc);
 342         wr32(hw, TXGBE_IMC(0), TXGBE_IMC_MASK);
 343         wr32(hw, TXGBE_IMC(1), TXGBE_IMC_MASK);
 344         txgbe_flush(hw);
 345 }
 346
 347 static void
 348 txgbe_disable_intr(struct txgbe_hw *hw)
 349 {
 350         PMD_INIT_FUNC_TRACE();
 351
 352         wr32(hw, TXGBE_IENMISC, ~BIT_MASK32);
 353         wr32(hw, TXGBE_IMS(0), TXGBE_IMC_MASK);
 354         wr32(hw, TXGBE_IMS(1), TXGBE_IMC_MASK);
 355         txgbe_flush(hw);
 356 }
 357
 358 static int
 359 txgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 360                                   uint16_t queue_id,
 361                                   uint8_t stat_idx,
 362                                   uint8_t is_rx)
 363 {
 364         struct txgbe_hw *hw = TXGBE_DEV_HW(eth_dev);
 365         struct txgbe_stat_mappings *stat_mappings =
 366                 TXGBE_DEV_STAT_MAPPINGS(eth_dev);
 367         uint32_t qsmr_mask = 0;
 368         uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
 369         uint32_t q_map;
 370         uint8_t n, offset;
 371
 372         if (hw->mac.type != txgbe_mac_raptor)
 373                 return -ENOSYS;
 374
 375         if (stat_idx & !QMAP_FIELD_RESERVED_BITS_MASK)
 376                 return -EIO;
 377
 378         PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d",
 379                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 380                      queue_id, stat_idx);
 381
 382         n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
 383         if (n >= TXGBE_NB_STAT_MAPPING) {
 384                 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
 385                 return -EIO;
 386         }
 387         offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
 388
 389         /* Now clear any previous stat_idx set */
 390         clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 391         if (!is_rx)
 392                 stat_mappings->tqsm[n] &= ~clearing_mask;
 393         else
 394                 stat_mappings->rqsm[n] &= ~clearing_mask;
 395
 396         q_map = (uint32_t)stat_idx;
 397         q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
 398         qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 399         if (!is_rx)
 400                 stat_mappings->tqsm[n] |= qsmr_mask;
 401         else
 402                 stat_mappings->rqsm[n] |= qsmr_mask;
 403
 404         PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d",
 405                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 406                      queue_id, stat_idx);
 407         PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
 408                      is_rx ? stat_mappings->rqsm[n] : stat_mappings->tqsm[n]);
 409         return 0;
 410 }
 411
 412 static void
 413 txgbe_dcb_init(struct txgbe_hw *hw, struct txgbe_dcb_config *dcb_config)
 414 {
 415         int i;
 416         u8 bwgp;
 417         struct txgbe_dcb_tc_config *tc;
 418
 419         UNREFERENCED_PARAMETER(hw);
 420
 421         dcb_config->num_tcs.pg_tcs = TXGBE_DCB_TC_MAX;
 422         dcb_config->num_tcs.pfc_tcs = TXGBE_DCB_TC_MAX;
 423         bwgp = (u8)(100 / TXGBE_DCB_TC_MAX);
 424         for (i = 0; i < TXGBE_DCB_TC_MAX; i++) {
 425                 tc = &dcb_config->tc_config[i];
 426                 tc->path[TXGBE_DCB_TX_CONFIG].bwg_id = i;
 427                 tc->path[TXGBE_DCB_TX_CONFIG].bwg_percent = bwgp + (i & 1);
 428                 tc->path[TXGBE_DCB_RX_CONFIG].bwg_id = i;
 429                 tc->path[TXGBE_DCB_RX_CONFIG].bwg_percent = bwgp + (i & 1);
 430                 tc->pfc = txgbe_dcb_pfc_disabled;
 431         }
 432
 433         /* Initialize default user to priority mapping, UPx->TC0 */
 434         tc = &dcb_config->tc_config[0];
 435         tc->path[TXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
 436         tc->path[TXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
 437         for (i = 0; i < TXGBE_DCB_BWG_MAX; i++) {
 438                 dcb_config->bw_percentage[i][TXGBE_DCB_TX_CONFIG] = 100;
 439                 dcb_config->bw_percentage[i][TXGBE_DCB_RX_CONFIG] = 100;
 440         }
 441         dcb_config->rx_pba_cfg = txgbe_dcb_pba_equal;
 442         dcb_config->pfc_mode_enable = false;
 443         dcb_config->vt_mode = true;
 444         dcb_config->round_robin_enable = false;
 445         /* support all DCB capabilities */
 446         dcb_config->support.capabilities = 0xFF;
 447 }
 448
 449 /*
 450  * Ensure that all locks are released before first NVM or PHY access
 451  */
 452 static void
 453 txgbe_swfw_lock_reset(struct txgbe_hw *hw)
 454 {
 455         uint16_t mask;
 456
 457         /*
 458          * These ones are more tricky since they are common to all ports; but
 459          * swfw_sync retries last long enough (1s) to be almost sure that if
 460          * lock can not be taken it is due to an improper lock of the
 461          * semaphore.
 462          */
 463         mask = TXGBE_MNGSEM_SWPHY |
 464                TXGBE_MNGSEM_SWMBX |
 465                TXGBE_MNGSEM_SWFLASH;
 466         if (hw->mac.acquire_swfw_sync(hw, mask) < 0)
 467                 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
 468
 469         hw->mac.release_swfw_sync(hw, mask);
 470 }
 471
 472 static int
 473 eth_txgbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params __rte_unused)
 474 {
 475         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
 476         struct txgbe_hw *hw = TXGBE_DEV_HW(eth_dev);
 477         struct txgbe_vfta *shadow_vfta = TXGBE_DEV_VFTA(eth_dev);
 478         struct txgbe_hwstrip *hwstrip = TXGBE_DEV_HWSTRIP(eth_dev);
 479         struct txgbe_dcb_config *dcb_config = TXGBE_DEV_DCB_CONFIG(eth_dev);
 480         struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(eth_dev);
 481         struct txgbe_bw_conf *bw_conf = TXGBE_DEV_BW_CONF(eth_dev);
 482         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 483         const struct rte_memzone *mz;
 484         uint32_t ctrl_ext;
 485         uint16_t csum;
 486         int err, i, ret;
 487
 488         PMD_INIT_FUNC_TRACE();
 489
 490         eth_dev->dev_ops = &txgbe_eth_dev_ops;
 491         eth_dev->rx_queue_count       = txgbe_dev_rx_queue_count;
 492         eth_dev->rx_descriptor_status = txgbe_dev_rx_descriptor_status;
 493         eth_dev->tx_descriptor_status = txgbe_dev_tx_descriptor_status;
 494         eth_dev->rx_pkt_burst = &txgbe_recv_pkts;
 495         eth_dev->tx_pkt_burst = &txgbe_xmit_pkts;
 496         eth_dev->tx_pkt_prepare = &txgbe_prep_pkts;
 497
 498         /*
 499          * For secondary processes, we don't initialise any further as primary
 500          * has already done this work. Only check we don't need a different
 501          * RX and TX function.
 502          */
 503         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
 504                 struct txgbe_tx_queue *txq;
 505                 /* TX queue function in primary, set by last queue initialized
 506                  * Tx queue may not initialized by primary process
 507                  */
 508                 if (eth_dev->data->tx_queues) {
 509                         uint16_t nb_tx_queues = eth_dev->data->nb_tx_queues;
 510                         txq = eth_dev->data->tx_queues[nb_tx_queues - 1];
 511                         txgbe_set_tx_function(eth_dev, txq);
 512                 } else {
 513                         /* Use default TX function if we get here */
 514                         PMD_INIT_LOG(NOTICE, "No TX queues configured yet. "
 515                                      "Using default TX function.");
 516                 }
 517
 518                 txgbe_set_rx_function(eth_dev);
 519
 520                 return 0;
 521         }
 522
 523         rte_eth_copy_pci_info(eth_dev, pci_dev);
 524
 525         /* Vendor and Device ID need to be set before init of shared code */
 526         hw->device_id = pci_dev->id.device_id;
 527         hw->vendor_id = pci_dev->id.vendor_id;
 528         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
 529         hw->allow_unsupported_sfp = 1;
 530
 531         /* Reserve memory for interrupt status block */
 532         mz = rte_eth_dma_zone_reserve(eth_dev, "txgbe_driver", -1,
 533                 16, TXGBE_ALIGN, SOCKET_ID_ANY);
 534         if (mz == NULL)
 535                 return -ENOMEM;
 536
 537         hw->isb_dma = TMZ_PADDR(mz);
 538         hw->isb_mem = TMZ_VADDR(mz);
 539
 540         /* Initialize the shared code (base driver) */
 541         err = txgbe_init_shared_code(hw);
 542         if (err != 0) {
 543                 PMD_INIT_LOG(ERR, "Shared code init failed: %d", err);
 544                 return -EIO;
 545         }
 546
 547         /* Unlock any pending hardware semaphore */
 548         txgbe_swfw_lock_reset(hw);
 549
 550         /* Initialize DCB configuration*/
 551         memset(dcb_config, 0, sizeof(struct txgbe_dcb_config));
 552         txgbe_dcb_init(hw, dcb_config);
 553
 554         /* Get Hardware Flow Control setting */
 555         hw->fc.requested_mode = txgbe_fc_full;
 556         hw->fc.current_mode = txgbe_fc_full;
 557         hw->fc.pause_time = TXGBE_FC_PAUSE_TIME;
 558         for (i = 0; i < TXGBE_DCB_TC_MAX; i++) {
 559                 hw->fc.low_water[i] = TXGBE_FC_XON_LOTH;
 560                 hw->fc.high_water[i] = TXGBE_FC_XOFF_HITH;
 561         }
 562         hw->fc.send_xon = 1;
 563
 564         err = hw->rom.init_params(hw);
 565         if (err != 0) {
 566                 PMD_INIT_LOG(ERR, "The EEPROM init failed: %d", err);
 567                 return -EIO;
 568         }
 569
 570         /* Make sure we have a good EEPROM before we read from it */
 571         err = hw->rom.validate_checksum(hw, &csum);
 572         if (err != 0) {
 573                 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", err);
 574                 return -EIO;
 575         }
 576
 577         err = hw->mac.init_hw(hw);
 578
 579         /*
 580          * Devices with copper phys will fail to initialise if txgbe_init_hw()
 581          * is called too soon after the kernel driver unbinding/binding occurs.
 582          * The failure occurs in txgbe_identify_phy() for all devices,
 583          * but for non-copper devies, txgbe_identify_sfp_module() is
 584          * also called. See txgbe_identify_phy(). The reason for the
 585          * failure is not known, and only occuts when virtualisation features
 586          * are disabled in the bios. A delay of 200ms  was found to be enough by
 587          * trial-and-error, and is doubled to be safe.
 588          */
 589         if (err && hw->phy.media_type == txgbe_media_type_copper) {
 590                 rte_delay_ms(200);
 591                 err = hw->mac.init_hw(hw);
 592         }
 593
 594         if (err == TXGBE_ERR_SFP_NOT_PRESENT)
 595                 err = 0;
 596
 597         if (err == TXGBE_ERR_EEPROM_VERSION) {
 598                 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
 599                              "LOM.  Please be aware there may be issues associated "
 600                              "with your hardware.");
 601                 PMD_INIT_LOG(ERR, "If you are experiencing problems "
 602                              "please contact your hardware representative "
 603                              "who provided you with this hardware.");
 604         } else if (err == TXGBE_ERR_SFP_NOT_SUPPORTED) {
 605                 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
 606         }
 607         if (err) {
 608                 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", err);
 609                 return -EIO;
 610         }
 611
 612         /* Reset the hw statistics */
 613         txgbe_dev_stats_reset(eth_dev);
 614
 615         /* disable interrupt */
 616         txgbe_disable_intr(hw);
 617
 618         /* Allocate memory for storing MAC addresses */
 619         eth_dev->data->mac_addrs = rte_zmalloc("txgbe", RTE_ETHER_ADDR_LEN *
 620                                                hw->mac.num_rar_entries, 0);
 621         if (eth_dev->data->mac_addrs == NULL) {
 622                 PMD_INIT_LOG(ERR,
 623                              "Failed to allocate %u bytes needed to store "
 624                              "MAC addresses",
 625                              RTE_ETHER_ADDR_LEN * hw->mac.num_rar_entries);
 626                 return -ENOMEM;
 627         }
 628
 629         /* Copy the permanent MAC address */
 630         rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.perm_addr,
 631                         &eth_dev->data->mac_addrs[0]);
 632
 633         /* Allocate memory for storing hash filter MAC addresses */
 634         eth_dev->data->hash_mac_addrs = rte_zmalloc("txgbe",
 635                         RTE_ETHER_ADDR_LEN * TXGBE_VMDQ_NUM_UC_MAC, 0);
 636         if (eth_dev->data->hash_mac_addrs == NULL) {
 637                 PMD_INIT_LOG(ERR,
 638                              "Failed to allocate %d bytes needed to store MAC addresses",
 639                              RTE_ETHER_ADDR_LEN * TXGBE_VMDQ_NUM_UC_MAC);
 640                 return -ENOMEM;
 641         }
 642
 643         /* initialize the vfta */
 644         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
 645
 646         /* initialize the hw strip bitmap*/
 647         memset(hwstrip, 0, sizeof(*hwstrip));
 648
 649         /* initialize PF if max_vfs not zero */
 650         ret = txgbe_pf_host_init(eth_dev);
 651         if (ret) {
 652                 rte_free(eth_dev->data->mac_addrs);
 653                 eth_dev->data->mac_addrs = NULL;
 654                 rte_free(eth_dev->data->hash_mac_addrs);
 655                 eth_dev->data->hash_mac_addrs = NULL;
 656                 return ret;
 657         }
 658
 659         ctrl_ext = rd32(hw, TXGBE_PORTCTL);
 660         /* let hardware know driver is loaded */
 661         ctrl_ext |= TXGBE_PORTCTL_DRVLOAD;
 662         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 663         ctrl_ext |= TXGBE_PORTCTL_RSTDONE;
 664         wr32(hw, TXGBE_PORTCTL, ctrl_ext);
 665         txgbe_flush(hw);
 666
 667         if (txgbe_is_sfp(hw) && hw->phy.sfp_type != txgbe_sfp_type_not_present)
 668                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
 669                              (int)hw->mac.type, (int)hw->phy.type,
 670                              (int)hw->phy.sfp_type);
 671         else
 672                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
 673                              (int)hw->mac.type, (int)hw->phy.type);
 674
 675         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
 676                      eth_dev->data->port_id, pci_dev->id.vendor_id,
 677                      pci_dev->id.device_id);
 678
 679         rte_intr_callback_register(intr_handle,
 680                                    txgbe_dev_interrupt_handler, eth_dev);
 681
 682         /* enable uio/vfio intr/eventfd mapping */
 683         rte_intr_enable(intr_handle);
 684
 685         /* enable support intr */
 686         txgbe_enable_intr(eth_dev);
 687
 688         /* initialize filter info */
 689         memset(filter_info, 0,
 690                sizeof(struct txgbe_filter_info));
 691
 692         /* initialize 5tuple filter list */
 693         TAILQ_INIT(&filter_info->fivetuple_list);
 694
 695         /* initialize flow director filter list & hash */
 696         txgbe_fdir_filter_init(eth_dev);
 697
 698         /* initialize l2 tunnel filter list & hash */
 699         txgbe_l2_tn_filter_init(eth_dev);
 700
 701         /* initialize bandwidth configuration info */
 702         memset(bw_conf, 0, sizeof(struct txgbe_bw_conf));
 703
 704         return 0;
 705 }
 706
 707 static int
 708 eth_txgbe_dev_uninit(struct rte_eth_dev *eth_dev)
 709 {
 710         PMD_INIT_FUNC_TRACE();
 711
 712         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 713                 return 0;
 714
 715         txgbe_dev_close(eth_dev);
 716
 717         return 0;
 718 }
 719
 720 static int txgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev)
 721 {
 722         struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(eth_dev);
 723         struct txgbe_5tuple_filter *p_5tuple;
 724
 725         while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) {
 726                 TAILQ_REMOVE(&filter_info->fivetuple_list,
 727                              p_5tuple,
 728                              entries);
 729                 rte_free(p_5tuple);
 730         }
 731         memset(filter_info->fivetuple_mask, 0,
 732                sizeof(uint32_t) * TXGBE_5TUPLE_ARRAY_SIZE);
 733
 734         return 0;
 735 }
 736
 737 static int txgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev)
 738 {
 739         struct txgbe_hw_fdir_info *fdir_info = TXGBE_DEV_FDIR(eth_dev);
 740         struct txgbe_fdir_filter *fdir_filter;
 741
 742         if (fdir_info->hash_map)
 743                 rte_free(fdir_info->hash_map);
 744         if (fdir_info->hash_handle)
 745                 rte_hash_free(fdir_info->hash_handle);
 746
 747         while ((fdir_filter = TAILQ_FIRST(&fdir_info->fdir_list))) {
 748                 TAILQ_REMOVE(&fdir_info->fdir_list,
 749                              fdir_filter,
 750                              entries);
 751                 rte_free(fdir_filter);
 752         }
 753
 754         return 0;
 755 }
 756
 757 static int txgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev)
 758 {
 759         struct txgbe_l2_tn_info *l2_tn_info = TXGBE_DEV_L2_TN(eth_dev);
 760         struct txgbe_l2_tn_filter *l2_tn_filter;
 761
 762         if (l2_tn_info->hash_map)
 763                 rte_free(l2_tn_info->hash_map);
 764         if (l2_tn_info->hash_handle)
 765                 rte_hash_free(l2_tn_info->hash_handle);
 766
 767         while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
 768                 TAILQ_REMOVE(&l2_tn_info->l2_tn_list,
 769                              l2_tn_filter,
 770                              entries);
 771                 rte_free(l2_tn_filter);
 772         }
 773
 774         return 0;
 775 }
 776
 777 static int txgbe_fdir_filter_init(struct rte_eth_dev *eth_dev)
 778 {
 779         struct txgbe_hw_fdir_info *fdir_info = TXGBE_DEV_FDIR(eth_dev);
 780         char fdir_hash_name[RTE_HASH_NAMESIZE];
 781         struct rte_hash_parameters fdir_hash_params = {
 782                 .name = fdir_hash_name,
 783                 .entries = TXGBE_MAX_FDIR_FILTER_NUM,
 784                 .key_len = sizeof(struct txgbe_atr_input),
 785                 .hash_func = rte_hash_crc,
 786                 .hash_func_init_val = 0,
 787                 .socket_id = rte_socket_id(),
 788         };
 789
 790         TAILQ_INIT(&fdir_info->fdir_list);
 791         snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
 792                  "fdir_%s", TDEV_NAME(eth_dev));
 793         fdir_info->hash_handle = rte_hash_create(&fdir_hash_params);
 794         if (!fdir_info->hash_handle) {
 795                 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
 796                 return -EINVAL;
 797         }
 798         fdir_info->hash_map = rte_zmalloc("txgbe",
 799                                           sizeof(struct txgbe_fdir_filter *) *
 800                                           TXGBE_MAX_FDIR_FILTER_NUM,
 801                                           0);
 802         if (!fdir_info->hash_map) {
 803                 PMD_INIT_LOG(ERR,
 804                              "Failed to allocate memory for fdir hash map!");
 805                 return -ENOMEM;
 806         }
 807         fdir_info->mask_added = FALSE;
 808
 809         return 0;
 810 }
 811
 812 static int txgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev)
 813 {
 814         struct txgbe_l2_tn_info *l2_tn_info = TXGBE_DEV_L2_TN(eth_dev);
 815         char l2_tn_hash_name[RTE_HASH_NAMESIZE];
 816         struct rte_hash_parameters l2_tn_hash_params = {
 817                 .name = l2_tn_hash_name,
 818                 .entries = TXGBE_MAX_L2_TN_FILTER_NUM,
 819                 .key_len = sizeof(struct txgbe_l2_tn_key),
 820                 .hash_func = rte_hash_crc,
 821                 .hash_func_init_val = 0,
 822                 .socket_id = rte_socket_id(),
 823         };
 824
 825         TAILQ_INIT(&l2_tn_info->l2_tn_list);
 826         snprintf(l2_tn_hash_name, RTE_HASH_NAMESIZE,
 827                  "l2_tn_%s", TDEV_NAME(eth_dev));
 828         l2_tn_info->hash_handle = rte_hash_create(&l2_tn_hash_params);
 829         if (!l2_tn_info->hash_handle) {
 830                 PMD_INIT_LOG(ERR, "Failed to create L2 TN hash table!");
 831                 return -EINVAL;
 832         }
 833         l2_tn_info->hash_map = rte_zmalloc("txgbe",
 834                                    sizeof(struct txgbe_l2_tn_filter *) *
 835                                    TXGBE_MAX_L2_TN_FILTER_NUM,
 836                                    0);
 837         if (!l2_tn_info->hash_map) {
 838                 PMD_INIT_LOG(ERR,
 839                         "Failed to allocate memory for L2 TN hash map!");
 840                 return -ENOMEM;
 841         }
 842         l2_tn_info->e_tag_en = FALSE;
 843         l2_tn_info->e_tag_fwd_en = FALSE;
 844         l2_tn_info->e_tag_ether_type = RTE_ETHER_TYPE_ETAG;
 845
 846         return 0;
 847 }
 848
 849 static int
 850 eth_txgbe_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
 851                 struct rte_pci_device *pci_dev)
 852 {
 853         struct rte_eth_dev *pf_ethdev;
 854         struct rte_eth_devargs eth_da;
 855         int retval;
 856
 857         if (pci_dev->device.devargs) {
 858                 retval = rte_eth_devargs_parse(pci_dev->device.devargs->args,
 859                                 &eth_da);
 860                 if (retval)
 861                         return retval;
 862         } else {
 863                 memset(&eth_da, 0, sizeof(eth_da));
 864         }
 865
 866         retval = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
 867                         sizeof(struct txgbe_adapter),
 868                         eth_dev_pci_specific_init, pci_dev,
 869                         eth_txgbe_dev_init, NULL);
 870
 871         if (retval || eth_da.nb_representor_ports < 1)
 872                 return retval;
 873
 874         pf_ethdev = rte_eth_dev_allocated(pci_dev->device.name);
 875         if (pf_ethdev == NULL)
 876                 return -ENODEV;
 877
 878         return 0;
 879 }
 880
 881 static int eth_txgbe_pci_remove(struct rte_pci_device *pci_dev)
 882 {
 883         struct rte_eth_dev *ethdev;
 884
 885         ethdev = rte_eth_dev_allocated(pci_dev->device.name);
 886         if (!ethdev)
 887                 return -ENODEV;
 888
 889         return rte_eth_dev_destroy(ethdev, eth_txgbe_dev_uninit);
 890 }
 891
 892 static struct rte_pci_driver rte_txgbe_pmd = {
 893         .id_table = pci_id_txgbe_map,
 894         .drv_flags = RTE_PCI_DRV_NEED_MAPPING |
 895                      RTE_PCI_DRV_INTR_LSC,
 896         .probe = eth_txgbe_pci_probe,
 897         .remove = eth_txgbe_pci_remove,
 898 };
 899
 900 static int
 901 txgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
 902 {
 903         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
 904         struct txgbe_vfta *shadow_vfta = TXGBE_DEV_VFTA(dev);
 905         uint32_t vfta;
 906         uint32_t vid_idx;
 907         uint32_t vid_bit;
 908
 909         vid_idx = (uint32_t)((vlan_id >> 5) & 0x7F);
 910         vid_bit = (uint32_t)(1 << (vlan_id & 0x1F));
 911         vfta = rd32(hw, TXGBE_VLANTBL(vid_idx));
 912         if (on)
 913                 vfta |= vid_bit;
 914         else
 915                 vfta &= ~vid_bit;
 916         wr32(hw, TXGBE_VLANTBL(vid_idx), vfta);
 917
 918         /* update local VFTA copy */
 919         shadow_vfta->vfta[vid_idx] = vfta;
 920
 921         return 0;
 922 }
 923
 924 static void
 925 txgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
 926 {
 927         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
 928         struct txgbe_rx_queue *rxq;
 929         bool restart;
 930         uint32_t rxcfg, rxbal, rxbah;
 931
 932         if (on)
 933                 txgbe_vlan_hw_strip_enable(dev, queue);
 934         else
 935                 txgbe_vlan_hw_strip_disable(dev, queue);
 936
 937         rxq = dev->data->rx_queues[queue];
 938         rxbal = rd32(hw, TXGBE_RXBAL(rxq->reg_idx));
 939         rxbah = rd32(hw, TXGBE_RXBAH(rxq->reg_idx));
 940         rxcfg = rd32(hw, TXGBE_RXCFG(rxq->reg_idx));
 941         if (rxq->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) {
 942                 restart = (rxcfg & TXGBE_RXCFG_ENA) &&
 943                         !(rxcfg & TXGBE_RXCFG_VLAN);
 944                 rxcfg |= TXGBE_RXCFG_VLAN;
 945         } else {
 946                 restart = (rxcfg & TXGBE_RXCFG_ENA) &&
 947                         (rxcfg & TXGBE_RXCFG_VLAN);
 948                 rxcfg &= ~TXGBE_RXCFG_VLAN;
 949         }
 950         rxcfg &= ~TXGBE_RXCFG_ENA;
 951
 952         if (restart) {
 953                 /* set vlan strip for ring */
 954                 txgbe_dev_rx_queue_stop(dev, queue);
 955                 wr32(hw, TXGBE_RXBAL(rxq->reg_idx), rxbal);
 956                 wr32(hw, TXGBE_RXBAH(rxq->reg_idx), rxbah);
 957                 wr32(hw, TXGBE_RXCFG(rxq->reg_idx), rxcfg);
 958                 txgbe_dev_rx_queue_start(dev, queue);
 959         }
 960 }
 961
 962 static int
 963 txgbe_vlan_tpid_set(struct rte_eth_dev *dev,
 964                     enum rte_vlan_type vlan_type,
 965                     uint16_t tpid)
 966 {
 967         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
 968         int ret = 0;
 969         uint32_t portctrl, vlan_ext, qinq;
 970
 971         portctrl = rd32(hw, TXGBE_PORTCTL);
 972
 973         vlan_ext = (portctrl & TXGBE_PORTCTL_VLANEXT);
 974         qinq = vlan_ext && (portctrl & TXGBE_PORTCTL_QINQ);
 975         switch (vlan_type) {
 976         case ETH_VLAN_TYPE_INNER:
 977                 if (vlan_ext) {
 978                         wr32m(hw, TXGBE_VLANCTL,
 979                                 TXGBE_VLANCTL_TPID_MASK,
 980                                 TXGBE_VLANCTL_TPID(tpid));
 981                         wr32m(hw, TXGBE_DMATXCTRL,
 982                                 TXGBE_DMATXCTRL_TPID_MASK,
 983                                 TXGBE_DMATXCTRL_TPID(tpid));
 984                 } else {
 985                         ret = -ENOTSUP;
 986                         PMD_DRV_LOG(ERR, "Inner type is not supported"
 987                                     " by single VLAN");
 988                 }
 989
 990                 if (qinq) {
 991                         wr32m(hw, TXGBE_TAGTPID(0),
 992                                 TXGBE_TAGTPID_LSB_MASK,
 993                                 TXGBE_TAGTPID_LSB(tpid));
 994                 }
 995                 break;
 996         case ETH_VLAN_TYPE_OUTER:
 997                 if (vlan_ext) {
 998                         /* Only the high 16-bits is valid */
 999                         wr32m(hw, TXGBE_EXTAG,
1000                                 TXGBE_EXTAG_VLAN_MASK,
1001                                 TXGBE_EXTAG_VLAN(tpid));
1002                 } else {
1003                         wr32m(hw, TXGBE_VLANCTL,
1004                                 TXGBE_VLANCTL_TPID_MASK,
1005                                 TXGBE_VLANCTL_TPID(tpid));
1006                         wr32m(hw, TXGBE_DMATXCTRL,
1007                                 TXGBE_DMATXCTRL_TPID_MASK,
1008                                 TXGBE_DMATXCTRL_TPID(tpid));
1009                 }
1010
1011                 if (qinq) {
1012                         wr32m(hw, TXGBE_TAGTPID(0),
1013                                 TXGBE_TAGTPID_MSB_MASK,
1014                                 TXGBE_TAGTPID_MSB(tpid));
1015                 }
1016                 break;
1017         default:
1018                 PMD_DRV_LOG(ERR, "Unsupported VLAN type %d", vlan_type);
1019                 return -EINVAL;
1020         }
1021
1022         return ret;
1023 }
1024
1025 void
1026 txgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1027 {
1028         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
1029         uint32_t vlnctrl;
1030
1031         PMD_INIT_FUNC_TRACE();
1032
1033         /* Filter Table Disable */
1034         vlnctrl = rd32(hw, TXGBE_VLANCTL);
1035         vlnctrl &= ~TXGBE_VLANCTL_VFE;
1036         wr32(hw, TXGBE_VLANCTL, vlnctrl);
1037 }
1038
1039 void
1040 txgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1041 {
1042         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
1043         struct txgbe_vfta *shadow_vfta = TXGBE_DEV_VFTA(dev);
1044         uint32_t vlnctrl;
1045         uint16_t i;
1046
1047         PMD_INIT_FUNC_TRACE();
1048
1049         /* Filter Table Enable */
1050         vlnctrl = rd32(hw, TXGBE_VLANCTL);
1051         vlnctrl &= ~TXGBE_VLANCTL_CFIENA;
1052         vlnctrl |= TXGBE_VLANCTL_VFE;
1053         wr32(hw, TXGBE_VLANCTL, vlnctrl);
1054
1055         /* write whatever is in local vfta copy */
1056         for (i = 0; i < TXGBE_VFTA_SIZE; i++)
1057                 wr32(hw, TXGBE_VLANTBL(i), shadow_vfta->vfta[i]);
1058 }
1059
1060 void
1061 txgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1062 {
1063         struct txgbe_hwstrip *hwstrip = TXGBE_DEV_HWSTRIP(dev);
1064         struct txgbe_rx_queue *rxq;
1065
1066         if (queue >= TXGBE_MAX_RX_QUEUE_NUM)
1067                 return;
1068
1069         if (on)
1070                 TXGBE_SET_HWSTRIP(hwstrip, queue);
1071         else
1072                 TXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1073
1074         if (queue >= dev->data->nb_rx_queues)
1075                 return;
1076
1077         rxq = dev->data->rx_queues[queue];
1078
1079         if (on) {
1080                 rxq->vlan_flags = PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
1081                 rxq->offloads |= DEV_RX_OFFLOAD_VLAN_STRIP;
1082         } else {
1083                 rxq->vlan_flags = PKT_RX_VLAN;
1084                 rxq->offloads &= ~DEV_RX_OFFLOAD_VLAN_STRIP;
1085         }
1086 }
1087
1088 static void
1089 txgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
1090 {
1091         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
1092         uint32_t ctrl;
1093
1094         PMD_INIT_FUNC_TRACE();
1095
1096         ctrl = rd32(hw, TXGBE_RXCFG(queue));
1097         ctrl &= ~TXGBE_RXCFG_VLAN;
1098         wr32(hw, TXGBE_RXCFG(queue), ctrl);
1099
1100         /* record those setting for HW strip per queue */
1101         txgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
1102 }
1103
1104 static void
1105 txgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
1106 {
1107         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
1108         uint32_t ctrl;
1109
1110         PMD_INIT_FUNC_TRACE();
1111
1112         ctrl = rd32(hw, TXGBE_RXCFG(queue));
1113         ctrl |= TXGBE_RXCFG_VLAN;
1114         wr32(hw, TXGBE_RXCFG(queue), ctrl);
1115
1116         /* record those setting for HW strip per queue */
1117         txgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
1118 }
1119
1120 static void
1121 txgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
1122 {
1123         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
1124         uint32_t ctrl;
1125
1126         PMD_INIT_FUNC_TRACE();
1127
1128         ctrl = rd32(hw, TXGBE_PORTCTL);
1129         ctrl &= ~TXGBE_PORTCTL_VLANEXT;
1130         ctrl &= ~TXGBE_PORTCTL_QINQ;
1131         wr32(hw, TXGBE_PORTCTL, ctrl);
1132 }
1133
1134 static void
1135 txgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
1136 {
1137         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
1138         struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
1139         struct rte_eth_txmode *txmode = &dev->data->dev_conf.txmode;
1140         uint32_t ctrl;
1141
1142         PMD_INIT_FUNC_TRACE();
1143
1144         ctrl  = rd32(hw, TXGBE_PORTCTL);
1145         ctrl |= TXGBE_PORTCTL_VLANEXT;
1146         if (rxmode->offloads & DEV_RX_OFFLOAD_QINQ_STRIP ||
1147             txmode->offloads & DEV_TX_OFFLOAD_QINQ_INSERT)
1148                 ctrl |= TXGBE_PORTCTL_QINQ;
1149         wr32(hw, TXGBE_PORTCTL, ctrl);
1150 }
1151
1152 void
1153 txgbe_vlan_hw_strip_config(struct rte_eth_dev *dev)
1154 {
1155         struct txgbe_rx_queue *rxq;
1156         uint16_t i;
1157
1158         PMD_INIT_FUNC_TRACE();
1159
1160         for (i = 0; i < dev->data->nb_rx_queues; i++) {
1161                 rxq = dev->data->rx_queues[i];
1162
1163                 if (rxq->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1164                         txgbe_vlan_strip_queue_set(dev, i, 1);
1165                 else
1166                         txgbe_vlan_strip_queue_set(dev, i, 0);
1167         }
1168 }
1169
1170 void
1171 txgbe_config_vlan_strip_on_all_queues(struct rte_eth_dev *dev, int mask)
1172 {
1173         uint16_t i;
1174         struct rte_eth_rxmode *rxmode;
1175         struct txgbe_rx_queue *rxq;
1176
1177         if (mask & ETH_VLAN_STRIP_MASK) {
1178                 rxmode = &dev->data->dev_conf.rxmode;
1179                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1180                         for (i = 0; i < dev->data->nb_rx_queues; i++) {
1181                                 rxq = dev->data->rx_queues[i];
1182                                 rxq->offloads |= DEV_RX_OFFLOAD_VLAN_STRIP;
1183                         }
1184                 else
1185                         for (i = 0; i < dev->data->nb_rx_queues; i++) {
1186                                 rxq = dev->data->rx_queues[i];
1187                                 rxq->offloads &= ~DEV_RX_OFFLOAD_VLAN_STRIP;
1188                         }
1189         }
1190 }
1191
1192 static int
1193 txgbe_vlan_offload_config(struct rte_eth_dev *dev, int mask)
1194 {
1195         struct rte_eth_rxmode *rxmode;
1196         rxmode = &dev->data->dev_conf.rxmode;
1197
1198         if (mask & ETH_VLAN_STRIP_MASK)
1199                 txgbe_vlan_hw_strip_config(dev);
1200
1201         if (mask & ETH_VLAN_FILTER_MASK) {
1202                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
1203                         txgbe_vlan_hw_filter_enable(dev);
1204                 else
1205                         txgbe_vlan_hw_filter_disable(dev);
1206         }
1207
1208         if (mask & ETH_VLAN_EXTEND_MASK) {
1209                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
1210                         txgbe_vlan_hw_extend_enable(dev);
1211                 else
1212                         txgbe_vlan_hw_extend_disable(dev);
1213         }
1214
1215         return 0;
1216 }
1217
1218 static int
1219 txgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1220 {
1221         txgbe_config_vlan_strip_on_all_queues(dev, mask);
1222
1223         txgbe_vlan_offload_config(dev, mask);
1224
1225         return 0;
1226 }
1227
1228 static void
1229 txgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1230 {
1231         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
1232         /* VLNCTL: enable vlan filtering and allow all vlan tags through */
1233         uint32_t vlanctrl = rd32(hw, TXGBE_VLANCTL);
1234
1235         vlanctrl |= TXGBE_VLANCTL_VFE; /* enable vlan filters */
1236         wr32(hw, TXGBE_VLANCTL, vlanctrl);
1237 }
1238
1239 static int
1240 txgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q)
1241 {
1242         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1243
1244         switch (nb_rx_q) {
1245         case 1:
1246         case 2:
1247                 RTE_ETH_DEV_SRIOV(dev).active = ETH_64_POOLS;
1248                 break;
1249         case 4:
1250                 RTE_ETH_DEV_SRIOV(dev).active = ETH_32_POOLS;
1251                 break;
1252         default:
1253                 return -EINVAL;
1254         }
1255
1256         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool =
1257                 TXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
1258         RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx =
1259                 pci_dev->max_vfs * RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
1260         return 0;
1261 }
1262
1263 static int
1264 txgbe_check_mq_mode(struct rte_eth_dev *dev)
1265 {
1266         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
1267         uint16_t nb_rx_q = dev->data->nb_rx_queues;
1268         uint16_t nb_tx_q = dev->data->nb_tx_queues;
1269
1270         if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
1271                 /* check multi-queue mode */
1272                 switch (dev_conf->rxmode.mq_mode) {
1273                 case ETH_MQ_RX_VMDQ_DCB:
1274                         PMD_INIT_LOG(INFO, "ETH_MQ_RX_VMDQ_DCB mode supported in SRIOV");
1275                         break;
1276                 case ETH_MQ_RX_VMDQ_DCB_RSS:
1277                         /* DCB/RSS VMDQ in SRIOV mode, not implement yet */
1278                         PMD_INIT_LOG(ERR, "SRIOV active,"
1279                                         " unsupported mq_mode rx %d.",
1280                                         dev_conf->rxmode.mq_mode);
1281                         return -EINVAL;
1282                 case ETH_MQ_RX_RSS:
1283                 case ETH_MQ_RX_VMDQ_RSS:
1284                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_RSS;
1285                         if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)
1286                                 if (txgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) {
1287                                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1288                                                 " invalid queue number"
1289                                                 " for VMDQ RSS, allowed"
1290                                                 " value are 1, 2 or 4.");
1291                                         return -EINVAL;
1292                                 }
1293                         break;
1294                 case ETH_MQ_RX_VMDQ_ONLY:
1295                 case ETH_MQ_RX_NONE:
1296                         /* if nothing mq mode configure, use default scheme */
1297                         dev->data->dev_conf.rxmode.mq_mode =
1298                                 ETH_MQ_RX_VMDQ_ONLY;
1299                         break;
1300                 default: /* ETH_MQ_RX_DCB, ETH_MQ_RX_DCB_RSS or ETH_MQ_TX_DCB*/
1301                         /* SRIOV only works in VMDq enable mode */
1302                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1303                                         " wrong mq_mode rx %d.",
1304                                         dev_conf->rxmode.mq_mode);
1305                         return -EINVAL;
1306                 }
1307
1308                 switch (dev_conf->txmode.mq_mode) {
1309                 case ETH_MQ_TX_VMDQ_DCB:
1310                         PMD_INIT_LOG(INFO, "ETH_MQ_TX_VMDQ_DCB mode supported in SRIOV");
1311                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_DCB;
1312                         break;
1313                 default: /* ETH_MQ_TX_VMDQ_ONLY or ETH_MQ_TX_NONE */
1314                         dev->data->dev_conf.txmode.mq_mode =
1315                                 ETH_MQ_TX_VMDQ_ONLY;
1316                         break;
1317                 }
1318
1319                 /* check valid queue number */
1320                 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) ||
1321                     (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) {
1322                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1323                                         " nb_rx_q=%d nb_tx_q=%d queue number"
1324                                         " must be less than or equal to %d.",
1325                                         nb_rx_q, nb_tx_q,
1326                                         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool);
1327                         return -EINVAL;
1328                 }
1329         } else {
1330                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
1331                         PMD_INIT_LOG(ERR, "VMDQ+DCB+RSS mq_mode is"
1332                                           " not supported.");
1333                         return -EINVAL;
1334                 }
1335                 /* check configuration for vmdb+dcb mode */
1336                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB) {
1337                         const struct rte_eth_vmdq_dcb_conf *conf;
1338
1339                         if (nb_rx_q != TXGBE_VMDQ_DCB_NB_QUEUES) {
1340                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.",
1341                                                 TXGBE_VMDQ_DCB_NB_QUEUES);
1342                                 return -EINVAL;
1343                         }
1344                         conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf;
1345                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
1346                                conf->nb_queue_pools == ETH_32_POOLS)) {
1347                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
1348                                                 " nb_queue_pools must be %d or %d.",
1349                                                 ETH_16_POOLS, ETH_32_POOLS);
1350                                 return -EINVAL;
1351                         }
1352                 }
1353                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) {
1354                         const struct rte_eth_vmdq_dcb_tx_conf *conf;
1355
1356                         if (nb_tx_q != TXGBE_VMDQ_DCB_NB_QUEUES) {
1357                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d",
1358                                                  TXGBE_VMDQ_DCB_NB_QUEUES);
1359                                 return -EINVAL;
1360                         }
1361                         conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf;
1362                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
1363                                conf->nb_queue_pools == ETH_32_POOLS)) {
1364                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
1365                                                 " nb_queue_pools != %d and"
1366                                                 " nb_queue_pools != %d.",
1367                                                 ETH_16_POOLS, ETH_32_POOLS);
1368                                 return -EINVAL;
1369                         }
1370                 }
1371
1372                 /* For DCB mode check our configuration before we go further */
1373                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_DCB) {
1374                         const struct rte_eth_dcb_rx_conf *conf;
1375
1376                         conf = &dev_conf->rx_adv_conf.dcb_rx_conf;
1377                         if (!(conf->nb_tcs == ETH_4_TCS ||
1378                                conf->nb_tcs == ETH_8_TCS)) {
1379                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
1380                                                 " and nb_tcs != %d.",
1381                                                 ETH_4_TCS, ETH_8_TCS);
1382                                 return -EINVAL;
1383                         }
1384                 }
1385
1386                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_DCB) {
1387                         const struct rte_eth_dcb_tx_conf *conf;
1388
1389                         conf = &dev_conf->tx_adv_conf.dcb_tx_conf;
1390                         if (!(conf->nb_tcs == ETH_4_TCS ||
1391                                conf->nb_tcs == ETH_8_TCS)) {
1392                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
1393                                                 " and nb_tcs != %d.",
1394                                                 ETH_4_TCS, ETH_8_TCS);
1395                                 return -EINVAL;
1396                         }
1397                 }
1398         }
1399         return 0;
1400 }
1401
1402 static int
1403 txgbe_dev_configure(struct rte_eth_dev *dev)
1404 {
1405         struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);
1406         struct txgbe_adapter *adapter = TXGBE_DEV_ADAPTER(dev);
1407         int ret;
1408
1409         PMD_INIT_FUNC_TRACE();
1410
1411         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
1412                 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
1413
1414         /* multiple queue mode checking */
1415         ret  = txgbe_check_mq_mode(dev);
1416         if (ret != 0) {
1417                 PMD_DRV_LOG(ERR, "txgbe_check_mq_mode fails with %d.",
1418                             ret);
1419                 return ret;
1420         }
1421
1422         /* set flag to update link status after init */
1423         intr->flags |= TXGBE_FLAG_NEED_LINK_UPDATE;
1424
1425         /*
1426          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
1427          * allocation Rx preconditions we will reset it.
1428          */
1429         adapter->rx_bulk_alloc_allowed = true;
1430
1431         return 0;
1432 }
1433
1434 static void
1435 txgbe_dev_phy_intr_setup(struct rte_eth_dev *dev)
1436 {
1437         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
1438         struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);
1439         uint32_t gpie;
1440
1441         gpie = rd32(hw, TXGBE_GPIOINTEN);
1442         gpie |= TXGBE_GPIOBIT_6;
1443         wr32(hw, TXGBE_GPIOINTEN, gpie);
1444         intr->mask_misc |= TXGBE_ICRMISC_GPIO;
1445 }
1446
1447 int
1448 txgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
1449                         uint16_t tx_rate, uint64_t q_msk)
1450 {
1451         struct txgbe_hw *hw;
1452         struct txgbe_vf_info *vfinfo;
1453         struct rte_eth_link link;
1454         uint8_t  nb_q_per_pool;
1455         uint32_t queue_stride;
1456         uint32_t queue_idx, idx = 0, vf_idx;
1457         uint32_t queue_end;
1458         uint16_t total_rate = 0;
1459         struct rte_pci_device *pci_dev;
1460         int ret;
1461
1462         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1463         ret = rte_eth_link_get_nowait(dev->data->port_id, &link);
1464         if (ret < 0)
1465                 return ret;
1466
1467         if (vf >= pci_dev->max_vfs)
1468                 return -EINVAL;
1469
1470         if (tx_rate > link.link_speed)
1471                 return -EINVAL;
1472
1473         if (q_msk == 0)
1474                 return 0;
1475
1476         hw = TXGBE_DEV_HW(dev);
1477         vfinfo = *(TXGBE_DEV_VFDATA(dev));
1478         nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
1479         queue_stride = TXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
1480         queue_idx = vf * queue_stride;
1481         queue_end = queue_idx + nb_q_per_pool - 1;
1482         if (queue_end >= hw->mac.max_tx_queues)
1483                 return -EINVAL;
1484
1485         if (vfinfo) {
1486                 for (vf_idx = 0; vf_idx < pci_dev->max_vfs; vf_idx++) {
1487                         if (vf_idx == vf)
1488                                 continue;
1489                         for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
1490                                 idx++)
1491                                 total_rate += vfinfo[vf_idx].tx_rate[idx];
1492                 }
1493         } else {
1494                 return -EINVAL;
1495         }
1496
1497         /* Store tx_rate for this vf. */
1498         for (idx = 0; idx < nb_q_per_pool; idx++) {
1499                 if (((uint64_t)0x1 << idx) & q_msk) {
1500                         if (vfinfo[vf].tx_rate[idx] != tx_rate)
1501                                 vfinfo[vf].tx_rate[idx] = tx_rate;
1502                         total_rate += tx_rate;
1503                 }
1504         }
1505
1506         if (total_rate > dev->data->dev_link.link_speed) {
1507                 /* Reset stored TX rate of the VF if it causes exceed
1508                  * link speed.
1509                  */
1510                 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
1511                 return -EINVAL;
1512         }
1513
1514         /* Set ARBTXRATE of each queue/pool for vf X  */
1515         for (; queue_idx <= queue_end; queue_idx++) {
1516                 if (0x1 & q_msk)
1517                         txgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
1518                 q_msk = q_msk >> 1;
1519         }
1520
1521         return 0;
1522 }
1523
1524 /*
1525  * Configure device link speed and setup link.
1526  * It returns 0 on success.
1527  */
1528 static int
1529 txgbe_dev_start(struct rte_eth_dev *dev)
1530 {
1531         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
1532         struct txgbe_hw_stats *hw_stats = TXGBE_DEV_STATS(dev);
1533         struct txgbe_vf_info *vfinfo = *TXGBE_DEV_VFDATA(dev);
1534         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1535         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1536         uint32_t intr_vector = 0;
1537         int err;
1538         bool link_up = false, negotiate = 0;
1539         uint32_t speed = 0;
1540         uint32_t allowed_speeds = 0;
1541         int mask = 0;
1542         int status;
1543         uint16_t vf, idx;
1544         uint32_t *link_speeds;
1545
1546         PMD_INIT_FUNC_TRACE();
1547
1548         /* TXGBE devices don't support:
1549          *    - half duplex (checked afterwards for valid speeds)
1550          *    - fixed speed: TODO implement
1551          */
1552         if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
1553                 PMD_INIT_LOG(ERR,
1554                 "Invalid link_speeds for port %u, fix speed not supported",
1555                                 dev->data->port_id);
1556                 return -EINVAL;
1557         }
1558
1559         /* Stop the link setup handler before resetting the HW. */
1560         rte_eal_alarm_cancel(txgbe_dev_setup_link_alarm_handler, dev);
1561
1562         /* disable uio/vfio intr/eventfd mapping */
1563         rte_intr_disable(intr_handle);
1564
1565         /* stop adapter */
1566         hw->adapter_stopped = 0;
1567         txgbe_stop_hw(hw);
1568
1569         /* reinitialize adapter
1570          * this calls reset and start
1571          */
1572         hw->nb_rx_queues = dev->data->nb_rx_queues;
1573         hw->nb_tx_queues = dev->data->nb_tx_queues;
1574         status = txgbe_pf_reset_hw(hw);
1575         if (status != 0)
1576                 return -1;
1577         hw->mac.start_hw(hw);
1578         hw->mac.get_link_status = true;
1579
1580         /* configure PF module if SRIOV enabled */
1581         txgbe_pf_host_configure(dev);
1582
1583         txgbe_dev_phy_intr_setup(dev);
1584
1585         /* check and configure queue intr-vector mapping */
1586         if ((rte_intr_cap_multiple(intr_handle) ||
1587              !RTE_ETH_DEV_SRIOV(dev).active) &&
1588             dev->data->dev_conf.intr_conf.rxq != 0) {
1589                 intr_vector = dev->data->nb_rx_queues;
1590                 if (rte_intr_efd_enable(intr_handle, intr_vector))
1591                         return -1;
1592         }
1593
1594         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1595                 intr_handle->intr_vec =
1596                         rte_zmalloc("intr_vec",
1597                                     dev->data->nb_rx_queues * sizeof(int), 0);
1598                 if (intr_handle->intr_vec == NULL) {
1599                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
1600                                      " intr_vec", dev->data->nb_rx_queues);
1601                         return -ENOMEM;
1602                 }
1603         }
1604
1605         /* confiugre msix for sleep until rx interrupt */
1606         txgbe_configure_msix(dev);
1607
1608         /* initialize transmission unit */
1609         txgbe_dev_tx_init(dev);
1610
1611         /* This can fail when allocating mbufs for descriptor rings */
1612         err = txgbe_dev_rx_init(dev);
1613         if (err) {
1614                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
1615                 goto error;
1616         }
1617
1618         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
1619                 ETH_VLAN_EXTEND_MASK;
1620         err = txgbe_vlan_offload_config(dev, mask);
1621         if (err) {
1622                 PMD_INIT_LOG(ERR, "Unable to set VLAN offload");
1623                 goto error;
1624         }
1625
1626         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1627                 /* Enable vlan filtering for VMDq */
1628                 txgbe_vmdq_vlan_hw_filter_enable(dev);
1629         }
1630
1631         /* Configure DCB hw */
1632         txgbe_configure_pb(dev);
1633         txgbe_configure_port(dev);
1634         txgbe_configure_dcb(dev);
1635
1636         /* Restore vf rate limit */
1637         if (vfinfo != NULL) {
1638                 for (vf = 0; vf < pci_dev->max_vfs; vf++)
1639                         for (idx = 0; idx < TXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
1640                                 if (vfinfo[vf].tx_rate[idx] != 0)
1641                                         txgbe_set_vf_rate_limit(dev, vf,
1642                                                 vfinfo[vf].tx_rate[idx],
1643                                                 1 << idx);
1644         }
1645
1646         err = txgbe_dev_rxtx_start(dev);
1647         if (err < 0) {
1648                 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
1649                 goto error;
1650         }
1651
1652         /* Skip link setup if loopback mode is enabled. */
1653         if (hw->mac.type == txgbe_mac_raptor &&
1654             dev->data->dev_conf.lpbk_mode)
1655                 goto skip_link_setup;
1656
1657         if (txgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
1658                 err = hw->mac.setup_sfp(hw);
1659                 if (err)
1660                         goto error;
1661         }
1662
1663         if (hw->phy.media_type == txgbe_media_type_copper) {
1664                 /* Turn on the copper */
1665                 hw->phy.set_phy_power(hw, true);
1666         } else {
1667                 /* Turn on the laser */
1668                 hw->mac.enable_tx_laser(hw);
1669         }
1670
1671         err = hw->mac.check_link(hw, &speed, &link_up, 0);
1672         if (err)
1673                 goto error;
1674         dev->data->dev_link.link_status = link_up;
1675
1676         err = hw->mac.get_link_capabilities(hw, &speed, &negotiate);
1677         if (err)
1678                 goto error;
1679
1680         allowed_speeds = ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
1681                         ETH_LINK_SPEED_10G;
1682
1683         link_speeds = &dev->data->dev_conf.link_speeds;
1684         if (*link_speeds & ~allowed_speeds) {
1685                 PMD_INIT_LOG(ERR, "Invalid link setting");
1686                 goto error;
1687         }
1688
1689         speed = 0x0;
1690         if (*link_speeds == ETH_LINK_SPEED_AUTONEG) {
1691                 speed = (TXGBE_LINK_SPEED_100M_FULL |
1692                          TXGBE_LINK_SPEED_1GB_FULL |
1693                          TXGBE_LINK_SPEED_10GB_FULL);
1694         } else {
1695                 if (*link_speeds & ETH_LINK_SPEED_10G)
1696                         speed |= TXGBE_LINK_SPEED_10GB_FULL;
1697                 if (*link_speeds & ETH_LINK_SPEED_5G)
1698                         speed |= TXGBE_LINK_SPEED_5GB_FULL;
1699                 if (*link_speeds & ETH_LINK_SPEED_2_5G)
1700                         speed |= TXGBE_LINK_SPEED_2_5GB_FULL;
1701                 if (*link_speeds & ETH_LINK_SPEED_1G)
1702                         speed |= TXGBE_LINK_SPEED_1GB_FULL;
1703                 if (*link_speeds & ETH_LINK_SPEED_100M)
1704                         speed |= TXGBE_LINK_SPEED_100M_FULL;
1705         }
1706
1707         err = hw->mac.setup_link(hw, speed, link_up);
1708         if (err)
1709                 goto error;
1710
1711 skip_link_setup:
1712
1713         if (rte_intr_allow_others(intr_handle)) {
1714                 /* check if lsc interrupt is enabled */
1715                 if (dev->data->dev_conf.intr_conf.lsc != 0)
1716                         txgbe_dev_lsc_interrupt_setup(dev, TRUE);
1717                 else
1718                         txgbe_dev_lsc_interrupt_setup(dev, FALSE);
1719                 txgbe_dev_macsec_interrupt_setup(dev);
1720                 txgbe_set_ivar_map(hw, -1, 1, TXGBE_MISC_VEC_ID);
1721         } else {
1722                 rte_intr_callback_unregister(intr_handle,
1723                                              txgbe_dev_interrupt_handler, dev);
1724                 if (dev->data->dev_conf.intr_conf.lsc != 0)
1725                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
1726                                      " no intr multiplex");
1727         }
1728
1729         /* check if rxq interrupt is enabled */
1730         if (dev->data->dev_conf.intr_conf.rxq != 0 &&
1731             rte_intr_dp_is_en(intr_handle))
1732                 txgbe_dev_rxq_interrupt_setup(dev);
1733
1734         /* enable uio/vfio intr/eventfd mapping */
1735         rte_intr_enable(intr_handle);
1736
1737         /* resume enabled intr since hw reset */
1738         txgbe_enable_intr(dev);
1739         txgbe_l2_tunnel_conf(dev);
1740         txgbe_filter_restore(dev);
1741
1742         /*
1743          * Update link status right before return, because it may
1744          * start link configuration process in a separate thread.
1745          */
1746         txgbe_dev_link_update(dev, 0);
1747
1748         wr32m(hw, TXGBE_LEDCTL, 0xFFFFFFFF, TXGBE_LEDCTL_ORD_MASK);
1749
1750         txgbe_read_stats_registers(hw, hw_stats);
1751         hw->offset_loaded = 1;
1752
1753         return 0;
1754
1755 error:
1756         PMD_INIT_LOG(ERR, "failure in dev start: %d", err);
1757         txgbe_dev_clear_queues(dev);
1758         return -EIO;
1759 }
1760
1761 /*
1762  * Stop device: disable rx and tx functions to allow for reconfiguring.
1763  */
1764 static int
1765 txgbe_dev_stop(struct rte_eth_dev *dev)
1766 {
1767         struct rte_eth_link link;
1768         struct txgbe_adapter *adapter = TXGBE_DEV_ADAPTER(dev);
1769         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
1770         struct txgbe_vf_info *vfinfo = *TXGBE_DEV_VFDATA(dev);
1771         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1772         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1773         int vf;
1774
1775         if (hw->adapter_stopped)
1776                 return 0;
1777
1778         PMD_INIT_FUNC_TRACE();
1779
1780         rte_eal_alarm_cancel(txgbe_dev_setup_link_alarm_handler, dev);
1781
1782         /* disable interrupts */
1783         txgbe_disable_intr(hw);
1784
1785         /* reset the NIC */
1786         txgbe_pf_reset_hw(hw);
1787         hw->adapter_stopped = 0;
1788
1789         /* stop adapter */
1790         txgbe_stop_hw(hw);
1791
1792         for (vf = 0; vfinfo != NULL && vf < pci_dev->max_vfs; vf++)
1793                 vfinfo[vf].clear_to_send = false;
1794
1795         if (hw->phy.media_type == txgbe_media_type_copper) {
1796                 /* Turn off the copper */
1797                 hw->phy.set_phy_power(hw, false);
1798         } else {
1799                 /* Turn off the laser */
1800                 hw->mac.disable_tx_laser(hw);
1801         }
1802
1803         txgbe_dev_clear_queues(dev);
1804
1805         /* Clear stored conf */
1806         dev->data->scattered_rx = 0;
1807         dev->data->lro = 0;
1808
1809         /* Clear recorded link status */
1810         memset(&link, 0, sizeof(link));
1811         rte_eth_linkstatus_set(dev, &link);
1812
1813         if (!rte_intr_allow_others(intr_handle))
1814                 /* resume to the default handler */
1815                 rte_intr_callback_register(intr_handle,
1816                                            txgbe_dev_interrupt_handler,
1817                                            (void *)dev);
1818
1819         /* Clean datapath event and queue/vec mapping */
1820         rte_intr_efd_disable(intr_handle);
1821         if (intr_handle->intr_vec != NULL) {
1822                 rte_free(intr_handle->intr_vec);
1823                 intr_handle->intr_vec = NULL;
1824         }
1825
1826         adapter->rss_reta_updated = 0;
1827         wr32m(hw, TXGBE_LEDCTL, 0xFFFFFFFF, TXGBE_LEDCTL_SEL_MASK);
1828
1829         hw->adapter_stopped = true;
1830         dev->data->dev_started = 0;
1831
1832         return 0;
1833 }
1834
1835 /*
1836  * Set device link up: enable tx.
1837  */
1838 static int
1839 txgbe_dev_set_link_up(struct rte_eth_dev *dev)
1840 {
1841         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
1842
1843         if (hw->phy.media_type == txgbe_media_type_copper) {
1844                 /* Turn on the copper */
1845                 hw->phy.set_phy_power(hw, true);
1846         } else {
1847                 /* Turn on the laser */
1848                 hw->mac.enable_tx_laser(hw);
1849                 txgbe_dev_link_update(dev, 0);
1850         }
1851
1852         return 0;
1853 }
1854
1855 /*
1856  * Set device link down: disable tx.
1857  */
1858 static int
1859 txgbe_dev_set_link_down(struct rte_eth_dev *dev)
1860 {
1861         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
1862
1863         if (hw->phy.media_type == txgbe_media_type_copper) {
1864                 /* Turn off the copper */
1865                 hw->phy.set_phy_power(hw, false);
1866         } else {
1867                 /* Turn off the laser */
1868                 hw->mac.disable_tx_laser(hw);
1869                 txgbe_dev_link_update(dev, 0);
1870         }
1871
1872         return 0;
1873 }
1874
1875 /*
1876  * Reset and stop device.
1877  */
1878 static int
1879 txgbe_dev_close(struct rte_eth_dev *dev)
1880 {
1881         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
1882         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1883         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1884         int retries = 0;
1885         int ret;
1886
1887         PMD_INIT_FUNC_TRACE();
1888
1889         txgbe_pf_reset_hw(hw);
1890
1891         ret = txgbe_dev_stop(dev);
1892
1893         txgbe_dev_free_queues(dev);
1894
1895         /* reprogram the RAR[0] in case user changed it. */
1896         txgbe_set_rar(hw, 0, hw->mac.addr, 0, true);
1897
1898         /* Unlock any pending hardware semaphore */
1899         txgbe_swfw_lock_reset(hw);
1900
1901         /* disable uio intr before callback unregister */
1902         rte_intr_disable(intr_handle);
1903
1904         do {
1905                 ret = rte_intr_callback_unregister(intr_handle,
1906                                 txgbe_dev_interrupt_handler, dev);
1907                 if (ret >= 0 || ret == -ENOENT) {
1908                         break;
1909                 } else if (ret != -EAGAIN) {
1910                         PMD_INIT_LOG(ERR,
1911                                 "intr callback unregister failed: %d",
1912                                 ret);
1913                 }
1914                 rte_delay_ms(100);
1915         } while (retries++ < (10 + TXGBE_LINK_UP_TIME));
1916
1917         /* cancel the delay handler before remove dev */
1918         rte_eal_alarm_cancel(txgbe_dev_interrupt_delayed_handler, dev);
1919
1920         /* uninitialize PF if max_vfs not zero */
1921         txgbe_pf_host_uninit(dev);
1922
1923         rte_free(dev->data->mac_addrs);
1924         dev->data->mac_addrs = NULL;
1925
1926         rte_free(dev->data->hash_mac_addrs);
1927         dev->data->hash_mac_addrs = NULL;
1928
1929         /* remove all the fdir filters & hash */
1930         txgbe_fdir_filter_uninit(dev);
1931
1932         /* remove all the L2 tunnel filters & hash */
1933         txgbe_l2_tn_filter_uninit(dev);
1934
1935         /* Remove all ntuple filters of the device */
1936         txgbe_ntuple_filter_uninit(dev);
1937
1938         return ret;
1939 }
1940
1941 /*
1942  * Reset PF device.
1943  */
1944 static int
1945 txgbe_dev_reset(struct rte_eth_dev *dev)
1946 {
1947         int ret;
1948
1949         /* When a DPDK PMD PF begin to reset PF port, it should notify all
1950          * its VF to make them align with it. The detailed notification
1951          * mechanism is PMD specific. As to txgbe PF, it is rather complex.
1952          * To avoid unexpected behavior in VF, currently reset of PF with
1953          * SR-IOV activation is not supported. It might be supported later.
1954          */
1955         if (dev->data->sriov.active)
1956                 return -ENOTSUP;
1957
1958         ret = eth_txgbe_dev_uninit(dev);
1959         if (ret)
1960                 return ret;
1961
1962         ret = eth_txgbe_dev_init(dev, NULL);
1963
1964         return ret;
1965 }
1966
1967 #define UPDATE_QP_COUNTER_32bit(reg, last_counter, counter)     \
1968         {                                                       \
1969                 uint32_t current_counter = rd32(hw, reg);       \
1970                 if (current_counter < last_counter)             \
1971                         current_counter += 0x100000000LL;       \
1972                 if (!hw->offset_loaded)                         \
1973                         last_counter = current_counter;         \
1974                 counter = current_counter - last_counter;       \
1975                 counter &= 0xFFFFFFFFLL;                        \
1976         }
1977
1978 #define UPDATE_QP_COUNTER_36bit(reg_lsb, reg_msb, last_counter, counter) \
1979         {                                                                \
1980                 uint64_t current_counter_lsb = rd32(hw, reg_lsb);        \
1981                 uint64_t current_counter_msb = rd32(hw, reg_msb);        \
1982                 uint64_t current_counter = (current_counter_msb << 32) | \
1983                         current_counter_lsb;                             \
1984                 if (current_counter < last_counter)                      \
1985                         current_counter += 0x1000000000LL;               \
1986                 if (!hw->offset_loaded)                                  \
1987                         last_counter = current_counter;                  \
1988                 counter = current_counter - last_counter;                \
1989                 counter &= 0xFFFFFFFFFLL;                                \
1990         }
1991
1992 void
1993 txgbe_read_stats_registers(struct txgbe_hw *hw,
1994                            struct txgbe_hw_stats *hw_stats)
1995 {
1996         unsigned int i;
1997
1998         /* QP Stats */
1999         for (i = 0; i < hw->nb_rx_queues; i++) {
2000                 UPDATE_QP_COUNTER_32bit(TXGBE_QPRXPKT(i),
2001                         hw->qp_last[i].rx_qp_packets,
2002                         hw_stats->qp[i].rx_qp_packets);
2003                 UPDATE_QP_COUNTER_36bit(TXGBE_QPRXOCTL(i), TXGBE_QPRXOCTH(i),
2004                         hw->qp_last[i].rx_qp_bytes,
2005                         hw_stats->qp[i].rx_qp_bytes);
2006                 UPDATE_QP_COUNTER_32bit(TXGBE_QPRXMPKT(i),
2007                         hw->qp_last[i].rx_qp_mc_packets,
2008                         hw_stats->qp[i].rx_qp_mc_packets);
2009         }
2010
2011         for (i = 0; i < hw->nb_tx_queues; i++) {
2012                 UPDATE_QP_COUNTER_32bit(TXGBE_QPTXPKT(i),
2013                         hw->qp_last[i].tx_qp_packets,
2014                         hw_stats->qp[i].tx_qp_packets);
2015                 UPDATE_QP_COUNTER_36bit(TXGBE_QPTXOCTL(i), TXGBE_QPTXOCTH(i),
2016                         hw->qp_last[i].tx_qp_bytes,
2017                         hw_stats->qp[i].tx_qp_bytes);
2018         }
2019         /* PB Stats */
2020         for (i = 0; i < TXGBE_MAX_UP; i++) {
2021                 hw_stats->up[i].rx_up_xon_packets +=
2022                                 rd32(hw, TXGBE_PBRXUPXON(i));
2023                 hw_stats->up[i].rx_up_xoff_packets +=
2024                                 rd32(hw, TXGBE_PBRXUPXOFF(i));
2025                 hw_stats->up[i].tx_up_xon_packets +=
2026                                 rd32(hw, TXGBE_PBTXUPXON(i));
2027                 hw_stats->up[i].tx_up_xoff_packets +=
2028                                 rd32(hw, TXGBE_PBTXUPXOFF(i));
2029                 hw_stats->up[i].tx_up_xon2off_packets +=
2030                                 rd32(hw, TXGBE_PBTXUPOFF(i));
2031                 hw_stats->up[i].rx_up_dropped +=
2032                                 rd32(hw, TXGBE_PBRXMISS(i));
2033         }
2034         hw_stats->rx_xon_packets += rd32(hw, TXGBE_PBRXLNKXON);
2035         hw_stats->rx_xoff_packets += rd32(hw, TXGBE_PBRXLNKXOFF);
2036         hw_stats->tx_xon_packets += rd32(hw, TXGBE_PBTXLNKXON);
2037         hw_stats->tx_xoff_packets += rd32(hw, TXGBE_PBTXLNKXOFF);
2038
2039         /* DMA Stats */
2040         hw_stats->rx_packets += rd32(hw, TXGBE_DMARXPKT);
2041         hw_stats->tx_packets += rd32(hw, TXGBE_DMATXPKT);
2042
2043         hw_stats->rx_bytes += rd64(hw, TXGBE_DMARXOCTL);
2044         hw_stats->tx_bytes += rd64(hw, TXGBE_DMATXOCTL);
2045         hw_stats->rx_drop_packets += rd32(hw, TXGBE_PBRXDROP);
2046
2047         /* MAC Stats */
2048         hw_stats->rx_crc_errors += rd64(hw, TXGBE_MACRXERRCRCL);
2049         hw_stats->rx_multicast_packets += rd64(hw, TXGBE_MACRXMPKTL);
2050         hw_stats->tx_multicast_packets += rd64(hw, TXGBE_MACTXMPKTL);
2051
2052         hw_stats->rx_total_packets += rd64(hw, TXGBE_MACRXPKTL);
2053         hw_stats->tx_total_packets += rd64(hw, TXGBE_MACTXPKTL);
2054         hw_stats->rx_total_bytes += rd64(hw, TXGBE_MACRXGBOCTL);
2055
2056         hw_stats->rx_broadcast_packets += rd64(hw, TXGBE_MACRXOCTL);
2057         hw_stats->tx_broadcast_packets += rd32(hw, TXGBE_MACTXOCTL);
2058
2059         hw_stats->rx_size_64_packets += rd64(hw, TXGBE_MACRX1TO64L);
2060         hw_stats->rx_size_65_to_127_packets += rd64(hw, TXGBE_MACRX65TO127L);
2061         hw_stats->rx_size_128_to_255_packets += rd64(hw, TXGBE_MACRX128TO255L);
2062         hw_stats->rx_size_256_to_511_packets += rd64(hw, TXGBE_MACRX256TO511L);
2063         hw_stats->rx_size_512_to_1023_packets +=
2064                         rd64(hw, TXGBE_MACRX512TO1023L);
2065         hw_stats->rx_size_1024_to_max_packets +=
2066                         rd64(hw, TXGBE_MACRX1024TOMAXL);
2067         hw_stats->tx_size_64_packets += rd64(hw, TXGBE_MACTX1TO64L);
2068         hw_stats->tx_size_65_to_127_packets += rd64(hw, TXGBE_MACTX65TO127L);
2069         hw_stats->tx_size_128_to_255_packets += rd64(hw, TXGBE_MACTX128TO255L);
2070         hw_stats->tx_size_256_to_511_packets += rd64(hw, TXGBE_MACTX256TO511L);
2071         hw_stats->tx_size_512_to_1023_packets +=
2072                         rd64(hw, TXGBE_MACTX512TO1023L);
2073         hw_stats->tx_size_1024_to_max_packets +=
2074                         rd64(hw, TXGBE_MACTX1024TOMAXL);
2075
2076         hw_stats->rx_undersize_errors += rd64(hw, TXGBE_MACRXERRLENL);
2077         hw_stats->rx_oversize_errors += rd32(hw, TXGBE_MACRXOVERSIZE);
2078         hw_stats->rx_jabber_errors += rd32(hw, TXGBE_MACRXJABBER);
2079
2080         /* MNG Stats */
2081         hw_stats->mng_bmc2host_packets = rd32(hw, TXGBE_MNGBMC2OS);
2082         hw_stats->mng_host2bmc_packets = rd32(hw, TXGBE_MNGOS2BMC);
2083         hw_stats->rx_management_packets = rd32(hw, TXGBE_DMARXMNG);
2084         hw_stats->tx_management_packets = rd32(hw, TXGBE_DMATXMNG);
2085
2086         /* FCoE Stats */
2087         hw_stats->rx_fcoe_crc_errors += rd32(hw, TXGBE_FCOECRC);
2088         hw_stats->rx_fcoe_mbuf_allocation_errors += rd32(hw, TXGBE_FCOELAST);
2089         hw_stats->rx_fcoe_dropped += rd32(hw, TXGBE_FCOERPDC);
2090         hw_stats->rx_fcoe_packets += rd32(hw, TXGBE_FCOEPRC);
2091         hw_stats->tx_fcoe_packets += rd32(hw, TXGBE_FCOEPTC);
2092         hw_stats->rx_fcoe_bytes += rd32(hw, TXGBE_FCOEDWRC);
2093         hw_stats->tx_fcoe_bytes += rd32(hw, TXGBE_FCOEDWTC);
2094
2095         /* Flow Director Stats */
2096         hw_stats->flow_director_matched_filters += rd32(hw, TXGBE_FDIRMATCH);
2097         hw_stats->flow_director_missed_filters += rd32(hw, TXGBE_FDIRMISS);
2098         hw_stats->flow_director_added_filters +=
2099                 TXGBE_FDIRUSED_ADD(rd32(hw, TXGBE_FDIRUSED));
2100         hw_stats->flow_director_removed_filters +=
2101                 TXGBE_FDIRUSED_REM(rd32(hw, TXGBE_FDIRUSED));
2102         hw_stats->flow_director_filter_add_errors +=
2103                 TXGBE_FDIRFAIL_ADD(rd32(hw, TXGBE_FDIRFAIL));
2104         hw_stats->flow_director_filter_remove_errors +=
2105                 TXGBE_FDIRFAIL_REM(rd32(hw, TXGBE_FDIRFAIL));
2106
2107         /* MACsec Stats */
2108         hw_stats->tx_macsec_pkts_untagged += rd32(hw, TXGBE_LSECTX_UTPKT);
2109         hw_stats->tx_macsec_pkts_encrypted +=
2110                         rd32(hw, TXGBE_LSECTX_ENCPKT);
2111         hw_stats->tx_macsec_pkts_protected +=
2112                         rd32(hw, TXGBE_LSECTX_PROTPKT);
2113         hw_stats->tx_macsec_octets_encrypted +=
2114                         rd32(hw, TXGBE_LSECTX_ENCOCT);
2115         hw_stats->tx_macsec_octets_protected +=
2116                         rd32(hw, TXGBE_LSECTX_PROTOCT);
2117         hw_stats->rx_macsec_pkts_untagged += rd32(hw, TXGBE_LSECRX_UTPKT);
2118         hw_stats->rx_macsec_pkts_badtag += rd32(hw, TXGBE_LSECRX_BTPKT);
2119         hw_stats->rx_macsec_pkts_nosci += rd32(hw, TXGBE_LSECRX_NOSCIPKT);
2120         hw_stats->rx_macsec_pkts_unknownsci += rd32(hw, TXGBE_LSECRX_UNSCIPKT);
2121         hw_stats->rx_macsec_octets_decrypted += rd32(hw, TXGBE_LSECRX_DECOCT);
2122         hw_stats->rx_macsec_octets_validated += rd32(hw, TXGBE_LSECRX_VLDOCT);
2123         hw_stats->rx_macsec_sc_pkts_unchecked +=
2124                         rd32(hw, TXGBE_LSECRX_UNCHKPKT);
2125         hw_stats->rx_macsec_sc_pkts_delayed += rd32(hw, TXGBE_LSECRX_DLYPKT);
2126         hw_stats->rx_macsec_sc_pkts_late += rd32(hw, TXGBE_LSECRX_LATEPKT);
2127         for (i = 0; i < 2; i++) {
2128                 hw_stats->rx_macsec_sa_pkts_ok +=
2129                         rd32(hw, TXGBE_LSECRX_OKPKT(i));
2130                 hw_stats->rx_macsec_sa_pkts_invalid +=
2131                         rd32(hw, TXGBE_LSECRX_INVPKT(i));
2132                 hw_stats->rx_macsec_sa_pkts_notvalid +=
2133                         rd32(hw, TXGBE_LSECRX_BADPKT(i));
2134         }
2135         hw_stats->rx_macsec_sa_pkts_unusedsa +=
2136                         rd32(hw, TXGBE_LSECRX_INVSAPKT);
2137         hw_stats->rx_macsec_sa_pkts_notusingsa +=
2138                         rd32(hw, TXGBE_LSECRX_BADSAPKT);
2139
2140         hw_stats->rx_total_missed_packets = 0;
2141         for (i = 0; i < TXGBE_MAX_UP; i++) {
2142                 hw_stats->rx_total_missed_packets +=
2143                         hw_stats->up[i].rx_up_dropped;
2144         }
2145 }
2146
2147 static int
2148 txgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2149 {
2150         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2151         struct txgbe_hw_stats *hw_stats = TXGBE_DEV_STATS(dev);
2152         struct txgbe_stat_mappings *stat_mappings =
2153                         TXGBE_DEV_STAT_MAPPINGS(dev);
2154         uint32_t i, j;
2155
2156         txgbe_read_stats_registers(hw, hw_stats);
2157
2158         if (stats == NULL)
2159                 return -EINVAL;
2160
2161         /* Fill out the rte_eth_stats statistics structure */
2162         stats->ipackets = hw_stats->rx_packets;
2163         stats->ibytes = hw_stats->rx_bytes;
2164         stats->opackets = hw_stats->tx_packets;
2165         stats->obytes = hw_stats->tx_bytes;
2166
2167         memset(&stats->q_ipackets, 0, sizeof(stats->q_ipackets));
2168         memset(&stats->q_opackets, 0, sizeof(stats->q_opackets));
2169         memset(&stats->q_ibytes, 0, sizeof(stats->q_ibytes));
2170         memset(&stats->q_obytes, 0, sizeof(stats->q_obytes));
2171         memset(&stats->q_errors, 0, sizeof(stats->q_errors));
2172         for (i = 0; i < TXGBE_MAX_QP; i++) {
2173                 uint32_t n = i / NB_QMAP_FIELDS_PER_QSM_REG;
2174                 uint32_t offset = (i % NB_QMAP_FIELDS_PER_QSM_REG) * 8;
2175                 uint32_t q_map;
2176
2177                 q_map = (stat_mappings->rqsm[n] >> offset)
2178                                 & QMAP_FIELD_RESERVED_BITS_MASK;
2179                 j = (q_map < RTE_ETHDEV_QUEUE_STAT_CNTRS
2180                      ? q_map : q_map % RTE_ETHDEV_QUEUE_STAT_CNTRS);
2181                 stats->q_ipackets[j] += hw_stats->qp[i].rx_qp_packets;
2182                 stats->q_ibytes[j] += hw_stats->qp[i].rx_qp_bytes;
2183
2184                 q_map = (stat_mappings->tqsm[n] >> offset)
2185                                 & QMAP_FIELD_RESERVED_BITS_MASK;
2186                 j = (q_map < RTE_ETHDEV_QUEUE_STAT_CNTRS
2187                      ? q_map : q_map % RTE_ETHDEV_QUEUE_STAT_CNTRS);
2188                 stats->q_opackets[j] += hw_stats->qp[i].tx_qp_packets;
2189                 stats->q_obytes[j] += hw_stats->qp[i].tx_qp_bytes;
2190         }
2191
2192         /* Rx Errors */
2193         stats->imissed  = hw_stats->rx_total_missed_packets;
2194         stats->ierrors  = hw_stats->rx_crc_errors +
2195                           hw_stats->rx_mac_short_packet_dropped +
2196                           hw_stats->rx_length_errors +
2197                           hw_stats->rx_undersize_errors +
2198                           hw_stats->rx_oversize_errors +
2199                           hw_stats->rx_drop_packets +
2200                           hw_stats->rx_illegal_byte_errors +
2201                           hw_stats->rx_error_bytes +
2202                           hw_stats->rx_fragment_errors +
2203                           hw_stats->rx_fcoe_crc_errors +
2204                           hw_stats->rx_fcoe_mbuf_allocation_errors;
2205
2206         /* Tx Errors */
2207         stats->oerrors  = 0;
2208         return 0;
2209 }
2210
2211 static int
2212 txgbe_dev_stats_reset(struct rte_eth_dev *dev)
2213 {
2214         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2215         struct txgbe_hw_stats *hw_stats = TXGBE_DEV_STATS(dev);
2216
2217         /* HW registers are cleared on read */
2218         hw->offset_loaded = 0;
2219         txgbe_dev_stats_get(dev, NULL);
2220         hw->offset_loaded = 1;
2221
2222         /* Reset software totals */
2223         memset(hw_stats, 0, sizeof(*hw_stats));
2224
2225         return 0;
2226 }
2227
2228 /* This function calculates the number of xstats based on the current config */
2229 static unsigned
2230 txgbe_xstats_calc_num(struct rte_eth_dev *dev)
2231 {
2232         int nb_queues = max(dev->data->nb_rx_queues, dev->data->nb_tx_queues);
2233         return TXGBE_NB_HW_STATS +
2234                TXGBE_NB_UP_STATS * TXGBE_MAX_UP +
2235                TXGBE_NB_QP_STATS * nb_queues;
2236 }
2237
2238 static inline int
2239 txgbe_get_name_by_id(uint32_t id, char *name, uint32_t size)
2240 {
2241         int nb, st;
2242
2243         /* Extended stats from txgbe_hw_stats */
2244         if (id < TXGBE_NB_HW_STATS) {
2245                 snprintf(name, size, "[hw]%s",
2246                         rte_txgbe_stats_strings[id].name);
2247                 return 0;
2248         }
2249         id -= TXGBE_NB_HW_STATS;
2250
2251         /* Priority Stats */
2252         if (id < TXGBE_NB_UP_STATS * TXGBE_MAX_UP) {
2253                 nb = id / TXGBE_NB_UP_STATS;
2254                 st = id % TXGBE_NB_UP_STATS;
2255                 snprintf(name, size, "[p%u]%s", nb,
2256                         rte_txgbe_up_strings[st].name);
2257                 return 0;
2258         }
2259         id -= TXGBE_NB_UP_STATS * TXGBE_MAX_UP;
2260
2261         /* Queue Stats */
2262         if (id < TXGBE_NB_QP_STATS * TXGBE_MAX_QP) {
2263                 nb = id / TXGBE_NB_QP_STATS;
2264                 st = id % TXGBE_NB_QP_STATS;
2265                 snprintf(name, size, "[q%u]%s", nb,
2266                         rte_txgbe_qp_strings[st].name);
2267                 return 0;
2268         }
2269         id -= TXGBE_NB_QP_STATS * TXGBE_MAX_QP;
2270
2271         return -(int)(id + 1);
2272 }
2273
2274 static inline int
2275 txgbe_get_offset_by_id(uint32_t id, uint32_t *offset)
2276 {
2277         int nb, st;
2278
2279         /* Extended stats from txgbe_hw_stats */
2280         if (id < TXGBE_NB_HW_STATS) {
2281                 *offset = rte_txgbe_stats_strings[id].offset;
2282                 return 0;
2283         }
2284         id -= TXGBE_NB_HW_STATS;
2285
2286         /* Priority Stats */
2287         if (id < TXGBE_NB_UP_STATS * TXGBE_MAX_UP) {
2288                 nb = id / TXGBE_NB_UP_STATS;
2289                 st = id % TXGBE_NB_UP_STATS;
2290                 *offset = rte_txgbe_up_strings[st].offset +
2291                         nb * (TXGBE_NB_UP_STATS * sizeof(uint64_t));
2292                 return 0;
2293         }
2294         id -= TXGBE_NB_UP_STATS * TXGBE_MAX_UP;
2295
2296         /* Queue Stats */
2297         if (id < TXGBE_NB_QP_STATS * TXGBE_MAX_QP) {
2298                 nb = id / TXGBE_NB_QP_STATS;
2299                 st = id % TXGBE_NB_QP_STATS;
2300                 *offset = rte_txgbe_qp_strings[st].offset +
2301                         nb * (TXGBE_NB_QP_STATS * sizeof(uint64_t));
2302                 return 0;
2303         }
2304
2305         return -1;
2306 }
2307
2308 static int txgbe_dev_xstats_get_names(struct rte_eth_dev *dev,
2309         struct rte_eth_xstat_name *xstats_names, unsigned int limit)
2310 {
2311         unsigned int i, count;
2312
2313         count = txgbe_xstats_calc_num(dev);
2314         if (xstats_names == NULL)
2315                 return count;
2316
2317         /* Note: limit >= cnt_stats checked upstream
2318          * in rte_eth_xstats_names()
2319          */
2320         limit = min(limit, count);
2321
2322         /* Extended stats from txgbe_hw_stats */
2323         for (i = 0; i < limit; i++) {
2324                 if (txgbe_get_name_by_id(i, xstats_names[i].name,
2325                         sizeof(xstats_names[i].name))) {
2326                         PMD_INIT_LOG(WARNING, "id value %d isn't valid", i);
2327                         break;
2328                 }
2329         }
2330
2331         return i;
2332 }
2333
2334 static int txgbe_dev_xstats_get_names_by_id(struct rte_eth_dev *dev,
2335         struct rte_eth_xstat_name *xstats_names,
2336         const uint64_t *ids,
2337         unsigned int limit)
2338 {
2339         unsigned int i;
2340
2341         if (ids == NULL)
2342                 return txgbe_dev_xstats_get_names(dev, xstats_names, limit);
2343
2344         for (i = 0; i < limit; i++) {
2345                 if (txgbe_get_name_by_id(ids[i], xstats_names[i].name,
2346                                 sizeof(xstats_names[i].name))) {
2347                         PMD_INIT_LOG(WARNING, "id value %d isn't valid", i);
2348                         return -1;
2349                 }
2350         }
2351
2352         return i;
2353 }
2354
2355 static int
2356 txgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2357                                          unsigned int limit)
2358 {
2359         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2360         struct txgbe_hw_stats *hw_stats = TXGBE_DEV_STATS(dev);
2361         unsigned int i, count;
2362
2363         txgbe_read_stats_registers(hw, hw_stats);
2364
2365         /* If this is a reset xstats is NULL, and we have cleared the
2366          * registers by reading them.
2367          */
2368         count = txgbe_xstats_calc_num(dev);
2369         if (xstats == NULL)
2370                 return count;
2371
2372         limit = min(limit, txgbe_xstats_calc_num(dev));
2373
2374         /* Extended stats from txgbe_hw_stats */
2375         for (i = 0; i < limit; i++) {
2376                 uint32_t offset = 0;
2377
2378                 if (txgbe_get_offset_by_id(i, &offset)) {
2379                         PMD_INIT_LOG(WARNING, "id value %d isn't valid", i);
2380                         break;
2381                 }
2382                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) + offset);
2383                 xstats[i].id = i;
2384         }
2385
2386         return i;
2387 }
2388
2389 static int
2390 txgbe_dev_xstats_get_(struct rte_eth_dev *dev, uint64_t *values,
2391                                          unsigned int limit)
2392 {
2393         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2394         struct txgbe_hw_stats *hw_stats = TXGBE_DEV_STATS(dev);
2395         unsigned int i, count;
2396
2397         txgbe_read_stats_registers(hw, hw_stats);
2398
2399         /* If this is a reset xstats is NULL, and we have cleared the
2400          * registers by reading them.
2401          */
2402         count = txgbe_xstats_calc_num(dev);
2403         if (values == NULL)
2404                 return count;
2405
2406         limit = min(limit, txgbe_xstats_calc_num(dev));
2407
2408         /* Extended stats from txgbe_hw_stats */
2409         for (i = 0; i < limit; i++) {
2410                 uint32_t offset;
2411
2412                 if (txgbe_get_offset_by_id(i, &offset)) {
2413                         PMD_INIT_LOG(WARNING, "id value %d isn't valid", i);
2414                         break;
2415                 }
2416                 values[i] = *(uint64_t *)(((char *)hw_stats) + offset);
2417         }
2418
2419         return i;
2420 }
2421
2422 static int
2423 txgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
2424                 uint64_t *values, unsigned int limit)
2425 {
2426         struct txgbe_hw_stats *hw_stats = TXGBE_DEV_STATS(dev);
2427         unsigned int i;
2428
2429         if (ids == NULL)
2430                 return txgbe_dev_xstats_get_(dev, values, limit);
2431
2432         for (i = 0; i < limit; i++) {
2433                 uint32_t offset;
2434
2435                 if (txgbe_get_offset_by_id(ids[i], &offset)) {
2436                         PMD_INIT_LOG(WARNING, "id value %d isn't valid", i);
2437                         break;
2438                 }
2439                 values[i] = *(uint64_t *)(((char *)hw_stats) + offset);
2440         }
2441
2442         return i;
2443 }
2444
2445 static int
2446 txgbe_dev_xstats_reset(struct rte_eth_dev *dev)
2447 {
2448         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2449         struct txgbe_hw_stats *hw_stats = TXGBE_DEV_STATS(dev);
2450
2451         /* HW registers are cleared on read */
2452         hw->offset_loaded = 0;
2453         txgbe_read_stats_registers(hw, hw_stats);
2454         hw->offset_loaded = 1;
2455
2456         /* Reset software totals */
2457         memset(hw_stats, 0, sizeof(*hw_stats));
2458
2459         return 0;
2460 }
2461
2462 static int
2463 txgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
2464 {
2465         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2466         u16 eeprom_verh, eeprom_verl;
2467         u32 etrack_id;
2468         int ret;
2469
2470         hw->rom.readw_sw(hw, TXGBE_EEPROM_VERSION_H, &eeprom_verh);
2471         hw->rom.readw_sw(hw, TXGBE_EEPROM_VERSION_L, &eeprom_verl);
2472
2473         etrack_id = (eeprom_verh << 16) | eeprom_verl;
2474         ret = snprintf(fw_version, fw_size, "0x%08x", etrack_id);
2475
2476         ret += 1; /* add the size of '\0' */
2477         if (fw_size < (u32)ret)
2478                 return ret;
2479         else
2480                 return 0;
2481 }
2482
2483 static int
2484 txgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2485 {
2486         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2487         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2488
2489         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
2490         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
2491         dev_info->min_rx_bufsize = 1024;
2492         dev_info->max_rx_pktlen = 15872;
2493         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
2494         dev_info->max_hash_mac_addrs = TXGBE_VMDQ_NUM_UC_MAC;
2495         dev_info->max_vfs = pci_dev->max_vfs;
2496         dev_info->max_vmdq_pools = ETH_64_POOLS;
2497         dev_info->vmdq_queue_num = dev_info->max_rx_queues;
2498         dev_info->rx_queue_offload_capa = txgbe_get_rx_queue_offloads(dev);
2499         dev_info->rx_offload_capa = (txgbe_get_rx_port_offloads(dev) |
2500                                      dev_info->rx_queue_offload_capa);
2501         dev_info->tx_queue_offload_capa = txgbe_get_tx_queue_offloads(dev);
2502         dev_info->tx_offload_capa = txgbe_get_tx_port_offloads(dev);
2503
2504         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2505                 .rx_thresh = {
2506                         .pthresh = TXGBE_DEFAULT_RX_PTHRESH,
2507                         .hthresh = TXGBE_DEFAULT_RX_HTHRESH,
2508                         .wthresh = TXGBE_DEFAULT_RX_WTHRESH,
2509                 },
2510                 .rx_free_thresh = TXGBE_DEFAULT_RX_FREE_THRESH,
2511                 .rx_drop_en = 0,
2512                 .offloads = 0,
2513         };
2514
2515         dev_info->default_txconf = (struct rte_eth_txconf) {
2516                 .tx_thresh = {
2517                         .pthresh = TXGBE_DEFAULT_TX_PTHRESH,
2518                         .hthresh = TXGBE_DEFAULT_TX_HTHRESH,
2519                         .wthresh = TXGBE_DEFAULT_TX_WTHRESH,
2520                 },
2521                 .tx_free_thresh = TXGBE_DEFAULT_TX_FREE_THRESH,
2522                 .offloads = 0,
2523         };
2524
2525         dev_info->rx_desc_lim = rx_desc_lim;
2526         dev_info->tx_desc_lim = tx_desc_lim;
2527
2528         dev_info->hash_key_size = TXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
2529         dev_info->reta_size = ETH_RSS_RETA_SIZE_128;
2530         dev_info->flow_type_rss_offloads = TXGBE_RSS_OFFLOAD_ALL;
2531
2532         dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
2533         dev_info->speed_capa |= ETH_LINK_SPEED_100M;
2534
2535         /* Driver-preferred Rx/Tx parameters */
2536         dev_info->default_rxportconf.burst_size = 32;
2537         dev_info->default_txportconf.burst_size = 32;
2538         dev_info->default_rxportconf.nb_queues = 1;
2539         dev_info->default_txportconf.nb_queues = 1;
2540         dev_info->default_rxportconf.ring_size = 256;
2541         dev_info->default_txportconf.ring_size = 256;
2542
2543         return 0;
2544 }
2545
2546 const uint32_t *
2547 txgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev)
2548 {
2549         if (dev->rx_pkt_burst == txgbe_recv_pkts ||
2550             dev->rx_pkt_burst == txgbe_recv_pkts_lro_single_alloc ||
2551             dev->rx_pkt_burst == txgbe_recv_pkts_lro_bulk_alloc ||
2552             dev->rx_pkt_burst == txgbe_recv_pkts_bulk_alloc)
2553                 return txgbe_get_supported_ptypes();
2554
2555         return NULL;
2556 }
2557
2558 void
2559 txgbe_dev_setup_link_alarm_handler(void *param)
2560 {
2561         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2562         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2563         struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);
2564         u32 speed;
2565         bool autoneg = false;
2566
2567         speed = hw->phy.autoneg_advertised;
2568         if (!speed)
2569                 hw->mac.get_link_capabilities(hw, &speed, &autoneg);
2570
2571         hw->mac.setup_link(hw, speed, true);
2572
2573         intr->flags &= ~TXGBE_FLAG_NEED_LINK_CONFIG;
2574 }
2575
2576 /* return 0 means link status changed, -1 means not changed */
2577 int
2578 txgbe_dev_link_update_share(struct rte_eth_dev *dev,
2579                             int wait_to_complete)
2580 {
2581         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2582         struct rte_eth_link link;
2583         u32 link_speed = TXGBE_LINK_SPEED_UNKNOWN;
2584         struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);
2585         bool link_up;
2586         int err;
2587         int wait = 1;
2588
2589         memset(&link, 0, sizeof(link));
2590         link.link_status = ETH_LINK_DOWN;
2591         link.link_speed = ETH_SPEED_NUM_NONE;
2592         link.link_duplex = ETH_LINK_HALF_DUPLEX;
2593         link.link_autoneg = ETH_LINK_AUTONEG;
2594
2595         hw->mac.get_link_status = true;
2596
2597         if (intr->flags & TXGBE_FLAG_NEED_LINK_CONFIG)
2598                 return rte_eth_linkstatus_set(dev, &link);
2599
2600         /* check if it needs to wait to complete, if lsc interrupt is enabled */
2601         if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
2602                 wait = 0;
2603
2604         err = hw->mac.check_link(hw, &link_speed, &link_up, wait);
2605
2606         if (err != 0) {
2607                 link.link_speed = ETH_SPEED_NUM_100M;
2608                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
2609                 return rte_eth_linkstatus_set(dev, &link);
2610         }
2611
2612         if (link_up == 0) {
2613                 if (hw->phy.media_type == txgbe_media_type_fiber) {
2614                         intr->flags |= TXGBE_FLAG_NEED_LINK_CONFIG;
2615                         rte_eal_alarm_set(10,
2616                                 txgbe_dev_setup_link_alarm_handler, dev);
2617                 }
2618                 return rte_eth_linkstatus_set(dev, &link);
2619         }
2620
2621         intr->flags &= ~TXGBE_FLAG_NEED_LINK_CONFIG;
2622         link.link_status = ETH_LINK_UP;
2623         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2624
2625         switch (link_speed) {
2626         default:
2627         case TXGBE_LINK_SPEED_UNKNOWN:
2628                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
2629                 link.link_speed = ETH_SPEED_NUM_100M;
2630                 break;
2631
2632         case TXGBE_LINK_SPEED_100M_FULL:
2633                 link.link_speed = ETH_SPEED_NUM_100M;
2634                 break;
2635
2636         case TXGBE_LINK_SPEED_1GB_FULL:
2637                 link.link_speed = ETH_SPEED_NUM_1G;
2638                 break;
2639
2640         case TXGBE_LINK_SPEED_2_5GB_FULL:
2641                 link.link_speed = ETH_SPEED_NUM_2_5G;
2642                 break;
2643
2644         case TXGBE_LINK_SPEED_5GB_FULL:
2645                 link.link_speed = ETH_SPEED_NUM_5G;
2646                 break;
2647
2648         case TXGBE_LINK_SPEED_10GB_FULL:
2649                 link.link_speed = ETH_SPEED_NUM_10G;
2650                 break;
2651         }
2652
2653         return rte_eth_linkstatus_set(dev, &link);
2654 }
2655
2656 static int
2657 txgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
2658 {
2659         return txgbe_dev_link_update_share(dev, wait_to_complete);
2660 }
2661
2662 static int
2663 txgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
2664 {
2665         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2666         uint32_t fctrl;
2667
2668         fctrl = rd32(hw, TXGBE_PSRCTL);
2669         fctrl |= (TXGBE_PSRCTL_UCP | TXGBE_PSRCTL_MCP);
2670         wr32(hw, TXGBE_PSRCTL, fctrl);
2671
2672         return 0;
2673 }
2674
2675 static int
2676 txgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
2677 {
2678         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2679         uint32_t fctrl;
2680
2681         fctrl = rd32(hw, TXGBE_PSRCTL);
2682         fctrl &= (~TXGBE_PSRCTL_UCP);
2683         if (dev->data->all_multicast == 1)
2684                 fctrl |= TXGBE_PSRCTL_MCP;
2685         else
2686                 fctrl &= (~TXGBE_PSRCTL_MCP);
2687         wr32(hw, TXGBE_PSRCTL, fctrl);
2688
2689         return 0;
2690 }
2691
2692 static int
2693 txgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
2694 {
2695         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2696         uint32_t fctrl;
2697
2698         fctrl = rd32(hw, TXGBE_PSRCTL);
2699         fctrl |= TXGBE_PSRCTL_MCP;
2700         wr32(hw, TXGBE_PSRCTL, fctrl);
2701
2702         return 0;
2703 }
2704
2705 static int
2706 txgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
2707 {
2708         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2709         uint32_t fctrl;
2710
2711         if (dev->data->promiscuous == 1)
2712                 return 0; /* must remain in all_multicast mode */
2713
2714         fctrl = rd32(hw, TXGBE_PSRCTL);
2715         fctrl &= (~TXGBE_PSRCTL_MCP);
2716         wr32(hw, TXGBE_PSRCTL, fctrl);
2717
2718         return 0;
2719 }
2720
2721 /**
2722  * It clears the interrupt causes and enables the interrupt.
2723  * It will be called once only during nic initialized.
2724  *
2725  * @param dev
2726  *  Pointer to struct rte_eth_dev.
2727  * @param on
2728  *  Enable or Disable.
2729  *
2730  * @return
2731  *  - On success, zero.
2732  *  - On failure, a negative value.
2733  */
2734 static int
2735 txgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on)
2736 {
2737         struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);
2738
2739         txgbe_dev_link_status_print(dev);
2740         if (on)
2741                 intr->mask_misc |= TXGBE_ICRMISC_LSC;
2742         else
2743                 intr->mask_misc &= ~TXGBE_ICRMISC_LSC;
2744
2745         return 0;
2746 }
2747
2748 /**
2749  * It clears the interrupt causes and enables the interrupt.
2750  * It will be called once only during nic initialized.
2751  *
2752  * @param dev
2753  *  Pointer to struct rte_eth_dev.
2754  *
2755  * @return
2756  *  - On success, zero.
2757  *  - On failure, a negative value.
2758  */
2759 static int
2760 txgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
2761 {
2762         struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);
2763
2764         intr->mask[0] |= TXGBE_ICR_MASK;
2765         intr->mask[1] |= TXGBE_ICR_MASK;
2766
2767         return 0;
2768 }
2769
2770 /**
2771  * It clears the interrupt causes and enables the interrupt.
2772  * It will be called once only during nic initialized.
2773  *
2774  * @param dev
2775  *  Pointer to struct rte_eth_dev.
2776  *
2777  * @return
2778  *  - On success, zero.
2779  *  - On failure, a negative value.
2780  */
2781 static int
2782 txgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev)
2783 {
2784         struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);
2785
2786         intr->mask_misc |= TXGBE_ICRMISC_LNKSEC;
2787
2788         return 0;
2789 }
2790
2791 /*
2792  * It reads ICR and sets flag (TXGBE_ICRMISC_LSC) for the link_update.
2793  *
2794  * @param dev
2795  *  Pointer to struct rte_eth_dev.
2796  *
2797  * @return
2798  *  - On success, zero.
2799  *  - On failure, a negative value.
2800  */
2801 static int
2802 txgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
2803 {
2804         uint32_t eicr;
2805         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2806         struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);
2807
2808         /* clear all cause mask */
2809         txgbe_disable_intr(hw);
2810
2811         /* read-on-clear nic registers here */
2812         eicr = ((u32 *)hw->isb_mem)[TXGBE_ISB_MISC];
2813         PMD_DRV_LOG(DEBUG, "eicr %x", eicr);
2814
2815         intr->flags = 0;
2816
2817         /* set flag for async link update */
2818         if (eicr & TXGBE_ICRMISC_LSC)
2819                 intr->flags |= TXGBE_FLAG_NEED_LINK_UPDATE;
2820
2821         if (eicr & TXGBE_ICRMISC_VFMBX)
2822                 intr->flags |= TXGBE_FLAG_MAILBOX;
2823
2824         if (eicr & TXGBE_ICRMISC_LNKSEC)
2825                 intr->flags |= TXGBE_FLAG_MACSEC;
2826
2827         if (eicr & TXGBE_ICRMISC_GPIO)
2828                 intr->flags |= TXGBE_FLAG_PHY_INTERRUPT;
2829
2830         return 0;
2831 }
2832
2833 /**
2834  * It gets and then prints the link status.
2835  *
2836  * @param dev
2837  *  Pointer to struct rte_eth_dev.
2838  *
2839  * @return
2840  *  - On success, zero.
2841  *  - On failure, a negative value.
2842  */
2843 static void
2844 txgbe_dev_link_status_print(struct rte_eth_dev *dev)
2845 {
2846         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2847         struct rte_eth_link link;
2848
2849         rte_eth_linkstatus_get(dev, &link);
2850
2851         if (link.link_status) {
2852                 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
2853                                         (int)(dev->data->port_id),
2854                                         (unsigned int)link.link_speed,
2855                         link.link_duplex == ETH_LINK_FULL_DUPLEX ?
2856                                         "full-duplex" : "half-duplex");
2857         } else {
2858                 PMD_INIT_LOG(INFO, " Port %d: Link Down",
2859                                 (int)(dev->data->port_id));
2860         }
2861         PMD_INIT_LOG(DEBUG, "PCI Address: " PCI_PRI_FMT,
2862                                 pci_dev->addr.domain,
2863                                 pci_dev->addr.bus,
2864                                 pci_dev->addr.devid,
2865                                 pci_dev->addr.function);
2866 }
2867
2868 /*
2869  * It executes link_update after knowing an interrupt occurred.
2870  *
2871  * @param dev
2872  *  Pointer to struct rte_eth_dev.
2873  *
2874  * @return
2875  *  - On success, zero.
2876  *  - On failure, a negative value.
2877  */
2878 static int
2879 txgbe_dev_interrupt_action(struct rte_eth_dev *dev,
2880                            struct rte_intr_handle *intr_handle)
2881 {
2882         struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);
2883         int64_t timeout;
2884         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2885
2886         PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
2887
2888         if (intr->flags & TXGBE_FLAG_MAILBOX) {
2889                 txgbe_pf_mbx_process(dev);
2890                 intr->flags &= ~TXGBE_FLAG_MAILBOX;
2891         }
2892
2893         if (intr->flags & TXGBE_FLAG_PHY_INTERRUPT) {
2894                 hw->phy.handle_lasi(hw);
2895                 intr->flags &= ~TXGBE_FLAG_PHY_INTERRUPT;
2896         }
2897
2898         if (intr->flags & TXGBE_FLAG_NEED_LINK_UPDATE) {
2899                 struct rte_eth_link link;
2900
2901                 /*get the link status before link update, for predicting later*/
2902                 rte_eth_linkstatus_get(dev, &link);
2903
2904                 txgbe_dev_link_update(dev, 0);
2905
2906                 /* likely to up */
2907                 if (!link.link_status)
2908                         /* handle it 1 sec later, wait it being stable */
2909                         timeout = TXGBE_LINK_UP_CHECK_TIMEOUT;
2910                 /* likely to down */
2911                 else
2912                         /* handle it 4 sec later, wait it being stable */
2913                         timeout = TXGBE_LINK_DOWN_CHECK_TIMEOUT;
2914
2915                 txgbe_dev_link_status_print(dev);
2916                 if (rte_eal_alarm_set(timeout * 1000,
2917                                       txgbe_dev_interrupt_delayed_handler,
2918                                       (void *)dev) < 0) {
2919                         PMD_DRV_LOG(ERR, "Error setting alarm");
2920                 } else {
2921                         /* remember original mask */
2922                         intr->mask_misc_orig = intr->mask_misc;
2923                         /* only disable lsc interrupt */
2924                         intr->mask_misc &= ~TXGBE_ICRMISC_LSC;
2925                 }
2926         }
2927
2928         PMD_DRV_LOG(DEBUG, "enable intr immediately");
2929         txgbe_enable_intr(dev);
2930         rte_intr_enable(intr_handle);
2931
2932         return 0;
2933 }
2934
2935 /**
2936  * Interrupt handler which shall be registered for alarm callback for delayed
2937  * handling specific interrupt to wait for the stable nic state. As the
2938  * NIC interrupt state is not stable for txgbe after link is just down,
2939  * it needs to wait 4 seconds to get the stable status.
2940  *
2941  * @param handle
2942  *  Pointer to interrupt handle.
2943  * @param param
2944  *  The address of parameter (struct rte_eth_dev *) registered before.
2945  *
2946  * @return
2947  *  void
2948  */
2949 static void
2950 txgbe_dev_interrupt_delayed_handler(void *param)
2951 {
2952         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2953         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2954         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2955         struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);
2956         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2957         uint32_t eicr;
2958
2959         txgbe_disable_intr(hw);
2960
2961         eicr = ((u32 *)hw->isb_mem)[TXGBE_ISB_MISC];
2962         if (eicr & TXGBE_ICRMISC_VFMBX)
2963                 txgbe_pf_mbx_process(dev);
2964
2965         if (intr->flags & TXGBE_FLAG_PHY_INTERRUPT) {
2966                 hw->phy.handle_lasi(hw);
2967                 intr->flags &= ~TXGBE_FLAG_PHY_INTERRUPT;
2968         }
2969
2970         if (intr->flags & TXGBE_FLAG_NEED_LINK_UPDATE) {
2971                 txgbe_dev_link_update(dev, 0);
2972                 intr->flags &= ~TXGBE_FLAG_NEED_LINK_UPDATE;
2973                 txgbe_dev_link_status_print(dev);
2974                 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC,
2975                                               NULL);
2976         }
2977
2978         if (intr->flags & TXGBE_FLAG_MACSEC) {
2979                 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_MACSEC,
2980                                               NULL);
2981                 intr->flags &= ~TXGBE_FLAG_MACSEC;
2982         }
2983
2984         /* restore original mask */
2985         intr->mask_misc = intr->mask_misc_orig;
2986         intr->mask_misc_orig = 0;
2987
2988         PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
2989         txgbe_enable_intr(dev);
2990         rte_intr_enable(intr_handle);
2991 }
2992
2993 /**
2994  * Interrupt handler triggered by NIC  for handling
2995  * specific interrupt.
2996  *
2997  * @param handle
2998  *  Pointer to interrupt handle.
2999  * @param param
3000  *  The address of parameter (struct rte_eth_dev *) registered before.
3001  *
3002  * @return
3003  *  void
3004  */
3005 static void
3006 txgbe_dev_interrupt_handler(void *param)
3007 {
3008         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3009
3010         txgbe_dev_interrupt_get_status(dev);
3011         txgbe_dev_interrupt_action(dev, dev->intr_handle);
3012 }
3013
3014 static int
3015 txgbe_dev_led_on(struct rte_eth_dev *dev)
3016 {
3017         struct txgbe_hw *hw;
3018
3019         hw = TXGBE_DEV_HW(dev);
3020         return txgbe_led_on(hw, 4) == 0 ? 0 : -ENOTSUP;
3021 }
3022
3023 static int
3024 txgbe_dev_led_off(struct rte_eth_dev *dev)
3025 {
3026         struct txgbe_hw *hw;
3027
3028         hw = TXGBE_DEV_HW(dev);
3029         return txgbe_led_off(hw, 4) == 0 ? 0 : -ENOTSUP;
3030 }
3031
3032 static int
3033 txgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3034 {
3035         struct txgbe_hw *hw;
3036         uint32_t mflcn_reg;
3037         uint32_t fccfg_reg;
3038         int rx_pause;
3039         int tx_pause;
3040
3041         hw = TXGBE_DEV_HW(dev);
3042
3043         fc_conf->pause_time = hw->fc.pause_time;
3044         fc_conf->high_water = hw->fc.high_water[0];
3045         fc_conf->low_water = hw->fc.low_water[0];
3046         fc_conf->send_xon = hw->fc.send_xon;
3047         fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
3048
3049         /*
3050          * Return rx_pause status according to actual setting of
3051          * RXFCCFG register.
3052          */
3053         mflcn_reg = rd32(hw, TXGBE_RXFCCFG);
3054         if (mflcn_reg & (TXGBE_RXFCCFG_FC | TXGBE_RXFCCFG_PFC))
3055                 rx_pause = 1;
3056         else
3057                 rx_pause = 0;
3058
3059         /*
3060          * Return tx_pause status according to actual setting of
3061          * TXFCCFG register.
3062          */
3063         fccfg_reg = rd32(hw, TXGBE_TXFCCFG);
3064         if (fccfg_reg & (TXGBE_TXFCCFG_FC | TXGBE_TXFCCFG_PFC))
3065                 tx_pause = 1;
3066         else
3067                 tx_pause = 0;
3068
3069         if (rx_pause && tx_pause)
3070                 fc_conf->mode = RTE_FC_FULL;
3071         else if (rx_pause)
3072                 fc_conf->mode = RTE_FC_RX_PAUSE;
3073         else if (tx_pause)
3074                 fc_conf->mode = RTE_FC_TX_PAUSE;
3075         else
3076                 fc_conf->mode = RTE_FC_NONE;
3077
3078         return 0;
3079 }
3080
3081 static int
3082 txgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3083 {
3084         struct txgbe_hw *hw;
3085         int err;
3086         uint32_t rx_buf_size;
3087         uint32_t max_high_water;
3088         enum txgbe_fc_mode rte_fcmode_2_txgbe_fcmode[] = {
3089                 txgbe_fc_none,
3090                 txgbe_fc_rx_pause,
3091                 txgbe_fc_tx_pause,
3092                 txgbe_fc_full
3093         };
3094
3095         PMD_INIT_FUNC_TRACE();
3096
3097         hw = TXGBE_DEV_HW(dev);
3098         rx_buf_size = rd32(hw, TXGBE_PBRXSIZE(0));
3099         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
3100
3101         /*
3102          * At least reserve one Ethernet frame for watermark
3103          * high_water/low_water in kilo bytes for txgbe
3104          */
3105         max_high_water = (rx_buf_size - RTE_ETHER_MAX_LEN) >> 10;
3106         if (fc_conf->high_water > max_high_water ||
3107             fc_conf->high_water < fc_conf->low_water) {
3108                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
3109                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
3110                 return -EINVAL;
3111         }
3112
3113         hw->fc.requested_mode = rte_fcmode_2_txgbe_fcmode[fc_conf->mode];
3114         hw->fc.pause_time     = fc_conf->pause_time;
3115         hw->fc.high_water[0]  = fc_conf->high_water;
3116         hw->fc.low_water[0]   = fc_conf->low_water;
3117         hw->fc.send_xon       = fc_conf->send_xon;
3118         hw->fc.disable_fc_autoneg = !fc_conf->autoneg;
3119
3120         err = txgbe_fc_enable(hw);
3121
3122         /* Not negotiated is not an error case */
3123         if (err == 0 || err == TXGBE_ERR_FC_NOT_NEGOTIATED) {
3124                 wr32m(hw, TXGBE_MACRXFLT, TXGBE_MACRXFLT_CTL_MASK,
3125                       (fc_conf->mac_ctrl_frame_fwd
3126                        ? TXGBE_MACRXFLT_CTL_NOPS : TXGBE_MACRXFLT_CTL_DROP));
3127                 txgbe_flush(hw);
3128
3129                 return 0;
3130         }
3131
3132         PMD_INIT_LOG(ERR, "txgbe_fc_enable = 0x%x", err);
3133         return -EIO;
3134 }
3135
3136 static int
3137 txgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
3138                 struct rte_eth_pfc_conf *pfc_conf)
3139 {
3140         int err;
3141         uint32_t rx_buf_size;
3142         uint32_t max_high_water;
3143         uint8_t tc_num;
3144         uint8_t  map[TXGBE_DCB_UP_MAX] = { 0 };
3145         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3146         struct txgbe_dcb_config *dcb_config = TXGBE_DEV_DCB_CONFIG(dev);
3147
3148         enum txgbe_fc_mode rte_fcmode_2_txgbe_fcmode[] = {
3149                 txgbe_fc_none,
3150                 txgbe_fc_rx_pause,
3151                 txgbe_fc_tx_pause,
3152                 txgbe_fc_full
3153         };
3154
3155         PMD_INIT_FUNC_TRACE();
3156
3157         txgbe_dcb_unpack_map_cee(dcb_config, TXGBE_DCB_RX_CONFIG, map);
3158         tc_num = map[pfc_conf->priority];
3159         rx_buf_size = rd32(hw, TXGBE_PBRXSIZE(tc_num));
3160         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
3161         /*
3162          * At least reserve one Ethernet frame for watermark
3163          * high_water/low_water in kilo bytes for txgbe
3164          */
3165         max_high_water = (rx_buf_size - RTE_ETHER_MAX_LEN) >> 10;
3166         if (pfc_conf->fc.high_water > max_high_water ||
3167             pfc_conf->fc.high_water <= pfc_conf->fc.low_water) {
3168                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
3169                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
3170                 return -EINVAL;
3171         }
3172
3173         hw->fc.requested_mode = rte_fcmode_2_txgbe_fcmode[pfc_conf->fc.mode];
3174         hw->fc.pause_time = pfc_conf->fc.pause_time;
3175         hw->fc.send_xon = pfc_conf->fc.send_xon;
3176         hw->fc.low_water[tc_num] =  pfc_conf->fc.low_water;
3177         hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
3178
3179         err = txgbe_dcb_pfc_enable(hw, tc_num);
3180
3181         /* Not negotiated is not an error case */
3182         if (err == 0 || err == TXGBE_ERR_FC_NOT_NEGOTIATED)
3183                 return 0;
3184
3185         PMD_INIT_LOG(ERR, "txgbe_dcb_pfc_enable = 0x%x", err);
3186         return -EIO;
3187 }
3188
3189 int
3190 txgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
3191                           struct rte_eth_rss_reta_entry64 *reta_conf,
3192                           uint16_t reta_size)
3193 {
3194         uint8_t i, j, mask;
3195         uint32_t reta;
3196         uint16_t idx, shift;
3197         struct txgbe_adapter *adapter = TXGBE_DEV_ADAPTER(dev);
3198         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3199
3200         PMD_INIT_FUNC_TRACE();
3201
3202         if (!txgbe_rss_update_sp(hw->mac.type)) {
3203                 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this "
3204                         "NIC.");
3205                 return -ENOTSUP;
3206         }
3207
3208         if (reta_size != ETH_RSS_RETA_SIZE_128) {
3209                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3210                         "(%d) doesn't match the number hardware can supported "
3211                         "(%d)", reta_size, ETH_RSS_RETA_SIZE_128);
3212                 return -EINVAL;
3213         }
3214
3215         for (i = 0; i < reta_size; i += 4) {
3216                 idx = i / RTE_RETA_GROUP_SIZE;
3217                 shift = i % RTE_RETA_GROUP_SIZE;
3218                 mask = (uint8_t)RS64(reta_conf[idx].mask, shift, 0xF);
3219                 if (!mask)
3220                         continue;
3221
3222                 reta = rd32a(hw, TXGBE_REG_RSSTBL, i >> 2);
3223                 for (j = 0; j < 4; j++) {
3224                         if (RS8(mask, j, 0x1)) {
3225                                 reta  &= ~(MS32(8 * j, 0xFF));
3226                                 reta |= LS32(reta_conf[idx].reta[shift + j],
3227                                                 8 * j, 0xFF);
3228                         }
3229                 }
3230                 wr32a(hw, TXGBE_REG_RSSTBL, i >> 2, reta);
3231         }
3232         adapter->rss_reta_updated = 1;
3233
3234         return 0;
3235 }
3236
3237 int
3238 txgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
3239                          struct rte_eth_rss_reta_entry64 *reta_conf,
3240                          uint16_t reta_size)
3241 {
3242         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3243         uint8_t i, j, mask;
3244         uint32_t reta;
3245         uint16_t idx, shift;
3246
3247         PMD_INIT_FUNC_TRACE();
3248
3249         if (reta_size != ETH_RSS_RETA_SIZE_128) {
3250                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3251                         "(%d) doesn't match the number hardware can supported "
3252                         "(%d)", reta_size, ETH_RSS_RETA_SIZE_128);
3253                 return -EINVAL;
3254         }
3255
3256         for (i = 0; i < reta_size; i += 4) {
3257                 idx = i / RTE_RETA_GROUP_SIZE;
3258                 shift = i % RTE_RETA_GROUP_SIZE;
3259                 mask = (uint8_t)RS64(reta_conf[idx].mask, shift, 0xF);
3260                 if (!mask)
3261                         continue;
3262
3263                 reta = rd32a(hw, TXGBE_REG_RSSTBL, i >> 2);
3264                 for (j = 0; j < 4; j++) {
3265                         if (RS8(mask, j, 0x1))
3266                                 reta_conf[idx].reta[shift + j] =
3267                                         (uint16_t)RS32(reta, 8 * j, 0xFF);
3268                 }
3269         }
3270
3271         return 0;
3272 }
3273
3274 static int
3275 txgbe_add_rar(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
3276                                 uint32_t index, uint32_t pool)
3277 {
3278         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3279         uint32_t enable_addr = 1;
3280
3281         return txgbe_set_rar(hw, index, mac_addr->addr_bytes,
3282                              pool, enable_addr);
3283 }
3284
3285 static void
3286 txgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
3287 {
3288         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3289
3290         txgbe_clear_rar(hw, index);
3291 }
3292
3293 static int
3294 txgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *addr)
3295 {
3296         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3297
3298         txgbe_remove_rar(dev, 0);
3299         txgbe_add_rar(dev, addr, 0, pci_dev->max_vfs);
3300
3301         return 0;
3302 }
3303
3304 static int
3305 txgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
3306 {
3307         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3308         struct rte_eth_dev_info dev_info;
3309         uint32_t frame_size = mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN;
3310         struct rte_eth_dev_data *dev_data = dev->data;
3311         int ret;
3312
3313         ret = txgbe_dev_info_get(dev, &dev_info);
3314         if (ret != 0)
3315                 return ret;
3316
3317         /* check that mtu is within the allowed range */
3318         if (mtu < RTE_ETHER_MIN_MTU || frame_size > dev_info.max_rx_pktlen)
3319                 return -EINVAL;
3320
3321         /* If device is started, refuse mtu that requires the support of
3322          * scattered packets when this feature has not been enabled before.
3323          */
3324         if (dev_data->dev_started && !dev_data->scattered_rx &&
3325             (frame_size + 2 * TXGBE_VLAN_TAG_SIZE >
3326              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
3327                 PMD_INIT_LOG(ERR, "Stop port first.");
3328                 return -EINVAL;
3329         }
3330
3331         /* update max frame size */
3332         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
3333
3334         if (hw->mode)
3335                 wr32m(hw, TXGBE_FRMSZ, TXGBE_FRMSZ_MAX_MASK,
3336                         TXGBE_FRAME_SIZE_MAX);
3337         else
3338                 wr32m(hw, TXGBE_FRMSZ, TXGBE_FRMSZ_MAX_MASK,
3339                         TXGBE_FRMSZ_MAX(frame_size));
3340
3341         return 0;
3342 }
3343
3344 static uint32_t
3345 txgbe_uta_vector(struct txgbe_hw *hw, struct rte_ether_addr *uc_addr)
3346 {
3347         uint32_t vector = 0;
3348
3349         switch (hw->mac.mc_filter_type) {
3350         case 0:   /* use bits [47:36] of the address */
3351                 vector = ((uc_addr->addr_bytes[4] >> 4) |
3352                         (((uint16_t)uc_addr->addr_bytes[5]) << 4));
3353                 break;
3354         case 1:   /* use bits [46:35] of the address */
3355                 vector = ((uc_addr->addr_bytes[4] >> 3) |
3356                         (((uint16_t)uc_addr->addr_bytes[5]) << 5));
3357                 break;
3358         case 2:   /* use bits [45:34] of the address */
3359                 vector = ((uc_addr->addr_bytes[4] >> 2) |
3360                         (((uint16_t)uc_addr->addr_bytes[5]) << 6));
3361                 break;
3362         case 3:   /* use bits [43:32] of the address */
3363                 vector = ((uc_addr->addr_bytes[4]) |
3364                         (((uint16_t)uc_addr->addr_bytes[5]) << 8));
3365                 break;
3366         default:  /* Invalid mc_filter_type */
3367                 break;
3368         }
3369
3370         /* vector can only be 12-bits or boundary will be exceeded */
3371         vector &= 0xFFF;
3372         return vector;
3373 }
3374
3375 static int
3376 txgbe_uc_hash_table_set(struct rte_eth_dev *dev,
3377                         struct rte_ether_addr *mac_addr, uint8_t on)
3378 {
3379         uint32_t vector;
3380         uint32_t uta_idx;
3381         uint32_t reg_val;
3382         uint32_t uta_mask;
3383         uint32_t psrctl;
3384
3385         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3386         struct txgbe_uta_info *uta_info = TXGBE_DEV_UTA_INFO(dev);
3387
3388         /* The UTA table only exists on pf hardware */
3389         if (hw->mac.type < txgbe_mac_raptor)
3390                 return -ENOTSUP;
3391
3392         vector = txgbe_uta_vector(hw, mac_addr);
3393         uta_idx = (vector >> 5) & 0x7F;
3394         uta_mask = 0x1UL << (vector & 0x1F);
3395
3396         if (!!on == !!(uta_info->uta_shadow[uta_idx] & uta_mask))
3397                 return 0;
3398
3399         reg_val = rd32(hw, TXGBE_UCADDRTBL(uta_idx));
3400         if (on) {
3401                 uta_info->uta_in_use++;
3402                 reg_val |= uta_mask;
3403                 uta_info->uta_shadow[uta_idx] |= uta_mask;
3404         } else {
3405                 uta_info->uta_in_use--;
3406                 reg_val &= ~uta_mask;
3407                 uta_info->uta_shadow[uta_idx] &= ~uta_mask;
3408         }
3409
3410         wr32(hw, TXGBE_UCADDRTBL(uta_idx), reg_val);
3411
3412         psrctl = rd32(hw, TXGBE_PSRCTL);
3413         if (uta_info->uta_in_use > 0)
3414                 psrctl |= TXGBE_PSRCTL_UCHFENA;
3415         else
3416                 psrctl &= ~TXGBE_PSRCTL_UCHFENA;
3417
3418         psrctl &= ~TXGBE_PSRCTL_ADHF12_MASK;
3419         psrctl |= TXGBE_PSRCTL_ADHF12(hw->mac.mc_filter_type);
3420         wr32(hw, TXGBE_PSRCTL, psrctl);
3421
3422         return 0;
3423 }
3424
3425 static int
3426 txgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
3427 {
3428         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3429         struct txgbe_uta_info *uta_info = TXGBE_DEV_UTA_INFO(dev);
3430         uint32_t psrctl;
3431         int i;
3432
3433         /* The UTA table only exists on pf hardware */
3434         if (hw->mac.type < txgbe_mac_raptor)
3435                 return -ENOTSUP;
3436
3437         if (on) {
3438                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
3439                         uta_info->uta_shadow[i] = ~0;
3440                         wr32(hw, TXGBE_UCADDRTBL(i), ~0);
3441                 }
3442         } else {
3443                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
3444                         uta_info->uta_shadow[i] = 0;
3445                         wr32(hw, TXGBE_UCADDRTBL(i), 0);
3446                 }
3447         }
3448
3449         psrctl = rd32(hw, TXGBE_PSRCTL);
3450         if (on)
3451                 psrctl |= TXGBE_PSRCTL_UCHFENA;
3452         else
3453                 psrctl &= ~TXGBE_PSRCTL_UCHFENA;
3454
3455         psrctl &= ~TXGBE_PSRCTL_ADHF12_MASK;
3456         psrctl |= TXGBE_PSRCTL_ADHF12(hw->mac.mc_filter_type);
3457         wr32(hw, TXGBE_PSRCTL, psrctl);
3458
3459         return 0;
3460 }
3461
3462 uint32_t
3463 txgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
3464 {
3465         uint32_t new_val = orig_val;
3466
3467         if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
3468                 new_val |= TXGBE_POOLETHCTL_UTA;
3469         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
3470                 new_val |= TXGBE_POOLETHCTL_MCHA;
3471         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
3472                 new_val |= TXGBE_POOLETHCTL_UCHA;
3473         if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
3474                 new_val |= TXGBE_POOLETHCTL_BCA;
3475         if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
3476                 new_val |= TXGBE_POOLETHCTL_MCP;
3477
3478         return new_val;
3479 }
3480
3481 static int
3482 txgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
3483 {
3484         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3485         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3486         uint32_t mask;
3487         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3488
3489         if (queue_id < 32) {
3490                 mask = rd32(hw, TXGBE_IMS(0));
3491                 mask &= (1 << queue_id);
3492                 wr32(hw, TXGBE_IMS(0), mask);
3493         } else if (queue_id < 64) {
3494                 mask = rd32(hw, TXGBE_IMS(1));
3495                 mask &= (1 << (queue_id - 32));
3496                 wr32(hw, TXGBE_IMS(1), mask);
3497         }
3498         rte_intr_enable(intr_handle);
3499
3500         return 0;
3501 }
3502
3503 static int
3504 txgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
3505 {
3506         uint32_t mask;
3507         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3508
3509         if (queue_id < 32) {
3510                 mask = rd32(hw, TXGBE_IMS(0));
3511                 mask &= ~(1 << queue_id);
3512                 wr32(hw, TXGBE_IMS(0), mask);
3513         } else if (queue_id < 64) {
3514                 mask = rd32(hw, TXGBE_IMS(1));
3515                 mask &= ~(1 << (queue_id - 32));
3516                 wr32(hw, TXGBE_IMS(1), mask);
3517         }
3518
3519         return 0;
3520 }
3521
3522 /**
3523  * set the IVAR registers, mapping interrupt causes to vectors
3524  * @param hw
3525  *  pointer to txgbe_hw struct
3526  * @direction
3527  *  0 for Rx, 1 for Tx, -1 for other causes
3528  * @queue
3529  *  queue to map the corresponding interrupt to
3530  * @msix_vector
3531  *  the vector to map to the corresponding queue
3532  */
3533 void
3534 txgbe_set_ivar_map(struct txgbe_hw *hw, int8_t direction,
3535                    uint8_t queue, uint8_t msix_vector)
3536 {
3537         uint32_t tmp, idx;
3538
3539         if (direction == -1) {
3540                 /* other causes */
3541                 msix_vector |= TXGBE_IVARMISC_VLD;
3542                 idx = 0;
3543                 tmp = rd32(hw, TXGBE_IVARMISC);
3544                 tmp &= ~(0xFF << idx);
3545                 tmp |= (msix_vector << idx);
3546                 wr32(hw, TXGBE_IVARMISC, tmp);
3547         } else {
3548                 /* rx or tx causes */
3549                 /* Workround for ICR lost */
3550                 idx = ((16 * (queue & 1)) + (8 * direction));
3551                 tmp = rd32(hw, TXGBE_IVAR(queue >> 1));
3552                 tmp &= ~(0xFF << idx);
3553                 tmp |= (msix_vector << idx);
3554                 wr32(hw, TXGBE_IVAR(queue >> 1), tmp);
3555         }
3556 }
3557
3558 /**
3559  * Sets up the hardware to properly generate MSI-X interrupts
3560  * @hw
3561  *  board private structure
3562  */
3563 static void
3564 txgbe_configure_msix(struct rte_eth_dev *dev)
3565 {
3566         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3567         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3568         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3569         uint32_t queue_id, base = TXGBE_MISC_VEC_ID;
3570         uint32_t vec = TXGBE_MISC_VEC_ID;
3571         uint32_t gpie;
3572
3573         /* won't configure msix register if no mapping is done
3574          * between intr vector and event fd
3575          * but if misx has been enabled already, need to configure
3576          * auto clean, auto mask and throttling.
3577          */
3578         gpie = rd32(hw, TXGBE_GPIE);
3579         if (!rte_intr_dp_is_en(intr_handle) &&
3580             !(gpie & TXGBE_GPIE_MSIX))
3581                 return;
3582
3583         if (rte_intr_allow_others(intr_handle)) {
3584                 base = TXGBE_RX_VEC_START;
3585                 vec = base;
3586         }
3587
3588         /* setup GPIE for MSI-x mode */
3589         gpie = rd32(hw, TXGBE_GPIE);
3590         gpie |= TXGBE_GPIE_MSIX;
3591         wr32(hw, TXGBE_GPIE, gpie);
3592
3593         /* Populate the IVAR table and set the ITR values to the
3594          * corresponding register.
3595          */
3596         if (rte_intr_dp_is_en(intr_handle)) {
3597                 for (queue_id = 0; queue_id < dev->data->nb_rx_queues;
3598                         queue_id++) {
3599                         /* by default, 1:1 mapping */
3600                         txgbe_set_ivar_map(hw, 0, queue_id, vec);
3601                         intr_handle->intr_vec[queue_id] = vec;
3602                         if (vec < base + intr_handle->nb_efd - 1)
3603                                 vec++;
3604                 }
3605
3606                 txgbe_set_ivar_map(hw, -1, 1, TXGBE_MISC_VEC_ID);
3607         }
3608         wr32(hw, TXGBE_ITR(TXGBE_MISC_VEC_ID),
3609                         TXGBE_ITR_IVAL_10G(TXGBE_QUEUE_ITR_INTERVAL_DEFAULT)
3610                         | TXGBE_ITR_WRDSA);
3611 }
3612
3613 int
3614 txgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
3615                            uint16_t queue_idx, uint16_t tx_rate)
3616 {
3617         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3618         uint32_t bcnrc_val;
3619
3620         if (queue_idx >= hw->mac.max_tx_queues)
3621                 return -EINVAL;
3622
3623         if (tx_rate != 0) {
3624                 bcnrc_val = TXGBE_ARBTXRATE_MAX(tx_rate);
3625                 bcnrc_val |= TXGBE_ARBTXRATE_MIN(tx_rate / 2);
3626         } else {
3627                 bcnrc_val = 0;
3628         }
3629
3630         /*
3631          * Set global transmit compensation time to the MMW_SIZE in ARBTXMMW
3632          * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported.
3633          */
3634         wr32(hw, TXGBE_ARBTXMMW, 0x14);
3635
3636         /* Set ARBTXRATE of queue X */
3637         wr32(hw, TXGBE_ARBPOOLIDX, queue_idx);
3638         wr32(hw, TXGBE_ARBTXRATE, bcnrc_val);
3639         txgbe_flush(hw);
3640
3641         return 0;
3642 }
3643
3644 int
3645 txgbe_syn_filter_set(struct rte_eth_dev *dev,
3646                         struct rte_eth_syn_filter *filter,
3647                         bool add)
3648 {
3649         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3650         struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(dev);
3651         uint32_t syn_info;
3652         uint32_t synqf;
3653
3654         if (filter->queue >= TXGBE_MAX_RX_QUEUE_NUM)
3655                 return -EINVAL;
3656
3657         syn_info = filter_info->syn_info;
3658
3659         if (add) {
3660                 if (syn_info & TXGBE_SYNCLS_ENA)
3661                         return -EINVAL;
3662                 synqf = (uint32_t)TXGBE_SYNCLS_QPID(filter->queue);
3663                 synqf |= TXGBE_SYNCLS_ENA;
3664
3665                 if (filter->hig_pri)
3666                         synqf |= TXGBE_SYNCLS_HIPRIO;
3667                 else
3668                         synqf &= ~TXGBE_SYNCLS_HIPRIO;
3669         } else {
3670                 synqf = rd32(hw, TXGBE_SYNCLS);
3671                 if (!(syn_info & TXGBE_SYNCLS_ENA))
3672                         return -ENOENT;
3673                 synqf &= ~(TXGBE_SYNCLS_QPID_MASK | TXGBE_SYNCLS_ENA);
3674         }
3675
3676         filter_info->syn_info = synqf;
3677         wr32(hw, TXGBE_SYNCLS, synqf);
3678         txgbe_flush(hw);
3679         return 0;
3680 }
3681
3682 static inline enum txgbe_5tuple_protocol
3683 convert_protocol_type(uint8_t protocol_value)
3684 {
3685         if (protocol_value == IPPROTO_TCP)
3686                 return TXGBE_5TF_PROT_TCP;
3687         else if (protocol_value == IPPROTO_UDP)
3688                 return TXGBE_5TF_PROT_UDP;
3689         else if (protocol_value == IPPROTO_SCTP)
3690                 return TXGBE_5TF_PROT_SCTP;
3691         else
3692                 return TXGBE_5TF_PROT_NONE;
3693 }
3694
3695 /* inject a 5-tuple filter to HW */
3696 static inline void
3697 txgbe_inject_5tuple_filter(struct rte_eth_dev *dev,
3698                            struct txgbe_5tuple_filter *filter)
3699 {
3700         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3701         int i;
3702         uint32_t ftqf, sdpqf;
3703         uint32_t l34timir = 0;
3704         uint32_t mask = TXGBE_5TFCTL0_MASK;
3705
3706         i = filter->index;
3707         sdpqf = TXGBE_5TFPORT_DST(be_to_le16(filter->filter_info.dst_port));
3708         sdpqf |= TXGBE_5TFPORT_SRC(be_to_le16(filter->filter_info.src_port));
3709
3710         ftqf = TXGBE_5TFCTL0_PROTO(filter->filter_info.proto);
3711         ftqf |= TXGBE_5TFCTL0_PRI(filter->filter_info.priority);
3712         if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
3713                 mask &= ~TXGBE_5TFCTL0_MSADDR;
3714         if (filter->filter_info.dst_ip_mask == 0)
3715                 mask &= ~TXGBE_5TFCTL0_MDADDR;
3716         if (filter->filter_info.src_port_mask == 0)
3717                 mask &= ~TXGBE_5TFCTL0_MSPORT;
3718         if (filter->filter_info.dst_port_mask == 0)
3719                 mask &= ~TXGBE_5TFCTL0_MDPORT;
3720         if (filter->filter_info.proto_mask == 0)
3721                 mask &= ~TXGBE_5TFCTL0_MPROTO;
3722         ftqf |= mask;
3723         ftqf |= TXGBE_5TFCTL0_MPOOL;
3724         ftqf |= TXGBE_5TFCTL0_ENA;
3725
3726         wr32(hw, TXGBE_5TFDADDR(i), be_to_le32(filter->filter_info.dst_ip));
3727         wr32(hw, TXGBE_5TFSADDR(i), be_to_le32(filter->filter_info.src_ip));
3728         wr32(hw, TXGBE_5TFPORT(i), sdpqf);
3729         wr32(hw, TXGBE_5TFCTL0(i), ftqf);
3730
3731         l34timir |= TXGBE_5TFCTL1_QP(filter->queue);
3732         wr32(hw, TXGBE_5TFCTL1(i), l34timir);
3733 }
3734
3735 /*
3736  * add a 5tuple filter
3737  *
3738  * @param
3739  * dev: Pointer to struct rte_eth_dev.
3740  * index: the index the filter allocates.
3741  * filter: pointer to the filter that will be added.
3742  * rx_queue: the queue id the filter assigned to.
3743  *
3744  * @return
3745  *    - On success, zero.
3746  *    - On failure, a negative value.
3747  */
3748 static int
3749 txgbe_add_5tuple_filter(struct rte_eth_dev *dev,
3750                         struct txgbe_5tuple_filter *filter)
3751 {
3752         struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(dev);
3753         int i, idx, shift;
3754
3755         /*
3756          * look for an unused 5tuple filter index,
3757          * and insert the filter to list.
3758          */
3759         for (i = 0; i < TXGBE_MAX_FTQF_FILTERS; i++) {
3760                 idx = i / (sizeof(uint32_t) * NBBY);
3761                 shift = i % (sizeof(uint32_t) * NBBY);
3762                 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
3763                         filter_info->fivetuple_mask[idx] |= 1 << shift;
3764                         filter->index = i;
3765                         TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
3766                                           filter,
3767                                           entries);
3768                         break;
3769                 }
3770         }
3771         if (i >= TXGBE_MAX_FTQF_FILTERS) {
3772                 PMD_DRV_LOG(ERR, "5tuple filters are full.");
3773                 return -ENOSYS;
3774         }
3775
3776         txgbe_inject_5tuple_filter(dev, filter);
3777
3778         return 0;
3779 }
3780
3781 /*
3782  * remove a 5tuple filter
3783  *
3784  * @param
3785  * dev: Pointer to struct rte_eth_dev.
3786  * filter: the pointer of the filter will be removed.
3787  */
3788 static void
3789 txgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
3790                         struct txgbe_5tuple_filter *filter)
3791 {
3792         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3793         struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(dev);
3794         uint16_t index = filter->index;
3795
3796         filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
3797                                 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
3798         TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
3799         rte_free(filter);
3800
3801         wr32(hw, TXGBE_5TFDADDR(index), 0);
3802         wr32(hw, TXGBE_5TFSADDR(index), 0);
3803         wr32(hw, TXGBE_5TFPORT(index), 0);
3804         wr32(hw, TXGBE_5TFCTL0(index), 0);
3805         wr32(hw, TXGBE_5TFCTL1(index), 0);
3806 }
3807
3808 static inline struct txgbe_5tuple_filter *
3809 txgbe_5tuple_filter_lookup(struct txgbe_5tuple_filter_list *filter_list,
3810                         struct txgbe_5tuple_filter_info *key)
3811 {
3812         struct txgbe_5tuple_filter *it;
3813
3814         TAILQ_FOREACH(it, filter_list, entries) {
3815                 if (memcmp(key, &it->filter_info,
3816                         sizeof(struct txgbe_5tuple_filter_info)) == 0) {
3817                         return it;
3818                 }
3819         }
3820         return NULL;
3821 }
3822
3823 /* translate elements in struct rte_eth_ntuple_filter
3824  * to struct txgbe_5tuple_filter_info
3825  */
3826 static inline int
3827 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
3828                         struct txgbe_5tuple_filter_info *filter_info)
3829 {
3830         if (filter->queue >= TXGBE_MAX_RX_QUEUE_NUM ||
3831                 filter->priority > TXGBE_5TUPLE_MAX_PRI ||
3832                 filter->priority < TXGBE_5TUPLE_MIN_PRI)
3833                 return -EINVAL;
3834
3835         switch (filter->dst_ip_mask) {
3836         case UINT32_MAX:
3837                 filter_info->dst_ip_mask = 0;
3838                 filter_info->dst_ip = filter->dst_ip;
3839                 break;
3840         case 0:
3841                 filter_info->dst_ip_mask = 1;
3842                 break;
3843         default:
3844                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
3845                 return -EINVAL;
3846         }
3847
3848         switch (filter->src_ip_mask) {
3849         case UINT32_MAX:
3850                 filter_info->src_ip_mask = 0;
3851                 filter_info->src_ip = filter->src_ip;
3852                 break;
3853         case 0:
3854                 filter_info->src_ip_mask = 1;
3855                 break;
3856         default:
3857                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
3858                 return -EINVAL;
3859         }
3860
3861         switch (filter->dst_port_mask) {
3862         case UINT16_MAX:
3863                 filter_info->dst_port_mask = 0;
3864                 filter_info->dst_port = filter->dst_port;
3865                 break;
3866         case 0:
3867                 filter_info->dst_port_mask = 1;
3868                 break;
3869         default:
3870                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
3871                 return -EINVAL;
3872         }
3873
3874         switch (filter->src_port_mask) {
3875         case UINT16_MAX:
3876                 filter_info->src_port_mask = 0;
3877                 filter_info->src_port = filter->src_port;
3878                 break;
3879         case 0:
3880                 filter_info->src_port_mask = 1;
3881                 break;
3882         default:
3883                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
3884                 return -EINVAL;
3885         }
3886
3887         switch (filter->proto_mask) {
3888         case UINT8_MAX:
3889                 filter_info->proto_mask = 0;
3890                 filter_info->proto =
3891                         convert_protocol_type(filter->proto);
3892                 break;
3893         case 0:
3894                 filter_info->proto_mask = 1;
3895                 break;
3896         default:
3897                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
3898                 return -EINVAL;
3899         }
3900
3901         filter_info->priority = (uint8_t)filter->priority;
3902         return 0;
3903 }
3904
3905 /*
3906  * add or delete a ntuple filter
3907  *
3908  * @param
3909  * dev: Pointer to struct rte_eth_dev.
3910  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
3911  * add: if true, add filter, if false, remove filter
3912  *
3913  * @return
3914  *    - On success, zero.
3915  *    - On failure, a negative value.
3916  */
3917 int
3918 txgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
3919                         struct rte_eth_ntuple_filter *ntuple_filter,
3920                         bool add)
3921 {
3922         struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(dev);
3923         struct txgbe_5tuple_filter_info filter_5tuple;
3924         struct txgbe_5tuple_filter *filter;
3925         int ret;
3926
3927         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
3928                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
3929                 return -EINVAL;
3930         }
3931
3932         memset(&filter_5tuple, 0, sizeof(struct txgbe_5tuple_filter_info));
3933         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
3934         if (ret < 0)
3935                 return ret;
3936
3937         filter = txgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
3938                                          &filter_5tuple);
3939         if (filter != NULL && add) {
3940                 PMD_DRV_LOG(ERR, "filter exists.");
3941                 return -EEXIST;
3942         }
3943         if (filter == NULL && !add) {
3944                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3945                 return -ENOENT;
3946         }
3947
3948         if (add) {
3949                 filter = rte_zmalloc("txgbe_5tuple_filter",
3950                                 sizeof(struct txgbe_5tuple_filter), 0);
3951                 if (filter == NULL)
3952                         return -ENOMEM;
3953                 rte_memcpy(&filter->filter_info,
3954                                  &filter_5tuple,
3955                                  sizeof(struct txgbe_5tuple_filter_info));
3956                 filter->queue = ntuple_filter->queue;
3957                 ret = txgbe_add_5tuple_filter(dev, filter);
3958                 if (ret < 0) {
3959                         rte_free(filter);
3960                         return ret;
3961                 }
3962         } else {
3963                 txgbe_remove_5tuple_filter(dev, filter);
3964         }
3965
3966         return 0;
3967 }
3968
3969 int
3970 txgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
3971                         struct rte_eth_ethertype_filter *filter,
3972                         bool add)
3973 {
3974         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3975         struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(dev);
3976         uint32_t etqf = 0;
3977         uint32_t etqs = 0;
3978         int ret;
3979         struct txgbe_ethertype_filter ethertype_filter;
3980
3981         if (filter->queue >= TXGBE_MAX_RX_QUEUE_NUM)
3982                 return -EINVAL;
3983
3984         if (filter->ether_type == RTE_ETHER_TYPE_IPV4 ||
3985             filter->ether_type == RTE_ETHER_TYPE_IPV6) {
3986                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
3987                         " ethertype filter.", filter->ether_type);
3988                 return -EINVAL;
3989         }
3990
3991         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
3992                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
3993                 return -EINVAL;
3994         }
3995         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
3996                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
3997                 return -EINVAL;
3998         }
3999
4000         ret = txgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
4001         if (ret >= 0 && add) {
4002                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
4003                             filter->ether_type);
4004                 return -EEXIST;
4005         }
4006         if (ret < 0 && !add) {
4007                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
4008                             filter->ether_type);
4009                 return -ENOENT;
4010         }
4011
4012         if (add) {
4013                 etqf = TXGBE_ETFLT_ENA;
4014                 etqf |= TXGBE_ETFLT_ETID(filter->ether_type);
4015                 etqs |= TXGBE_ETCLS_QPID(filter->queue);
4016                 etqs |= TXGBE_ETCLS_QENA;
4017
4018                 ethertype_filter.ethertype = filter->ether_type;
4019                 ethertype_filter.etqf = etqf;
4020                 ethertype_filter.etqs = etqs;
4021                 ethertype_filter.conf = FALSE;
4022                 ret = txgbe_ethertype_filter_insert(filter_info,
4023                                                     &ethertype_filter);
4024                 if (ret < 0) {
4025                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
4026                         return -ENOSPC;
4027                 }
4028         } else {
4029                 ret = txgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
4030                 if (ret < 0)
4031                         return -ENOSYS;
4032         }
4033         wr32(hw, TXGBE_ETFLT(ret), etqf);
4034         wr32(hw, TXGBE_ETCLS(ret), etqs);
4035         txgbe_flush(hw);
4036
4037         return 0;
4038 }
4039
4040 static int
4041 txgbe_dev_filter_ctrl(__rte_unused struct rte_eth_dev *dev,
4042                      enum rte_filter_type filter_type,
4043                      enum rte_filter_op filter_op,
4044                      void *arg)
4045 {
4046         int ret = 0;
4047
4048         switch (filter_type) {
4049         case RTE_ETH_FILTER_GENERIC:
4050                 if (filter_op != RTE_ETH_FILTER_GET)
4051                         return -EINVAL;
4052                 *(const void **)arg = &txgbe_flow_ops;
4053                 break;
4054         default:
4055                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
4056                                                         filter_type);
4057                 ret = -EINVAL;
4058                 break;
4059         }
4060
4061         return ret;
4062 }
4063
4064 static u8 *
4065 txgbe_dev_addr_list_itr(__rte_unused struct txgbe_hw *hw,
4066                         u8 **mc_addr_ptr, u32 *vmdq)
4067 {
4068         u8 *mc_addr;
4069
4070         *vmdq = 0;
4071         mc_addr = *mc_addr_ptr;
4072         *mc_addr_ptr = (mc_addr + sizeof(struct rte_ether_addr));
4073         return mc_addr;
4074 }
4075
4076 int
4077 txgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
4078                           struct rte_ether_addr *mc_addr_set,
4079                           uint32_t nb_mc_addr)
4080 {
4081         struct txgbe_hw *hw;
4082         u8 *mc_addr_list;
4083
4084         hw = TXGBE_DEV_HW(dev);
4085         mc_addr_list = (u8 *)mc_addr_set;
4086         return txgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
4087                                          txgbe_dev_addr_list_itr, TRUE);
4088 }
4089
4090 static uint64_t
4091 txgbe_read_systime_cyclecounter(struct rte_eth_dev *dev)
4092 {
4093         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4094         uint64_t systime_cycles;
4095
4096         systime_cycles = (uint64_t)rd32(hw, TXGBE_TSTIMEL);
4097         systime_cycles |= (uint64_t)rd32(hw, TXGBE_TSTIMEH) << 32;
4098
4099         return systime_cycles;
4100 }
4101
4102 static uint64_t
4103 txgbe_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
4104 {
4105         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4106         uint64_t rx_tstamp_cycles;
4107
4108         /* TSRXSTMPL stores ns and TSRXSTMPH stores seconds. */
4109         rx_tstamp_cycles = (uint64_t)rd32(hw, TXGBE_TSRXSTMPL);
4110         rx_tstamp_cycles |= (uint64_t)rd32(hw, TXGBE_TSRXSTMPH) << 32;
4111
4112         return rx_tstamp_cycles;
4113 }
4114
4115 static uint64_t
4116 txgbe_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
4117 {
4118         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4119         uint64_t tx_tstamp_cycles;
4120
4121         /* TSTXSTMPL stores ns and TSTXSTMPH stores seconds. */
4122         tx_tstamp_cycles = (uint64_t)rd32(hw, TXGBE_TSTXSTMPL);
4123         tx_tstamp_cycles |= (uint64_t)rd32(hw, TXGBE_TSTXSTMPH) << 32;
4124
4125         return tx_tstamp_cycles;
4126 }
4127
4128 static void
4129 txgbe_start_timecounters(struct rte_eth_dev *dev)
4130 {
4131         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4132         struct txgbe_adapter *adapter = TXGBE_DEV_ADAPTER(dev);
4133         struct rte_eth_link link;
4134         uint32_t incval = 0;
4135         uint32_t shift = 0;
4136
4137         /* Get current link speed. */
4138         txgbe_dev_link_update(dev, 1);
4139         rte_eth_linkstatus_get(dev, &link);
4140
4141         switch (link.link_speed) {
4142         case ETH_SPEED_NUM_100M:
4143                 incval = TXGBE_INCVAL_100;
4144                 shift = TXGBE_INCVAL_SHIFT_100;
4145                 break;
4146         case ETH_SPEED_NUM_1G:
4147                 incval = TXGBE_INCVAL_1GB;
4148                 shift = TXGBE_INCVAL_SHIFT_1GB;
4149                 break;
4150         case ETH_SPEED_NUM_10G:
4151         default:
4152                 incval = TXGBE_INCVAL_10GB;
4153                 shift = TXGBE_INCVAL_SHIFT_10GB;
4154                 break;
4155         }
4156
4157         wr32(hw, TXGBE_TSTIMEINC, TXGBE_TSTIMEINC_VP(incval, 2));
4158
4159         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
4160         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
4161         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
4162
4163         adapter->systime_tc.cc_mask = TXGBE_CYCLECOUNTER_MASK;
4164         adapter->systime_tc.cc_shift = shift;
4165         adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
4166
4167         adapter->rx_tstamp_tc.cc_mask = TXGBE_CYCLECOUNTER_MASK;
4168         adapter->rx_tstamp_tc.cc_shift = shift;
4169         adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
4170
4171         adapter->tx_tstamp_tc.cc_mask = TXGBE_CYCLECOUNTER_MASK;
4172         adapter->tx_tstamp_tc.cc_shift = shift;
4173         adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
4174 }
4175
4176 static int
4177 txgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
4178 {
4179         struct txgbe_adapter *adapter = TXGBE_DEV_ADAPTER(dev);
4180
4181         adapter->systime_tc.nsec += delta;
4182         adapter->rx_tstamp_tc.nsec += delta;
4183         adapter->tx_tstamp_tc.nsec += delta;
4184
4185         return 0;
4186 }
4187
4188 static int
4189 txgbe_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
4190 {
4191         uint64_t ns;
4192         struct txgbe_adapter *adapter = TXGBE_DEV_ADAPTER(dev);
4193
4194         ns = rte_timespec_to_ns(ts);
4195         /* Set the timecounters to a new value. */
4196         adapter->systime_tc.nsec = ns;
4197         adapter->rx_tstamp_tc.nsec = ns;
4198         adapter->tx_tstamp_tc.nsec = ns;
4199
4200         return 0;
4201 }
4202
4203 static int
4204 txgbe_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
4205 {
4206         uint64_t ns, systime_cycles;
4207         struct txgbe_adapter *adapter = TXGBE_DEV_ADAPTER(dev);
4208
4209         systime_cycles = txgbe_read_systime_cyclecounter(dev);
4210         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
4211         *ts = rte_ns_to_timespec(ns);
4212
4213         return 0;
4214 }
4215
4216 static int
4217 txgbe_timesync_enable(struct rte_eth_dev *dev)
4218 {
4219         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4220         uint32_t tsync_ctl;
4221
4222         /* Stop the timesync system time. */
4223         wr32(hw, TXGBE_TSTIMEINC, 0x0);
4224         /* Reset the timesync system time value. */
4225         wr32(hw, TXGBE_TSTIMEL, 0x0);
4226         wr32(hw, TXGBE_TSTIMEH, 0x0);
4227
4228         txgbe_start_timecounters(dev);
4229
4230         /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
4231         wr32(hw, TXGBE_ETFLT(TXGBE_ETF_ID_1588),
4232                 RTE_ETHER_TYPE_1588 | TXGBE_ETFLT_ENA | TXGBE_ETFLT_1588);
4233
4234         /* Enable timestamping of received PTP packets. */
4235         tsync_ctl = rd32(hw, TXGBE_TSRXCTL);
4236         tsync_ctl |= TXGBE_TSRXCTL_ENA;
4237         wr32(hw, TXGBE_TSRXCTL, tsync_ctl);
4238
4239         /* Enable timestamping of transmitted PTP packets. */
4240         tsync_ctl = rd32(hw, TXGBE_TSTXCTL);
4241         tsync_ctl |= TXGBE_TSTXCTL_ENA;
4242         wr32(hw, TXGBE_TSTXCTL, tsync_ctl);
4243
4244         txgbe_flush(hw);
4245
4246         return 0;
4247 }
4248
4249 static int
4250 txgbe_timesync_disable(struct rte_eth_dev *dev)
4251 {
4252         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4253         uint32_t tsync_ctl;
4254
4255         /* Disable timestamping of transmitted PTP packets. */
4256         tsync_ctl = rd32(hw, TXGBE_TSTXCTL);
4257         tsync_ctl &= ~TXGBE_TSTXCTL_ENA;
4258         wr32(hw, TXGBE_TSTXCTL, tsync_ctl);
4259
4260         /* Disable timestamping of received PTP packets. */
4261         tsync_ctl = rd32(hw, TXGBE_TSRXCTL);
4262         tsync_ctl &= ~TXGBE_TSRXCTL_ENA;
4263         wr32(hw, TXGBE_TSRXCTL, tsync_ctl);
4264
4265         /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
4266         wr32(hw, TXGBE_ETFLT(TXGBE_ETF_ID_1588), 0);
4267
4268         /* Stop incrementating the System Time registers. */
4269         wr32(hw, TXGBE_TSTIMEINC, 0);
4270
4271         return 0;
4272 }
4273
4274 static int
4275 txgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
4276                                  struct timespec *timestamp,
4277                                  uint32_t flags __rte_unused)
4278 {
4279         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4280         struct txgbe_adapter *adapter = TXGBE_DEV_ADAPTER(dev);
4281         uint32_t tsync_rxctl;
4282         uint64_t rx_tstamp_cycles;
4283         uint64_t ns;
4284
4285         tsync_rxctl = rd32(hw, TXGBE_TSRXCTL);
4286         if ((tsync_rxctl & TXGBE_TSRXCTL_VLD) == 0)
4287                 return -EINVAL;
4288
4289         rx_tstamp_cycles = txgbe_read_rx_tstamp_cyclecounter(dev);
4290         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
4291         *timestamp = rte_ns_to_timespec(ns);
4292
4293         return  0;
4294 }
4295
4296 static int
4297 txgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
4298                                  struct timespec *timestamp)
4299 {
4300         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4301         struct txgbe_adapter *adapter = TXGBE_DEV_ADAPTER(dev);
4302         uint32_t tsync_txctl;
4303         uint64_t tx_tstamp_cycles;
4304         uint64_t ns;
4305
4306         tsync_txctl = rd32(hw, TXGBE_TSTXCTL);
4307         if ((tsync_txctl & TXGBE_TSTXCTL_VLD) == 0)
4308                 return -EINVAL;
4309
4310         tx_tstamp_cycles = txgbe_read_tx_tstamp_cyclecounter(dev);
4311         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
4312         *timestamp = rte_ns_to_timespec(ns);
4313
4314         return 0;
4315 }
4316
4317 static int
4318 txgbe_get_reg_length(struct rte_eth_dev *dev __rte_unused)
4319 {
4320         int count = 0;
4321         int g_ind = 0;
4322         const struct reg_info *reg_group;
4323         const struct reg_info **reg_set = txgbe_regs_others;
4324
4325         while ((reg_group = reg_set[g_ind++]))
4326                 count += txgbe_regs_group_count(reg_group);
4327
4328         return count;
4329 }
4330
4331 static int
4332 txgbe_get_regs(struct rte_eth_dev *dev,
4333               struct rte_dev_reg_info *regs)
4334 {
4335         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4336         uint32_t *data = regs->data;
4337         int g_ind = 0;
4338         int count = 0;
4339         const struct reg_info *reg_group;
4340         const struct reg_info **reg_set = txgbe_regs_others;
4341
4342         if (data == NULL) {
4343                 regs->length = txgbe_get_reg_length(dev);
4344                 regs->width = sizeof(uint32_t);
4345                 return 0;
4346         }
4347
4348         /* Support only full register dump */
4349         if (regs->length == 0 ||
4350             regs->length == (uint32_t)txgbe_get_reg_length(dev)) {
4351                 regs->version = hw->mac.type << 24 |
4352                                 hw->revision_id << 16 |
4353                                 hw->device_id;
4354                 while ((reg_group = reg_set[g_ind++]))
4355                         count += txgbe_read_regs_group(dev, &data[count],
4356                                                       reg_group);
4357                 return 0;
4358         }
4359
4360         return -ENOTSUP;
4361 }
4362
4363 static int
4364 txgbe_get_eeprom_length(struct rte_eth_dev *dev)
4365 {
4366         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4367
4368         /* Return unit is byte count */
4369         return hw->rom.word_size * 2;
4370 }
4371
4372 static int
4373 txgbe_get_eeprom(struct rte_eth_dev *dev,
4374                 struct rte_dev_eeprom_info *in_eeprom)
4375 {
4376         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4377         struct txgbe_rom_info *eeprom = &hw->rom;
4378         uint16_t *data = in_eeprom->data;
4379         int first, length;
4380
4381         first = in_eeprom->offset >> 1;
4382         length = in_eeprom->length >> 1;
4383         if (first > hw->rom.word_size ||
4384             ((first + length) > hw->rom.word_size))
4385                 return -EINVAL;
4386
4387         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
4388
4389         return eeprom->readw_buffer(hw, first, length, data);
4390 }
4391
4392 static int
4393 txgbe_set_eeprom(struct rte_eth_dev *dev,
4394                 struct rte_dev_eeprom_info *in_eeprom)
4395 {
4396         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4397         struct txgbe_rom_info *eeprom = &hw->rom;
4398         uint16_t *data = in_eeprom->data;
4399         int first, length;
4400
4401         first = in_eeprom->offset >> 1;
4402         length = in_eeprom->length >> 1;
4403         if (first > hw->rom.word_size ||
4404             ((first + length) > hw->rom.word_size))
4405                 return -EINVAL;
4406
4407         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
4408
4409         return eeprom->writew_buffer(hw,  first, length, data);
4410 }
4411
4412 static int
4413 txgbe_get_module_info(struct rte_eth_dev *dev,
4414                       struct rte_eth_dev_module_info *modinfo)
4415 {
4416         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4417         uint32_t status;
4418         uint8_t sff8472_rev, addr_mode;
4419         bool page_swap = false;
4420
4421         /* Check whether we support SFF-8472 or not */
4422         status = hw->phy.read_i2c_eeprom(hw,
4423                                              TXGBE_SFF_SFF_8472_COMP,
4424                                              &sff8472_rev);
4425         if (status != 0)
4426                 return -EIO;
4427
4428         /* addressing mode is not supported */
4429         status = hw->phy.read_i2c_eeprom(hw,
4430                                              TXGBE_SFF_SFF_8472_SWAP,
4431                                              &addr_mode);
4432         if (status != 0)
4433                 return -EIO;
4434
4435         if (addr_mode & TXGBE_SFF_ADDRESSING_MODE) {
4436                 PMD_DRV_LOG(ERR,
4437                             "Address change required to access page 0xA2, "
4438                             "but not supported. Please report the module "
4439                             "type to the driver maintainers.");
4440                 page_swap = true;
4441         }
4442
4443         if (sff8472_rev == TXGBE_SFF_SFF_8472_UNSUP || page_swap) {
4444                 /* We have a SFP, but it does not support SFF-8472 */
4445                 modinfo->type = RTE_ETH_MODULE_SFF_8079;
4446                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
4447         } else {
4448                 /* We have a SFP which supports a revision of SFF-8472. */
4449                 modinfo->type = RTE_ETH_MODULE_SFF_8472;
4450                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
4451         }
4452
4453         return 0;
4454 }
4455
4456 static int
4457 txgbe_get_module_eeprom(struct rte_eth_dev *dev,
4458                         struct rte_dev_eeprom_info *info)
4459 {
4460         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4461         uint32_t status = TXGBE_ERR_PHY_ADDR_INVALID;
4462         uint8_t databyte = 0xFF;
4463         uint8_t *data = info->data;
4464         uint32_t i = 0;
4465
4466         if (info->length == 0)
4467                 return -EINVAL;
4468
4469         for (i = info->offset; i < info->offset + info->length; i++) {
4470                 if (i < RTE_ETH_MODULE_SFF_8079_LEN)
4471                         status = hw->phy.read_i2c_eeprom(hw, i, &databyte);
4472                 else
4473                         status = hw->phy.read_i2c_sff8472(hw, i, &databyte);
4474
4475                 if (status != 0)
4476                         return -EIO;
4477
4478                 data[i - info->offset] = databyte;
4479         }
4480
4481         return 0;
4482 }
4483
4484 bool
4485 txgbe_rss_update_sp(enum txgbe_mac_type mac_type)
4486 {
4487         switch (mac_type) {
4488         case txgbe_mac_raptor:
4489                 return 1;
4490         default:
4491                 return 0;
4492         }
4493 }
4494
4495 static int
4496 txgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
4497                         struct rte_eth_dcb_info *dcb_info)
4498 {
4499         struct txgbe_dcb_config *dcb_config = TXGBE_DEV_DCB_CONFIG(dev);
4500         struct txgbe_dcb_tc_config *tc;
4501         struct rte_eth_dcb_tc_queue_mapping *tc_queue;
4502         uint8_t nb_tcs;
4503         uint8_t i, j;
4504
4505         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
4506                 dcb_info->nb_tcs = dcb_config->num_tcs.pg_tcs;
4507         else
4508                 dcb_info->nb_tcs = 1;
4509
4510         tc_queue = &dcb_info->tc_queue;
4511         nb_tcs = dcb_info->nb_tcs;
4512
4513         if (dcb_config->vt_mode) { /* vt is enabled */
4514                 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
4515                                 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
4516                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
4517                         dcb_info->prio_tc[i] = vmdq_rx_conf->dcb_tc[i];
4518                 if (RTE_ETH_DEV_SRIOV(dev).active > 0) {
4519                         for (j = 0; j < nb_tcs; j++) {
4520                                 tc_queue->tc_rxq[0][j].base = j;
4521                                 tc_queue->tc_rxq[0][j].nb_queue = 1;
4522                                 tc_queue->tc_txq[0][j].base = j;
4523                                 tc_queue->tc_txq[0][j].nb_queue = 1;
4524                         }
4525                 } else {
4526                         for (i = 0; i < vmdq_rx_conf->nb_queue_pools; i++) {
4527                                 for (j = 0; j < nb_tcs; j++) {
4528                                         tc_queue->tc_rxq[i][j].base =
4529                                                 i * nb_tcs + j;
4530                                         tc_queue->tc_rxq[i][j].nb_queue = 1;
4531                                         tc_queue->tc_txq[i][j].base =
4532                                                 i * nb_tcs + j;
4533                                         tc_queue->tc_txq[i][j].nb_queue = 1;
4534                                 }
4535                         }
4536                 }
4537         } else { /* vt is disabled */
4538                 struct rte_eth_dcb_rx_conf *rx_conf =
4539                                 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
4540                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
4541                         dcb_info->prio_tc[i] = rx_conf->dcb_tc[i];
4542                 if (dcb_info->nb_tcs == ETH_4_TCS) {
4543                         for (i = 0; i < dcb_info->nb_tcs; i++) {
4544                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 32;
4545                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
4546                         }
4547                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
4548                         dcb_info->tc_queue.tc_txq[0][1].base = 64;
4549                         dcb_info->tc_queue.tc_txq[0][2].base = 96;
4550                         dcb_info->tc_queue.tc_txq[0][3].base = 112;
4551                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 64;
4552                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
4553                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
4554                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
4555                 } else if (dcb_info->nb_tcs == ETH_8_TCS) {
4556                         for (i = 0; i < dcb_info->nb_tcs; i++) {
4557                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 16;
4558                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
4559                         }
4560                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
4561                         dcb_info->tc_queue.tc_txq[0][1].base = 32;
4562                         dcb_info->tc_queue.tc_txq[0][2].base = 64;
4563                         dcb_info->tc_queue.tc_txq[0][3].base = 80;
4564                         dcb_info->tc_queue.tc_txq[0][4].base = 96;
4565                         dcb_info->tc_queue.tc_txq[0][5].base = 104;
4566                         dcb_info->tc_queue.tc_txq[0][6].base = 112;
4567                         dcb_info->tc_queue.tc_txq[0][7].base = 120;
4568                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 32;
4569                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
4570                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
4571                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
4572                         dcb_info->tc_queue.tc_txq[0][4].nb_queue = 8;
4573                         dcb_info->tc_queue.tc_txq[0][5].nb_queue = 8;
4574                         dcb_info->tc_queue.tc_txq[0][6].nb_queue = 8;
4575                         dcb_info->tc_queue.tc_txq[0][7].nb_queue = 8;
4576                 }
4577         }
4578         for (i = 0; i < dcb_info->nb_tcs; i++) {
4579                 tc = &dcb_config->tc_config[i];
4580                 dcb_info->tc_bws[i] = tc->path[TXGBE_DCB_TX_CONFIG].bwg_percent;
4581         }
4582         return 0;
4583 }
4584
4585 /* Update e-tag ether type */
4586 static int
4587 txgbe_update_e_tag_eth_type(struct txgbe_hw *hw,
4588                             uint16_t ether_type)
4589 {
4590         uint32_t etag_etype;
4591
4592         etag_etype = rd32(hw, TXGBE_EXTAG);
4593         etag_etype &= ~TXGBE_EXTAG_ETAG_MASK;
4594         etag_etype |= ether_type;
4595         wr32(hw, TXGBE_EXTAG, etag_etype);
4596         txgbe_flush(hw);
4597
4598         return 0;
4599 }
4600
4601 /* Enable e-tag tunnel */
4602 static int
4603 txgbe_e_tag_enable(struct txgbe_hw *hw)
4604 {
4605         uint32_t etag_etype;
4606
4607         etag_etype = rd32(hw, TXGBE_PORTCTL);
4608         etag_etype |= TXGBE_PORTCTL_ETAG;
4609         wr32(hw, TXGBE_PORTCTL, etag_etype);
4610         txgbe_flush(hw);
4611
4612         return 0;
4613 }
4614
4615 static int
4616 txgbe_e_tag_filter_del(struct rte_eth_dev *dev,
4617                        struct txgbe_l2_tunnel_conf  *l2_tunnel)
4618 {
4619         int ret = 0;
4620         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4621         uint32_t i, rar_entries;
4622         uint32_t rar_low, rar_high;
4623
4624         rar_entries = hw->mac.num_rar_entries;
4625
4626         for (i = 1; i < rar_entries; i++) {
4627                 wr32(hw, TXGBE_ETHADDRIDX, i);
4628                 rar_high = rd32(hw, TXGBE_ETHADDRH);
4629                 rar_low  = rd32(hw, TXGBE_ETHADDRL);
4630                 if ((rar_high & TXGBE_ETHADDRH_VLD) &&
4631                     (rar_high & TXGBE_ETHADDRH_ETAG) &&
4632                     (TXGBE_ETHADDRL_ETAG(rar_low) ==
4633                      l2_tunnel->tunnel_id)) {
4634                         wr32(hw, TXGBE_ETHADDRL, 0);
4635                         wr32(hw, TXGBE_ETHADDRH, 0);
4636
4637                         txgbe_clear_vmdq(hw, i, BIT_MASK32);
4638
4639                         return ret;
4640                 }
4641         }
4642
4643         return ret;
4644 }
4645
4646 static int
4647 txgbe_e_tag_filter_add(struct rte_eth_dev *dev,
4648                        struct txgbe_l2_tunnel_conf *l2_tunnel)
4649 {
4650         int ret = 0;
4651         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4652         uint32_t i, rar_entries;
4653         uint32_t rar_low, rar_high;
4654
4655         /* One entry for one tunnel. Try to remove potential existing entry. */
4656         txgbe_e_tag_filter_del(dev, l2_tunnel);
4657
4658         rar_entries = hw->mac.num_rar_entries;
4659
4660         for (i = 1; i < rar_entries; i++) {
4661                 wr32(hw, TXGBE_ETHADDRIDX, i);
4662                 rar_high = rd32(hw, TXGBE_ETHADDRH);
4663                 if (rar_high & TXGBE_ETHADDRH_VLD) {
4664                         continue;
4665                 } else {
4666                         txgbe_set_vmdq(hw, i, l2_tunnel->pool);
4667                         rar_high = TXGBE_ETHADDRH_VLD | TXGBE_ETHADDRH_ETAG;
4668                         rar_low = l2_tunnel->tunnel_id;
4669
4670                         wr32(hw, TXGBE_ETHADDRL, rar_low);
4671                         wr32(hw, TXGBE_ETHADDRH, rar_high);
4672
4673                         return ret;
4674                 }
4675         }
4676
4677         PMD_INIT_LOG(NOTICE, "The table of E-tag forwarding rule is full."
4678                      " Please remove a rule before adding a new one.");
4679         return -EINVAL;
4680 }
4681
4682 static inline struct txgbe_l2_tn_filter *
4683 txgbe_l2_tn_filter_lookup(struct txgbe_l2_tn_info *l2_tn_info,
4684                           struct txgbe_l2_tn_key *key)
4685 {
4686         int ret;
4687
4688         ret = rte_hash_lookup(l2_tn_info->hash_handle, (const void *)key);
4689         if (ret < 0)
4690                 return NULL;
4691
4692         return l2_tn_info->hash_map[ret];
4693 }
4694
4695 static inline int
4696 txgbe_insert_l2_tn_filter(struct txgbe_l2_tn_info *l2_tn_info,
4697                           struct txgbe_l2_tn_filter *l2_tn_filter)
4698 {
4699         int ret;
4700
4701         ret = rte_hash_add_key(l2_tn_info->hash_handle,
4702                                &l2_tn_filter->key);
4703
4704         if (ret < 0) {
4705                 PMD_DRV_LOG(ERR,
4706                             "Failed to insert L2 tunnel filter"
4707                             " to hash table %d!",
4708                             ret);
4709                 return ret;
4710         }
4711
4712         l2_tn_info->hash_map[ret] = l2_tn_filter;
4713
4714         TAILQ_INSERT_TAIL(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
4715
4716         return 0;
4717 }
4718
4719 static inline int
4720 txgbe_remove_l2_tn_filter(struct txgbe_l2_tn_info *l2_tn_info,
4721                           struct txgbe_l2_tn_key *key)
4722 {
4723         int ret;
4724         struct txgbe_l2_tn_filter *l2_tn_filter;
4725
4726         ret = rte_hash_del_key(l2_tn_info->hash_handle, key);
4727
4728         if (ret < 0) {
4729                 PMD_DRV_LOG(ERR,
4730                             "No such L2 tunnel filter to delete %d!",
4731                             ret);
4732                 return ret;
4733         }
4734
4735         l2_tn_filter = l2_tn_info->hash_map[ret];
4736         l2_tn_info->hash_map[ret] = NULL;
4737
4738         TAILQ_REMOVE(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
4739         rte_free(l2_tn_filter);
4740
4741         return 0;
4742 }
4743
4744 /* Add l2 tunnel filter */
4745 int
4746 txgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev,
4747                                struct txgbe_l2_tunnel_conf *l2_tunnel,
4748                                bool restore)
4749 {
4750         int ret;
4751         struct txgbe_l2_tn_info *l2_tn_info = TXGBE_DEV_L2_TN(dev);
4752         struct txgbe_l2_tn_key key;
4753         struct txgbe_l2_tn_filter *node;
4754
4755         if (!restore) {
4756                 key.l2_tn_type = l2_tunnel->l2_tunnel_type;
4757                 key.tn_id = l2_tunnel->tunnel_id;
4758
4759                 node = txgbe_l2_tn_filter_lookup(l2_tn_info, &key);
4760
4761                 if (node) {
4762                         PMD_DRV_LOG(ERR,
4763                                     "The L2 tunnel filter already exists!");
4764                         return -EINVAL;
4765                 }
4766
4767                 node = rte_zmalloc("txgbe_l2_tn",
4768                                    sizeof(struct txgbe_l2_tn_filter),
4769                                    0);
4770                 if (!node)
4771                         return -ENOMEM;
4772
4773                 rte_memcpy(&node->key,
4774                                  &key,
4775                                  sizeof(struct txgbe_l2_tn_key));
4776                 node->pool = l2_tunnel->pool;
4777                 ret = txgbe_insert_l2_tn_filter(l2_tn_info, node);
4778                 if (ret < 0) {
4779                         rte_free(node);
4780                         return ret;
4781                 }
4782         }
4783
4784         switch (l2_tunnel->l2_tunnel_type) {
4785         case RTE_L2_TUNNEL_TYPE_E_TAG:
4786                 ret = txgbe_e_tag_filter_add(dev, l2_tunnel);
4787                 break;
4788         default:
4789                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
4790                 ret = -EINVAL;
4791                 break;
4792         }
4793
4794         if (!restore && ret < 0)
4795                 (void)txgbe_remove_l2_tn_filter(l2_tn_info, &key);
4796
4797         return ret;
4798 }
4799
4800 /* Delete l2 tunnel filter */
4801 int
4802 txgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev,
4803                                struct txgbe_l2_tunnel_conf *l2_tunnel)
4804 {
4805         int ret;
4806         struct txgbe_l2_tn_info *l2_tn_info = TXGBE_DEV_L2_TN(dev);
4807         struct txgbe_l2_tn_key key;
4808
4809         key.l2_tn_type = l2_tunnel->l2_tunnel_type;
4810         key.tn_id = l2_tunnel->tunnel_id;
4811         ret = txgbe_remove_l2_tn_filter(l2_tn_info, &key);
4812         if (ret < 0)
4813                 return ret;
4814
4815         switch (l2_tunnel->l2_tunnel_type) {
4816         case RTE_L2_TUNNEL_TYPE_E_TAG:
4817                 ret = txgbe_e_tag_filter_del(dev, l2_tunnel);
4818                 break;
4819         default:
4820                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
4821                 ret = -EINVAL;
4822                 break;
4823         }
4824
4825         return ret;
4826 }
4827
4828 static int
4829 txgbe_e_tag_forwarding_en_dis(struct rte_eth_dev *dev, bool en)
4830 {
4831         int ret = 0;
4832         uint32_t ctrl;
4833         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4834
4835         ctrl = rd32(hw, TXGBE_POOLCTL);
4836         ctrl &= ~TXGBE_POOLCTL_MODE_MASK;
4837         if (en)
4838                 ctrl |= TXGBE_PSRPOOL_MODE_ETAG;
4839         wr32(hw, TXGBE_POOLCTL, ctrl);
4840
4841         return ret;
4842 }
4843
4844 /* restore n-tuple filter */
4845 static inline void
4846 txgbe_ntuple_filter_restore(struct rte_eth_dev *dev)
4847 {
4848         struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(dev);
4849         struct txgbe_5tuple_filter *node;
4850
4851         TAILQ_FOREACH(node, &filter_info->fivetuple_list, entries) {
4852                 txgbe_inject_5tuple_filter(dev, node);
4853         }
4854 }
4855
4856 /* restore ethernet type filter */
4857 static inline void
4858 txgbe_ethertype_filter_restore(struct rte_eth_dev *dev)
4859 {
4860         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4861         struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(dev);
4862         int i;
4863
4864         for (i = 0; i < TXGBE_ETF_ID_MAX; i++) {
4865                 if (filter_info->ethertype_mask & (1 << i)) {
4866                         wr32(hw, TXGBE_ETFLT(i),
4867                                         filter_info->ethertype_filters[i].etqf);
4868                         wr32(hw, TXGBE_ETCLS(i),
4869                                         filter_info->ethertype_filters[i].etqs);
4870                         txgbe_flush(hw);
4871                 }
4872         }
4873 }
4874
4875 /* restore SYN filter */
4876 static inline void
4877 txgbe_syn_filter_restore(struct rte_eth_dev *dev)
4878 {
4879         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4880         struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(dev);
4881         uint32_t synqf;
4882
4883         synqf = filter_info->syn_info;
4884
4885         if (synqf & TXGBE_SYNCLS_ENA) {
4886                 wr32(hw, TXGBE_SYNCLS, synqf);
4887                 txgbe_flush(hw);
4888         }
4889 }
4890
4891 /* restore L2 tunnel filter */
4892 static inline void
4893 txgbe_l2_tn_filter_restore(struct rte_eth_dev *dev)
4894 {
4895         struct txgbe_l2_tn_info *l2_tn_info = TXGBE_DEV_L2_TN(dev);
4896         struct txgbe_l2_tn_filter *node;
4897         struct txgbe_l2_tunnel_conf l2_tn_conf;
4898
4899         TAILQ_FOREACH(node, &l2_tn_info->l2_tn_list, entries) {
4900                 l2_tn_conf.l2_tunnel_type = node->key.l2_tn_type;
4901                 l2_tn_conf.tunnel_id      = node->key.tn_id;
4902                 l2_tn_conf.pool           = node->pool;
4903                 (void)txgbe_dev_l2_tunnel_filter_add(dev, &l2_tn_conf, TRUE);
4904         }
4905 }
4906
4907 static int
4908 txgbe_filter_restore(struct rte_eth_dev *dev)
4909 {
4910         txgbe_ntuple_filter_restore(dev);
4911         txgbe_ethertype_filter_restore(dev);
4912         txgbe_syn_filter_restore(dev);
4913         txgbe_l2_tn_filter_restore(dev);
4914
4915         return 0;
4916 }
4917
4918 static void
4919 txgbe_l2_tunnel_conf(struct rte_eth_dev *dev)
4920 {
4921         struct txgbe_l2_tn_info *l2_tn_info = TXGBE_DEV_L2_TN(dev);
4922         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4923
4924         if (l2_tn_info->e_tag_en)
4925                 (void)txgbe_e_tag_enable(hw);
4926
4927         if (l2_tn_info->e_tag_fwd_en)
4928                 (void)txgbe_e_tag_forwarding_en_dis(dev, 1);
4929
4930         (void)txgbe_update_e_tag_eth_type(hw, l2_tn_info->e_tag_ether_type);
4931 }
4932
4933 static const struct eth_dev_ops txgbe_eth_dev_ops = {
4934         .dev_configure              = txgbe_dev_configure,
4935         .dev_infos_get              = txgbe_dev_info_get,
4936         .dev_start                  = txgbe_dev_start,
4937         .dev_stop                   = txgbe_dev_stop,
4938         .dev_set_link_up            = txgbe_dev_set_link_up,
4939         .dev_set_link_down          = txgbe_dev_set_link_down,
4940         .dev_close                  = txgbe_dev_close,
4941         .dev_reset                  = txgbe_dev_reset,
4942         .promiscuous_enable         = txgbe_dev_promiscuous_enable,
4943         .promiscuous_disable        = txgbe_dev_promiscuous_disable,
4944         .allmulticast_enable        = txgbe_dev_allmulticast_enable,
4945         .allmulticast_disable       = txgbe_dev_allmulticast_disable,
4946         .link_update                = txgbe_dev_link_update,
4947         .stats_get                  = txgbe_dev_stats_get,
4948         .xstats_get                 = txgbe_dev_xstats_get,
4949         .xstats_get_by_id           = txgbe_dev_xstats_get_by_id,
4950         .stats_reset                = txgbe_dev_stats_reset,
4951         .xstats_reset               = txgbe_dev_xstats_reset,
4952         .xstats_get_names           = txgbe_dev_xstats_get_names,
4953         .xstats_get_names_by_id     = txgbe_dev_xstats_get_names_by_id,
4954         .queue_stats_mapping_set    = txgbe_dev_queue_stats_mapping_set,
4955         .fw_version_get             = txgbe_fw_version_get,
4956         .dev_supported_ptypes_get   = txgbe_dev_supported_ptypes_get,
4957         .mtu_set                    = txgbe_dev_mtu_set,
4958         .vlan_filter_set            = txgbe_vlan_filter_set,
4959         .vlan_tpid_set              = txgbe_vlan_tpid_set,
4960         .vlan_offload_set           = txgbe_vlan_offload_set,
4961         .vlan_strip_queue_set       = txgbe_vlan_strip_queue_set,
4962         .rx_queue_start             = txgbe_dev_rx_queue_start,
4963         .rx_queue_stop              = txgbe_dev_rx_queue_stop,
4964         .tx_queue_start             = txgbe_dev_tx_queue_start,
4965         .tx_queue_stop              = txgbe_dev_tx_queue_stop,
4966         .rx_queue_setup             = txgbe_dev_rx_queue_setup,
4967         .rx_queue_intr_enable       = txgbe_dev_rx_queue_intr_enable,
4968         .rx_queue_intr_disable      = txgbe_dev_rx_queue_intr_disable,
4969         .rx_queue_release           = txgbe_dev_rx_queue_release,
4970         .tx_queue_setup             = txgbe_dev_tx_queue_setup,
4971         .tx_queue_release           = txgbe_dev_tx_queue_release,
4972         .dev_led_on                 = txgbe_dev_led_on,
4973         .dev_led_off                = txgbe_dev_led_off,
4974         .flow_ctrl_get              = txgbe_flow_ctrl_get,
4975         .flow_ctrl_set              = txgbe_flow_ctrl_set,
4976         .priority_flow_ctrl_set     = txgbe_priority_flow_ctrl_set,
4977         .mac_addr_add               = txgbe_add_rar,
4978         .mac_addr_remove            = txgbe_remove_rar,
4979         .mac_addr_set               = txgbe_set_default_mac_addr,
4980         .uc_hash_table_set          = txgbe_uc_hash_table_set,
4981         .uc_all_hash_table_set      = txgbe_uc_all_hash_table_set,
4982         .set_queue_rate_limit       = txgbe_set_queue_rate_limit,
4983         .reta_update                = txgbe_dev_rss_reta_update,
4984         .reta_query                 = txgbe_dev_rss_reta_query,
4985         .rss_hash_update            = txgbe_dev_rss_hash_update,
4986         .rss_hash_conf_get          = txgbe_dev_rss_hash_conf_get,
4987         .filter_ctrl                = txgbe_dev_filter_ctrl,
4988         .set_mc_addr_list           = txgbe_dev_set_mc_addr_list,
4989         .rxq_info_get               = txgbe_rxq_info_get,
4990         .txq_info_get               = txgbe_txq_info_get,
4991         .timesync_enable            = txgbe_timesync_enable,
4992         .timesync_disable           = txgbe_timesync_disable,
4993         .timesync_read_rx_timestamp = txgbe_timesync_read_rx_timestamp,
4994         .timesync_read_tx_timestamp = txgbe_timesync_read_tx_timestamp,
4995         .get_reg                    = txgbe_get_regs,
4996         .get_eeprom_length          = txgbe_get_eeprom_length,
4997         .get_eeprom                 = txgbe_get_eeprom,
4998         .set_eeprom                 = txgbe_set_eeprom,
4999         .get_module_info            = txgbe_get_module_info,
5000         .get_module_eeprom          = txgbe_get_module_eeprom,
5001         .get_dcb_info               = txgbe_dev_get_dcb_info,
5002         .timesync_adjust_time       = txgbe_timesync_adjust_time,
5003         .timesync_read_time         = txgbe_timesync_read_time,
5004         .timesync_write_time        = txgbe_timesync_write_time,
5005         .tx_done_cleanup            = txgbe_dev_tx_done_cleanup,
5006 };
5007
5008 RTE_PMD_REGISTER_PCI(net_txgbe, rte_txgbe_pmd);
5009 RTE_PMD_REGISTER_PCI_TABLE(net_txgbe, pci_id_txgbe_map);
5010 RTE_PMD_REGISTER_KMOD_DEP(net_txgbe, "* igb_uio | uio_pci_generic | vfio-pci");
5011
5012 RTE_LOG_REGISTER(txgbe_logtype_init, pmd.net.txgbe.init, NOTICE);
5013 RTE_LOG_REGISTER(txgbe_logtype_driver, pmd.net.txgbe.driver, NOTICE);
5014
5015 #ifdef RTE_LIBRTE_TXGBE_DEBUG_RX
5016         RTE_LOG_REGISTER(txgbe_logtype_rx, pmd.net.txgbe.rx, DEBUG);
5017 #endif
5018 #ifdef RTE_LIBRTE_TXGBE_DEBUG_TX
5019         RTE_LOG_REGISTER(txgbe_logtype_tx, pmd.net.txgbe.tx, DEBUG);
5020 #endif
5021
5022 #ifdef RTE_LIBRTE_TXGBE_DEBUG_TX_FREE
5023         RTE_LOG_REGISTER(txgbe_logtype_tx_free, pmd.net.txgbe.tx_free, DEBUG);
5024 #endif