1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2015-2020 Beijing WangXun Technology Co., Ltd.
3 * Copyright(c) 2010-2017 Intel Corporation
10 #include <rte_common.h>
11 #include <ethdev_pci.h>
13 #include <rte_interrupts.h>
15 #include <rte_debug.h>
17 #include <rte_memory.h>
19 #include <rte_alarm.h>
20 #include <rte_kvargs.h>
22 #include "txgbe_logs.h"
23 #include "base/txgbe.h"
24 #include "txgbe_ethdev.h"
25 #include "txgbe_rxtx.h"
26 #include "txgbe_regs_group.h"
28 static const struct reg_info txgbe_regs_general[] = {
29 {TXGBE_RST, 1, 1, "TXGBE_RST"},
30 {TXGBE_STAT, 1, 1, "TXGBE_STAT"},
31 {TXGBE_PORTCTL, 1, 1, "TXGBE_PORTCTL"},
32 {TXGBE_SDP, 1, 1, "TXGBE_SDP"},
33 {TXGBE_SDPCTL, 1, 1, "TXGBE_SDPCTL"},
34 {TXGBE_LEDCTL, 1, 1, "TXGBE_LEDCTL"},
38 static const struct reg_info txgbe_regs_nvm[] = {
42 static const struct reg_info txgbe_regs_interrupt[] = {
46 static const struct reg_info txgbe_regs_fctl_others[] = {
50 static const struct reg_info txgbe_regs_rxdma[] = {
54 static const struct reg_info txgbe_regs_rx[] = {
58 static struct reg_info txgbe_regs_tx[] = {
62 static const struct reg_info txgbe_regs_wakeup[] = {
66 static const struct reg_info txgbe_regs_dcb[] = {
70 static const struct reg_info txgbe_regs_mac[] = {
74 static const struct reg_info txgbe_regs_diagnostic[] = {
79 static const struct reg_info *txgbe_regs_others[] = {
83 txgbe_regs_fctl_others,
90 txgbe_regs_diagnostic,
93 static int txgbe_fdir_filter_init(struct rte_eth_dev *eth_dev);
94 static int txgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev);
95 static int txgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev);
96 static int txgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev);
97 static int txgbe_dev_set_link_up(struct rte_eth_dev *dev);
98 static int txgbe_dev_set_link_down(struct rte_eth_dev *dev);
99 static int txgbe_dev_close(struct rte_eth_dev *dev);
100 static int txgbe_dev_link_update(struct rte_eth_dev *dev,
101 int wait_to_complete);
102 static int txgbe_dev_stats_reset(struct rte_eth_dev *dev);
103 static void txgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
104 static void txgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev,
107 static void txgbe_dev_link_status_print(struct rte_eth_dev *dev);
108 static int txgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on);
109 static int txgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev);
110 static int txgbe_dev_misc_interrupt_setup(struct rte_eth_dev *dev);
111 static int txgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
112 static int txgbe_dev_interrupt_get_status(struct rte_eth_dev *dev,
113 struct rte_intr_handle *handle);
114 static int txgbe_dev_interrupt_action(struct rte_eth_dev *dev,
115 struct rte_intr_handle *handle);
116 static void txgbe_dev_interrupt_handler(void *param);
117 static void txgbe_dev_interrupt_delayed_handler(void *param);
118 static void txgbe_configure_msix(struct rte_eth_dev *dev);
120 static int txgbe_filter_restore(struct rte_eth_dev *dev);
121 static void txgbe_l2_tunnel_conf(struct rte_eth_dev *dev);
123 #define TXGBE_SET_HWSTRIP(h, q) do {\
124 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
125 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
126 (h)->bitmap[idx] |= 1 << bit;\
129 #define TXGBE_CLEAR_HWSTRIP(h, q) do {\
130 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
131 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
132 (h)->bitmap[idx] &= ~(1 << bit);\
135 #define TXGBE_GET_HWSTRIP(h, q, r) do {\
136 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
137 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
138 (r) = (h)->bitmap[idx] >> bit & 1;\
142 * The set of PCI devices this driver supports
144 static const struct rte_pci_id pci_id_txgbe_map[] = {
145 { RTE_PCI_DEVICE(PCI_VENDOR_ID_WANGXUN, TXGBE_DEV_ID_SP1000) },
146 { RTE_PCI_DEVICE(PCI_VENDOR_ID_WANGXUN, TXGBE_DEV_ID_WX1820) },
147 { .vendor_id = 0, /* sentinel */ },
150 static const struct rte_eth_desc_lim rx_desc_lim = {
151 .nb_max = TXGBE_RING_DESC_MAX,
152 .nb_min = TXGBE_RING_DESC_MIN,
153 .nb_align = TXGBE_RXD_ALIGN,
156 static const struct rte_eth_desc_lim tx_desc_lim = {
157 .nb_max = TXGBE_RING_DESC_MAX,
158 .nb_min = TXGBE_RING_DESC_MIN,
159 .nb_align = TXGBE_TXD_ALIGN,
160 .nb_seg_max = TXGBE_TX_MAX_SEG,
161 .nb_mtu_seg_max = TXGBE_TX_MAX_SEG,
164 static const struct eth_dev_ops txgbe_eth_dev_ops;
166 #define HW_XSTAT(m) {#m, offsetof(struct txgbe_hw_stats, m)}
167 #define HW_XSTAT_NAME(m, n) {n, offsetof(struct txgbe_hw_stats, m)}
168 static const struct rte_txgbe_xstats_name_off rte_txgbe_stats_strings[] = {
170 HW_XSTAT(mng_bmc2host_packets),
171 HW_XSTAT(mng_host2bmc_packets),
173 HW_XSTAT(rx_packets),
174 HW_XSTAT(tx_packets),
177 HW_XSTAT(rx_total_bytes),
178 HW_XSTAT(rx_total_packets),
179 HW_XSTAT(tx_total_packets),
180 HW_XSTAT(rx_total_missed_packets),
181 HW_XSTAT(rx_broadcast_packets),
182 HW_XSTAT(rx_multicast_packets),
183 HW_XSTAT(rx_management_packets),
184 HW_XSTAT(tx_management_packets),
185 HW_XSTAT(rx_management_dropped),
188 HW_XSTAT(rx_crc_errors),
189 HW_XSTAT(rx_illegal_byte_errors),
190 HW_XSTAT(rx_error_bytes),
191 HW_XSTAT(rx_mac_short_packet_dropped),
192 HW_XSTAT(rx_length_errors),
193 HW_XSTAT(rx_undersize_errors),
194 HW_XSTAT(rx_fragment_errors),
195 HW_XSTAT(rx_oversize_errors),
196 HW_XSTAT(rx_jabber_errors),
197 HW_XSTAT(rx_l3_l4_xsum_error),
198 HW_XSTAT(mac_local_errors),
199 HW_XSTAT(mac_remote_errors),
202 HW_XSTAT(flow_director_added_filters),
203 HW_XSTAT(flow_director_removed_filters),
204 HW_XSTAT(flow_director_filter_add_errors),
205 HW_XSTAT(flow_director_filter_remove_errors),
206 HW_XSTAT(flow_director_matched_filters),
207 HW_XSTAT(flow_director_missed_filters),
210 HW_XSTAT(rx_fcoe_crc_errors),
211 HW_XSTAT(rx_fcoe_mbuf_allocation_errors),
212 HW_XSTAT(rx_fcoe_dropped),
213 HW_XSTAT(rx_fcoe_packets),
214 HW_XSTAT(tx_fcoe_packets),
215 HW_XSTAT(rx_fcoe_bytes),
216 HW_XSTAT(tx_fcoe_bytes),
217 HW_XSTAT(rx_fcoe_no_ddp),
218 HW_XSTAT(rx_fcoe_no_ddp_ext_buff),
221 HW_XSTAT(tx_macsec_pkts_untagged),
222 HW_XSTAT(tx_macsec_pkts_encrypted),
223 HW_XSTAT(tx_macsec_pkts_protected),
224 HW_XSTAT(tx_macsec_octets_encrypted),
225 HW_XSTAT(tx_macsec_octets_protected),
226 HW_XSTAT(rx_macsec_pkts_untagged),
227 HW_XSTAT(rx_macsec_pkts_badtag),
228 HW_XSTAT(rx_macsec_pkts_nosci),
229 HW_XSTAT(rx_macsec_pkts_unknownsci),
230 HW_XSTAT(rx_macsec_octets_decrypted),
231 HW_XSTAT(rx_macsec_octets_validated),
232 HW_XSTAT(rx_macsec_sc_pkts_unchecked),
233 HW_XSTAT(rx_macsec_sc_pkts_delayed),
234 HW_XSTAT(rx_macsec_sc_pkts_late),
235 HW_XSTAT(rx_macsec_sa_pkts_ok),
236 HW_XSTAT(rx_macsec_sa_pkts_invalid),
237 HW_XSTAT(rx_macsec_sa_pkts_notvalid),
238 HW_XSTAT(rx_macsec_sa_pkts_unusedsa),
239 HW_XSTAT(rx_macsec_sa_pkts_notusingsa),
242 HW_XSTAT(rx_size_64_packets),
243 HW_XSTAT(rx_size_65_to_127_packets),
244 HW_XSTAT(rx_size_128_to_255_packets),
245 HW_XSTAT(rx_size_256_to_511_packets),
246 HW_XSTAT(rx_size_512_to_1023_packets),
247 HW_XSTAT(rx_size_1024_to_max_packets),
248 HW_XSTAT(tx_size_64_packets),
249 HW_XSTAT(tx_size_65_to_127_packets),
250 HW_XSTAT(tx_size_128_to_255_packets),
251 HW_XSTAT(tx_size_256_to_511_packets),
252 HW_XSTAT(tx_size_512_to_1023_packets),
253 HW_XSTAT(tx_size_1024_to_max_packets),
256 HW_XSTAT(tx_xon_packets),
257 HW_XSTAT(rx_xon_packets),
258 HW_XSTAT(tx_xoff_packets),
259 HW_XSTAT(rx_xoff_packets),
261 HW_XSTAT_NAME(tx_xon_packets, "tx_flow_control_xon_packets"),
262 HW_XSTAT_NAME(rx_xon_packets, "rx_flow_control_xon_packets"),
263 HW_XSTAT_NAME(tx_xoff_packets, "tx_flow_control_xoff_packets"),
264 HW_XSTAT_NAME(rx_xoff_packets, "rx_flow_control_xoff_packets"),
267 #define TXGBE_NB_HW_STATS (sizeof(rte_txgbe_stats_strings) / \
268 sizeof(rte_txgbe_stats_strings[0]))
270 /* Per-priority statistics */
271 #define UP_XSTAT(m) {#m, offsetof(struct txgbe_hw_stats, up[0].m)}
272 static const struct rte_txgbe_xstats_name_off rte_txgbe_up_strings[] = {
273 UP_XSTAT(rx_up_packets),
274 UP_XSTAT(tx_up_packets),
275 UP_XSTAT(rx_up_bytes),
276 UP_XSTAT(tx_up_bytes),
277 UP_XSTAT(rx_up_drop_packets),
279 UP_XSTAT(tx_up_xon_packets),
280 UP_XSTAT(rx_up_xon_packets),
281 UP_XSTAT(tx_up_xoff_packets),
282 UP_XSTAT(rx_up_xoff_packets),
283 UP_XSTAT(rx_up_dropped),
284 UP_XSTAT(rx_up_mbuf_alloc_errors),
285 UP_XSTAT(tx_up_xon2off_packets),
288 #define TXGBE_NB_UP_STATS (sizeof(rte_txgbe_up_strings) / \
289 sizeof(rte_txgbe_up_strings[0]))
291 /* Per-queue statistics */
292 #define QP_XSTAT(m) {#m, offsetof(struct txgbe_hw_stats, qp[0].m)}
293 static const struct rte_txgbe_xstats_name_off rte_txgbe_qp_strings[] = {
294 QP_XSTAT(rx_qp_packets),
295 QP_XSTAT(tx_qp_packets),
296 QP_XSTAT(rx_qp_bytes),
297 QP_XSTAT(tx_qp_bytes),
298 QP_XSTAT(rx_qp_mc_packets),
301 #define TXGBE_NB_QP_STATS (sizeof(rte_txgbe_qp_strings) / \
302 sizeof(rte_txgbe_qp_strings[0]))
305 txgbe_is_sfp(struct txgbe_hw *hw)
307 switch (hw->phy.type) {
308 case txgbe_phy_sfp_avago:
309 case txgbe_phy_sfp_ftl:
310 case txgbe_phy_sfp_intel:
311 case txgbe_phy_sfp_unknown:
312 case txgbe_phy_sfp_tyco_passive:
313 case txgbe_phy_sfp_unknown_passive:
320 static inline int32_t
321 txgbe_pf_reset_hw(struct txgbe_hw *hw)
326 status = hw->mac.reset_hw(hw);
328 ctrl_ext = rd32(hw, TXGBE_PORTCTL);
329 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
330 ctrl_ext |= TXGBE_PORTCTL_RSTDONE;
331 wr32(hw, TXGBE_PORTCTL, ctrl_ext);
334 if (status == TXGBE_ERR_SFP_NOT_PRESENT)
340 txgbe_enable_intr(struct rte_eth_dev *dev)
342 struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);
343 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
345 wr32(hw, TXGBE_IENMISC, intr->mask_misc);
346 wr32(hw, TXGBE_IMC(0), TXGBE_IMC_MASK);
347 wr32(hw, TXGBE_IMC(1), TXGBE_IMC_MASK);
352 txgbe_disable_intr(struct txgbe_hw *hw)
354 PMD_INIT_FUNC_TRACE();
356 wr32(hw, TXGBE_IENMISC, ~BIT_MASK32);
357 wr32(hw, TXGBE_IMS(0), TXGBE_IMC_MASK);
358 wr32(hw, TXGBE_IMS(1), TXGBE_IMC_MASK);
363 txgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
368 struct txgbe_hw *hw = TXGBE_DEV_HW(eth_dev);
369 struct txgbe_stat_mappings *stat_mappings =
370 TXGBE_DEV_STAT_MAPPINGS(eth_dev);
371 uint32_t qsmr_mask = 0;
372 uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
376 if (hw->mac.type != txgbe_mac_raptor)
379 if (stat_idx & ~QMAP_FIELD_RESERVED_BITS_MASK)
382 PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d",
383 (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
386 n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
387 if (n >= TXGBE_NB_STAT_MAPPING) {
388 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
391 offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
393 /* Now clear any previous stat_idx set */
394 clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
396 stat_mappings->tqsm[n] &= ~clearing_mask;
398 stat_mappings->rqsm[n] &= ~clearing_mask;
400 q_map = (uint32_t)stat_idx;
401 q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
402 qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
404 stat_mappings->tqsm[n] |= qsmr_mask;
406 stat_mappings->rqsm[n] |= qsmr_mask;
408 PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d",
409 (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
411 PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
412 is_rx ? stat_mappings->rqsm[n] : stat_mappings->tqsm[n]);
417 txgbe_dcb_init(struct txgbe_hw *hw, struct txgbe_dcb_config *dcb_config)
421 struct txgbe_dcb_tc_config *tc;
423 UNREFERENCED_PARAMETER(hw);
425 dcb_config->num_tcs.pg_tcs = TXGBE_DCB_TC_MAX;
426 dcb_config->num_tcs.pfc_tcs = TXGBE_DCB_TC_MAX;
427 bwgp = (u8)(100 / TXGBE_DCB_TC_MAX);
428 for (i = 0; i < TXGBE_DCB_TC_MAX; i++) {
429 tc = &dcb_config->tc_config[i];
430 tc->path[TXGBE_DCB_TX_CONFIG].bwg_id = i;
431 tc->path[TXGBE_DCB_TX_CONFIG].bwg_percent = bwgp + (i & 1);
432 tc->path[TXGBE_DCB_RX_CONFIG].bwg_id = i;
433 tc->path[TXGBE_DCB_RX_CONFIG].bwg_percent = bwgp + (i & 1);
434 tc->pfc = txgbe_dcb_pfc_disabled;
437 /* Initialize default user to priority mapping, UPx->TC0 */
438 tc = &dcb_config->tc_config[0];
439 tc->path[TXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
440 tc->path[TXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
441 for (i = 0; i < TXGBE_DCB_BWG_MAX; i++) {
442 dcb_config->bw_percentage[i][TXGBE_DCB_TX_CONFIG] = 100;
443 dcb_config->bw_percentage[i][TXGBE_DCB_RX_CONFIG] = 100;
445 dcb_config->rx_pba_cfg = txgbe_dcb_pba_equal;
446 dcb_config->pfc_mode_enable = false;
447 dcb_config->vt_mode = true;
448 dcb_config->round_robin_enable = false;
449 /* support all DCB capabilities */
450 dcb_config->support.capabilities = 0xFF;
454 * Ensure that all locks are released before first NVM or PHY access
457 txgbe_swfw_lock_reset(struct txgbe_hw *hw)
462 * These ones are more tricky since they are common to all ports; but
463 * swfw_sync retries last long enough (1s) to be almost sure that if
464 * lock can not be taken it is due to an improper lock of the
467 mask = TXGBE_MNGSEM_SWPHY |
469 TXGBE_MNGSEM_SWFLASH;
470 if (hw->mac.acquire_swfw_sync(hw, mask) < 0)
471 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
473 hw->mac.release_swfw_sync(hw, mask);
477 txgbe_handle_devarg(__rte_unused const char *key, const char *value,
480 uint16_t *n = extra_args;
482 if (value == NULL || extra_args == NULL)
485 *n = (uint16_t)strtoul(value, NULL, 10);
486 if (*n == USHRT_MAX && errno == ERANGE)
493 txgbe_parse_devargs(struct txgbe_hw *hw, struct rte_devargs *devargs)
495 struct rte_kvargs *kvlist;
508 kvlist = rte_kvargs_parse(devargs->args, txgbe_valid_arguments);
512 rte_kvargs_process(kvlist, TXGBE_DEVARG_BP_AUTO,
513 &txgbe_handle_devarg, &auto_neg);
514 rte_kvargs_process(kvlist, TXGBE_DEVARG_KR_POLL,
515 &txgbe_handle_devarg, &poll);
516 rte_kvargs_process(kvlist, TXGBE_DEVARG_KR_PRESENT,
517 &txgbe_handle_devarg, &present);
518 rte_kvargs_process(kvlist, TXGBE_DEVARG_KX_SGMII,
519 &txgbe_handle_devarg, &sgmii);
520 rte_kvargs_process(kvlist, TXGBE_DEVARG_FFE_SET,
521 &txgbe_handle_devarg, &ffe_set);
522 rte_kvargs_process(kvlist, TXGBE_DEVARG_FFE_MAIN,
523 &txgbe_handle_devarg, &ffe_main);
524 rte_kvargs_process(kvlist, TXGBE_DEVARG_FFE_PRE,
525 &txgbe_handle_devarg, &ffe_pre);
526 rte_kvargs_process(kvlist, TXGBE_DEVARG_FFE_POST,
527 &txgbe_handle_devarg, &ffe_post);
528 rte_kvargs_free(kvlist);
531 hw->devarg.auto_neg = auto_neg;
532 hw->devarg.poll = poll;
533 hw->devarg.present = present;
534 hw->devarg.sgmii = sgmii;
535 hw->phy.ffe_set = ffe_set;
536 hw->phy.ffe_main = ffe_main;
537 hw->phy.ffe_pre = ffe_pre;
538 hw->phy.ffe_post = ffe_post;
542 eth_txgbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params __rte_unused)
544 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
545 struct txgbe_hw *hw = TXGBE_DEV_HW(eth_dev);
546 struct txgbe_vfta *shadow_vfta = TXGBE_DEV_VFTA(eth_dev);
547 struct txgbe_hwstrip *hwstrip = TXGBE_DEV_HWSTRIP(eth_dev);
548 struct txgbe_dcb_config *dcb_config = TXGBE_DEV_DCB_CONFIG(eth_dev);
549 struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(eth_dev);
550 struct txgbe_bw_conf *bw_conf = TXGBE_DEV_BW_CONF(eth_dev);
551 struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
552 const struct rte_memzone *mz;
557 PMD_INIT_FUNC_TRACE();
559 eth_dev->dev_ops = &txgbe_eth_dev_ops;
560 eth_dev->rx_queue_count = txgbe_dev_rx_queue_count;
561 eth_dev->rx_descriptor_status = txgbe_dev_rx_descriptor_status;
562 eth_dev->tx_descriptor_status = txgbe_dev_tx_descriptor_status;
563 eth_dev->rx_pkt_burst = &txgbe_recv_pkts;
564 eth_dev->tx_pkt_burst = &txgbe_xmit_pkts;
565 eth_dev->tx_pkt_prepare = &txgbe_prep_pkts;
568 * For secondary processes, we don't initialise any further as primary
569 * has already done this work. Only check we don't need a different
570 * RX and TX function.
572 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
573 struct txgbe_tx_queue *txq;
574 /* TX queue function in primary, set by last queue initialized
575 * Tx queue may not initialized by primary process
577 if (eth_dev->data->tx_queues) {
578 uint16_t nb_tx_queues = eth_dev->data->nb_tx_queues;
579 txq = eth_dev->data->tx_queues[nb_tx_queues - 1];
580 txgbe_set_tx_function(eth_dev, txq);
582 /* Use default TX function if we get here */
583 PMD_INIT_LOG(NOTICE, "No TX queues configured yet. "
584 "Using default TX function.");
587 txgbe_set_rx_function(eth_dev);
592 rte_eth_copy_pci_info(eth_dev, pci_dev);
594 /* Vendor and Device ID need to be set before init of shared code */
595 hw->device_id = pci_dev->id.device_id;
596 hw->vendor_id = pci_dev->id.vendor_id;
597 if (pci_dev->id.subsystem_vendor_id == PCI_VENDOR_ID_WANGXUN) {
598 hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
602 ssid = txgbe_flash_read_dword(hw, 0xFFFDC);
605 "Read of internal subsystem device id failed\n");
608 hw->subsystem_device_id = (u16)ssid >> 8 | (u16)ssid << 8;
610 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
611 hw->allow_unsupported_sfp = 1;
613 /* Reserve memory for interrupt status block */
614 mz = rte_eth_dma_zone_reserve(eth_dev, "txgbe_driver", -1,
615 16, TXGBE_ALIGN, SOCKET_ID_ANY);
619 hw->isb_dma = TMZ_PADDR(mz);
620 hw->isb_mem = TMZ_VADDR(mz);
622 txgbe_parse_devargs(hw, pci_dev->device.devargs);
623 /* Initialize the shared code (base driver) */
624 err = txgbe_init_shared_code(hw);
626 PMD_INIT_LOG(ERR, "Shared code init failed: %d", err);
630 /* Unlock any pending hardware semaphore */
631 txgbe_swfw_lock_reset(hw);
633 #ifdef RTE_LIB_SECURITY
634 /* Initialize security_ctx only for primary process*/
635 if (txgbe_ipsec_ctx_create(eth_dev))
639 /* Initialize DCB configuration*/
640 memset(dcb_config, 0, sizeof(struct txgbe_dcb_config));
641 txgbe_dcb_init(hw, dcb_config);
643 /* Get Hardware Flow Control setting */
644 hw->fc.requested_mode = txgbe_fc_full;
645 hw->fc.current_mode = txgbe_fc_full;
646 hw->fc.pause_time = TXGBE_FC_PAUSE_TIME;
647 for (i = 0; i < TXGBE_DCB_TC_MAX; i++) {
648 hw->fc.low_water[i] = TXGBE_FC_XON_LOTH;
649 hw->fc.high_water[i] = TXGBE_FC_XOFF_HITH;
653 err = hw->rom.init_params(hw);
655 PMD_INIT_LOG(ERR, "The EEPROM init failed: %d", err);
659 /* Make sure we have a good EEPROM before we read from it */
660 err = hw->rom.validate_checksum(hw, &csum);
662 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", err);
666 err = hw->mac.init_hw(hw);
669 * Devices with copper phys will fail to initialise if txgbe_init_hw()
670 * is called too soon after the kernel driver unbinding/binding occurs.
671 * The failure occurs in txgbe_identify_phy() for all devices,
672 * but for non-copper devies, txgbe_identify_sfp_module() is
673 * also called. See txgbe_identify_phy(). The reason for the
674 * failure is not known, and only occuts when virtualisation features
675 * are disabled in the bios. A delay of 200ms was found to be enough by
676 * trial-and-error, and is doubled to be safe.
678 if (err && hw->phy.media_type == txgbe_media_type_copper) {
680 err = hw->mac.init_hw(hw);
683 if (err == TXGBE_ERR_SFP_NOT_PRESENT)
686 if (err == TXGBE_ERR_EEPROM_VERSION) {
687 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
688 "LOM. Please be aware there may be issues associated "
689 "with your hardware.");
690 PMD_INIT_LOG(ERR, "If you are experiencing problems "
691 "please contact your hardware representative "
692 "who provided you with this hardware.");
693 } else if (err == TXGBE_ERR_SFP_NOT_SUPPORTED) {
694 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
697 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", err);
701 /* Reset the hw statistics */
702 txgbe_dev_stats_reset(eth_dev);
704 /* disable interrupt */
705 txgbe_disable_intr(hw);
707 /* Allocate memory for storing MAC addresses */
708 eth_dev->data->mac_addrs = rte_zmalloc("txgbe", RTE_ETHER_ADDR_LEN *
709 hw->mac.num_rar_entries, 0);
710 if (eth_dev->data->mac_addrs == NULL) {
712 "Failed to allocate %u bytes needed to store "
714 RTE_ETHER_ADDR_LEN * hw->mac.num_rar_entries);
718 /* Copy the permanent MAC address */
719 rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.perm_addr,
720 ð_dev->data->mac_addrs[0]);
722 /* Allocate memory for storing hash filter MAC addresses */
723 eth_dev->data->hash_mac_addrs = rte_zmalloc("txgbe",
724 RTE_ETHER_ADDR_LEN * TXGBE_VMDQ_NUM_UC_MAC, 0);
725 if (eth_dev->data->hash_mac_addrs == NULL) {
727 "Failed to allocate %d bytes needed to store MAC addresses",
728 RTE_ETHER_ADDR_LEN * TXGBE_VMDQ_NUM_UC_MAC);
732 /* initialize the vfta */
733 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
735 /* initialize the hw strip bitmap*/
736 memset(hwstrip, 0, sizeof(*hwstrip));
738 /* initialize PF if max_vfs not zero */
739 ret = txgbe_pf_host_init(eth_dev);
741 rte_free(eth_dev->data->mac_addrs);
742 eth_dev->data->mac_addrs = NULL;
743 rte_free(eth_dev->data->hash_mac_addrs);
744 eth_dev->data->hash_mac_addrs = NULL;
748 ctrl_ext = rd32(hw, TXGBE_PORTCTL);
749 /* let hardware know driver is loaded */
750 ctrl_ext |= TXGBE_PORTCTL_DRVLOAD;
751 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
752 ctrl_ext |= TXGBE_PORTCTL_RSTDONE;
753 wr32(hw, TXGBE_PORTCTL, ctrl_ext);
756 if (txgbe_is_sfp(hw) && hw->phy.sfp_type != txgbe_sfp_type_not_present)
757 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
758 (int)hw->mac.type, (int)hw->phy.type,
759 (int)hw->phy.sfp_type);
761 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
762 (int)hw->mac.type, (int)hw->phy.type);
764 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
765 eth_dev->data->port_id, pci_dev->id.vendor_id,
766 pci_dev->id.device_id);
768 rte_intr_callback_register(intr_handle,
769 txgbe_dev_interrupt_handler, eth_dev);
771 /* enable uio/vfio intr/eventfd mapping */
772 rte_intr_enable(intr_handle);
774 /* enable support intr */
775 txgbe_enable_intr(eth_dev);
777 /* initialize filter info */
778 memset(filter_info, 0,
779 sizeof(struct txgbe_filter_info));
781 /* initialize 5tuple filter list */
782 TAILQ_INIT(&filter_info->fivetuple_list);
784 /* initialize flow director filter list & hash */
785 txgbe_fdir_filter_init(eth_dev);
787 /* initialize l2 tunnel filter list & hash */
788 txgbe_l2_tn_filter_init(eth_dev);
790 /* initialize flow filter lists */
791 txgbe_filterlist_init();
793 /* initialize bandwidth configuration info */
794 memset(bw_conf, 0, sizeof(struct txgbe_bw_conf));
796 /* initialize Traffic Manager configuration */
797 txgbe_tm_conf_init(eth_dev);
803 eth_txgbe_dev_uninit(struct rte_eth_dev *eth_dev)
805 PMD_INIT_FUNC_TRACE();
807 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
810 txgbe_dev_close(eth_dev);
815 static int txgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev)
817 struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(eth_dev);
818 struct txgbe_5tuple_filter *p_5tuple;
820 while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) {
821 TAILQ_REMOVE(&filter_info->fivetuple_list,
826 memset(filter_info->fivetuple_mask, 0,
827 sizeof(uint32_t) * TXGBE_5TUPLE_ARRAY_SIZE);
832 static int txgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev)
834 struct txgbe_hw_fdir_info *fdir_info = TXGBE_DEV_FDIR(eth_dev);
835 struct txgbe_fdir_filter *fdir_filter;
837 rte_free(fdir_info->hash_map);
838 rte_hash_free(fdir_info->hash_handle);
840 while ((fdir_filter = TAILQ_FIRST(&fdir_info->fdir_list))) {
841 TAILQ_REMOVE(&fdir_info->fdir_list,
844 rte_free(fdir_filter);
850 static int txgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev)
852 struct txgbe_l2_tn_info *l2_tn_info = TXGBE_DEV_L2_TN(eth_dev);
853 struct txgbe_l2_tn_filter *l2_tn_filter;
855 rte_free(l2_tn_info->hash_map);
856 rte_hash_free(l2_tn_info->hash_handle);
858 while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
859 TAILQ_REMOVE(&l2_tn_info->l2_tn_list,
862 rte_free(l2_tn_filter);
868 static int txgbe_fdir_filter_init(struct rte_eth_dev *eth_dev)
870 struct txgbe_hw_fdir_info *fdir_info = TXGBE_DEV_FDIR(eth_dev);
871 char fdir_hash_name[RTE_HASH_NAMESIZE];
872 struct rte_hash_parameters fdir_hash_params = {
873 .name = fdir_hash_name,
874 .entries = TXGBE_MAX_FDIR_FILTER_NUM,
875 .key_len = sizeof(struct txgbe_atr_input),
876 .hash_func = rte_hash_crc,
877 .hash_func_init_val = 0,
878 .socket_id = rte_socket_id(),
881 TAILQ_INIT(&fdir_info->fdir_list);
882 snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
883 "fdir_%s", TDEV_NAME(eth_dev));
884 fdir_info->hash_handle = rte_hash_create(&fdir_hash_params);
885 if (!fdir_info->hash_handle) {
886 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
889 fdir_info->hash_map = rte_zmalloc("txgbe",
890 sizeof(struct txgbe_fdir_filter *) *
891 TXGBE_MAX_FDIR_FILTER_NUM,
893 if (!fdir_info->hash_map) {
895 "Failed to allocate memory for fdir hash map!");
898 fdir_info->mask_added = FALSE;
903 static int txgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev)
905 struct txgbe_l2_tn_info *l2_tn_info = TXGBE_DEV_L2_TN(eth_dev);
906 char l2_tn_hash_name[RTE_HASH_NAMESIZE];
907 struct rte_hash_parameters l2_tn_hash_params = {
908 .name = l2_tn_hash_name,
909 .entries = TXGBE_MAX_L2_TN_FILTER_NUM,
910 .key_len = sizeof(struct txgbe_l2_tn_key),
911 .hash_func = rte_hash_crc,
912 .hash_func_init_val = 0,
913 .socket_id = rte_socket_id(),
916 TAILQ_INIT(&l2_tn_info->l2_tn_list);
917 snprintf(l2_tn_hash_name, RTE_HASH_NAMESIZE,
918 "l2_tn_%s", TDEV_NAME(eth_dev));
919 l2_tn_info->hash_handle = rte_hash_create(&l2_tn_hash_params);
920 if (!l2_tn_info->hash_handle) {
921 PMD_INIT_LOG(ERR, "Failed to create L2 TN hash table!");
924 l2_tn_info->hash_map = rte_zmalloc("txgbe",
925 sizeof(struct txgbe_l2_tn_filter *) *
926 TXGBE_MAX_L2_TN_FILTER_NUM,
928 if (!l2_tn_info->hash_map) {
930 "Failed to allocate memory for L2 TN hash map!");
933 l2_tn_info->e_tag_en = FALSE;
934 l2_tn_info->e_tag_fwd_en = FALSE;
935 l2_tn_info->e_tag_ether_type = RTE_ETHER_TYPE_ETAG;
941 eth_txgbe_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
942 struct rte_pci_device *pci_dev)
944 return rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
945 sizeof(struct txgbe_adapter),
946 eth_dev_pci_specific_init, pci_dev,
947 eth_txgbe_dev_init, NULL);
950 static int eth_txgbe_pci_remove(struct rte_pci_device *pci_dev)
952 struct rte_eth_dev *ethdev;
954 ethdev = rte_eth_dev_allocated(pci_dev->device.name);
958 return rte_eth_dev_destroy(ethdev, eth_txgbe_dev_uninit);
961 static struct rte_pci_driver rte_txgbe_pmd = {
962 .id_table = pci_id_txgbe_map,
963 .drv_flags = RTE_PCI_DRV_NEED_MAPPING |
964 RTE_PCI_DRV_INTR_LSC,
965 .probe = eth_txgbe_pci_probe,
966 .remove = eth_txgbe_pci_remove,
970 txgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
972 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
973 struct txgbe_vfta *shadow_vfta = TXGBE_DEV_VFTA(dev);
978 vid_idx = (uint32_t)((vlan_id >> 5) & 0x7F);
979 vid_bit = (uint32_t)(1 << (vlan_id & 0x1F));
980 vfta = rd32(hw, TXGBE_VLANTBL(vid_idx));
985 wr32(hw, TXGBE_VLANTBL(vid_idx), vfta);
987 /* update local VFTA copy */
988 shadow_vfta->vfta[vid_idx] = vfta;
994 txgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
996 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
997 struct txgbe_rx_queue *rxq;
999 uint32_t rxcfg, rxbal, rxbah;
1002 txgbe_vlan_hw_strip_enable(dev, queue);
1004 txgbe_vlan_hw_strip_disable(dev, queue);
1006 rxq = dev->data->rx_queues[queue];
1007 rxbal = rd32(hw, TXGBE_RXBAL(rxq->reg_idx));
1008 rxbah = rd32(hw, TXGBE_RXBAH(rxq->reg_idx));
1009 rxcfg = rd32(hw, TXGBE_RXCFG(rxq->reg_idx));
1010 if (rxq->offloads & RTE_ETH_RX_OFFLOAD_VLAN_STRIP) {
1011 restart = (rxcfg & TXGBE_RXCFG_ENA) &&
1012 !(rxcfg & TXGBE_RXCFG_VLAN);
1013 rxcfg |= TXGBE_RXCFG_VLAN;
1015 restart = (rxcfg & TXGBE_RXCFG_ENA) &&
1016 (rxcfg & TXGBE_RXCFG_VLAN);
1017 rxcfg &= ~TXGBE_RXCFG_VLAN;
1019 rxcfg &= ~TXGBE_RXCFG_ENA;
1022 /* set vlan strip for ring */
1023 txgbe_dev_rx_queue_stop(dev, queue);
1024 wr32(hw, TXGBE_RXBAL(rxq->reg_idx), rxbal);
1025 wr32(hw, TXGBE_RXBAH(rxq->reg_idx), rxbah);
1026 wr32(hw, TXGBE_RXCFG(rxq->reg_idx), rxcfg);
1027 txgbe_dev_rx_queue_start(dev, queue);
1032 txgbe_vlan_tpid_set(struct rte_eth_dev *dev,
1033 enum rte_vlan_type vlan_type,
1036 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
1038 uint32_t portctrl, vlan_ext, qinq;
1040 portctrl = rd32(hw, TXGBE_PORTCTL);
1042 vlan_ext = (portctrl & TXGBE_PORTCTL_VLANEXT);
1043 qinq = vlan_ext && (portctrl & TXGBE_PORTCTL_QINQ);
1044 switch (vlan_type) {
1045 case RTE_ETH_VLAN_TYPE_INNER:
1047 wr32m(hw, TXGBE_VLANCTL,
1048 TXGBE_VLANCTL_TPID_MASK,
1049 TXGBE_VLANCTL_TPID(tpid));
1050 wr32m(hw, TXGBE_DMATXCTRL,
1051 TXGBE_DMATXCTRL_TPID_MASK,
1052 TXGBE_DMATXCTRL_TPID(tpid));
1055 PMD_DRV_LOG(ERR, "Inner type is not supported"
1060 wr32m(hw, TXGBE_TAGTPID(0),
1061 TXGBE_TAGTPID_LSB_MASK,
1062 TXGBE_TAGTPID_LSB(tpid));
1065 case RTE_ETH_VLAN_TYPE_OUTER:
1067 /* Only the high 16-bits is valid */
1068 wr32m(hw, TXGBE_EXTAG,
1069 TXGBE_EXTAG_VLAN_MASK,
1070 TXGBE_EXTAG_VLAN(tpid));
1072 wr32m(hw, TXGBE_VLANCTL,
1073 TXGBE_VLANCTL_TPID_MASK,
1074 TXGBE_VLANCTL_TPID(tpid));
1075 wr32m(hw, TXGBE_DMATXCTRL,
1076 TXGBE_DMATXCTRL_TPID_MASK,
1077 TXGBE_DMATXCTRL_TPID(tpid));
1081 wr32m(hw, TXGBE_TAGTPID(0),
1082 TXGBE_TAGTPID_MSB_MASK,
1083 TXGBE_TAGTPID_MSB(tpid));
1087 PMD_DRV_LOG(ERR, "Unsupported VLAN type %d", vlan_type);
1095 txgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1097 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
1100 PMD_INIT_FUNC_TRACE();
1102 /* Filter Table Disable */
1103 vlnctrl = rd32(hw, TXGBE_VLANCTL);
1104 vlnctrl &= ~TXGBE_VLANCTL_VFE;
1105 wr32(hw, TXGBE_VLANCTL, vlnctrl);
1109 txgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1111 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
1112 struct txgbe_vfta *shadow_vfta = TXGBE_DEV_VFTA(dev);
1116 PMD_INIT_FUNC_TRACE();
1118 /* Filter Table Enable */
1119 vlnctrl = rd32(hw, TXGBE_VLANCTL);
1120 vlnctrl &= ~TXGBE_VLANCTL_CFIENA;
1121 vlnctrl |= TXGBE_VLANCTL_VFE;
1122 wr32(hw, TXGBE_VLANCTL, vlnctrl);
1124 /* write whatever is in local vfta copy */
1125 for (i = 0; i < TXGBE_VFTA_SIZE; i++)
1126 wr32(hw, TXGBE_VLANTBL(i), shadow_vfta->vfta[i]);
1130 txgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1132 struct txgbe_hwstrip *hwstrip = TXGBE_DEV_HWSTRIP(dev);
1133 struct txgbe_rx_queue *rxq;
1135 if (queue >= TXGBE_MAX_RX_QUEUE_NUM)
1139 TXGBE_SET_HWSTRIP(hwstrip, queue);
1141 TXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1143 if (queue >= dev->data->nb_rx_queues)
1146 rxq = dev->data->rx_queues[queue];
1149 rxq->vlan_flags = RTE_MBUF_F_RX_VLAN | RTE_MBUF_F_RX_VLAN_STRIPPED;
1150 rxq->offloads |= RTE_ETH_RX_OFFLOAD_VLAN_STRIP;
1152 rxq->vlan_flags = RTE_MBUF_F_RX_VLAN;
1153 rxq->offloads &= ~RTE_ETH_RX_OFFLOAD_VLAN_STRIP;
1158 txgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
1160 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
1163 PMD_INIT_FUNC_TRACE();
1165 ctrl = rd32(hw, TXGBE_RXCFG(queue));
1166 ctrl &= ~TXGBE_RXCFG_VLAN;
1167 wr32(hw, TXGBE_RXCFG(queue), ctrl);
1169 /* record those setting for HW strip per queue */
1170 txgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
1174 txgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
1176 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
1179 PMD_INIT_FUNC_TRACE();
1181 ctrl = rd32(hw, TXGBE_RXCFG(queue));
1182 ctrl |= TXGBE_RXCFG_VLAN;
1183 wr32(hw, TXGBE_RXCFG(queue), ctrl);
1185 /* record those setting for HW strip per queue */
1186 txgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
1190 txgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
1192 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
1195 PMD_INIT_FUNC_TRACE();
1197 ctrl = rd32(hw, TXGBE_PORTCTL);
1198 ctrl &= ~TXGBE_PORTCTL_VLANEXT;
1199 wr32(hw, TXGBE_PORTCTL, ctrl);
1203 txgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
1205 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
1208 PMD_INIT_FUNC_TRACE();
1210 ctrl = rd32(hw, TXGBE_PORTCTL);
1211 ctrl |= TXGBE_PORTCTL_VLANEXT;
1212 wr32(hw, TXGBE_PORTCTL, ctrl);
1216 txgbe_qinq_hw_strip_disable(struct rte_eth_dev *dev)
1218 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
1221 PMD_INIT_FUNC_TRACE();
1223 ctrl = rd32(hw, TXGBE_PORTCTL);
1224 ctrl &= ~TXGBE_PORTCTL_QINQ;
1225 wr32(hw, TXGBE_PORTCTL, ctrl);
1229 txgbe_qinq_hw_strip_enable(struct rte_eth_dev *dev)
1231 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
1234 PMD_INIT_FUNC_TRACE();
1236 ctrl = rd32(hw, TXGBE_PORTCTL);
1237 ctrl |= TXGBE_PORTCTL_QINQ | TXGBE_PORTCTL_VLANEXT;
1238 wr32(hw, TXGBE_PORTCTL, ctrl);
1242 txgbe_vlan_hw_strip_config(struct rte_eth_dev *dev)
1244 struct txgbe_rx_queue *rxq;
1247 PMD_INIT_FUNC_TRACE();
1249 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1250 rxq = dev->data->rx_queues[i];
1252 if (rxq->offloads & RTE_ETH_RX_OFFLOAD_VLAN_STRIP)
1253 txgbe_vlan_strip_queue_set(dev, i, 1);
1255 txgbe_vlan_strip_queue_set(dev, i, 0);
1260 txgbe_config_vlan_strip_on_all_queues(struct rte_eth_dev *dev, int mask)
1263 struct rte_eth_rxmode *rxmode;
1264 struct txgbe_rx_queue *rxq;
1266 if (mask & RTE_ETH_VLAN_STRIP_MASK) {
1267 rxmode = &dev->data->dev_conf.rxmode;
1268 if (rxmode->offloads & RTE_ETH_RX_OFFLOAD_VLAN_STRIP)
1269 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1270 rxq = dev->data->rx_queues[i];
1271 rxq->offloads |= RTE_ETH_RX_OFFLOAD_VLAN_STRIP;
1274 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1275 rxq = dev->data->rx_queues[i];
1276 rxq->offloads &= ~RTE_ETH_RX_OFFLOAD_VLAN_STRIP;
1282 txgbe_vlan_offload_config(struct rte_eth_dev *dev, int mask)
1284 struct rte_eth_rxmode *rxmode;
1285 rxmode = &dev->data->dev_conf.rxmode;
1287 if (mask & RTE_ETH_VLAN_STRIP_MASK)
1288 txgbe_vlan_hw_strip_config(dev);
1290 if (mask & RTE_ETH_VLAN_FILTER_MASK) {
1291 if (rxmode->offloads & RTE_ETH_RX_OFFLOAD_VLAN_FILTER)
1292 txgbe_vlan_hw_filter_enable(dev);
1294 txgbe_vlan_hw_filter_disable(dev);
1297 if (mask & RTE_ETH_VLAN_EXTEND_MASK) {
1298 if (rxmode->offloads & RTE_ETH_RX_OFFLOAD_VLAN_EXTEND)
1299 txgbe_vlan_hw_extend_enable(dev);
1301 txgbe_vlan_hw_extend_disable(dev);
1304 if (mask & RTE_ETH_QINQ_STRIP_MASK) {
1305 if (rxmode->offloads & RTE_ETH_RX_OFFLOAD_QINQ_STRIP)
1306 txgbe_qinq_hw_strip_enable(dev);
1308 txgbe_qinq_hw_strip_disable(dev);
1315 txgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1317 txgbe_config_vlan_strip_on_all_queues(dev, mask);
1319 txgbe_vlan_offload_config(dev, mask);
1325 txgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1327 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
1328 /* VLNCTL: enable vlan filtering and allow all vlan tags through */
1329 uint32_t vlanctrl = rd32(hw, TXGBE_VLANCTL);
1331 vlanctrl |= TXGBE_VLANCTL_VFE; /* enable vlan filters */
1332 wr32(hw, TXGBE_VLANCTL, vlanctrl);
1336 txgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q)
1338 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1343 RTE_ETH_DEV_SRIOV(dev).active = RTE_ETH_64_POOLS;
1346 RTE_ETH_DEV_SRIOV(dev).active = RTE_ETH_32_POOLS;
1352 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool =
1353 TXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
1354 RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx =
1355 pci_dev->max_vfs * RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
1360 txgbe_check_mq_mode(struct rte_eth_dev *dev)
1362 struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
1363 uint16_t nb_rx_q = dev->data->nb_rx_queues;
1364 uint16_t nb_tx_q = dev->data->nb_tx_queues;
1366 if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
1367 /* check multi-queue mode */
1368 switch (dev_conf->rxmode.mq_mode) {
1369 case RTE_ETH_MQ_RX_VMDQ_DCB:
1370 PMD_INIT_LOG(INFO, "RTE_ETH_MQ_RX_VMDQ_DCB mode supported in SRIOV");
1372 case RTE_ETH_MQ_RX_VMDQ_DCB_RSS:
1373 /* DCB/RSS VMDQ in SRIOV mode, not implement yet */
1374 PMD_INIT_LOG(ERR, "SRIOV active,"
1375 " unsupported mq_mode rx %d.",
1376 dev_conf->rxmode.mq_mode);
1378 case RTE_ETH_MQ_RX_RSS:
1379 case RTE_ETH_MQ_RX_VMDQ_RSS:
1380 dev->data->dev_conf.rxmode.mq_mode = RTE_ETH_MQ_RX_VMDQ_RSS;
1381 if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)
1382 if (txgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) {
1383 PMD_INIT_LOG(ERR, "SRIOV is active,"
1384 " invalid queue number"
1385 " for VMDQ RSS, allowed"
1386 " value are 1, 2 or 4.");
1390 case RTE_ETH_MQ_RX_VMDQ_ONLY:
1391 case RTE_ETH_MQ_RX_NONE:
1392 /* if nothing mq mode configure, use default scheme */
1393 dev->data->dev_conf.rxmode.mq_mode =
1394 RTE_ETH_MQ_RX_VMDQ_ONLY;
1396 default: /* RTE_ETH_MQ_RX_DCB, RTE_ETH_MQ_RX_DCB_RSS or RTE_ETH_MQ_TX_DCB*/
1397 /* SRIOV only works in VMDq enable mode */
1398 PMD_INIT_LOG(ERR, "SRIOV is active,"
1399 " wrong mq_mode rx %d.",
1400 dev_conf->rxmode.mq_mode);
1404 switch (dev_conf->txmode.mq_mode) {
1405 case RTE_ETH_MQ_TX_VMDQ_DCB:
1406 PMD_INIT_LOG(INFO, "RTE_ETH_MQ_TX_VMDQ_DCB mode supported in SRIOV");
1407 dev->data->dev_conf.txmode.mq_mode = RTE_ETH_MQ_TX_VMDQ_DCB;
1409 default: /* RTE_ETH_MQ_TX_VMDQ_ONLY or RTE_ETH_MQ_TX_NONE */
1410 dev->data->dev_conf.txmode.mq_mode =
1411 RTE_ETH_MQ_TX_VMDQ_ONLY;
1415 /* check valid queue number */
1416 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) ||
1417 (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) {
1418 PMD_INIT_LOG(ERR, "SRIOV is active,"
1419 " nb_rx_q=%d nb_tx_q=%d queue number"
1420 " must be less than or equal to %d.",
1422 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool);
1426 if (dev_conf->rxmode.mq_mode == RTE_ETH_MQ_RX_VMDQ_DCB_RSS) {
1427 PMD_INIT_LOG(ERR, "VMDQ+DCB+RSS mq_mode is"
1431 /* check configuration for vmdb+dcb mode */
1432 if (dev_conf->rxmode.mq_mode == RTE_ETH_MQ_RX_VMDQ_DCB) {
1433 const struct rte_eth_vmdq_dcb_conf *conf;
1435 if (nb_rx_q != TXGBE_VMDQ_DCB_NB_QUEUES) {
1436 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.",
1437 TXGBE_VMDQ_DCB_NB_QUEUES);
1440 conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf;
1441 if (!(conf->nb_queue_pools == RTE_ETH_16_POOLS ||
1442 conf->nb_queue_pools == RTE_ETH_32_POOLS)) {
1443 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
1444 " nb_queue_pools must be %d or %d.",
1445 RTE_ETH_16_POOLS, RTE_ETH_32_POOLS);
1449 if (dev_conf->txmode.mq_mode == RTE_ETH_MQ_TX_VMDQ_DCB) {
1450 const struct rte_eth_vmdq_dcb_tx_conf *conf;
1452 if (nb_tx_q != TXGBE_VMDQ_DCB_NB_QUEUES) {
1453 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d",
1454 TXGBE_VMDQ_DCB_NB_QUEUES);
1457 conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf;
1458 if (!(conf->nb_queue_pools == RTE_ETH_16_POOLS ||
1459 conf->nb_queue_pools == RTE_ETH_32_POOLS)) {
1460 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
1461 " nb_queue_pools != %d and"
1462 " nb_queue_pools != %d.",
1463 RTE_ETH_16_POOLS, RTE_ETH_32_POOLS);
1468 /* For DCB mode check our configuration before we go further */
1469 if (dev_conf->rxmode.mq_mode == RTE_ETH_MQ_RX_DCB) {
1470 const struct rte_eth_dcb_rx_conf *conf;
1472 conf = &dev_conf->rx_adv_conf.dcb_rx_conf;
1473 if (!(conf->nb_tcs == RTE_ETH_4_TCS ||
1474 conf->nb_tcs == RTE_ETH_8_TCS)) {
1475 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
1476 " and nb_tcs != %d.",
1477 RTE_ETH_4_TCS, RTE_ETH_8_TCS);
1482 if (dev_conf->txmode.mq_mode == RTE_ETH_MQ_TX_DCB) {
1483 const struct rte_eth_dcb_tx_conf *conf;
1485 conf = &dev_conf->tx_adv_conf.dcb_tx_conf;
1486 if (!(conf->nb_tcs == RTE_ETH_4_TCS ||
1487 conf->nb_tcs == RTE_ETH_8_TCS)) {
1488 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
1489 " and nb_tcs != %d.",
1490 RTE_ETH_4_TCS, RTE_ETH_8_TCS);
1499 txgbe_dev_configure(struct rte_eth_dev *dev)
1501 struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);
1502 struct txgbe_adapter *adapter = TXGBE_DEV_ADAPTER(dev);
1505 PMD_INIT_FUNC_TRACE();
1507 if (dev->data->dev_conf.rxmode.mq_mode & RTE_ETH_MQ_RX_RSS_FLAG)
1508 dev->data->dev_conf.rxmode.offloads |= RTE_ETH_RX_OFFLOAD_RSS_HASH;
1510 /* multiple queue mode checking */
1511 ret = txgbe_check_mq_mode(dev);
1513 PMD_DRV_LOG(ERR, "txgbe_check_mq_mode fails with %d.",
1518 /* set flag to update link status after init */
1519 intr->flags |= TXGBE_FLAG_NEED_LINK_UPDATE;
1522 * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
1523 * allocation Rx preconditions we will reset it.
1525 adapter->rx_bulk_alloc_allowed = true;
1531 txgbe_dev_phy_intr_setup(struct rte_eth_dev *dev)
1533 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
1534 struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);
1537 gpie = rd32(hw, TXGBE_GPIOINTEN);
1538 gpie |= TXGBE_GPIOBIT_6;
1539 wr32(hw, TXGBE_GPIOINTEN, gpie);
1540 intr->mask_misc |= TXGBE_ICRMISC_GPIO;
1541 intr->mask_misc |= TXGBE_ICRMISC_ANDONE;
1545 txgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
1546 uint16_t tx_rate, uint64_t q_msk)
1548 struct txgbe_hw *hw;
1549 struct txgbe_vf_info *vfinfo;
1550 struct rte_eth_link link;
1551 uint8_t nb_q_per_pool;
1552 uint32_t queue_stride;
1553 uint32_t queue_idx, idx = 0, vf_idx;
1555 uint16_t total_rate = 0;
1556 struct rte_pci_device *pci_dev;
1559 pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1560 ret = rte_eth_link_get_nowait(dev->data->port_id, &link);
1564 if (vf >= pci_dev->max_vfs)
1567 if (tx_rate > link.link_speed)
1573 hw = TXGBE_DEV_HW(dev);
1574 vfinfo = *(TXGBE_DEV_VFDATA(dev));
1575 nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
1576 queue_stride = TXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
1577 queue_idx = vf * queue_stride;
1578 queue_end = queue_idx + nb_q_per_pool - 1;
1579 if (queue_end >= hw->mac.max_tx_queues)
1583 for (vf_idx = 0; vf_idx < pci_dev->max_vfs; vf_idx++) {
1586 for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
1588 total_rate += vfinfo[vf_idx].tx_rate[idx];
1594 /* Store tx_rate for this vf. */
1595 for (idx = 0; idx < nb_q_per_pool; idx++) {
1596 if (((uint64_t)0x1 << idx) & q_msk) {
1597 if (vfinfo[vf].tx_rate[idx] != tx_rate)
1598 vfinfo[vf].tx_rate[idx] = tx_rate;
1599 total_rate += tx_rate;
1603 if (total_rate > dev->data->dev_link.link_speed) {
1604 /* Reset stored TX rate of the VF if it causes exceed
1607 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
1611 /* Set ARBTXRATE of each queue/pool for vf X */
1612 for (; queue_idx <= queue_end; queue_idx++) {
1614 txgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
1622 * Configure device link speed and setup link.
1623 * It returns 0 on success.
1626 txgbe_dev_start(struct rte_eth_dev *dev)
1628 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
1629 struct txgbe_hw_stats *hw_stats = TXGBE_DEV_STATS(dev);
1630 struct txgbe_vf_info *vfinfo = *TXGBE_DEV_VFDATA(dev);
1631 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1632 struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
1633 uint32_t intr_vector = 0;
1635 bool link_up = false, negotiate = 0;
1637 uint32_t allowed_speeds = 0;
1641 uint32_t *link_speeds;
1642 struct txgbe_tm_conf *tm_conf = TXGBE_DEV_TM_CONF(dev);
1644 PMD_INIT_FUNC_TRACE();
1646 /* Stop the link setup handler before resetting the HW. */
1647 rte_eal_alarm_cancel(txgbe_dev_setup_link_alarm_handler, dev);
1649 /* disable uio/vfio intr/eventfd mapping */
1650 rte_intr_disable(intr_handle);
1653 hw->adapter_stopped = 0;
1656 /* reinitialize adapter
1657 * this calls reset and start
1659 hw->nb_rx_queues = dev->data->nb_rx_queues;
1660 hw->nb_tx_queues = dev->data->nb_tx_queues;
1661 status = txgbe_pf_reset_hw(hw);
1664 hw->mac.start_hw(hw);
1665 hw->mac.get_link_status = true;
1666 hw->dev_start = true;
1668 /* configure PF module if SRIOV enabled */
1669 txgbe_pf_host_configure(dev);
1671 txgbe_dev_phy_intr_setup(dev);
1673 /* check and configure queue intr-vector mapping */
1674 if ((rte_intr_cap_multiple(intr_handle) ||
1675 !RTE_ETH_DEV_SRIOV(dev).active) &&
1676 dev->data->dev_conf.intr_conf.rxq != 0) {
1677 intr_vector = dev->data->nb_rx_queues;
1678 if (rte_intr_efd_enable(intr_handle, intr_vector))
1682 if (rte_intr_dp_is_en(intr_handle)) {
1683 if (rte_intr_vec_list_alloc(intr_handle, "intr_vec",
1684 dev->data->nb_rx_queues)) {
1685 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
1686 " intr_vec", dev->data->nb_rx_queues);
1690 /* configure msix for sleep until rx interrupt */
1691 txgbe_configure_msix(dev);
1693 /* initialize transmission unit */
1694 txgbe_dev_tx_init(dev);
1696 /* This can fail when allocating mbufs for descriptor rings */
1697 err = txgbe_dev_rx_init(dev);
1699 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
1703 mask = RTE_ETH_VLAN_STRIP_MASK | RTE_ETH_VLAN_FILTER_MASK |
1704 RTE_ETH_VLAN_EXTEND_MASK;
1705 err = txgbe_vlan_offload_config(dev, mask);
1707 PMD_INIT_LOG(ERR, "Unable to set VLAN offload");
1711 if (dev->data->dev_conf.rxmode.mq_mode == RTE_ETH_MQ_RX_VMDQ_ONLY) {
1712 /* Enable vlan filtering for VMDq */
1713 txgbe_vmdq_vlan_hw_filter_enable(dev);
1716 /* Configure DCB hw */
1717 txgbe_configure_pb(dev);
1718 txgbe_configure_port(dev);
1719 txgbe_configure_dcb(dev);
1721 if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
1722 err = txgbe_fdir_configure(dev);
1727 /* Restore vf rate limit */
1728 if (vfinfo != NULL) {
1729 for (vf = 0; vf < pci_dev->max_vfs; vf++)
1730 for (idx = 0; idx < TXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
1731 if (vfinfo[vf].tx_rate[idx] != 0)
1732 txgbe_set_vf_rate_limit(dev, vf,
1733 vfinfo[vf].tx_rate[idx],
1737 err = txgbe_dev_rxtx_start(dev);
1739 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
1743 /* Skip link setup if loopback mode is enabled. */
1744 if (hw->mac.type == txgbe_mac_raptor &&
1745 dev->data->dev_conf.lpbk_mode)
1746 goto skip_link_setup;
1748 if (txgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
1749 err = hw->mac.setup_sfp(hw);
1754 if (hw->phy.media_type == txgbe_media_type_copper) {
1755 /* Turn on the copper */
1756 hw->phy.set_phy_power(hw, true);
1758 /* Turn on the laser */
1759 hw->mac.enable_tx_laser(hw);
1762 if ((hw->subsystem_device_id & 0xFF) != TXGBE_DEV_ID_KR_KX_KX4)
1763 err = hw->mac.check_link(hw, &speed, &link_up, 0);
1766 dev->data->dev_link.link_status = link_up;
1768 err = hw->mac.get_link_capabilities(hw, &speed, &negotiate);
1772 allowed_speeds = RTE_ETH_LINK_SPEED_100M | RTE_ETH_LINK_SPEED_1G |
1773 RTE_ETH_LINK_SPEED_10G;
1775 link_speeds = &dev->data->dev_conf.link_speeds;
1776 if (((*link_speeds) >> 1) & ~(allowed_speeds >> 1)) {
1777 PMD_INIT_LOG(ERR, "Invalid link setting");
1782 if (*link_speeds == RTE_ETH_LINK_SPEED_AUTONEG) {
1783 speed = (TXGBE_LINK_SPEED_100M_FULL |
1784 TXGBE_LINK_SPEED_1GB_FULL |
1785 TXGBE_LINK_SPEED_10GB_FULL);
1787 if (*link_speeds & RTE_ETH_LINK_SPEED_10G)
1788 speed |= TXGBE_LINK_SPEED_10GB_FULL;
1789 if (*link_speeds & RTE_ETH_LINK_SPEED_5G)
1790 speed |= TXGBE_LINK_SPEED_5GB_FULL;
1791 if (*link_speeds & RTE_ETH_LINK_SPEED_2_5G)
1792 speed |= TXGBE_LINK_SPEED_2_5GB_FULL;
1793 if (*link_speeds & RTE_ETH_LINK_SPEED_1G)
1794 speed |= TXGBE_LINK_SPEED_1GB_FULL;
1795 if (*link_speeds & RTE_ETH_LINK_SPEED_100M)
1796 speed |= TXGBE_LINK_SPEED_100M_FULL;
1799 err = hw->mac.setup_link(hw, speed, link_up);
1805 if (rte_intr_allow_others(intr_handle)) {
1806 txgbe_dev_misc_interrupt_setup(dev);
1807 /* check if lsc interrupt is enabled */
1808 if (dev->data->dev_conf.intr_conf.lsc != 0)
1809 txgbe_dev_lsc_interrupt_setup(dev, TRUE);
1811 txgbe_dev_lsc_interrupt_setup(dev, FALSE);
1812 txgbe_dev_macsec_interrupt_setup(dev);
1813 txgbe_set_ivar_map(hw, -1, 1, TXGBE_MISC_VEC_ID);
1815 rte_intr_callback_unregister(intr_handle,
1816 txgbe_dev_interrupt_handler, dev);
1817 if (dev->data->dev_conf.intr_conf.lsc != 0)
1818 PMD_INIT_LOG(INFO, "lsc won't enable because of"
1819 " no intr multiplex");
1822 /* check if rxq interrupt is enabled */
1823 if (dev->data->dev_conf.intr_conf.rxq != 0 &&
1824 rte_intr_dp_is_en(intr_handle))
1825 txgbe_dev_rxq_interrupt_setup(dev);
1827 /* enable uio/vfio intr/eventfd mapping */
1828 rte_intr_enable(intr_handle);
1830 /* resume enabled intr since hw reset */
1831 txgbe_enable_intr(dev);
1832 txgbe_l2_tunnel_conf(dev);
1833 txgbe_filter_restore(dev);
1835 if (tm_conf->root && !tm_conf->committed)
1836 PMD_DRV_LOG(WARNING,
1837 "please call hierarchy_commit() "
1838 "before starting the port");
1841 * Update link status right before return, because it may
1842 * start link configuration process in a separate thread.
1844 txgbe_dev_link_update(dev, 0);
1846 wr32m(hw, TXGBE_LEDCTL, 0xFFFFFFFF, TXGBE_LEDCTL_ORD_MASK);
1848 txgbe_read_stats_registers(hw, hw_stats);
1849 hw->offset_loaded = 1;
1854 PMD_INIT_LOG(ERR, "failure in dev start: %d", err);
1855 txgbe_dev_clear_queues(dev);
1860 * Stop device: disable rx and tx functions to allow for reconfiguring.
1863 txgbe_dev_stop(struct rte_eth_dev *dev)
1865 struct rte_eth_link link;
1866 struct txgbe_adapter *adapter = TXGBE_DEV_ADAPTER(dev);
1867 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
1868 struct txgbe_vf_info *vfinfo = *TXGBE_DEV_VFDATA(dev);
1869 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1870 struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
1872 struct txgbe_tm_conf *tm_conf = TXGBE_DEV_TM_CONF(dev);
1874 if (hw->adapter_stopped)
1877 PMD_INIT_FUNC_TRACE();
1879 rte_eal_alarm_cancel(txgbe_dev_setup_link_alarm_handler, dev);
1881 /* disable interrupts */
1882 txgbe_disable_intr(hw);
1885 txgbe_pf_reset_hw(hw);
1886 hw->adapter_stopped = 0;
1891 for (vf = 0; vfinfo != NULL && vf < pci_dev->max_vfs; vf++)
1892 vfinfo[vf].clear_to_send = false;
1894 if (hw->phy.media_type == txgbe_media_type_copper) {
1895 /* Turn off the copper */
1896 hw->phy.set_phy_power(hw, false);
1898 /* Turn off the laser */
1899 hw->mac.disable_tx_laser(hw);
1902 txgbe_dev_clear_queues(dev);
1904 /* Clear stored conf */
1905 dev->data->scattered_rx = 0;
1908 /* Clear recorded link status */
1909 memset(&link, 0, sizeof(link));
1910 rte_eth_linkstatus_set(dev, &link);
1912 if (!rte_intr_allow_others(intr_handle))
1913 /* resume to the default handler */
1914 rte_intr_callback_register(intr_handle,
1915 txgbe_dev_interrupt_handler,
1918 /* Clean datapath event and queue/vec mapping */
1919 rte_intr_efd_disable(intr_handle);
1920 rte_intr_vec_list_free(intr_handle);
1922 /* reset hierarchy commit */
1923 tm_conf->committed = false;
1925 adapter->rss_reta_updated = 0;
1926 wr32m(hw, TXGBE_LEDCTL, 0xFFFFFFFF, TXGBE_LEDCTL_SEL_MASK);
1928 hw->adapter_stopped = true;
1929 dev->data->dev_started = 0;
1930 hw->dev_start = false;
1936 * Set device link up: enable tx.
1939 txgbe_dev_set_link_up(struct rte_eth_dev *dev)
1941 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
1943 if (hw->phy.media_type == txgbe_media_type_copper) {
1944 /* Turn on the copper */
1945 hw->phy.set_phy_power(hw, true);
1947 /* Turn on the laser */
1948 hw->mac.enable_tx_laser(hw);
1949 hw->dev_start = true;
1950 txgbe_dev_link_update(dev, 0);
1957 * Set device link down: disable tx.
1960 txgbe_dev_set_link_down(struct rte_eth_dev *dev)
1962 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
1964 if (hw->phy.media_type == txgbe_media_type_copper) {
1965 /* Turn off the copper */
1966 hw->phy.set_phy_power(hw, false);
1968 /* Turn off the laser */
1969 hw->mac.disable_tx_laser(hw);
1970 hw->dev_start = false;
1971 txgbe_dev_link_update(dev, 0);
1978 * Reset and stop device.
1981 txgbe_dev_close(struct rte_eth_dev *dev)
1983 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
1984 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1985 struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
1989 PMD_INIT_FUNC_TRACE();
1991 txgbe_pf_reset_hw(hw);
1993 ret = txgbe_dev_stop(dev);
1995 txgbe_dev_free_queues(dev);
1997 /* reprogram the RAR[0] in case user changed it. */
1998 txgbe_set_rar(hw, 0, hw->mac.addr, 0, true);
2000 /* Unlock any pending hardware semaphore */
2001 txgbe_swfw_lock_reset(hw);
2003 /* disable uio intr before callback unregister */
2004 rte_intr_disable(intr_handle);
2007 ret = rte_intr_callback_unregister(intr_handle,
2008 txgbe_dev_interrupt_handler, dev);
2009 if (ret >= 0 || ret == -ENOENT) {
2011 } else if (ret != -EAGAIN) {
2013 "intr callback unregister failed: %d",
2017 } while (retries++ < (10 + TXGBE_LINK_UP_TIME));
2019 /* cancel the delay handler before remove dev */
2020 rte_eal_alarm_cancel(txgbe_dev_interrupt_delayed_handler, dev);
2022 /* uninitialize PF if max_vfs not zero */
2023 txgbe_pf_host_uninit(dev);
2025 rte_free(dev->data->mac_addrs);
2026 dev->data->mac_addrs = NULL;
2028 rte_free(dev->data->hash_mac_addrs);
2029 dev->data->hash_mac_addrs = NULL;
2031 /* remove all the fdir filters & hash */
2032 txgbe_fdir_filter_uninit(dev);
2034 /* remove all the L2 tunnel filters & hash */
2035 txgbe_l2_tn_filter_uninit(dev);
2037 /* Remove all ntuple filters of the device */
2038 txgbe_ntuple_filter_uninit(dev);
2040 /* clear all the filters list */
2041 txgbe_filterlist_flush();
2043 /* Remove all Traffic Manager configuration */
2044 txgbe_tm_conf_uninit(dev);
2046 #ifdef RTE_LIB_SECURITY
2047 rte_free(dev->security_ctx);
2048 dev->security_ctx = NULL;
2058 txgbe_dev_reset(struct rte_eth_dev *dev)
2062 /* When a DPDK PMD PF begin to reset PF port, it should notify all
2063 * its VF to make them align with it. The detailed notification
2064 * mechanism is PMD specific. As to txgbe PF, it is rather complex.
2065 * To avoid unexpected behavior in VF, currently reset of PF with
2066 * SR-IOV activation is not supported. It might be supported later.
2068 if (dev->data->sriov.active)
2071 ret = eth_txgbe_dev_uninit(dev);
2075 ret = eth_txgbe_dev_init(dev, NULL);
2080 #define UPDATE_QP_COUNTER_32bit(reg, last_counter, counter) \
2082 uint32_t current_counter = rd32(hw, reg); \
2083 if (current_counter < last_counter) \
2084 current_counter += 0x100000000LL; \
2085 if (!hw->offset_loaded) \
2086 last_counter = current_counter; \
2087 counter = current_counter - last_counter; \
2088 counter &= 0xFFFFFFFFLL; \
2091 #define UPDATE_QP_COUNTER_36bit(reg_lsb, reg_msb, last_counter, counter) \
2093 uint64_t current_counter_lsb = rd32(hw, reg_lsb); \
2094 uint64_t current_counter_msb = rd32(hw, reg_msb); \
2095 uint64_t current_counter = (current_counter_msb << 32) | \
2096 current_counter_lsb; \
2097 if (current_counter < last_counter) \
2098 current_counter += 0x1000000000LL; \
2099 if (!hw->offset_loaded) \
2100 last_counter = current_counter; \
2101 counter = current_counter - last_counter; \
2102 counter &= 0xFFFFFFFFFLL; \
2106 txgbe_read_stats_registers(struct txgbe_hw *hw,
2107 struct txgbe_hw_stats *hw_stats)
2112 for (i = 0; i < hw->nb_rx_queues; i++) {
2113 UPDATE_QP_COUNTER_32bit(TXGBE_QPRXPKT(i),
2114 hw->qp_last[i].rx_qp_packets,
2115 hw_stats->qp[i].rx_qp_packets);
2116 UPDATE_QP_COUNTER_36bit(TXGBE_QPRXOCTL(i), TXGBE_QPRXOCTH(i),
2117 hw->qp_last[i].rx_qp_bytes,
2118 hw_stats->qp[i].rx_qp_bytes);
2119 UPDATE_QP_COUNTER_32bit(TXGBE_QPRXMPKT(i),
2120 hw->qp_last[i].rx_qp_mc_packets,
2121 hw_stats->qp[i].rx_qp_mc_packets);
2124 for (i = 0; i < hw->nb_tx_queues; i++) {
2125 UPDATE_QP_COUNTER_32bit(TXGBE_QPTXPKT(i),
2126 hw->qp_last[i].tx_qp_packets,
2127 hw_stats->qp[i].tx_qp_packets);
2128 UPDATE_QP_COUNTER_36bit(TXGBE_QPTXOCTL(i), TXGBE_QPTXOCTH(i),
2129 hw->qp_last[i].tx_qp_bytes,
2130 hw_stats->qp[i].tx_qp_bytes);
2133 for (i = 0; i < TXGBE_MAX_UP; i++) {
2134 hw_stats->up[i].rx_up_xon_packets +=
2135 rd32(hw, TXGBE_PBRXUPXON(i));
2136 hw_stats->up[i].rx_up_xoff_packets +=
2137 rd32(hw, TXGBE_PBRXUPXOFF(i));
2138 hw_stats->up[i].tx_up_xon_packets +=
2139 rd32(hw, TXGBE_PBTXUPXON(i));
2140 hw_stats->up[i].tx_up_xoff_packets +=
2141 rd32(hw, TXGBE_PBTXUPXOFF(i));
2142 hw_stats->up[i].tx_up_xon2off_packets +=
2143 rd32(hw, TXGBE_PBTXUPOFF(i));
2144 hw_stats->up[i].rx_up_dropped +=
2145 rd32(hw, TXGBE_PBRXMISS(i));
2147 hw_stats->rx_xon_packets += rd32(hw, TXGBE_PBRXLNKXON);
2148 hw_stats->rx_xoff_packets += rd32(hw, TXGBE_PBRXLNKXOFF);
2149 hw_stats->tx_xon_packets += rd32(hw, TXGBE_PBTXLNKXON);
2150 hw_stats->tx_xoff_packets += rd32(hw, TXGBE_PBTXLNKXOFF);
2153 hw_stats->rx_packets += rd32(hw, TXGBE_DMARXPKT);
2154 hw_stats->tx_packets += rd32(hw, TXGBE_DMATXPKT);
2156 hw_stats->rx_bytes += rd64(hw, TXGBE_DMARXOCTL);
2157 hw_stats->tx_bytes += rd64(hw, TXGBE_DMATXOCTL);
2158 hw_stats->rx_dma_drop += rd32(hw, TXGBE_DMARXDROP);
2159 hw_stats->rx_drop_packets += rd32(hw, TXGBE_PBRXDROP);
2162 hw_stats->rx_crc_errors += rd64(hw, TXGBE_MACRXERRCRCL);
2163 hw_stats->rx_multicast_packets += rd64(hw, TXGBE_MACRXMPKTL);
2164 hw_stats->tx_multicast_packets += rd64(hw, TXGBE_MACTXMPKTL);
2166 hw_stats->rx_total_packets += rd64(hw, TXGBE_MACRXPKTL);
2167 hw_stats->tx_total_packets += rd64(hw, TXGBE_MACTXPKTL);
2168 hw_stats->rx_total_bytes += rd64(hw, TXGBE_MACRXGBOCTL);
2170 hw_stats->rx_broadcast_packets += rd64(hw, TXGBE_MACRXOCTL);
2171 hw_stats->tx_broadcast_packets += rd32(hw, TXGBE_MACTXOCTL);
2173 hw_stats->rx_size_64_packets += rd64(hw, TXGBE_MACRX1TO64L);
2174 hw_stats->rx_size_65_to_127_packets += rd64(hw, TXGBE_MACRX65TO127L);
2175 hw_stats->rx_size_128_to_255_packets += rd64(hw, TXGBE_MACRX128TO255L);
2176 hw_stats->rx_size_256_to_511_packets += rd64(hw, TXGBE_MACRX256TO511L);
2177 hw_stats->rx_size_512_to_1023_packets +=
2178 rd64(hw, TXGBE_MACRX512TO1023L);
2179 hw_stats->rx_size_1024_to_max_packets +=
2180 rd64(hw, TXGBE_MACRX1024TOMAXL);
2181 hw_stats->tx_size_64_packets += rd64(hw, TXGBE_MACTX1TO64L);
2182 hw_stats->tx_size_65_to_127_packets += rd64(hw, TXGBE_MACTX65TO127L);
2183 hw_stats->tx_size_128_to_255_packets += rd64(hw, TXGBE_MACTX128TO255L);
2184 hw_stats->tx_size_256_to_511_packets += rd64(hw, TXGBE_MACTX256TO511L);
2185 hw_stats->tx_size_512_to_1023_packets +=
2186 rd64(hw, TXGBE_MACTX512TO1023L);
2187 hw_stats->tx_size_1024_to_max_packets +=
2188 rd64(hw, TXGBE_MACTX1024TOMAXL);
2190 hw_stats->rx_undersize_errors += rd64(hw, TXGBE_MACRXERRLENL);
2191 hw_stats->rx_oversize_errors += rd32(hw, TXGBE_MACRXOVERSIZE);
2192 hw_stats->rx_jabber_errors += rd32(hw, TXGBE_MACRXJABBER);
2195 hw_stats->mng_bmc2host_packets = rd32(hw, TXGBE_MNGBMC2OS);
2196 hw_stats->mng_host2bmc_packets = rd32(hw, TXGBE_MNGOS2BMC);
2197 hw_stats->rx_management_packets = rd32(hw, TXGBE_DMARXMNG);
2198 hw_stats->tx_management_packets = rd32(hw, TXGBE_DMATXMNG);
2201 hw_stats->rx_fcoe_crc_errors += rd32(hw, TXGBE_FCOECRC);
2202 hw_stats->rx_fcoe_mbuf_allocation_errors += rd32(hw, TXGBE_FCOELAST);
2203 hw_stats->rx_fcoe_dropped += rd32(hw, TXGBE_FCOERPDC);
2204 hw_stats->rx_fcoe_packets += rd32(hw, TXGBE_FCOEPRC);
2205 hw_stats->tx_fcoe_packets += rd32(hw, TXGBE_FCOEPTC);
2206 hw_stats->rx_fcoe_bytes += rd32(hw, TXGBE_FCOEDWRC);
2207 hw_stats->tx_fcoe_bytes += rd32(hw, TXGBE_FCOEDWTC);
2209 /* Flow Director Stats */
2210 hw_stats->flow_director_matched_filters += rd32(hw, TXGBE_FDIRMATCH);
2211 hw_stats->flow_director_missed_filters += rd32(hw, TXGBE_FDIRMISS);
2212 hw_stats->flow_director_added_filters +=
2213 TXGBE_FDIRUSED_ADD(rd32(hw, TXGBE_FDIRUSED));
2214 hw_stats->flow_director_removed_filters +=
2215 TXGBE_FDIRUSED_REM(rd32(hw, TXGBE_FDIRUSED));
2216 hw_stats->flow_director_filter_add_errors +=
2217 TXGBE_FDIRFAIL_ADD(rd32(hw, TXGBE_FDIRFAIL));
2218 hw_stats->flow_director_filter_remove_errors +=
2219 TXGBE_FDIRFAIL_REM(rd32(hw, TXGBE_FDIRFAIL));
2222 hw_stats->tx_macsec_pkts_untagged += rd32(hw, TXGBE_LSECTX_UTPKT);
2223 hw_stats->tx_macsec_pkts_encrypted +=
2224 rd32(hw, TXGBE_LSECTX_ENCPKT);
2225 hw_stats->tx_macsec_pkts_protected +=
2226 rd32(hw, TXGBE_LSECTX_PROTPKT);
2227 hw_stats->tx_macsec_octets_encrypted +=
2228 rd32(hw, TXGBE_LSECTX_ENCOCT);
2229 hw_stats->tx_macsec_octets_protected +=
2230 rd32(hw, TXGBE_LSECTX_PROTOCT);
2231 hw_stats->rx_macsec_pkts_untagged += rd32(hw, TXGBE_LSECRX_UTPKT);
2232 hw_stats->rx_macsec_pkts_badtag += rd32(hw, TXGBE_LSECRX_BTPKT);
2233 hw_stats->rx_macsec_pkts_nosci += rd32(hw, TXGBE_LSECRX_NOSCIPKT);
2234 hw_stats->rx_macsec_pkts_unknownsci += rd32(hw, TXGBE_LSECRX_UNSCIPKT);
2235 hw_stats->rx_macsec_octets_decrypted += rd32(hw, TXGBE_LSECRX_DECOCT);
2236 hw_stats->rx_macsec_octets_validated += rd32(hw, TXGBE_LSECRX_VLDOCT);
2237 hw_stats->rx_macsec_sc_pkts_unchecked +=
2238 rd32(hw, TXGBE_LSECRX_UNCHKPKT);
2239 hw_stats->rx_macsec_sc_pkts_delayed += rd32(hw, TXGBE_LSECRX_DLYPKT);
2240 hw_stats->rx_macsec_sc_pkts_late += rd32(hw, TXGBE_LSECRX_LATEPKT);
2241 for (i = 0; i < 2; i++) {
2242 hw_stats->rx_macsec_sa_pkts_ok +=
2243 rd32(hw, TXGBE_LSECRX_OKPKT(i));
2244 hw_stats->rx_macsec_sa_pkts_invalid +=
2245 rd32(hw, TXGBE_LSECRX_INVPKT(i));
2246 hw_stats->rx_macsec_sa_pkts_notvalid +=
2247 rd32(hw, TXGBE_LSECRX_BADPKT(i));
2249 hw_stats->rx_macsec_sa_pkts_unusedsa +=
2250 rd32(hw, TXGBE_LSECRX_INVSAPKT);
2251 hw_stats->rx_macsec_sa_pkts_notusingsa +=
2252 rd32(hw, TXGBE_LSECRX_BADSAPKT);
2254 hw_stats->rx_total_missed_packets = 0;
2255 for (i = 0; i < TXGBE_MAX_UP; i++) {
2256 hw_stats->rx_total_missed_packets +=
2257 hw_stats->up[i].rx_up_dropped;
2262 txgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2264 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2265 struct txgbe_hw_stats *hw_stats = TXGBE_DEV_STATS(dev);
2266 struct txgbe_stat_mappings *stat_mappings =
2267 TXGBE_DEV_STAT_MAPPINGS(dev);
2270 txgbe_read_stats_registers(hw, hw_stats);
2275 /* Fill out the rte_eth_stats statistics structure */
2276 stats->ipackets = hw_stats->rx_packets;
2277 stats->ibytes = hw_stats->rx_bytes;
2278 stats->opackets = hw_stats->tx_packets;
2279 stats->obytes = hw_stats->tx_bytes;
2281 memset(&stats->q_ipackets, 0, sizeof(stats->q_ipackets));
2282 memset(&stats->q_opackets, 0, sizeof(stats->q_opackets));
2283 memset(&stats->q_ibytes, 0, sizeof(stats->q_ibytes));
2284 memset(&stats->q_obytes, 0, sizeof(stats->q_obytes));
2285 memset(&stats->q_errors, 0, sizeof(stats->q_errors));
2286 for (i = 0; i < TXGBE_MAX_QP; i++) {
2287 uint32_t n = i / NB_QMAP_FIELDS_PER_QSM_REG;
2288 uint32_t offset = (i % NB_QMAP_FIELDS_PER_QSM_REG) * 8;
2291 q_map = (stat_mappings->rqsm[n] >> offset)
2292 & QMAP_FIELD_RESERVED_BITS_MASK;
2293 j = (q_map < RTE_ETHDEV_QUEUE_STAT_CNTRS
2294 ? q_map : q_map % RTE_ETHDEV_QUEUE_STAT_CNTRS);
2295 stats->q_ipackets[j] += hw_stats->qp[i].rx_qp_packets;
2296 stats->q_ibytes[j] += hw_stats->qp[i].rx_qp_bytes;
2298 q_map = (stat_mappings->tqsm[n] >> offset)
2299 & QMAP_FIELD_RESERVED_BITS_MASK;
2300 j = (q_map < RTE_ETHDEV_QUEUE_STAT_CNTRS
2301 ? q_map : q_map % RTE_ETHDEV_QUEUE_STAT_CNTRS);
2302 stats->q_opackets[j] += hw_stats->qp[i].tx_qp_packets;
2303 stats->q_obytes[j] += hw_stats->qp[i].tx_qp_bytes;
2307 stats->imissed = hw_stats->rx_total_missed_packets +
2308 hw_stats->rx_dma_drop;
2309 stats->ierrors = hw_stats->rx_crc_errors +
2310 hw_stats->rx_mac_short_packet_dropped +
2311 hw_stats->rx_length_errors +
2312 hw_stats->rx_undersize_errors +
2313 hw_stats->rx_oversize_errors +
2314 hw_stats->rx_drop_packets +
2315 hw_stats->rx_illegal_byte_errors +
2316 hw_stats->rx_error_bytes +
2317 hw_stats->rx_fragment_errors +
2318 hw_stats->rx_fcoe_crc_errors +
2319 hw_stats->rx_fcoe_mbuf_allocation_errors;
2327 txgbe_dev_stats_reset(struct rte_eth_dev *dev)
2329 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2330 struct txgbe_hw_stats *hw_stats = TXGBE_DEV_STATS(dev);
2332 /* HW registers are cleared on read */
2333 hw->offset_loaded = 0;
2334 txgbe_dev_stats_get(dev, NULL);
2335 hw->offset_loaded = 1;
2337 /* Reset software totals */
2338 memset(hw_stats, 0, sizeof(*hw_stats));
2343 /* This function calculates the number of xstats based on the current config */
2345 txgbe_xstats_calc_num(struct rte_eth_dev *dev)
2347 int nb_queues = max(dev->data->nb_rx_queues, dev->data->nb_tx_queues);
2348 return TXGBE_NB_HW_STATS +
2349 TXGBE_NB_UP_STATS * TXGBE_MAX_UP +
2350 TXGBE_NB_QP_STATS * nb_queues;
2354 txgbe_get_name_by_id(uint32_t id, char *name, uint32_t size)
2358 /* Extended stats from txgbe_hw_stats */
2359 if (id < TXGBE_NB_HW_STATS) {
2360 snprintf(name, size, "[hw]%s",
2361 rte_txgbe_stats_strings[id].name);
2364 id -= TXGBE_NB_HW_STATS;
2366 /* Priority Stats */
2367 if (id < TXGBE_NB_UP_STATS * TXGBE_MAX_UP) {
2368 nb = id / TXGBE_NB_UP_STATS;
2369 st = id % TXGBE_NB_UP_STATS;
2370 snprintf(name, size, "[p%u]%s", nb,
2371 rte_txgbe_up_strings[st].name);
2374 id -= TXGBE_NB_UP_STATS * TXGBE_MAX_UP;
2377 if (id < TXGBE_NB_QP_STATS * TXGBE_MAX_QP) {
2378 nb = id / TXGBE_NB_QP_STATS;
2379 st = id % TXGBE_NB_QP_STATS;
2380 snprintf(name, size, "[q%u]%s", nb,
2381 rte_txgbe_qp_strings[st].name);
2384 id -= TXGBE_NB_QP_STATS * TXGBE_MAX_QP;
2386 return -(int)(id + 1);
2390 txgbe_get_offset_by_id(uint32_t id, uint32_t *offset)
2394 /* Extended stats from txgbe_hw_stats */
2395 if (id < TXGBE_NB_HW_STATS) {
2396 *offset = rte_txgbe_stats_strings[id].offset;
2399 id -= TXGBE_NB_HW_STATS;
2401 /* Priority Stats */
2402 if (id < TXGBE_NB_UP_STATS * TXGBE_MAX_UP) {
2403 nb = id / TXGBE_NB_UP_STATS;
2404 st = id % TXGBE_NB_UP_STATS;
2405 *offset = rte_txgbe_up_strings[st].offset +
2406 nb * (TXGBE_NB_UP_STATS * sizeof(uint64_t));
2409 id -= TXGBE_NB_UP_STATS * TXGBE_MAX_UP;
2412 if (id < TXGBE_NB_QP_STATS * TXGBE_MAX_QP) {
2413 nb = id / TXGBE_NB_QP_STATS;
2414 st = id % TXGBE_NB_QP_STATS;
2415 *offset = rte_txgbe_qp_strings[st].offset +
2416 nb * (TXGBE_NB_QP_STATS * sizeof(uint64_t));
2423 static int txgbe_dev_xstats_get_names(struct rte_eth_dev *dev,
2424 struct rte_eth_xstat_name *xstats_names, unsigned int limit)
2426 unsigned int i, count;
2428 count = txgbe_xstats_calc_num(dev);
2429 if (xstats_names == NULL)
2432 /* Note: limit >= cnt_stats checked upstream
2433 * in rte_eth_xstats_names()
2435 limit = min(limit, count);
2437 /* Extended stats from txgbe_hw_stats */
2438 for (i = 0; i < limit; i++) {
2439 if (txgbe_get_name_by_id(i, xstats_names[i].name,
2440 sizeof(xstats_names[i].name))) {
2441 PMD_INIT_LOG(WARNING, "id value %d isn't valid", i);
2449 static int txgbe_dev_xstats_get_names_by_id(struct rte_eth_dev *dev,
2450 const uint64_t *ids,
2451 struct rte_eth_xstat_name *xstats_names,
2457 return txgbe_dev_xstats_get_names(dev, xstats_names, limit);
2459 for (i = 0; i < limit; i++) {
2460 if (txgbe_get_name_by_id(ids[i], xstats_names[i].name,
2461 sizeof(xstats_names[i].name))) {
2462 PMD_INIT_LOG(WARNING, "id value %d isn't valid", i);
2471 txgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2474 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2475 struct txgbe_hw_stats *hw_stats = TXGBE_DEV_STATS(dev);
2476 unsigned int i, count;
2478 txgbe_read_stats_registers(hw, hw_stats);
2480 /* If this is a reset xstats is NULL, and we have cleared the
2481 * registers by reading them.
2483 count = txgbe_xstats_calc_num(dev);
2487 limit = min(limit, txgbe_xstats_calc_num(dev));
2489 /* Extended stats from txgbe_hw_stats */
2490 for (i = 0; i < limit; i++) {
2491 uint32_t offset = 0;
2493 if (txgbe_get_offset_by_id(i, &offset)) {
2494 PMD_INIT_LOG(WARNING, "id value %d isn't valid", i);
2497 xstats[i].value = *(uint64_t *)(((char *)hw_stats) + offset);
2505 txgbe_dev_xstats_get_(struct rte_eth_dev *dev, uint64_t *values,
2508 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2509 struct txgbe_hw_stats *hw_stats = TXGBE_DEV_STATS(dev);
2510 unsigned int i, count;
2512 txgbe_read_stats_registers(hw, hw_stats);
2514 /* If this is a reset xstats is NULL, and we have cleared the
2515 * registers by reading them.
2517 count = txgbe_xstats_calc_num(dev);
2521 limit = min(limit, txgbe_xstats_calc_num(dev));
2523 /* Extended stats from txgbe_hw_stats */
2524 for (i = 0; i < limit; i++) {
2527 if (txgbe_get_offset_by_id(i, &offset)) {
2528 PMD_INIT_LOG(WARNING, "id value %d isn't valid", i);
2531 values[i] = *(uint64_t *)(((char *)hw_stats) + offset);
2538 txgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
2539 uint64_t *values, unsigned int limit)
2541 struct txgbe_hw_stats *hw_stats = TXGBE_DEV_STATS(dev);
2545 return txgbe_dev_xstats_get_(dev, values, limit);
2547 for (i = 0; i < limit; i++) {
2550 if (txgbe_get_offset_by_id(ids[i], &offset)) {
2551 PMD_INIT_LOG(WARNING, "id value %d isn't valid", i);
2554 values[i] = *(uint64_t *)(((char *)hw_stats) + offset);
2561 txgbe_dev_xstats_reset(struct rte_eth_dev *dev)
2563 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2564 struct txgbe_hw_stats *hw_stats = TXGBE_DEV_STATS(dev);
2566 /* HW registers are cleared on read */
2567 hw->offset_loaded = 0;
2568 txgbe_read_stats_registers(hw, hw_stats);
2569 hw->offset_loaded = 1;
2571 /* Reset software totals */
2572 memset(hw_stats, 0, sizeof(*hw_stats));
2578 txgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
2580 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2584 hw->phy.get_fw_version(hw, &etrack_id);
2586 ret = snprintf(fw_version, fw_size, "0x%08x", etrack_id);
2590 ret += 1; /* add the size of '\0' */
2591 if (fw_size < (size_t)ret)
2598 txgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2600 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2601 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2603 dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
2604 dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
2605 dev_info->min_rx_bufsize = 1024;
2606 dev_info->max_rx_pktlen = 15872;
2607 dev_info->max_mac_addrs = hw->mac.num_rar_entries;
2608 dev_info->max_hash_mac_addrs = TXGBE_VMDQ_NUM_UC_MAC;
2609 dev_info->max_vfs = pci_dev->max_vfs;
2610 dev_info->max_vmdq_pools = RTE_ETH_64_POOLS;
2611 dev_info->vmdq_queue_num = dev_info->max_rx_queues;
2612 dev_info->dev_capa &= ~RTE_ETH_DEV_CAPA_FLOW_RULE_KEEP;
2613 dev_info->rx_queue_offload_capa = txgbe_get_rx_queue_offloads(dev);
2614 dev_info->rx_offload_capa = (txgbe_get_rx_port_offloads(dev) |
2615 dev_info->rx_queue_offload_capa);
2616 dev_info->tx_queue_offload_capa = txgbe_get_tx_queue_offloads(dev);
2617 dev_info->tx_offload_capa = txgbe_get_tx_port_offloads(dev);
2619 dev_info->default_rxconf = (struct rte_eth_rxconf) {
2621 .pthresh = TXGBE_DEFAULT_RX_PTHRESH,
2622 .hthresh = TXGBE_DEFAULT_RX_HTHRESH,
2623 .wthresh = TXGBE_DEFAULT_RX_WTHRESH,
2625 .rx_free_thresh = TXGBE_DEFAULT_RX_FREE_THRESH,
2630 dev_info->default_txconf = (struct rte_eth_txconf) {
2632 .pthresh = TXGBE_DEFAULT_TX_PTHRESH,
2633 .hthresh = TXGBE_DEFAULT_TX_HTHRESH,
2634 .wthresh = TXGBE_DEFAULT_TX_WTHRESH,
2636 .tx_free_thresh = TXGBE_DEFAULT_TX_FREE_THRESH,
2640 dev_info->rx_desc_lim = rx_desc_lim;
2641 dev_info->tx_desc_lim = tx_desc_lim;
2643 dev_info->hash_key_size = TXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
2644 dev_info->reta_size = RTE_ETH_RSS_RETA_SIZE_128;
2645 dev_info->flow_type_rss_offloads = TXGBE_RSS_OFFLOAD_ALL;
2647 dev_info->speed_capa = RTE_ETH_LINK_SPEED_1G | RTE_ETH_LINK_SPEED_10G;
2648 dev_info->speed_capa |= RTE_ETH_LINK_SPEED_100M;
2650 /* Driver-preferred Rx/Tx parameters */
2651 dev_info->default_rxportconf.burst_size = 32;
2652 dev_info->default_txportconf.burst_size = 32;
2653 dev_info->default_rxportconf.nb_queues = 1;
2654 dev_info->default_txportconf.nb_queues = 1;
2655 dev_info->default_rxportconf.ring_size = 256;
2656 dev_info->default_txportconf.ring_size = 256;
2662 txgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev)
2664 if (dev->rx_pkt_burst == txgbe_recv_pkts ||
2665 dev->rx_pkt_burst == txgbe_recv_pkts_lro_single_alloc ||
2666 dev->rx_pkt_burst == txgbe_recv_pkts_lro_bulk_alloc ||
2667 dev->rx_pkt_burst == txgbe_recv_pkts_bulk_alloc)
2668 return txgbe_get_supported_ptypes();
2674 txgbe_dev_setup_link_alarm_handler(void *param)
2676 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2677 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2678 struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);
2680 bool autoneg = false;
2682 speed = hw->phy.autoneg_advertised;
2684 hw->mac.get_link_capabilities(hw, &speed, &autoneg);
2686 hw->mac.setup_link(hw, speed, true);
2688 intr->flags &= ~TXGBE_FLAG_NEED_LINK_CONFIG;
2691 /* return 0 means link status changed, -1 means not changed */
2693 txgbe_dev_link_update_share(struct rte_eth_dev *dev,
2694 int wait_to_complete)
2696 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2697 struct rte_eth_link link;
2698 u32 link_speed = TXGBE_LINK_SPEED_UNKNOWN;
2699 struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);
2704 memset(&link, 0, sizeof(link));
2705 link.link_status = RTE_ETH_LINK_DOWN;
2706 link.link_speed = RTE_ETH_SPEED_NUM_NONE;
2707 link.link_duplex = RTE_ETH_LINK_HALF_DUPLEX;
2708 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2709 RTE_ETH_LINK_SPEED_FIXED);
2711 hw->mac.get_link_status = true;
2713 if (intr->flags & TXGBE_FLAG_NEED_LINK_CONFIG)
2714 return rte_eth_linkstatus_set(dev, &link);
2716 /* check if it needs to wait to complete, if lsc interrupt is enabled */
2717 if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
2720 err = hw->mac.check_link(hw, &link_speed, &link_up, wait);
2723 link.link_speed = RTE_ETH_SPEED_NUM_100M;
2724 link.link_duplex = RTE_ETH_LINK_FULL_DUPLEX;
2725 return rte_eth_linkstatus_set(dev, &link);
2729 if ((hw->subsystem_device_id & 0xFF) ==
2730 TXGBE_DEV_ID_KR_KX_KX4) {
2731 hw->mac.bp_down_event(hw);
2732 } else if (hw->phy.media_type == txgbe_media_type_fiber) {
2733 intr->flags |= TXGBE_FLAG_NEED_LINK_CONFIG;
2734 rte_eal_alarm_set(10,
2735 txgbe_dev_setup_link_alarm_handler, dev);
2737 return rte_eth_linkstatus_set(dev, &link);
2738 } else if (!hw->dev_start) {
2739 return rte_eth_linkstatus_set(dev, &link);
2742 intr->flags &= ~TXGBE_FLAG_NEED_LINK_CONFIG;
2743 link.link_status = RTE_ETH_LINK_UP;
2744 link.link_duplex = RTE_ETH_LINK_FULL_DUPLEX;
2746 switch (link_speed) {
2748 case TXGBE_LINK_SPEED_UNKNOWN:
2749 link.link_duplex = RTE_ETH_LINK_FULL_DUPLEX;
2750 link.link_speed = RTE_ETH_SPEED_NUM_100M;
2753 case TXGBE_LINK_SPEED_100M_FULL:
2754 link.link_speed = RTE_ETH_SPEED_NUM_100M;
2757 case TXGBE_LINK_SPEED_1GB_FULL:
2758 link.link_speed = RTE_ETH_SPEED_NUM_1G;
2761 case TXGBE_LINK_SPEED_2_5GB_FULL:
2762 link.link_speed = RTE_ETH_SPEED_NUM_2_5G;
2765 case TXGBE_LINK_SPEED_5GB_FULL:
2766 link.link_speed = RTE_ETH_SPEED_NUM_5G;
2769 case TXGBE_LINK_SPEED_10GB_FULL:
2770 link.link_speed = RTE_ETH_SPEED_NUM_10G;
2774 return rte_eth_linkstatus_set(dev, &link);
2778 txgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
2780 return txgbe_dev_link_update_share(dev, wait_to_complete);
2784 txgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
2786 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2789 fctrl = rd32(hw, TXGBE_PSRCTL);
2790 fctrl |= (TXGBE_PSRCTL_UCP | TXGBE_PSRCTL_MCP);
2791 wr32(hw, TXGBE_PSRCTL, fctrl);
2797 txgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
2799 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2802 fctrl = rd32(hw, TXGBE_PSRCTL);
2803 fctrl &= (~TXGBE_PSRCTL_UCP);
2804 if (dev->data->all_multicast == 1)
2805 fctrl |= TXGBE_PSRCTL_MCP;
2807 fctrl &= (~TXGBE_PSRCTL_MCP);
2808 wr32(hw, TXGBE_PSRCTL, fctrl);
2814 txgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
2816 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2819 fctrl = rd32(hw, TXGBE_PSRCTL);
2820 fctrl |= TXGBE_PSRCTL_MCP;
2821 wr32(hw, TXGBE_PSRCTL, fctrl);
2827 txgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
2829 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2832 if (dev->data->promiscuous == 1)
2833 return 0; /* must remain in all_multicast mode */
2835 fctrl = rd32(hw, TXGBE_PSRCTL);
2836 fctrl &= (~TXGBE_PSRCTL_MCP);
2837 wr32(hw, TXGBE_PSRCTL, fctrl);
2843 * It clears the interrupt causes and enables the interrupt.
2844 * It will be called once only during nic initialized.
2847 * Pointer to struct rte_eth_dev.
2849 * Enable or Disable.
2852 * - On success, zero.
2853 * - On failure, a negative value.
2856 txgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on)
2858 struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);
2860 txgbe_dev_link_status_print(dev);
2862 intr->mask_misc |= TXGBE_ICRMISC_LSC;
2864 intr->mask_misc &= ~TXGBE_ICRMISC_LSC;
2870 txgbe_dev_misc_interrupt_setup(struct rte_eth_dev *dev)
2872 struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);
2875 mask = TXGBE_ICR_MASK;
2876 mask &= (1ULL << TXGBE_MISC_VEC_ID);
2878 intr->mask_misc |= TXGBE_ICRMISC_GPIO;
2879 intr->mask_misc |= TXGBE_ICRMISC_ANDONE;
2884 * It clears the interrupt causes and enables the interrupt.
2885 * It will be called once only during nic initialized.
2888 * Pointer to struct rte_eth_dev.
2891 * - On success, zero.
2892 * - On failure, a negative value.
2895 txgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
2897 struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);
2900 mask = TXGBE_ICR_MASK;
2901 mask &= ~((1ULL << TXGBE_RX_VEC_START) - 1);
2908 * It clears the interrupt causes and enables the interrupt.
2909 * It will be called once only during nic initialized.
2912 * Pointer to struct rte_eth_dev.
2915 * - On success, zero.
2916 * - On failure, a negative value.
2919 txgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev)
2921 struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);
2923 intr->mask_misc |= TXGBE_ICRMISC_LNKSEC;
2929 * It reads ICR and sets flag (TXGBE_ICRMISC_LSC) for the link_update.
2932 * Pointer to struct rte_eth_dev.
2935 * - On success, zero.
2936 * - On failure, a negative value.
2939 txgbe_dev_interrupt_get_status(struct rte_eth_dev *dev,
2940 struct rte_intr_handle *intr_handle)
2943 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2944 struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);
2946 if (rte_intr_type_get(intr_handle) != RTE_INTR_HANDLE_UIO &&
2947 rte_intr_type_get(intr_handle) != RTE_INTR_HANDLE_VFIO_MSIX)
2948 wr32(hw, TXGBE_PX_INTA, 1);
2950 /* clear all cause mask */
2951 txgbe_disable_intr(hw);
2953 /* read-on-clear nic registers here */
2954 eicr = ((u32 *)hw->isb_mem)[TXGBE_ISB_MISC];
2955 PMD_DRV_LOG(DEBUG, "eicr %x", eicr);
2959 /* set flag for async link update */
2960 if (eicr & TXGBE_ICRMISC_LSC)
2961 intr->flags |= TXGBE_FLAG_NEED_LINK_UPDATE;
2963 if (eicr & TXGBE_ICRMISC_ANDONE)
2964 intr->flags |= TXGBE_FLAG_NEED_AN_CONFIG;
2966 if (eicr & TXGBE_ICRMISC_VFMBX)
2967 intr->flags |= TXGBE_FLAG_MAILBOX;
2969 if (eicr & TXGBE_ICRMISC_LNKSEC)
2970 intr->flags |= TXGBE_FLAG_MACSEC;
2972 if (eicr & TXGBE_ICRMISC_GPIO)
2973 intr->flags |= TXGBE_FLAG_PHY_INTERRUPT;
2979 * It gets and then prints the link status.
2982 * Pointer to struct rte_eth_dev.
2985 * - On success, zero.
2986 * - On failure, a negative value.
2989 txgbe_dev_link_status_print(struct rte_eth_dev *dev)
2991 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2992 struct rte_eth_link link;
2994 rte_eth_linkstatus_get(dev, &link);
2996 if (link.link_status) {
2997 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
2998 (int)(dev->data->port_id),
2999 (unsigned int)link.link_speed,
3000 link.link_duplex == RTE_ETH_LINK_FULL_DUPLEX ?
3001 "full-duplex" : "half-duplex");
3003 PMD_INIT_LOG(INFO, " Port %d: Link Down",
3004 (int)(dev->data->port_id));
3006 PMD_INIT_LOG(DEBUG, "PCI Address: " PCI_PRI_FMT,
3007 pci_dev->addr.domain,
3009 pci_dev->addr.devid,
3010 pci_dev->addr.function);
3014 * It executes link_update after knowing an interrupt occurred.
3017 * Pointer to struct rte_eth_dev.
3020 * - On success, zero.
3021 * - On failure, a negative value.
3024 txgbe_dev_interrupt_action(struct rte_eth_dev *dev,
3025 struct rte_intr_handle *intr_handle)
3027 struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);
3029 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3031 PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
3033 if (intr->flags & TXGBE_FLAG_MAILBOX) {
3034 txgbe_pf_mbx_process(dev);
3035 intr->flags &= ~TXGBE_FLAG_MAILBOX;
3038 if (intr->flags & TXGBE_FLAG_PHY_INTERRUPT) {
3039 hw->phy.handle_lasi(hw);
3040 intr->flags &= ~TXGBE_FLAG_PHY_INTERRUPT;
3043 if (intr->flags & TXGBE_FLAG_NEED_AN_CONFIG) {
3044 if (hw->devarg.auto_neg == 1 && hw->devarg.poll == 0) {
3045 hw->mac.kr_handle(hw);
3046 intr->flags &= ~TXGBE_FLAG_NEED_AN_CONFIG;
3050 if (intr->flags & TXGBE_FLAG_NEED_LINK_UPDATE) {
3051 struct rte_eth_link link;
3053 /*get the link status before link update, for predicting later*/
3054 rte_eth_linkstatus_get(dev, &link);
3056 txgbe_dev_link_update(dev, 0);
3059 if (!link.link_status)
3060 /* handle it 1 sec later, wait it being stable */
3061 timeout = TXGBE_LINK_UP_CHECK_TIMEOUT;
3062 /* likely to down */
3063 else if ((hw->subsystem_device_id & 0xFF) ==
3064 TXGBE_DEV_ID_KR_KX_KX4 &&
3065 hw->devarg.auto_neg == 1)
3066 /* handle it 2 sec later for backplane AN73 */
3069 /* handle it 4 sec later, wait it being stable */
3070 timeout = TXGBE_LINK_DOWN_CHECK_TIMEOUT;
3072 txgbe_dev_link_status_print(dev);
3073 if (rte_eal_alarm_set(timeout * 1000,
3074 txgbe_dev_interrupt_delayed_handler,
3076 PMD_DRV_LOG(ERR, "Error setting alarm");
3078 /* only disable lsc interrupt */
3079 intr->mask_misc &= ~TXGBE_ICRMISC_LSC;
3081 intr->mask_orig = intr->mask;
3082 /* only disable all misc interrupts */
3083 intr->mask &= ~(1ULL << TXGBE_MISC_VEC_ID);
3087 PMD_DRV_LOG(DEBUG, "enable intr immediately");
3088 txgbe_enable_intr(dev);
3089 rte_intr_enable(intr_handle);
3095 * Interrupt handler which shall be registered for alarm callback for delayed
3096 * handling specific interrupt to wait for the stable nic state. As the
3097 * NIC interrupt state is not stable for txgbe after link is just down,
3098 * it needs to wait 4 seconds to get the stable status.
3101 * Pointer to interrupt handle.
3103 * The address of parameter (struct rte_eth_dev *) registered before.
3109 txgbe_dev_interrupt_delayed_handler(void *param)
3111 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3112 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3113 struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
3114 struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);
3115 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3118 txgbe_disable_intr(hw);
3120 eicr = ((u32 *)hw->isb_mem)[TXGBE_ISB_MISC];
3121 if (eicr & TXGBE_ICRMISC_VFMBX)
3122 txgbe_pf_mbx_process(dev);
3124 if (intr->flags & TXGBE_FLAG_PHY_INTERRUPT) {
3125 hw->phy.handle_lasi(hw);
3126 intr->flags &= ~TXGBE_FLAG_PHY_INTERRUPT;
3129 if (intr->flags & TXGBE_FLAG_NEED_LINK_UPDATE) {
3130 txgbe_dev_link_update(dev, 0);
3131 intr->flags &= ~TXGBE_FLAG_NEED_LINK_UPDATE;
3132 txgbe_dev_link_status_print(dev);
3133 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC,
3137 if (intr->flags & TXGBE_FLAG_MACSEC) {
3138 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_MACSEC,
3140 intr->flags &= ~TXGBE_FLAG_MACSEC;
3143 /* restore original mask */
3144 intr->mask_misc |= TXGBE_ICRMISC_LSC;
3146 intr->mask = intr->mask_orig;
3147 intr->mask_orig = 0;
3149 PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
3150 txgbe_enable_intr(dev);
3151 rte_intr_enable(intr_handle);
3155 * Interrupt handler triggered by NIC for handling
3156 * specific interrupt.
3159 * Pointer to interrupt handle.
3161 * The address of parameter (struct rte_eth_dev *) registered before.
3167 txgbe_dev_interrupt_handler(void *param)
3169 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3171 txgbe_dev_interrupt_get_status(dev, dev->intr_handle);
3172 txgbe_dev_interrupt_action(dev, dev->intr_handle);
3176 txgbe_dev_led_on(struct rte_eth_dev *dev)
3178 struct txgbe_hw *hw;
3180 hw = TXGBE_DEV_HW(dev);
3181 return txgbe_led_on(hw, TXGBE_LEDCTL_ACTIVE) == 0 ? 0 : -ENOTSUP;
3185 txgbe_dev_led_off(struct rte_eth_dev *dev)
3187 struct txgbe_hw *hw;
3189 hw = TXGBE_DEV_HW(dev);
3190 return txgbe_led_off(hw, TXGBE_LEDCTL_ACTIVE) == 0 ? 0 : -ENOTSUP;
3194 txgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3196 struct txgbe_hw *hw;
3202 hw = TXGBE_DEV_HW(dev);
3204 fc_conf->pause_time = hw->fc.pause_time;
3205 fc_conf->high_water = hw->fc.high_water[0];
3206 fc_conf->low_water = hw->fc.low_water[0];
3207 fc_conf->send_xon = hw->fc.send_xon;
3208 fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
3211 * Return rx_pause status according to actual setting of
3214 mflcn_reg = rd32(hw, TXGBE_RXFCCFG);
3215 if (mflcn_reg & (TXGBE_RXFCCFG_FC | TXGBE_RXFCCFG_PFC))
3221 * Return tx_pause status according to actual setting of
3224 fccfg_reg = rd32(hw, TXGBE_TXFCCFG);
3225 if (fccfg_reg & (TXGBE_TXFCCFG_FC | TXGBE_TXFCCFG_PFC))
3230 if (rx_pause && tx_pause)
3231 fc_conf->mode = RTE_ETH_FC_FULL;
3233 fc_conf->mode = RTE_ETH_FC_RX_PAUSE;
3235 fc_conf->mode = RTE_ETH_FC_TX_PAUSE;
3237 fc_conf->mode = RTE_ETH_FC_NONE;
3243 txgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3245 struct txgbe_hw *hw;
3247 uint32_t rx_buf_size;
3248 uint32_t max_high_water;
3249 enum txgbe_fc_mode rte_fcmode_2_txgbe_fcmode[] = {
3256 PMD_INIT_FUNC_TRACE();
3258 hw = TXGBE_DEV_HW(dev);
3259 rx_buf_size = rd32(hw, TXGBE_PBRXSIZE(0));
3260 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
3263 * At least reserve one Ethernet frame for watermark
3264 * high_water/low_water in kilo bytes for txgbe
3266 max_high_water = (rx_buf_size - RTE_ETHER_MAX_LEN) >> 10;
3267 if (fc_conf->high_water > max_high_water ||
3268 fc_conf->high_water < fc_conf->low_water) {
3269 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
3270 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
3274 hw->fc.requested_mode = rte_fcmode_2_txgbe_fcmode[fc_conf->mode];
3275 hw->fc.pause_time = fc_conf->pause_time;
3276 hw->fc.high_water[0] = fc_conf->high_water;
3277 hw->fc.low_water[0] = fc_conf->low_water;
3278 hw->fc.send_xon = fc_conf->send_xon;
3279 hw->fc.disable_fc_autoneg = !fc_conf->autoneg;
3281 err = txgbe_fc_enable(hw);
3283 /* Not negotiated is not an error case */
3284 if (err == 0 || err == TXGBE_ERR_FC_NOT_NEGOTIATED) {
3285 wr32m(hw, TXGBE_MACRXFLT, TXGBE_MACRXFLT_CTL_MASK,
3286 (fc_conf->mac_ctrl_frame_fwd
3287 ? TXGBE_MACRXFLT_CTL_NOPS : TXGBE_MACRXFLT_CTL_DROP));
3293 PMD_INIT_LOG(ERR, "txgbe_fc_enable = 0x%x", err);
3298 txgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
3299 struct rte_eth_pfc_conf *pfc_conf)
3302 uint32_t rx_buf_size;
3303 uint32_t max_high_water;
3305 uint8_t map[TXGBE_DCB_UP_MAX] = { 0 };
3306 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3307 struct txgbe_dcb_config *dcb_config = TXGBE_DEV_DCB_CONFIG(dev);
3309 enum txgbe_fc_mode rte_fcmode_2_txgbe_fcmode[] = {
3316 PMD_INIT_FUNC_TRACE();
3318 txgbe_dcb_unpack_map_cee(dcb_config, TXGBE_DCB_RX_CONFIG, map);
3319 tc_num = map[pfc_conf->priority];
3320 rx_buf_size = rd32(hw, TXGBE_PBRXSIZE(tc_num));
3321 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
3323 * At least reserve one Ethernet frame for watermark
3324 * high_water/low_water in kilo bytes for txgbe
3326 max_high_water = (rx_buf_size - RTE_ETHER_MAX_LEN) >> 10;
3327 if (pfc_conf->fc.high_water > max_high_water ||
3328 pfc_conf->fc.high_water <= pfc_conf->fc.low_water) {
3329 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
3330 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
3334 hw->fc.requested_mode = rte_fcmode_2_txgbe_fcmode[pfc_conf->fc.mode];
3335 hw->fc.pause_time = pfc_conf->fc.pause_time;
3336 hw->fc.send_xon = pfc_conf->fc.send_xon;
3337 hw->fc.low_water[tc_num] = pfc_conf->fc.low_water;
3338 hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
3340 err = txgbe_dcb_pfc_enable(hw, tc_num);
3342 /* Not negotiated is not an error case */
3343 if (err == 0 || err == TXGBE_ERR_FC_NOT_NEGOTIATED)
3346 PMD_INIT_LOG(ERR, "txgbe_dcb_pfc_enable = 0x%x", err);
3351 txgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
3352 struct rte_eth_rss_reta_entry64 *reta_conf,
3357 uint16_t idx, shift;
3358 struct txgbe_adapter *adapter = TXGBE_DEV_ADAPTER(dev);
3359 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3361 PMD_INIT_FUNC_TRACE();
3363 if (!txgbe_rss_update_sp(hw->mac.type)) {
3364 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this "
3369 if (reta_size != RTE_ETH_RSS_RETA_SIZE_128) {
3370 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3371 "(%d) doesn't match the number hardware can supported "
3372 "(%d)", reta_size, RTE_ETH_RSS_RETA_SIZE_128);
3376 for (i = 0; i < reta_size; i += 4) {
3377 idx = i / RTE_ETH_RETA_GROUP_SIZE;
3378 shift = i % RTE_ETH_RETA_GROUP_SIZE;
3379 mask = (uint8_t)RS64(reta_conf[idx].mask, shift, 0xF);
3383 reta = rd32at(hw, TXGBE_REG_RSSTBL, i >> 2);
3384 for (j = 0; j < 4; j++) {
3385 if (RS8(mask, j, 0x1)) {
3386 reta &= ~(MS32(8 * j, 0xFF));
3387 reta |= LS32(reta_conf[idx].reta[shift + j],
3391 wr32at(hw, TXGBE_REG_RSSTBL, i >> 2, reta);
3393 adapter->rss_reta_updated = 1;
3399 txgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
3400 struct rte_eth_rss_reta_entry64 *reta_conf,
3403 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3406 uint16_t idx, shift;
3408 PMD_INIT_FUNC_TRACE();
3410 if (reta_size != RTE_ETH_RSS_RETA_SIZE_128) {
3411 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3412 "(%d) doesn't match the number hardware can supported "
3413 "(%d)", reta_size, RTE_ETH_RSS_RETA_SIZE_128);
3417 for (i = 0; i < reta_size; i += 4) {
3418 idx = i / RTE_ETH_RETA_GROUP_SIZE;
3419 shift = i % RTE_ETH_RETA_GROUP_SIZE;
3420 mask = (uint8_t)RS64(reta_conf[idx].mask, shift, 0xF);
3424 reta = rd32at(hw, TXGBE_REG_RSSTBL, i >> 2);
3425 for (j = 0; j < 4; j++) {
3426 if (RS8(mask, j, 0x1))
3427 reta_conf[idx].reta[shift + j] =
3428 (uint16_t)RS32(reta, 8 * j, 0xFF);
3436 txgbe_add_rar(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
3437 uint32_t index, uint32_t pool)
3439 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3440 uint32_t enable_addr = 1;
3442 return txgbe_set_rar(hw, index, mac_addr->addr_bytes,
3447 txgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
3449 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3451 txgbe_clear_rar(hw, index);
3455 txgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *addr)
3457 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3459 txgbe_remove_rar(dev, 0);
3460 txgbe_add_rar(dev, addr, 0, pci_dev->max_vfs);
3466 txgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
3468 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3469 uint32_t frame_size = mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN;
3470 struct rte_eth_dev_data *dev_data = dev->data;
3472 /* If device is started, refuse mtu that requires the support of
3473 * scattered packets when this feature has not been enabled before.
3475 if (dev_data->dev_started && !dev_data->scattered_rx &&
3476 (frame_size + 2 * RTE_VLAN_HLEN >
3477 dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
3478 PMD_INIT_LOG(ERR, "Stop port first.");
3483 wr32m(hw, TXGBE_FRMSZ, TXGBE_FRMSZ_MAX_MASK,
3484 TXGBE_FRAME_SIZE_MAX);
3486 wr32m(hw, TXGBE_FRMSZ, TXGBE_FRMSZ_MAX_MASK,
3487 TXGBE_FRMSZ_MAX(frame_size));
3493 txgbe_uta_vector(struct txgbe_hw *hw, struct rte_ether_addr *uc_addr)
3495 uint32_t vector = 0;
3497 switch (hw->mac.mc_filter_type) {
3498 case 0: /* use bits [47:36] of the address */
3499 vector = ((uc_addr->addr_bytes[4] >> 4) |
3500 (((uint16_t)uc_addr->addr_bytes[5]) << 4));
3502 case 1: /* use bits [46:35] of the address */
3503 vector = ((uc_addr->addr_bytes[4] >> 3) |
3504 (((uint16_t)uc_addr->addr_bytes[5]) << 5));
3506 case 2: /* use bits [45:34] of the address */
3507 vector = ((uc_addr->addr_bytes[4] >> 2) |
3508 (((uint16_t)uc_addr->addr_bytes[5]) << 6));
3510 case 3: /* use bits [43:32] of the address */
3511 vector = ((uc_addr->addr_bytes[4]) |
3512 (((uint16_t)uc_addr->addr_bytes[5]) << 8));
3514 default: /* Invalid mc_filter_type */
3518 /* vector can only be 12-bits or boundary will be exceeded */
3524 txgbe_uc_hash_table_set(struct rte_eth_dev *dev,
3525 struct rte_ether_addr *mac_addr, uint8_t on)
3533 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3534 struct txgbe_uta_info *uta_info = TXGBE_DEV_UTA_INFO(dev);
3536 /* The UTA table only exists on pf hardware */
3537 if (hw->mac.type < txgbe_mac_raptor)
3540 vector = txgbe_uta_vector(hw, mac_addr);
3541 uta_idx = (vector >> 5) & 0x7F;
3542 uta_mask = 0x1UL << (vector & 0x1F);
3544 if (!!on == !!(uta_info->uta_shadow[uta_idx] & uta_mask))
3547 reg_val = rd32(hw, TXGBE_UCADDRTBL(uta_idx));
3549 uta_info->uta_in_use++;
3550 reg_val |= uta_mask;
3551 uta_info->uta_shadow[uta_idx] |= uta_mask;
3553 uta_info->uta_in_use--;
3554 reg_val &= ~uta_mask;
3555 uta_info->uta_shadow[uta_idx] &= ~uta_mask;
3558 wr32(hw, TXGBE_UCADDRTBL(uta_idx), reg_val);
3560 psrctl = rd32(hw, TXGBE_PSRCTL);
3561 if (uta_info->uta_in_use > 0)
3562 psrctl |= TXGBE_PSRCTL_UCHFENA;
3564 psrctl &= ~TXGBE_PSRCTL_UCHFENA;
3566 psrctl &= ~TXGBE_PSRCTL_ADHF12_MASK;
3567 psrctl |= TXGBE_PSRCTL_ADHF12(hw->mac.mc_filter_type);
3568 wr32(hw, TXGBE_PSRCTL, psrctl);
3574 txgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
3576 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3577 struct txgbe_uta_info *uta_info = TXGBE_DEV_UTA_INFO(dev);
3581 /* The UTA table only exists on pf hardware */
3582 if (hw->mac.type < txgbe_mac_raptor)
3586 for (i = 0; i < RTE_ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
3587 uta_info->uta_shadow[i] = ~0;
3588 wr32(hw, TXGBE_UCADDRTBL(i), ~0);
3591 for (i = 0; i < RTE_ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
3592 uta_info->uta_shadow[i] = 0;
3593 wr32(hw, TXGBE_UCADDRTBL(i), 0);
3597 psrctl = rd32(hw, TXGBE_PSRCTL);
3599 psrctl |= TXGBE_PSRCTL_UCHFENA;
3601 psrctl &= ~TXGBE_PSRCTL_UCHFENA;
3603 psrctl &= ~TXGBE_PSRCTL_ADHF12_MASK;
3604 psrctl |= TXGBE_PSRCTL_ADHF12(hw->mac.mc_filter_type);
3605 wr32(hw, TXGBE_PSRCTL, psrctl);
3611 txgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
3613 uint32_t new_val = orig_val;
3615 if (rx_mask & RTE_ETH_VMDQ_ACCEPT_UNTAG)
3616 new_val |= TXGBE_POOLETHCTL_UTA;
3617 if (rx_mask & RTE_ETH_VMDQ_ACCEPT_HASH_MC)
3618 new_val |= TXGBE_POOLETHCTL_MCHA;
3619 if (rx_mask & RTE_ETH_VMDQ_ACCEPT_HASH_UC)
3620 new_val |= TXGBE_POOLETHCTL_UCHA;
3621 if (rx_mask & RTE_ETH_VMDQ_ACCEPT_BROADCAST)
3622 new_val |= TXGBE_POOLETHCTL_BCA;
3623 if (rx_mask & RTE_ETH_VMDQ_ACCEPT_MULTICAST)
3624 new_val |= TXGBE_POOLETHCTL_MCP;
3630 txgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
3632 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3633 struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
3635 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3637 if (queue_id < 32) {
3638 mask = rd32(hw, TXGBE_IMS(0));
3639 mask &= (1 << queue_id);
3640 wr32(hw, TXGBE_IMS(0), mask);
3641 } else if (queue_id < 64) {
3642 mask = rd32(hw, TXGBE_IMS(1));
3643 mask &= (1 << (queue_id - 32));
3644 wr32(hw, TXGBE_IMS(1), mask);
3646 rte_intr_enable(intr_handle);
3652 txgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
3655 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3657 if (queue_id < 32) {
3658 mask = rd32(hw, TXGBE_IMS(0));
3659 mask &= ~(1 << queue_id);
3660 wr32(hw, TXGBE_IMS(0), mask);
3661 } else if (queue_id < 64) {
3662 mask = rd32(hw, TXGBE_IMS(1));
3663 mask &= ~(1 << (queue_id - 32));
3664 wr32(hw, TXGBE_IMS(1), mask);
3671 * set the IVAR registers, mapping interrupt causes to vectors
3673 * pointer to txgbe_hw struct
3675 * 0 for Rx, 1 for Tx, -1 for other causes
3677 * queue to map the corresponding interrupt to
3679 * the vector to map to the corresponding queue
3682 txgbe_set_ivar_map(struct txgbe_hw *hw, int8_t direction,
3683 uint8_t queue, uint8_t msix_vector)
3687 if (direction == -1) {
3689 msix_vector |= TXGBE_IVARMISC_VLD;
3691 tmp = rd32(hw, TXGBE_IVARMISC);
3692 tmp &= ~(0xFF << idx);
3693 tmp |= (msix_vector << idx);
3694 wr32(hw, TXGBE_IVARMISC, tmp);
3696 /* rx or tx causes */
3697 /* Workaround for ICR lost */
3698 idx = ((16 * (queue & 1)) + (8 * direction));
3699 tmp = rd32(hw, TXGBE_IVAR(queue >> 1));
3700 tmp &= ~(0xFF << idx);
3701 tmp |= (msix_vector << idx);
3702 wr32(hw, TXGBE_IVAR(queue >> 1), tmp);
3707 * Sets up the hardware to properly generate MSI-X interrupts
3709 * board private structure
3712 txgbe_configure_msix(struct rte_eth_dev *dev)
3714 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3715 struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
3716 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3717 uint32_t queue_id, base = TXGBE_MISC_VEC_ID;
3718 uint32_t vec = TXGBE_MISC_VEC_ID;
3721 /* won't configure msix register if no mapping is done
3722 * between intr vector and event fd
3723 * but if misx has been enabled already, need to configure
3724 * auto clean, auto mask and throttling.
3726 gpie = rd32(hw, TXGBE_GPIE);
3727 if (!rte_intr_dp_is_en(intr_handle) &&
3728 !(gpie & TXGBE_GPIE_MSIX))
3731 if (rte_intr_allow_others(intr_handle)) {
3732 base = TXGBE_RX_VEC_START;
3736 /* setup GPIE for MSI-x mode */
3737 gpie = rd32(hw, TXGBE_GPIE);
3738 gpie |= TXGBE_GPIE_MSIX;
3739 wr32(hw, TXGBE_GPIE, gpie);
3741 /* Populate the IVAR table and set the ITR values to the
3742 * corresponding register.
3744 if (rte_intr_dp_is_en(intr_handle)) {
3745 for (queue_id = 0; queue_id < dev->data->nb_rx_queues;
3747 /* by default, 1:1 mapping */
3748 txgbe_set_ivar_map(hw, 0, queue_id, vec);
3749 rte_intr_vec_list_index_set(intr_handle,
3751 if (vec < base + rte_intr_nb_efd_get(intr_handle)
3756 txgbe_set_ivar_map(hw, -1, 1, TXGBE_MISC_VEC_ID);
3758 wr32(hw, TXGBE_ITR(TXGBE_MISC_VEC_ID),
3759 TXGBE_ITR_IVAL_10G(TXGBE_QUEUE_ITR_INTERVAL_DEFAULT)
3764 txgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
3765 uint16_t queue_idx, uint16_t tx_rate)
3767 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3770 if (queue_idx >= hw->mac.max_tx_queues)
3774 bcnrc_val = TXGBE_ARBTXRATE_MAX(tx_rate);
3775 bcnrc_val |= TXGBE_ARBTXRATE_MIN(tx_rate / 2);
3781 * Set global transmit compensation time to the MMW_SIZE in ARBTXMMW
3782 * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported.
3784 wr32(hw, TXGBE_ARBTXMMW, 0x14);
3786 /* Set ARBTXRATE of queue X */
3787 wr32(hw, TXGBE_ARBPOOLIDX, queue_idx);
3788 wr32(hw, TXGBE_ARBTXRATE, bcnrc_val);
3795 txgbe_syn_filter_set(struct rte_eth_dev *dev,
3796 struct rte_eth_syn_filter *filter,
3799 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3800 struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(dev);
3804 if (filter->queue >= TXGBE_MAX_RX_QUEUE_NUM)
3807 syn_info = filter_info->syn_info;
3810 if (syn_info & TXGBE_SYNCLS_ENA)
3812 synqf = (uint32_t)TXGBE_SYNCLS_QPID(filter->queue);
3813 synqf |= TXGBE_SYNCLS_ENA;
3815 if (filter->hig_pri)
3816 synqf |= TXGBE_SYNCLS_HIPRIO;
3818 synqf &= ~TXGBE_SYNCLS_HIPRIO;
3820 synqf = rd32(hw, TXGBE_SYNCLS);
3821 if (!(syn_info & TXGBE_SYNCLS_ENA))
3823 synqf &= ~(TXGBE_SYNCLS_QPID_MASK | TXGBE_SYNCLS_ENA);
3826 filter_info->syn_info = synqf;
3827 wr32(hw, TXGBE_SYNCLS, synqf);
3832 static inline enum txgbe_5tuple_protocol
3833 convert_protocol_type(uint8_t protocol_value)
3835 if (protocol_value == IPPROTO_TCP)
3836 return TXGBE_5TF_PROT_TCP;
3837 else if (protocol_value == IPPROTO_UDP)
3838 return TXGBE_5TF_PROT_UDP;
3839 else if (protocol_value == IPPROTO_SCTP)
3840 return TXGBE_5TF_PROT_SCTP;
3842 return TXGBE_5TF_PROT_NONE;
3845 /* inject a 5-tuple filter to HW */
3847 txgbe_inject_5tuple_filter(struct rte_eth_dev *dev,
3848 struct txgbe_5tuple_filter *filter)
3850 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3852 uint32_t ftqf, sdpqf;
3853 uint32_t l34timir = 0;
3854 uint32_t mask = TXGBE_5TFCTL0_MASK;
3857 sdpqf = TXGBE_5TFPORT_DST(be_to_le16(filter->filter_info.dst_port));
3858 sdpqf |= TXGBE_5TFPORT_SRC(be_to_le16(filter->filter_info.src_port));
3860 ftqf = TXGBE_5TFCTL0_PROTO(filter->filter_info.proto);
3861 ftqf |= TXGBE_5TFCTL0_PRI(filter->filter_info.priority);
3862 if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
3863 mask &= ~TXGBE_5TFCTL0_MSADDR;
3864 if (filter->filter_info.dst_ip_mask == 0)
3865 mask &= ~TXGBE_5TFCTL0_MDADDR;
3866 if (filter->filter_info.src_port_mask == 0)
3867 mask &= ~TXGBE_5TFCTL0_MSPORT;
3868 if (filter->filter_info.dst_port_mask == 0)
3869 mask &= ~TXGBE_5TFCTL0_MDPORT;
3870 if (filter->filter_info.proto_mask == 0)
3871 mask &= ~TXGBE_5TFCTL0_MPROTO;
3873 ftqf |= TXGBE_5TFCTL0_MPOOL;
3874 ftqf |= TXGBE_5TFCTL0_ENA;
3876 wr32(hw, TXGBE_5TFDADDR(i), be_to_le32(filter->filter_info.dst_ip));
3877 wr32(hw, TXGBE_5TFSADDR(i), be_to_le32(filter->filter_info.src_ip));
3878 wr32(hw, TXGBE_5TFPORT(i), sdpqf);
3879 wr32(hw, TXGBE_5TFCTL0(i), ftqf);
3881 l34timir |= TXGBE_5TFCTL1_QP(filter->queue);
3882 wr32(hw, TXGBE_5TFCTL1(i), l34timir);
3886 * add a 5tuple filter
3889 * dev: Pointer to struct rte_eth_dev.
3890 * index: the index the filter allocates.
3891 * filter: pointer to the filter that will be added.
3892 * rx_queue: the queue id the filter assigned to.
3895 * - On success, zero.
3896 * - On failure, a negative value.
3899 txgbe_add_5tuple_filter(struct rte_eth_dev *dev,
3900 struct txgbe_5tuple_filter *filter)
3902 struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(dev);
3906 * look for an unused 5tuple filter index,
3907 * and insert the filter to list.
3909 for (i = 0; i < TXGBE_MAX_FTQF_FILTERS; i++) {
3910 idx = i / (sizeof(uint32_t) * NBBY);
3911 shift = i % (sizeof(uint32_t) * NBBY);
3912 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
3913 filter_info->fivetuple_mask[idx] |= 1 << shift;
3915 TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
3921 if (i >= TXGBE_MAX_FTQF_FILTERS) {
3922 PMD_DRV_LOG(ERR, "5tuple filters are full.");
3926 txgbe_inject_5tuple_filter(dev, filter);
3932 * remove a 5tuple filter
3935 * dev: Pointer to struct rte_eth_dev.
3936 * filter: the pointer of the filter will be removed.
3939 txgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
3940 struct txgbe_5tuple_filter *filter)
3942 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3943 struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(dev);
3944 uint16_t index = filter->index;
3946 filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
3947 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
3948 TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
3951 wr32(hw, TXGBE_5TFDADDR(index), 0);
3952 wr32(hw, TXGBE_5TFSADDR(index), 0);
3953 wr32(hw, TXGBE_5TFPORT(index), 0);
3954 wr32(hw, TXGBE_5TFCTL0(index), 0);
3955 wr32(hw, TXGBE_5TFCTL1(index), 0);
3958 static inline struct txgbe_5tuple_filter *
3959 txgbe_5tuple_filter_lookup(struct txgbe_5tuple_filter_list *filter_list,
3960 struct txgbe_5tuple_filter_info *key)
3962 struct txgbe_5tuple_filter *it;
3964 TAILQ_FOREACH(it, filter_list, entries) {
3965 if (memcmp(key, &it->filter_info,
3966 sizeof(struct txgbe_5tuple_filter_info)) == 0) {
3973 /* translate elements in struct rte_eth_ntuple_filter
3974 * to struct txgbe_5tuple_filter_info
3977 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
3978 struct txgbe_5tuple_filter_info *filter_info)
3980 if (filter->queue >= TXGBE_MAX_RX_QUEUE_NUM ||
3981 filter->priority > TXGBE_5TUPLE_MAX_PRI ||
3982 filter->priority < TXGBE_5TUPLE_MIN_PRI)
3985 switch (filter->dst_ip_mask) {
3987 filter_info->dst_ip_mask = 0;
3988 filter_info->dst_ip = filter->dst_ip;
3991 filter_info->dst_ip_mask = 1;
3994 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
3998 switch (filter->src_ip_mask) {
4000 filter_info->src_ip_mask = 0;
4001 filter_info->src_ip = filter->src_ip;
4004 filter_info->src_ip_mask = 1;
4007 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
4011 switch (filter->dst_port_mask) {
4013 filter_info->dst_port_mask = 0;
4014 filter_info->dst_port = filter->dst_port;
4017 filter_info->dst_port_mask = 1;
4020 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
4024 switch (filter->src_port_mask) {
4026 filter_info->src_port_mask = 0;
4027 filter_info->src_port = filter->src_port;
4030 filter_info->src_port_mask = 1;
4033 PMD_DRV_LOG(ERR, "invalid src_port mask.");
4037 switch (filter->proto_mask) {
4039 filter_info->proto_mask = 0;
4040 filter_info->proto =
4041 convert_protocol_type(filter->proto);
4044 filter_info->proto_mask = 1;
4047 PMD_DRV_LOG(ERR, "invalid protocol mask.");
4051 filter_info->priority = (uint8_t)filter->priority;
4056 * add or delete a ntuple filter
4059 * dev: Pointer to struct rte_eth_dev.
4060 * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
4061 * add: if true, add filter, if false, remove filter
4064 * - On success, zero.
4065 * - On failure, a negative value.
4068 txgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
4069 struct rte_eth_ntuple_filter *ntuple_filter,
4072 struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(dev);
4073 struct txgbe_5tuple_filter_info filter_5tuple;
4074 struct txgbe_5tuple_filter *filter;
4077 if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
4078 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
4082 memset(&filter_5tuple, 0, sizeof(struct txgbe_5tuple_filter_info));
4083 ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
4087 filter = txgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
4089 if (filter != NULL && add) {
4090 PMD_DRV_LOG(ERR, "filter exists.");
4093 if (filter == NULL && !add) {
4094 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4099 filter = rte_zmalloc("txgbe_5tuple_filter",
4100 sizeof(struct txgbe_5tuple_filter), 0);
4103 rte_memcpy(&filter->filter_info,
4105 sizeof(struct txgbe_5tuple_filter_info));
4106 filter->queue = ntuple_filter->queue;
4107 ret = txgbe_add_5tuple_filter(dev, filter);
4113 txgbe_remove_5tuple_filter(dev, filter);
4120 txgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
4121 struct rte_eth_ethertype_filter *filter,
4124 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4125 struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(dev);
4129 struct txgbe_ethertype_filter ethertype_filter;
4131 if (filter->queue >= TXGBE_MAX_RX_QUEUE_NUM)
4134 if (filter->ether_type == RTE_ETHER_TYPE_IPV4 ||
4135 filter->ether_type == RTE_ETHER_TYPE_IPV6) {
4136 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
4137 " ethertype filter.", filter->ether_type);
4141 if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
4142 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
4145 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
4146 PMD_DRV_LOG(ERR, "drop option is unsupported.");
4150 ret = txgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
4151 if (ret >= 0 && add) {
4152 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
4153 filter->ether_type);
4156 if (ret < 0 && !add) {
4157 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
4158 filter->ether_type);
4163 etqf = TXGBE_ETFLT_ENA;
4164 etqf |= TXGBE_ETFLT_ETID(filter->ether_type);
4165 etqs |= TXGBE_ETCLS_QPID(filter->queue);
4166 etqs |= TXGBE_ETCLS_QENA;
4168 ethertype_filter.ethertype = filter->ether_type;
4169 ethertype_filter.etqf = etqf;
4170 ethertype_filter.etqs = etqs;
4171 ethertype_filter.conf = FALSE;
4172 ret = txgbe_ethertype_filter_insert(filter_info,
4175 PMD_DRV_LOG(ERR, "ethertype filters are full.");
4179 ret = txgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
4183 wr32(hw, TXGBE_ETFLT(ret), etqf);
4184 wr32(hw, TXGBE_ETCLS(ret), etqs);
4191 txgbe_dev_flow_ops_get(__rte_unused struct rte_eth_dev *dev,
4192 const struct rte_flow_ops **ops)
4194 *ops = &txgbe_flow_ops;
4199 txgbe_dev_addr_list_itr(__rte_unused struct txgbe_hw *hw,
4200 u8 **mc_addr_ptr, u32 *vmdq)
4205 mc_addr = *mc_addr_ptr;
4206 *mc_addr_ptr = (mc_addr + sizeof(struct rte_ether_addr));
4211 txgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
4212 struct rte_ether_addr *mc_addr_set,
4213 uint32_t nb_mc_addr)
4215 struct txgbe_hw *hw;
4218 hw = TXGBE_DEV_HW(dev);
4219 mc_addr_list = (u8 *)mc_addr_set;
4220 return hw->mac.update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
4221 txgbe_dev_addr_list_itr, TRUE);
4225 txgbe_read_systime_cyclecounter(struct rte_eth_dev *dev)
4227 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4228 uint64_t systime_cycles;
4230 systime_cycles = (uint64_t)rd32(hw, TXGBE_TSTIMEL);
4231 systime_cycles |= (uint64_t)rd32(hw, TXGBE_TSTIMEH) << 32;
4233 return systime_cycles;
4237 txgbe_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
4239 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4240 uint64_t rx_tstamp_cycles;
4242 /* TSRXSTMPL stores ns and TSRXSTMPH stores seconds. */
4243 rx_tstamp_cycles = (uint64_t)rd32(hw, TXGBE_TSRXSTMPL);
4244 rx_tstamp_cycles |= (uint64_t)rd32(hw, TXGBE_TSRXSTMPH) << 32;
4246 return rx_tstamp_cycles;
4250 txgbe_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
4252 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4253 uint64_t tx_tstamp_cycles;
4255 /* TSTXSTMPL stores ns and TSTXSTMPH stores seconds. */
4256 tx_tstamp_cycles = (uint64_t)rd32(hw, TXGBE_TSTXSTMPL);
4257 tx_tstamp_cycles |= (uint64_t)rd32(hw, TXGBE_TSTXSTMPH) << 32;
4259 return tx_tstamp_cycles;
4263 txgbe_start_timecounters(struct rte_eth_dev *dev)
4265 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4266 struct txgbe_adapter *adapter = TXGBE_DEV_ADAPTER(dev);
4267 struct rte_eth_link link;
4268 uint32_t incval = 0;
4271 /* Get current link speed. */
4272 txgbe_dev_link_update(dev, 1);
4273 rte_eth_linkstatus_get(dev, &link);
4275 switch (link.link_speed) {
4276 case RTE_ETH_SPEED_NUM_100M:
4277 incval = TXGBE_INCVAL_100;
4278 shift = TXGBE_INCVAL_SHIFT_100;
4280 case RTE_ETH_SPEED_NUM_1G:
4281 incval = TXGBE_INCVAL_1GB;
4282 shift = TXGBE_INCVAL_SHIFT_1GB;
4284 case RTE_ETH_SPEED_NUM_10G:
4286 incval = TXGBE_INCVAL_10GB;
4287 shift = TXGBE_INCVAL_SHIFT_10GB;
4291 wr32(hw, TXGBE_TSTIMEINC, TXGBE_TSTIMEINC_VP(incval, 2));
4293 memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
4294 memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
4295 memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
4297 adapter->systime_tc.cc_mask = TXGBE_CYCLECOUNTER_MASK;
4298 adapter->systime_tc.cc_shift = shift;
4299 adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
4301 adapter->rx_tstamp_tc.cc_mask = TXGBE_CYCLECOUNTER_MASK;
4302 adapter->rx_tstamp_tc.cc_shift = shift;
4303 adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
4305 adapter->tx_tstamp_tc.cc_mask = TXGBE_CYCLECOUNTER_MASK;
4306 adapter->tx_tstamp_tc.cc_shift = shift;
4307 adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
4311 txgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
4313 struct txgbe_adapter *adapter = TXGBE_DEV_ADAPTER(dev);
4315 adapter->systime_tc.nsec += delta;
4316 adapter->rx_tstamp_tc.nsec += delta;
4317 adapter->tx_tstamp_tc.nsec += delta;
4323 txgbe_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
4326 struct txgbe_adapter *adapter = TXGBE_DEV_ADAPTER(dev);
4328 ns = rte_timespec_to_ns(ts);
4329 /* Set the timecounters to a new value. */
4330 adapter->systime_tc.nsec = ns;
4331 adapter->rx_tstamp_tc.nsec = ns;
4332 adapter->tx_tstamp_tc.nsec = ns;
4338 txgbe_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
4340 uint64_t ns, systime_cycles;
4341 struct txgbe_adapter *adapter = TXGBE_DEV_ADAPTER(dev);
4343 systime_cycles = txgbe_read_systime_cyclecounter(dev);
4344 ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
4345 *ts = rte_ns_to_timespec(ns);
4351 txgbe_timesync_enable(struct rte_eth_dev *dev)
4353 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4356 /* Stop the timesync system time. */
4357 wr32(hw, TXGBE_TSTIMEINC, 0x0);
4358 /* Reset the timesync system time value. */
4359 wr32(hw, TXGBE_TSTIMEL, 0x0);
4360 wr32(hw, TXGBE_TSTIMEH, 0x0);
4362 txgbe_start_timecounters(dev);
4364 /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
4365 wr32(hw, TXGBE_ETFLT(TXGBE_ETF_ID_1588),
4366 RTE_ETHER_TYPE_1588 | TXGBE_ETFLT_ENA | TXGBE_ETFLT_1588);
4368 /* Enable timestamping of received PTP packets. */
4369 tsync_ctl = rd32(hw, TXGBE_TSRXCTL);
4370 tsync_ctl |= TXGBE_TSRXCTL_ENA;
4371 wr32(hw, TXGBE_TSRXCTL, tsync_ctl);
4373 /* Enable timestamping of transmitted PTP packets. */
4374 tsync_ctl = rd32(hw, TXGBE_TSTXCTL);
4375 tsync_ctl |= TXGBE_TSTXCTL_ENA;
4376 wr32(hw, TXGBE_TSTXCTL, tsync_ctl);
4384 txgbe_timesync_disable(struct rte_eth_dev *dev)
4386 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4389 /* Disable timestamping of transmitted PTP packets. */
4390 tsync_ctl = rd32(hw, TXGBE_TSTXCTL);
4391 tsync_ctl &= ~TXGBE_TSTXCTL_ENA;
4392 wr32(hw, TXGBE_TSTXCTL, tsync_ctl);
4394 /* Disable timestamping of received PTP packets. */
4395 tsync_ctl = rd32(hw, TXGBE_TSRXCTL);
4396 tsync_ctl &= ~TXGBE_TSRXCTL_ENA;
4397 wr32(hw, TXGBE_TSRXCTL, tsync_ctl);
4399 /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
4400 wr32(hw, TXGBE_ETFLT(TXGBE_ETF_ID_1588), 0);
4402 /* Stop incrementing the System Time registers. */
4403 wr32(hw, TXGBE_TSTIMEINC, 0);
4409 txgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
4410 struct timespec *timestamp,
4411 uint32_t flags __rte_unused)
4413 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4414 struct txgbe_adapter *adapter = TXGBE_DEV_ADAPTER(dev);
4415 uint32_t tsync_rxctl;
4416 uint64_t rx_tstamp_cycles;
4419 tsync_rxctl = rd32(hw, TXGBE_TSRXCTL);
4420 if ((tsync_rxctl & TXGBE_TSRXCTL_VLD) == 0)
4423 rx_tstamp_cycles = txgbe_read_rx_tstamp_cyclecounter(dev);
4424 ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
4425 *timestamp = rte_ns_to_timespec(ns);
4431 txgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
4432 struct timespec *timestamp)
4434 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4435 struct txgbe_adapter *adapter = TXGBE_DEV_ADAPTER(dev);
4436 uint32_t tsync_txctl;
4437 uint64_t tx_tstamp_cycles;
4440 tsync_txctl = rd32(hw, TXGBE_TSTXCTL);
4441 if ((tsync_txctl & TXGBE_TSTXCTL_VLD) == 0)
4444 tx_tstamp_cycles = txgbe_read_tx_tstamp_cyclecounter(dev);
4445 ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
4446 *timestamp = rte_ns_to_timespec(ns);
4452 txgbe_get_reg_length(struct rte_eth_dev *dev __rte_unused)
4456 const struct reg_info *reg_group;
4457 const struct reg_info **reg_set = txgbe_regs_others;
4459 while ((reg_group = reg_set[g_ind++]))
4460 count += txgbe_regs_group_count(reg_group);
4466 txgbe_get_regs(struct rte_eth_dev *dev,
4467 struct rte_dev_reg_info *regs)
4469 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4470 uint32_t *data = regs->data;
4473 const struct reg_info *reg_group;
4474 const struct reg_info **reg_set = txgbe_regs_others;
4477 regs->length = txgbe_get_reg_length(dev);
4478 regs->width = sizeof(uint32_t);
4482 /* Support only full register dump */
4483 if (regs->length == 0 ||
4484 regs->length == (uint32_t)txgbe_get_reg_length(dev)) {
4485 regs->version = hw->mac.type << 24 |
4486 hw->revision_id << 16 |
4488 while ((reg_group = reg_set[g_ind++]))
4489 count += txgbe_read_regs_group(dev, &data[count],
4498 txgbe_get_eeprom_length(struct rte_eth_dev *dev)
4500 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4502 /* Return unit is byte count */
4503 return hw->rom.word_size * 2;
4507 txgbe_get_eeprom(struct rte_eth_dev *dev,
4508 struct rte_dev_eeprom_info *in_eeprom)
4510 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4511 struct txgbe_rom_info *eeprom = &hw->rom;
4512 uint16_t *data = in_eeprom->data;
4515 first = in_eeprom->offset >> 1;
4516 length = in_eeprom->length >> 1;
4517 if (first > hw->rom.word_size ||
4518 ((first + length) > hw->rom.word_size))
4521 in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
4523 return eeprom->readw_buffer(hw, first, length, data);
4527 txgbe_set_eeprom(struct rte_eth_dev *dev,
4528 struct rte_dev_eeprom_info *in_eeprom)
4530 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4531 struct txgbe_rom_info *eeprom = &hw->rom;
4532 uint16_t *data = in_eeprom->data;
4535 first = in_eeprom->offset >> 1;
4536 length = in_eeprom->length >> 1;
4537 if (first > hw->rom.word_size ||
4538 ((first + length) > hw->rom.word_size))
4541 in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
4543 return eeprom->writew_buffer(hw, first, length, data);
4547 txgbe_get_module_info(struct rte_eth_dev *dev,
4548 struct rte_eth_dev_module_info *modinfo)
4550 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4552 uint8_t sff8472_rev, addr_mode;
4553 bool page_swap = false;
4555 /* Check whether we support SFF-8472 or not */
4556 status = hw->phy.read_i2c_eeprom(hw,
4557 TXGBE_SFF_SFF_8472_COMP,
4562 /* addressing mode is not supported */
4563 status = hw->phy.read_i2c_eeprom(hw,
4564 TXGBE_SFF_SFF_8472_SWAP,
4569 if (addr_mode & TXGBE_SFF_ADDRESSING_MODE) {
4571 "Address change required to access page 0xA2, "
4572 "but not supported. Please report the module "
4573 "type to the driver maintainers.");
4577 if (sff8472_rev == TXGBE_SFF_SFF_8472_UNSUP || page_swap) {
4578 /* We have a SFP, but it does not support SFF-8472 */
4579 modinfo->type = RTE_ETH_MODULE_SFF_8079;
4580 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
4582 /* We have a SFP which supports a revision of SFF-8472. */
4583 modinfo->type = RTE_ETH_MODULE_SFF_8472;
4584 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
4591 txgbe_get_module_eeprom(struct rte_eth_dev *dev,
4592 struct rte_dev_eeprom_info *info)
4594 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4595 uint32_t status = TXGBE_ERR_PHY_ADDR_INVALID;
4596 uint8_t databyte = 0xFF;
4597 uint8_t *data = info->data;
4600 if (info->length == 0)
4603 for (i = info->offset; i < info->offset + info->length; i++) {
4604 if (i < RTE_ETH_MODULE_SFF_8079_LEN)
4605 status = hw->phy.read_i2c_eeprom(hw, i, &databyte);
4607 status = hw->phy.read_i2c_sff8472(hw, i, &databyte);
4612 data[i - info->offset] = databyte;
4619 txgbe_rss_update_sp(enum txgbe_mac_type mac_type)
4622 case txgbe_mac_raptor:
4623 case txgbe_mac_raptor_vf:
4631 txgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
4632 struct rte_eth_dcb_info *dcb_info)
4634 struct txgbe_dcb_config *dcb_config = TXGBE_DEV_DCB_CONFIG(dev);
4635 struct txgbe_dcb_tc_config *tc;
4636 struct rte_eth_dcb_tc_queue_mapping *tc_queue;
4640 if (dev->data->dev_conf.rxmode.mq_mode & RTE_ETH_MQ_RX_DCB_FLAG)
4641 dcb_info->nb_tcs = dcb_config->num_tcs.pg_tcs;
4643 dcb_info->nb_tcs = 1;
4645 tc_queue = &dcb_info->tc_queue;
4646 nb_tcs = dcb_info->nb_tcs;
4648 if (dcb_config->vt_mode) { /* vt is enabled */
4649 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
4650 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
4651 for (i = 0; i < RTE_ETH_DCB_NUM_USER_PRIORITIES; i++)
4652 dcb_info->prio_tc[i] = vmdq_rx_conf->dcb_tc[i];
4653 if (RTE_ETH_DEV_SRIOV(dev).active > 0) {
4654 for (j = 0; j < nb_tcs; j++) {
4655 tc_queue->tc_rxq[0][j].base = j;
4656 tc_queue->tc_rxq[0][j].nb_queue = 1;
4657 tc_queue->tc_txq[0][j].base = j;
4658 tc_queue->tc_txq[0][j].nb_queue = 1;
4661 for (i = 0; i < vmdq_rx_conf->nb_queue_pools; i++) {
4662 for (j = 0; j < nb_tcs; j++) {
4663 tc_queue->tc_rxq[i][j].base =
4665 tc_queue->tc_rxq[i][j].nb_queue = 1;
4666 tc_queue->tc_txq[i][j].base =
4668 tc_queue->tc_txq[i][j].nb_queue = 1;
4672 } else { /* vt is disabled */
4673 struct rte_eth_dcb_rx_conf *rx_conf =
4674 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
4675 for (i = 0; i < RTE_ETH_DCB_NUM_USER_PRIORITIES; i++)
4676 dcb_info->prio_tc[i] = rx_conf->dcb_tc[i];
4677 if (dcb_info->nb_tcs == RTE_ETH_4_TCS) {
4678 for (i = 0; i < dcb_info->nb_tcs; i++) {
4679 dcb_info->tc_queue.tc_rxq[0][i].base = i * 32;
4680 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
4682 dcb_info->tc_queue.tc_txq[0][0].base = 0;
4683 dcb_info->tc_queue.tc_txq[0][1].base = 64;
4684 dcb_info->tc_queue.tc_txq[0][2].base = 96;
4685 dcb_info->tc_queue.tc_txq[0][3].base = 112;
4686 dcb_info->tc_queue.tc_txq[0][0].nb_queue = 64;
4687 dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
4688 dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
4689 dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
4690 } else if (dcb_info->nb_tcs == RTE_ETH_8_TCS) {
4691 for (i = 0; i < dcb_info->nb_tcs; i++) {
4692 dcb_info->tc_queue.tc_rxq[0][i].base = i * 16;
4693 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
4695 dcb_info->tc_queue.tc_txq[0][0].base = 0;
4696 dcb_info->tc_queue.tc_txq[0][1].base = 32;
4697 dcb_info->tc_queue.tc_txq[0][2].base = 64;
4698 dcb_info->tc_queue.tc_txq[0][3].base = 80;
4699 dcb_info->tc_queue.tc_txq[0][4].base = 96;
4700 dcb_info->tc_queue.tc_txq[0][5].base = 104;
4701 dcb_info->tc_queue.tc_txq[0][6].base = 112;
4702 dcb_info->tc_queue.tc_txq[0][7].base = 120;
4703 dcb_info->tc_queue.tc_txq[0][0].nb_queue = 32;
4704 dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
4705 dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
4706 dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
4707 dcb_info->tc_queue.tc_txq[0][4].nb_queue = 8;
4708 dcb_info->tc_queue.tc_txq[0][5].nb_queue = 8;
4709 dcb_info->tc_queue.tc_txq[0][6].nb_queue = 8;
4710 dcb_info->tc_queue.tc_txq[0][7].nb_queue = 8;
4713 for (i = 0; i < dcb_info->nb_tcs; i++) {
4714 tc = &dcb_config->tc_config[i];
4715 dcb_info->tc_bws[i] = tc->path[TXGBE_DCB_TX_CONFIG].bwg_percent;
4720 /* Update e-tag ether type */
4722 txgbe_update_e_tag_eth_type(struct txgbe_hw *hw,
4723 uint16_t ether_type)
4725 uint32_t etag_etype;
4727 etag_etype = rd32(hw, TXGBE_EXTAG);
4728 etag_etype &= ~TXGBE_EXTAG_ETAG_MASK;
4729 etag_etype |= ether_type;
4730 wr32(hw, TXGBE_EXTAG, etag_etype);
4736 /* Enable e-tag tunnel */
4738 txgbe_e_tag_enable(struct txgbe_hw *hw)
4740 uint32_t etag_etype;
4742 etag_etype = rd32(hw, TXGBE_PORTCTL);
4743 etag_etype |= TXGBE_PORTCTL_ETAG;
4744 wr32(hw, TXGBE_PORTCTL, etag_etype);
4751 txgbe_e_tag_filter_del(struct rte_eth_dev *dev,
4752 struct txgbe_l2_tunnel_conf *l2_tunnel)
4755 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4756 uint32_t i, rar_entries;
4757 uint32_t rar_low, rar_high;
4759 rar_entries = hw->mac.num_rar_entries;
4761 for (i = 1; i < rar_entries; i++) {
4762 wr32(hw, TXGBE_ETHADDRIDX, i);
4763 rar_high = rd32(hw, TXGBE_ETHADDRH);
4764 rar_low = rd32(hw, TXGBE_ETHADDRL);
4765 if ((rar_high & TXGBE_ETHADDRH_VLD) &&
4766 (rar_high & TXGBE_ETHADDRH_ETAG) &&
4767 (TXGBE_ETHADDRL_ETAG(rar_low) ==
4768 l2_tunnel->tunnel_id)) {
4769 wr32(hw, TXGBE_ETHADDRL, 0);
4770 wr32(hw, TXGBE_ETHADDRH, 0);
4772 txgbe_clear_vmdq(hw, i, BIT_MASK32);
4782 txgbe_e_tag_filter_add(struct rte_eth_dev *dev,
4783 struct txgbe_l2_tunnel_conf *l2_tunnel)
4786 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4787 uint32_t i, rar_entries;
4788 uint32_t rar_low, rar_high;
4790 /* One entry for one tunnel. Try to remove potential existing entry. */
4791 txgbe_e_tag_filter_del(dev, l2_tunnel);
4793 rar_entries = hw->mac.num_rar_entries;
4795 for (i = 1; i < rar_entries; i++) {
4796 wr32(hw, TXGBE_ETHADDRIDX, i);
4797 rar_high = rd32(hw, TXGBE_ETHADDRH);
4798 if (rar_high & TXGBE_ETHADDRH_VLD) {
4801 txgbe_set_vmdq(hw, i, l2_tunnel->pool);
4802 rar_high = TXGBE_ETHADDRH_VLD | TXGBE_ETHADDRH_ETAG;
4803 rar_low = l2_tunnel->tunnel_id;
4805 wr32(hw, TXGBE_ETHADDRL, rar_low);
4806 wr32(hw, TXGBE_ETHADDRH, rar_high);
4812 PMD_INIT_LOG(NOTICE, "The table of E-tag forwarding rule is full."
4813 " Please remove a rule before adding a new one.");
4817 static inline struct txgbe_l2_tn_filter *
4818 txgbe_l2_tn_filter_lookup(struct txgbe_l2_tn_info *l2_tn_info,
4819 struct txgbe_l2_tn_key *key)
4823 ret = rte_hash_lookup(l2_tn_info->hash_handle, (const void *)key);
4827 return l2_tn_info->hash_map[ret];
4831 txgbe_insert_l2_tn_filter(struct txgbe_l2_tn_info *l2_tn_info,
4832 struct txgbe_l2_tn_filter *l2_tn_filter)
4836 ret = rte_hash_add_key(l2_tn_info->hash_handle,
4837 &l2_tn_filter->key);
4841 "Failed to insert L2 tunnel filter"
4842 " to hash table %d!",
4847 l2_tn_info->hash_map[ret] = l2_tn_filter;
4849 TAILQ_INSERT_TAIL(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
4855 txgbe_remove_l2_tn_filter(struct txgbe_l2_tn_info *l2_tn_info,
4856 struct txgbe_l2_tn_key *key)
4859 struct txgbe_l2_tn_filter *l2_tn_filter;
4861 ret = rte_hash_del_key(l2_tn_info->hash_handle, key);
4865 "No such L2 tunnel filter to delete %d!",
4870 l2_tn_filter = l2_tn_info->hash_map[ret];
4871 l2_tn_info->hash_map[ret] = NULL;
4873 TAILQ_REMOVE(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
4874 rte_free(l2_tn_filter);
4879 /* Add l2 tunnel filter */
4881 txgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev,
4882 struct txgbe_l2_tunnel_conf *l2_tunnel,
4886 struct txgbe_l2_tn_info *l2_tn_info = TXGBE_DEV_L2_TN(dev);
4887 struct txgbe_l2_tn_key key;
4888 struct txgbe_l2_tn_filter *node;
4891 key.l2_tn_type = l2_tunnel->l2_tunnel_type;
4892 key.tn_id = l2_tunnel->tunnel_id;
4894 node = txgbe_l2_tn_filter_lookup(l2_tn_info, &key);
4898 "The L2 tunnel filter already exists!");
4902 node = rte_zmalloc("txgbe_l2_tn",
4903 sizeof(struct txgbe_l2_tn_filter),
4908 rte_memcpy(&node->key,
4910 sizeof(struct txgbe_l2_tn_key));
4911 node->pool = l2_tunnel->pool;
4912 ret = txgbe_insert_l2_tn_filter(l2_tn_info, node);
4919 switch (l2_tunnel->l2_tunnel_type) {
4920 case RTE_ETH_L2_TUNNEL_TYPE_E_TAG:
4921 ret = txgbe_e_tag_filter_add(dev, l2_tunnel);
4924 PMD_DRV_LOG(ERR, "Invalid tunnel type");
4929 if (!restore && ret < 0)
4930 (void)txgbe_remove_l2_tn_filter(l2_tn_info, &key);
4935 /* Delete l2 tunnel filter */
4937 txgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev,
4938 struct txgbe_l2_tunnel_conf *l2_tunnel)
4941 struct txgbe_l2_tn_info *l2_tn_info = TXGBE_DEV_L2_TN(dev);
4942 struct txgbe_l2_tn_key key;
4944 key.l2_tn_type = l2_tunnel->l2_tunnel_type;
4945 key.tn_id = l2_tunnel->tunnel_id;
4946 ret = txgbe_remove_l2_tn_filter(l2_tn_info, &key);
4950 switch (l2_tunnel->l2_tunnel_type) {
4951 case RTE_ETH_L2_TUNNEL_TYPE_E_TAG:
4952 ret = txgbe_e_tag_filter_del(dev, l2_tunnel);
4955 PMD_DRV_LOG(ERR, "Invalid tunnel type");
4964 txgbe_e_tag_forwarding_en_dis(struct rte_eth_dev *dev, bool en)
4968 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4970 ctrl = rd32(hw, TXGBE_POOLCTL);
4971 ctrl &= ~TXGBE_POOLCTL_MODE_MASK;
4973 ctrl |= TXGBE_PSRPOOL_MODE_ETAG;
4974 wr32(hw, TXGBE_POOLCTL, ctrl);
4979 /* Add UDP tunneling port */
4981 txgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
4982 struct rte_eth_udp_tunnel *udp_tunnel)
4984 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4987 if (udp_tunnel == NULL)
4990 switch (udp_tunnel->prot_type) {
4991 case RTE_ETH_TUNNEL_TYPE_VXLAN:
4992 if (udp_tunnel->udp_port == 0) {
4993 PMD_DRV_LOG(ERR, "Add VxLAN port 0 is not allowed.");
4997 wr32(hw, TXGBE_VXLANPORT, udp_tunnel->udp_port);
4999 case RTE_ETH_TUNNEL_TYPE_GENEVE:
5000 if (udp_tunnel->udp_port == 0) {
5001 PMD_DRV_LOG(ERR, "Add Geneve port 0 is not allowed.");
5005 wr32(hw, TXGBE_GENEVEPORT, udp_tunnel->udp_port);
5007 case RTE_ETH_TUNNEL_TYPE_TEREDO:
5008 if (udp_tunnel->udp_port == 0) {
5009 PMD_DRV_LOG(ERR, "Add Teredo port 0 is not allowed.");
5013 wr32(hw, TXGBE_TEREDOPORT, udp_tunnel->udp_port);
5015 case RTE_ETH_TUNNEL_TYPE_VXLAN_GPE:
5016 if (udp_tunnel->udp_port == 0) {
5017 PMD_DRV_LOG(ERR, "Add VxLAN port 0 is not allowed.");
5021 wr32(hw, TXGBE_VXLANPORTGPE, udp_tunnel->udp_port);
5024 PMD_DRV_LOG(ERR, "Invalid tunnel type");
5034 /* Remove UDP tunneling port */
5036 txgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
5037 struct rte_eth_udp_tunnel *udp_tunnel)
5039 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
5043 if (udp_tunnel == NULL)
5046 switch (udp_tunnel->prot_type) {
5047 case RTE_ETH_TUNNEL_TYPE_VXLAN:
5048 cur_port = (uint16_t)rd32(hw, TXGBE_VXLANPORT);
5049 if (cur_port != udp_tunnel->udp_port) {
5050 PMD_DRV_LOG(ERR, "Port %u does not exist.",
5051 udp_tunnel->udp_port);
5055 wr32(hw, TXGBE_VXLANPORT, 0);
5057 case RTE_ETH_TUNNEL_TYPE_GENEVE:
5058 cur_port = (uint16_t)rd32(hw, TXGBE_GENEVEPORT);
5059 if (cur_port != udp_tunnel->udp_port) {
5060 PMD_DRV_LOG(ERR, "Port %u does not exist.",
5061 udp_tunnel->udp_port);
5065 wr32(hw, TXGBE_GENEVEPORT, 0);
5067 case RTE_ETH_TUNNEL_TYPE_TEREDO:
5068 cur_port = (uint16_t)rd32(hw, TXGBE_TEREDOPORT);
5069 if (cur_port != udp_tunnel->udp_port) {
5070 PMD_DRV_LOG(ERR, "Port %u does not exist.",
5071 udp_tunnel->udp_port);
5075 wr32(hw, TXGBE_TEREDOPORT, 0);
5077 case RTE_ETH_TUNNEL_TYPE_VXLAN_GPE:
5078 cur_port = (uint16_t)rd32(hw, TXGBE_VXLANPORTGPE);
5079 if (cur_port != udp_tunnel->udp_port) {
5080 PMD_DRV_LOG(ERR, "Port %u does not exist.",
5081 udp_tunnel->udp_port);
5085 wr32(hw, TXGBE_VXLANPORTGPE, 0);
5088 PMD_DRV_LOG(ERR, "Invalid tunnel type");
5098 /* restore n-tuple filter */
5100 txgbe_ntuple_filter_restore(struct rte_eth_dev *dev)
5102 struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(dev);
5103 struct txgbe_5tuple_filter *node;
5105 TAILQ_FOREACH(node, &filter_info->fivetuple_list, entries) {
5106 txgbe_inject_5tuple_filter(dev, node);
5110 /* restore ethernet type filter */
5112 txgbe_ethertype_filter_restore(struct rte_eth_dev *dev)
5114 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
5115 struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(dev);
5118 for (i = 0; i < TXGBE_ETF_ID_MAX; i++) {
5119 if (filter_info->ethertype_mask & (1 << i)) {
5120 wr32(hw, TXGBE_ETFLT(i),
5121 filter_info->ethertype_filters[i].etqf);
5122 wr32(hw, TXGBE_ETCLS(i),
5123 filter_info->ethertype_filters[i].etqs);
5129 /* restore SYN filter */
5131 txgbe_syn_filter_restore(struct rte_eth_dev *dev)
5133 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
5134 struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(dev);
5137 synqf = filter_info->syn_info;
5139 if (synqf & TXGBE_SYNCLS_ENA) {
5140 wr32(hw, TXGBE_SYNCLS, synqf);
5145 /* restore L2 tunnel filter */
5147 txgbe_l2_tn_filter_restore(struct rte_eth_dev *dev)
5149 struct txgbe_l2_tn_info *l2_tn_info = TXGBE_DEV_L2_TN(dev);
5150 struct txgbe_l2_tn_filter *node;
5151 struct txgbe_l2_tunnel_conf l2_tn_conf;
5153 TAILQ_FOREACH(node, &l2_tn_info->l2_tn_list, entries) {
5154 l2_tn_conf.l2_tunnel_type = node->key.l2_tn_type;
5155 l2_tn_conf.tunnel_id = node->key.tn_id;
5156 l2_tn_conf.pool = node->pool;
5157 (void)txgbe_dev_l2_tunnel_filter_add(dev, &l2_tn_conf, TRUE);
5161 /* restore rss filter */
5163 txgbe_rss_filter_restore(struct rte_eth_dev *dev)
5165 struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(dev);
5167 if (filter_info->rss_info.conf.queue_num)
5168 txgbe_config_rss_filter(dev,
5169 &filter_info->rss_info, TRUE);
5173 txgbe_filter_restore(struct rte_eth_dev *dev)
5175 txgbe_ntuple_filter_restore(dev);
5176 txgbe_ethertype_filter_restore(dev);
5177 txgbe_syn_filter_restore(dev);
5178 txgbe_fdir_filter_restore(dev);
5179 txgbe_l2_tn_filter_restore(dev);
5180 txgbe_rss_filter_restore(dev);
5186 txgbe_l2_tunnel_conf(struct rte_eth_dev *dev)
5188 struct txgbe_l2_tn_info *l2_tn_info = TXGBE_DEV_L2_TN(dev);
5189 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
5191 if (l2_tn_info->e_tag_en)
5192 (void)txgbe_e_tag_enable(hw);
5194 if (l2_tn_info->e_tag_fwd_en)
5195 (void)txgbe_e_tag_forwarding_en_dis(dev, 1);
5197 (void)txgbe_update_e_tag_eth_type(hw, l2_tn_info->e_tag_ether_type);
5200 /* remove all the n-tuple filters */
5202 txgbe_clear_all_ntuple_filter(struct rte_eth_dev *dev)
5204 struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(dev);
5205 struct txgbe_5tuple_filter *p_5tuple;
5207 while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list)))
5208 txgbe_remove_5tuple_filter(dev, p_5tuple);
5211 /* remove all the ether type filters */
5213 txgbe_clear_all_ethertype_filter(struct rte_eth_dev *dev)
5215 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
5216 struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(dev);
5219 for (i = 0; i < TXGBE_ETF_ID_MAX; i++) {
5220 if (filter_info->ethertype_mask & (1 << i) &&
5221 !filter_info->ethertype_filters[i].conf) {
5222 (void)txgbe_ethertype_filter_remove(filter_info,
5224 wr32(hw, TXGBE_ETFLT(i), 0);
5225 wr32(hw, TXGBE_ETCLS(i), 0);
5231 /* remove the SYN filter */
5233 txgbe_clear_syn_filter(struct rte_eth_dev *dev)
5235 struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
5236 struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(dev);
5238 if (filter_info->syn_info & TXGBE_SYNCLS_ENA) {
5239 filter_info->syn_info = 0;
5241 wr32(hw, TXGBE_SYNCLS, 0);
5246 /* remove all the L2 tunnel filters */
5248 txgbe_clear_all_l2_tn_filter(struct rte_eth_dev *dev)
5250 struct txgbe_l2_tn_info *l2_tn_info = TXGBE_DEV_L2_TN(dev);
5251 struct txgbe_l2_tn_filter *l2_tn_filter;
5252 struct txgbe_l2_tunnel_conf l2_tn_conf;
5255 while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
5256 l2_tn_conf.l2_tunnel_type = l2_tn_filter->key.l2_tn_type;
5257 l2_tn_conf.tunnel_id = l2_tn_filter->key.tn_id;
5258 l2_tn_conf.pool = l2_tn_filter->pool;
5259 ret = txgbe_dev_l2_tunnel_filter_del(dev, &l2_tn_conf);
5267 static const struct eth_dev_ops txgbe_eth_dev_ops = {
5268 .dev_configure = txgbe_dev_configure,
5269 .dev_infos_get = txgbe_dev_info_get,
5270 .dev_start = txgbe_dev_start,
5271 .dev_stop = txgbe_dev_stop,
5272 .dev_set_link_up = txgbe_dev_set_link_up,
5273 .dev_set_link_down = txgbe_dev_set_link_down,
5274 .dev_close = txgbe_dev_close,
5275 .dev_reset = txgbe_dev_reset,
5276 .promiscuous_enable = txgbe_dev_promiscuous_enable,
5277 .promiscuous_disable = txgbe_dev_promiscuous_disable,
5278 .allmulticast_enable = txgbe_dev_allmulticast_enable,
5279 .allmulticast_disable = txgbe_dev_allmulticast_disable,
5280 .link_update = txgbe_dev_link_update,
5281 .stats_get = txgbe_dev_stats_get,
5282 .xstats_get = txgbe_dev_xstats_get,
5283 .xstats_get_by_id = txgbe_dev_xstats_get_by_id,
5284 .stats_reset = txgbe_dev_stats_reset,
5285 .xstats_reset = txgbe_dev_xstats_reset,
5286 .xstats_get_names = txgbe_dev_xstats_get_names,
5287 .xstats_get_names_by_id = txgbe_dev_xstats_get_names_by_id,
5288 .queue_stats_mapping_set = txgbe_dev_queue_stats_mapping_set,
5289 .fw_version_get = txgbe_fw_version_get,
5290 .dev_supported_ptypes_get = txgbe_dev_supported_ptypes_get,
5291 .mtu_set = txgbe_dev_mtu_set,
5292 .vlan_filter_set = txgbe_vlan_filter_set,
5293 .vlan_tpid_set = txgbe_vlan_tpid_set,
5294 .vlan_offload_set = txgbe_vlan_offload_set,
5295 .vlan_strip_queue_set = txgbe_vlan_strip_queue_set,
5296 .rx_queue_start = txgbe_dev_rx_queue_start,
5297 .rx_queue_stop = txgbe_dev_rx_queue_stop,
5298 .tx_queue_start = txgbe_dev_tx_queue_start,
5299 .tx_queue_stop = txgbe_dev_tx_queue_stop,
5300 .rx_queue_setup = txgbe_dev_rx_queue_setup,
5301 .rx_queue_intr_enable = txgbe_dev_rx_queue_intr_enable,
5302 .rx_queue_intr_disable = txgbe_dev_rx_queue_intr_disable,
5303 .rx_queue_release = txgbe_dev_rx_queue_release,
5304 .tx_queue_setup = txgbe_dev_tx_queue_setup,
5305 .tx_queue_release = txgbe_dev_tx_queue_release,
5306 .dev_led_on = txgbe_dev_led_on,
5307 .dev_led_off = txgbe_dev_led_off,
5308 .flow_ctrl_get = txgbe_flow_ctrl_get,
5309 .flow_ctrl_set = txgbe_flow_ctrl_set,
5310 .priority_flow_ctrl_set = txgbe_priority_flow_ctrl_set,
5311 .mac_addr_add = txgbe_add_rar,
5312 .mac_addr_remove = txgbe_remove_rar,
5313 .mac_addr_set = txgbe_set_default_mac_addr,
5314 .uc_hash_table_set = txgbe_uc_hash_table_set,
5315 .uc_all_hash_table_set = txgbe_uc_all_hash_table_set,
5316 .set_queue_rate_limit = txgbe_set_queue_rate_limit,
5317 .reta_update = txgbe_dev_rss_reta_update,
5318 .reta_query = txgbe_dev_rss_reta_query,
5319 .rss_hash_update = txgbe_dev_rss_hash_update,
5320 .rss_hash_conf_get = txgbe_dev_rss_hash_conf_get,
5321 .flow_ops_get = txgbe_dev_flow_ops_get,
5322 .set_mc_addr_list = txgbe_dev_set_mc_addr_list,
5323 .rxq_info_get = txgbe_rxq_info_get,
5324 .txq_info_get = txgbe_txq_info_get,
5325 .timesync_enable = txgbe_timesync_enable,
5326 .timesync_disable = txgbe_timesync_disable,
5327 .timesync_read_rx_timestamp = txgbe_timesync_read_rx_timestamp,
5328 .timesync_read_tx_timestamp = txgbe_timesync_read_tx_timestamp,
5329 .get_reg = txgbe_get_regs,
5330 .get_eeprom_length = txgbe_get_eeprom_length,
5331 .get_eeprom = txgbe_get_eeprom,
5332 .set_eeprom = txgbe_set_eeprom,
5333 .get_module_info = txgbe_get_module_info,
5334 .get_module_eeprom = txgbe_get_module_eeprom,
5335 .get_dcb_info = txgbe_dev_get_dcb_info,
5336 .timesync_adjust_time = txgbe_timesync_adjust_time,
5337 .timesync_read_time = txgbe_timesync_read_time,
5338 .timesync_write_time = txgbe_timesync_write_time,
5339 .udp_tunnel_port_add = txgbe_dev_udp_tunnel_port_add,
5340 .udp_tunnel_port_del = txgbe_dev_udp_tunnel_port_del,
5341 .tm_ops_get = txgbe_tm_ops_get,
5342 .tx_done_cleanup = txgbe_dev_tx_done_cleanup,
5345 RTE_PMD_REGISTER_PCI(net_txgbe, rte_txgbe_pmd);
5346 RTE_PMD_REGISTER_PCI_TABLE(net_txgbe, pci_id_txgbe_map);
5347 RTE_PMD_REGISTER_KMOD_DEP(net_txgbe, "* igb_uio | uio_pci_generic | vfio-pci");
5348 RTE_PMD_REGISTER_PARAM_STRING(net_txgbe,
5349 TXGBE_DEVARG_BP_AUTO "=<0|1>"
5350 TXGBE_DEVARG_KR_POLL "=<0|1>"
5351 TXGBE_DEVARG_KR_PRESENT "=<0|1>"
5352 TXGBE_DEVARG_KX_SGMII "=<0|1>"
5353 TXGBE_DEVARG_FFE_SET "=<0-4>"
5354 TXGBE_DEVARG_FFE_MAIN "=<uint16>"
5355 TXGBE_DEVARG_FFE_PRE "=<uint16>"
5356 TXGBE_DEVARG_FFE_POST "=<uint16>");
5358 RTE_LOG_REGISTER_SUFFIX(txgbe_logtype_init, init, NOTICE);
5359 RTE_LOG_REGISTER_SUFFIX(txgbe_logtype_driver, driver, NOTICE);
5360 RTE_LOG_REGISTER_SUFFIX(txgbe_logtype_bp, bp, NOTICE);
5362 #ifdef RTE_LIBRTE_TXGBE_DEBUG_RX
5363 RTE_LOG_REGISTER_SUFFIX(txgbe_logtype_rx, rx, DEBUG);
5365 #ifdef RTE_LIBRTE_TXGBE_DEBUG_TX
5366 RTE_LOG_REGISTER_SUFFIX(txgbe_logtype_tx, tx, DEBUG);
5369 #ifdef RTE_LIBRTE_TXGBE_DEBUG_TX_FREE
5370 RTE_LOG_REGISTER_SUFFIX(txgbe_logtype_tx_free, tx_free, DEBUG);