drivers/net/txgbe/txgbe_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2015-2020
   3  */
   4
   5 #include <stdio.h>
   6 #include <errno.h>
   7 #include <stdint.h>
   8 #include <string.h>
   9 #include <rte_common.h>
  10 #include <rte_ethdev_pci.h>
  11
  12 #include <rte_interrupts.h>
  13 #include <rte_log.h>
  14 #include <rte_debug.h>
  15 #include <rte_pci.h>
  16 #include <rte_memory.h>
  17 #include <rte_eal.h>
  18 #include <rte_alarm.h>
  19
  20 #include "txgbe_logs.h"
  21 #include "base/txgbe.h"
  22 #include "txgbe_ethdev.h"
  23 #include "txgbe_rxtx.h"
  24 #include "txgbe_regs_group.h"
  25
  26 static const struct reg_info txgbe_regs_general[] = {
  27         {TXGBE_RST, 1, 1, "TXGBE_RST"},
  28         {TXGBE_STAT, 1, 1, "TXGBE_STAT"},
  29         {TXGBE_PORTCTL, 1, 1, "TXGBE_PORTCTL"},
  30         {TXGBE_SDP, 1, 1, "TXGBE_SDP"},
  31         {TXGBE_SDPCTL, 1, 1, "TXGBE_SDPCTL"},
  32         {TXGBE_LEDCTL, 1, 1, "TXGBE_LEDCTL"},
  33         {0, 0, 0, ""}
  34 };
  35
  36 static const struct reg_info txgbe_regs_nvm[] = {
  37         {0, 0, 0, ""}
  38 };
  39
  40 static const struct reg_info txgbe_regs_interrupt[] = {
  41         {0, 0, 0, ""}
  42 };
  43
  44 static const struct reg_info txgbe_regs_fctl_others[] = {
  45         {0, 0, 0, ""}
  46 };
  47
  48 static const struct reg_info txgbe_regs_rxdma[] = {
  49         {0, 0, 0, ""}
  50 };
  51
  52 static const struct reg_info txgbe_regs_rx[] = {
  53         {0, 0, 0, ""}
  54 };
  55
  56 static struct reg_info txgbe_regs_tx[] = {
  57         {0, 0, 0, ""}
  58 };
  59
  60 static const struct reg_info txgbe_regs_wakeup[] = {
  61         {0, 0, 0, ""}
  62 };
  63
  64 static const struct reg_info txgbe_regs_dcb[] = {
  65         {0, 0, 0, ""}
  66 };
  67
  68 static const struct reg_info txgbe_regs_mac[] = {
  69         {0, 0, 0, ""}
  70 };
  71
  72 static const struct reg_info txgbe_regs_diagnostic[] = {
  73         {0, 0, 0, ""},
  74 };
  75
  76 /* PF registers */
  77 static const struct reg_info *txgbe_regs_others[] = {
  78                                 txgbe_regs_general,
  79                                 txgbe_regs_nvm,
  80                                 txgbe_regs_interrupt,
  81                                 txgbe_regs_fctl_others,
  82                                 txgbe_regs_rxdma,
  83                                 txgbe_regs_rx,
  84                                 txgbe_regs_tx,
  85                                 txgbe_regs_wakeup,
  86                                 txgbe_regs_dcb,
  87                                 txgbe_regs_mac,
  88                                 txgbe_regs_diagnostic,
  89                                 NULL};
  90
  91 static int txgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev);
  92 static int txgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev);
  93 static int  txgbe_dev_set_link_up(struct rte_eth_dev *dev);
  94 static int  txgbe_dev_set_link_down(struct rte_eth_dev *dev);
  95 static int txgbe_dev_close(struct rte_eth_dev *dev);
  96 static int txgbe_dev_link_update(struct rte_eth_dev *dev,
  97                                 int wait_to_complete);
  98 static int txgbe_dev_stats_reset(struct rte_eth_dev *dev);
  99 static void txgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
 100 static void txgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev,
 101                                         uint16_t queue);
 102
 103 static void txgbe_dev_link_status_print(struct rte_eth_dev *dev);
 104 static int txgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on);
 105 static int txgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev);
 106 static int txgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
 107 static int txgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
 108 static int txgbe_dev_interrupt_action(struct rte_eth_dev *dev,
 109                                       struct rte_intr_handle *handle);
 110 static void txgbe_dev_interrupt_handler(void *param);
 111 static void txgbe_dev_interrupt_delayed_handler(void *param);
 112 static void txgbe_configure_msix(struct rte_eth_dev *dev);
 113
 114 static int txgbe_filter_restore(struct rte_eth_dev *dev);
 115
 116 #define TXGBE_SET_HWSTRIP(h, q) do {\
 117                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 118                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 119                 (h)->bitmap[idx] |= 1 << bit;\
 120         } while (0)
 121
 122 #define TXGBE_CLEAR_HWSTRIP(h, q) do {\
 123                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 124                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 125                 (h)->bitmap[idx] &= ~(1 << bit);\
 126         } while (0)
 127
 128 #define TXGBE_GET_HWSTRIP(h, q, r) do {\
 129                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 130                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 131                 (r) = (h)->bitmap[idx] >> bit & 1;\
 132         } while (0)
 133
 134 /*
 135  * The set of PCI devices this driver supports
 136  */
 137 static const struct rte_pci_id pci_id_txgbe_map[] = {
 138         { RTE_PCI_DEVICE(PCI_VENDOR_ID_WANGXUN, TXGBE_DEV_ID_RAPTOR_SFP) },
 139         { RTE_PCI_DEVICE(PCI_VENDOR_ID_WANGXUN, TXGBE_DEV_ID_WX1820_SFP) },
 140         { .vendor_id = 0, /* sentinel */ },
 141 };
 142
 143 static const struct rte_eth_desc_lim rx_desc_lim = {
 144         .nb_max = TXGBE_RING_DESC_MAX,
 145         .nb_min = TXGBE_RING_DESC_MIN,
 146         .nb_align = TXGBE_RXD_ALIGN,
 147 };
 148
 149 static const struct rte_eth_desc_lim tx_desc_lim = {
 150         .nb_max = TXGBE_RING_DESC_MAX,
 151         .nb_min = TXGBE_RING_DESC_MIN,
 152         .nb_align = TXGBE_TXD_ALIGN,
 153         .nb_seg_max = TXGBE_TX_MAX_SEG,
 154         .nb_mtu_seg_max = TXGBE_TX_MAX_SEG,
 155 };
 156
 157 static const struct eth_dev_ops txgbe_eth_dev_ops;
 158
 159 #define HW_XSTAT(m) {#m, offsetof(struct txgbe_hw_stats, m)}
 160 #define HW_XSTAT_NAME(m, n) {n, offsetof(struct txgbe_hw_stats, m)}
 161 static const struct rte_txgbe_xstats_name_off rte_txgbe_stats_strings[] = {
 162         /* MNG RxTx */
 163         HW_XSTAT(mng_bmc2host_packets),
 164         HW_XSTAT(mng_host2bmc_packets),
 165         /* Basic RxTx */
 166         HW_XSTAT(rx_packets),
 167         HW_XSTAT(tx_packets),
 168         HW_XSTAT(rx_bytes),
 169         HW_XSTAT(tx_bytes),
 170         HW_XSTAT(rx_total_bytes),
 171         HW_XSTAT(rx_total_packets),
 172         HW_XSTAT(tx_total_packets),
 173         HW_XSTAT(rx_total_missed_packets),
 174         HW_XSTAT(rx_broadcast_packets),
 175         HW_XSTAT(rx_multicast_packets),
 176         HW_XSTAT(rx_management_packets),
 177         HW_XSTAT(tx_management_packets),
 178         HW_XSTAT(rx_management_dropped),
 179
 180         /* Basic Error */
 181         HW_XSTAT(rx_crc_errors),
 182         HW_XSTAT(rx_illegal_byte_errors),
 183         HW_XSTAT(rx_error_bytes),
 184         HW_XSTAT(rx_mac_short_packet_dropped),
 185         HW_XSTAT(rx_length_errors),
 186         HW_XSTAT(rx_undersize_errors),
 187         HW_XSTAT(rx_fragment_errors),
 188         HW_XSTAT(rx_oversize_errors),
 189         HW_XSTAT(rx_jabber_errors),
 190         HW_XSTAT(rx_l3_l4_xsum_error),
 191         HW_XSTAT(mac_local_errors),
 192         HW_XSTAT(mac_remote_errors),
 193
 194         /* Flow Director */
 195         HW_XSTAT(flow_director_added_filters),
 196         HW_XSTAT(flow_director_removed_filters),
 197         HW_XSTAT(flow_director_filter_add_errors),
 198         HW_XSTAT(flow_director_filter_remove_errors),
 199         HW_XSTAT(flow_director_matched_filters),
 200         HW_XSTAT(flow_director_missed_filters),
 201
 202         /* FCoE */
 203         HW_XSTAT(rx_fcoe_crc_errors),
 204         HW_XSTAT(rx_fcoe_mbuf_allocation_errors),
 205         HW_XSTAT(rx_fcoe_dropped),
 206         HW_XSTAT(rx_fcoe_packets),
 207         HW_XSTAT(tx_fcoe_packets),
 208         HW_XSTAT(rx_fcoe_bytes),
 209         HW_XSTAT(tx_fcoe_bytes),
 210         HW_XSTAT(rx_fcoe_no_ddp),
 211         HW_XSTAT(rx_fcoe_no_ddp_ext_buff),
 212
 213         /* MACSEC */
 214         HW_XSTAT(tx_macsec_pkts_untagged),
 215         HW_XSTAT(tx_macsec_pkts_encrypted),
 216         HW_XSTAT(tx_macsec_pkts_protected),
 217         HW_XSTAT(tx_macsec_octets_encrypted),
 218         HW_XSTAT(tx_macsec_octets_protected),
 219         HW_XSTAT(rx_macsec_pkts_untagged),
 220         HW_XSTAT(rx_macsec_pkts_badtag),
 221         HW_XSTAT(rx_macsec_pkts_nosci),
 222         HW_XSTAT(rx_macsec_pkts_unknownsci),
 223         HW_XSTAT(rx_macsec_octets_decrypted),
 224         HW_XSTAT(rx_macsec_octets_validated),
 225         HW_XSTAT(rx_macsec_sc_pkts_unchecked),
 226         HW_XSTAT(rx_macsec_sc_pkts_delayed),
 227         HW_XSTAT(rx_macsec_sc_pkts_late),
 228         HW_XSTAT(rx_macsec_sa_pkts_ok),
 229         HW_XSTAT(rx_macsec_sa_pkts_invalid),
 230         HW_XSTAT(rx_macsec_sa_pkts_notvalid),
 231         HW_XSTAT(rx_macsec_sa_pkts_unusedsa),
 232         HW_XSTAT(rx_macsec_sa_pkts_notusingsa),
 233
 234         /* MAC RxTx */
 235         HW_XSTAT(rx_size_64_packets),
 236         HW_XSTAT(rx_size_65_to_127_packets),
 237         HW_XSTAT(rx_size_128_to_255_packets),
 238         HW_XSTAT(rx_size_256_to_511_packets),
 239         HW_XSTAT(rx_size_512_to_1023_packets),
 240         HW_XSTAT(rx_size_1024_to_max_packets),
 241         HW_XSTAT(tx_size_64_packets),
 242         HW_XSTAT(tx_size_65_to_127_packets),
 243         HW_XSTAT(tx_size_128_to_255_packets),
 244         HW_XSTAT(tx_size_256_to_511_packets),
 245         HW_XSTAT(tx_size_512_to_1023_packets),
 246         HW_XSTAT(tx_size_1024_to_max_packets),
 247
 248         /* Flow Control */
 249         HW_XSTAT(tx_xon_packets),
 250         HW_XSTAT(rx_xon_packets),
 251         HW_XSTAT(tx_xoff_packets),
 252         HW_XSTAT(rx_xoff_packets),
 253
 254         HW_XSTAT_NAME(tx_xon_packets, "tx_flow_control_xon_packets"),
 255         HW_XSTAT_NAME(rx_xon_packets, "rx_flow_control_xon_packets"),
 256         HW_XSTAT_NAME(tx_xoff_packets, "tx_flow_control_xoff_packets"),
 257         HW_XSTAT_NAME(rx_xoff_packets, "rx_flow_control_xoff_packets"),
 258 };
 259
 260 #define TXGBE_NB_HW_STATS (sizeof(rte_txgbe_stats_strings) / \
 261                            sizeof(rte_txgbe_stats_strings[0]))
 262
 263 /* Per-priority statistics */
 264 #define UP_XSTAT(m) {#m, offsetof(struct txgbe_hw_stats, up[0].m)}
 265 static const struct rte_txgbe_xstats_name_off rte_txgbe_up_strings[] = {
 266         UP_XSTAT(rx_up_packets),
 267         UP_XSTAT(tx_up_packets),
 268         UP_XSTAT(rx_up_bytes),
 269         UP_XSTAT(tx_up_bytes),
 270         UP_XSTAT(rx_up_drop_packets),
 271
 272         UP_XSTAT(tx_up_xon_packets),
 273         UP_XSTAT(rx_up_xon_packets),
 274         UP_XSTAT(tx_up_xoff_packets),
 275         UP_XSTAT(rx_up_xoff_packets),
 276         UP_XSTAT(rx_up_dropped),
 277         UP_XSTAT(rx_up_mbuf_alloc_errors),
 278         UP_XSTAT(tx_up_xon2off_packets),
 279 };
 280
 281 #define TXGBE_NB_UP_STATS (sizeof(rte_txgbe_up_strings) / \
 282                            sizeof(rte_txgbe_up_strings[0]))
 283
 284 /* Per-queue statistics */
 285 #define QP_XSTAT(m) {#m, offsetof(struct txgbe_hw_stats, qp[0].m)}
 286 static const struct rte_txgbe_xstats_name_off rte_txgbe_qp_strings[] = {
 287         QP_XSTAT(rx_qp_packets),
 288         QP_XSTAT(tx_qp_packets),
 289         QP_XSTAT(rx_qp_bytes),
 290         QP_XSTAT(tx_qp_bytes),
 291         QP_XSTAT(rx_qp_mc_packets),
 292 };
 293
 294 #define TXGBE_NB_QP_STATS (sizeof(rte_txgbe_qp_strings) / \
 295                            sizeof(rte_txgbe_qp_strings[0]))
 296
 297 static inline int
 298 txgbe_is_sfp(struct txgbe_hw *hw)
 299 {
 300         switch (hw->phy.type) {
 301         case txgbe_phy_sfp_avago:
 302         case txgbe_phy_sfp_ftl:
 303         case txgbe_phy_sfp_intel:
 304         case txgbe_phy_sfp_unknown:
 305         case txgbe_phy_sfp_tyco_passive:
 306         case txgbe_phy_sfp_unknown_passive:
 307                 return 1;
 308         default:
 309                 return 0;
 310         }
 311 }
 312
 313 static inline int32_t
 314 txgbe_pf_reset_hw(struct txgbe_hw *hw)
 315 {
 316         uint32_t ctrl_ext;
 317         int32_t status;
 318
 319         status = hw->mac.reset_hw(hw);
 320
 321         ctrl_ext = rd32(hw, TXGBE_PORTCTL);
 322         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 323         ctrl_ext |= TXGBE_PORTCTL_RSTDONE;
 324         wr32(hw, TXGBE_PORTCTL, ctrl_ext);
 325         txgbe_flush(hw);
 326
 327         if (status == TXGBE_ERR_SFP_NOT_PRESENT)
 328                 status = 0;
 329         return status;
 330 }
 331
 332 static inline void
 333 txgbe_enable_intr(struct rte_eth_dev *dev)
 334 {
 335         struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);
 336         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
 337
 338         wr32(hw, TXGBE_IENMISC, intr->mask_misc);
 339         wr32(hw, TXGBE_IMC(0), TXGBE_IMC_MASK);
 340         wr32(hw, TXGBE_IMC(1), TXGBE_IMC_MASK);
 341         txgbe_flush(hw);
 342 }
 343
 344 static void
 345 txgbe_disable_intr(struct txgbe_hw *hw)
 346 {
 347         PMD_INIT_FUNC_TRACE();
 348
 349         wr32(hw, TXGBE_IENMISC, ~BIT_MASK32);
 350         wr32(hw, TXGBE_IMS(0), TXGBE_IMC_MASK);
 351         wr32(hw, TXGBE_IMS(1), TXGBE_IMC_MASK);
 352         txgbe_flush(hw);
 353 }
 354
 355 static int
 356 txgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 357                                   uint16_t queue_id,
 358                                   uint8_t stat_idx,
 359                                   uint8_t is_rx)
 360 {
 361         struct txgbe_hw *hw = TXGBE_DEV_HW(eth_dev);
 362         struct txgbe_stat_mappings *stat_mappings =
 363                 TXGBE_DEV_STAT_MAPPINGS(eth_dev);
 364         uint32_t qsmr_mask = 0;
 365         uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
 366         uint32_t q_map;
 367         uint8_t n, offset;
 368
 369         if (hw->mac.type != txgbe_mac_raptor)
 370                 return -ENOSYS;
 371
 372         if (stat_idx & !QMAP_FIELD_RESERVED_BITS_MASK)
 373                 return -EIO;
 374
 375         PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d",
 376                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 377                      queue_id, stat_idx);
 378
 379         n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
 380         if (n >= TXGBE_NB_STAT_MAPPING) {
 381                 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
 382                 return -EIO;
 383         }
 384         offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
 385
 386         /* Now clear any previous stat_idx set */
 387         clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 388         if (!is_rx)
 389                 stat_mappings->tqsm[n] &= ~clearing_mask;
 390         else
 391                 stat_mappings->rqsm[n] &= ~clearing_mask;
 392
 393         q_map = (uint32_t)stat_idx;
 394         q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
 395         qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 396         if (!is_rx)
 397                 stat_mappings->tqsm[n] |= qsmr_mask;
 398         else
 399                 stat_mappings->rqsm[n] |= qsmr_mask;
 400
 401         PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d",
 402                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 403                      queue_id, stat_idx);
 404         PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
 405                      is_rx ? stat_mappings->rqsm[n] : stat_mappings->tqsm[n]);
 406         return 0;
 407 }
 408
 409 static void
 410 txgbe_dcb_init(struct txgbe_hw *hw, struct txgbe_dcb_config *dcb_config)
 411 {
 412         int i;
 413         u8 bwgp;
 414         struct txgbe_dcb_tc_config *tc;
 415
 416         UNREFERENCED_PARAMETER(hw);
 417
 418         dcb_config->num_tcs.pg_tcs = TXGBE_DCB_TC_MAX;
 419         dcb_config->num_tcs.pfc_tcs = TXGBE_DCB_TC_MAX;
 420         bwgp = (u8)(100 / TXGBE_DCB_TC_MAX);
 421         for (i = 0; i < TXGBE_DCB_TC_MAX; i++) {
 422                 tc = &dcb_config->tc_config[i];
 423                 tc->path[TXGBE_DCB_TX_CONFIG].bwg_id = i;
 424                 tc->path[TXGBE_DCB_TX_CONFIG].bwg_percent = bwgp + (i & 1);
 425                 tc->path[TXGBE_DCB_RX_CONFIG].bwg_id = i;
 426                 tc->path[TXGBE_DCB_RX_CONFIG].bwg_percent = bwgp + (i & 1);
 427                 tc->pfc = txgbe_dcb_pfc_disabled;
 428         }
 429
 430         /* Initialize default user to priority mapping, UPx->TC0 */
 431         tc = &dcb_config->tc_config[0];
 432         tc->path[TXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
 433         tc->path[TXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
 434         for (i = 0; i < TXGBE_DCB_BWG_MAX; i++) {
 435                 dcb_config->bw_percentage[i][TXGBE_DCB_TX_CONFIG] = 100;
 436                 dcb_config->bw_percentage[i][TXGBE_DCB_RX_CONFIG] = 100;
 437         }
 438         dcb_config->rx_pba_cfg = txgbe_dcb_pba_equal;
 439         dcb_config->pfc_mode_enable = false;
 440         dcb_config->vt_mode = true;
 441         dcb_config->round_robin_enable = false;
 442         /* support all DCB capabilities */
 443         dcb_config->support.capabilities = 0xFF;
 444 }
 445
 446 /*
 447  * Ensure that all locks are released before first NVM or PHY access
 448  */
 449 static void
 450 txgbe_swfw_lock_reset(struct txgbe_hw *hw)
 451 {
 452         uint16_t mask;
 453
 454         /*
 455          * These ones are more tricky since they are common to all ports; but
 456          * swfw_sync retries last long enough (1s) to be almost sure that if
 457          * lock can not be taken it is due to an improper lock of the
 458          * semaphore.
 459          */
 460         mask = TXGBE_MNGSEM_SWPHY |
 461                TXGBE_MNGSEM_SWMBX |
 462                TXGBE_MNGSEM_SWFLASH;
 463         if (hw->mac.acquire_swfw_sync(hw, mask) < 0)
 464                 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
 465
 466         hw->mac.release_swfw_sync(hw, mask);
 467 }
 468
 469 static int
 470 eth_txgbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params __rte_unused)
 471 {
 472         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
 473         struct txgbe_hw *hw = TXGBE_DEV_HW(eth_dev);
 474         struct txgbe_vfta *shadow_vfta = TXGBE_DEV_VFTA(eth_dev);
 475         struct txgbe_hwstrip *hwstrip = TXGBE_DEV_HWSTRIP(eth_dev);
 476         struct txgbe_dcb_config *dcb_config = TXGBE_DEV_DCB_CONFIG(eth_dev);
 477         struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(eth_dev);
 478         struct txgbe_bw_conf *bw_conf = TXGBE_DEV_BW_CONF(eth_dev);
 479         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 480         const struct rte_memzone *mz;
 481         uint32_t ctrl_ext;
 482         uint16_t csum;
 483         int err, i, ret;
 484
 485         PMD_INIT_FUNC_TRACE();
 486
 487         eth_dev->dev_ops = &txgbe_eth_dev_ops;
 488         eth_dev->rx_queue_count       = txgbe_dev_rx_queue_count;
 489         eth_dev->rx_descriptor_status = txgbe_dev_rx_descriptor_status;
 490         eth_dev->tx_descriptor_status = txgbe_dev_tx_descriptor_status;
 491         eth_dev->rx_pkt_burst = &txgbe_recv_pkts;
 492         eth_dev->tx_pkt_burst = &txgbe_xmit_pkts;
 493         eth_dev->tx_pkt_prepare = &txgbe_prep_pkts;
 494
 495         /*
 496          * For secondary processes, we don't initialise any further as primary
 497          * has already done this work. Only check we don't need a different
 498          * RX and TX function.
 499          */
 500         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
 501                 struct txgbe_tx_queue *txq;
 502                 /* TX queue function in primary, set by last queue initialized
 503                  * Tx queue may not initialized by primary process
 504                  */
 505                 if (eth_dev->data->tx_queues) {
 506                         uint16_t nb_tx_queues = eth_dev->data->nb_tx_queues;
 507                         txq = eth_dev->data->tx_queues[nb_tx_queues - 1];
 508                         txgbe_set_tx_function(eth_dev, txq);
 509                 } else {
 510                         /* Use default TX function if we get here */
 511                         PMD_INIT_LOG(NOTICE, "No TX queues configured yet. "
 512                                      "Using default TX function.");
 513                 }
 514
 515                 txgbe_set_rx_function(eth_dev);
 516
 517                 return 0;
 518         }
 519
 520         rte_eth_copy_pci_info(eth_dev, pci_dev);
 521
 522         /* Vendor and Device ID need to be set before init of shared code */
 523         hw->device_id = pci_dev->id.device_id;
 524         hw->vendor_id = pci_dev->id.vendor_id;
 525         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
 526         hw->allow_unsupported_sfp = 1;
 527
 528         /* Reserve memory for interrupt status block */
 529         mz = rte_eth_dma_zone_reserve(eth_dev, "txgbe_driver", -1,
 530                 16, TXGBE_ALIGN, SOCKET_ID_ANY);
 531         if (mz == NULL)
 532                 return -ENOMEM;
 533
 534         hw->isb_dma = TMZ_PADDR(mz);
 535         hw->isb_mem = TMZ_VADDR(mz);
 536
 537         /* Initialize the shared code (base driver) */
 538         err = txgbe_init_shared_code(hw);
 539         if (err != 0) {
 540                 PMD_INIT_LOG(ERR, "Shared code init failed: %d", err);
 541                 return -EIO;
 542         }
 543
 544         /* Unlock any pending hardware semaphore */
 545         txgbe_swfw_lock_reset(hw);
 546
 547         /* Initialize DCB configuration*/
 548         memset(dcb_config, 0, sizeof(struct txgbe_dcb_config));
 549         txgbe_dcb_init(hw, dcb_config);
 550
 551         /* Get Hardware Flow Control setting */
 552         hw->fc.requested_mode = txgbe_fc_full;
 553         hw->fc.current_mode = txgbe_fc_full;
 554         hw->fc.pause_time = TXGBE_FC_PAUSE_TIME;
 555         for (i = 0; i < TXGBE_DCB_TC_MAX; i++) {
 556                 hw->fc.low_water[i] = TXGBE_FC_XON_LOTH;
 557                 hw->fc.high_water[i] = TXGBE_FC_XOFF_HITH;
 558         }
 559         hw->fc.send_xon = 1;
 560
 561         err = hw->rom.init_params(hw);
 562         if (err != 0) {
 563                 PMD_INIT_LOG(ERR, "The EEPROM init failed: %d", err);
 564                 return -EIO;
 565         }
 566
 567         /* Make sure we have a good EEPROM before we read from it */
 568         err = hw->rom.validate_checksum(hw, &csum);
 569         if (err != 0) {
 570                 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", err);
 571                 return -EIO;
 572         }
 573
 574         err = hw->mac.init_hw(hw);
 575
 576         /*
 577          * Devices with copper phys will fail to initialise if txgbe_init_hw()
 578          * is called too soon after the kernel driver unbinding/binding occurs.
 579          * The failure occurs in txgbe_identify_phy() for all devices,
 580          * but for non-copper devies, txgbe_identify_sfp_module() is
 581          * also called. See txgbe_identify_phy(). The reason for the
 582          * failure is not known, and only occuts when virtualisation features
 583          * are disabled in the bios. A delay of 200ms  was found to be enough by
 584          * trial-and-error, and is doubled to be safe.
 585          */
 586         if (err && hw->phy.media_type == txgbe_media_type_copper) {
 587                 rte_delay_ms(200);
 588                 err = hw->mac.init_hw(hw);
 589         }
 590
 591         if (err == TXGBE_ERR_SFP_NOT_PRESENT)
 592                 err = 0;
 593
 594         if (err == TXGBE_ERR_EEPROM_VERSION) {
 595                 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
 596                              "LOM.  Please be aware there may be issues associated "
 597                              "with your hardware.");
 598                 PMD_INIT_LOG(ERR, "If you are experiencing problems "
 599                              "please contact your hardware representative "
 600                              "who provided you with this hardware.");
 601         } else if (err == TXGBE_ERR_SFP_NOT_SUPPORTED) {
 602                 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
 603         }
 604         if (err) {
 605                 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", err);
 606                 return -EIO;
 607         }
 608
 609         /* Reset the hw statistics */
 610         txgbe_dev_stats_reset(eth_dev);
 611
 612         /* disable interrupt */
 613         txgbe_disable_intr(hw);
 614
 615         /* Allocate memory for storing MAC addresses */
 616         eth_dev->data->mac_addrs = rte_zmalloc("txgbe", RTE_ETHER_ADDR_LEN *
 617                                                hw->mac.num_rar_entries, 0);
 618         if (eth_dev->data->mac_addrs == NULL) {
 619                 PMD_INIT_LOG(ERR,
 620                              "Failed to allocate %u bytes needed to store "
 621                              "MAC addresses",
 622                              RTE_ETHER_ADDR_LEN * hw->mac.num_rar_entries);
 623                 return -ENOMEM;
 624         }
 625
 626         /* Copy the permanent MAC address */
 627         rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.perm_addr,
 628                         &eth_dev->data->mac_addrs[0]);
 629
 630         /* Allocate memory for storing hash filter MAC addresses */
 631         eth_dev->data->hash_mac_addrs = rte_zmalloc("txgbe",
 632                         RTE_ETHER_ADDR_LEN * TXGBE_VMDQ_NUM_UC_MAC, 0);
 633         if (eth_dev->data->hash_mac_addrs == NULL) {
 634                 PMD_INIT_LOG(ERR,
 635                              "Failed to allocate %d bytes needed to store MAC addresses",
 636                              RTE_ETHER_ADDR_LEN * TXGBE_VMDQ_NUM_UC_MAC);
 637                 return -ENOMEM;
 638         }
 639
 640         /* initialize the vfta */
 641         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
 642
 643         /* initialize the hw strip bitmap*/
 644         memset(hwstrip, 0, sizeof(*hwstrip));
 645
 646         /* initialize PF if max_vfs not zero */
 647         ret = txgbe_pf_host_init(eth_dev);
 648         if (ret) {
 649                 rte_free(eth_dev->data->mac_addrs);
 650                 eth_dev->data->mac_addrs = NULL;
 651                 rte_free(eth_dev->data->hash_mac_addrs);
 652                 eth_dev->data->hash_mac_addrs = NULL;
 653                 return ret;
 654         }
 655
 656         ctrl_ext = rd32(hw, TXGBE_PORTCTL);
 657         /* let hardware know driver is loaded */
 658         ctrl_ext |= TXGBE_PORTCTL_DRVLOAD;
 659         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 660         ctrl_ext |= TXGBE_PORTCTL_RSTDONE;
 661         wr32(hw, TXGBE_PORTCTL, ctrl_ext);
 662         txgbe_flush(hw);
 663
 664         if (txgbe_is_sfp(hw) && hw->phy.sfp_type != txgbe_sfp_type_not_present)
 665                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
 666                              (int)hw->mac.type, (int)hw->phy.type,
 667                              (int)hw->phy.sfp_type);
 668         else
 669                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
 670                              (int)hw->mac.type, (int)hw->phy.type);
 671
 672         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
 673                      eth_dev->data->port_id, pci_dev->id.vendor_id,
 674                      pci_dev->id.device_id);
 675
 676         rte_intr_callback_register(intr_handle,
 677                                    txgbe_dev_interrupt_handler, eth_dev);
 678
 679         /* enable uio/vfio intr/eventfd mapping */
 680         rte_intr_enable(intr_handle);
 681
 682         /* enable support intr */
 683         txgbe_enable_intr(eth_dev);
 684
 685         /* initialize filter info */
 686         memset(filter_info, 0,
 687                sizeof(struct txgbe_filter_info));
 688
 689         /* initialize 5tuple filter list */
 690         TAILQ_INIT(&filter_info->fivetuple_list);
 691
 692         /* initialize l2 tunnel filter list & hash */
 693         txgbe_l2_tn_filter_init(eth_dev);
 694
 695         /* initialize bandwidth configuration info */
 696         memset(bw_conf, 0, sizeof(struct txgbe_bw_conf));
 697
 698         return 0;
 699 }
 700
 701 static int
 702 eth_txgbe_dev_uninit(struct rte_eth_dev *eth_dev)
 703 {
 704         PMD_INIT_FUNC_TRACE();
 705
 706         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 707                 return 0;
 708
 709         txgbe_dev_close(eth_dev);
 710
 711         return 0;
 712 }
 713
 714 static int txgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev)
 715 {
 716         struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(eth_dev);
 717         struct txgbe_5tuple_filter *p_5tuple;
 718
 719         while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) {
 720                 TAILQ_REMOVE(&filter_info->fivetuple_list,
 721                              p_5tuple,
 722                              entries);
 723                 rte_free(p_5tuple);
 724         }
 725         memset(filter_info->fivetuple_mask, 0,
 726                sizeof(uint32_t) * TXGBE_5TUPLE_ARRAY_SIZE);
 727
 728         return 0;
 729 }
 730
 731 static int txgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev)
 732 {
 733         struct txgbe_l2_tn_info *l2_tn_info = TXGBE_DEV_L2_TN(eth_dev);
 734         struct txgbe_l2_tn_filter *l2_tn_filter;
 735
 736         if (l2_tn_info->hash_map)
 737                 rte_free(l2_tn_info->hash_map);
 738         if (l2_tn_info->hash_handle)
 739                 rte_hash_free(l2_tn_info->hash_handle);
 740
 741         while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
 742                 TAILQ_REMOVE(&l2_tn_info->l2_tn_list,
 743                              l2_tn_filter,
 744                              entries);
 745                 rte_free(l2_tn_filter);
 746         }
 747
 748         return 0;
 749 }
 750
 751 static int txgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev)
 752 {
 753         struct txgbe_l2_tn_info *l2_tn_info = TXGBE_DEV_L2_TN(eth_dev);
 754         char l2_tn_hash_name[RTE_HASH_NAMESIZE];
 755         struct rte_hash_parameters l2_tn_hash_params = {
 756                 .name = l2_tn_hash_name,
 757                 .entries = TXGBE_MAX_L2_TN_FILTER_NUM,
 758                 .key_len = sizeof(struct txgbe_l2_tn_key),
 759                 .hash_func = rte_hash_crc,
 760                 .hash_func_init_val = 0,
 761                 .socket_id = rte_socket_id(),
 762         };
 763
 764         TAILQ_INIT(&l2_tn_info->l2_tn_list);
 765         snprintf(l2_tn_hash_name, RTE_HASH_NAMESIZE,
 766                  "l2_tn_%s", TDEV_NAME(eth_dev));
 767         l2_tn_info->hash_handle = rte_hash_create(&l2_tn_hash_params);
 768         if (!l2_tn_info->hash_handle) {
 769                 PMD_INIT_LOG(ERR, "Failed to create L2 TN hash table!");
 770                 return -EINVAL;
 771         }
 772         l2_tn_info->hash_map = rte_zmalloc("txgbe",
 773                                    sizeof(struct txgbe_l2_tn_filter *) *
 774                                    TXGBE_MAX_L2_TN_FILTER_NUM,
 775                                    0);
 776         if (!l2_tn_info->hash_map) {
 777                 PMD_INIT_LOG(ERR,
 778                         "Failed to allocate memory for L2 TN hash map!");
 779                 return -ENOMEM;
 780         }
 781         l2_tn_info->e_tag_en = FALSE;
 782         l2_tn_info->e_tag_fwd_en = FALSE;
 783         l2_tn_info->e_tag_ether_type = RTE_ETHER_TYPE_ETAG;
 784
 785         return 0;
 786 }
 787
 788 static int
 789 eth_txgbe_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
 790                 struct rte_pci_device *pci_dev)
 791 {
 792         struct rte_eth_dev *pf_ethdev;
 793         struct rte_eth_devargs eth_da;
 794         int retval;
 795
 796         if (pci_dev->device.devargs) {
 797                 retval = rte_eth_devargs_parse(pci_dev->device.devargs->args,
 798                                 &eth_da);
 799                 if (retval)
 800                         return retval;
 801         } else {
 802                 memset(&eth_da, 0, sizeof(eth_da));
 803         }
 804
 805         retval = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
 806                         sizeof(struct txgbe_adapter),
 807                         eth_dev_pci_specific_init, pci_dev,
 808                         eth_txgbe_dev_init, NULL);
 809
 810         if (retval || eth_da.nb_representor_ports < 1)
 811                 return retval;
 812
 813         pf_ethdev = rte_eth_dev_allocated(pci_dev->device.name);
 814         if (pf_ethdev == NULL)
 815                 return -ENODEV;
 816
 817         return 0;
 818 }
 819
 820 static int eth_txgbe_pci_remove(struct rte_pci_device *pci_dev)
 821 {
 822         struct rte_eth_dev *ethdev;
 823
 824         ethdev = rte_eth_dev_allocated(pci_dev->device.name);
 825         if (!ethdev)
 826                 return -ENODEV;
 827
 828         return rte_eth_dev_destroy(ethdev, eth_txgbe_dev_uninit);
 829 }
 830
 831 static struct rte_pci_driver rte_txgbe_pmd = {
 832         .id_table = pci_id_txgbe_map,
 833         .drv_flags = RTE_PCI_DRV_NEED_MAPPING |
 834                      RTE_PCI_DRV_INTR_LSC,
 835         .probe = eth_txgbe_pci_probe,
 836         .remove = eth_txgbe_pci_remove,
 837 };
 838
 839 static int
 840 txgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
 841 {
 842         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
 843         struct txgbe_vfta *shadow_vfta = TXGBE_DEV_VFTA(dev);
 844         uint32_t vfta;
 845         uint32_t vid_idx;
 846         uint32_t vid_bit;
 847
 848         vid_idx = (uint32_t)((vlan_id >> 5) & 0x7F);
 849         vid_bit = (uint32_t)(1 << (vlan_id & 0x1F));
 850         vfta = rd32(hw, TXGBE_VLANTBL(vid_idx));
 851         if (on)
 852                 vfta |= vid_bit;
 853         else
 854                 vfta &= ~vid_bit;
 855         wr32(hw, TXGBE_VLANTBL(vid_idx), vfta);
 856
 857         /* update local VFTA copy */
 858         shadow_vfta->vfta[vid_idx] = vfta;
 859
 860         return 0;
 861 }
 862
 863 static void
 864 txgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
 865 {
 866         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
 867         struct txgbe_rx_queue *rxq;
 868         bool restart;
 869         uint32_t rxcfg, rxbal, rxbah;
 870
 871         if (on)
 872                 txgbe_vlan_hw_strip_enable(dev, queue);
 873         else
 874                 txgbe_vlan_hw_strip_disable(dev, queue);
 875
 876         rxq = dev->data->rx_queues[queue];
 877         rxbal = rd32(hw, TXGBE_RXBAL(rxq->reg_idx));
 878         rxbah = rd32(hw, TXGBE_RXBAH(rxq->reg_idx));
 879         rxcfg = rd32(hw, TXGBE_RXCFG(rxq->reg_idx));
 880         if (rxq->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) {
 881                 restart = (rxcfg & TXGBE_RXCFG_ENA) &&
 882                         !(rxcfg & TXGBE_RXCFG_VLAN);
 883                 rxcfg |= TXGBE_RXCFG_VLAN;
 884         } else {
 885                 restart = (rxcfg & TXGBE_RXCFG_ENA) &&
 886                         (rxcfg & TXGBE_RXCFG_VLAN);
 887                 rxcfg &= ~TXGBE_RXCFG_VLAN;
 888         }
 889         rxcfg &= ~TXGBE_RXCFG_ENA;
 890
 891         if (restart) {
 892                 /* set vlan strip for ring */
 893                 txgbe_dev_rx_queue_stop(dev, queue);
 894                 wr32(hw, TXGBE_RXBAL(rxq->reg_idx), rxbal);
 895                 wr32(hw, TXGBE_RXBAH(rxq->reg_idx), rxbah);
 896                 wr32(hw, TXGBE_RXCFG(rxq->reg_idx), rxcfg);
 897                 txgbe_dev_rx_queue_start(dev, queue);
 898         }
 899 }
 900
 901 static int
 902 txgbe_vlan_tpid_set(struct rte_eth_dev *dev,
 903                     enum rte_vlan_type vlan_type,
 904                     uint16_t tpid)
 905 {
 906         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
 907         int ret = 0;
 908         uint32_t portctrl, vlan_ext, qinq;
 909
 910         portctrl = rd32(hw, TXGBE_PORTCTL);
 911
 912         vlan_ext = (portctrl & TXGBE_PORTCTL_VLANEXT);
 913         qinq = vlan_ext && (portctrl & TXGBE_PORTCTL_QINQ);
 914         switch (vlan_type) {
 915         case ETH_VLAN_TYPE_INNER:
 916                 if (vlan_ext) {
 917                         wr32m(hw, TXGBE_VLANCTL,
 918                                 TXGBE_VLANCTL_TPID_MASK,
 919                                 TXGBE_VLANCTL_TPID(tpid));
 920                         wr32m(hw, TXGBE_DMATXCTRL,
 921                                 TXGBE_DMATXCTRL_TPID_MASK,
 922                                 TXGBE_DMATXCTRL_TPID(tpid));
 923                 } else {
 924                         ret = -ENOTSUP;
 925                         PMD_DRV_LOG(ERR, "Inner type is not supported"
 926                                     " by single VLAN");
 927                 }
 928
 929                 if (qinq) {
 930                         wr32m(hw, TXGBE_TAGTPID(0),
 931                                 TXGBE_TAGTPID_LSB_MASK,
 932                                 TXGBE_TAGTPID_LSB(tpid));
 933                 }
 934                 break;
 935         case ETH_VLAN_TYPE_OUTER:
 936                 if (vlan_ext) {
 937                         /* Only the high 16-bits is valid */
 938                         wr32m(hw, TXGBE_EXTAG,
 939                                 TXGBE_EXTAG_VLAN_MASK,
 940                                 TXGBE_EXTAG_VLAN(tpid));
 941                 } else {
 942                         wr32m(hw, TXGBE_VLANCTL,
 943                                 TXGBE_VLANCTL_TPID_MASK,
 944                                 TXGBE_VLANCTL_TPID(tpid));
 945                         wr32m(hw, TXGBE_DMATXCTRL,
 946                                 TXGBE_DMATXCTRL_TPID_MASK,
 947                                 TXGBE_DMATXCTRL_TPID(tpid));
 948                 }
 949
 950                 if (qinq) {
 951                         wr32m(hw, TXGBE_TAGTPID(0),
 952                                 TXGBE_TAGTPID_MSB_MASK,
 953                                 TXGBE_TAGTPID_MSB(tpid));
 954                 }
 955                 break;
 956         default:
 957                 PMD_DRV_LOG(ERR, "Unsupported VLAN type %d", vlan_type);
 958                 return -EINVAL;
 959         }
 960
 961         return ret;
 962 }
 963
 964 void
 965 txgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
 966 {
 967         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
 968         uint32_t vlnctrl;
 969
 970         PMD_INIT_FUNC_TRACE();
 971
 972         /* Filter Table Disable */
 973         vlnctrl = rd32(hw, TXGBE_VLANCTL);
 974         vlnctrl &= ~TXGBE_VLANCTL_VFE;
 975         wr32(hw, TXGBE_VLANCTL, vlnctrl);
 976 }
 977
 978 void
 979 txgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
 980 {
 981         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
 982         struct txgbe_vfta *shadow_vfta = TXGBE_DEV_VFTA(dev);
 983         uint32_t vlnctrl;
 984         uint16_t i;
 985
 986         PMD_INIT_FUNC_TRACE();
 987
 988         /* Filter Table Enable */
 989         vlnctrl = rd32(hw, TXGBE_VLANCTL);
 990         vlnctrl &= ~TXGBE_VLANCTL_CFIENA;
 991         vlnctrl |= TXGBE_VLANCTL_VFE;
 992         wr32(hw, TXGBE_VLANCTL, vlnctrl);
 993
 994         /* write whatever is in local vfta copy */
 995         for (i = 0; i < TXGBE_VFTA_SIZE; i++)
 996                 wr32(hw, TXGBE_VLANTBL(i), shadow_vfta->vfta[i]);
 997 }
 998
 999 void
1000 txgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1001 {
1002         struct txgbe_hwstrip *hwstrip = TXGBE_DEV_HWSTRIP(dev);
1003         struct txgbe_rx_queue *rxq;
1004
1005         if (queue >= TXGBE_MAX_RX_QUEUE_NUM)
1006                 return;
1007
1008         if (on)
1009                 TXGBE_SET_HWSTRIP(hwstrip, queue);
1010         else
1011                 TXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1012
1013         if (queue >= dev->data->nb_rx_queues)
1014                 return;
1015
1016         rxq = dev->data->rx_queues[queue];
1017
1018         if (on) {
1019                 rxq->vlan_flags = PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
1020                 rxq->offloads |= DEV_RX_OFFLOAD_VLAN_STRIP;
1021         } else {
1022                 rxq->vlan_flags = PKT_RX_VLAN;
1023                 rxq->offloads &= ~DEV_RX_OFFLOAD_VLAN_STRIP;
1024         }
1025 }
1026
1027 static void
1028 txgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
1029 {
1030         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
1031         uint32_t ctrl;
1032
1033         PMD_INIT_FUNC_TRACE();
1034
1035         ctrl = rd32(hw, TXGBE_RXCFG(queue));
1036         ctrl &= ~TXGBE_RXCFG_VLAN;
1037         wr32(hw, TXGBE_RXCFG(queue), ctrl);
1038
1039         /* record those setting for HW strip per queue */
1040         txgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
1041 }
1042
1043 static void
1044 txgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
1045 {
1046         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
1047         uint32_t ctrl;
1048
1049         PMD_INIT_FUNC_TRACE();
1050
1051         ctrl = rd32(hw, TXGBE_RXCFG(queue));
1052         ctrl |= TXGBE_RXCFG_VLAN;
1053         wr32(hw, TXGBE_RXCFG(queue), ctrl);
1054
1055         /* record those setting for HW strip per queue */
1056         txgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
1057 }
1058
1059 static void
1060 txgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
1061 {
1062         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
1063         uint32_t ctrl;
1064
1065         PMD_INIT_FUNC_TRACE();
1066
1067         ctrl = rd32(hw, TXGBE_PORTCTL);
1068         ctrl &= ~TXGBE_PORTCTL_VLANEXT;
1069         ctrl &= ~TXGBE_PORTCTL_QINQ;
1070         wr32(hw, TXGBE_PORTCTL, ctrl);
1071 }
1072
1073 static void
1074 txgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
1075 {
1076         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
1077         struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
1078         struct rte_eth_txmode *txmode = &dev->data->dev_conf.txmode;
1079         uint32_t ctrl;
1080
1081         PMD_INIT_FUNC_TRACE();
1082
1083         ctrl  = rd32(hw, TXGBE_PORTCTL);
1084         ctrl |= TXGBE_PORTCTL_VLANEXT;
1085         if (rxmode->offloads & DEV_RX_OFFLOAD_QINQ_STRIP ||
1086             txmode->offloads & DEV_TX_OFFLOAD_QINQ_INSERT)
1087                 ctrl |= TXGBE_PORTCTL_QINQ;
1088         wr32(hw, TXGBE_PORTCTL, ctrl);
1089 }
1090
1091 void
1092 txgbe_vlan_hw_strip_config(struct rte_eth_dev *dev)
1093 {
1094         struct txgbe_rx_queue *rxq;
1095         uint16_t i;
1096
1097         PMD_INIT_FUNC_TRACE();
1098
1099         for (i = 0; i < dev->data->nb_rx_queues; i++) {
1100                 rxq = dev->data->rx_queues[i];
1101
1102                 if (rxq->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1103                         txgbe_vlan_strip_queue_set(dev, i, 1);
1104                 else
1105                         txgbe_vlan_strip_queue_set(dev, i, 0);
1106         }
1107 }
1108
1109 void
1110 txgbe_config_vlan_strip_on_all_queues(struct rte_eth_dev *dev, int mask)
1111 {
1112         uint16_t i;
1113         struct rte_eth_rxmode *rxmode;
1114         struct txgbe_rx_queue *rxq;
1115
1116         if (mask & ETH_VLAN_STRIP_MASK) {
1117                 rxmode = &dev->data->dev_conf.rxmode;
1118                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1119                         for (i = 0; i < dev->data->nb_rx_queues; i++) {
1120                                 rxq = dev->data->rx_queues[i];
1121                                 rxq->offloads |= DEV_RX_OFFLOAD_VLAN_STRIP;
1122                         }
1123                 else
1124                         for (i = 0; i < dev->data->nb_rx_queues; i++) {
1125                                 rxq = dev->data->rx_queues[i];
1126                                 rxq->offloads &= ~DEV_RX_OFFLOAD_VLAN_STRIP;
1127                         }
1128         }
1129 }
1130
1131 static int
1132 txgbe_vlan_offload_config(struct rte_eth_dev *dev, int mask)
1133 {
1134         struct rte_eth_rxmode *rxmode;
1135         rxmode = &dev->data->dev_conf.rxmode;
1136
1137         if (mask & ETH_VLAN_STRIP_MASK)
1138                 txgbe_vlan_hw_strip_config(dev);
1139
1140         if (mask & ETH_VLAN_FILTER_MASK) {
1141                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
1142                         txgbe_vlan_hw_filter_enable(dev);
1143                 else
1144                         txgbe_vlan_hw_filter_disable(dev);
1145         }
1146
1147         if (mask & ETH_VLAN_EXTEND_MASK) {
1148                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
1149                         txgbe_vlan_hw_extend_enable(dev);
1150                 else
1151                         txgbe_vlan_hw_extend_disable(dev);
1152         }
1153
1154         return 0;
1155 }
1156
1157 static int
1158 txgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1159 {
1160         txgbe_config_vlan_strip_on_all_queues(dev, mask);
1161
1162         txgbe_vlan_offload_config(dev, mask);
1163
1164         return 0;
1165 }
1166
1167 static void
1168 txgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1169 {
1170         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
1171         /* VLNCTL: enable vlan filtering and allow all vlan tags through */
1172         uint32_t vlanctrl = rd32(hw, TXGBE_VLANCTL);
1173
1174         vlanctrl |= TXGBE_VLANCTL_VFE; /* enable vlan filters */
1175         wr32(hw, TXGBE_VLANCTL, vlanctrl);
1176 }
1177
1178 static int
1179 txgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q)
1180 {
1181         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1182
1183         switch (nb_rx_q) {
1184         case 1:
1185         case 2:
1186                 RTE_ETH_DEV_SRIOV(dev).active = ETH_64_POOLS;
1187                 break;
1188         case 4:
1189                 RTE_ETH_DEV_SRIOV(dev).active = ETH_32_POOLS;
1190                 break;
1191         default:
1192                 return -EINVAL;
1193         }
1194
1195         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool =
1196                 TXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
1197         RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx =
1198                 pci_dev->max_vfs * RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
1199         return 0;
1200 }
1201
1202 static int
1203 txgbe_check_mq_mode(struct rte_eth_dev *dev)
1204 {
1205         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
1206         uint16_t nb_rx_q = dev->data->nb_rx_queues;
1207         uint16_t nb_tx_q = dev->data->nb_tx_queues;
1208
1209         if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
1210                 /* check multi-queue mode */
1211                 switch (dev_conf->rxmode.mq_mode) {
1212                 case ETH_MQ_RX_VMDQ_DCB:
1213                         PMD_INIT_LOG(INFO, "ETH_MQ_RX_VMDQ_DCB mode supported in SRIOV");
1214                         break;
1215                 case ETH_MQ_RX_VMDQ_DCB_RSS:
1216                         /* DCB/RSS VMDQ in SRIOV mode, not implement yet */
1217                         PMD_INIT_LOG(ERR, "SRIOV active,"
1218                                         " unsupported mq_mode rx %d.",
1219                                         dev_conf->rxmode.mq_mode);
1220                         return -EINVAL;
1221                 case ETH_MQ_RX_RSS:
1222                 case ETH_MQ_RX_VMDQ_RSS:
1223                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_RSS;
1224                         if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)
1225                                 if (txgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) {
1226                                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1227                                                 " invalid queue number"
1228                                                 " for VMDQ RSS, allowed"
1229                                                 " value are 1, 2 or 4.");
1230                                         return -EINVAL;
1231                                 }
1232                         break;
1233                 case ETH_MQ_RX_VMDQ_ONLY:
1234                 case ETH_MQ_RX_NONE:
1235                         /* if nothing mq mode configure, use default scheme */
1236                         dev->data->dev_conf.rxmode.mq_mode =
1237                                 ETH_MQ_RX_VMDQ_ONLY;
1238                         break;
1239                 default: /* ETH_MQ_RX_DCB, ETH_MQ_RX_DCB_RSS or ETH_MQ_TX_DCB*/
1240                         /* SRIOV only works in VMDq enable mode */
1241                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1242                                         " wrong mq_mode rx %d.",
1243                                         dev_conf->rxmode.mq_mode);
1244                         return -EINVAL;
1245                 }
1246
1247                 switch (dev_conf->txmode.mq_mode) {
1248                 case ETH_MQ_TX_VMDQ_DCB:
1249                         PMD_INIT_LOG(INFO, "ETH_MQ_TX_VMDQ_DCB mode supported in SRIOV");
1250                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_DCB;
1251                         break;
1252                 default: /* ETH_MQ_TX_VMDQ_ONLY or ETH_MQ_TX_NONE */
1253                         dev->data->dev_conf.txmode.mq_mode =
1254                                 ETH_MQ_TX_VMDQ_ONLY;
1255                         break;
1256                 }
1257
1258                 /* check valid queue number */
1259                 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) ||
1260                     (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) {
1261                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1262                                         " nb_rx_q=%d nb_tx_q=%d queue number"
1263                                         " must be less than or equal to %d.",
1264                                         nb_rx_q, nb_tx_q,
1265                                         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool);
1266                         return -EINVAL;
1267                 }
1268         } else {
1269                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
1270                         PMD_INIT_LOG(ERR, "VMDQ+DCB+RSS mq_mode is"
1271                                           " not supported.");
1272                         return -EINVAL;
1273                 }
1274                 /* check configuration for vmdb+dcb mode */
1275                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB) {
1276                         const struct rte_eth_vmdq_dcb_conf *conf;
1277
1278                         if (nb_rx_q != TXGBE_VMDQ_DCB_NB_QUEUES) {
1279                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.",
1280                                                 TXGBE_VMDQ_DCB_NB_QUEUES);
1281                                 return -EINVAL;
1282                         }
1283                         conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf;
1284                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
1285                                conf->nb_queue_pools == ETH_32_POOLS)) {
1286                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
1287                                                 " nb_queue_pools must be %d or %d.",
1288                                                 ETH_16_POOLS, ETH_32_POOLS);
1289                                 return -EINVAL;
1290                         }
1291                 }
1292                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) {
1293                         const struct rte_eth_vmdq_dcb_tx_conf *conf;
1294
1295                         if (nb_tx_q != TXGBE_VMDQ_DCB_NB_QUEUES) {
1296                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d",
1297                                                  TXGBE_VMDQ_DCB_NB_QUEUES);
1298                                 return -EINVAL;
1299                         }
1300                         conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf;
1301                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
1302                                conf->nb_queue_pools == ETH_32_POOLS)) {
1303                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
1304                                                 " nb_queue_pools != %d and"
1305                                                 " nb_queue_pools != %d.",
1306                                                 ETH_16_POOLS, ETH_32_POOLS);
1307                                 return -EINVAL;
1308                         }
1309                 }
1310
1311                 /* For DCB mode check our configuration before we go further */
1312                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_DCB) {
1313                         const struct rte_eth_dcb_rx_conf *conf;
1314
1315                         conf = &dev_conf->rx_adv_conf.dcb_rx_conf;
1316                         if (!(conf->nb_tcs == ETH_4_TCS ||
1317                                conf->nb_tcs == ETH_8_TCS)) {
1318                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
1319                                                 " and nb_tcs != %d.",
1320                                                 ETH_4_TCS, ETH_8_TCS);
1321                                 return -EINVAL;
1322                         }
1323                 }
1324
1325                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_DCB) {
1326                         const struct rte_eth_dcb_tx_conf *conf;
1327
1328                         conf = &dev_conf->tx_adv_conf.dcb_tx_conf;
1329                         if (!(conf->nb_tcs == ETH_4_TCS ||
1330                                conf->nb_tcs == ETH_8_TCS)) {
1331                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
1332                                                 " and nb_tcs != %d.",
1333                                                 ETH_4_TCS, ETH_8_TCS);
1334                                 return -EINVAL;
1335                         }
1336                 }
1337         }
1338         return 0;
1339 }
1340
1341 static int
1342 txgbe_dev_configure(struct rte_eth_dev *dev)
1343 {
1344         struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);
1345         struct txgbe_adapter *adapter = TXGBE_DEV_ADAPTER(dev);
1346         int ret;
1347
1348         PMD_INIT_FUNC_TRACE();
1349
1350         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
1351                 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
1352
1353         /* multiple queue mode checking */
1354         ret  = txgbe_check_mq_mode(dev);
1355         if (ret != 0) {
1356                 PMD_DRV_LOG(ERR, "txgbe_check_mq_mode fails with %d.",
1357                             ret);
1358                 return ret;
1359         }
1360
1361         /* set flag to update link status after init */
1362         intr->flags |= TXGBE_FLAG_NEED_LINK_UPDATE;
1363
1364         /*
1365          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
1366          * allocation Rx preconditions we will reset it.
1367          */
1368         adapter->rx_bulk_alloc_allowed = true;
1369
1370         return 0;
1371 }
1372
1373 static void
1374 txgbe_dev_phy_intr_setup(struct rte_eth_dev *dev)
1375 {
1376         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
1377         struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);
1378         uint32_t gpie;
1379
1380         gpie = rd32(hw, TXGBE_GPIOINTEN);
1381         gpie |= TXGBE_GPIOBIT_6;
1382         wr32(hw, TXGBE_GPIOINTEN, gpie);
1383         intr->mask_misc |= TXGBE_ICRMISC_GPIO;
1384 }
1385
1386 int
1387 txgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
1388                         uint16_t tx_rate, uint64_t q_msk)
1389 {
1390         struct txgbe_hw *hw;
1391         struct txgbe_vf_info *vfinfo;
1392         struct rte_eth_link link;
1393         uint8_t  nb_q_per_pool;
1394         uint32_t queue_stride;
1395         uint32_t queue_idx, idx = 0, vf_idx;
1396         uint32_t queue_end;
1397         uint16_t total_rate = 0;
1398         struct rte_pci_device *pci_dev;
1399         int ret;
1400
1401         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1402         ret = rte_eth_link_get_nowait(dev->data->port_id, &link);
1403         if (ret < 0)
1404                 return ret;
1405
1406         if (vf >= pci_dev->max_vfs)
1407                 return -EINVAL;
1408
1409         if (tx_rate > link.link_speed)
1410                 return -EINVAL;
1411
1412         if (q_msk == 0)
1413                 return 0;
1414
1415         hw = TXGBE_DEV_HW(dev);
1416         vfinfo = *(TXGBE_DEV_VFDATA(dev));
1417         nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
1418         queue_stride = TXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
1419         queue_idx = vf * queue_stride;
1420         queue_end = queue_idx + nb_q_per_pool - 1;
1421         if (queue_end >= hw->mac.max_tx_queues)
1422                 return -EINVAL;
1423
1424         if (vfinfo) {
1425                 for (vf_idx = 0; vf_idx < pci_dev->max_vfs; vf_idx++) {
1426                         if (vf_idx == vf)
1427                                 continue;
1428                         for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
1429                                 idx++)
1430                                 total_rate += vfinfo[vf_idx].tx_rate[idx];
1431                 }
1432         } else {
1433                 return -EINVAL;
1434         }
1435
1436         /* Store tx_rate for this vf. */
1437         for (idx = 0; idx < nb_q_per_pool; idx++) {
1438                 if (((uint64_t)0x1 << idx) & q_msk) {
1439                         if (vfinfo[vf].tx_rate[idx] != tx_rate)
1440                                 vfinfo[vf].tx_rate[idx] = tx_rate;
1441                         total_rate += tx_rate;
1442                 }
1443         }
1444
1445         if (total_rate > dev->data->dev_link.link_speed) {
1446                 /* Reset stored TX rate of the VF if it causes exceed
1447                  * link speed.
1448                  */
1449                 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
1450                 return -EINVAL;
1451         }
1452
1453         /* Set ARBTXRATE of each queue/pool for vf X  */
1454         for (; queue_idx <= queue_end; queue_idx++) {
1455                 if (0x1 & q_msk)
1456                         txgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
1457                 q_msk = q_msk >> 1;
1458         }
1459
1460         return 0;
1461 }
1462
1463 /*
1464  * Configure device link speed and setup link.
1465  * It returns 0 on success.
1466  */
1467 static int
1468 txgbe_dev_start(struct rte_eth_dev *dev)
1469 {
1470         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
1471         struct txgbe_hw_stats *hw_stats = TXGBE_DEV_STATS(dev);
1472         struct txgbe_vf_info *vfinfo = *TXGBE_DEV_VFDATA(dev);
1473         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1474         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1475         uint32_t intr_vector = 0;
1476         int err;
1477         bool link_up = false, negotiate = 0;
1478         uint32_t speed = 0;
1479         uint32_t allowed_speeds = 0;
1480         int mask = 0;
1481         int status;
1482         uint16_t vf, idx;
1483         uint32_t *link_speeds;
1484
1485         PMD_INIT_FUNC_TRACE();
1486
1487         /* TXGBE devices don't support:
1488          *    - half duplex (checked afterwards for valid speeds)
1489          *    - fixed speed: TODO implement
1490          */
1491         if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
1492                 PMD_INIT_LOG(ERR,
1493                 "Invalid link_speeds for port %u, fix speed not supported",
1494                                 dev->data->port_id);
1495                 return -EINVAL;
1496         }
1497
1498         /* Stop the link setup handler before resetting the HW. */
1499         rte_eal_alarm_cancel(txgbe_dev_setup_link_alarm_handler, dev);
1500
1501         /* disable uio/vfio intr/eventfd mapping */
1502         rte_intr_disable(intr_handle);
1503
1504         /* stop adapter */
1505         hw->adapter_stopped = 0;
1506         txgbe_stop_hw(hw);
1507
1508         /* reinitialize adapter
1509          * this calls reset and start
1510          */
1511         hw->nb_rx_queues = dev->data->nb_rx_queues;
1512         hw->nb_tx_queues = dev->data->nb_tx_queues;
1513         status = txgbe_pf_reset_hw(hw);
1514         if (status != 0)
1515                 return -1;
1516         hw->mac.start_hw(hw);
1517         hw->mac.get_link_status = true;
1518
1519         /* configure PF module if SRIOV enabled */
1520         txgbe_pf_host_configure(dev);
1521
1522         txgbe_dev_phy_intr_setup(dev);
1523
1524         /* check and configure queue intr-vector mapping */
1525         if ((rte_intr_cap_multiple(intr_handle) ||
1526              !RTE_ETH_DEV_SRIOV(dev).active) &&
1527             dev->data->dev_conf.intr_conf.rxq != 0) {
1528                 intr_vector = dev->data->nb_rx_queues;
1529                 if (rte_intr_efd_enable(intr_handle, intr_vector))
1530                         return -1;
1531         }
1532
1533         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1534                 intr_handle->intr_vec =
1535                         rte_zmalloc("intr_vec",
1536                                     dev->data->nb_rx_queues * sizeof(int), 0);
1537                 if (intr_handle->intr_vec == NULL) {
1538                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
1539                                      " intr_vec", dev->data->nb_rx_queues);
1540                         return -ENOMEM;
1541                 }
1542         }
1543
1544         /* confiugre msix for sleep until rx interrupt */
1545         txgbe_configure_msix(dev);
1546
1547         /* initialize transmission unit */
1548         txgbe_dev_tx_init(dev);
1549
1550         /* This can fail when allocating mbufs for descriptor rings */
1551         err = txgbe_dev_rx_init(dev);
1552         if (err) {
1553                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
1554                 goto error;
1555         }
1556
1557         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
1558                 ETH_VLAN_EXTEND_MASK;
1559         err = txgbe_vlan_offload_config(dev, mask);
1560         if (err) {
1561                 PMD_INIT_LOG(ERR, "Unable to set VLAN offload");
1562                 goto error;
1563         }
1564
1565         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1566                 /* Enable vlan filtering for VMDq */
1567                 txgbe_vmdq_vlan_hw_filter_enable(dev);
1568         }
1569
1570         /* Configure DCB hw */
1571         txgbe_configure_pb(dev);
1572         txgbe_configure_port(dev);
1573         txgbe_configure_dcb(dev);
1574
1575         /* Restore vf rate limit */
1576         if (vfinfo != NULL) {
1577                 for (vf = 0; vf < pci_dev->max_vfs; vf++)
1578                         for (idx = 0; idx < TXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
1579                                 if (vfinfo[vf].tx_rate[idx] != 0)
1580                                         txgbe_set_vf_rate_limit(dev, vf,
1581                                                 vfinfo[vf].tx_rate[idx],
1582                                                 1 << idx);
1583         }
1584
1585         err = txgbe_dev_rxtx_start(dev);
1586         if (err < 0) {
1587                 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
1588                 goto error;
1589         }
1590
1591         /* Skip link setup if loopback mode is enabled. */
1592         if (hw->mac.type == txgbe_mac_raptor &&
1593             dev->data->dev_conf.lpbk_mode)
1594                 goto skip_link_setup;
1595
1596         if (txgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
1597                 err = hw->mac.setup_sfp(hw);
1598                 if (err)
1599                         goto error;
1600         }
1601
1602         if (hw->phy.media_type == txgbe_media_type_copper) {
1603                 /* Turn on the copper */
1604                 hw->phy.set_phy_power(hw, true);
1605         } else {
1606                 /* Turn on the laser */
1607                 hw->mac.enable_tx_laser(hw);
1608         }
1609
1610         err = hw->mac.check_link(hw, &speed, &link_up, 0);
1611         if (err)
1612                 goto error;
1613         dev->data->dev_link.link_status = link_up;
1614
1615         err = hw->mac.get_link_capabilities(hw, &speed, &negotiate);
1616         if (err)
1617                 goto error;
1618
1619         allowed_speeds = ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
1620                         ETH_LINK_SPEED_10G;
1621
1622         link_speeds = &dev->data->dev_conf.link_speeds;
1623         if (*link_speeds & ~allowed_speeds) {
1624                 PMD_INIT_LOG(ERR, "Invalid link setting");
1625                 goto error;
1626         }
1627
1628         speed = 0x0;
1629         if (*link_speeds == ETH_LINK_SPEED_AUTONEG) {
1630                 speed = (TXGBE_LINK_SPEED_100M_FULL |
1631                          TXGBE_LINK_SPEED_1GB_FULL |
1632                          TXGBE_LINK_SPEED_10GB_FULL);
1633         } else {
1634                 if (*link_speeds & ETH_LINK_SPEED_10G)
1635                         speed |= TXGBE_LINK_SPEED_10GB_FULL;
1636                 if (*link_speeds & ETH_LINK_SPEED_5G)
1637                         speed |= TXGBE_LINK_SPEED_5GB_FULL;
1638                 if (*link_speeds & ETH_LINK_SPEED_2_5G)
1639                         speed |= TXGBE_LINK_SPEED_2_5GB_FULL;
1640                 if (*link_speeds & ETH_LINK_SPEED_1G)
1641                         speed |= TXGBE_LINK_SPEED_1GB_FULL;
1642                 if (*link_speeds & ETH_LINK_SPEED_100M)
1643                         speed |= TXGBE_LINK_SPEED_100M_FULL;
1644         }
1645
1646         err = hw->mac.setup_link(hw, speed, link_up);
1647         if (err)
1648                 goto error;
1649
1650 skip_link_setup:
1651
1652         if (rte_intr_allow_others(intr_handle)) {
1653                 /* check if lsc interrupt is enabled */
1654                 if (dev->data->dev_conf.intr_conf.lsc != 0)
1655                         txgbe_dev_lsc_interrupt_setup(dev, TRUE);
1656                 else
1657                         txgbe_dev_lsc_interrupt_setup(dev, FALSE);
1658                 txgbe_dev_macsec_interrupt_setup(dev);
1659                 txgbe_set_ivar_map(hw, -1, 1, TXGBE_MISC_VEC_ID);
1660         } else {
1661                 rte_intr_callback_unregister(intr_handle,
1662                                              txgbe_dev_interrupt_handler, dev);
1663                 if (dev->data->dev_conf.intr_conf.lsc != 0)
1664                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
1665                                      " no intr multiplex");
1666         }
1667
1668         /* check if rxq interrupt is enabled */
1669         if (dev->data->dev_conf.intr_conf.rxq != 0 &&
1670             rte_intr_dp_is_en(intr_handle))
1671                 txgbe_dev_rxq_interrupt_setup(dev);
1672
1673         /* enable uio/vfio intr/eventfd mapping */
1674         rte_intr_enable(intr_handle);
1675
1676         /* resume enabled intr since hw reset */
1677         txgbe_enable_intr(dev);
1678         txgbe_filter_restore(dev);
1679
1680         /*
1681          * Update link status right before return, because it may
1682          * start link configuration process in a separate thread.
1683          */
1684         txgbe_dev_link_update(dev, 0);
1685
1686         wr32m(hw, TXGBE_LEDCTL, 0xFFFFFFFF, TXGBE_LEDCTL_ORD_MASK);
1687
1688         txgbe_read_stats_registers(hw, hw_stats);
1689         hw->offset_loaded = 1;
1690
1691         return 0;
1692
1693 error:
1694         PMD_INIT_LOG(ERR, "failure in dev start: %d", err);
1695         txgbe_dev_clear_queues(dev);
1696         return -EIO;
1697 }
1698
1699 /*
1700  * Stop device: disable rx and tx functions to allow for reconfiguring.
1701  */
1702 static int
1703 txgbe_dev_stop(struct rte_eth_dev *dev)
1704 {
1705         struct rte_eth_link link;
1706         struct txgbe_adapter *adapter = TXGBE_DEV_ADAPTER(dev);
1707         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
1708         struct txgbe_vf_info *vfinfo = *TXGBE_DEV_VFDATA(dev);
1709         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1710         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1711         int vf;
1712
1713         if (hw->adapter_stopped)
1714                 return 0;
1715
1716         PMD_INIT_FUNC_TRACE();
1717
1718         rte_eal_alarm_cancel(txgbe_dev_setup_link_alarm_handler, dev);
1719
1720         /* disable interrupts */
1721         txgbe_disable_intr(hw);
1722
1723         /* reset the NIC */
1724         txgbe_pf_reset_hw(hw);
1725         hw->adapter_stopped = 0;
1726
1727         /* stop adapter */
1728         txgbe_stop_hw(hw);
1729
1730         for (vf = 0; vfinfo != NULL && vf < pci_dev->max_vfs; vf++)
1731                 vfinfo[vf].clear_to_send = false;
1732
1733         if (hw->phy.media_type == txgbe_media_type_copper) {
1734                 /* Turn off the copper */
1735                 hw->phy.set_phy_power(hw, false);
1736         } else {
1737                 /* Turn off the laser */
1738                 hw->mac.disable_tx_laser(hw);
1739         }
1740
1741         txgbe_dev_clear_queues(dev);
1742
1743         /* Clear stored conf */
1744         dev->data->scattered_rx = 0;
1745         dev->data->lro = 0;
1746
1747         /* Clear recorded link status */
1748         memset(&link, 0, sizeof(link));
1749         rte_eth_linkstatus_set(dev, &link);
1750
1751         if (!rte_intr_allow_others(intr_handle))
1752                 /* resume to the default handler */
1753                 rte_intr_callback_register(intr_handle,
1754                                            txgbe_dev_interrupt_handler,
1755                                            (void *)dev);
1756
1757         /* Clean datapath event and queue/vec mapping */
1758         rte_intr_efd_disable(intr_handle);
1759         if (intr_handle->intr_vec != NULL) {
1760                 rte_free(intr_handle->intr_vec);
1761                 intr_handle->intr_vec = NULL;
1762         }
1763
1764         adapter->rss_reta_updated = 0;
1765         wr32m(hw, TXGBE_LEDCTL, 0xFFFFFFFF, TXGBE_LEDCTL_SEL_MASK);
1766
1767         hw->adapter_stopped = true;
1768         dev->data->dev_started = 0;
1769
1770         return 0;
1771 }
1772
1773 /*
1774  * Set device link up: enable tx.
1775  */
1776 static int
1777 txgbe_dev_set_link_up(struct rte_eth_dev *dev)
1778 {
1779         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
1780
1781         if (hw->phy.media_type == txgbe_media_type_copper) {
1782                 /* Turn on the copper */
1783                 hw->phy.set_phy_power(hw, true);
1784         } else {
1785                 /* Turn on the laser */
1786                 hw->mac.enable_tx_laser(hw);
1787                 txgbe_dev_link_update(dev, 0);
1788         }
1789
1790         return 0;
1791 }
1792
1793 /*
1794  * Set device link down: disable tx.
1795  */
1796 static int
1797 txgbe_dev_set_link_down(struct rte_eth_dev *dev)
1798 {
1799         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
1800
1801         if (hw->phy.media_type == txgbe_media_type_copper) {
1802                 /* Turn off the copper */
1803                 hw->phy.set_phy_power(hw, false);
1804         } else {
1805                 /* Turn off the laser */
1806                 hw->mac.disable_tx_laser(hw);
1807                 txgbe_dev_link_update(dev, 0);
1808         }
1809
1810         return 0;
1811 }
1812
1813 /*
1814  * Reset and stop device.
1815  */
1816 static int
1817 txgbe_dev_close(struct rte_eth_dev *dev)
1818 {
1819         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
1820         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1821         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1822         int retries = 0;
1823         int ret;
1824
1825         PMD_INIT_FUNC_TRACE();
1826
1827         txgbe_pf_reset_hw(hw);
1828
1829         ret = txgbe_dev_stop(dev);
1830
1831         txgbe_dev_free_queues(dev);
1832
1833         /* reprogram the RAR[0] in case user changed it. */
1834         txgbe_set_rar(hw, 0, hw->mac.addr, 0, true);
1835
1836         /* Unlock any pending hardware semaphore */
1837         txgbe_swfw_lock_reset(hw);
1838
1839         /* disable uio intr before callback unregister */
1840         rte_intr_disable(intr_handle);
1841
1842         do {
1843                 ret = rte_intr_callback_unregister(intr_handle,
1844                                 txgbe_dev_interrupt_handler, dev);
1845                 if (ret >= 0 || ret == -ENOENT) {
1846                         break;
1847                 } else if (ret != -EAGAIN) {
1848                         PMD_INIT_LOG(ERR,
1849                                 "intr callback unregister failed: %d",
1850                                 ret);
1851                 }
1852                 rte_delay_ms(100);
1853         } while (retries++ < (10 + TXGBE_LINK_UP_TIME));
1854
1855         /* cancel the delay handler before remove dev */
1856         rte_eal_alarm_cancel(txgbe_dev_interrupt_delayed_handler, dev);
1857
1858         /* uninitialize PF if max_vfs not zero */
1859         txgbe_pf_host_uninit(dev);
1860
1861         rte_free(dev->data->mac_addrs);
1862         dev->data->mac_addrs = NULL;
1863
1864         rte_free(dev->data->hash_mac_addrs);
1865         dev->data->hash_mac_addrs = NULL;
1866
1867         /* remove all the L2 tunnel filters & hash */
1868         txgbe_l2_tn_filter_uninit(dev);
1869
1870         /* Remove all ntuple filters of the device */
1871         txgbe_ntuple_filter_uninit(dev);
1872
1873         return ret;
1874 }
1875
1876 /*
1877  * Reset PF device.
1878  */
1879 static int
1880 txgbe_dev_reset(struct rte_eth_dev *dev)
1881 {
1882         int ret;
1883
1884         /* When a DPDK PMD PF begin to reset PF port, it should notify all
1885          * its VF to make them align with it. The detailed notification
1886          * mechanism is PMD specific. As to txgbe PF, it is rather complex.
1887          * To avoid unexpected behavior in VF, currently reset of PF with
1888          * SR-IOV activation is not supported. It might be supported later.
1889          */
1890         if (dev->data->sriov.active)
1891                 return -ENOTSUP;
1892
1893         ret = eth_txgbe_dev_uninit(dev);
1894         if (ret)
1895                 return ret;
1896
1897         ret = eth_txgbe_dev_init(dev, NULL);
1898
1899         return ret;
1900 }
1901
1902 #define UPDATE_QP_COUNTER_32bit(reg, last_counter, counter)     \
1903         {                                                       \
1904                 uint32_t current_counter = rd32(hw, reg);       \
1905                 if (current_counter < last_counter)             \
1906                         current_counter += 0x100000000LL;       \
1907                 if (!hw->offset_loaded)                         \
1908                         last_counter = current_counter;         \
1909                 counter = current_counter - last_counter;       \
1910                 counter &= 0xFFFFFFFFLL;                        \
1911         }
1912
1913 #define UPDATE_QP_COUNTER_36bit(reg_lsb, reg_msb, last_counter, counter) \
1914         {                                                                \
1915                 uint64_t current_counter_lsb = rd32(hw, reg_lsb);        \
1916                 uint64_t current_counter_msb = rd32(hw, reg_msb);        \
1917                 uint64_t current_counter = (current_counter_msb << 32) | \
1918                         current_counter_lsb;                             \
1919                 if (current_counter < last_counter)                      \
1920                         current_counter += 0x1000000000LL;               \
1921                 if (!hw->offset_loaded)                                  \
1922                         last_counter = current_counter;                  \
1923                 counter = current_counter - last_counter;                \
1924                 counter &= 0xFFFFFFFFFLL;                                \
1925         }
1926
1927 void
1928 txgbe_read_stats_registers(struct txgbe_hw *hw,
1929                            struct txgbe_hw_stats *hw_stats)
1930 {
1931         unsigned int i;
1932
1933         /* QP Stats */
1934         for (i = 0; i < hw->nb_rx_queues; i++) {
1935                 UPDATE_QP_COUNTER_32bit(TXGBE_QPRXPKT(i),
1936                         hw->qp_last[i].rx_qp_packets,
1937                         hw_stats->qp[i].rx_qp_packets);
1938                 UPDATE_QP_COUNTER_36bit(TXGBE_QPRXOCTL(i), TXGBE_QPRXOCTH(i),
1939                         hw->qp_last[i].rx_qp_bytes,
1940                         hw_stats->qp[i].rx_qp_bytes);
1941                 UPDATE_QP_COUNTER_32bit(TXGBE_QPRXMPKT(i),
1942                         hw->qp_last[i].rx_qp_mc_packets,
1943                         hw_stats->qp[i].rx_qp_mc_packets);
1944         }
1945
1946         for (i = 0; i < hw->nb_tx_queues; i++) {
1947                 UPDATE_QP_COUNTER_32bit(TXGBE_QPTXPKT(i),
1948                         hw->qp_last[i].tx_qp_packets,
1949                         hw_stats->qp[i].tx_qp_packets);
1950                 UPDATE_QP_COUNTER_36bit(TXGBE_QPTXOCTL(i), TXGBE_QPTXOCTH(i),
1951                         hw->qp_last[i].tx_qp_bytes,
1952                         hw_stats->qp[i].tx_qp_bytes);
1953         }
1954         /* PB Stats */
1955         for (i = 0; i < TXGBE_MAX_UP; i++) {
1956                 hw_stats->up[i].rx_up_xon_packets +=
1957                                 rd32(hw, TXGBE_PBRXUPXON(i));
1958                 hw_stats->up[i].rx_up_xoff_packets +=
1959                                 rd32(hw, TXGBE_PBRXUPXOFF(i));
1960                 hw_stats->up[i].tx_up_xon_packets +=
1961                                 rd32(hw, TXGBE_PBTXUPXON(i));
1962                 hw_stats->up[i].tx_up_xoff_packets +=
1963                                 rd32(hw, TXGBE_PBTXUPXOFF(i));
1964                 hw_stats->up[i].tx_up_xon2off_packets +=
1965                                 rd32(hw, TXGBE_PBTXUPOFF(i));
1966                 hw_stats->up[i].rx_up_dropped +=
1967                                 rd32(hw, TXGBE_PBRXMISS(i));
1968         }
1969         hw_stats->rx_xon_packets += rd32(hw, TXGBE_PBRXLNKXON);
1970         hw_stats->rx_xoff_packets += rd32(hw, TXGBE_PBRXLNKXOFF);
1971         hw_stats->tx_xon_packets += rd32(hw, TXGBE_PBTXLNKXON);
1972         hw_stats->tx_xoff_packets += rd32(hw, TXGBE_PBTXLNKXOFF);
1973
1974         /* DMA Stats */
1975         hw_stats->rx_packets += rd32(hw, TXGBE_DMARXPKT);
1976         hw_stats->tx_packets += rd32(hw, TXGBE_DMATXPKT);
1977
1978         hw_stats->rx_bytes += rd64(hw, TXGBE_DMARXOCTL);
1979         hw_stats->tx_bytes += rd64(hw, TXGBE_DMATXOCTL);
1980         hw_stats->rx_drop_packets += rd32(hw, TXGBE_PBRXDROP);
1981
1982         /* MAC Stats */
1983         hw_stats->rx_crc_errors += rd64(hw, TXGBE_MACRXERRCRCL);
1984         hw_stats->rx_multicast_packets += rd64(hw, TXGBE_MACRXMPKTL);
1985         hw_stats->tx_multicast_packets += rd64(hw, TXGBE_MACTXMPKTL);
1986
1987         hw_stats->rx_total_packets += rd64(hw, TXGBE_MACRXPKTL);
1988         hw_stats->tx_total_packets += rd64(hw, TXGBE_MACTXPKTL);
1989         hw_stats->rx_total_bytes += rd64(hw, TXGBE_MACRXGBOCTL);
1990
1991         hw_stats->rx_broadcast_packets += rd64(hw, TXGBE_MACRXOCTL);
1992         hw_stats->tx_broadcast_packets += rd32(hw, TXGBE_MACTXOCTL);
1993
1994         hw_stats->rx_size_64_packets += rd64(hw, TXGBE_MACRX1TO64L);
1995         hw_stats->rx_size_65_to_127_packets += rd64(hw, TXGBE_MACRX65TO127L);
1996         hw_stats->rx_size_128_to_255_packets += rd64(hw, TXGBE_MACRX128TO255L);
1997         hw_stats->rx_size_256_to_511_packets += rd64(hw, TXGBE_MACRX256TO511L);
1998         hw_stats->rx_size_512_to_1023_packets +=
1999                         rd64(hw, TXGBE_MACRX512TO1023L);
2000         hw_stats->rx_size_1024_to_max_packets +=
2001                         rd64(hw, TXGBE_MACRX1024TOMAXL);
2002         hw_stats->tx_size_64_packets += rd64(hw, TXGBE_MACTX1TO64L);
2003         hw_stats->tx_size_65_to_127_packets += rd64(hw, TXGBE_MACTX65TO127L);
2004         hw_stats->tx_size_128_to_255_packets += rd64(hw, TXGBE_MACTX128TO255L);
2005         hw_stats->tx_size_256_to_511_packets += rd64(hw, TXGBE_MACTX256TO511L);
2006         hw_stats->tx_size_512_to_1023_packets +=
2007                         rd64(hw, TXGBE_MACTX512TO1023L);
2008         hw_stats->tx_size_1024_to_max_packets +=
2009                         rd64(hw, TXGBE_MACTX1024TOMAXL);
2010
2011         hw_stats->rx_undersize_errors += rd64(hw, TXGBE_MACRXERRLENL);
2012         hw_stats->rx_oversize_errors += rd32(hw, TXGBE_MACRXOVERSIZE);
2013         hw_stats->rx_jabber_errors += rd32(hw, TXGBE_MACRXJABBER);
2014
2015         /* MNG Stats */
2016         hw_stats->mng_bmc2host_packets = rd32(hw, TXGBE_MNGBMC2OS);
2017         hw_stats->mng_host2bmc_packets = rd32(hw, TXGBE_MNGOS2BMC);
2018         hw_stats->rx_management_packets = rd32(hw, TXGBE_DMARXMNG);
2019         hw_stats->tx_management_packets = rd32(hw, TXGBE_DMATXMNG);
2020
2021         /* FCoE Stats */
2022         hw_stats->rx_fcoe_crc_errors += rd32(hw, TXGBE_FCOECRC);
2023         hw_stats->rx_fcoe_mbuf_allocation_errors += rd32(hw, TXGBE_FCOELAST);
2024         hw_stats->rx_fcoe_dropped += rd32(hw, TXGBE_FCOERPDC);
2025         hw_stats->rx_fcoe_packets += rd32(hw, TXGBE_FCOEPRC);
2026         hw_stats->tx_fcoe_packets += rd32(hw, TXGBE_FCOEPTC);
2027         hw_stats->rx_fcoe_bytes += rd32(hw, TXGBE_FCOEDWRC);
2028         hw_stats->tx_fcoe_bytes += rd32(hw, TXGBE_FCOEDWTC);
2029
2030         /* Flow Director Stats */
2031         hw_stats->flow_director_matched_filters += rd32(hw, TXGBE_FDIRMATCH);
2032         hw_stats->flow_director_missed_filters += rd32(hw, TXGBE_FDIRMISS);
2033         hw_stats->flow_director_added_filters +=
2034                 TXGBE_FDIRUSED_ADD(rd32(hw, TXGBE_FDIRUSED));
2035         hw_stats->flow_director_removed_filters +=
2036                 TXGBE_FDIRUSED_REM(rd32(hw, TXGBE_FDIRUSED));
2037         hw_stats->flow_director_filter_add_errors +=
2038                 TXGBE_FDIRFAIL_ADD(rd32(hw, TXGBE_FDIRFAIL));
2039         hw_stats->flow_director_filter_remove_errors +=
2040                 TXGBE_FDIRFAIL_REM(rd32(hw, TXGBE_FDIRFAIL));
2041
2042         /* MACsec Stats */
2043         hw_stats->tx_macsec_pkts_untagged += rd32(hw, TXGBE_LSECTX_UTPKT);
2044         hw_stats->tx_macsec_pkts_encrypted +=
2045                         rd32(hw, TXGBE_LSECTX_ENCPKT);
2046         hw_stats->tx_macsec_pkts_protected +=
2047                         rd32(hw, TXGBE_LSECTX_PROTPKT);
2048         hw_stats->tx_macsec_octets_encrypted +=
2049                         rd32(hw, TXGBE_LSECTX_ENCOCT);
2050         hw_stats->tx_macsec_octets_protected +=
2051                         rd32(hw, TXGBE_LSECTX_PROTOCT);
2052         hw_stats->rx_macsec_pkts_untagged += rd32(hw, TXGBE_LSECRX_UTPKT);
2053         hw_stats->rx_macsec_pkts_badtag += rd32(hw, TXGBE_LSECRX_BTPKT);
2054         hw_stats->rx_macsec_pkts_nosci += rd32(hw, TXGBE_LSECRX_NOSCIPKT);
2055         hw_stats->rx_macsec_pkts_unknownsci += rd32(hw, TXGBE_LSECRX_UNSCIPKT);
2056         hw_stats->rx_macsec_octets_decrypted += rd32(hw, TXGBE_LSECRX_DECOCT);
2057         hw_stats->rx_macsec_octets_validated += rd32(hw, TXGBE_LSECRX_VLDOCT);
2058         hw_stats->rx_macsec_sc_pkts_unchecked +=
2059                         rd32(hw, TXGBE_LSECRX_UNCHKPKT);
2060         hw_stats->rx_macsec_sc_pkts_delayed += rd32(hw, TXGBE_LSECRX_DLYPKT);
2061         hw_stats->rx_macsec_sc_pkts_late += rd32(hw, TXGBE_LSECRX_LATEPKT);
2062         for (i = 0; i < 2; i++) {
2063                 hw_stats->rx_macsec_sa_pkts_ok +=
2064                         rd32(hw, TXGBE_LSECRX_OKPKT(i));
2065                 hw_stats->rx_macsec_sa_pkts_invalid +=
2066                         rd32(hw, TXGBE_LSECRX_INVPKT(i));
2067                 hw_stats->rx_macsec_sa_pkts_notvalid +=
2068                         rd32(hw, TXGBE_LSECRX_BADPKT(i));
2069         }
2070         hw_stats->rx_macsec_sa_pkts_unusedsa +=
2071                         rd32(hw, TXGBE_LSECRX_INVSAPKT);
2072         hw_stats->rx_macsec_sa_pkts_notusingsa +=
2073                         rd32(hw, TXGBE_LSECRX_BADSAPKT);
2074
2075         hw_stats->rx_total_missed_packets = 0;
2076         for (i = 0; i < TXGBE_MAX_UP; i++) {
2077                 hw_stats->rx_total_missed_packets +=
2078                         hw_stats->up[i].rx_up_dropped;
2079         }
2080 }
2081
2082 static int
2083 txgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2084 {
2085         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2086         struct txgbe_hw_stats *hw_stats = TXGBE_DEV_STATS(dev);
2087         struct txgbe_stat_mappings *stat_mappings =
2088                         TXGBE_DEV_STAT_MAPPINGS(dev);
2089         uint32_t i, j;
2090
2091         txgbe_read_stats_registers(hw, hw_stats);
2092
2093         if (stats == NULL)
2094                 return -EINVAL;
2095
2096         /* Fill out the rte_eth_stats statistics structure */
2097         stats->ipackets = hw_stats->rx_packets;
2098         stats->ibytes = hw_stats->rx_bytes;
2099         stats->opackets = hw_stats->tx_packets;
2100         stats->obytes = hw_stats->tx_bytes;
2101
2102         memset(&stats->q_ipackets, 0, sizeof(stats->q_ipackets));
2103         memset(&stats->q_opackets, 0, sizeof(stats->q_opackets));
2104         memset(&stats->q_ibytes, 0, sizeof(stats->q_ibytes));
2105         memset(&stats->q_obytes, 0, sizeof(stats->q_obytes));
2106         memset(&stats->q_errors, 0, sizeof(stats->q_errors));
2107         for (i = 0; i < TXGBE_MAX_QP; i++) {
2108                 uint32_t n = i / NB_QMAP_FIELDS_PER_QSM_REG;
2109                 uint32_t offset = (i % NB_QMAP_FIELDS_PER_QSM_REG) * 8;
2110                 uint32_t q_map;
2111
2112                 q_map = (stat_mappings->rqsm[n] >> offset)
2113                                 & QMAP_FIELD_RESERVED_BITS_MASK;
2114                 j = (q_map < RTE_ETHDEV_QUEUE_STAT_CNTRS
2115                      ? q_map : q_map % RTE_ETHDEV_QUEUE_STAT_CNTRS);
2116                 stats->q_ipackets[j] += hw_stats->qp[i].rx_qp_packets;
2117                 stats->q_ibytes[j] += hw_stats->qp[i].rx_qp_bytes;
2118
2119                 q_map = (stat_mappings->tqsm[n] >> offset)
2120                                 & QMAP_FIELD_RESERVED_BITS_MASK;
2121                 j = (q_map < RTE_ETHDEV_QUEUE_STAT_CNTRS
2122                      ? q_map : q_map % RTE_ETHDEV_QUEUE_STAT_CNTRS);
2123                 stats->q_opackets[j] += hw_stats->qp[i].tx_qp_packets;
2124                 stats->q_obytes[j] += hw_stats->qp[i].tx_qp_bytes;
2125         }
2126
2127         /* Rx Errors */
2128         stats->imissed  = hw_stats->rx_total_missed_packets;
2129         stats->ierrors  = hw_stats->rx_crc_errors +
2130                           hw_stats->rx_mac_short_packet_dropped +
2131                           hw_stats->rx_length_errors +
2132                           hw_stats->rx_undersize_errors +
2133                           hw_stats->rx_oversize_errors +
2134                           hw_stats->rx_drop_packets +
2135                           hw_stats->rx_illegal_byte_errors +
2136                           hw_stats->rx_error_bytes +
2137                           hw_stats->rx_fragment_errors +
2138                           hw_stats->rx_fcoe_crc_errors +
2139                           hw_stats->rx_fcoe_mbuf_allocation_errors;
2140
2141         /* Tx Errors */
2142         stats->oerrors  = 0;
2143         return 0;
2144 }
2145
2146 static int
2147 txgbe_dev_stats_reset(struct rte_eth_dev *dev)
2148 {
2149         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2150         struct txgbe_hw_stats *hw_stats = TXGBE_DEV_STATS(dev);
2151
2152         /* HW registers are cleared on read */
2153         hw->offset_loaded = 0;
2154         txgbe_dev_stats_get(dev, NULL);
2155         hw->offset_loaded = 1;
2156
2157         /* Reset software totals */
2158         memset(hw_stats, 0, sizeof(*hw_stats));
2159
2160         return 0;
2161 }
2162
2163 /* This function calculates the number of xstats based on the current config */
2164 static unsigned
2165 txgbe_xstats_calc_num(struct rte_eth_dev *dev)
2166 {
2167         int nb_queues = max(dev->data->nb_rx_queues, dev->data->nb_tx_queues);
2168         return TXGBE_NB_HW_STATS +
2169                TXGBE_NB_UP_STATS * TXGBE_MAX_UP +
2170                TXGBE_NB_QP_STATS * nb_queues;
2171 }
2172
2173 static inline int
2174 txgbe_get_name_by_id(uint32_t id, char *name, uint32_t size)
2175 {
2176         int nb, st;
2177
2178         /* Extended stats from txgbe_hw_stats */
2179         if (id < TXGBE_NB_HW_STATS) {
2180                 snprintf(name, size, "[hw]%s",
2181                         rte_txgbe_stats_strings[id].name);
2182                 return 0;
2183         }
2184         id -= TXGBE_NB_HW_STATS;
2185
2186         /* Priority Stats */
2187         if (id < TXGBE_NB_UP_STATS * TXGBE_MAX_UP) {
2188                 nb = id / TXGBE_NB_UP_STATS;
2189                 st = id % TXGBE_NB_UP_STATS;
2190                 snprintf(name, size, "[p%u]%s", nb,
2191                         rte_txgbe_up_strings[st].name);
2192                 return 0;
2193         }
2194         id -= TXGBE_NB_UP_STATS * TXGBE_MAX_UP;
2195
2196         /* Queue Stats */
2197         if (id < TXGBE_NB_QP_STATS * TXGBE_MAX_QP) {
2198                 nb = id / TXGBE_NB_QP_STATS;
2199                 st = id % TXGBE_NB_QP_STATS;
2200                 snprintf(name, size, "[q%u]%s", nb,
2201                         rte_txgbe_qp_strings[st].name);
2202                 return 0;
2203         }
2204         id -= TXGBE_NB_QP_STATS * TXGBE_MAX_QP;
2205
2206         return -(int)(id + 1);
2207 }
2208
2209 static inline int
2210 txgbe_get_offset_by_id(uint32_t id, uint32_t *offset)
2211 {
2212         int nb, st;
2213
2214         /* Extended stats from txgbe_hw_stats */
2215         if (id < TXGBE_NB_HW_STATS) {
2216                 *offset = rte_txgbe_stats_strings[id].offset;
2217                 return 0;
2218         }
2219         id -= TXGBE_NB_HW_STATS;
2220
2221         /* Priority Stats */
2222         if (id < TXGBE_NB_UP_STATS * TXGBE_MAX_UP) {
2223                 nb = id / TXGBE_NB_UP_STATS;
2224                 st = id % TXGBE_NB_UP_STATS;
2225                 *offset = rte_txgbe_up_strings[st].offset +
2226                         nb * (TXGBE_NB_UP_STATS * sizeof(uint64_t));
2227                 return 0;
2228         }
2229         id -= TXGBE_NB_UP_STATS * TXGBE_MAX_UP;
2230
2231         /* Queue Stats */
2232         if (id < TXGBE_NB_QP_STATS * TXGBE_MAX_QP) {
2233                 nb = id / TXGBE_NB_QP_STATS;
2234                 st = id % TXGBE_NB_QP_STATS;
2235                 *offset = rte_txgbe_qp_strings[st].offset +
2236                         nb * (TXGBE_NB_QP_STATS * sizeof(uint64_t));
2237                 return 0;
2238         }
2239
2240         return -1;
2241 }
2242
2243 static int txgbe_dev_xstats_get_names(struct rte_eth_dev *dev,
2244         struct rte_eth_xstat_name *xstats_names, unsigned int limit)
2245 {
2246         unsigned int i, count;
2247
2248         count = txgbe_xstats_calc_num(dev);
2249         if (xstats_names == NULL)
2250                 return count;
2251
2252         /* Note: limit >= cnt_stats checked upstream
2253          * in rte_eth_xstats_names()
2254          */
2255         limit = min(limit, count);
2256
2257         /* Extended stats from txgbe_hw_stats */
2258         for (i = 0; i < limit; i++) {
2259                 if (txgbe_get_name_by_id(i, xstats_names[i].name,
2260                         sizeof(xstats_names[i].name))) {
2261                         PMD_INIT_LOG(WARNING, "id value %d isn't valid", i);
2262                         break;
2263                 }
2264         }
2265
2266         return i;
2267 }
2268
2269 static int txgbe_dev_xstats_get_names_by_id(struct rte_eth_dev *dev,
2270         struct rte_eth_xstat_name *xstats_names,
2271         const uint64_t *ids,
2272         unsigned int limit)
2273 {
2274         unsigned int i;
2275
2276         if (ids == NULL)
2277                 return txgbe_dev_xstats_get_names(dev, xstats_names, limit);
2278
2279         for (i = 0; i < limit; i++) {
2280                 if (txgbe_get_name_by_id(ids[i], xstats_names[i].name,
2281                                 sizeof(xstats_names[i].name))) {
2282                         PMD_INIT_LOG(WARNING, "id value %d isn't valid", i);
2283                         return -1;
2284                 }
2285         }
2286
2287         return i;
2288 }
2289
2290 static int
2291 txgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2292                                          unsigned int limit)
2293 {
2294         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2295         struct txgbe_hw_stats *hw_stats = TXGBE_DEV_STATS(dev);
2296         unsigned int i, count;
2297
2298         txgbe_read_stats_registers(hw, hw_stats);
2299
2300         /* If this is a reset xstats is NULL, and we have cleared the
2301          * registers by reading them.
2302          */
2303         count = txgbe_xstats_calc_num(dev);
2304         if (xstats == NULL)
2305                 return count;
2306
2307         limit = min(limit, txgbe_xstats_calc_num(dev));
2308
2309         /* Extended stats from txgbe_hw_stats */
2310         for (i = 0; i < limit; i++) {
2311                 uint32_t offset = 0;
2312
2313                 if (txgbe_get_offset_by_id(i, &offset)) {
2314                         PMD_INIT_LOG(WARNING, "id value %d isn't valid", i);
2315                         break;
2316                 }
2317                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) + offset);
2318                 xstats[i].id = i;
2319         }
2320
2321         return i;
2322 }
2323
2324 static int
2325 txgbe_dev_xstats_get_(struct rte_eth_dev *dev, uint64_t *values,
2326                                          unsigned int limit)
2327 {
2328         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2329         struct txgbe_hw_stats *hw_stats = TXGBE_DEV_STATS(dev);
2330         unsigned int i, count;
2331
2332         txgbe_read_stats_registers(hw, hw_stats);
2333
2334         /* If this is a reset xstats is NULL, and we have cleared the
2335          * registers by reading them.
2336          */
2337         count = txgbe_xstats_calc_num(dev);
2338         if (values == NULL)
2339                 return count;
2340
2341         limit = min(limit, txgbe_xstats_calc_num(dev));
2342
2343         /* Extended stats from txgbe_hw_stats */
2344         for (i = 0; i < limit; i++) {
2345                 uint32_t offset;
2346
2347                 if (txgbe_get_offset_by_id(i, &offset)) {
2348                         PMD_INIT_LOG(WARNING, "id value %d isn't valid", i);
2349                         break;
2350                 }
2351                 values[i] = *(uint64_t *)(((char *)hw_stats) + offset);
2352         }
2353
2354         return i;
2355 }
2356
2357 static int
2358 txgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
2359                 uint64_t *values, unsigned int limit)
2360 {
2361         struct txgbe_hw_stats *hw_stats = TXGBE_DEV_STATS(dev);
2362         unsigned int i;
2363
2364         if (ids == NULL)
2365                 return txgbe_dev_xstats_get_(dev, values, limit);
2366
2367         for (i = 0; i < limit; i++) {
2368                 uint32_t offset;
2369
2370                 if (txgbe_get_offset_by_id(ids[i], &offset)) {
2371                         PMD_INIT_LOG(WARNING, "id value %d isn't valid", i);
2372                         break;
2373                 }
2374                 values[i] = *(uint64_t *)(((char *)hw_stats) + offset);
2375         }
2376
2377         return i;
2378 }
2379
2380 static int
2381 txgbe_dev_xstats_reset(struct rte_eth_dev *dev)
2382 {
2383         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2384         struct txgbe_hw_stats *hw_stats = TXGBE_DEV_STATS(dev);
2385
2386         /* HW registers are cleared on read */
2387         hw->offset_loaded = 0;
2388         txgbe_read_stats_registers(hw, hw_stats);
2389         hw->offset_loaded = 1;
2390
2391         /* Reset software totals */
2392         memset(hw_stats, 0, sizeof(*hw_stats));
2393
2394         return 0;
2395 }
2396
2397 static int
2398 txgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
2399 {
2400         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2401         u16 eeprom_verh, eeprom_verl;
2402         u32 etrack_id;
2403         int ret;
2404
2405         hw->rom.readw_sw(hw, TXGBE_EEPROM_VERSION_H, &eeprom_verh);
2406         hw->rom.readw_sw(hw, TXGBE_EEPROM_VERSION_L, &eeprom_verl);
2407
2408         etrack_id = (eeprom_verh << 16) | eeprom_verl;
2409         ret = snprintf(fw_version, fw_size, "0x%08x", etrack_id);
2410
2411         ret += 1; /* add the size of '\0' */
2412         if (fw_size < (u32)ret)
2413                 return ret;
2414         else
2415                 return 0;
2416 }
2417
2418 static int
2419 txgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2420 {
2421         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2422         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2423
2424         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
2425         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
2426         dev_info->min_rx_bufsize = 1024;
2427         dev_info->max_rx_pktlen = 15872;
2428         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
2429         dev_info->max_hash_mac_addrs = TXGBE_VMDQ_NUM_UC_MAC;
2430         dev_info->max_vfs = pci_dev->max_vfs;
2431         dev_info->max_vmdq_pools = ETH_64_POOLS;
2432         dev_info->vmdq_queue_num = dev_info->max_rx_queues;
2433         dev_info->rx_queue_offload_capa = txgbe_get_rx_queue_offloads(dev);
2434         dev_info->rx_offload_capa = (txgbe_get_rx_port_offloads(dev) |
2435                                      dev_info->rx_queue_offload_capa);
2436         dev_info->tx_queue_offload_capa = txgbe_get_tx_queue_offloads(dev);
2437         dev_info->tx_offload_capa = txgbe_get_tx_port_offloads(dev);
2438
2439         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2440                 .rx_thresh = {
2441                         .pthresh = TXGBE_DEFAULT_RX_PTHRESH,
2442                         .hthresh = TXGBE_DEFAULT_RX_HTHRESH,
2443                         .wthresh = TXGBE_DEFAULT_RX_WTHRESH,
2444                 },
2445                 .rx_free_thresh = TXGBE_DEFAULT_RX_FREE_THRESH,
2446                 .rx_drop_en = 0,
2447                 .offloads = 0,
2448         };
2449
2450         dev_info->default_txconf = (struct rte_eth_txconf) {
2451                 .tx_thresh = {
2452                         .pthresh = TXGBE_DEFAULT_TX_PTHRESH,
2453                         .hthresh = TXGBE_DEFAULT_TX_HTHRESH,
2454                         .wthresh = TXGBE_DEFAULT_TX_WTHRESH,
2455                 },
2456                 .tx_free_thresh = TXGBE_DEFAULT_TX_FREE_THRESH,
2457                 .offloads = 0,
2458         };
2459
2460         dev_info->rx_desc_lim = rx_desc_lim;
2461         dev_info->tx_desc_lim = tx_desc_lim;
2462
2463         dev_info->hash_key_size = TXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
2464         dev_info->reta_size = ETH_RSS_RETA_SIZE_128;
2465         dev_info->flow_type_rss_offloads = TXGBE_RSS_OFFLOAD_ALL;
2466
2467         dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
2468         dev_info->speed_capa |= ETH_LINK_SPEED_100M;
2469
2470         /* Driver-preferred Rx/Tx parameters */
2471         dev_info->default_rxportconf.burst_size = 32;
2472         dev_info->default_txportconf.burst_size = 32;
2473         dev_info->default_rxportconf.nb_queues = 1;
2474         dev_info->default_txportconf.nb_queues = 1;
2475         dev_info->default_rxportconf.ring_size = 256;
2476         dev_info->default_txportconf.ring_size = 256;
2477
2478         return 0;
2479 }
2480
2481 const uint32_t *
2482 txgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev)
2483 {
2484         if (dev->rx_pkt_burst == txgbe_recv_pkts ||
2485             dev->rx_pkt_burst == txgbe_recv_pkts_lro_single_alloc ||
2486             dev->rx_pkt_burst == txgbe_recv_pkts_lro_bulk_alloc ||
2487             dev->rx_pkt_burst == txgbe_recv_pkts_bulk_alloc)
2488                 return txgbe_get_supported_ptypes();
2489
2490         return NULL;
2491 }
2492
2493 void
2494 txgbe_dev_setup_link_alarm_handler(void *param)
2495 {
2496         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2497         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2498         struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);
2499         u32 speed;
2500         bool autoneg = false;
2501
2502         speed = hw->phy.autoneg_advertised;
2503         if (!speed)
2504                 hw->mac.get_link_capabilities(hw, &speed, &autoneg);
2505
2506         hw->mac.setup_link(hw, speed, true);
2507
2508         intr->flags &= ~TXGBE_FLAG_NEED_LINK_CONFIG;
2509 }
2510
2511 /* return 0 means link status changed, -1 means not changed */
2512 int
2513 txgbe_dev_link_update_share(struct rte_eth_dev *dev,
2514                             int wait_to_complete)
2515 {
2516         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2517         struct rte_eth_link link;
2518         u32 link_speed = TXGBE_LINK_SPEED_UNKNOWN;
2519         struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);
2520         bool link_up;
2521         int err;
2522         int wait = 1;
2523
2524         memset(&link, 0, sizeof(link));
2525         link.link_status = ETH_LINK_DOWN;
2526         link.link_speed = ETH_SPEED_NUM_NONE;
2527         link.link_duplex = ETH_LINK_HALF_DUPLEX;
2528         link.link_autoneg = ETH_LINK_AUTONEG;
2529
2530         hw->mac.get_link_status = true;
2531
2532         if (intr->flags & TXGBE_FLAG_NEED_LINK_CONFIG)
2533                 return rte_eth_linkstatus_set(dev, &link);
2534
2535         /* check if it needs to wait to complete, if lsc interrupt is enabled */
2536         if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
2537                 wait = 0;
2538
2539         err = hw->mac.check_link(hw, &link_speed, &link_up, wait);
2540
2541         if (err != 0) {
2542                 link.link_speed = ETH_SPEED_NUM_100M;
2543                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
2544                 return rte_eth_linkstatus_set(dev, &link);
2545         }
2546
2547         if (link_up == 0) {
2548                 if (hw->phy.media_type == txgbe_media_type_fiber) {
2549                         intr->flags |= TXGBE_FLAG_NEED_LINK_CONFIG;
2550                         rte_eal_alarm_set(10,
2551                                 txgbe_dev_setup_link_alarm_handler, dev);
2552                 }
2553                 return rte_eth_linkstatus_set(dev, &link);
2554         }
2555
2556         intr->flags &= ~TXGBE_FLAG_NEED_LINK_CONFIG;
2557         link.link_status = ETH_LINK_UP;
2558         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2559
2560         switch (link_speed) {
2561         default:
2562         case TXGBE_LINK_SPEED_UNKNOWN:
2563                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
2564                 link.link_speed = ETH_SPEED_NUM_100M;
2565                 break;
2566
2567         case TXGBE_LINK_SPEED_100M_FULL:
2568                 link.link_speed = ETH_SPEED_NUM_100M;
2569                 break;
2570
2571         case TXGBE_LINK_SPEED_1GB_FULL:
2572                 link.link_speed = ETH_SPEED_NUM_1G;
2573                 break;
2574
2575         case TXGBE_LINK_SPEED_2_5GB_FULL:
2576                 link.link_speed = ETH_SPEED_NUM_2_5G;
2577                 break;
2578
2579         case TXGBE_LINK_SPEED_5GB_FULL:
2580                 link.link_speed = ETH_SPEED_NUM_5G;
2581                 break;
2582
2583         case TXGBE_LINK_SPEED_10GB_FULL:
2584                 link.link_speed = ETH_SPEED_NUM_10G;
2585                 break;
2586         }
2587
2588         return rte_eth_linkstatus_set(dev, &link);
2589 }
2590
2591 static int
2592 txgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
2593 {
2594         return txgbe_dev_link_update_share(dev, wait_to_complete);
2595 }
2596
2597 static int
2598 txgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
2599 {
2600         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2601         uint32_t fctrl;
2602
2603         fctrl = rd32(hw, TXGBE_PSRCTL);
2604         fctrl |= (TXGBE_PSRCTL_UCP | TXGBE_PSRCTL_MCP);
2605         wr32(hw, TXGBE_PSRCTL, fctrl);
2606
2607         return 0;
2608 }
2609
2610 static int
2611 txgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
2612 {
2613         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2614         uint32_t fctrl;
2615
2616         fctrl = rd32(hw, TXGBE_PSRCTL);
2617         fctrl &= (~TXGBE_PSRCTL_UCP);
2618         if (dev->data->all_multicast == 1)
2619                 fctrl |= TXGBE_PSRCTL_MCP;
2620         else
2621                 fctrl &= (~TXGBE_PSRCTL_MCP);
2622         wr32(hw, TXGBE_PSRCTL, fctrl);
2623
2624         return 0;
2625 }
2626
2627 static int
2628 txgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
2629 {
2630         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2631         uint32_t fctrl;
2632
2633         fctrl = rd32(hw, TXGBE_PSRCTL);
2634         fctrl |= TXGBE_PSRCTL_MCP;
2635         wr32(hw, TXGBE_PSRCTL, fctrl);
2636
2637         return 0;
2638 }
2639
2640 static int
2641 txgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
2642 {
2643         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2644         uint32_t fctrl;
2645
2646         if (dev->data->promiscuous == 1)
2647                 return 0; /* must remain in all_multicast mode */
2648
2649         fctrl = rd32(hw, TXGBE_PSRCTL);
2650         fctrl &= (~TXGBE_PSRCTL_MCP);
2651         wr32(hw, TXGBE_PSRCTL, fctrl);
2652
2653         return 0;
2654 }
2655
2656 /**
2657  * It clears the interrupt causes and enables the interrupt.
2658  * It will be called once only during nic initialized.
2659  *
2660  * @param dev
2661  *  Pointer to struct rte_eth_dev.
2662  * @param on
2663  *  Enable or Disable.
2664  *
2665  * @return
2666  *  - On success, zero.
2667  *  - On failure, a negative value.
2668  */
2669 static int
2670 txgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on)
2671 {
2672         struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);
2673
2674         txgbe_dev_link_status_print(dev);
2675         if (on)
2676                 intr->mask_misc |= TXGBE_ICRMISC_LSC;
2677         else
2678                 intr->mask_misc &= ~TXGBE_ICRMISC_LSC;
2679
2680         return 0;
2681 }
2682
2683 /**
2684  * It clears the interrupt causes and enables the interrupt.
2685  * It will be called once only during nic initialized.
2686  *
2687  * @param dev
2688  *  Pointer to struct rte_eth_dev.
2689  *
2690  * @return
2691  *  - On success, zero.
2692  *  - On failure, a negative value.
2693  */
2694 static int
2695 txgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
2696 {
2697         struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);
2698
2699         intr->mask[0] |= TXGBE_ICR_MASK;
2700         intr->mask[1] |= TXGBE_ICR_MASK;
2701
2702         return 0;
2703 }
2704
2705 /**
2706  * It clears the interrupt causes and enables the interrupt.
2707  * It will be called once only during nic initialized.
2708  *
2709  * @param dev
2710  *  Pointer to struct rte_eth_dev.
2711  *
2712  * @return
2713  *  - On success, zero.
2714  *  - On failure, a negative value.
2715  */
2716 static int
2717 txgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev)
2718 {
2719         struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);
2720
2721         intr->mask_misc |= TXGBE_ICRMISC_LNKSEC;
2722
2723         return 0;
2724 }
2725
2726 /*
2727  * It reads ICR and sets flag (TXGBE_ICRMISC_LSC) for the link_update.
2728  *
2729  * @param dev
2730  *  Pointer to struct rte_eth_dev.
2731  *
2732  * @return
2733  *  - On success, zero.
2734  *  - On failure, a negative value.
2735  */
2736 static int
2737 txgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
2738 {
2739         uint32_t eicr;
2740         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2741         struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);
2742
2743         /* clear all cause mask */
2744         txgbe_disable_intr(hw);
2745
2746         /* read-on-clear nic registers here */
2747         eicr = ((u32 *)hw->isb_mem)[TXGBE_ISB_MISC];
2748         PMD_DRV_LOG(DEBUG, "eicr %x", eicr);
2749
2750         intr->flags = 0;
2751
2752         /* set flag for async link update */
2753         if (eicr & TXGBE_ICRMISC_LSC)
2754                 intr->flags |= TXGBE_FLAG_NEED_LINK_UPDATE;
2755
2756         if (eicr & TXGBE_ICRMISC_VFMBX)
2757                 intr->flags |= TXGBE_FLAG_MAILBOX;
2758
2759         if (eicr & TXGBE_ICRMISC_LNKSEC)
2760                 intr->flags |= TXGBE_FLAG_MACSEC;
2761
2762         if (eicr & TXGBE_ICRMISC_GPIO)
2763                 intr->flags |= TXGBE_FLAG_PHY_INTERRUPT;
2764
2765         return 0;
2766 }
2767
2768 /**
2769  * It gets and then prints the link status.
2770  *
2771  * @param dev
2772  *  Pointer to struct rte_eth_dev.
2773  *
2774  * @return
2775  *  - On success, zero.
2776  *  - On failure, a negative value.
2777  */
2778 static void
2779 txgbe_dev_link_status_print(struct rte_eth_dev *dev)
2780 {
2781         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2782         struct rte_eth_link link;
2783
2784         rte_eth_linkstatus_get(dev, &link);
2785
2786         if (link.link_status) {
2787                 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
2788                                         (int)(dev->data->port_id),
2789                                         (unsigned int)link.link_speed,
2790                         link.link_duplex == ETH_LINK_FULL_DUPLEX ?
2791                                         "full-duplex" : "half-duplex");
2792         } else {
2793                 PMD_INIT_LOG(INFO, " Port %d: Link Down",
2794                                 (int)(dev->data->port_id));
2795         }
2796         PMD_INIT_LOG(DEBUG, "PCI Address: " PCI_PRI_FMT,
2797                                 pci_dev->addr.domain,
2798                                 pci_dev->addr.bus,
2799                                 pci_dev->addr.devid,
2800                                 pci_dev->addr.function);
2801 }
2802
2803 /*
2804  * It executes link_update after knowing an interrupt occurred.
2805  *
2806  * @param dev
2807  *  Pointer to struct rte_eth_dev.
2808  *
2809  * @return
2810  *  - On success, zero.
2811  *  - On failure, a negative value.
2812  */
2813 static int
2814 txgbe_dev_interrupt_action(struct rte_eth_dev *dev,
2815                            struct rte_intr_handle *intr_handle)
2816 {
2817         struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);
2818         int64_t timeout;
2819         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2820
2821         PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
2822
2823         if (intr->flags & TXGBE_FLAG_MAILBOX) {
2824                 txgbe_pf_mbx_process(dev);
2825                 intr->flags &= ~TXGBE_FLAG_MAILBOX;
2826         }
2827
2828         if (intr->flags & TXGBE_FLAG_PHY_INTERRUPT) {
2829                 hw->phy.handle_lasi(hw);
2830                 intr->flags &= ~TXGBE_FLAG_PHY_INTERRUPT;
2831         }
2832
2833         if (intr->flags & TXGBE_FLAG_NEED_LINK_UPDATE) {
2834                 struct rte_eth_link link;
2835
2836                 /*get the link status before link update, for predicting later*/
2837                 rte_eth_linkstatus_get(dev, &link);
2838
2839                 txgbe_dev_link_update(dev, 0);
2840
2841                 /* likely to up */
2842                 if (!link.link_status)
2843                         /* handle it 1 sec later, wait it being stable */
2844                         timeout = TXGBE_LINK_UP_CHECK_TIMEOUT;
2845                 /* likely to down */
2846                 else
2847                         /* handle it 4 sec later, wait it being stable */
2848                         timeout = TXGBE_LINK_DOWN_CHECK_TIMEOUT;
2849
2850                 txgbe_dev_link_status_print(dev);
2851                 if (rte_eal_alarm_set(timeout * 1000,
2852                                       txgbe_dev_interrupt_delayed_handler,
2853                                       (void *)dev) < 0) {
2854                         PMD_DRV_LOG(ERR, "Error setting alarm");
2855                 } else {
2856                         /* remember original mask */
2857                         intr->mask_misc_orig = intr->mask_misc;
2858                         /* only disable lsc interrupt */
2859                         intr->mask_misc &= ~TXGBE_ICRMISC_LSC;
2860                 }
2861         }
2862
2863         PMD_DRV_LOG(DEBUG, "enable intr immediately");
2864         txgbe_enable_intr(dev);
2865         rte_intr_enable(intr_handle);
2866
2867         return 0;
2868 }
2869
2870 /**
2871  * Interrupt handler which shall be registered for alarm callback for delayed
2872  * handling specific interrupt to wait for the stable nic state. As the
2873  * NIC interrupt state is not stable for txgbe after link is just down,
2874  * it needs to wait 4 seconds to get the stable status.
2875  *
2876  * @param handle
2877  *  Pointer to interrupt handle.
2878  * @param param
2879  *  The address of parameter (struct rte_eth_dev *) registered before.
2880  *
2881  * @return
2882  *  void
2883  */
2884 static void
2885 txgbe_dev_interrupt_delayed_handler(void *param)
2886 {
2887         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2888         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2889         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2890         struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);
2891         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2892         uint32_t eicr;
2893
2894         txgbe_disable_intr(hw);
2895
2896         eicr = ((u32 *)hw->isb_mem)[TXGBE_ISB_MISC];
2897         if (eicr & TXGBE_ICRMISC_VFMBX)
2898                 txgbe_pf_mbx_process(dev);
2899
2900         if (intr->flags & TXGBE_FLAG_PHY_INTERRUPT) {
2901                 hw->phy.handle_lasi(hw);
2902                 intr->flags &= ~TXGBE_FLAG_PHY_INTERRUPT;
2903         }
2904
2905         if (intr->flags & TXGBE_FLAG_NEED_LINK_UPDATE) {
2906                 txgbe_dev_link_update(dev, 0);
2907                 intr->flags &= ~TXGBE_FLAG_NEED_LINK_UPDATE;
2908                 txgbe_dev_link_status_print(dev);
2909                 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC,
2910                                               NULL);
2911         }
2912
2913         if (intr->flags & TXGBE_FLAG_MACSEC) {
2914                 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_MACSEC,
2915                                               NULL);
2916                 intr->flags &= ~TXGBE_FLAG_MACSEC;
2917         }
2918
2919         /* restore original mask */
2920         intr->mask_misc = intr->mask_misc_orig;
2921         intr->mask_misc_orig = 0;
2922
2923         PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
2924         txgbe_enable_intr(dev);
2925         rte_intr_enable(intr_handle);
2926 }
2927
2928 /**
2929  * Interrupt handler triggered by NIC  for handling
2930  * specific interrupt.
2931  *
2932  * @param handle
2933  *  Pointer to interrupt handle.
2934  * @param param
2935  *  The address of parameter (struct rte_eth_dev *) registered before.
2936  *
2937  * @return
2938  *  void
2939  */
2940 static void
2941 txgbe_dev_interrupt_handler(void *param)
2942 {
2943         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2944
2945         txgbe_dev_interrupt_get_status(dev);
2946         txgbe_dev_interrupt_action(dev, dev->intr_handle);
2947 }
2948
2949 static int
2950 txgbe_dev_led_on(struct rte_eth_dev *dev)
2951 {
2952         struct txgbe_hw *hw;
2953
2954         hw = TXGBE_DEV_HW(dev);
2955         return txgbe_led_on(hw, 4) == 0 ? 0 : -ENOTSUP;
2956 }
2957
2958 static int
2959 txgbe_dev_led_off(struct rte_eth_dev *dev)
2960 {
2961         struct txgbe_hw *hw;
2962
2963         hw = TXGBE_DEV_HW(dev);
2964         return txgbe_led_off(hw, 4) == 0 ? 0 : -ENOTSUP;
2965 }
2966
2967 static int
2968 txgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2969 {
2970         struct txgbe_hw *hw;
2971         uint32_t mflcn_reg;
2972         uint32_t fccfg_reg;
2973         int rx_pause;
2974         int tx_pause;
2975
2976         hw = TXGBE_DEV_HW(dev);
2977
2978         fc_conf->pause_time = hw->fc.pause_time;
2979         fc_conf->high_water = hw->fc.high_water[0];
2980         fc_conf->low_water = hw->fc.low_water[0];
2981         fc_conf->send_xon = hw->fc.send_xon;
2982         fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
2983
2984         /*
2985          * Return rx_pause status according to actual setting of
2986          * RXFCCFG register.
2987          */
2988         mflcn_reg = rd32(hw, TXGBE_RXFCCFG);
2989         if (mflcn_reg & (TXGBE_RXFCCFG_FC | TXGBE_RXFCCFG_PFC))
2990                 rx_pause = 1;
2991         else
2992                 rx_pause = 0;
2993
2994         /*
2995          * Return tx_pause status according to actual setting of
2996          * TXFCCFG register.
2997          */
2998         fccfg_reg = rd32(hw, TXGBE_TXFCCFG);
2999         if (fccfg_reg & (TXGBE_TXFCCFG_FC | TXGBE_TXFCCFG_PFC))
3000                 tx_pause = 1;
3001         else
3002                 tx_pause = 0;
3003
3004         if (rx_pause && tx_pause)
3005                 fc_conf->mode = RTE_FC_FULL;
3006         else if (rx_pause)
3007                 fc_conf->mode = RTE_FC_RX_PAUSE;
3008         else if (tx_pause)
3009                 fc_conf->mode = RTE_FC_TX_PAUSE;
3010         else
3011                 fc_conf->mode = RTE_FC_NONE;
3012
3013         return 0;
3014 }
3015
3016 static int
3017 txgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3018 {
3019         struct txgbe_hw *hw;
3020         int err;
3021         uint32_t rx_buf_size;
3022         uint32_t max_high_water;
3023         enum txgbe_fc_mode rte_fcmode_2_txgbe_fcmode[] = {
3024                 txgbe_fc_none,
3025                 txgbe_fc_rx_pause,
3026                 txgbe_fc_tx_pause,
3027                 txgbe_fc_full
3028         };
3029
3030         PMD_INIT_FUNC_TRACE();
3031
3032         hw = TXGBE_DEV_HW(dev);
3033         rx_buf_size = rd32(hw, TXGBE_PBRXSIZE(0));
3034         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
3035
3036         /*
3037          * At least reserve one Ethernet frame for watermark
3038          * high_water/low_water in kilo bytes for txgbe
3039          */
3040         max_high_water = (rx_buf_size - RTE_ETHER_MAX_LEN) >> 10;
3041         if (fc_conf->high_water > max_high_water ||
3042             fc_conf->high_water < fc_conf->low_water) {
3043                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
3044                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
3045                 return -EINVAL;
3046         }
3047
3048         hw->fc.requested_mode = rte_fcmode_2_txgbe_fcmode[fc_conf->mode];
3049         hw->fc.pause_time     = fc_conf->pause_time;
3050         hw->fc.high_water[0]  = fc_conf->high_water;
3051         hw->fc.low_water[0]   = fc_conf->low_water;
3052         hw->fc.send_xon       = fc_conf->send_xon;
3053         hw->fc.disable_fc_autoneg = !fc_conf->autoneg;
3054
3055         err = txgbe_fc_enable(hw);
3056
3057         /* Not negotiated is not an error case */
3058         if (err == 0 || err == TXGBE_ERR_FC_NOT_NEGOTIATED) {
3059                 wr32m(hw, TXGBE_MACRXFLT, TXGBE_MACRXFLT_CTL_MASK,
3060                       (fc_conf->mac_ctrl_frame_fwd
3061                        ? TXGBE_MACRXFLT_CTL_NOPS : TXGBE_MACRXFLT_CTL_DROP));
3062                 txgbe_flush(hw);
3063
3064                 return 0;
3065         }
3066
3067         PMD_INIT_LOG(ERR, "txgbe_fc_enable = 0x%x", err);
3068         return -EIO;
3069 }
3070
3071 static int
3072 txgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
3073                 struct rte_eth_pfc_conf *pfc_conf)
3074 {
3075         int err;
3076         uint32_t rx_buf_size;
3077         uint32_t max_high_water;
3078         uint8_t tc_num;
3079         uint8_t  map[TXGBE_DCB_UP_MAX] = { 0 };
3080         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3081         struct txgbe_dcb_config *dcb_config = TXGBE_DEV_DCB_CONFIG(dev);
3082
3083         enum txgbe_fc_mode rte_fcmode_2_txgbe_fcmode[] = {
3084                 txgbe_fc_none,
3085                 txgbe_fc_rx_pause,
3086                 txgbe_fc_tx_pause,
3087                 txgbe_fc_full
3088         };
3089
3090         PMD_INIT_FUNC_TRACE();
3091
3092         txgbe_dcb_unpack_map_cee(dcb_config, TXGBE_DCB_RX_CONFIG, map);
3093         tc_num = map[pfc_conf->priority];
3094         rx_buf_size = rd32(hw, TXGBE_PBRXSIZE(tc_num));
3095         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
3096         /*
3097          * At least reserve one Ethernet frame for watermark
3098          * high_water/low_water in kilo bytes for txgbe
3099          */
3100         max_high_water = (rx_buf_size - RTE_ETHER_MAX_LEN) >> 10;
3101         if (pfc_conf->fc.high_water > max_high_water ||
3102             pfc_conf->fc.high_water <= pfc_conf->fc.low_water) {
3103                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
3104                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
3105                 return -EINVAL;
3106         }
3107
3108         hw->fc.requested_mode = rte_fcmode_2_txgbe_fcmode[pfc_conf->fc.mode];
3109         hw->fc.pause_time = pfc_conf->fc.pause_time;
3110         hw->fc.send_xon = pfc_conf->fc.send_xon;
3111         hw->fc.low_water[tc_num] =  pfc_conf->fc.low_water;
3112         hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
3113
3114         err = txgbe_dcb_pfc_enable(hw, tc_num);
3115
3116         /* Not negotiated is not an error case */
3117         if (err == 0 || err == TXGBE_ERR_FC_NOT_NEGOTIATED)
3118                 return 0;
3119
3120         PMD_INIT_LOG(ERR, "txgbe_dcb_pfc_enable = 0x%x", err);
3121         return -EIO;
3122 }
3123
3124 int
3125 txgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
3126                           struct rte_eth_rss_reta_entry64 *reta_conf,
3127                           uint16_t reta_size)
3128 {
3129         uint8_t i, j, mask;
3130         uint32_t reta;
3131         uint16_t idx, shift;
3132         struct txgbe_adapter *adapter = TXGBE_DEV_ADAPTER(dev);
3133         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3134
3135         PMD_INIT_FUNC_TRACE();
3136
3137         if (!txgbe_rss_update_sp(hw->mac.type)) {
3138                 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this "
3139                         "NIC.");
3140                 return -ENOTSUP;
3141         }
3142
3143         if (reta_size != ETH_RSS_RETA_SIZE_128) {
3144                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3145                         "(%d) doesn't match the number hardware can supported "
3146                         "(%d)", reta_size, ETH_RSS_RETA_SIZE_128);
3147                 return -EINVAL;
3148         }
3149
3150         for (i = 0; i < reta_size; i += 4) {
3151                 idx = i / RTE_RETA_GROUP_SIZE;
3152                 shift = i % RTE_RETA_GROUP_SIZE;
3153                 mask = (uint8_t)RS64(reta_conf[idx].mask, shift, 0xF);
3154                 if (!mask)
3155                         continue;
3156
3157                 reta = rd32a(hw, TXGBE_REG_RSSTBL, i >> 2);
3158                 for (j = 0; j < 4; j++) {
3159                         if (RS8(mask, j, 0x1)) {
3160                                 reta  &= ~(MS32(8 * j, 0xFF));
3161                                 reta |= LS32(reta_conf[idx].reta[shift + j],
3162                                                 8 * j, 0xFF);
3163                         }
3164                 }
3165                 wr32a(hw, TXGBE_REG_RSSTBL, i >> 2, reta);
3166         }
3167         adapter->rss_reta_updated = 1;
3168
3169         return 0;
3170 }
3171
3172 int
3173 txgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
3174                          struct rte_eth_rss_reta_entry64 *reta_conf,
3175                          uint16_t reta_size)
3176 {
3177         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3178         uint8_t i, j, mask;
3179         uint32_t reta;
3180         uint16_t idx, shift;
3181
3182         PMD_INIT_FUNC_TRACE();
3183
3184         if (reta_size != ETH_RSS_RETA_SIZE_128) {
3185                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3186                         "(%d) doesn't match the number hardware can supported "
3187                         "(%d)", reta_size, ETH_RSS_RETA_SIZE_128);
3188                 return -EINVAL;
3189         }
3190
3191         for (i = 0; i < reta_size; i += 4) {
3192                 idx = i / RTE_RETA_GROUP_SIZE;
3193                 shift = i % RTE_RETA_GROUP_SIZE;
3194                 mask = (uint8_t)RS64(reta_conf[idx].mask, shift, 0xF);
3195                 if (!mask)
3196                         continue;
3197
3198                 reta = rd32a(hw, TXGBE_REG_RSSTBL, i >> 2);
3199                 for (j = 0; j < 4; j++) {
3200                         if (RS8(mask, j, 0x1))
3201                                 reta_conf[idx].reta[shift + j] =
3202                                         (uint16_t)RS32(reta, 8 * j, 0xFF);
3203                 }
3204         }
3205
3206         return 0;
3207 }
3208
3209 static int
3210 txgbe_add_rar(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
3211                                 uint32_t index, uint32_t pool)
3212 {
3213         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3214         uint32_t enable_addr = 1;
3215
3216         return txgbe_set_rar(hw, index, mac_addr->addr_bytes,
3217                              pool, enable_addr);
3218 }
3219
3220 static void
3221 txgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
3222 {
3223         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3224
3225         txgbe_clear_rar(hw, index);
3226 }
3227
3228 static int
3229 txgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *addr)
3230 {
3231         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3232
3233         txgbe_remove_rar(dev, 0);
3234         txgbe_add_rar(dev, addr, 0, pci_dev->max_vfs);
3235
3236         return 0;
3237 }
3238
3239 static int
3240 txgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
3241 {
3242         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3243         struct rte_eth_dev_info dev_info;
3244         uint32_t frame_size = mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN;
3245         struct rte_eth_dev_data *dev_data = dev->data;
3246         int ret;
3247
3248         ret = txgbe_dev_info_get(dev, &dev_info);
3249         if (ret != 0)
3250                 return ret;
3251
3252         /* check that mtu is within the allowed range */
3253         if (mtu < RTE_ETHER_MIN_MTU || frame_size > dev_info.max_rx_pktlen)
3254                 return -EINVAL;
3255
3256         /* If device is started, refuse mtu that requires the support of
3257          * scattered packets when this feature has not been enabled before.
3258          */
3259         if (dev_data->dev_started && !dev_data->scattered_rx &&
3260             (frame_size + 2 * TXGBE_VLAN_TAG_SIZE >
3261              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
3262                 PMD_INIT_LOG(ERR, "Stop port first.");
3263                 return -EINVAL;
3264         }
3265
3266         /* update max frame size */
3267         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
3268
3269         if (hw->mode)
3270                 wr32m(hw, TXGBE_FRMSZ, TXGBE_FRMSZ_MAX_MASK,
3271                         TXGBE_FRAME_SIZE_MAX);
3272         else
3273                 wr32m(hw, TXGBE_FRMSZ, TXGBE_FRMSZ_MAX_MASK,
3274                         TXGBE_FRMSZ_MAX(frame_size));
3275
3276         return 0;
3277 }
3278
3279 static uint32_t
3280 txgbe_uta_vector(struct txgbe_hw *hw, struct rte_ether_addr *uc_addr)
3281 {
3282         uint32_t vector = 0;
3283
3284         switch (hw->mac.mc_filter_type) {
3285         case 0:   /* use bits [47:36] of the address */
3286                 vector = ((uc_addr->addr_bytes[4] >> 4) |
3287                         (((uint16_t)uc_addr->addr_bytes[5]) << 4));
3288                 break;
3289         case 1:   /* use bits [46:35] of the address */
3290                 vector = ((uc_addr->addr_bytes[4] >> 3) |
3291                         (((uint16_t)uc_addr->addr_bytes[5]) << 5));
3292                 break;
3293         case 2:   /* use bits [45:34] of the address */
3294                 vector = ((uc_addr->addr_bytes[4] >> 2) |
3295                         (((uint16_t)uc_addr->addr_bytes[5]) << 6));
3296                 break;
3297         case 3:   /* use bits [43:32] of the address */
3298                 vector = ((uc_addr->addr_bytes[4]) |
3299                         (((uint16_t)uc_addr->addr_bytes[5]) << 8));
3300                 break;
3301         default:  /* Invalid mc_filter_type */
3302                 break;
3303         }
3304
3305         /* vector can only be 12-bits or boundary will be exceeded */
3306         vector &= 0xFFF;
3307         return vector;
3308 }
3309
3310 static int
3311 txgbe_uc_hash_table_set(struct rte_eth_dev *dev,
3312                         struct rte_ether_addr *mac_addr, uint8_t on)
3313 {
3314         uint32_t vector;
3315         uint32_t uta_idx;
3316         uint32_t reg_val;
3317         uint32_t uta_mask;
3318         uint32_t psrctl;
3319
3320         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3321         struct txgbe_uta_info *uta_info = TXGBE_DEV_UTA_INFO(dev);
3322
3323         /* The UTA table only exists on pf hardware */
3324         if (hw->mac.type < txgbe_mac_raptor)
3325                 return -ENOTSUP;
3326
3327         vector = txgbe_uta_vector(hw, mac_addr);
3328         uta_idx = (vector >> 5) & 0x7F;
3329         uta_mask = 0x1UL << (vector & 0x1F);
3330
3331         if (!!on == !!(uta_info->uta_shadow[uta_idx] & uta_mask))
3332                 return 0;
3333
3334         reg_val = rd32(hw, TXGBE_UCADDRTBL(uta_idx));
3335         if (on) {
3336                 uta_info->uta_in_use++;
3337                 reg_val |= uta_mask;
3338                 uta_info->uta_shadow[uta_idx] |= uta_mask;
3339         } else {
3340                 uta_info->uta_in_use--;
3341                 reg_val &= ~uta_mask;
3342                 uta_info->uta_shadow[uta_idx] &= ~uta_mask;
3343         }
3344
3345         wr32(hw, TXGBE_UCADDRTBL(uta_idx), reg_val);
3346
3347         psrctl = rd32(hw, TXGBE_PSRCTL);
3348         if (uta_info->uta_in_use > 0)
3349                 psrctl |= TXGBE_PSRCTL_UCHFENA;
3350         else
3351                 psrctl &= ~TXGBE_PSRCTL_UCHFENA;
3352
3353         psrctl &= ~TXGBE_PSRCTL_ADHF12_MASK;
3354         psrctl |= TXGBE_PSRCTL_ADHF12(hw->mac.mc_filter_type);
3355         wr32(hw, TXGBE_PSRCTL, psrctl);
3356
3357         return 0;
3358 }
3359
3360 static int
3361 txgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
3362 {
3363         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3364         struct txgbe_uta_info *uta_info = TXGBE_DEV_UTA_INFO(dev);
3365         uint32_t psrctl;
3366         int i;
3367
3368         /* The UTA table only exists on pf hardware */
3369         if (hw->mac.type < txgbe_mac_raptor)
3370                 return -ENOTSUP;
3371
3372         if (on) {
3373                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
3374                         uta_info->uta_shadow[i] = ~0;
3375                         wr32(hw, TXGBE_UCADDRTBL(i), ~0);
3376                 }
3377         } else {
3378                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
3379                         uta_info->uta_shadow[i] = 0;
3380                         wr32(hw, TXGBE_UCADDRTBL(i), 0);
3381                 }
3382         }
3383
3384         psrctl = rd32(hw, TXGBE_PSRCTL);
3385         if (on)
3386                 psrctl |= TXGBE_PSRCTL_UCHFENA;
3387         else
3388                 psrctl &= ~TXGBE_PSRCTL_UCHFENA;
3389
3390         psrctl &= ~TXGBE_PSRCTL_ADHF12_MASK;
3391         psrctl |= TXGBE_PSRCTL_ADHF12(hw->mac.mc_filter_type);
3392         wr32(hw, TXGBE_PSRCTL, psrctl);
3393
3394         return 0;
3395 }
3396
3397 uint32_t
3398 txgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
3399 {
3400         uint32_t new_val = orig_val;
3401
3402         if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
3403                 new_val |= TXGBE_POOLETHCTL_UTA;
3404         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
3405                 new_val |= TXGBE_POOLETHCTL_MCHA;
3406         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
3407                 new_val |= TXGBE_POOLETHCTL_UCHA;
3408         if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
3409                 new_val |= TXGBE_POOLETHCTL_BCA;
3410         if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
3411                 new_val |= TXGBE_POOLETHCTL_MCP;
3412
3413         return new_val;
3414 }
3415
3416 static int
3417 txgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
3418 {
3419         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3420         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3421         uint32_t mask;
3422         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3423
3424         if (queue_id < 32) {
3425                 mask = rd32(hw, TXGBE_IMS(0));
3426                 mask &= (1 << queue_id);
3427                 wr32(hw, TXGBE_IMS(0), mask);
3428         } else if (queue_id < 64) {
3429                 mask = rd32(hw, TXGBE_IMS(1));
3430                 mask &= (1 << (queue_id - 32));
3431                 wr32(hw, TXGBE_IMS(1), mask);
3432         }
3433         rte_intr_enable(intr_handle);
3434
3435         return 0;
3436 }
3437
3438 static int
3439 txgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
3440 {
3441         uint32_t mask;
3442         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3443
3444         if (queue_id < 32) {
3445                 mask = rd32(hw, TXGBE_IMS(0));
3446                 mask &= ~(1 << queue_id);
3447                 wr32(hw, TXGBE_IMS(0), mask);
3448         } else if (queue_id < 64) {
3449                 mask = rd32(hw, TXGBE_IMS(1));
3450                 mask &= ~(1 << (queue_id - 32));
3451                 wr32(hw, TXGBE_IMS(1), mask);
3452         }
3453
3454         return 0;
3455 }
3456
3457 /**
3458  * set the IVAR registers, mapping interrupt causes to vectors
3459  * @param hw
3460  *  pointer to txgbe_hw struct
3461  * @direction
3462  *  0 for Rx, 1 for Tx, -1 for other causes
3463  * @queue
3464  *  queue to map the corresponding interrupt to
3465  * @msix_vector
3466  *  the vector to map to the corresponding queue
3467  */
3468 void
3469 txgbe_set_ivar_map(struct txgbe_hw *hw, int8_t direction,
3470                    uint8_t queue, uint8_t msix_vector)
3471 {
3472         uint32_t tmp, idx;
3473
3474         if (direction == -1) {
3475                 /* other causes */
3476                 msix_vector |= TXGBE_IVARMISC_VLD;
3477                 idx = 0;
3478                 tmp = rd32(hw, TXGBE_IVARMISC);
3479                 tmp &= ~(0xFF << idx);
3480                 tmp |= (msix_vector << idx);
3481                 wr32(hw, TXGBE_IVARMISC, tmp);
3482         } else {
3483                 /* rx or tx causes */
3484                 /* Workround for ICR lost */
3485                 idx = ((16 * (queue & 1)) + (8 * direction));
3486                 tmp = rd32(hw, TXGBE_IVAR(queue >> 1));
3487                 tmp &= ~(0xFF << idx);
3488                 tmp |= (msix_vector << idx);
3489                 wr32(hw, TXGBE_IVAR(queue >> 1), tmp);
3490         }
3491 }
3492
3493 /**
3494  * Sets up the hardware to properly generate MSI-X interrupts
3495  * @hw
3496  *  board private structure
3497  */
3498 static void
3499 txgbe_configure_msix(struct rte_eth_dev *dev)
3500 {
3501         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3502         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3503         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3504         uint32_t queue_id, base = TXGBE_MISC_VEC_ID;
3505         uint32_t vec = TXGBE_MISC_VEC_ID;
3506         uint32_t gpie;
3507
3508         /* won't configure msix register if no mapping is done
3509          * between intr vector and event fd
3510          * but if misx has been enabled already, need to configure
3511          * auto clean, auto mask and throttling.
3512          */
3513         gpie = rd32(hw, TXGBE_GPIE);
3514         if (!rte_intr_dp_is_en(intr_handle) &&
3515             !(gpie & TXGBE_GPIE_MSIX))
3516                 return;
3517
3518         if (rte_intr_allow_others(intr_handle)) {
3519                 base = TXGBE_RX_VEC_START;
3520                 vec = base;
3521         }
3522
3523         /* setup GPIE for MSI-x mode */
3524         gpie = rd32(hw, TXGBE_GPIE);
3525         gpie |= TXGBE_GPIE_MSIX;
3526         wr32(hw, TXGBE_GPIE, gpie);
3527
3528         /* Populate the IVAR table and set the ITR values to the
3529          * corresponding register.
3530          */
3531         if (rte_intr_dp_is_en(intr_handle)) {
3532                 for (queue_id = 0; queue_id < dev->data->nb_rx_queues;
3533                         queue_id++) {
3534                         /* by default, 1:1 mapping */
3535                         txgbe_set_ivar_map(hw, 0, queue_id, vec);
3536                         intr_handle->intr_vec[queue_id] = vec;
3537                         if (vec < base + intr_handle->nb_efd - 1)
3538                                 vec++;
3539                 }
3540
3541                 txgbe_set_ivar_map(hw, -1, 1, TXGBE_MISC_VEC_ID);
3542         }
3543         wr32(hw, TXGBE_ITR(TXGBE_MISC_VEC_ID),
3544                         TXGBE_ITR_IVAL_10G(TXGBE_QUEUE_ITR_INTERVAL_DEFAULT)
3545                         | TXGBE_ITR_WRDSA);
3546 }
3547
3548 int
3549 txgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
3550                            uint16_t queue_idx, uint16_t tx_rate)
3551 {
3552         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3553         uint32_t bcnrc_val;
3554
3555         if (queue_idx >= hw->mac.max_tx_queues)
3556                 return -EINVAL;
3557
3558         if (tx_rate != 0) {
3559                 bcnrc_val = TXGBE_ARBTXRATE_MAX(tx_rate);
3560                 bcnrc_val |= TXGBE_ARBTXRATE_MIN(tx_rate / 2);
3561         } else {
3562                 bcnrc_val = 0;
3563         }
3564
3565         /*
3566          * Set global transmit compensation time to the MMW_SIZE in ARBTXMMW
3567          * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported.
3568          */
3569         wr32(hw, TXGBE_ARBTXMMW, 0x14);
3570
3571         /* Set ARBTXRATE of queue X */
3572         wr32(hw, TXGBE_ARBPOOLIDX, queue_idx);
3573         wr32(hw, TXGBE_ARBTXRATE, bcnrc_val);
3574         txgbe_flush(hw);
3575
3576         return 0;
3577 }
3578
3579 int
3580 txgbe_syn_filter_set(struct rte_eth_dev *dev,
3581                         struct rte_eth_syn_filter *filter,
3582                         bool add)
3583 {
3584         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3585         struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(dev);
3586         uint32_t syn_info;
3587         uint32_t synqf;
3588
3589         if (filter->queue >= TXGBE_MAX_RX_QUEUE_NUM)
3590                 return -EINVAL;
3591
3592         syn_info = filter_info->syn_info;
3593
3594         if (add) {
3595                 if (syn_info & TXGBE_SYNCLS_ENA)
3596                         return -EINVAL;
3597                 synqf = (uint32_t)TXGBE_SYNCLS_QPID(filter->queue);
3598                 synqf |= TXGBE_SYNCLS_ENA;
3599
3600                 if (filter->hig_pri)
3601                         synqf |= TXGBE_SYNCLS_HIPRIO;
3602                 else
3603                         synqf &= ~TXGBE_SYNCLS_HIPRIO;
3604         } else {
3605                 synqf = rd32(hw, TXGBE_SYNCLS);
3606                 if (!(syn_info & TXGBE_SYNCLS_ENA))
3607                         return -ENOENT;
3608                 synqf &= ~(TXGBE_SYNCLS_QPID_MASK | TXGBE_SYNCLS_ENA);
3609         }
3610
3611         filter_info->syn_info = synqf;
3612         wr32(hw, TXGBE_SYNCLS, synqf);
3613         txgbe_flush(hw);
3614         return 0;
3615 }
3616
3617 static inline enum txgbe_5tuple_protocol
3618 convert_protocol_type(uint8_t protocol_value)
3619 {
3620         if (protocol_value == IPPROTO_TCP)
3621                 return TXGBE_5TF_PROT_TCP;
3622         else if (protocol_value == IPPROTO_UDP)
3623                 return TXGBE_5TF_PROT_UDP;
3624         else if (protocol_value == IPPROTO_SCTP)
3625                 return TXGBE_5TF_PROT_SCTP;
3626         else
3627                 return TXGBE_5TF_PROT_NONE;
3628 }
3629
3630 /* inject a 5-tuple filter to HW */
3631 static inline void
3632 txgbe_inject_5tuple_filter(struct rte_eth_dev *dev,
3633                            struct txgbe_5tuple_filter *filter)
3634 {
3635         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3636         int i;
3637         uint32_t ftqf, sdpqf;
3638         uint32_t l34timir = 0;
3639         uint32_t mask = TXGBE_5TFCTL0_MASK;
3640
3641         i = filter->index;
3642         sdpqf = TXGBE_5TFPORT_DST(be_to_le16(filter->filter_info.dst_port));
3643         sdpqf |= TXGBE_5TFPORT_SRC(be_to_le16(filter->filter_info.src_port));
3644
3645         ftqf = TXGBE_5TFCTL0_PROTO(filter->filter_info.proto);
3646         ftqf |= TXGBE_5TFCTL0_PRI(filter->filter_info.priority);
3647         if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
3648                 mask &= ~TXGBE_5TFCTL0_MSADDR;
3649         if (filter->filter_info.dst_ip_mask == 0)
3650                 mask &= ~TXGBE_5TFCTL0_MDADDR;
3651         if (filter->filter_info.src_port_mask == 0)
3652                 mask &= ~TXGBE_5TFCTL0_MSPORT;
3653         if (filter->filter_info.dst_port_mask == 0)
3654                 mask &= ~TXGBE_5TFCTL0_MDPORT;
3655         if (filter->filter_info.proto_mask == 0)
3656                 mask &= ~TXGBE_5TFCTL0_MPROTO;
3657         ftqf |= mask;
3658         ftqf |= TXGBE_5TFCTL0_MPOOL;
3659         ftqf |= TXGBE_5TFCTL0_ENA;
3660
3661         wr32(hw, TXGBE_5TFDADDR(i), be_to_le32(filter->filter_info.dst_ip));
3662         wr32(hw, TXGBE_5TFSADDR(i), be_to_le32(filter->filter_info.src_ip));
3663         wr32(hw, TXGBE_5TFPORT(i), sdpqf);
3664         wr32(hw, TXGBE_5TFCTL0(i), ftqf);
3665
3666         l34timir |= TXGBE_5TFCTL1_QP(filter->queue);
3667         wr32(hw, TXGBE_5TFCTL1(i), l34timir);
3668 }
3669
3670 /*
3671  * add a 5tuple filter
3672  *
3673  * @param
3674  * dev: Pointer to struct rte_eth_dev.
3675  * index: the index the filter allocates.
3676  * filter: pointer to the filter that will be added.
3677  * rx_queue: the queue id the filter assigned to.
3678  *
3679  * @return
3680  *    - On success, zero.
3681  *    - On failure, a negative value.
3682  */
3683 static int
3684 txgbe_add_5tuple_filter(struct rte_eth_dev *dev,
3685                         struct txgbe_5tuple_filter *filter)
3686 {
3687         struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(dev);
3688         int i, idx, shift;
3689
3690         /*
3691          * look for an unused 5tuple filter index,
3692          * and insert the filter to list.
3693          */
3694         for (i = 0; i < TXGBE_MAX_FTQF_FILTERS; i++) {
3695                 idx = i / (sizeof(uint32_t) * NBBY);
3696                 shift = i % (sizeof(uint32_t) * NBBY);
3697                 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
3698                         filter_info->fivetuple_mask[idx] |= 1 << shift;
3699                         filter->index = i;
3700                         TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
3701                                           filter,
3702                                           entries);
3703                         break;
3704                 }
3705         }
3706         if (i >= TXGBE_MAX_FTQF_FILTERS) {
3707                 PMD_DRV_LOG(ERR, "5tuple filters are full.");
3708                 return -ENOSYS;
3709         }
3710
3711         txgbe_inject_5tuple_filter(dev, filter);
3712
3713         return 0;
3714 }
3715
3716 /*
3717  * remove a 5tuple filter
3718  *
3719  * @param
3720  * dev: Pointer to struct rte_eth_dev.
3721  * filter: the pointer of the filter will be removed.
3722  */
3723 static void
3724 txgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
3725                         struct txgbe_5tuple_filter *filter)
3726 {
3727         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3728         struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(dev);
3729         uint16_t index = filter->index;
3730
3731         filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
3732                                 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
3733         TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
3734         rte_free(filter);
3735
3736         wr32(hw, TXGBE_5TFDADDR(index), 0);
3737         wr32(hw, TXGBE_5TFSADDR(index), 0);
3738         wr32(hw, TXGBE_5TFPORT(index), 0);
3739         wr32(hw, TXGBE_5TFCTL0(index), 0);
3740         wr32(hw, TXGBE_5TFCTL1(index), 0);
3741 }
3742
3743 static inline struct txgbe_5tuple_filter *
3744 txgbe_5tuple_filter_lookup(struct txgbe_5tuple_filter_list *filter_list,
3745                         struct txgbe_5tuple_filter_info *key)
3746 {
3747         struct txgbe_5tuple_filter *it;
3748
3749         TAILQ_FOREACH(it, filter_list, entries) {
3750                 if (memcmp(key, &it->filter_info,
3751                         sizeof(struct txgbe_5tuple_filter_info)) == 0) {
3752                         return it;
3753                 }
3754         }
3755         return NULL;
3756 }
3757
3758 /* translate elements in struct rte_eth_ntuple_filter
3759  * to struct txgbe_5tuple_filter_info
3760  */
3761 static inline int
3762 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
3763                         struct txgbe_5tuple_filter_info *filter_info)
3764 {
3765         if (filter->queue >= TXGBE_MAX_RX_QUEUE_NUM ||
3766                 filter->priority > TXGBE_5TUPLE_MAX_PRI ||
3767                 filter->priority < TXGBE_5TUPLE_MIN_PRI)
3768                 return -EINVAL;
3769
3770         switch (filter->dst_ip_mask) {
3771         case UINT32_MAX:
3772                 filter_info->dst_ip_mask = 0;
3773                 filter_info->dst_ip = filter->dst_ip;
3774                 break;
3775         case 0:
3776                 filter_info->dst_ip_mask = 1;
3777                 break;
3778         default:
3779                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
3780                 return -EINVAL;
3781         }
3782
3783         switch (filter->src_ip_mask) {
3784         case UINT32_MAX:
3785                 filter_info->src_ip_mask = 0;
3786                 filter_info->src_ip = filter->src_ip;
3787                 break;
3788         case 0:
3789                 filter_info->src_ip_mask = 1;
3790                 break;
3791         default:
3792                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
3793                 return -EINVAL;
3794         }
3795
3796         switch (filter->dst_port_mask) {
3797         case UINT16_MAX:
3798                 filter_info->dst_port_mask = 0;
3799                 filter_info->dst_port = filter->dst_port;
3800                 break;
3801         case 0:
3802                 filter_info->dst_port_mask = 1;
3803                 break;
3804         default:
3805                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
3806                 return -EINVAL;
3807         }
3808
3809         switch (filter->src_port_mask) {
3810         case UINT16_MAX:
3811                 filter_info->src_port_mask = 0;
3812                 filter_info->src_port = filter->src_port;
3813                 break;
3814         case 0:
3815                 filter_info->src_port_mask = 1;
3816                 break;
3817         default:
3818                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
3819                 return -EINVAL;
3820         }
3821
3822         switch (filter->proto_mask) {
3823         case UINT8_MAX:
3824                 filter_info->proto_mask = 0;
3825                 filter_info->proto =
3826                         convert_protocol_type(filter->proto);
3827                 break;
3828         case 0:
3829                 filter_info->proto_mask = 1;
3830                 break;
3831         default:
3832                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
3833                 return -EINVAL;
3834         }
3835
3836         filter_info->priority = (uint8_t)filter->priority;
3837         return 0;
3838 }
3839
3840 /*
3841  * add or delete a ntuple filter
3842  *
3843  * @param
3844  * dev: Pointer to struct rte_eth_dev.
3845  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
3846  * add: if true, add filter, if false, remove filter
3847  *
3848  * @return
3849  *    - On success, zero.
3850  *    - On failure, a negative value.
3851  */
3852 int
3853 txgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
3854                         struct rte_eth_ntuple_filter *ntuple_filter,
3855                         bool add)
3856 {
3857         struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(dev);
3858         struct txgbe_5tuple_filter_info filter_5tuple;
3859         struct txgbe_5tuple_filter *filter;
3860         int ret;
3861
3862         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
3863                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
3864                 return -EINVAL;
3865         }
3866
3867         memset(&filter_5tuple, 0, sizeof(struct txgbe_5tuple_filter_info));
3868         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
3869         if (ret < 0)
3870                 return ret;
3871
3872         filter = txgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
3873                                          &filter_5tuple);
3874         if (filter != NULL && add) {
3875                 PMD_DRV_LOG(ERR, "filter exists.");
3876                 return -EEXIST;
3877         }
3878         if (filter == NULL && !add) {
3879                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3880                 return -ENOENT;
3881         }
3882
3883         if (add) {
3884                 filter = rte_zmalloc("txgbe_5tuple_filter",
3885                                 sizeof(struct txgbe_5tuple_filter), 0);
3886                 if (filter == NULL)
3887                         return -ENOMEM;
3888                 rte_memcpy(&filter->filter_info,
3889                                  &filter_5tuple,
3890                                  sizeof(struct txgbe_5tuple_filter_info));
3891                 filter->queue = ntuple_filter->queue;
3892                 ret = txgbe_add_5tuple_filter(dev, filter);
3893                 if (ret < 0) {
3894                         rte_free(filter);
3895                         return ret;
3896                 }
3897         } else {
3898                 txgbe_remove_5tuple_filter(dev, filter);
3899         }
3900
3901         return 0;
3902 }
3903
3904 int
3905 txgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
3906                         struct rte_eth_ethertype_filter *filter,
3907                         bool add)
3908 {
3909         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3910         struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(dev);
3911         uint32_t etqf = 0;
3912         uint32_t etqs = 0;
3913         int ret;
3914         struct txgbe_ethertype_filter ethertype_filter;
3915
3916         if (filter->queue >= TXGBE_MAX_RX_QUEUE_NUM)
3917                 return -EINVAL;
3918
3919         if (filter->ether_type == RTE_ETHER_TYPE_IPV4 ||
3920             filter->ether_type == RTE_ETHER_TYPE_IPV6) {
3921                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
3922                         " ethertype filter.", filter->ether_type);
3923                 return -EINVAL;
3924         }
3925
3926         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
3927                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
3928                 return -EINVAL;
3929         }
3930         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
3931                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
3932                 return -EINVAL;
3933         }
3934
3935         ret = txgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
3936         if (ret >= 0 && add) {
3937                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
3938                             filter->ether_type);
3939                 return -EEXIST;
3940         }
3941         if (ret < 0 && !add) {
3942                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
3943                             filter->ether_type);
3944                 return -ENOENT;
3945         }
3946
3947         if (add) {
3948                 etqf = TXGBE_ETFLT_ENA;
3949                 etqf |= TXGBE_ETFLT_ETID(filter->ether_type);
3950                 etqs |= TXGBE_ETCLS_QPID(filter->queue);
3951                 etqs |= TXGBE_ETCLS_QENA;
3952
3953                 ethertype_filter.ethertype = filter->ether_type;
3954                 ethertype_filter.etqf = etqf;
3955                 ethertype_filter.etqs = etqs;
3956                 ethertype_filter.conf = FALSE;
3957                 ret = txgbe_ethertype_filter_insert(filter_info,
3958                                                     &ethertype_filter);
3959                 if (ret < 0) {
3960                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
3961                         return -ENOSPC;
3962                 }
3963         } else {
3964                 ret = txgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
3965                 if (ret < 0)
3966                         return -ENOSYS;
3967         }
3968         wr32(hw, TXGBE_ETFLT(ret), etqf);
3969         wr32(hw, TXGBE_ETCLS(ret), etqs);
3970         txgbe_flush(hw);
3971
3972         return 0;
3973 }
3974
3975 static int
3976 txgbe_dev_filter_ctrl(__rte_unused struct rte_eth_dev *dev,
3977                      enum rte_filter_type filter_type,
3978                      enum rte_filter_op filter_op,
3979                      void *arg)
3980 {
3981         int ret = 0;
3982
3983         switch (filter_type) {
3984         case RTE_ETH_FILTER_GENERIC:
3985                 if (filter_op != RTE_ETH_FILTER_GET)
3986                         return -EINVAL;
3987                 *(const void **)arg = &txgbe_flow_ops;
3988                 break;
3989         default:
3990                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
3991                                                         filter_type);
3992                 ret = -EINVAL;
3993                 break;
3994         }
3995
3996         return ret;
3997 }
3998
3999 static u8 *
4000 txgbe_dev_addr_list_itr(__rte_unused struct txgbe_hw *hw,
4001                         u8 **mc_addr_ptr, u32 *vmdq)
4002 {
4003         u8 *mc_addr;
4004
4005         *vmdq = 0;
4006         mc_addr = *mc_addr_ptr;
4007         *mc_addr_ptr = (mc_addr + sizeof(struct rte_ether_addr));
4008         return mc_addr;
4009 }
4010
4011 int
4012 txgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
4013                           struct rte_ether_addr *mc_addr_set,
4014                           uint32_t nb_mc_addr)
4015 {
4016         struct txgbe_hw *hw;
4017         u8 *mc_addr_list;
4018
4019         hw = TXGBE_DEV_HW(dev);
4020         mc_addr_list = (u8 *)mc_addr_set;
4021         return txgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
4022                                          txgbe_dev_addr_list_itr, TRUE);
4023 }
4024
4025 static uint64_t
4026 txgbe_read_systime_cyclecounter(struct rte_eth_dev *dev)
4027 {
4028         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4029         uint64_t systime_cycles;
4030
4031         systime_cycles = (uint64_t)rd32(hw, TXGBE_TSTIMEL);
4032         systime_cycles |= (uint64_t)rd32(hw, TXGBE_TSTIMEH) << 32;
4033
4034         return systime_cycles;
4035 }
4036
4037 static uint64_t
4038 txgbe_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
4039 {
4040         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4041         uint64_t rx_tstamp_cycles;
4042
4043         /* TSRXSTMPL stores ns and TSRXSTMPH stores seconds. */
4044         rx_tstamp_cycles = (uint64_t)rd32(hw, TXGBE_TSRXSTMPL);
4045         rx_tstamp_cycles |= (uint64_t)rd32(hw, TXGBE_TSRXSTMPH) << 32;
4046
4047         return rx_tstamp_cycles;
4048 }
4049
4050 static uint64_t
4051 txgbe_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
4052 {
4053         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4054         uint64_t tx_tstamp_cycles;
4055
4056         /* TSTXSTMPL stores ns and TSTXSTMPH stores seconds. */
4057         tx_tstamp_cycles = (uint64_t)rd32(hw, TXGBE_TSTXSTMPL);
4058         tx_tstamp_cycles |= (uint64_t)rd32(hw, TXGBE_TSTXSTMPH) << 32;
4059
4060         return tx_tstamp_cycles;
4061 }
4062
4063 static void
4064 txgbe_start_timecounters(struct rte_eth_dev *dev)
4065 {
4066         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4067         struct txgbe_adapter *adapter = TXGBE_DEV_ADAPTER(dev);
4068         struct rte_eth_link link;
4069         uint32_t incval = 0;
4070         uint32_t shift = 0;
4071
4072         /* Get current link speed. */
4073         txgbe_dev_link_update(dev, 1);
4074         rte_eth_linkstatus_get(dev, &link);
4075
4076         switch (link.link_speed) {
4077         case ETH_SPEED_NUM_100M:
4078                 incval = TXGBE_INCVAL_100;
4079                 shift = TXGBE_INCVAL_SHIFT_100;
4080                 break;
4081         case ETH_SPEED_NUM_1G:
4082                 incval = TXGBE_INCVAL_1GB;
4083                 shift = TXGBE_INCVAL_SHIFT_1GB;
4084                 break;
4085         case ETH_SPEED_NUM_10G:
4086         default:
4087                 incval = TXGBE_INCVAL_10GB;
4088                 shift = TXGBE_INCVAL_SHIFT_10GB;
4089                 break;
4090         }
4091
4092         wr32(hw, TXGBE_TSTIMEINC, TXGBE_TSTIMEINC_VP(incval, 2));
4093
4094         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
4095         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
4096         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
4097
4098         adapter->systime_tc.cc_mask = TXGBE_CYCLECOUNTER_MASK;
4099         adapter->systime_tc.cc_shift = shift;
4100         adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
4101
4102         adapter->rx_tstamp_tc.cc_mask = TXGBE_CYCLECOUNTER_MASK;
4103         adapter->rx_tstamp_tc.cc_shift = shift;
4104         adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
4105
4106         adapter->tx_tstamp_tc.cc_mask = TXGBE_CYCLECOUNTER_MASK;
4107         adapter->tx_tstamp_tc.cc_shift = shift;
4108         adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
4109 }
4110
4111 static int
4112 txgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
4113 {
4114         struct txgbe_adapter *adapter = TXGBE_DEV_ADAPTER(dev);
4115
4116         adapter->systime_tc.nsec += delta;
4117         adapter->rx_tstamp_tc.nsec += delta;
4118         adapter->tx_tstamp_tc.nsec += delta;
4119
4120         return 0;
4121 }
4122
4123 static int
4124 txgbe_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
4125 {
4126         uint64_t ns;
4127         struct txgbe_adapter *adapter = TXGBE_DEV_ADAPTER(dev);
4128
4129         ns = rte_timespec_to_ns(ts);
4130         /* Set the timecounters to a new value. */
4131         adapter->systime_tc.nsec = ns;
4132         adapter->rx_tstamp_tc.nsec = ns;
4133         adapter->tx_tstamp_tc.nsec = ns;
4134
4135         return 0;
4136 }
4137
4138 static int
4139 txgbe_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
4140 {
4141         uint64_t ns, systime_cycles;
4142         struct txgbe_adapter *adapter = TXGBE_DEV_ADAPTER(dev);
4143
4144         systime_cycles = txgbe_read_systime_cyclecounter(dev);
4145         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
4146         *ts = rte_ns_to_timespec(ns);
4147
4148         return 0;
4149 }
4150
4151 static int
4152 txgbe_timesync_enable(struct rte_eth_dev *dev)
4153 {
4154         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4155         uint32_t tsync_ctl;
4156
4157         /* Stop the timesync system time. */
4158         wr32(hw, TXGBE_TSTIMEINC, 0x0);
4159         /* Reset the timesync system time value. */
4160         wr32(hw, TXGBE_TSTIMEL, 0x0);
4161         wr32(hw, TXGBE_TSTIMEH, 0x0);
4162
4163         txgbe_start_timecounters(dev);
4164
4165         /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
4166         wr32(hw, TXGBE_ETFLT(TXGBE_ETF_ID_1588),
4167                 RTE_ETHER_TYPE_1588 | TXGBE_ETFLT_ENA | TXGBE_ETFLT_1588);
4168
4169         /* Enable timestamping of received PTP packets. */
4170         tsync_ctl = rd32(hw, TXGBE_TSRXCTL);
4171         tsync_ctl |= TXGBE_TSRXCTL_ENA;
4172         wr32(hw, TXGBE_TSRXCTL, tsync_ctl);
4173
4174         /* Enable timestamping of transmitted PTP packets. */
4175         tsync_ctl = rd32(hw, TXGBE_TSTXCTL);
4176         tsync_ctl |= TXGBE_TSTXCTL_ENA;
4177         wr32(hw, TXGBE_TSTXCTL, tsync_ctl);
4178
4179         txgbe_flush(hw);
4180
4181         return 0;
4182 }
4183
4184 static int
4185 txgbe_timesync_disable(struct rte_eth_dev *dev)
4186 {
4187         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4188         uint32_t tsync_ctl;
4189
4190         /* Disable timestamping of transmitted PTP packets. */
4191         tsync_ctl = rd32(hw, TXGBE_TSTXCTL);
4192         tsync_ctl &= ~TXGBE_TSTXCTL_ENA;
4193         wr32(hw, TXGBE_TSTXCTL, tsync_ctl);
4194
4195         /* Disable timestamping of received PTP packets. */
4196         tsync_ctl = rd32(hw, TXGBE_TSRXCTL);
4197         tsync_ctl &= ~TXGBE_TSRXCTL_ENA;
4198         wr32(hw, TXGBE_TSRXCTL, tsync_ctl);
4199
4200         /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
4201         wr32(hw, TXGBE_ETFLT(TXGBE_ETF_ID_1588), 0);
4202
4203         /* Stop incrementating the System Time registers. */
4204         wr32(hw, TXGBE_TSTIMEINC, 0);
4205
4206         return 0;
4207 }
4208
4209 static int
4210 txgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
4211                                  struct timespec *timestamp,
4212                                  uint32_t flags __rte_unused)
4213 {
4214         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4215         struct txgbe_adapter *adapter = TXGBE_DEV_ADAPTER(dev);
4216         uint32_t tsync_rxctl;
4217         uint64_t rx_tstamp_cycles;
4218         uint64_t ns;
4219
4220         tsync_rxctl = rd32(hw, TXGBE_TSRXCTL);
4221         if ((tsync_rxctl & TXGBE_TSRXCTL_VLD) == 0)
4222                 return -EINVAL;
4223
4224         rx_tstamp_cycles = txgbe_read_rx_tstamp_cyclecounter(dev);
4225         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
4226         *timestamp = rte_ns_to_timespec(ns);
4227
4228         return  0;
4229 }
4230
4231 static int
4232 txgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
4233                                  struct timespec *timestamp)
4234 {
4235         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4236         struct txgbe_adapter *adapter = TXGBE_DEV_ADAPTER(dev);
4237         uint32_t tsync_txctl;
4238         uint64_t tx_tstamp_cycles;
4239         uint64_t ns;
4240
4241         tsync_txctl = rd32(hw, TXGBE_TSTXCTL);
4242         if ((tsync_txctl & TXGBE_TSTXCTL_VLD) == 0)
4243                 return -EINVAL;
4244
4245         tx_tstamp_cycles = txgbe_read_tx_tstamp_cyclecounter(dev);
4246         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
4247         *timestamp = rte_ns_to_timespec(ns);
4248
4249         return 0;
4250 }
4251
4252 static int
4253 txgbe_get_reg_length(struct rte_eth_dev *dev __rte_unused)
4254 {
4255         int count = 0;
4256         int g_ind = 0;
4257         const struct reg_info *reg_group;
4258         const struct reg_info **reg_set = txgbe_regs_others;
4259
4260         while ((reg_group = reg_set[g_ind++]))
4261                 count += txgbe_regs_group_count(reg_group);
4262
4263         return count;
4264 }
4265
4266 static int
4267 txgbe_get_regs(struct rte_eth_dev *dev,
4268               struct rte_dev_reg_info *regs)
4269 {
4270         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4271         uint32_t *data = regs->data;
4272         int g_ind = 0;
4273         int count = 0;
4274         const struct reg_info *reg_group;
4275         const struct reg_info **reg_set = txgbe_regs_others;
4276
4277         if (data == NULL) {
4278                 regs->length = txgbe_get_reg_length(dev);
4279                 regs->width = sizeof(uint32_t);
4280                 return 0;
4281         }
4282
4283         /* Support only full register dump */
4284         if (regs->length == 0 ||
4285             regs->length == (uint32_t)txgbe_get_reg_length(dev)) {
4286                 regs->version = hw->mac.type << 24 |
4287                                 hw->revision_id << 16 |
4288                                 hw->device_id;
4289                 while ((reg_group = reg_set[g_ind++]))
4290                         count += txgbe_read_regs_group(dev, &data[count],
4291                                                       reg_group);
4292                 return 0;
4293         }
4294
4295         return -ENOTSUP;
4296 }
4297
4298 static int
4299 txgbe_get_eeprom_length(struct rte_eth_dev *dev)
4300 {
4301         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4302
4303         /* Return unit is byte count */
4304         return hw->rom.word_size * 2;
4305 }
4306
4307 static int
4308 txgbe_get_eeprom(struct rte_eth_dev *dev,
4309                 struct rte_dev_eeprom_info *in_eeprom)
4310 {
4311         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4312         struct txgbe_rom_info *eeprom = &hw->rom;
4313         uint16_t *data = in_eeprom->data;
4314         int first, length;
4315
4316         first = in_eeprom->offset >> 1;
4317         length = in_eeprom->length >> 1;
4318         if (first > hw->rom.word_size ||
4319             ((first + length) > hw->rom.word_size))
4320                 return -EINVAL;
4321
4322         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
4323
4324         return eeprom->readw_buffer(hw, first, length, data);
4325 }
4326
4327 static int
4328 txgbe_set_eeprom(struct rte_eth_dev *dev,
4329                 struct rte_dev_eeprom_info *in_eeprom)
4330 {
4331         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4332         struct txgbe_rom_info *eeprom = &hw->rom;
4333         uint16_t *data = in_eeprom->data;
4334         int first, length;
4335
4336         first = in_eeprom->offset >> 1;
4337         length = in_eeprom->length >> 1;
4338         if (first > hw->rom.word_size ||
4339             ((first + length) > hw->rom.word_size))
4340                 return -EINVAL;
4341
4342         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
4343
4344         return eeprom->writew_buffer(hw,  first, length, data);
4345 }
4346
4347 static int
4348 txgbe_get_module_info(struct rte_eth_dev *dev,
4349                       struct rte_eth_dev_module_info *modinfo)
4350 {
4351         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4352         uint32_t status;
4353         uint8_t sff8472_rev, addr_mode;
4354         bool page_swap = false;
4355
4356         /* Check whether we support SFF-8472 or not */
4357         status = hw->phy.read_i2c_eeprom(hw,
4358                                              TXGBE_SFF_SFF_8472_COMP,
4359                                              &sff8472_rev);
4360         if (status != 0)
4361                 return -EIO;
4362
4363         /* addressing mode is not supported */
4364         status = hw->phy.read_i2c_eeprom(hw,
4365                                              TXGBE_SFF_SFF_8472_SWAP,
4366                                              &addr_mode);
4367         if (status != 0)
4368                 return -EIO;
4369
4370         if (addr_mode & TXGBE_SFF_ADDRESSING_MODE) {
4371                 PMD_DRV_LOG(ERR,
4372                             "Address change required to access page 0xA2, "
4373                             "but not supported. Please report the module "
4374                             "type to the driver maintainers.");
4375                 page_swap = true;
4376         }
4377
4378         if (sff8472_rev == TXGBE_SFF_SFF_8472_UNSUP || page_swap) {
4379                 /* We have a SFP, but it does not support SFF-8472 */
4380                 modinfo->type = RTE_ETH_MODULE_SFF_8079;
4381                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
4382         } else {
4383                 /* We have a SFP which supports a revision of SFF-8472. */
4384                 modinfo->type = RTE_ETH_MODULE_SFF_8472;
4385                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
4386         }
4387
4388         return 0;
4389 }
4390
4391 static int
4392 txgbe_get_module_eeprom(struct rte_eth_dev *dev,
4393                         struct rte_dev_eeprom_info *info)
4394 {
4395         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4396         uint32_t status = TXGBE_ERR_PHY_ADDR_INVALID;
4397         uint8_t databyte = 0xFF;
4398         uint8_t *data = info->data;
4399         uint32_t i = 0;
4400
4401         if (info->length == 0)
4402                 return -EINVAL;
4403
4404         for (i = info->offset; i < info->offset + info->length; i++) {
4405                 if (i < RTE_ETH_MODULE_SFF_8079_LEN)
4406                         status = hw->phy.read_i2c_eeprom(hw, i, &databyte);
4407                 else
4408                         status = hw->phy.read_i2c_sff8472(hw, i, &databyte);
4409
4410                 if (status != 0)
4411                         return -EIO;
4412
4413                 data[i - info->offset] = databyte;
4414         }
4415
4416         return 0;
4417 }
4418
4419 bool
4420 txgbe_rss_update_sp(enum txgbe_mac_type mac_type)
4421 {
4422         switch (mac_type) {
4423         case txgbe_mac_raptor:
4424                 return 1;
4425         default:
4426                 return 0;
4427         }
4428 }
4429
4430 static int
4431 txgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
4432                         struct rte_eth_dcb_info *dcb_info)
4433 {
4434         struct txgbe_dcb_config *dcb_config = TXGBE_DEV_DCB_CONFIG(dev);
4435         struct txgbe_dcb_tc_config *tc;
4436         struct rte_eth_dcb_tc_queue_mapping *tc_queue;
4437         uint8_t nb_tcs;
4438         uint8_t i, j;
4439
4440         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
4441                 dcb_info->nb_tcs = dcb_config->num_tcs.pg_tcs;
4442         else
4443                 dcb_info->nb_tcs = 1;
4444
4445         tc_queue = &dcb_info->tc_queue;
4446         nb_tcs = dcb_info->nb_tcs;
4447
4448         if (dcb_config->vt_mode) { /* vt is enabled */
4449                 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
4450                                 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
4451                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
4452                         dcb_info->prio_tc[i] = vmdq_rx_conf->dcb_tc[i];
4453                 if (RTE_ETH_DEV_SRIOV(dev).active > 0) {
4454                         for (j = 0; j < nb_tcs; j++) {
4455                                 tc_queue->tc_rxq[0][j].base = j;
4456                                 tc_queue->tc_rxq[0][j].nb_queue = 1;
4457                                 tc_queue->tc_txq[0][j].base = j;
4458                                 tc_queue->tc_txq[0][j].nb_queue = 1;
4459                         }
4460                 } else {
4461                         for (i = 0; i < vmdq_rx_conf->nb_queue_pools; i++) {
4462                                 for (j = 0; j < nb_tcs; j++) {
4463                                         tc_queue->tc_rxq[i][j].base =
4464                                                 i * nb_tcs + j;
4465                                         tc_queue->tc_rxq[i][j].nb_queue = 1;
4466                                         tc_queue->tc_txq[i][j].base =
4467                                                 i * nb_tcs + j;
4468                                         tc_queue->tc_txq[i][j].nb_queue = 1;
4469                                 }
4470                         }
4471                 }
4472         } else { /* vt is disabled */
4473                 struct rte_eth_dcb_rx_conf *rx_conf =
4474                                 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
4475                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
4476                         dcb_info->prio_tc[i] = rx_conf->dcb_tc[i];
4477                 if (dcb_info->nb_tcs == ETH_4_TCS) {
4478                         for (i = 0; i < dcb_info->nb_tcs; i++) {
4479                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 32;
4480                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
4481                         }
4482                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
4483                         dcb_info->tc_queue.tc_txq[0][1].base = 64;
4484                         dcb_info->tc_queue.tc_txq[0][2].base = 96;
4485                         dcb_info->tc_queue.tc_txq[0][3].base = 112;
4486                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 64;
4487                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
4488                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
4489                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
4490                 } else if (dcb_info->nb_tcs == ETH_8_TCS) {
4491                         for (i = 0; i < dcb_info->nb_tcs; i++) {
4492                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 16;
4493                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
4494                         }
4495                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
4496                         dcb_info->tc_queue.tc_txq[0][1].base = 32;
4497                         dcb_info->tc_queue.tc_txq[0][2].base = 64;
4498                         dcb_info->tc_queue.tc_txq[0][3].base = 80;
4499                         dcb_info->tc_queue.tc_txq[0][4].base = 96;
4500                         dcb_info->tc_queue.tc_txq[0][5].base = 104;
4501                         dcb_info->tc_queue.tc_txq[0][6].base = 112;
4502                         dcb_info->tc_queue.tc_txq[0][7].base = 120;
4503                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 32;
4504                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
4505                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
4506                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
4507                         dcb_info->tc_queue.tc_txq[0][4].nb_queue = 8;
4508                         dcb_info->tc_queue.tc_txq[0][5].nb_queue = 8;
4509                         dcb_info->tc_queue.tc_txq[0][6].nb_queue = 8;
4510                         dcb_info->tc_queue.tc_txq[0][7].nb_queue = 8;
4511                 }
4512         }
4513         for (i = 0; i < dcb_info->nb_tcs; i++) {
4514                 tc = &dcb_config->tc_config[i];
4515                 dcb_info->tc_bws[i] = tc->path[TXGBE_DCB_TX_CONFIG].bwg_percent;
4516         }
4517         return 0;
4518 }
4519
4520 /* restore n-tuple filter */
4521 static inline void
4522 txgbe_ntuple_filter_restore(struct rte_eth_dev *dev)
4523 {
4524         struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(dev);
4525         struct txgbe_5tuple_filter *node;
4526
4527         TAILQ_FOREACH(node, &filter_info->fivetuple_list, entries) {
4528                 txgbe_inject_5tuple_filter(dev, node);
4529         }
4530 }
4531
4532 /* restore ethernet type filter */
4533 static inline void
4534 txgbe_ethertype_filter_restore(struct rte_eth_dev *dev)
4535 {
4536         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4537         struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(dev);
4538         int i;
4539
4540         for (i = 0; i < TXGBE_ETF_ID_MAX; i++) {
4541                 if (filter_info->ethertype_mask & (1 << i)) {
4542                         wr32(hw, TXGBE_ETFLT(i),
4543                                         filter_info->ethertype_filters[i].etqf);
4544                         wr32(hw, TXGBE_ETCLS(i),
4545                                         filter_info->ethertype_filters[i].etqs);
4546                         txgbe_flush(hw);
4547                 }
4548         }
4549 }
4550
4551 /* restore SYN filter */
4552 static inline void
4553 txgbe_syn_filter_restore(struct rte_eth_dev *dev)
4554 {
4555         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4556         struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(dev);
4557         uint32_t synqf;
4558
4559         synqf = filter_info->syn_info;
4560
4561         if (synqf & TXGBE_SYNCLS_ENA) {
4562                 wr32(hw, TXGBE_SYNCLS, synqf);
4563                 txgbe_flush(hw);
4564         }
4565 }
4566
4567 static int
4568 txgbe_filter_restore(struct rte_eth_dev *dev)
4569 {
4570         txgbe_ntuple_filter_restore(dev);
4571         txgbe_ethertype_filter_restore(dev);
4572         txgbe_syn_filter_restore(dev);
4573
4574         return 0;
4575 }
4576
4577 static const struct eth_dev_ops txgbe_eth_dev_ops = {
4578         .dev_configure              = txgbe_dev_configure,
4579         .dev_infos_get              = txgbe_dev_info_get,
4580         .dev_start                  = txgbe_dev_start,
4581         .dev_stop                   = txgbe_dev_stop,
4582         .dev_set_link_up            = txgbe_dev_set_link_up,
4583         .dev_set_link_down          = txgbe_dev_set_link_down,
4584         .dev_close                  = txgbe_dev_close,
4585         .dev_reset                  = txgbe_dev_reset,
4586         .promiscuous_enable         = txgbe_dev_promiscuous_enable,
4587         .promiscuous_disable        = txgbe_dev_promiscuous_disable,
4588         .allmulticast_enable        = txgbe_dev_allmulticast_enable,
4589         .allmulticast_disable       = txgbe_dev_allmulticast_disable,
4590         .link_update                = txgbe_dev_link_update,
4591         .stats_get                  = txgbe_dev_stats_get,
4592         .xstats_get                 = txgbe_dev_xstats_get,
4593         .xstats_get_by_id           = txgbe_dev_xstats_get_by_id,
4594         .stats_reset                = txgbe_dev_stats_reset,
4595         .xstats_reset               = txgbe_dev_xstats_reset,
4596         .xstats_get_names           = txgbe_dev_xstats_get_names,
4597         .xstats_get_names_by_id     = txgbe_dev_xstats_get_names_by_id,
4598         .queue_stats_mapping_set    = txgbe_dev_queue_stats_mapping_set,
4599         .fw_version_get             = txgbe_fw_version_get,
4600         .dev_supported_ptypes_get   = txgbe_dev_supported_ptypes_get,
4601         .mtu_set                    = txgbe_dev_mtu_set,
4602         .vlan_filter_set            = txgbe_vlan_filter_set,
4603         .vlan_tpid_set              = txgbe_vlan_tpid_set,
4604         .vlan_offload_set           = txgbe_vlan_offload_set,
4605         .vlan_strip_queue_set       = txgbe_vlan_strip_queue_set,
4606         .rx_queue_start             = txgbe_dev_rx_queue_start,
4607         .rx_queue_stop              = txgbe_dev_rx_queue_stop,
4608         .tx_queue_start             = txgbe_dev_tx_queue_start,
4609         .tx_queue_stop              = txgbe_dev_tx_queue_stop,
4610         .rx_queue_setup             = txgbe_dev_rx_queue_setup,
4611         .rx_queue_intr_enable       = txgbe_dev_rx_queue_intr_enable,
4612         .rx_queue_intr_disable      = txgbe_dev_rx_queue_intr_disable,
4613         .rx_queue_release           = txgbe_dev_rx_queue_release,
4614         .tx_queue_setup             = txgbe_dev_tx_queue_setup,
4615         .tx_queue_release           = txgbe_dev_tx_queue_release,
4616         .dev_led_on                 = txgbe_dev_led_on,
4617         .dev_led_off                = txgbe_dev_led_off,
4618         .flow_ctrl_get              = txgbe_flow_ctrl_get,
4619         .flow_ctrl_set              = txgbe_flow_ctrl_set,
4620         .priority_flow_ctrl_set     = txgbe_priority_flow_ctrl_set,
4621         .mac_addr_add               = txgbe_add_rar,
4622         .mac_addr_remove            = txgbe_remove_rar,
4623         .mac_addr_set               = txgbe_set_default_mac_addr,
4624         .uc_hash_table_set          = txgbe_uc_hash_table_set,
4625         .uc_all_hash_table_set      = txgbe_uc_all_hash_table_set,
4626         .set_queue_rate_limit       = txgbe_set_queue_rate_limit,
4627         .reta_update                = txgbe_dev_rss_reta_update,
4628         .reta_query                 = txgbe_dev_rss_reta_query,
4629         .rss_hash_update            = txgbe_dev_rss_hash_update,
4630         .rss_hash_conf_get          = txgbe_dev_rss_hash_conf_get,
4631         .filter_ctrl                = txgbe_dev_filter_ctrl,
4632         .set_mc_addr_list           = txgbe_dev_set_mc_addr_list,
4633         .rxq_info_get               = txgbe_rxq_info_get,
4634         .txq_info_get               = txgbe_txq_info_get,
4635         .timesync_enable            = txgbe_timesync_enable,
4636         .timesync_disable           = txgbe_timesync_disable,
4637         .timesync_read_rx_timestamp = txgbe_timesync_read_rx_timestamp,
4638         .timesync_read_tx_timestamp = txgbe_timesync_read_tx_timestamp,
4639         .get_reg                    = txgbe_get_regs,
4640         .get_eeprom_length          = txgbe_get_eeprom_length,
4641         .get_eeprom                 = txgbe_get_eeprom,
4642         .set_eeprom                 = txgbe_set_eeprom,
4643         .get_module_info            = txgbe_get_module_info,
4644         .get_module_eeprom          = txgbe_get_module_eeprom,
4645         .get_dcb_info               = txgbe_dev_get_dcb_info,
4646         .timesync_adjust_time       = txgbe_timesync_adjust_time,
4647         .timesync_read_time         = txgbe_timesync_read_time,
4648         .timesync_write_time        = txgbe_timesync_write_time,
4649         .tx_done_cleanup            = txgbe_dev_tx_done_cleanup,
4650 };
4651
4652 RTE_PMD_REGISTER_PCI(net_txgbe, rte_txgbe_pmd);
4653 RTE_PMD_REGISTER_PCI_TABLE(net_txgbe, pci_id_txgbe_map);
4654 RTE_PMD_REGISTER_KMOD_DEP(net_txgbe, "* igb_uio | uio_pci_generic | vfio-pci");
4655
4656 RTE_LOG_REGISTER(txgbe_logtype_init, pmd.net.txgbe.init, NOTICE);
4657 RTE_LOG_REGISTER(txgbe_logtype_driver, pmd.net.txgbe.driver, NOTICE);
4658
4659 #ifdef RTE_LIBRTE_TXGBE_DEBUG_RX
4660         RTE_LOG_REGISTER(txgbe_logtype_rx, pmd.net.txgbe.rx, DEBUG);
4661 #endif
4662 #ifdef RTE_LIBRTE_TXGBE_DEBUG_TX
4663         RTE_LOG_REGISTER(txgbe_logtype_tx, pmd.net.txgbe.tx, DEBUG);
4664 #endif
4665
4666 #ifdef RTE_LIBRTE_TXGBE_DEBUG_TX_FREE
4667         RTE_LOG_REGISTER(txgbe_logtype_tx_free, pmd.net.txgbe.tx_free, DEBUG);
4668 #endif