drivers/net/txgbe/txgbe_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2015-2020
   3  */
   4
   5 #include <stdio.h>
   6 #include <errno.h>
   7 #include <stdint.h>
   8 #include <string.h>
   9 #include <rte_common.h>
  10 #include <rte_ethdev_pci.h>
  11
  12 #include <rte_interrupts.h>
  13 #include <rte_log.h>
  14 #include <rte_debug.h>
  15 #include <rte_pci.h>
  16 #include <rte_memory.h>
  17 #include <rte_eal.h>
  18 #include <rte_alarm.h>
  19
  20 #include "txgbe_logs.h"
  21 #include "base/txgbe.h"
  22 #include "txgbe_ethdev.h"
  23 #include "txgbe_rxtx.h"
  24 #include "txgbe_regs_group.h"
  25
  26 static const struct reg_info txgbe_regs_general[] = {
  27         {TXGBE_RST, 1, 1, "TXGBE_RST"},
  28         {TXGBE_STAT, 1, 1, "TXGBE_STAT"},
  29         {TXGBE_PORTCTL, 1, 1, "TXGBE_PORTCTL"},
  30         {TXGBE_SDP, 1, 1, "TXGBE_SDP"},
  31         {TXGBE_SDPCTL, 1, 1, "TXGBE_SDPCTL"},
  32         {TXGBE_LEDCTL, 1, 1, "TXGBE_LEDCTL"},
  33         {0, 0, 0, ""}
  34 };
  35
  36 static const struct reg_info txgbe_regs_nvm[] = {
  37         {0, 0, 0, ""}
  38 };
  39
  40 static const struct reg_info txgbe_regs_interrupt[] = {
  41         {0, 0, 0, ""}
  42 };
  43
  44 static const struct reg_info txgbe_regs_fctl_others[] = {
  45         {0, 0, 0, ""}
  46 };
  47
  48 static const struct reg_info txgbe_regs_rxdma[] = {
  49         {0, 0, 0, ""}
  50 };
  51
  52 static const struct reg_info txgbe_regs_rx[] = {
  53         {0, 0, 0, ""}
  54 };
  55
  56 static struct reg_info txgbe_regs_tx[] = {
  57         {0, 0, 0, ""}
  58 };
  59
  60 static const struct reg_info txgbe_regs_wakeup[] = {
  61         {0, 0, 0, ""}
  62 };
  63
  64 static const struct reg_info txgbe_regs_dcb[] = {
  65         {0, 0, 0, ""}
  66 };
  67
  68 static const struct reg_info txgbe_regs_mac[] = {
  69         {0, 0, 0, ""}
  70 };
  71
  72 static const struct reg_info txgbe_regs_diagnostic[] = {
  73         {0, 0, 0, ""},
  74 };
  75
  76 /* PF registers */
  77 static const struct reg_info *txgbe_regs_others[] = {
  78                                 txgbe_regs_general,
  79                                 txgbe_regs_nvm,
  80                                 txgbe_regs_interrupt,
  81                                 txgbe_regs_fctl_others,
  82                                 txgbe_regs_rxdma,
  83                                 txgbe_regs_rx,
  84                                 txgbe_regs_tx,
  85                                 txgbe_regs_wakeup,
  86                                 txgbe_regs_dcb,
  87                                 txgbe_regs_mac,
  88                                 txgbe_regs_diagnostic,
  89                                 NULL};
  90
  91 static int txgbe_fdir_filter_init(struct rte_eth_dev *eth_dev);
  92 static int txgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev);
  93 static int txgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev);
  94 static int txgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev);
  95 static int  txgbe_dev_set_link_up(struct rte_eth_dev *dev);
  96 static int  txgbe_dev_set_link_down(struct rte_eth_dev *dev);
  97 static int txgbe_dev_close(struct rte_eth_dev *dev);
  98 static int txgbe_dev_link_update(struct rte_eth_dev *dev,
  99                                 int wait_to_complete);
 100 static int txgbe_dev_stats_reset(struct rte_eth_dev *dev);
 101 static void txgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
 102 static void txgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev,
 103                                         uint16_t queue);
 104
 105 static void txgbe_dev_link_status_print(struct rte_eth_dev *dev);
 106 static int txgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on);
 107 static int txgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev);
 108 static int txgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
 109 static int txgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
 110 static int txgbe_dev_interrupt_action(struct rte_eth_dev *dev,
 111                                       struct rte_intr_handle *handle);
 112 static void txgbe_dev_interrupt_handler(void *param);
 113 static void txgbe_dev_interrupt_delayed_handler(void *param);
 114 static void txgbe_configure_msix(struct rte_eth_dev *dev);
 115
 116 static int txgbe_filter_restore(struct rte_eth_dev *dev);
 117 static void txgbe_l2_tunnel_conf(struct rte_eth_dev *dev);
 118
 119 #define TXGBE_SET_HWSTRIP(h, q) do {\
 120                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 121                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 122                 (h)->bitmap[idx] |= 1 << bit;\
 123         } while (0)
 124
 125 #define TXGBE_CLEAR_HWSTRIP(h, q) do {\
 126                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 127                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 128                 (h)->bitmap[idx] &= ~(1 << bit);\
 129         } while (0)
 130
 131 #define TXGBE_GET_HWSTRIP(h, q, r) do {\
 132                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 133                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 134                 (r) = (h)->bitmap[idx] >> bit & 1;\
 135         } while (0)
 136
 137 /*
 138  * The set of PCI devices this driver supports
 139  */
 140 static const struct rte_pci_id pci_id_txgbe_map[] = {
 141         { RTE_PCI_DEVICE(PCI_VENDOR_ID_WANGXUN, TXGBE_DEV_ID_RAPTOR_SFP) },
 142         { RTE_PCI_DEVICE(PCI_VENDOR_ID_WANGXUN, TXGBE_DEV_ID_WX1820_SFP) },
 143         { .vendor_id = 0, /* sentinel */ },
 144 };
 145
 146 static const struct rte_eth_desc_lim rx_desc_lim = {
 147         .nb_max = TXGBE_RING_DESC_MAX,
 148         .nb_min = TXGBE_RING_DESC_MIN,
 149         .nb_align = TXGBE_RXD_ALIGN,
 150 };
 151
 152 static const struct rte_eth_desc_lim tx_desc_lim = {
 153         .nb_max = TXGBE_RING_DESC_MAX,
 154         .nb_min = TXGBE_RING_DESC_MIN,
 155         .nb_align = TXGBE_TXD_ALIGN,
 156         .nb_seg_max = TXGBE_TX_MAX_SEG,
 157         .nb_mtu_seg_max = TXGBE_TX_MAX_SEG,
 158 };
 159
 160 static const struct eth_dev_ops txgbe_eth_dev_ops;
 161
 162 #define HW_XSTAT(m) {#m, offsetof(struct txgbe_hw_stats, m)}
 163 #define HW_XSTAT_NAME(m, n) {n, offsetof(struct txgbe_hw_stats, m)}
 164 static const struct rte_txgbe_xstats_name_off rte_txgbe_stats_strings[] = {
 165         /* MNG RxTx */
 166         HW_XSTAT(mng_bmc2host_packets),
 167         HW_XSTAT(mng_host2bmc_packets),
 168         /* Basic RxTx */
 169         HW_XSTAT(rx_packets),
 170         HW_XSTAT(tx_packets),
 171         HW_XSTAT(rx_bytes),
 172         HW_XSTAT(tx_bytes),
 173         HW_XSTAT(rx_total_bytes),
 174         HW_XSTAT(rx_total_packets),
 175         HW_XSTAT(tx_total_packets),
 176         HW_XSTAT(rx_total_missed_packets),
 177         HW_XSTAT(rx_broadcast_packets),
 178         HW_XSTAT(rx_multicast_packets),
 179         HW_XSTAT(rx_management_packets),
 180         HW_XSTAT(tx_management_packets),
 181         HW_XSTAT(rx_management_dropped),
 182
 183         /* Basic Error */
 184         HW_XSTAT(rx_crc_errors),
 185         HW_XSTAT(rx_illegal_byte_errors),
 186         HW_XSTAT(rx_error_bytes),
 187         HW_XSTAT(rx_mac_short_packet_dropped),
 188         HW_XSTAT(rx_length_errors),
 189         HW_XSTAT(rx_undersize_errors),
 190         HW_XSTAT(rx_fragment_errors),
 191         HW_XSTAT(rx_oversize_errors),
 192         HW_XSTAT(rx_jabber_errors),
 193         HW_XSTAT(rx_l3_l4_xsum_error),
 194         HW_XSTAT(mac_local_errors),
 195         HW_XSTAT(mac_remote_errors),
 196
 197         /* Flow Director */
 198         HW_XSTAT(flow_director_added_filters),
 199         HW_XSTAT(flow_director_removed_filters),
 200         HW_XSTAT(flow_director_filter_add_errors),
 201         HW_XSTAT(flow_director_filter_remove_errors),
 202         HW_XSTAT(flow_director_matched_filters),
 203         HW_XSTAT(flow_director_missed_filters),
 204
 205         /* FCoE */
 206         HW_XSTAT(rx_fcoe_crc_errors),
 207         HW_XSTAT(rx_fcoe_mbuf_allocation_errors),
 208         HW_XSTAT(rx_fcoe_dropped),
 209         HW_XSTAT(rx_fcoe_packets),
 210         HW_XSTAT(tx_fcoe_packets),
 211         HW_XSTAT(rx_fcoe_bytes),
 212         HW_XSTAT(tx_fcoe_bytes),
 213         HW_XSTAT(rx_fcoe_no_ddp),
 214         HW_XSTAT(rx_fcoe_no_ddp_ext_buff),
 215
 216         /* MACSEC */
 217         HW_XSTAT(tx_macsec_pkts_untagged),
 218         HW_XSTAT(tx_macsec_pkts_encrypted),
 219         HW_XSTAT(tx_macsec_pkts_protected),
 220         HW_XSTAT(tx_macsec_octets_encrypted),
 221         HW_XSTAT(tx_macsec_octets_protected),
 222         HW_XSTAT(rx_macsec_pkts_untagged),
 223         HW_XSTAT(rx_macsec_pkts_badtag),
 224         HW_XSTAT(rx_macsec_pkts_nosci),
 225         HW_XSTAT(rx_macsec_pkts_unknownsci),
 226         HW_XSTAT(rx_macsec_octets_decrypted),
 227         HW_XSTAT(rx_macsec_octets_validated),
 228         HW_XSTAT(rx_macsec_sc_pkts_unchecked),
 229         HW_XSTAT(rx_macsec_sc_pkts_delayed),
 230         HW_XSTAT(rx_macsec_sc_pkts_late),
 231         HW_XSTAT(rx_macsec_sa_pkts_ok),
 232         HW_XSTAT(rx_macsec_sa_pkts_invalid),
 233         HW_XSTAT(rx_macsec_sa_pkts_notvalid),
 234         HW_XSTAT(rx_macsec_sa_pkts_unusedsa),
 235         HW_XSTAT(rx_macsec_sa_pkts_notusingsa),
 236
 237         /* MAC RxTx */
 238         HW_XSTAT(rx_size_64_packets),
 239         HW_XSTAT(rx_size_65_to_127_packets),
 240         HW_XSTAT(rx_size_128_to_255_packets),
 241         HW_XSTAT(rx_size_256_to_511_packets),
 242         HW_XSTAT(rx_size_512_to_1023_packets),
 243         HW_XSTAT(rx_size_1024_to_max_packets),
 244         HW_XSTAT(tx_size_64_packets),
 245         HW_XSTAT(tx_size_65_to_127_packets),
 246         HW_XSTAT(tx_size_128_to_255_packets),
 247         HW_XSTAT(tx_size_256_to_511_packets),
 248         HW_XSTAT(tx_size_512_to_1023_packets),
 249         HW_XSTAT(tx_size_1024_to_max_packets),
 250
 251         /* Flow Control */
 252         HW_XSTAT(tx_xon_packets),
 253         HW_XSTAT(rx_xon_packets),
 254         HW_XSTAT(tx_xoff_packets),
 255         HW_XSTAT(rx_xoff_packets),
 256
 257         HW_XSTAT_NAME(tx_xon_packets, "tx_flow_control_xon_packets"),
 258         HW_XSTAT_NAME(rx_xon_packets, "rx_flow_control_xon_packets"),
 259         HW_XSTAT_NAME(tx_xoff_packets, "tx_flow_control_xoff_packets"),
 260         HW_XSTAT_NAME(rx_xoff_packets, "rx_flow_control_xoff_packets"),
 261 };
 262
 263 #define TXGBE_NB_HW_STATS (sizeof(rte_txgbe_stats_strings) / \
 264                            sizeof(rte_txgbe_stats_strings[0]))
 265
 266 /* Per-priority statistics */
 267 #define UP_XSTAT(m) {#m, offsetof(struct txgbe_hw_stats, up[0].m)}
 268 static const struct rte_txgbe_xstats_name_off rte_txgbe_up_strings[] = {
 269         UP_XSTAT(rx_up_packets),
 270         UP_XSTAT(tx_up_packets),
 271         UP_XSTAT(rx_up_bytes),
 272         UP_XSTAT(tx_up_bytes),
 273         UP_XSTAT(rx_up_drop_packets),
 274
 275         UP_XSTAT(tx_up_xon_packets),
 276         UP_XSTAT(rx_up_xon_packets),
 277         UP_XSTAT(tx_up_xoff_packets),
 278         UP_XSTAT(rx_up_xoff_packets),
 279         UP_XSTAT(rx_up_dropped),
 280         UP_XSTAT(rx_up_mbuf_alloc_errors),
 281         UP_XSTAT(tx_up_xon2off_packets),
 282 };
 283
 284 #define TXGBE_NB_UP_STATS (sizeof(rte_txgbe_up_strings) / \
 285                            sizeof(rte_txgbe_up_strings[0]))
 286
 287 /* Per-queue statistics */
 288 #define QP_XSTAT(m) {#m, offsetof(struct txgbe_hw_stats, qp[0].m)}
 289 static const struct rte_txgbe_xstats_name_off rte_txgbe_qp_strings[] = {
 290         QP_XSTAT(rx_qp_packets),
 291         QP_XSTAT(tx_qp_packets),
 292         QP_XSTAT(rx_qp_bytes),
 293         QP_XSTAT(tx_qp_bytes),
 294         QP_XSTAT(rx_qp_mc_packets),
 295 };
 296
 297 #define TXGBE_NB_QP_STATS (sizeof(rte_txgbe_qp_strings) / \
 298                            sizeof(rte_txgbe_qp_strings[0]))
 299
 300 static inline int
 301 txgbe_is_sfp(struct txgbe_hw *hw)
 302 {
 303         switch (hw->phy.type) {
 304         case txgbe_phy_sfp_avago:
 305         case txgbe_phy_sfp_ftl:
 306         case txgbe_phy_sfp_intel:
 307         case txgbe_phy_sfp_unknown:
 308         case txgbe_phy_sfp_tyco_passive:
 309         case txgbe_phy_sfp_unknown_passive:
 310                 return 1;
 311         default:
 312                 return 0;
 313         }
 314 }
 315
 316 static inline int32_t
 317 txgbe_pf_reset_hw(struct txgbe_hw *hw)
 318 {
 319         uint32_t ctrl_ext;
 320         int32_t status;
 321
 322         status = hw->mac.reset_hw(hw);
 323
 324         ctrl_ext = rd32(hw, TXGBE_PORTCTL);
 325         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 326         ctrl_ext |= TXGBE_PORTCTL_RSTDONE;
 327         wr32(hw, TXGBE_PORTCTL, ctrl_ext);
 328         txgbe_flush(hw);
 329
 330         if (status == TXGBE_ERR_SFP_NOT_PRESENT)
 331                 status = 0;
 332         return status;
 333 }
 334
 335 static inline void
 336 txgbe_enable_intr(struct rte_eth_dev *dev)
 337 {
 338         struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);
 339         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
 340
 341         wr32(hw, TXGBE_IENMISC, intr->mask_misc);
 342         wr32(hw, TXGBE_IMC(0), TXGBE_IMC_MASK);
 343         wr32(hw, TXGBE_IMC(1), TXGBE_IMC_MASK);
 344         txgbe_flush(hw);
 345 }
 346
 347 static void
 348 txgbe_disable_intr(struct txgbe_hw *hw)
 349 {
 350         PMD_INIT_FUNC_TRACE();
 351
 352         wr32(hw, TXGBE_IENMISC, ~BIT_MASK32);
 353         wr32(hw, TXGBE_IMS(0), TXGBE_IMC_MASK);
 354         wr32(hw, TXGBE_IMS(1), TXGBE_IMC_MASK);
 355         txgbe_flush(hw);
 356 }
 357
 358 static int
 359 txgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 360                                   uint16_t queue_id,
 361                                   uint8_t stat_idx,
 362                                   uint8_t is_rx)
 363 {
 364         struct txgbe_hw *hw = TXGBE_DEV_HW(eth_dev);
 365         struct txgbe_stat_mappings *stat_mappings =
 366                 TXGBE_DEV_STAT_MAPPINGS(eth_dev);
 367         uint32_t qsmr_mask = 0;
 368         uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
 369         uint32_t q_map;
 370         uint8_t n, offset;
 371
 372         if (hw->mac.type != txgbe_mac_raptor)
 373                 return -ENOSYS;
 374
 375         if (stat_idx & !QMAP_FIELD_RESERVED_BITS_MASK)
 376                 return -EIO;
 377
 378         PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d",
 379                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 380                      queue_id, stat_idx);
 381
 382         n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
 383         if (n >= TXGBE_NB_STAT_MAPPING) {
 384                 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
 385                 return -EIO;
 386         }
 387         offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
 388
 389         /* Now clear any previous stat_idx set */
 390         clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 391         if (!is_rx)
 392                 stat_mappings->tqsm[n] &= ~clearing_mask;
 393         else
 394                 stat_mappings->rqsm[n] &= ~clearing_mask;
 395
 396         q_map = (uint32_t)stat_idx;
 397         q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
 398         qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 399         if (!is_rx)
 400                 stat_mappings->tqsm[n] |= qsmr_mask;
 401         else
 402                 stat_mappings->rqsm[n] |= qsmr_mask;
 403
 404         PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d",
 405                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 406                      queue_id, stat_idx);
 407         PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
 408                      is_rx ? stat_mappings->rqsm[n] : stat_mappings->tqsm[n]);
 409         return 0;
 410 }
 411
 412 static void
 413 txgbe_dcb_init(struct txgbe_hw *hw, struct txgbe_dcb_config *dcb_config)
 414 {
 415         int i;
 416         u8 bwgp;
 417         struct txgbe_dcb_tc_config *tc;
 418
 419         UNREFERENCED_PARAMETER(hw);
 420
 421         dcb_config->num_tcs.pg_tcs = TXGBE_DCB_TC_MAX;
 422         dcb_config->num_tcs.pfc_tcs = TXGBE_DCB_TC_MAX;
 423         bwgp = (u8)(100 / TXGBE_DCB_TC_MAX);
 424         for (i = 0; i < TXGBE_DCB_TC_MAX; i++) {
 425                 tc = &dcb_config->tc_config[i];
 426                 tc->path[TXGBE_DCB_TX_CONFIG].bwg_id = i;
 427                 tc->path[TXGBE_DCB_TX_CONFIG].bwg_percent = bwgp + (i & 1);
 428                 tc->path[TXGBE_DCB_RX_CONFIG].bwg_id = i;
 429                 tc->path[TXGBE_DCB_RX_CONFIG].bwg_percent = bwgp + (i & 1);
 430                 tc->pfc = txgbe_dcb_pfc_disabled;
 431         }
 432
 433         /* Initialize default user to priority mapping, UPx->TC0 */
 434         tc = &dcb_config->tc_config[0];
 435         tc->path[TXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
 436         tc->path[TXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
 437         for (i = 0; i < TXGBE_DCB_BWG_MAX; i++) {
 438                 dcb_config->bw_percentage[i][TXGBE_DCB_TX_CONFIG] = 100;
 439                 dcb_config->bw_percentage[i][TXGBE_DCB_RX_CONFIG] = 100;
 440         }
 441         dcb_config->rx_pba_cfg = txgbe_dcb_pba_equal;
 442         dcb_config->pfc_mode_enable = false;
 443         dcb_config->vt_mode = true;
 444         dcb_config->round_robin_enable = false;
 445         /* support all DCB capabilities */
 446         dcb_config->support.capabilities = 0xFF;
 447 }
 448
 449 /*
 450  * Ensure that all locks are released before first NVM or PHY access
 451  */
 452 static void
 453 txgbe_swfw_lock_reset(struct txgbe_hw *hw)
 454 {
 455         uint16_t mask;
 456
 457         /*
 458          * These ones are more tricky since they are common to all ports; but
 459          * swfw_sync retries last long enough (1s) to be almost sure that if
 460          * lock can not be taken it is due to an improper lock of the
 461          * semaphore.
 462          */
 463         mask = TXGBE_MNGSEM_SWPHY |
 464                TXGBE_MNGSEM_SWMBX |
 465                TXGBE_MNGSEM_SWFLASH;
 466         if (hw->mac.acquire_swfw_sync(hw, mask) < 0)
 467                 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
 468
 469         hw->mac.release_swfw_sync(hw, mask);
 470 }
 471
 472 static int
 473 eth_txgbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params __rte_unused)
 474 {
 475         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
 476         struct txgbe_hw *hw = TXGBE_DEV_HW(eth_dev);
 477         struct txgbe_vfta *shadow_vfta = TXGBE_DEV_VFTA(eth_dev);
 478         struct txgbe_hwstrip *hwstrip = TXGBE_DEV_HWSTRIP(eth_dev);
 479         struct txgbe_dcb_config *dcb_config = TXGBE_DEV_DCB_CONFIG(eth_dev);
 480         struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(eth_dev);
 481         struct txgbe_bw_conf *bw_conf = TXGBE_DEV_BW_CONF(eth_dev);
 482         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 483         const struct rte_memzone *mz;
 484         uint32_t ctrl_ext;
 485         uint16_t csum;
 486         int err, i, ret;
 487
 488         PMD_INIT_FUNC_TRACE();
 489
 490         eth_dev->dev_ops = &txgbe_eth_dev_ops;
 491         eth_dev->rx_queue_count       = txgbe_dev_rx_queue_count;
 492         eth_dev->rx_descriptor_status = txgbe_dev_rx_descriptor_status;
 493         eth_dev->tx_descriptor_status = txgbe_dev_tx_descriptor_status;
 494         eth_dev->rx_pkt_burst = &txgbe_recv_pkts;
 495         eth_dev->tx_pkt_burst = &txgbe_xmit_pkts;
 496         eth_dev->tx_pkt_prepare = &txgbe_prep_pkts;
 497
 498         /*
 499          * For secondary processes, we don't initialise any further as primary
 500          * has already done this work. Only check we don't need a different
 501          * RX and TX function.
 502          */
 503         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
 504                 struct txgbe_tx_queue *txq;
 505                 /* TX queue function in primary, set by last queue initialized
 506                  * Tx queue may not initialized by primary process
 507                  */
 508                 if (eth_dev->data->tx_queues) {
 509                         uint16_t nb_tx_queues = eth_dev->data->nb_tx_queues;
 510                         txq = eth_dev->data->tx_queues[nb_tx_queues - 1];
 511                         txgbe_set_tx_function(eth_dev, txq);
 512                 } else {
 513                         /* Use default TX function if we get here */
 514                         PMD_INIT_LOG(NOTICE, "No TX queues configured yet. "
 515                                      "Using default TX function.");
 516                 }
 517
 518                 txgbe_set_rx_function(eth_dev);
 519
 520                 return 0;
 521         }
 522
 523         rte_eth_copy_pci_info(eth_dev, pci_dev);
 524
 525         /* Vendor and Device ID need to be set before init of shared code */
 526         hw->device_id = pci_dev->id.device_id;
 527         hw->vendor_id = pci_dev->id.vendor_id;
 528         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
 529         hw->allow_unsupported_sfp = 1;
 530
 531         /* Reserve memory for interrupt status block */
 532         mz = rte_eth_dma_zone_reserve(eth_dev, "txgbe_driver", -1,
 533                 16, TXGBE_ALIGN, SOCKET_ID_ANY);
 534         if (mz == NULL)
 535                 return -ENOMEM;
 536
 537         hw->isb_dma = TMZ_PADDR(mz);
 538         hw->isb_mem = TMZ_VADDR(mz);
 539
 540         /* Initialize the shared code (base driver) */
 541         err = txgbe_init_shared_code(hw);
 542         if (err != 0) {
 543                 PMD_INIT_LOG(ERR, "Shared code init failed: %d", err);
 544                 return -EIO;
 545         }
 546
 547         /* Unlock any pending hardware semaphore */
 548         txgbe_swfw_lock_reset(hw);
 549
 550         /* Initialize DCB configuration*/
 551         memset(dcb_config, 0, sizeof(struct txgbe_dcb_config));
 552         txgbe_dcb_init(hw, dcb_config);
 553
 554         /* Get Hardware Flow Control setting */
 555         hw->fc.requested_mode = txgbe_fc_full;
 556         hw->fc.current_mode = txgbe_fc_full;
 557         hw->fc.pause_time = TXGBE_FC_PAUSE_TIME;
 558         for (i = 0; i < TXGBE_DCB_TC_MAX; i++) {
 559                 hw->fc.low_water[i] = TXGBE_FC_XON_LOTH;
 560                 hw->fc.high_water[i] = TXGBE_FC_XOFF_HITH;
 561         }
 562         hw->fc.send_xon = 1;
 563
 564         err = hw->rom.init_params(hw);
 565         if (err != 0) {
 566                 PMD_INIT_LOG(ERR, "The EEPROM init failed: %d", err);
 567                 return -EIO;
 568         }
 569
 570         /* Make sure we have a good EEPROM before we read from it */
 571         err = hw->rom.validate_checksum(hw, &csum);
 572         if (err != 0) {
 573                 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", err);
 574                 return -EIO;
 575         }
 576
 577         err = hw->mac.init_hw(hw);
 578
 579         /*
 580          * Devices with copper phys will fail to initialise if txgbe_init_hw()
 581          * is called too soon after the kernel driver unbinding/binding occurs.
 582          * The failure occurs in txgbe_identify_phy() for all devices,
 583          * but for non-copper devies, txgbe_identify_sfp_module() is
 584          * also called. See txgbe_identify_phy(). The reason for the
 585          * failure is not known, and only occuts when virtualisation features
 586          * are disabled in the bios. A delay of 200ms  was found to be enough by
 587          * trial-and-error, and is doubled to be safe.
 588          */
 589         if (err && hw->phy.media_type == txgbe_media_type_copper) {
 590                 rte_delay_ms(200);
 591                 err = hw->mac.init_hw(hw);
 592         }
 593
 594         if (err == TXGBE_ERR_SFP_NOT_PRESENT)
 595                 err = 0;
 596
 597         if (err == TXGBE_ERR_EEPROM_VERSION) {
 598                 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
 599                              "LOM.  Please be aware there may be issues associated "
 600                              "with your hardware.");
 601                 PMD_INIT_LOG(ERR, "If you are experiencing problems "
 602                              "please contact your hardware representative "
 603                              "who provided you with this hardware.");
 604         } else if (err == TXGBE_ERR_SFP_NOT_SUPPORTED) {
 605                 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
 606         }
 607         if (err) {
 608                 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", err);
 609                 return -EIO;
 610         }
 611
 612         /* Reset the hw statistics */
 613         txgbe_dev_stats_reset(eth_dev);
 614
 615         /* disable interrupt */
 616         txgbe_disable_intr(hw);
 617
 618         /* Allocate memory for storing MAC addresses */
 619         eth_dev->data->mac_addrs = rte_zmalloc("txgbe", RTE_ETHER_ADDR_LEN *
 620                                                hw->mac.num_rar_entries, 0);
 621         if (eth_dev->data->mac_addrs == NULL) {
 622                 PMD_INIT_LOG(ERR,
 623                              "Failed to allocate %u bytes needed to store "
 624                              "MAC addresses",
 625                              RTE_ETHER_ADDR_LEN * hw->mac.num_rar_entries);
 626                 return -ENOMEM;
 627         }
 628
 629         /* Copy the permanent MAC address */
 630         rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.perm_addr,
 631                         &eth_dev->data->mac_addrs[0]);
 632
 633         /* Allocate memory for storing hash filter MAC addresses */
 634         eth_dev->data->hash_mac_addrs = rte_zmalloc("txgbe",
 635                         RTE_ETHER_ADDR_LEN * TXGBE_VMDQ_NUM_UC_MAC, 0);
 636         if (eth_dev->data->hash_mac_addrs == NULL) {
 637                 PMD_INIT_LOG(ERR,
 638                              "Failed to allocate %d bytes needed to store MAC addresses",
 639                              RTE_ETHER_ADDR_LEN * TXGBE_VMDQ_NUM_UC_MAC);
 640                 return -ENOMEM;
 641         }
 642
 643         /* initialize the vfta */
 644         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
 645
 646         /* initialize the hw strip bitmap*/
 647         memset(hwstrip, 0, sizeof(*hwstrip));
 648
 649         /* initialize PF if max_vfs not zero */
 650         ret = txgbe_pf_host_init(eth_dev);
 651         if (ret) {
 652                 rte_free(eth_dev->data->mac_addrs);
 653                 eth_dev->data->mac_addrs = NULL;
 654                 rte_free(eth_dev->data->hash_mac_addrs);
 655                 eth_dev->data->hash_mac_addrs = NULL;
 656                 return ret;
 657         }
 658
 659         ctrl_ext = rd32(hw, TXGBE_PORTCTL);
 660         /* let hardware know driver is loaded */
 661         ctrl_ext |= TXGBE_PORTCTL_DRVLOAD;
 662         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 663         ctrl_ext |= TXGBE_PORTCTL_RSTDONE;
 664         wr32(hw, TXGBE_PORTCTL, ctrl_ext);
 665         txgbe_flush(hw);
 666
 667         if (txgbe_is_sfp(hw) && hw->phy.sfp_type != txgbe_sfp_type_not_present)
 668                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
 669                              (int)hw->mac.type, (int)hw->phy.type,
 670                              (int)hw->phy.sfp_type);
 671         else
 672                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
 673                              (int)hw->mac.type, (int)hw->phy.type);
 674
 675         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
 676                      eth_dev->data->port_id, pci_dev->id.vendor_id,
 677                      pci_dev->id.device_id);
 678
 679         rte_intr_callback_register(intr_handle,
 680                                    txgbe_dev_interrupt_handler, eth_dev);
 681
 682         /* enable uio/vfio intr/eventfd mapping */
 683         rte_intr_enable(intr_handle);
 684
 685         /* enable support intr */
 686         txgbe_enable_intr(eth_dev);
 687
 688         /* initialize filter info */
 689         memset(filter_info, 0,
 690                sizeof(struct txgbe_filter_info));
 691
 692         /* initialize 5tuple filter list */
 693         TAILQ_INIT(&filter_info->fivetuple_list);
 694
 695         /* initialize flow director filter list & hash */
 696         txgbe_fdir_filter_init(eth_dev);
 697
 698         /* initialize l2 tunnel filter list & hash */
 699         txgbe_l2_tn_filter_init(eth_dev);
 700
 701         /* initialize bandwidth configuration info */
 702         memset(bw_conf, 0, sizeof(struct txgbe_bw_conf));
 703
 704         return 0;
 705 }
 706
 707 static int
 708 eth_txgbe_dev_uninit(struct rte_eth_dev *eth_dev)
 709 {
 710         PMD_INIT_FUNC_TRACE();
 711
 712         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 713                 return 0;
 714
 715         txgbe_dev_close(eth_dev);
 716
 717         return 0;
 718 }
 719
 720 static int txgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev)
 721 {
 722         struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(eth_dev);
 723         struct txgbe_5tuple_filter *p_5tuple;
 724
 725         while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) {
 726                 TAILQ_REMOVE(&filter_info->fivetuple_list,
 727                              p_5tuple,
 728                              entries);
 729                 rte_free(p_5tuple);
 730         }
 731         memset(filter_info->fivetuple_mask, 0,
 732                sizeof(uint32_t) * TXGBE_5TUPLE_ARRAY_SIZE);
 733
 734         return 0;
 735 }
 736
 737 static int txgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev)
 738 {
 739         struct txgbe_hw_fdir_info *fdir_info = TXGBE_DEV_FDIR(eth_dev);
 740         struct txgbe_fdir_filter *fdir_filter;
 741
 742         if (fdir_info->hash_map)
 743                 rte_free(fdir_info->hash_map);
 744         if (fdir_info->hash_handle)
 745                 rte_hash_free(fdir_info->hash_handle);
 746
 747         while ((fdir_filter = TAILQ_FIRST(&fdir_info->fdir_list))) {
 748                 TAILQ_REMOVE(&fdir_info->fdir_list,
 749                              fdir_filter,
 750                              entries);
 751                 rte_free(fdir_filter);
 752         }
 753
 754         return 0;
 755 }
 756
 757 static int txgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev)
 758 {
 759         struct txgbe_l2_tn_info *l2_tn_info = TXGBE_DEV_L2_TN(eth_dev);
 760         struct txgbe_l2_tn_filter *l2_tn_filter;
 761
 762         if (l2_tn_info->hash_map)
 763                 rte_free(l2_tn_info->hash_map);
 764         if (l2_tn_info->hash_handle)
 765                 rte_hash_free(l2_tn_info->hash_handle);
 766
 767         while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
 768                 TAILQ_REMOVE(&l2_tn_info->l2_tn_list,
 769                              l2_tn_filter,
 770                              entries);
 771                 rte_free(l2_tn_filter);
 772         }
 773
 774         return 0;
 775 }
 776
 777 static int txgbe_fdir_filter_init(struct rte_eth_dev *eth_dev)
 778 {
 779         struct txgbe_hw_fdir_info *fdir_info = TXGBE_DEV_FDIR(eth_dev);
 780         char fdir_hash_name[RTE_HASH_NAMESIZE];
 781         struct rte_hash_parameters fdir_hash_params = {
 782                 .name = fdir_hash_name,
 783                 .entries = TXGBE_MAX_FDIR_FILTER_NUM,
 784                 .key_len = sizeof(struct txgbe_atr_input),
 785                 .hash_func = rte_hash_crc,
 786                 .hash_func_init_val = 0,
 787                 .socket_id = rte_socket_id(),
 788         };
 789
 790         TAILQ_INIT(&fdir_info->fdir_list);
 791         snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
 792                  "fdir_%s", TDEV_NAME(eth_dev));
 793         fdir_info->hash_handle = rte_hash_create(&fdir_hash_params);
 794         if (!fdir_info->hash_handle) {
 795                 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
 796                 return -EINVAL;
 797         }
 798         fdir_info->hash_map = rte_zmalloc("txgbe",
 799                                           sizeof(struct txgbe_fdir_filter *) *
 800                                           TXGBE_MAX_FDIR_FILTER_NUM,
 801                                           0);
 802         if (!fdir_info->hash_map) {
 803                 PMD_INIT_LOG(ERR,
 804                              "Failed to allocate memory for fdir hash map!");
 805                 return -ENOMEM;
 806         }
 807         fdir_info->mask_added = FALSE;
 808
 809         return 0;
 810 }
 811
 812 static int txgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev)
 813 {
 814         struct txgbe_l2_tn_info *l2_tn_info = TXGBE_DEV_L2_TN(eth_dev);
 815         char l2_tn_hash_name[RTE_HASH_NAMESIZE];
 816         struct rte_hash_parameters l2_tn_hash_params = {
 817                 .name = l2_tn_hash_name,
 818                 .entries = TXGBE_MAX_L2_TN_FILTER_NUM,
 819                 .key_len = sizeof(struct txgbe_l2_tn_key),
 820                 .hash_func = rte_hash_crc,
 821                 .hash_func_init_val = 0,
 822                 .socket_id = rte_socket_id(),
 823         };
 824
 825         TAILQ_INIT(&l2_tn_info->l2_tn_list);
 826         snprintf(l2_tn_hash_name, RTE_HASH_NAMESIZE,
 827                  "l2_tn_%s", TDEV_NAME(eth_dev));
 828         l2_tn_info->hash_handle = rte_hash_create(&l2_tn_hash_params);
 829         if (!l2_tn_info->hash_handle) {
 830                 PMD_INIT_LOG(ERR, "Failed to create L2 TN hash table!");
 831                 return -EINVAL;
 832         }
 833         l2_tn_info->hash_map = rte_zmalloc("txgbe",
 834                                    sizeof(struct txgbe_l2_tn_filter *) *
 835                                    TXGBE_MAX_L2_TN_FILTER_NUM,
 836                                    0);
 837         if (!l2_tn_info->hash_map) {
 838                 PMD_INIT_LOG(ERR,
 839                         "Failed to allocate memory for L2 TN hash map!");
 840                 return -ENOMEM;
 841         }
 842         l2_tn_info->e_tag_en = FALSE;
 843         l2_tn_info->e_tag_fwd_en = FALSE;
 844         l2_tn_info->e_tag_ether_type = RTE_ETHER_TYPE_ETAG;
 845
 846         return 0;
 847 }
 848
 849 static int
 850 eth_txgbe_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
 851                 struct rte_pci_device *pci_dev)
 852 {
 853         struct rte_eth_dev *pf_ethdev;
 854         struct rte_eth_devargs eth_da;
 855         int retval;
 856
 857         if (pci_dev->device.devargs) {
 858                 retval = rte_eth_devargs_parse(pci_dev->device.devargs->args,
 859                                 &eth_da);
 860                 if (retval)
 861                         return retval;
 862         } else {
 863                 memset(&eth_da, 0, sizeof(eth_da));
 864         }
 865
 866         retval = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
 867                         sizeof(struct txgbe_adapter),
 868                         eth_dev_pci_specific_init, pci_dev,
 869                         eth_txgbe_dev_init, NULL);
 870
 871         if (retval || eth_da.nb_representor_ports < 1)
 872                 return retval;
 873
 874         pf_ethdev = rte_eth_dev_allocated(pci_dev->device.name);
 875         if (pf_ethdev == NULL)
 876                 return -ENODEV;
 877
 878         return 0;
 879 }
 880
 881 static int eth_txgbe_pci_remove(struct rte_pci_device *pci_dev)
 882 {
 883         struct rte_eth_dev *ethdev;
 884
 885         ethdev = rte_eth_dev_allocated(pci_dev->device.name);
 886         if (!ethdev)
 887                 return -ENODEV;
 888
 889         return rte_eth_dev_destroy(ethdev, eth_txgbe_dev_uninit);
 890 }
 891
 892 static struct rte_pci_driver rte_txgbe_pmd = {
 893         .id_table = pci_id_txgbe_map,
 894         .drv_flags = RTE_PCI_DRV_NEED_MAPPING |
 895                      RTE_PCI_DRV_INTR_LSC,
 896         .probe = eth_txgbe_pci_probe,
 897         .remove = eth_txgbe_pci_remove,
 898 };
 899
 900 static int
 901 txgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
 902 {
 903         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
 904         struct txgbe_vfta *shadow_vfta = TXGBE_DEV_VFTA(dev);
 905         uint32_t vfta;
 906         uint32_t vid_idx;
 907         uint32_t vid_bit;
 908
 909         vid_idx = (uint32_t)((vlan_id >> 5) & 0x7F);
 910         vid_bit = (uint32_t)(1 << (vlan_id & 0x1F));
 911         vfta = rd32(hw, TXGBE_VLANTBL(vid_idx));
 912         if (on)
 913                 vfta |= vid_bit;
 914         else
 915                 vfta &= ~vid_bit;
 916         wr32(hw, TXGBE_VLANTBL(vid_idx), vfta);
 917
 918         /* update local VFTA copy */
 919         shadow_vfta->vfta[vid_idx] = vfta;
 920
 921         return 0;
 922 }
 923
 924 static void
 925 txgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
 926 {
 927         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
 928         struct txgbe_rx_queue *rxq;
 929         bool restart;
 930         uint32_t rxcfg, rxbal, rxbah;
 931
 932         if (on)
 933                 txgbe_vlan_hw_strip_enable(dev, queue);
 934         else
 935                 txgbe_vlan_hw_strip_disable(dev, queue);
 936
 937         rxq = dev->data->rx_queues[queue];
 938         rxbal = rd32(hw, TXGBE_RXBAL(rxq->reg_idx));
 939         rxbah = rd32(hw, TXGBE_RXBAH(rxq->reg_idx));
 940         rxcfg = rd32(hw, TXGBE_RXCFG(rxq->reg_idx));
 941         if (rxq->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) {
 942                 restart = (rxcfg & TXGBE_RXCFG_ENA) &&
 943                         !(rxcfg & TXGBE_RXCFG_VLAN);
 944                 rxcfg |= TXGBE_RXCFG_VLAN;
 945         } else {
 946                 restart = (rxcfg & TXGBE_RXCFG_ENA) &&
 947                         (rxcfg & TXGBE_RXCFG_VLAN);
 948                 rxcfg &= ~TXGBE_RXCFG_VLAN;
 949         }
 950         rxcfg &= ~TXGBE_RXCFG_ENA;
 951
 952         if (restart) {
 953                 /* set vlan strip for ring */
 954                 txgbe_dev_rx_queue_stop(dev, queue);
 955                 wr32(hw, TXGBE_RXBAL(rxq->reg_idx), rxbal);
 956                 wr32(hw, TXGBE_RXBAH(rxq->reg_idx), rxbah);
 957                 wr32(hw, TXGBE_RXCFG(rxq->reg_idx), rxcfg);
 958                 txgbe_dev_rx_queue_start(dev, queue);
 959         }
 960 }
 961
 962 static int
 963 txgbe_vlan_tpid_set(struct rte_eth_dev *dev,
 964                     enum rte_vlan_type vlan_type,
 965                     uint16_t tpid)
 966 {
 967         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
 968         int ret = 0;
 969         uint32_t portctrl, vlan_ext, qinq;
 970
 971         portctrl = rd32(hw, TXGBE_PORTCTL);
 972
 973         vlan_ext = (portctrl & TXGBE_PORTCTL_VLANEXT);
 974         qinq = vlan_ext && (portctrl & TXGBE_PORTCTL_QINQ);
 975         switch (vlan_type) {
 976         case ETH_VLAN_TYPE_INNER:
 977                 if (vlan_ext) {
 978                         wr32m(hw, TXGBE_VLANCTL,
 979                                 TXGBE_VLANCTL_TPID_MASK,
 980                                 TXGBE_VLANCTL_TPID(tpid));
 981                         wr32m(hw, TXGBE_DMATXCTRL,
 982                                 TXGBE_DMATXCTRL_TPID_MASK,
 983                                 TXGBE_DMATXCTRL_TPID(tpid));
 984                 } else {
 985                         ret = -ENOTSUP;
 986                         PMD_DRV_LOG(ERR, "Inner type is not supported"
 987                                     " by single VLAN");
 988                 }
 989
 990                 if (qinq) {
 991                         wr32m(hw, TXGBE_TAGTPID(0),
 992                                 TXGBE_TAGTPID_LSB_MASK,
 993                                 TXGBE_TAGTPID_LSB(tpid));
 994                 }
 995                 break;
 996         case ETH_VLAN_TYPE_OUTER:
 997                 if (vlan_ext) {
 998                         /* Only the high 16-bits is valid */
 999                         wr32m(hw, TXGBE_EXTAG,
1000                                 TXGBE_EXTAG_VLAN_MASK,
1001                                 TXGBE_EXTAG_VLAN(tpid));
1002                 } else {
1003                         wr32m(hw, TXGBE_VLANCTL,
1004                                 TXGBE_VLANCTL_TPID_MASK,
1005                                 TXGBE_VLANCTL_TPID(tpid));
1006                         wr32m(hw, TXGBE_DMATXCTRL,
1007                                 TXGBE_DMATXCTRL_TPID_MASK,
1008                                 TXGBE_DMATXCTRL_TPID(tpid));
1009                 }
1010
1011                 if (qinq) {
1012                         wr32m(hw, TXGBE_TAGTPID(0),
1013                                 TXGBE_TAGTPID_MSB_MASK,
1014                                 TXGBE_TAGTPID_MSB(tpid));
1015                 }
1016                 break;
1017         default:
1018                 PMD_DRV_LOG(ERR, "Unsupported VLAN type %d", vlan_type);
1019                 return -EINVAL;
1020         }
1021
1022         return ret;
1023 }
1024
1025 void
1026 txgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1027 {
1028         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
1029         uint32_t vlnctrl;
1030
1031         PMD_INIT_FUNC_TRACE();
1032
1033         /* Filter Table Disable */
1034         vlnctrl = rd32(hw, TXGBE_VLANCTL);
1035         vlnctrl &= ~TXGBE_VLANCTL_VFE;
1036         wr32(hw, TXGBE_VLANCTL, vlnctrl);
1037 }
1038
1039 void
1040 txgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1041 {
1042         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
1043         struct txgbe_vfta *shadow_vfta = TXGBE_DEV_VFTA(dev);
1044         uint32_t vlnctrl;
1045         uint16_t i;
1046
1047         PMD_INIT_FUNC_TRACE();
1048
1049         /* Filter Table Enable */
1050         vlnctrl = rd32(hw, TXGBE_VLANCTL);
1051         vlnctrl &= ~TXGBE_VLANCTL_CFIENA;
1052         vlnctrl |= TXGBE_VLANCTL_VFE;
1053         wr32(hw, TXGBE_VLANCTL, vlnctrl);
1054
1055         /* write whatever is in local vfta copy */
1056         for (i = 0; i < TXGBE_VFTA_SIZE; i++)
1057                 wr32(hw, TXGBE_VLANTBL(i), shadow_vfta->vfta[i]);
1058 }
1059
1060 void
1061 txgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1062 {
1063         struct txgbe_hwstrip *hwstrip = TXGBE_DEV_HWSTRIP(dev);
1064         struct txgbe_rx_queue *rxq;
1065
1066         if (queue >= TXGBE_MAX_RX_QUEUE_NUM)
1067                 return;
1068
1069         if (on)
1070                 TXGBE_SET_HWSTRIP(hwstrip, queue);
1071         else
1072                 TXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1073
1074         if (queue >= dev->data->nb_rx_queues)
1075                 return;
1076
1077         rxq = dev->data->rx_queues[queue];
1078
1079         if (on) {
1080                 rxq->vlan_flags = PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
1081                 rxq->offloads |= DEV_RX_OFFLOAD_VLAN_STRIP;
1082         } else {
1083                 rxq->vlan_flags = PKT_RX_VLAN;
1084                 rxq->offloads &= ~DEV_RX_OFFLOAD_VLAN_STRIP;
1085         }
1086 }
1087
1088 static void
1089 txgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
1090 {
1091         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
1092         uint32_t ctrl;
1093
1094         PMD_INIT_FUNC_TRACE();
1095
1096         ctrl = rd32(hw, TXGBE_RXCFG(queue));
1097         ctrl &= ~TXGBE_RXCFG_VLAN;
1098         wr32(hw, TXGBE_RXCFG(queue), ctrl);
1099
1100         /* record those setting for HW strip per queue */
1101         txgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
1102 }
1103
1104 static void
1105 txgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
1106 {
1107         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
1108         uint32_t ctrl;
1109
1110         PMD_INIT_FUNC_TRACE();
1111
1112         ctrl = rd32(hw, TXGBE_RXCFG(queue));
1113         ctrl |= TXGBE_RXCFG_VLAN;
1114         wr32(hw, TXGBE_RXCFG(queue), ctrl);
1115
1116         /* record those setting for HW strip per queue */
1117         txgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
1118 }
1119
1120 static void
1121 txgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
1122 {
1123         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
1124         uint32_t ctrl;
1125
1126         PMD_INIT_FUNC_TRACE();
1127
1128         ctrl = rd32(hw, TXGBE_PORTCTL);
1129         ctrl &= ~TXGBE_PORTCTL_VLANEXT;
1130         ctrl &= ~TXGBE_PORTCTL_QINQ;
1131         wr32(hw, TXGBE_PORTCTL, ctrl);
1132 }
1133
1134 static void
1135 txgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
1136 {
1137         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
1138         struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
1139         struct rte_eth_txmode *txmode = &dev->data->dev_conf.txmode;
1140         uint32_t ctrl;
1141
1142         PMD_INIT_FUNC_TRACE();
1143
1144         ctrl  = rd32(hw, TXGBE_PORTCTL);
1145         ctrl |= TXGBE_PORTCTL_VLANEXT;
1146         if (rxmode->offloads & DEV_RX_OFFLOAD_QINQ_STRIP ||
1147             txmode->offloads & DEV_TX_OFFLOAD_QINQ_INSERT)
1148                 ctrl |= TXGBE_PORTCTL_QINQ;
1149         wr32(hw, TXGBE_PORTCTL, ctrl);
1150 }
1151
1152 void
1153 txgbe_vlan_hw_strip_config(struct rte_eth_dev *dev)
1154 {
1155         struct txgbe_rx_queue *rxq;
1156         uint16_t i;
1157
1158         PMD_INIT_FUNC_TRACE();
1159
1160         for (i = 0; i < dev->data->nb_rx_queues; i++) {
1161                 rxq = dev->data->rx_queues[i];
1162
1163                 if (rxq->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1164                         txgbe_vlan_strip_queue_set(dev, i, 1);
1165                 else
1166                         txgbe_vlan_strip_queue_set(dev, i, 0);
1167         }
1168 }
1169
1170 void
1171 txgbe_config_vlan_strip_on_all_queues(struct rte_eth_dev *dev, int mask)
1172 {
1173         uint16_t i;
1174         struct rte_eth_rxmode *rxmode;
1175         struct txgbe_rx_queue *rxq;
1176
1177         if (mask & ETH_VLAN_STRIP_MASK) {
1178                 rxmode = &dev->data->dev_conf.rxmode;
1179                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1180                         for (i = 0; i < dev->data->nb_rx_queues; i++) {
1181                                 rxq = dev->data->rx_queues[i];
1182                                 rxq->offloads |= DEV_RX_OFFLOAD_VLAN_STRIP;
1183                         }
1184                 else
1185                         for (i = 0; i < dev->data->nb_rx_queues; i++) {
1186                                 rxq = dev->data->rx_queues[i];
1187                                 rxq->offloads &= ~DEV_RX_OFFLOAD_VLAN_STRIP;
1188                         }
1189         }
1190 }
1191
1192 static int
1193 txgbe_vlan_offload_config(struct rte_eth_dev *dev, int mask)
1194 {
1195         struct rte_eth_rxmode *rxmode;
1196         rxmode = &dev->data->dev_conf.rxmode;
1197
1198         if (mask & ETH_VLAN_STRIP_MASK)
1199                 txgbe_vlan_hw_strip_config(dev);
1200
1201         if (mask & ETH_VLAN_FILTER_MASK) {
1202                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
1203                         txgbe_vlan_hw_filter_enable(dev);
1204                 else
1205                         txgbe_vlan_hw_filter_disable(dev);
1206         }
1207
1208         if (mask & ETH_VLAN_EXTEND_MASK) {
1209                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
1210                         txgbe_vlan_hw_extend_enable(dev);
1211                 else
1212                         txgbe_vlan_hw_extend_disable(dev);
1213         }
1214
1215         return 0;
1216 }
1217
1218 static int
1219 txgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1220 {
1221         txgbe_config_vlan_strip_on_all_queues(dev, mask);
1222
1223         txgbe_vlan_offload_config(dev, mask);
1224
1225         return 0;
1226 }
1227
1228 static void
1229 txgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1230 {
1231         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
1232         /* VLNCTL: enable vlan filtering and allow all vlan tags through */
1233         uint32_t vlanctrl = rd32(hw, TXGBE_VLANCTL);
1234
1235         vlanctrl |= TXGBE_VLANCTL_VFE; /* enable vlan filters */
1236         wr32(hw, TXGBE_VLANCTL, vlanctrl);
1237 }
1238
1239 static int
1240 txgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q)
1241 {
1242         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1243
1244         switch (nb_rx_q) {
1245         case 1:
1246         case 2:
1247                 RTE_ETH_DEV_SRIOV(dev).active = ETH_64_POOLS;
1248                 break;
1249         case 4:
1250                 RTE_ETH_DEV_SRIOV(dev).active = ETH_32_POOLS;
1251                 break;
1252         default:
1253                 return -EINVAL;
1254         }
1255
1256         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool =
1257                 TXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
1258         RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx =
1259                 pci_dev->max_vfs * RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
1260         return 0;
1261 }
1262
1263 static int
1264 txgbe_check_mq_mode(struct rte_eth_dev *dev)
1265 {
1266         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
1267         uint16_t nb_rx_q = dev->data->nb_rx_queues;
1268         uint16_t nb_tx_q = dev->data->nb_tx_queues;
1269
1270         if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
1271                 /* check multi-queue mode */
1272                 switch (dev_conf->rxmode.mq_mode) {
1273                 case ETH_MQ_RX_VMDQ_DCB:
1274                         PMD_INIT_LOG(INFO, "ETH_MQ_RX_VMDQ_DCB mode supported in SRIOV");
1275                         break;
1276                 case ETH_MQ_RX_VMDQ_DCB_RSS:
1277                         /* DCB/RSS VMDQ in SRIOV mode, not implement yet */
1278                         PMD_INIT_LOG(ERR, "SRIOV active,"
1279                                         " unsupported mq_mode rx %d.",
1280                                         dev_conf->rxmode.mq_mode);
1281                         return -EINVAL;
1282                 case ETH_MQ_RX_RSS:
1283                 case ETH_MQ_RX_VMDQ_RSS:
1284                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_RSS;
1285                         if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)
1286                                 if (txgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) {
1287                                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1288                                                 " invalid queue number"
1289                                                 " for VMDQ RSS, allowed"
1290                                                 " value are 1, 2 or 4.");
1291                                         return -EINVAL;
1292                                 }
1293                         break;
1294                 case ETH_MQ_RX_VMDQ_ONLY:
1295                 case ETH_MQ_RX_NONE:
1296                         /* if nothing mq mode configure, use default scheme */
1297                         dev->data->dev_conf.rxmode.mq_mode =
1298                                 ETH_MQ_RX_VMDQ_ONLY;
1299                         break;
1300                 default: /* ETH_MQ_RX_DCB, ETH_MQ_RX_DCB_RSS or ETH_MQ_TX_DCB*/
1301                         /* SRIOV only works in VMDq enable mode */
1302                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1303                                         " wrong mq_mode rx %d.",
1304                                         dev_conf->rxmode.mq_mode);
1305                         return -EINVAL;
1306                 }
1307
1308                 switch (dev_conf->txmode.mq_mode) {
1309                 case ETH_MQ_TX_VMDQ_DCB:
1310                         PMD_INIT_LOG(INFO, "ETH_MQ_TX_VMDQ_DCB mode supported in SRIOV");
1311                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_DCB;
1312                         break;
1313                 default: /* ETH_MQ_TX_VMDQ_ONLY or ETH_MQ_TX_NONE */
1314                         dev->data->dev_conf.txmode.mq_mode =
1315                                 ETH_MQ_TX_VMDQ_ONLY;
1316                         break;
1317                 }
1318
1319                 /* check valid queue number */
1320                 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) ||
1321                     (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) {
1322                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1323                                         " nb_rx_q=%d nb_tx_q=%d queue number"
1324                                         " must be less than or equal to %d.",
1325                                         nb_rx_q, nb_tx_q,
1326                                         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool);
1327                         return -EINVAL;
1328                 }
1329         } else {
1330                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
1331                         PMD_INIT_LOG(ERR, "VMDQ+DCB+RSS mq_mode is"
1332                                           " not supported.");
1333                         return -EINVAL;
1334                 }
1335                 /* check configuration for vmdb+dcb mode */
1336                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB) {
1337                         const struct rte_eth_vmdq_dcb_conf *conf;
1338
1339                         if (nb_rx_q != TXGBE_VMDQ_DCB_NB_QUEUES) {
1340                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.",
1341                                                 TXGBE_VMDQ_DCB_NB_QUEUES);
1342                                 return -EINVAL;
1343                         }
1344                         conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf;
1345                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
1346                                conf->nb_queue_pools == ETH_32_POOLS)) {
1347                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
1348                                                 " nb_queue_pools must be %d or %d.",
1349                                                 ETH_16_POOLS, ETH_32_POOLS);
1350                                 return -EINVAL;
1351                         }
1352                 }
1353                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) {
1354                         const struct rte_eth_vmdq_dcb_tx_conf *conf;
1355
1356                         if (nb_tx_q != TXGBE_VMDQ_DCB_NB_QUEUES) {
1357                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d",
1358                                                  TXGBE_VMDQ_DCB_NB_QUEUES);
1359                                 return -EINVAL;
1360                         }
1361                         conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf;
1362                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
1363                                conf->nb_queue_pools == ETH_32_POOLS)) {
1364                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
1365                                                 " nb_queue_pools != %d and"
1366                                                 " nb_queue_pools != %d.",
1367                                                 ETH_16_POOLS, ETH_32_POOLS);
1368                                 return -EINVAL;
1369                         }
1370                 }
1371
1372                 /* For DCB mode check our configuration before we go further */
1373                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_DCB) {
1374                         const struct rte_eth_dcb_rx_conf *conf;
1375
1376                         conf = &dev_conf->rx_adv_conf.dcb_rx_conf;
1377                         if (!(conf->nb_tcs == ETH_4_TCS ||
1378                                conf->nb_tcs == ETH_8_TCS)) {
1379                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
1380                                                 " and nb_tcs != %d.",
1381                                                 ETH_4_TCS, ETH_8_TCS);
1382                                 return -EINVAL;
1383                         }
1384                 }
1385
1386                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_DCB) {
1387                         const struct rte_eth_dcb_tx_conf *conf;
1388
1389                         conf = &dev_conf->tx_adv_conf.dcb_tx_conf;
1390                         if (!(conf->nb_tcs == ETH_4_TCS ||
1391                                conf->nb_tcs == ETH_8_TCS)) {
1392                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
1393                                                 " and nb_tcs != %d.",
1394                                                 ETH_4_TCS, ETH_8_TCS);
1395                                 return -EINVAL;
1396                         }
1397                 }
1398         }
1399         return 0;
1400 }
1401
1402 static int
1403 txgbe_dev_configure(struct rte_eth_dev *dev)
1404 {
1405         struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);
1406         struct txgbe_adapter *adapter = TXGBE_DEV_ADAPTER(dev);
1407         int ret;
1408
1409         PMD_INIT_FUNC_TRACE();
1410
1411         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
1412                 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
1413
1414         /* multiple queue mode checking */
1415         ret  = txgbe_check_mq_mode(dev);
1416         if (ret != 0) {
1417                 PMD_DRV_LOG(ERR, "txgbe_check_mq_mode fails with %d.",
1418                             ret);
1419                 return ret;
1420         }
1421
1422         /* set flag to update link status after init */
1423         intr->flags |= TXGBE_FLAG_NEED_LINK_UPDATE;
1424
1425         /*
1426          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
1427          * allocation Rx preconditions we will reset it.
1428          */
1429         adapter->rx_bulk_alloc_allowed = true;
1430
1431         return 0;
1432 }
1433
1434 static void
1435 txgbe_dev_phy_intr_setup(struct rte_eth_dev *dev)
1436 {
1437         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
1438         struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);
1439         uint32_t gpie;
1440
1441         gpie = rd32(hw, TXGBE_GPIOINTEN);
1442         gpie |= TXGBE_GPIOBIT_6;
1443         wr32(hw, TXGBE_GPIOINTEN, gpie);
1444         intr->mask_misc |= TXGBE_ICRMISC_GPIO;
1445 }
1446
1447 int
1448 txgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
1449                         uint16_t tx_rate, uint64_t q_msk)
1450 {
1451         struct txgbe_hw *hw;
1452         struct txgbe_vf_info *vfinfo;
1453         struct rte_eth_link link;
1454         uint8_t  nb_q_per_pool;
1455         uint32_t queue_stride;
1456         uint32_t queue_idx, idx = 0, vf_idx;
1457         uint32_t queue_end;
1458         uint16_t total_rate = 0;
1459         struct rte_pci_device *pci_dev;
1460         int ret;
1461
1462         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1463         ret = rte_eth_link_get_nowait(dev->data->port_id, &link);
1464         if (ret < 0)
1465                 return ret;
1466
1467         if (vf >= pci_dev->max_vfs)
1468                 return -EINVAL;
1469
1470         if (tx_rate > link.link_speed)
1471                 return -EINVAL;
1472
1473         if (q_msk == 0)
1474                 return 0;
1475
1476         hw = TXGBE_DEV_HW(dev);
1477         vfinfo = *(TXGBE_DEV_VFDATA(dev));
1478         nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
1479         queue_stride = TXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
1480         queue_idx = vf * queue_stride;
1481         queue_end = queue_idx + nb_q_per_pool - 1;
1482         if (queue_end >= hw->mac.max_tx_queues)
1483                 return -EINVAL;
1484
1485         if (vfinfo) {
1486                 for (vf_idx = 0; vf_idx < pci_dev->max_vfs; vf_idx++) {
1487                         if (vf_idx == vf)
1488                                 continue;
1489                         for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
1490                                 idx++)
1491                                 total_rate += vfinfo[vf_idx].tx_rate[idx];
1492                 }
1493         } else {
1494                 return -EINVAL;
1495         }
1496
1497         /* Store tx_rate for this vf. */
1498         for (idx = 0; idx < nb_q_per_pool; idx++) {
1499                 if (((uint64_t)0x1 << idx) & q_msk) {
1500                         if (vfinfo[vf].tx_rate[idx] != tx_rate)
1501                                 vfinfo[vf].tx_rate[idx] = tx_rate;
1502                         total_rate += tx_rate;
1503                 }
1504         }
1505
1506         if (total_rate > dev->data->dev_link.link_speed) {
1507                 /* Reset stored TX rate of the VF if it causes exceed
1508                  * link speed.
1509                  */
1510                 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
1511                 return -EINVAL;
1512         }
1513
1514         /* Set ARBTXRATE of each queue/pool for vf X  */
1515         for (; queue_idx <= queue_end; queue_idx++) {
1516                 if (0x1 & q_msk)
1517                         txgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
1518                 q_msk = q_msk >> 1;
1519         }
1520
1521         return 0;
1522 }
1523
1524 /*
1525  * Configure device link speed and setup link.
1526  * It returns 0 on success.
1527  */
1528 static int
1529 txgbe_dev_start(struct rte_eth_dev *dev)
1530 {
1531         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
1532         struct txgbe_hw_stats *hw_stats = TXGBE_DEV_STATS(dev);
1533         struct txgbe_vf_info *vfinfo = *TXGBE_DEV_VFDATA(dev);
1534         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1535         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1536         uint32_t intr_vector = 0;
1537         int err;
1538         bool link_up = false, negotiate = 0;
1539         uint32_t speed = 0;
1540         uint32_t allowed_speeds = 0;
1541         int mask = 0;
1542         int status;
1543         uint16_t vf, idx;
1544         uint32_t *link_speeds;
1545
1546         PMD_INIT_FUNC_TRACE();
1547
1548         /* TXGBE devices don't support:
1549          *    - half duplex (checked afterwards for valid speeds)
1550          *    - fixed speed: TODO implement
1551          */
1552         if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
1553                 PMD_INIT_LOG(ERR,
1554                 "Invalid link_speeds for port %u, fix speed not supported",
1555                                 dev->data->port_id);
1556                 return -EINVAL;
1557         }
1558
1559         /* Stop the link setup handler before resetting the HW. */
1560         rte_eal_alarm_cancel(txgbe_dev_setup_link_alarm_handler, dev);
1561
1562         /* disable uio/vfio intr/eventfd mapping */
1563         rte_intr_disable(intr_handle);
1564
1565         /* stop adapter */
1566         hw->adapter_stopped = 0;
1567         txgbe_stop_hw(hw);
1568
1569         /* reinitialize adapter
1570          * this calls reset and start
1571          */
1572         hw->nb_rx_queues = dev->data->nb_rx_queues;
1573         hw->nb_tx_queues = dev->data->nb_tx_queues;
1574         status = txgbe_pf_reset_hw(hw);
1575         if (status != 0)
1576                 return -1;
1577         hw->mac.start_hw(hw);
1578         hw->mac.get_link_status = true;
1579
1580         /* configure PF module if SRIOV enabled */
1581         txgbe_pf_host_configure(dev);
1582
1583         txgbe_dev_phy_intr_setup(dev);
1584
1585         /* check and configure queue intr-vector mapping */
1586         if ((rte_intr_cap_multiple(intr_handle) ||
1587              !RTE_ETH_DEV_SRIOV(dev).active) &&
1588             dev->data->dev_conf.intr_conf.rxq != 0) {
1589                 intr_vector = dev->data->nb_rx_queues;
1590                 if (rte_intr_efd_enable(intr_handle, intr_vector))
1591                         return -1;
1592         }
1593
1594         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1595                 intr_handle->intr_vec =
1596                         rte_zmalloc("intr_vec",
1597                                     dev->data->nb_rx_queues * sizeof(int), 0);
1598                 if (intr_handle->intr_vec == NULL) {
1599                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
1600                                      " intr_vec", dev->data->nb_rx_queues);
1601                         return -ENOMEM;
1602                 }
1603         }
1604
1605         /* confiugre msix for sleep until rx interrupt */
1606         txgbe_configure_msix(dev);
1607
1608         /* initialize transmission unit */
1609         txgbe_dev_tx_init(dev);
1610
1611         /* This can fail when allocating mbufs for descriptor rings */
1612         err = txgbe_dev_rx_init(dev);
1613         if (err) {
1614                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
1615                 goto error;
1616         }
1617
1618         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
1619                 ETH_VLAN_EXTEND_MASK;
1620         err = txgbe_vlan_offload_config(dev, mask);
1621         if (err) {
1622                 PMD_INIT_LOG(ERR, "Unable to set VLAN offload");
1623                 goto error;
1624         }
1625
1626         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1627                 /* Enable vlan filtering for VMDq */
1628                 txgbe_vmdq_vlan_hw_filter_enable(dev);
1629         }
1630
1631         /* Configure DCB hw */
1632         txgbe_configure_pb(dev);
1633         txgbe_configure_port(dev);
1634         txgbe_configure_dcb(dev);
1635
1636         if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
1637                 err = txgbe_fdir_configure(dev);
1638                 if (err)
1639                         goto error;
1640         }
1641
1642         /* Restore vf rate limit */
1643         if (vfinfo != NULL) {
1644                 for (vf = 0; vf < pci_dev->max_vfs; vf++)
1645                         for (idx = 0; idx < TXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
1646                                 if (vfinfo[vf].tx_rate[idx] != 0)
1647                                         txgbe_set_vf_rate_limit(dev, vf,
1648                                                 vfinfo[vf].tx_rate[idx],
1649                                                 1 << idx);
1650         }
1651
1652         err = txgbe_dev_rxtx_start(dev);
1653         if (err < 0) {
1654                 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
1655                 goto error;
1656         }
1657
1658         /* Skip link setup if loopback mode is enabled. */
1659         if (hw->mac.type == txgbe_mac_raptor &&
1660             dev->data->dev_conf.lpbk_mode)
1661                 goto skip_link_setup;
1662
1663         if (txgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
1664                 err = hw->mac.setup_sfp(hw);
1665                 if (err)
1666                         goto error;
1667         }
1668
1669         if (hw->phy.media_type == txgbe_media_type_copper) {
1670                 /* Turn on the copper */
1671                 hw->phy.set_phy_power(hw, true);
1672         } else {
1673                 /* Turn on the laser */
1674                 hw->mac.enable_tx_laser(hw);
1675         }
1676
1677         err = hw->mac.check_link(hw, &speed, &link_up, 0);
1678         if (err)
1679                 goto error;
1680         dev->data->dev_link.link_status = link_up;
1681
1682         err = hw->mac.get_link_capabilities(hw, &speed, &negotiate);
1683         if (err)
1684                 goto error;
1685
1686         allowed_speeds = ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
1687                         ETH_LINK_SPEED_10G;
1688
1689         link_speeds = &dev->data->dev_conf.link_speeds;
1690         if (*link_speeds & ~allowed_speeds) {
1691                 PMD_INIT_LOG(ERR, "Invalid link setting");
1692                 goto error;
1693         }
1694
1695         speed = 0x0;
1696         if (*link_speeds == ETH_LINK_SPEED_AUTONEG) {
1697                 speed = (TXGBE_LINK_SPEED_100M_FULL |
1698                          TXGBE_LINK_SPEED_1GB_FULL |
1699                          TXGBE_LINK_SPEED_10GB_FULL);
1700         } else {
1701                 if (*link_speeds & ETH_LINK_SPEED_10G)
1702                         speed |= TXGBE_LINK_SPEED_10GB_FULL;
1703                 if (*link_speeds & ETH_LINK_SPEED_5G)
1704                         speed |= TXGBE_LINK_SPEED_5GB_FULL;
1705                 if (*link_speeds & ETH_LINK_SPEED_2_5G)
1706                         speed |= TXGBE_LINK_SPEED_2_5GB_FULL;
1707                 if (*link_speeds & ETH_LINK_SPEED_1G)
1708                         speed |= TXGBE_LINK_SPEED_1GB_FULL;
1709                 if (*link_speeds & ETH_LINK_SPEED_100M)
1710                         speed |= TXGBE_LINK_SPEED_100M_FULL;
1711         }
1712
1713         err = hw->mac.setup_link(hw, speed, link_up);
1714         if (err)
1715                 goto error;
1716
1717 skip_link_setup:
1718
1719         if (rte_intr_allow_others(intr_handle)) {
1720                 /* check if lsc interrupt is enabled */
1721                 if (dev->data->dev_conf.intr_conf.lsc != 0)
1722                         txgbe_dev_lsc_interrupt_setup(dev, TRUE);
1723                 else
1724                         txgbe_dev_lsc_interrupt_setup(dev, FALSE);
1725                 txgbe_dev_macsec_interrupt_setup(dev);
1726                 txgbe_set_ivar_map(hw, -1, 1, TXGBE_MISC_VEC_ID);
1727         } else {
1728                 rte_intr_callback_unregister(intr_handle,
1729                                              txgbe_dev_interrupt_handler, dev);
1730                 if (dev->data->dev_conf.intr_conf.lsc != 0)
1731                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
1732                                      " no intr multiplex");
1733         }
1734
1735         /* check if rxq interrupt is enabled */
1736         if (dev->data->dev_conf.intr_conf.rxq != 0 &&
1737             rte_intr_dp_is_en(intr_handle))
1738                 txgbe_dev_rxq_interrupt_setup(dev);
1739
1740         /* enable uio/vfio intr/eventfd mapping */
1741         rte_intr_enable(intr_handle);
1742
1743         /* resume enabled intr since hw reset */
1744         txgbe_enable_intr(dev);
1745         txgbe_l2_tunnel_conf(dev);
1746         txgbe_filter_restore(dev);
1747
1748         /*
1749          * Update link status right before return, because it may
1750          * start link configuration process in a separate thread.
1751          */
1752         txgbe_dev_link_update(dev, 0);
1753
1754         wr32m(hw, TXGBE_LEDCTL, 0xFFFFFFFF, TXGBE_LEDCTL_ORD_MASK);
1755
1756         txgbe_read_stats_registers(hw, hw_stats);
1757         hw->offset_loaded = 1;
1758
1759         return 0;
1760
1761 error:
1762         PMD_INIT_LOG(ERR, "failure in dev start: %d", err);
1763         txgbe_dev_clear_queues(dev);
1764         return -EIO;
1765 }
1766
1767 /*
1768  * Stop device: disable rx and tx functions to allow for reconfiguring.
1769  */
1770 static int
1771 txgbe_dev_stop(struct rte_eth_dev *dev)
1772 {
1773         struct rte_eth_link link;
1774         struct txgbe_adapter *adapter = TXGBE_DEV_ADAPTER(dev);
1775         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
1776         struct txgbe_vf_info *vfinfo = *TXGBE_DEV_VFDATA(dev);
1777         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1778         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1779         int vf;
1780
1781         if (hw->adapter_stopped)
1782                 return 0;
1783
1784         PMD_INIT_FUNC_TRACE();
1785
1786         rte_eal_alarm_cancel(txgbe_dev_setup_link_alarm_handler, dev);
1787
1788         /* disable interrupts */
1789         txgbe_disable_intr(hw);
1790
1791         /* reset the NIC */
1792         txgbe_pf_reset_hw(hw);
1793         hw->adapter_stopped = 0;
1794
1795         /* stop adapter */
1796         txgbe_stop_hw(hw);
1797
1798         for (vf = 0; vfinfo != NULL && vf < pci_dev->max_vfs; vf++)
1799                 vfinfo[vf].clear_to_send = false;
1800
1801         if (hw->phy.media_type == txgbe_media_type_copper) {
1802                 /* Turn off the copper */
1803                 hw->phy.set_phy_power(hw, false);
1804         } else {
1805                 /* Turn off the laser */
1806                 hw->mac.disable_tx_laser(hw);
1807         }
1808
1809         txgbe_dev_clear_queues(dev);
1810
1811         /* Clear stored conf */
1812         dev->data->scattered_rx = 0;
1813         dev->data->lro = 0;
1814
1815         /* Clear recorded link status */
1816         memset(&link, 0, sizeof(link));
1817         rte_eth_linkstatus_set(dev, &link);
1818
1819         if (!rte_intr_allow_others(intr_handle))
1820                 /* resume to the default handler */
1821                 rte_intr_callback_register(intr_handle,
1822                                            txgbe_dev_interrupt_handler,
1823                                            (void *)dev);
1824
1825         /* Clean datapath event and queue/vec mapping */
1826         rte_intr_efd_disable(intr_handle);
1827         if (intr_handle->intr_vec != NULL) {
1828                 rte_free(intr_handle->intr_vec);
1829                 intr_handle->intr_vec = NULL;
1830         }
1831
1832         adapter->rss_reta_updated = 0;
1833         wr32m(hw, TXGBE_LEDCTL, 0xFFFFFFFF, TXGBE_LEDCTL_SEL_MASK);
1834
1835         hw->adapter_stopped = true;
1836         dev->data->dev_started = 0;
1837
1838         return 0;
1839 }
1840
1841 /*
1842  * Set device link up: enable tx.
1843  */
1844 static int
1845 txgbe_dev_set_link_up(struct rte_eth_dev *dev)
1846 {
1847         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
1848
1849         if (hw->phy.media_type == txgbe_media_type_copper) {
1850                 /* Turn on the copper */
1851                 hw->phy.set_phy_power(hw, true);
1852         } else {
1853                 /* Turn on the laser */
1854                 hw->mac.enable_tx_laser(hw);
1855                 txgbe_dev_link_update(dev, 0);
1856         }
1857
1858         return 0;
1859 }
1860
1861 /*
1862  * Set device link down: disable tx.
1863  */
1864 static int
1865 txgbe_dev_set_link_down(struct rte_eth_dev *dev)
1866 {
1867         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
1868
1869         if (hw->phy.media_type == txgbe_media_type_copper) {
1870                 /* Turn off the copper */
1871                 hw->phy.set_phy_power(hw, false);
1872         } else {
1873                 /* Turn off the laser */
1874                 hw->mac.disable_tx_laser(hw);
1875                 txgbe_dev_link_update(dev, 0);
1876         }
1877
1878         return 0;
1879 }
1880
1881 /*
1882  * Reset and stop device.
1883  */
1884 static int
1885 txgbe_dev_close(struct rte_eth_dev *dev)
1886 {
1887         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
1888         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1889         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1890         int retries = 0;
1891         int ret;
1892
1893         PMD_INIT_FUNC_TRACE();
1894
1895         txgbe_pf_reset_hw(hw);
1896
1897         ret = txgbe_dev_stop(dev);
1898
1899         txgbe_dev_free_queues(dev);
1900
1901         /* reprogram the RAR[0] in case user changed it. */
1902         txgbe_set_rar(hw, 0, hw->mac.addr, 0, true);
1903
1904         /* Unlock any pending hardware semaphore */
1905         txgbe_swfw_lock_reset(hw);
1906
1907         /* disable uio intr before callback unregister */
1908         rte_intr_disable(intr_handle);
1909
1910         do {
1911                 ret = rte_intr_callback_unregister(intr_handle,
1912                                 txgbe_dev_interrupt_handler, dev);
1913                 if (ret >= 0 || ret == -ENOENT) {
1914                         break;
1915                 } else if (ret != -EAGAIN) {
1916                         PMD_INIT_LOG(ERR,
1917                                 "intr callback unregister failed: %d",
1918                                 ret);
1919                 }
1920                 rte_delay_ms(100);
1921         } while (retries++ < (10 + TXGBE_LINK_UP_TIME));
1922
1923         /* cancel the delay handler before remove dev */
1924         rte_eal_alarm_cancel(txgbe_dev_interrupt_delayed_handler, dev);
1925
1926         /* uninitialize PF if max_vfs not zero */
1927         txgbe_pf_host_uninit(dev);
1928
1929         rte_free(dev->data->mac_addrs);
1930         dev->data->mac_addrs = NULL;
1931
1932         rte_free(dev->data->hash_mac_addrs);
1933         dev->data->hash_mac_addrs = NULL;
1934
1935         /* remove all the fdir filters & hash */
1936         txgbe_fdir_filter_uninit(dev);
1937
1938         /* remove all the L2 tunnel filters & hash */
1939         txgbe_l2_tn_filter_uninit(dev);
1940
1941         /* Remove all ntuple filters of the device */
1942         txgbe_ntuple_filter_uninit(dev);
1943
1944         return ret;
1945 }
1946
1947 /*
1948  * Reset PF device.
1949  */
1950 static int
1951 txgbe_dev_reset(struct rte_eth_dev *dev)
1952 {
1953         int ret;
1954
1955         /* When a DPDK PMD PF begin to reset PF port, it should notify all
1956          * its VF to make them align with it. The detailed notification
1957          * mechanism is PMD specific. As to txgbe PF, it is rather complex.
1958          * To avoid unexpected behavior in VF, currently reset of PF with
1959          * SR-IOV activation is not supported. It might be supported later.
1960          */
1961         if (dev->data->sriov.active)
1962                 return -ENOTSUP;
1963
1964         ret = eth_txgbe_dev_uninit(dev);
1965         if (ret)
1966                 return ret;
1967
1968         ret = eth_txgbe_dev_init(dev, NULL);
1969
1970         return ret;
1971 }
1972
1973 #define UPDATE_QP_COUNTER_32bit(reg, last_counter, counter)     \
1974         {                                                       \
1975                 uint32_t current_counter = rd32(hw, reg);       \
1976                 if (current_counter < last_counter)             \
1977                         current_counter += 0x100000000LL;       \
1978                 if (!hw->offset_loaded)                         \
1979                         last_counter = current_counter;         \
1980                 counter = current_counter - last_counter;       \
1981                 counter &= 0xFFFFFFFFLL;                        \
1982         }
1983
1984 #define UPDATE_QP_COUNTER_36bit(reg_lsb, reg_msb, last_counter, counter) \
1985         {                                                                \
1986                 uint64_t current_counter_lsb = rd32(hw, reg_lsb);        \
1987                 uint64_t current_counter_msb = rd32(hw, reg_msb);        \
1988                 uint64_t current_counter = (current_counter_msb << 32) | \
1989                         current_counter_lsb;                             \
1990                 if (current_counter < last_counter)                      \
1991                         current_counter += 0x1000000000LL;               \
1992                 if (!hw->offset_loaded)                                  \
1993                         last_counter = current_counter;                  \
1994                 counter = current_counter - last_counter;                \
1995                 counter &= 0xFFFFFFFFFLL;                                \
1996         }
1997
1998 void
1999 txgbe_read_stats_registers(struct txgbe_hw *hw,
2000                            struct txgbe_hw_stats *hw_stats)
2001 {
2002         unsigned int i;
2003
2004         /* QP Stats */
2005         for (i = 0; i < hw->nb_rx_queues; i++) {
2006                 UPDATE_QP_COUNTER_32bit(TXGBE_QPRXPKT(i),
2007                         hw->qp_last[i].rx_qp_packets,
2008                         hw_stats->qp[i].rx_qp_packets);
2009                 UPDATE_QP_COUNTER_36bit(TXGBE_QPRXOCTL(i), TXGBE_QPRXOCTH(i),
2010                         hw->qp_last[i].rx_qp_bytes,
2011                         hw_stats->qp[i].rx_qp_bytes);
2012                 UPDATE_QP_COUNTER_32bit(TXGBE_QPRXMPKT(i),
2013                         hw->qp_last[i].rx_qp_mc_packets,
2014                         hw_stats->qp[i].rx_qp_mc_packets);
2015         }
2016
2017         for (i = 0; i < hw->nb_tx_queues; i++) {
2018                 UPDATE_QP_COUNTER_32bit(TXGBE_QPTXPKT(i),
2019                         hw->qp_last[i].tx_qp_packets,
2020                         hw_stats->qp[i].tx_qp_packets);
2021                 UPDATE_QP_COUNTER_36bit(TXGBE_QPTXOCTL(i), TXGBE_QPTXOCTH(i),
2022                         hw->qp_last[i].tx_qp_bytes,
2023                         hw_stats->qp[i].tx_qp_bytes);
2024         }
2025         /* PB Stats */
2026         for (i = 0; i < TXGBE_MAX_UP; i++) {
2027                 hw_stats->up[i].rx_up_xon_packets +=
2028                                 rd32(hw, TXGBE_PBRXUPXON(i));
2029                 hw_stats->up[i].rx_up_xoff_packets +=
2030                                 rd32(hw, TXGBE_PBRXUPXOFF(i));
2031                 hw_stats->up[i].tx_up_xon_packets +=
2032                                 rd32(hw, TXGBE_PBTXUPXON(i));
2033                 hw_stats->up[i].tx_up_xoff_packets +=
2034                                 rd32(hw, TXGBE_PBTXUPXOFF(i));
2035                 hw_stats->up[i].tx_up_xon2off_packets +=
2036                                 rd32(hw, TXGBE_PBTXUPOFF(i));
2037                 hw_stats->up[i].rx_up_dropped +=
2038                                 rd32(hw, TXGBE_PBRXMISS(i));
2039         }
2040         hw_stats->rx_xon_packets += rd32(hw, TXGBE_PBRXLNKXON);
2041         hw_stats->rx_xoff_packets += rd32(hw, TXGBE_PBRXLNKXOFF);
2042         hw_stats->tx_xon_packets += rd32(hw, TXGBE_PBTXLNKXON);
2043         hw_stats->tx_xoff_packets += rd32(hw, TXGBE_PBTXLNKXOFF);
2044
2045         /* DMA Stats */
2046         hw_stats->rx_packets += rd32(hw, TXGBE_DMARXPKT);
2047         hw_stats->tx_packets += rd32(hw, TXGBE_DMATXPKT);
2048
2049         hw_stats->rx_bytes += rd64(hw, TXGBE_DMARXOCTL);
2050         hw_stats->tx_bytes += rd64(hw, TXGBE_DMATXOCTL);
2051         hw_stats->rx_drop_packets += rd32(hw, TXGBE_PBRXDROP);
2052
2053         /* MAC Stats */
2054         hw_stats->rx_crc_errors += rd64(hw, TXGBE_MACRXERRCRCL);
2055         hw_stats->rx_multicast_packets += rd64(hw, TXGBE_MACRXMPKTL);
2056         hw_stats->tx_multicast_packets += rd64(hw, TXGBE_MACTXMPKTL);
2057
2058         hw_stats->rx_total_packets += rd64(hw, TXGBE_MACRXPKTL);
2059         hw_stats->tx_total_packets += rd64(hw, TXGBE_MACTXPKTL);
2060         hw_stats->rx_total_bytes += rd64(hw, TXGBE_MACRXGBOCTL);
2061
2062         hw_stats->rx_broadcast_packets += rd64(hw, TXGBE_MACRXOCTL);
2063         hw_stats->tx_broadcast_packets += rd32(hw, TXGBE_MACTXOCTL);
2064
2065         hw_stats->rx_size_64_packets += rd64(hw, TXGBE_MACRX1TO64L);
2066         hw_stats->rx_size_65_to_127_packets += rd64(hw, TXGBE_MACRX65TO127L);
2067         hw_stats->rx_size_128_to_255_packets += rd64(hw, TXGBE_MACRX128TO255L);
2068         hw_stats->rx_size_256_to_511_packets += rd64(hw, TXGBE_MACRX256TO511L);
2069         hw_stats->rx_size_512_to_1023_packets +=
2070                         rd64(hw, TXGBE_MACRX512TO1023L);
2071         hw_stats->rx_size_1024_to_max_packets +=
2072                         rd64(hw, TXGBE_MACRX1024TOMAXL);
2073         hw_stats->tx_size_64_packets += rd64(hw, TXGBE_MACTX1TO64L);
2074         hw_stats->tx_size_65_to_127_packets += rd64(hw, TXGBE_MACTX65TO127L);
2075         hw_stats->tx_size_128_to_255_packets += rd64(hw, TXGBE_MACTX128TO255L);
2076         hw_stats->tx_size_256_to_511_packets += rd64(hw, TXGBE_MACTX256TO511L);
2077         hw_stats->tx_size_512_to_1023_packets +=
2078                         rd64(hw, TXGBE_MACTX512TO1023L);
2079         hw_stats->tx_size_1024_to_max_packets +=
2080                         rd64(hw, TXGBE_MACTX1024TOMAXL);
2081
2082         hw_stats->rx_undersize_errors += rd64(hw, TXGBE_MACRXERRLENL);
2083         hw_stats->rx_oversize_errors += rd32(hw, TXGBE_MACRXOVERSIZE);
2084         hw_stats->rx_jabber_errors += rd32(hw, TXGBE_MACRXJABBER);
2085
2086         /* MNG Stats */
2087         hw_stats->mng_bmc2host_packets = rd32(hw, TXGBE_MNGBMC2OS);
2088         hw_stats->mng_host2bmc_packets = rd32(hw, TXGBE_MNGOS2BMC);
2089         hw_stats->rx_management_packets = rd32(hw, TXGBE_DMARXMNG);
2090         hw_stats->tx_management_packets = rd32(hw, TXGBE_DMATXMNG);
2091
2092         /* FCoE Stats */
2093         hw_stats->rx_fcoe_crc_errors += rd32(hw, TXGBE_FCOECRC);
2094         hw_stats->rx_fcoe_mbuf_allocation_errors += rd32(hw, TXGBE_FCOELAST);
2095         hw_stats->rx_fcoe_dropped += rd32(hw, TXGBE_FCOERPDC);
2096         hw_stats->rx_fcoe_packets += rd32(hw, TXGBE_FCOEPRC);
2097         hw_stats->tx_fcoe_packets += rd32(hw, TXGBE_FCOEPTC);
2098         hw_stats->rx_fcoe_bytes += rd32(hw, TXGBE_FCOEDWRC);
2099         hw_stats->tx_fcoe_bytes += rd32(hw, TXGBE_FCOEDWTC);
2100
2101         /* Flow Director Stats */
2102         hw_stats->flow_director_matched_filters += rd32(hw, TXGBE_FDIRMATCH);
2103         hw_stats->flow_director_missed_filters += rd32(hw, TXGBE_FDIRMISS);
2104         hw_stats->flow_director_added_filters +=
2105                 TXGBE_FDIRUSED_ADD(rd32(hw, TXGBE_FDIRUSED));
2106         hw_stats->flow_director_removed_filters +=
2107                 TXGBE_FDIRUSED_REM(rd32(hw, TXGBE_FDIRUSED));
2108         hw_stats->flow_director_filter_add_errors +=
2109                 TXGBE_FDIRFAIL_ADD(rd32(hw, TXGBE_FDIRFAIL));
2110         hw_stats->flow_director_filter_remove_errors +=
2111                 TXGBE_FDIRFAIL_REM(rd32(hw, TXGBE_FDIRFAIL));
2112
2113         /* MACsec Stats */
2114         hw_stats->tx_macsec_pkts_untagged += rd32(hw, TXGBE_LSECTX_UTPKT);
2115         hw_stats->tx_macsec_pkts_encrypted +=
2116                         rd32(hw, TXGBE_LSECTX_ENCPKT);
2117         hw_stats->tx_macsec_pkts_protected +=
2118                         rd32(hw, TXGBE_LSECTX_PROTPKT);
2119         hw_stats->tx_macsec_octets_encrypted +=
2120                         rd32(hw, TXGBE_LSECTX_ENCOCT);
2121         hw_stats->tx_macsec_octets_protected +=
2122                         rd32(hw, TXGBE_LSECTX_PROTOCT);
2123         hw_stats->rx_macsec_pkts_untagged += rd32(hw, TXGBE_LSECRX_UTPKT);
2124         hw_stats->rx_macsec_pkts_badtag += rd32(hw, TXGBE_LSECRX_BTPKT);
2125         hw_stats->rx_macsec_pkts_nosci += rd32(hw, TXGBE_LSECRX_NOSCIPKT);
2126         hw_stats->rx_macsec_pkts_unknownsci += rd32(hw, TXGBE_LSECRX_UNSCIPKT);
2127         hw_stats->rx_macsec_octets_decrypted += rd32(hw, TXGBE_LSECRX_DECOCT);
2128         hw_stats->rx_macsec_octets_validated += rd32(hw, TXGBE_LSECRX_VLDOCT);
2129         hw_stats->rx_macsec_sc_pkts_unchecked +=
2130                         rd32(hw, TXGBE_LSECRX_UNCHKPKT);
2131         hw_stats->rx_macsec_sc_pkts_delayed += rd32(hw, TXGBE_LSECRX_DLYPKT);
2132         hw_stats->rx_macsec_sc_pkts_late += rd32(hw, TXGBE_LSECRX_LATEPKT);
2133         for (i = 0; i < 2; i++) {
2134                 hw_stats->rx_macsec_sa_pkts_ok +=
2135                         rd32(hw, TXGBE_LSECRX_OKPKT(i));
2136                 hw_stats->rx_macsec_sa_pkts_invalid +=
2137                         rd32(hw, TXGBE_LSECRX_INVPKT(i));
2138                 hw_stats->rx_macsec_sa_pkts_notvalid +=
2139                         rd32(hw, TXGBE_LSECRX_BADPKT(i));
2140         }
2141         hw_stats->rx_macsec_sa_pkts_unusedsa +=
2142                         rd32(hw, TXGBE_LSECRX_INVSAPKT);
2143         hw_stats->rx_macsec_sa_pkts_notusingsa +=
2144                         rd32(hw, TXGBE_LSECRX_BADSAPKT);
2145
2146         hw_stats->rx_total_missed_packets = 0;
2147         for (i = 0; i < TXGBE_MAX_UP; i++) {
2148                 hw_stats->rx_total_missed_packets +=
2149                         hw_stats->up[i].rx_up_dropped;
2150         }
2151 }
2152
2153 static int
2154 txgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2155 {
2156         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2157         struct txgbe_hw_stats *hw_stats = TXGBE_DEV_STATS(dev);
2158         struct txgbe_stat_mappings *stat_mappings =
2159                         TXGBE_DEV_STAT_MAPPINGS(dev);
2160         uint32_t i, j;
2161
2162         txgbe_read_stats_registers(hw, hw_stats);
2163
2164         if (stats == NULL)
2165                 return -EINVAL;
2166
2167         /* Fill out the rte_eth_stats statistics structure */
2168         stats->ipackets = hw_stats->rx_packets;
2169         stats->ibytes = hw_stats->rx_bytes;
2170         stats->opackets = hw_stats->tx_packets;
2171         stats->obytes = hw_stats->tx_bytes;
2172
2173         memset(&stats->q_ipackets, 0, sizeof(stats->q_ipackets));
2174         memset(&stats->q_opackets, 0, sizeof(stats->q_opackets));
2175         memset(&stats->q_ibytes, 0, sizeof(stats->q_ibytes));
2176         memset(&stats->q_obytes, 0, sizeof(stats->q_obytes));
2177         memset(&stats->q_errors, 0, sizeof(stats->q_errors));
2178         for (i = 0; i < TXGBE_MAX_QP; i++) {
2179                 uint32_t n = i / NB_QMAP_FIELDS_PER_QSM_REG;
2180                 uint32_t offset = (i % NB_QMAP_FIELDS_PER_QSM_REG) * 8;
2181                 uint32_t q_map;
2182
2183                 q_map = (stat_mappings->rqsm[n] >> offset)
2184                                 & QMAP_FIELD_RESERVED_BITS_MASK;
2185                 j = (q_map < RTE_ETHDEV_QUEUE_STAT_CNTRS
2186                      ? q_map : q_map % RTE_ETHDEV_QUEUE_STAT_CNTRS);
2187                 stats->q_ipackets[j] += hw_stats->qp[i].rx_qp_packets;
2188                 stats->q_ibytes[j] += hw_stats->qp[i].rx_qp_bytes;
2189
2190                 q_map = (stat_mappings->tqsm[n] >> offset)
2191                                 & QMAP_FIELD_RESERVED_BITS_MASK;
2192                 j = (q_map < RTE_ETHDEV_QUEUE_STAT_CNTRS
2193                      ? q_map : q_map % RTE_ETHDEV_QUEUE_STAT_CNTRS);
2194                 stats->q_opackets[j] += hw_stats->qp[i].tx_qp_packets;
2195                 stats->q_obytes[j] += hw_stats->qp[i].tx_qp_bytes;
2196         }
2197
2198         /* Rx Errors */
2199         stats->imissed  = hw_stats->rx_total_missed_packets;
2200         stats->ierrors  = hw_stats->rx_crc_errors +
2201                           hw_stats->rx_mac_short_packet_dropped +
2202                           hw_stats->rx_length_errors +
2203                           hw_stats->rx_undersize_errors +
2204                           hw_stats->rx_oversize_errors +
2205                           hw_stats->rx_drop_packets +
2206                           hw_stats->rx_illegal_byte_errors +
2207                           hw_stats->rx_error_bytes +
2208                           hw_stats->rx_fragment_errors +
2209                           hw_stats->rx_fcoe_crc_errors +
2210                           hw_stats->rx_fcoe_mbuf_allocation_errors;
2211
2212         /* Tx Errors */
2213         stats->oerrors  = 0;
2214         return 0;
2215 }
2216
2217 static int
2218 txgbe_dev_stats_reset(struct rte_eth_dev *dev)
2219 {
2220         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2221         struct txgbe_hw_stats *hw_stats = TXGBE_DEV_STATS(dev);
2222
2223         /* HW registers are cleared on read */
2224         hw->offset_loaded = 0;
2225         txgbe_dev_stats_get(dev, NULL);
2226         hw->offset_loaded = 1;
2227
2228         /* Reset software totals */
2229         memset(hw_stats, 0, sizeof(*hw_stats));
2230
2231         return 0;
2232 }
2233
2234 /* This function calculates the number of xstats based on the current config */
2235 static unsigned
2236 txgbe_xstats_calc_num(struct rte_eth_dev *dev)
2237 {
2238         int nb_queues = max(dev->data->nb_rx_queues, dev->data->nb_tx_queues);
2239         return TXGBE_NB_HW_STATS +
2240                TXGBE_NB_UP_STATS * TXGBE_MAX_UP +
2241                TXGBE_NB_QP_STATS * nb_queues;
2242 }
2243
2244 static inline int
2245 txgbe_get_name_by_id(uint32_t id, char *name, uint32_t size)
2246 {
2247         int nb, st;
2248
2249         /* Extended stats from txgbe_hw_stats */
2250         if (id < TXGBE_NB_HW_STATS) {
2251                 snprintf(name, size, "[hw]%s",
2252                         rte_txgbe_stats_strings[id].name);
2253                 return 0;
2254         }
2255         id -= TXGBE_NB_HW_STATS;
2256
2257         /* Priority Stats */
2258         if (id < TXGBE_NB_UP_STATS * TXGBE_MAX_UP) {
2259                 nb = id / TXGBE_NB_UP_STATS;
2260                 st = id % TXGBE_NB_UP_STATS;
2261                 snprintf(name, size, "[p%u]%s", nb,
2262                         rte_txgbe_up_strings[st].name);
2263                 return 0;
2264         }
2265         id -= TXGBE_NB_UP_STATS * TXGBE_MAX_UP;
2266
2267         /* Queue Stats */
2268         if (id < TXGBE_NB_QP_STATS * TXGBE_MAX_QP) {
2269                 nb = id / TXGBE_NB_QP_STATS;
2270                 st = id % TXGBE_NB_QP_STATS;
2271                 snprintf(name, size, "[q%u]%s", nb,
2272                         rte_txgbe_qp_strings[st].name);
2273                 return 0;
2274         }
2275         id -= TXGBE_NB_QP_STATS * TXGBE_MAX_QP;
2276
2277         return -(int)(id + 1);
2278 }
2279
2280 static inline int
2281 txgbe_get_offset_by_id(uint32_t id, uint32_t *offset)
2282 {
2283         int nb, st;
2284
2285         /* Extended stats from txgbe_hw_stats */
2286         if (id < TXGBE_NB_HW_STATS) {
2287                 *offset = rte_txgbe_stats_strings[id].offset;
2288                 return 0;
2289         }
2290         id -= TXGBE_NB_HW_STATS;
2291
2292         /* Priority Stats */
2293         if (id < TXGBE_NB_UP_STATS * TXGBE_MAX_UP) {
2294                 nb = id / TXGBE_NB_UP_STATS;
2295                 st = id % TXGBE_NB_UP_STATS;
2296                 *offset = rte_txgbe_up_strings[st].offset +
2297                         nb * (TXGBE_NB_UP_STATS * sizeof(uint64_t));
2298                 return 0;
2299         }
2300         id -= TXGBE_NB_UP_STATS * TXGBE_MAX_UP;
2301
2302         /* Queue Stats */
2303         if (id < TXGBE_NB_QP_STATS * TXGBE_MAX_QP) {
2304                 nb = id / TXGBE_NB_QP_STATS;
2305                 st = id % TXGBE_NB_QP_STATS;
2306                 *offset = rte_txgbe_qp_strings[st].offset +
2307                         nb * (TXGBE_NB_QP_STATS * sizeof(uint64_t));
2308                 return 0;
2309         }
2310
2311         return -1;
2312 }
2313
2314 static int txgbe_dev_xstats_get_names(struct rte_eth_dev *dev,
2315         struct rte_eth_xstat_name *xstats_names, unsigned int limit)
2316 {
2317         unsigned int i, count;
2318
2319         count = txgbe_xstats_calc_num(dev);
2320         if (xstats_names == NULL)
2321                 return count;
2322
2323         /* Note: limit >= cnt_stats checked upstream
2324          * in rte_eth_xstats_names()
2325          */
2326         limit = min(limit, count);
2327
2328         /* Extended stats from txgbe_hw_stats */
2329         for (i = 0; i < limit; i++) {
2330                 if (txgbe_get_name_by_id(i, xstats_names[i].name,
2331                         sizeof(xstats_names[i].name))) {
2332                         PMD_INIT_LOG(WARNING, "id value %d isn't valid", i);
2333                         break;
2334                 }
2335         }
2336
2337         return i;
2338 }
2339
2340 static int txgbe_dev_xstats_get_names_by_id(struct rte_eth_dev *dev,
2341         struct rte_eth_xstat_name *xstats_names,
2342         const uint64_t *ids,
2343         unsigned int limit)
2344 {
2345         unsigned int i;
2346
2347         if (ids == NULL)
2348                 return txgbe_dev_xstats_get_names(dev, xstats_names, limit);
2349
2350         for (i = 0; i < limit; i++) {
2351                 if (txgbe_get_name_by_id(ids[i], xstats_names[i].name,
2352                                 sizeof(xstats_names[i].name))) {
2353                         PMD_INIT_LOG(WARNING, "id value %d isn't valid", i);
2354                         return -1;
2355                 }
2356         }
2357
2358         return i;
2359 }
2360
2361 static int
2362 txgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2363                                          unsigned int limit)
2364 {
2365         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2366         struct txgbe_hw_stats *hw_stats = TXGBE_DEV_STATS(dev);
2367         unsigned int i, count;
2368
2369         txgbe_read_stats_registers(hw, hw_stats);
2370
2371         /* If this is a reset xstats is NULL, and we have cleared the
2372          * registers by reading them.
2373          */
2374         count = txgbe_xstats_calc_num(dev);
2375         if (xstats == NULL)
2376                 return count;
2377
2378         limit = min(limit, txgbe_xstats_calc_num(dev));
2379
2380         /* Extended stats from txgbe_hw_stats */
2381         for (i = 0; i < limit; i++) {
2382                 uint32_t offset = 0;
2383
2384                 if (txgbe_get_offset_by_id(i, &offset)) {
2385                         PMD_INIT_LOG(WARNING, "id value %d isn't valid", i);
2386                         break;
2387                 }
2388                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) + offset);
2389                 xstats[i].id = i;
2390         }
2391
2392         return i;
2393 }
2394
2395 static int
2396 txgbe_dev_xstats_get_(struct rte_eth_dev *dev, uint64_t *values,
2397                                          unsigned int limit)
2398 {
2399         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2400         struct txgbe_hw_stats *hw_stats = TXGBE_DEV_STATS(dev);
2401         unsigned int i, count;
2402
2403         txgbe_read_stats_registers(hw, hw_stats);
2404
2405         /* If this is a reset xstats is NULL, and we have cleared the
2406          * registers by reading them.
2407          */
2408         count = txgbe_xstats_calc_num(dev);
2409         if (values == NULL)
2410                 return count;
2411
2412         limit = min(limit, txgbe_xstats_calc_num(dev));
2413
2414         /* Extended stats from txgbe_hw_stats */
2415         for (i = 0; i < limit; i++) {
2416                 uint32_t offset;
2417
2418                 if (txgbe_get_offset_by_id(i, &offset)) {
2419                         PMD_INIT_LOG(WARNING, "id value %d isn't valid", i);
2420                         break;
2421                 }
2422                 values[i] = *(uint64_t *)(((char *)hw_stats) + offset);
2423         }
2424
2425         return i;
2426 }
2427
2428 static int
2429 txgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
2430                 uint64_t *values, unsigned int limit)
2431 {
2432         struct txgbe_hw_stats *hw_stats = TXGBE_DEV_STATS(dev);
2433         unsigned int i;
2434
2435         if (ids == NULL)
2436                 return txgbe_dev_xstats_get_(dev, values, limit);
2437
2438         for (i = 0; i < limit; i++) {
2439                 uint32_t offset;
2440
2441                 if (txgbe_get_offset_by_id(ids[i], &offset)) {
2442                         PMD_INIT_LOG(WARNING, "id value %d isn't valid", i);
2443                         break;
2444                 }
2445                 values[i] = *(uint64_t *)(((char *)hw_stats) + offset);
2446         }
2447
2448         return i;
2449 }
2450
2451 static int
2452 txgbe_dev_xstats_reset(struct rte_eth_dev *dev)
2453 {
2454         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2455         struct txgbe_hw_stats *hw_stats = TXGBE_DEV_STATS(dev);
2456
2457         /* HW registers are cleared on read */
2458         hw->offset_loaded = 0;
2459         txgbe_read_stats_registers(hw, hw_stats);
2460         hw->offset_loaded = 1;
2461
2462         /* Reset software totals */
2463         memset(hw_stats, 0, sizeof(*hw_stats));
2464
2465         return 0;
2466 }
2467
2468 static int
2469 txgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
2470 {
2471         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2472         u16 eeprom_verh, eeprom_verl;
2473         u32 etrack_id;
2474         int ret;
2475
2476         hw->rom.readw_sw(hw, TXGBE_EEPROM_VERSION_H, &eeprom_verh);
2477         hw->rom.readw_sw(hw, TXGBE_EEPROM_VERSION_L, &eeprom_verl);
2478
2479         etrack_id = (eeprom_verh << 16) | eeprom_verl;
2480         ret = snprintf(fw_version, fw_size, "0x%08x", etrack_id);
2481
2482         ret += 1; /* add the size of '\0' */
2483         if (fw_size < (u32)ret)
2484                 return ret;
2485         else
2486                 return 0;
2487 }
2488
2489 static int
2490 txgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2491 {
2492         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2493         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2494
2495         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
2496         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
2497         dev_info->min_rx_bufsize = 1024;
2498         dev_info->max_rx_pktlen = 15872;
2499         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
2500         dev_info->max_hash_mac_addrs = TXGBE_VMDQ_NUM_UC_MAC;
2501         dev_info->max_vfs = pci_dev->max_vfs;
2502         dev_info->max_vmdq_pools = ETH_64_POOLS;
2503         dev_info->vmdq_queue_num = dev_info->max_rx_queues;
2504         dev_info->rx_queue_offload_capa = txgbe_get_rx_queue_offloads(dev);
2505         dev_info->rx_offload_capa = (txgbe_get_rx_port_offloads(dev) |
2506                                      dev_info->rx_queue_offload_capa);
2507         dev_info->tx_queue_offload_capa = txgbe_get_tx_queue_offloads(dev);
2508         dev_info->tx_offload_capa = txgbe_get_tx_port_offloads(dev);
2509
2510         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2511                 .rx_thresh = {
2512                         .pthresh = TXGBE_DEFAULT_RX_PTHRESH,
2513                         .hthresh = TXGBE_DEFAULT_RX_HTHRESH,
2514                         .wthresh = TXGBE_DEFAULT_RX_WTHRESH,
2515                 },
2516                 .rx_free_thresh = TXGBE_DEFAULT_RX_FREE_THRESH,
2517                 .rx_drop_en = 0,
2518                 .offloads = 0,
2519         };
2520
2521         dev_info->default_txconf = (struct rte_eth_txconf) {
2522                 .tx_thresh = {
2523                         .pthresh = TXGBE_DEFAULT_TX_PTHRESH,
2524                         .hthresh = TXGBE_DEFAULT_TX_HTHRESH,
2525                         .wthresh = TXGBE_DEFAULT_TX_WTHRESH,
2526                 },
2527                 .tx_free_thresh = TXGBE_DEFAULT_TX_FREE_THRESH,
2528                 .offloads = 0,
2529         };
2530
2531         dev_info->rx_desc_lim = rx_desc_lim;
2532         dev_info->tx_desc_lim = tx_desc_lim;
2533
2534         dev_info->hash_key_size = TXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
2535         dev_info->reta_size = ETH_RSS_RETA_SIZE_128;
2536         dev_info->flow_type_rss_offloads = TXGBE_RSS_OFFLOAD_ALL;
2537
2538         dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
2539         dev_info->speed_capa |= ETH_LINK_SPEED_100M;
2540
2541         /* Driver-preferred Rx/Tx parameters */
2542         dev_info->default_rxportconf.burst_size = 32;
2543         dev_info->default_txportconf.burst_size = 32;
2544         dev_info->default_rxportconf.nb_queues = 1;
2545         dev_info->default_txportconf.nb_queues = 1;
2546         dev_info->default_rxportconf.ring_size = 256;
2547         dev_info->default_txportconf.ring_size = 256;
2548
2549         return 0;
2550 }
2551
2552 const uint32_t *
2553 txgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev)
2554 {
2555         if (dev->rx_pkt_burst == txgbe_recv_pkts ||
2556             dev->rx_pkt_burst == txgbe_recv_pkts_lro_single_alloc ||
2557             dev->rx_pkt_burst == txgbe_recv_pkts_lro_bulk_alloc ||
2558             dev->rx_pkt_burst == txgbe_recv_pkts_bulk_alloc)
2559                 return txgbe_get_supported_ptypes();
2560
2561         return NULL;
2562 }
2563
2564 void
2565 txgbe_dev_setup_link_alarm_handler(void *param)
2566 {
2567         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2568         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2569         struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);
2570         u32 speed;
2571         bool autoneg = false;
2572
2573         speed = hw->phy.autoneg_advertised;
2574         if (!speed)
2575                 hw->mac.get_link_capabilities(hw, &speed, &autoneg);
2576
2577         hw->mac.setup_link(hw, speed, true);
2578
2579         intr->flags &= ~TXGBE_FLAG_NEED_LINK_CONFIG;
2580 }
2581
2582 /* return 0 means link status changed, -1 means not changed */
2583 int
2584 txgbe_dev_link_update_share(struct rte_eth_dev *dev,
2585                             int wait_to_complete)
2586 {
2587         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2588         struct rte_eth_link link;
2589         u32 link_speed = TXGBE_LINK_SPEED_UNKNOWN;
2590         struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);
2591         bool link_up;
2592         int err;
2593         int wait = 1;
2594
2595         memset(&link, 0, sizeof(link));
2596         link.link_status = ETH_LINK_DOWN;
2597         link.link_speed = ETH_SPEED_NUM_NONE;
2598         link.link_duplex = ETH_LINK_HALF_DUPLEX;
2599         link.link_autoneg = ETH_LINK_AUTONEG;
2600
2601         hw->mac.get_link_status = true;
2602
2603         if (intr->flags & TXGBE_FLAG_NEED_LINK_CONFIG)
2604                 return rte_eth_linkstatus_set(dev, &link);
2605
2606         /* check if it needs to wait to complete, if lsc interrupt is enabled */
2607         if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
2608                 wait = 0;
2609
2610         err = hw->mac.check_link(hw, &link_speed, &link_up, wait);
2611
2612         if (err != 0) {
2613                 link.link_speed = ETH_SPEED_NUM_100M;
2614                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
2615                 return rte_eth_linkstatus_set(dev, &link);
2616         }
2617
2618         if (link_up == 0) {
2619                 if (hw->phy.media_type == txgbe_media_type_fiber) {
2620                         intr->flags |= TXGBE_FLAG_NEED_LINK_CONFIG;
2621                         rte_eal_alarm_set(10,
2622                                 txgbe_dev_setup_link_alarm_handler, dev);
2623                 }
2624                 return rte_eth_linkstatus_set(dev, &link);
2625         }
2626
2627         intr->flags &= ~TXGBE_FLAG_NEED_LINK_CONFIG;
2628         link.link_status = ETH_LINK_UP;
2629         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2630
2631         switch (link_speed) {
2632         default:
2633         case TXGBE_LINK_SPEED_UNKNOWN:
2634                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
2635                 link.link_speed = ETH_SPEED_NUM_100M;
2636                 break;
2637
2638         case TXGBE_LINK_SPEED_100M_FULL:
2639                 link.link_speed = ETH_SPEED_NUM_100M;
2640                 break;
2641
2642         case TXGBE_LINK_SPEED_1GB_FULL:
2643                 link.link_speed = ETH_SPEED_NUM_1G;
2644                 break;
2645
2646         case TXGBE_LINK_SPEED_2_5GB_FULL:
2647                 link.link_speed = ETH_SPEED_NUM_2_5G;
2648                 break;
2649
2650         case TXGBE_LINK_SPEED_5GB_FULL:
2651                 link.link_speed = ETH_SPEED_NUM_5G;
2652                 break;
2653
2654         case TXGBE_LINK_SPEED_10GB_FULL:
2655                 link.link_speed = ETH_SPEED_NUM_10G;
2656                 break;
2657         }
2658
2659         return rte_eth_linkstatus_set(dev, &link);
2660 }
2661
2662 static int
2663 txgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
2664 {
2665         return txgbe_dev_link_update_share(dev, wait_to_complete);
2666 }
2667
2668 static int
2669 txgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
2670 {
2671         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2672         uint32_t fctrl;
2673
2674         fctrl = rd32(hw, TXGBE_PSRCTL);
2675         fctrl |= (TXGBE_PSRCTL_UCP | TXGBE_PSRCTL_MCP);
2676         wr32(hw, TXGBE_PSRCTL, fctrl);
2677
2678         return 0;
2679 }
2680
2681 static int
2682 txgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
2683 {
2684         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2685         uint32_t fctrl;
2686
2687         fctrl = rd32(hw, TXGBE_PSRCTL);
2688         fctrl &= (~TXGBE_PSRCTL_UCP);
2689         if (dev->data->all_multicast == 1)
2690                 fctrl |= TXGBE_PSRCTL_MCP;
2691         else
2692                 fctrl &= (~TXGBE_PSRCTL_MCP);
2693         wr32(hw, TXGBE_PSRCTL, fctrl);
2694
2695         return 0;
2696 }
2697
2698 static int
2699 txgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
2700 {
2701         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2702         uint32_t fctrl;
2703
2704         fctrl = rd32(hw, TXGBE_PSRCTL);
2705         fctrl |= TXGBE_PSRCTL_MCP;
2706         wr32(hw, TXGBE_PSRCTL, fctrl);
2707
2708         return 0;
2709 }
2710
2711 static int
2712 txgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
2713 {
2714         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2715         uint32_t fctrl;
2716
2717         if (dev->data->promiscuous == 1)
2718                 return 0; /* must remain in all_multicast mode */
2719
2720         fctrl = rd32(hw, TXGBE_PSRCTL);
2721         fctrl &= (~TXGBE_PSRCTL_MCP);
2722         wr32(hw, TXGBE_PSRCTL, fctrl);
2723
2724         return 0;
2725 }
2726
2727 /**
2728  * It clears the interrupt causes and enables the interrupt.
2729  * It will be called once only during nic initialized.
2730  *
2731  * @param dev
2732  *  Pointer to struct rte_eth_dev.
2733  * @param on
2734  *  Enable or Disable.
2735  *
2736  * @return
2737  *  - On success, zero.
2738  *  - On failure, a negative value.
2739  */
2740 static int
2741 txgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on)
2742 {
2743         struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);
2744
2745         txgbe_dev_link_status_print(dev);
2746         if (on)
2747                 intr->mask_misc |= TXGBE_ICRMISC_LSC;
2748         else
2749                 intr->mask_misc &= ~TXGBE_ICRMISC_LSC;
2750
2751         return 0;
2752 }
2753
2754 /**
2755  * It clears the interrupt causes and enables the interrupt.
2756  * It will be called once only during nic initialized.
2757  *
2758  * @param dev
2759  *  Pointer to struct rte_eth_dev.
2760  *
2761  * @return
2762  *  - On success, zero.
2763  *  - On failure, a negative value.
2764  */
2765 static int
2766 txgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
2767 {
2768         struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);
2769
2770         intr->mask[0] |= TXGBE_ICR_MASK;
2771         intr->mask[1] |= TXGBE_ICR_MASK;
2772
2773         return 0;
2774 }
2775
2776 /**
2777  * It clears the interrupt causes and enables the interrupt.
2778  * It will be called once only during nic initialized.
2779  *
2780  * @param dev
2781  *  Pointer to struct rte_eth_dev.
2782  *
2783  * @return
2784  *  - On success, zero.
2785  *  - On failure, a negative value.
2786  */
2787 static int
2788 txgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev)
2789 {
2790         struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);
2791
2792         intr->mask_misc |= TXGBE_ICRMISC_LNKSEC;
2793
2794         return 0;
2795 }
2796
2797 /*
2798  * It reads ICR and sets flag (TXGBE_ICRMISC_LSC) for the link_update.
2799  *
2800  * @param dev
2801  *  Pointer to struct rte_eth_dev.
2802  *
2803  * @return
2804  *  - On success, zero.
2805  *  - On failure, a negative value.
2806  */
2807 static int
2808 txgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
2809 {
2810         uint32_t eicr;
2811         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2812         struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);
2813
2814         /* clear all cause mask */
2815         txgbe_disable_intr(hw);
2816
2817         /* read-on-clear nic registers here */
2818         eicr = ((u32 *)hw->isb_mem)[TXGBE_ISB_MISC];
2819         PMD_DRV_LOG(DEBUG, "eicr %x", eicr);
2820
2821         intr->flags = 0;
2822
2823         /* set flag for async link update */
2824         if (eicr & TXGBE_ICRMISC_LSC)
2825                 intr->flags |= TXGBE_FLAG_NEED_LINK_UPDATE;
2826
2827         if (eicr & TXGBE_ICRMISC_VFMBX)
2828                 intr->flags |= TXGBE_FLAG_MAILBOX;
2829
2830         if (eicr & TXGBE_ICRMISC_LNKSEC)
2831                 intr->flags |= TXGBE_FLAG_MACSEC;
2832
2833         if (eicr & TXGBE_ICRMISC_GPIO)
2834                 intr->flags |= TXGBE_FLAG_PHY_INTERRUPT;
2835
2836         return 0;
2837 }
2838
2839 /**
2840  * It gets and then prints the link status.
2841  *
2842  * @param dev
2843  *  Pointer to struct rte_eth_dev.
2844  *
2845  * @return
2846  *  - On success, zero.
2847  *  - On failure, a negative value.
2848  */
2849 static void
2850 txgbe_dev_link_status_print(struct rte_eth_dev *dev)
2851 {
2852         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2853         struct rte_eth_link link;
2854
2855         rte_eth_linkstatus_get(dev, &link);
2856
2857         if (link.link_status) {
2858                 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
2859                                         (int)(dev->data->port_id),
2860                                         (unsigned int)link.link_speed,
2861                         link.link_duplex == ETH_LINK_FULL_DUPLEX ?
2862                                         "full-duplex" : "half-duplex");
2863         } else {
2864                 PMD_INIT_LOG(INFO, " Port %d: Link Down",
2865                                 (int)(dev->data->port_id));
2866         }
2867         PMD_INIT_LOG(DEBUG, "PCI Address: " PCI_PRI_FMT,
2868                                 pci_dev->addr.domain,
2869                                 pci_dev->addr.bus,
2870                                 pci_dev->addr.devid,
2871                                 pci_dev->addr.function);
2872 }
2873
2874 /*
2875  * It executes link_update after knowing an interrupt occurred.
2876  *
2877  * @param dev
2878  *  Pointer to struct rte_eth_dev.
2879  *
2880  * @return
2881  *  - On success, zero.
2882  *  - On failure, a negative value.
2883  */
2884 static int
2885 txgbe_dev_interrupt_action(struct rte_eth_dev *dev,
2886                            struct rte_intr_handle *intr_handle)
2887 {
2888         struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);
2889         int64_t timeout;
2890         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2891
2892         PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
2893
2894         if (intr->flags & TXGBE_FLAG_MAILBOX) {
2895                 txgbe_pf_mbx_process(dev);
2896                 intr->flags &= ~TXGBE_FLAG_MAILBOX;
2897         }
2898
2899         if (intr->flags & TXGBE_FLAG_PHY_INTERRUPT) {
2900                 hw->phy.handle_lasi(hw);
2901                 intr->flags &= ~TXGBE_FLAG_PHY_INTERRUPT;
2902         }
2903
2904         if (intr->flags & TXGBE_FLAG_NEED_LINK_UPDATE) {
2905                 struct rte_eth_link link;
2906
2907                 /*get the link status before link update, for predicting later*/
2908                 rte_eth_linkstatus_get(dev, &link);
2909
2910                 txgbe_dev_link_update(dev, 0);
2911
2912                 /* likely to up */
2913                 if (!link.link_status)
2914                         /* handle it 1 sec later, wait it being stable */
2915                         timeout = TXGBE_LINK_UP_CHECK_TIMEOUT;
2916                 /* likely to down */
2917                 else
2918                         /* handle it 4 sec later, wait it being stable */
2919                         timeout = TXGBE_LINK_DOWN_CHECK_TIMEOUT;
2920
2921                 txgbe_dev_link_status_print(dev);
2922                 if (rte_eal_alarm_set(timeout * 1000,
2923                                       txgbe_dev_interrupt_delayed_handler,
2924                                       (void *)dev) < 0) {
2925                         PMD_DRV_LOG(ERR, "Error setting alarm");
2926                 } else {
2927                         /* remember original mask */
2928                         intr->mask_misc_orig = intr->mask_misc;
2929                         /* only disable lsc interrupt */
2930                         intr->mask_misc &= ~TXGBE_ICRMISC_LSC;
2931                 }
2932         }
2933
2934         PMD_DRV_LOG(DEBUG, "enable intr immediately");
2935         txgbe_enable_intr(dev);
2936         rte_intr_enable(intr_handle);
2937
2938         return 0;
2939 }
2940
2941 /**
2942  * Interrupt handler which shall be registered for alarm callback for delayed
2943  * handling specific interrupt to wait for the stable nic state. As the
2944  * NIC interrupt state is not stable for txgbe after link is just down,
2945  * it needs to wait 4 seconds to get the stable status.
2946  *
2947  * @param handle
2948  *  Pointer to interrupt handle.
2949  * @param param
2950  *  The address of parameter (struct rte_eth_dev *) registered before.
2951  *
2952  * @return
2953  *  void
2954  */
2955 static void
2956 txgbe_dev_interrupt_delayed_handler(void *param)
2957 {
2958         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2959         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2960         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2961         struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);
2962         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2963         uint32_t eicr;
2964
2965         txgbe_disable_intr(hw);
2966
2967         eicr = ((u32 *)hw->isb_mem)[TXGBE_ISB_MISC];
2968         if (eicr & TXGBE_ICRMISC_VFMBX)
2969                 txgbe_pf_mbx_process(dev);
2970
2971         if (intr->flags & TXGBE_FLAG_PHY_INTERRUPT) {
2972                 hw->phy.handle_lasi(hw);
2973                 intr->flags &= ~TXGBE_FLAG_PHY_INTERRUPT;
2974         }
2975
2976         if (intr->flags & TXGBE_FLAG_NEED_LINK_UPDATE) {
2977                 txgbe_dev_link_update(dev, 0);
2978                 intr->flags &= ~TXGBE_FLAG_NEED_LINK_UPDATE;
2979                 txgbe_dev_link_status_print(dev);
2980                 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC,
2981                                               NULL);
2982         }
2983
2984         if (intr->flags & TXGBE_FLAG_MACSEC) {
2985                 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_MACSEC,
2986                                               NULL);
2987                 intr->flags &= ~TXGBE_FLAG_MACSEC;
2988         }
2989
2990         /* restore original mask */
2991         intr->mask_misc = intr->mask_misc_orig;
2992         intr->mask_misc_orig = 0;
2993
2994         PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
2995         txgbe_enable_intr(dev);
2996         rte_intr_enable(intr_handle);
2997 }
2998
2999 /**
3000  * Interrupt handler triggered by NIC  for handling
3001  * specific interrupt.
3002  *
3003  * @param handle
3004  *  Pointer to interrupt handle.
3005  * @param param
3006  *  The address of parameter (struct rte_eth_dev *) registered before.
3007  *
3008  * @return
3009  *  void
3010  */
3011 static void
3012 txgbe_dev_interrupt_handler(void *param)
3013 {
3014         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3015
3016         txgbe_dev_interrupt_get_status(dev);
3017         txgbe_dev_interrupt_action(dev, dev->intr_handle);
3018 }
3019
3020 static int
3021 txgbe_dev_led_on(struct rte_eth_dev *dev)
3022 {
3023         struct txgbe_hw *hw;
3024
3025         hw = TXGBE_DEV_HW(dev);
3026         return txgbe_led_on(hw, 4) == 0 ? 0 : -ENOTSUP;
3027 }
3028
3029 static int
3030 txgbe_dev_led_off(struct rte_eth_dev *dev)
3031 {
3032         struct txgbe_hw *hw;
3033
3034         hw = TXGBE_DEV_HW(dev);
3035         return txgbe_led_off(hw, 4) == 0 ? 0 : -ENOTSUP;
3036 }
3037
3038 static int
3039 txgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3040 {
3041         struct txgbe_hw *hw;
3042         uint32_t mflcn_reg;
3043         uint32_t fccfg_reg;
3044         int rx_pause;
3045         int tx_pause;
3046
3047         hw = TXGBE_DEV_HW(dev);
3048
3049         fc_conf->pause_time = hw->fc.pause_time;
3050         fc_conf->high_water = hw->fc.high_water[0];
3051         fc_conf->low_water = hw->fc.low_water[0];
3052         fc_conf->send_xon = hw->fc.send_xon;
3053         fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
3054
3055         /*
3056          * Return rx_pause status according to actual setting of
3057          * RXFCCFG register.
3058          */
3059         mflcn_reg = rd32(hw, TXGBE_RXFCCFG);
3060         if (mflcn_reg & (TXGBE_RXFCCFG_FC | TXGBE_RXFCCFG_PFC))
3061                 rx_pause = 1;
3062         else
3063                 rx_pause = 0;
3064
3065         /*
3066          * Return tx_pause status according to actual setting of
3067          * TXFCCFG register.
3068          */
3069         fccfg_reg = rd32(hw, TXGBE_TXFCCFG);
3070         if (fccfg_reg & (TXGBE_TXFCCFG_FC | TXGBE_TXFCCFG_PFC))
3071                 tx_pause = 1;
3072         else
3073                 tx_pause = 0;
3074
3075         if (rx_pause && tx_pause)
3076                 fc_conf->mode = RTE_FC_FULL;
3077         else if (rx_pause)
3078                 fc_conf->mode = RTE_FC_RX_PAUSE;
3079         else if (tx_pause)
3080                 fc_conf->mode = RTE_FC_TX_PAUSE;
3081         else
3082                 fc_conf->mode = RTE_FC_NONE;
3083
3084         return 0;
3085 }
3086
3087 static int
3088 txgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3089 {
3090         struct txgbe_hw *hw;
3091         int err;
3092         uint32_t rx_buf_size;
3093         uint32_t max_high_water;
3094         enum txgbe_fc_mode rte_fcmode_2_txgbe_fcmode[] = {
3095                 txgbe_fc_none,
3096                 txgbe_fc_rx_pause,
3097                 txgbe_fc_tx_pause,
3098                 txgbe_fc_full
3099         };
3100
3101         PMD_INIT_FUNC_TRACE();
3102
3103         hw = TXGBE_DEV_HW(dev);
3104         rx_buf_size = rd32(hw, TXGBE_PBRXSIZE(0));
3105         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
3106
3107         /*
3108          * At least reserve one Ethernet frame for watermark
3109          * high_water/low_water in kilo bytes for txgbe
3110          */
3111         max_high_water = (rx_buf_size - RTE_ETHER_MAX_LEN) >> 10;
3112         if (fc_conf->high_water > max_high_water ||
3113             fc_conf->high_water < fc_conf->low_water) {
3114                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
3115                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
3116                 return -EINVAL;
3117         }
3118
3119         hw->fc.requested_mode = rte_fcmode_2_txgbe_fcmode[fc_conf->mode];
3120         hw->fc.pause_time     = fc_conf->pause_time;
3121         hw->fc.high_water[0]  = fc_conf->high_water;
3122         hw->fc.low_water[0]   = fc_conf->low_water;
3123         hw->fc.send_xon       = fc_conf->send_xon;
3124         hw->fc.disable_fc_autoneg = !fc_conf->autoneg;
3125
3126         err = txgbe_fc_enable(hw);
3127
3128         /* Not negotiated is not an error case */
3129         if (err == 0 || err == TXGBE_ERR_FC_NOT_NEGOTIATED) {
3130                 wr32m(hw, TXGBE_MACRXFLT, TXGBE_MACRXFLT_CTL_MASK,
3131                       (fc_conf->mac_ctrl_frame_fwd
3132                        ? TXGBE_MACRXFLT_CTL_NOPS : TXGBE_MACRXFLT_CTL_DROP));
3133                 txgbe_flush(hw);
3134
3135                 return 0;
3136         }
3137
3138         PMD_INIT_LOG(ERR, "txgbe_fc_enable = 0x%x", err);
3139         return -EIO;
3140 }
3141
3142 static int
3143 txgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
3144                 struct rte_eth_pfc_conf *pfc_conf)
3145 {
3146         int err;
3147         uint32_t rx_buf_size;
3148         uint32_t max_high_water;
3149         uint8_t tc_num;
3150         uint8_t  map[TXGBE_DCB_UP_MAX] = { 0 };
3151         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3152         struct txgbe_dcb_config *dcb_config = TXGBE_DEV_DCB_CONFIG(dev);
3153
3154         enum txgbe_fc_mode rte_fcmode_2_txgbe_fcmode[] = {
3155                 txgbe_fc_none,
3156                 txgbe_fc_rx_pause,
3157                 txgbe_fc_tx_pause,
3158                 txgbe_fc_full
3159         };
3160
3161         PMD_INIT_FUNC_TRACE();
3162
3163         txgbe_dcb_unpack_map_cee(dcb_config, TXGBE_DCB_RX_CONFIG, map);
3164         tc_num = map[pfc_conf->priority];
3165         rx_buf_size = rd32(hw, TXGBE_PBRXSIZE(tc_num));
3166         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
3167         /*
3168          * At least reserve one Ethernet frame for watermark
3169          * high_water/low_water in kilo bytes for txgbe
3170          */
3171         max_high_water = (rx_buf_size - RTE_ETHER_MAX_LEN) >> 10;
3172         if (pfc_conf->fc.high_water > max_high_water ||
3173             pfc_conf->fc.high_water <= pfc_conf->fc.low_water) {
3174                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
3175                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
3176                 return -EINVAL;
3177         }
3178
3179         hw->fc.requested_mode = rte_fcmode_2_txgbe_fcmode[pfc_conf->fc.mode];
3180         hw->fc.pause_time = pfc_conf->fc.pause_time;
3181         hw->fc.send_xon = pfc_conf->fc.send_xon;
3182         hw->fc.low_water[tc_num] =  pfc_conf->fc.low_water;
3183         hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
3184
3185         err = txgbe_dcb_pfc_enable(hw, tc_num);
3186
3187         /* Not negotiated is not an error case */
3188         if (err == 0 || err == TXGBE_ERR_FC_NOT_NEGOTIATED)
3189                 return 0;
3190
3191         PMD_INIT_LOG(ERR, "txgbe_dcb_pfc_enable = 0x%x", err);
3192         return -EIO;
3193 }
3194
3195 int
3196 txgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
3197                           struct rte_eth_rss_reta_entry64 *reta_conf,
3198                           uint16_t reta_size)
3199 {
3200         uint8_t i, j, mask;
3201         uint32_t reta;
3202         uint16_t idx, shift;
3203         struct txgbe_adapter *adapter = TXGBE_DEV_ADAPTER(dev);
3204         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3205
3206         PMD_INIT_FUNC_TRACE();
3207
3208         if (!txgbe_rss_update_sp(hw->mac.type)) {
3209                 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this "
3210                         "NIC.");
3211                 return -ENOTSUP;
3212         }
3213
3214         if (reta_size != ETH_RSS_RETA_SIZE_128) {
3215                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3216                         "(%d) doesn't match the number hardware can supported "
3217                         "(%d)", reta_size, ETH_RSS_RETA_SIZE_128);
3218                 return -EINVAL;
3219         }
3220
3221         for (i = 0; i < reta_size; i += 4) {
3222                 idx = i / RTE_RETA_GROUP_SIZE;
3223                 shift = i % RTE_RETA_GROUP_SIZE;
3224                 mask = (uint8_t)RS64(reta_conf[idx].mask, shift, 0xF);
3225                 if (!mask)
3226                         continue;
3227
3228                 reta = rd32a(hw, TXGBE_REG_RSSTBL, i >> 2);
3229                 for (j = 0; j < 4; j++) {
3230                         if (RS8(mask, j, 0x1)) {
3231                                 reta  &= ~(MS32(8 * j, 0xFF));
3232                                 reta |= LS32(reta_conf[idx].reta[shift + j],
3233                                                 8 * j, 0xFF);
3234                         }
3235                 }
3236                 wr32a(hw, TXGBE_REG_RSSTBL, i >> 2, reta);
3237         }
3238         adapter->rss_reta_updated = 1;
3239
3240         return 0;
3241 }
3242
3243 int
3244 txgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
3245                          struct rte_eth_rss_reta_entry64 *reta_conf,
3246                          uint16_t reta_size)
3247 {
3248         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3249         uint8_t i, j, mask;
3250         uint32_t reta;
3251         uint16_t idx, shift;
3252
3253         PMD_INIT_FUNC_TRACE();
3254
3255         if (reta_size != ETH_RSS_RETA_SIZE_128) {
3256                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3257                         "(%d) doesn't match the number hardware can supported "
3258                         "(%d)", reta_size, ETH_RSS_RETA_SIZE_128);
3259                 return -EINVAL;
3260         }
3261
3262         for (i = 0; i < reta_size; i += 4) {
3263                 idx = i / RTE_RETA_GROUP_SIZE;
3264                 shift = i % RTE_RETA_GROUP_SIZE;
3265                 mask = (uint8_t)RS64(reta_conf[idx].mask, shift, 0xF);
3266                 if (!mask)
3267                         continue;
3268
3269                 reta = rd32a(hw, TXGBE_REG_RSSTBL, i >> 2);
3270                 for (j = 0; j < 4; j++) {
3271                         if (RS8(mask, j, 0x1))
3272                                 reta_conf[idx].reta[shift + j] =
3273                                         (uint16_t)RS32(reta, 8 * j, 0xFF);
3274                 }
3275         }
3276
3277         return 0;
3278 }
3279
3280 static int
3281 txgbe_add_rar(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
3282                                 uint32_t index, uint32_t pool)
3283 {
3284         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3285         uint32_t enable_addr = 1;
3286
3287         return txgbe_set_rar(hw, index, mac_addr->addr_bytes,
3288                              pool, enable_addr);
3289 }
3290
3291 static void
3292 txgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
3293 {
3294         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3295
3296         txgbe_clear_rar(hw, index);
3297 }
3298
3299 static int
3300 txgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *addr)
3301 {
3302         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3303
3304         txgbe_remove_rar(dev, 0);
3305         txgbe_add_rar(dev, addr, 0, pci_dev->max_vfs);
3306
3307         return 0;
3308 }
3309
3310 static int
3311 txgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
3312 {
3313         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3314         struct rte_eth_dev_info dev_info;
3315         uint32_t frame_size = mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN;
3316         struct rte_eth_dev_data *dev_data = dev->data;
3317         int ret;
3318
3319         ret = txgbe_dev_info_get(dev, &dev_info);
3320         if (ret != 0)
3321                 return ret;
3322
3323         /* check that mtu is within the allowed range */
3324         if (mtu < RTE_ETHER_MIN_MTU || frame_size > dev_info.max_rx_pktlen)
3325                 return -EINVAL;
3326
3327         /* If device is started, refuse mtu that requires the support of
3328          * scattered packets when this feature has not been enabled before.
3329          */
3330         if (dev_data->dev_started && !dev_data->scattered_rx &&
3331             (frame_size + 2 * TXGBE_VLAN_TAG_SIZE >
3332              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
3333                 PMD_INIT_LOG(ERR, "Stop port first.");
3334                 return -EINVAL;
3335         }
3336
3337         /* update max frame size */
3338         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
3339
3340         if (hw->mode)
3341                 wr32m(hw, TXGBE_FRMSZ, TXGBE_FRMSZ_MAX_MASK,
3342                         TXGBE_FRAME_SIZE_MAX);
3343         else
3344                 wr32m(hw, TXGBE_FRMSZ, TXGBE_FRMSZ_MAX_MASK,
3345                         TXGBE_FRMSZ_MAX(frame_size));
3346
3347         return 0;
3348 }
3349
3350 static uint32_t
3351 txgbe_uta_vector(struct txgbe_hw *hw, struct rte_ether_addr *uc_addr)
3352 {
3353         uint32_t vector = 0;
3354
3355         switch (hw->mac.mc_filter_type) {
3356         case 0:   /* use bits [47:36] of the address */
3357                 vector = ((uc_addr->addr_bytes[4] >> 4) |
3358                         (((uint16_t)uc_addr->addr_bytes[5]) << 4));
3359                 break;
3360         case 1:   /* use bits [46:35] of the address */
3361                 vector = ((uc_addr->addr_bytes[4] >> 3) |
3362                         (((uint16_t)uc_addr->addr_bytes[5]) << 5));
3363                 break;
3364         case 2:   /* use bits [45:34] of the address */
3365                 vector = ((uc_addr->addr_bytes[4] >> 2) |
3366                         (((uint16_t)uc_addr->addr_bytes[5]) << 6));
3367                 break;
3368         case 3:   /* use bits [43:32] of the address */
3369                 vector = ((uc_addr->addr_bytes[4]) |
3370                         (((uint16_t)uc_addr->addr_bytes[5]) << 8));
3371                 break;
3372         default:  /* Invalid mc_filter_type */
3373                 break;
3374         }
3375
3376         /* vector can only be 12-bits or boundary will be exceeded */
3377         vector &= 0xFFF;
3378         return vector;
3379 }
3380
3381 static int
3382 txgbe_uc_hash_table_set(struct rte_eth_dev *dev,
3383                         struct rte_ether_addr *mac_addr, uint8_t on)
3384 {
3385         uint32_t vector;
3386         uint32_t uta_idx;
3387         uint32_t reg_val;
3388         uint32_t uta_mask;
3389         uint32_t psrctl;
3390
3391         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3392         struct txgbe_uta_info *uta_info = TXGBE_DEV_UTA_INFO(dev);
3393
3394         /* The UTA table only exists on pf hardware */
3395         if (hw->mac.type < txgbe_mac_raptor)
3396                 return -ENOTSUP;
3397
3398         vector = txgbe_uta_vector(hw, mac_addr);
3399         uta_idx = (vector >> 5) & 0x7F;
3400         uta_mask = 0x1UL << (vector & 0x1F);
3401
3402         if (!!on == !!(uta_info->uta_shadow[uta_idx] & uta_mask))
3403                 return 0;
3404
3405         reg_val = rd32(hw, TXGBE_UCADDRTBL(uta_idx));
3406         if (on) {
3407                 uta_info->uta_in_use++;
3408                 reg_val |= uta_mask;
3409                 uta_info->uta_shadow[uta_idx] |= uta_mask;
3410         } else {
3411                 uta_info->uta_in_use--;
3412                 reg_val &= ~uta_mask;
3413                 uta_info->uta_shadow[uta_idx] &= ~uta_mask;
3414         }
3415
3416         wr32(hw, TXGBE_UCADDRTBL(uta_idx), reg_val);
3417
3418         psrctl = rd32(hw, TXGBE_PSRCTL);
3419         if (uta_info->uta_in_use > 0)
3420                 psrctl |= TXGBE_PSRCTL_UCHFENA;
3421         else
3422                 psrctl &= ~TXGBE_PSRCTL_UCHFENA;
3423
3424         psrctl &= ~TXGBE_PSRCTL_ADHF12_MASK;
3425         psrctl |= TXGBE_PSRCTL_ADHF12(hw->mac.mc_filter_type);
3426         wr32(hw, TXGBE_PSRCTL, psrctl);
3427
3428         return 0;
3429 }
3430
3431 static int
3432 txgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
3433 {
3434         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3435         struct txgbe_uta_info *uta_info = TXGBE_DEV_UTA_INFO(dev);
3436         uint32_t psrctl;
3437         int i;
3438
3439         /* The UTA table only exists on pf hardware */
3440         if (hw->mac.type < txgbe_mac_raptor)
3441                 return -ENOTSUP;
3442
3443         if (on) {
3444                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
3445                         uta_info->uta_shadow[i] = ~0;
3446                         wr32(hw, TXGBE_UCADDRTBL(i), ~0);
3447                 }
3448         } else {
3449                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
3450                         uta_info->uta_shadow[i] = 0;
3451                         wr32(hw, TXGBE_UCADDRTBL(i), 0);
3452                 }
3453         }
3454
3455         psrctl = rd32(hw, TXGBE_PSRCTL);
3456         if (on)
3457                 psrctl |= TXGBE_PSRCTL_UCHFENA;
3458         else
3459                 psrctl &= ~TXGBE_PSRCTL_UCHFENA;
3460
3461         psrctl &= ~TXGBE_PSRCTL_ADHF12_MASK;
3462         psrctl |= TXGBE_PSRCTL_ADHF12(hw->mac.mc_filter_type);
3463         wr32(hw, TXGBE_PSRCTL, psrctl);
3464
3465         return 0;
3466 }
3467
3468 uint32_t
3469 txgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
3470 {
3471         uint32_t new_val = orig_val;
3472
3473         if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
3474                 new_val |= TXGBE_POOLETHCTL_UTA;
3475         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
3476                 new_val |= TXGBE_POOLETHCTL_MCHA;
3477         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
3478                 new_val |= TXGBE_POOLETHCTL_UCHA;
3479         if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
3480                 new_val |= TXGBE_POOLETHCTL_BCA;
3481         if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
3482                 new_val |= TXGBE_POOLETHCTL_MCP;
3483
3484         return new_val;
3485 }
3486
3487 static int
3488 txgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
3489 {
3490         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3491         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3492         uint32_t mask;
3493         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3494
3495         if (queue_id < 32) {
3496                 mask = rd32(hw, TXGBE_IMS(0));
3497                 mask &= (1 << queue_id);
3498                 wr32(hw, TXGBE_IMS(0), mask);
3499         } else if (queue_id < 64) {
3500                 mask = rd32(hw, TXGBE_IMS(1));
3501                 mask &= (1 << (queue_id - 32));
3502                 wr32(hw, TXGBE_IMS(1), mask);
3503         }
3504         rte_intr_enable(intr_handle);
3505
3506         return 0;
3507 }
3508
3509 static int
3510 txgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
3511 {
3512         uint32_t mask;
3513         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3514
3515         if (queue_id < 32) {
3516                 mask = rd32(hw, TXGBE_IMS(0));
3517                 mask &= ~(1 << queue_id);
3518                 wr32(hw, TXGBE_IMS(0), mask);
3519         } else if (queue_id < 64) {
3520                 mask = rd32(hw, TXGBE_IMS(1));
3521                 mask &= ~(1 << (queue_id - 32));
3522                 wr32(hw, TXGBE_IMS(1), mask);
3523         }
3524
3525         return 0;
3526 }
3527
3528 /**
3529  * set the IVAR registers, mapping interrupt causes to vectors
3530  * @param hw
3531  *  pointer to txgbe_hw struct
3532  * @direction
3533  *  0 for Rx, 1 for Tx, -1 for other causes
3534  * @queue
3535  *  queue to map the corresponding interrupt to
3536  * @msix_vector
3537  *  the vector to map to the corresponding queue
3538  */
3539 void
3540 txgbe_set_ivar_map(struct txgbe_hw *hw, int8_t direction,
3541                    uint8_t queue, uint8_t msix_vector)
3542 {
3543         uint32_t tmp, idx;
3544
3545         if (direction == -1) {
3546                 /* other causes */
3547                 msix_vector |= TXGBE_IVARMISC_VLD;
3548                 idx = 0;
3549                 tmp = rd32(hw, TXGBE_IVARMISC);
3550                 tmp &= ~(0xFF << idx);
3551                 tmp |= (msix_vector << idx);
3552                 wr32(hw, TXGBE_IVARMISC, tmp);
3553         } else {
3554                 /* rx or tx causes */
3555                 /* Workround for ICR lost */
3556                 idx = ((16 * (queue & 1)) + (8 * direction));
3557                 tmp = rd32(hw, TXGBE_IVAR(queue >> 1));
3558                 tmp &= ~(0xFF << idx);
3559                 tmp |= (msix_vector << idx);
3560                 wr32(hw, TXGBE_IVAR(queue >> 1), tmp);
3561         }
3562 }
3563
3564 /**
3565  * Sets up the hardware to properly generate MSI-X interrupts
3566  * @hw
3567  *  board private structure
3568  */
3569 static void
3570 txgbe_configure_msix(struct rte_eth_dev *dev)
3571 {
3572         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3573         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3574         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3575         uint32_t queue_id, base = TXGBE_MISC_VEC_ID;
3576         uint32_t vec = TXGBE_MISC_VEC_ID;
3577         uint32_t gpie;
3578
3579         /* won't configure msix register if no mapping is done
3580          * between intr vector and event fd
3581          * but if misx has been enabled already, need to configure
3582          * auto clean, auto mask and throttling.
3583          */
3584         gpie = rd32(hw, TXGBE_GPIE);
3585         if (!rte_intr_dp_is_en(intr_handle) &&
3586             !(gpie & TXGBE_GPIE_MSIX))
3587                 return;
3588
3589         if (rte_intr_allow_others(intr_handle)) {
3590                 base = TXGBE_RX_VEC_START;
3591                 vec = base;
3592         }
3593
3594         /* setup GPIE for MSI-x mode */
3595         gpie = rd32(hw, TXGBE_GPIE);
3596         gpie |= TXGBE_GPIE_MSIX;
3597         wr32(hw, TXGBE_GPIE, gpie);
3598
3599         /* Populate the IVAR table and set the ITR values to the
3600          * corresponding register.
3601          */
3602         if (rte_intr_dp_is_en(intr_handle)) {
3603                 for (queue_id = 0; queue_id < dev->data->nb_rx_queues;
3604                         queue_id++) {
3605                         /* by default, 1:1 mapping */
3606                         txgbe_set_ivar_map(hw, 0, queue_id, vec);
3607                         intr_handle->intr_vec[queue_id] = vec;
3608                         if (vec < base + intr_handle->nb_efd - 1)
3609                                 vec++;
3610                 }
3611
3612                 txgbe_set_ivar_map(hw, -1, 1, TXGBE_MISC_VEC_ID);
3613         }
3614         wr32(hw, TXGBE_ITR(TXGBE_MISC_VEC_ID),
3615                         TXGBE_ITR_IVAL_10G(TXGBE_QUEUE_ITR_INTERVAL_DEFAULT)
3616                         | TXGBE_ITR_WRDSA);
3617 }
3618
3619 int
3620 txgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
3621                            uint16_t queue_idx, uint16_t tx_rate)
3622 {
3623         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3624         uint32_t bcnrc_val;
3625
3626         if (queue_idx >= hw->mac.max_tx_queues)
3627                 return -EINVAL;
3628
3629         if (tx_rate != 0) {
3630                 bcnrc_val = TXGBE_ARBTXRATE_MAX(tx_rate);
3631                 bcnrc_val |= TXGBE_ARBTXRATE_MIN(tx_rate / 2);
3632         } else {
3633                 bcnrc_val = 0;
3634         }
3635
3636         /*
3637          * Set global transmit compensation time to the MMW_SIZE in ARBTXMMW
3638          * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported.
3639          */
3640         wr32(hw, TXGBE_ARBTXMMW, 0x14);
3641
3642         /* Set ARBTXRATE of queue X */
3643         wr32(hw, TXGBE_ARBPOOLIDX, queue_idx);
3644         wr32(hw, TXGBE_ARBTXRATE, bcnrc_val);
3645         txgbe_flush(hw);
3646
3647         return 0;
3648 }
3649
3650 int
3651 txgbe_syn_filter_set(struct rte_eth_dev *dev,
3652                         struct rte_eth_syn_filter *filter,
3653                         bool add)
3654 {
3655         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3656         struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(dev);
3657         uint32_t syn_info;
3658         uint32_t synqf;
3659
3660         if (filter->queue >= TXGBE_MAX_RX_QUEUE_NUM)
3661                 return -EINVAL;
3662
3663         syn_info = filter_info->syn_info;
3664
3665         if (add) {
3666                 if (syn_info & TXGBE_SYNCLS_ENA)
3667                         return -EINVAL;
3668                 synqf = (uint32_t)TXGBE_SYNCLS_QPID(filter->queue);
3669                 synqf |= TXGBE_SYNCLS_ENA;
3670
3671                 if (filter->hig_pri)
3672                         synqf |= TXGBE_SYNCLS_HIPRIO;
3673                 else
3674                         synqf &= ~TXGBE_SYNCLS_HIPRIO;
3675         } else {
3676                 synqf = rd32(hw, TXGBE_SYNCLS);
3677                 if (!(syn_info & TXGBE_SYNCLS_ENA))
3678                         return -ENOENT;
3679                 synqf &= ~(TXGBE_SYNCLS_QPID_MASK | TXGBE_SYNCLS_ENA);
3680         }
3681
3682         filter_info->syn_info = synqf;
3683         wr32(hw, TXGBE_SYNCLS, synqf);
3684         txgbe_flush(hw);
3685         return 0;
3686 }
3687
3688 static inline enum txgbe_5tuple_protocol
3689 convert_protocol_type(uint8_t protocol_value)
3690 {
3691         if (protocol_value == IPPROTO_TCP)
3692                 return TXGBE_5TF_PROT_TCP;
3693         else if (protocol_value == IPPROTO_UDP)
3694                 return TXGBE_5TF_PROT_UDP;
3695         else if (protocol_value == IPPROTO_SCTP)
3696                 return TXGBE_5TF_PROT_SCTP;
3697         else
3698                 return TXGBE_5TF_PROT_NONE;
3699 }
3700
3701 /* inject a 5-tuple filter to HW */
3702 static inline void
3703 txgbe_inject_5tuple_filter(struct rte_eth_dev *dev,
3704                            struct txgbe_5tuple_filter *filter)
3705 {
3706         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3707         int i;
3708         uint32_t ftqf, sdpqf;
3709         uint32_t l34timir = 0;
3710         uint32_t mask = TXGBE_5TFCTL0_MASK;
3711
3712         i = filter->index;
3713         sdpqf = TXGBE_5TFPORT_DST(be_to_le16(filter->filter_info.dst_port));
3714         sdpqf |= TXGBE_5TFPORT_SRC(be_to_le16(filter->filter_info.src_port));
3715
3716         ftqf = TXGBE_5TFCTL0_PROTO(filter->filter_info.proto);
3717         ftqf |= TXGBE_5TFCTL0_PRI(filter->filter_info.priority);
3718         if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
3719                 mask &= ~TXGBE_5TFCTL0_MSADDR;
3720         if (filter->filter_info.dst_ip_mask == 0)
3721                 mask &= ~TXGBE_5TFCTL0_MDADDR;
3722         if (filter->filter_info.src_port_mask == 0)
3723                 mask &= ~TXGBE_5TFCTL0_MSPORT;
3724         if (filter->filter_info.dst_port_mask == 0)
3725                 mask &= ~TXGBE_5TFCTL0_MDPORT;
3726         if (filter->filter_info.proto_mask == 0)
3727                 mask &= ~TXGBE_5TFCTL0_MPROTO;
3728         ftqf |= mask;
3729         ftqf |= TXGBE_5TFCTL0_MPOOL;
3730         ftqf |= TXGBE_5TFCTL0_ENA;
3731
3732         wr32(hw, TXGBE_5TFDADDR(i), be_to_le32(filter->filter_info.dst_ip));
3733         wr32(hw, TXGBE_5TFSADDR(i), be_to_le32(filter->filter_info.src_ip));
3734         wr32(hw, TXGBE_5TFPORT(i), sdpqf);
3735         wr32(hw, TXGBE_5TFCTL0(i), ftqf);
3736
3737         l34timir |= TXGBE_5TFCTL1_QP(filter->queue);
3738         wr32(hw, TXGBE_5TFCTL1(i), l34timir);
3739 }
3740
3741 /*
3742  * add a 5tuple filter
3743  *
3744  * @param
3745  * dev: Pointer to struct rte_eth_dev.
3746  * index: the index the filter allocates.
3747  * filter: pointer to the filter that will be added.
3748  * rx_queue: the queue id the filter assigned to.
3749  *
3750  * @return
3751  *    - On success, zero.
3752  *    - On failure, a negative value.
3753  */
3754 static int
3755 txgbe_add_5tuple_filter(struct rte_eth_dev *dev,
3756                         struct txgbe_5tuple_filter *filter)
3757 {
3758         struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(dev);
3759         int i, idx, shift;
3760
3761         /*
3762          * look for an unused 5tuple filter index,
3763          * and insert the filter to list.
3764          */
3765         for (i = 0; i < TXGBE_MAX_FTQF_FILTERS; i++) {
3766                 idx = i / (sizeof(uint32_t) * NBBY);
3767                 shift = i % (sizeof(uint32_t) * NBBY);
3768                 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
3769                         filter_info->fivetuple_mask[idx] |= 1 << shift;
3770                         filter->index = i;
3771                         TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
3772                                           filter,
3773                                           entries);
3774                         break;
3775                 }
3776         }
3777         if (i >= TXGBE_MAX_FTQF_FILTERS) {
3778                 PMD_DRV_LOG(ERR, "5tuple filters are full.");
3779                 return -ENOSYS;
3780         }
3781
3782         txgbe_inject_5tuple_filter(dev, filter);
3783
3784         return 0;
3785 }
3786
3787 /*
3788  * remove a 5tuple filter
3789  *
3790  * @param
3791  * dev: Pointer to struct rte_eth_dev.
3792  * filter: the pointer of the filter will be removed.
3793  */
3794 static void
3795 txgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
3796                         struct txgbe_5tuple_filter *filter)
3797 {
3798         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3799         struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(dev);
3800         uint16_t index = filter->index;
3801
3802         filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
3803                                 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
3804         TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
3805         rte_free(filter);
3806
3807         wr32(hw, TXGBE_5TFDADDR(index), 0);
3808         wr32(hw, TXGBE_5TFSADDR(index), 0);
3809         wr32(hw, TXGBE_5TFPORT(index), 0);
3810         wr32(hw, TXGBE_5TFCTL0(index), 0);
3811         wr32(hw, TXGBE_5TFCTL1(index), 0);
3812 }
3813
3814 static inline struct txgbe_5tuple_filter *
3815 txgbe_5tuple_filter_lookup(struct txgbe_5tuple_filter_list *filter_list,
3816                         struct txgbe_5tuple_filter_info *key)
3817 {
3818         struct txgbe_5tuple_filter *it;
3819
3820         TAILQ_FOREACH(it, filter_list, entries) {
3821                 if (memcmp(key, &it->filter_info,
3822                         sizeof(struct txgbe_5tuple_filter_info)) == 0) {
3823                         return it;
3824                 }
3825         }
3826         return NULL;
3827 }
3828
3829 /* translate elements in struct rte_eth_ntuple_filter
3830  * to struct txgbe_5tuple_filter_info
3831  */
3832 static inline int
3833 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
3834                         struct txgbe_5tuple_filter_info *filter_info)
3835 {
3836         if (filter->queue >= TXGBE_MAX_RX_QUEUE_NUM ||
3837                 filter->priority > TXGBE_5TUPLE_MAX_PRI ||
3838                 filter->priority < TXGBE_5TUPLE_MIN_PRI)
3839                 return -EINVAL;
3840
3841         switch (filter->dst_ip_mask) {
3842         case UINT32_MAX:
3843                 filter_info->dst_ip_mask = 0;
3844                 filter_info->dst_ip = filter->dst_ip;
3845                 break;
3846         case 0:
3847                 filter_info->dst_ip_mask = 1;
3848                 break;
3849         default:
3850                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
3851                 return -EINVAL;
3852         }
3853
3854         switch (filter->src_ip_mask) {
3855         case UINT32_MAX:
3856                 filter_info->src_ip_mask = 0;
3857                 filter_info->src_ip = filter->src_ip;
3858                 break;
3859         case 0:
3860                 filter_info->src_ip_mask = 1;
3861                 break;
3862         default:
3863                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
3864                 return -EINVAL;
3865         }
3866
3867         switch (filter->dst_port_mask) {
3868         case UINT16_MAX:
3869                 filter_info->dst_port_mask = 0;
3870                 filter_info->dst_port = filter->dst_port;
3871                 break;
3872         case 0:
3873                 filter_info->dst_port_mask = 1;
3874                 break;
3875         default:
3876                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
3877                 return -EINVAL;
3878         }
3879
3880         switch (filter->src_port_mask) {
3881         case UINT16_MAX:
3882                 filter_info->src_port_mask = 0;
3883                 filter_info->src_port = filter->src_port;
3884                 break;
3885         case 0:
3886                 filter_info->src_port_mask = 1;
3887                 break;
3888         default:
3889                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
3890                 return -EINVAL;
3891         }
3892
3893         switch (filter->proto_mask) {
3894         case UINT8_MAX:
3895                 filter_info->proto_mask = 0;
3896                 filter_info->proto =
3897                         convert_protocol_type(filter->proto);
3898                 break;
3899         case 0:
3900                 filter_info->proto_mask = 1;
3901                 break;
3902         default:
3903                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
3904                 return -EINVAL;
3905         }
3906
3907         filter_info->priority = (uint8_t)filter->priority;
3908         return 0;
3909 }
3910
3911 /*
3912  * add or delete a ntuple filter
3913  *
3914  * @param
3915  * dev: Pointer to struct rte_eth_dev.
3916  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
3917  * add: if true, add filter, if false, remove filter
3918  *
3919  * @return
3920  *    - On success, zero.
3921  *    - On failure, a negative value.
3922  */
3923 int
3924 txgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
3925                         struct rte_eth_ntuple_filter *ntuple_filter,
3926                         bool add)
3927 {
3928         struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(dev);
3929         struct txgbe_5tuple_filter_info filter_5tuple;
3930         struct txgbe_5tuple_filter *filter;
3931         int ret;
3932
3933         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
3934                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
3935                 return -EINVAL;
3936         }
3937
3938         memset(&filter_5tuple, 0, sizeof(struct txgbe_5tuple_filter_info));
3939         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
3940         if (ret < 0)
3941                 return ret;
3942
3943         filter = txgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
3944                                          &filter_5tuple);
3945         if (filter != NULL && add) {
3946                 PMD_DRV_LOG(ERR, "filter exists.");
3947                 return -EEXIST;
3948         }
3949         if (filter == NULL && !add) {
3950                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
3951                 return -ENOENT;
3952         }
3953
3954         if (add) {
3955                 filter = rte_zmalloc("txgbe_5tuple_filter",
3956                                 sizeof(struct txgbe_5tuple_filter), 0);
3957                 if (filter == NULL)
3958                         return -ENOMEM;
3959                 rte_memcpy(&filter->filter_info,
3960                                  &filter_5tuple,
3961                                  sizeof(struct txgbe_5tuple_filter_info));
3962                 filter->queue = ntuple_filter->queue;
3963                 ret = txgbe_add_5tuple_filter(dev, filter);
3964                 if (ret < 0) {
3965                         rte_free(filter);
3966                         return ret;
3967                 }
3968         } else {
3969                 txgbe_remove_5tuple_filter(dev, filter);
3970         }
3971
3972         return 0;
3973 }
3974
3975 int
3976 txgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
3977                         struct rte_eth_ethertype_filter *filter,
3978                         bool add)
3979 {
3980         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3981         struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(dev);
3982         uint32_t etqf = 0;
3983         uint32_t etqs = 0;
3984         int ret;
3985         struct txgbe_ethertype_filter ethertype_filter;
3986
3987         if (filter->queue >= TXGBE_MAX_RX_QUEUE_NUM)
3988                 return -EINVAL;
3989
3990         if (filter->ether_type == RTE_ETHER_TYPE_IPV4 ||
3991             filter->ether_type == RTE_ETHER_TYPE_IPV6) {
3992                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
3993                         " ethertype filter.", filter->ether_type);
3994                 return -EINVAL;
3995         }
3996
3997         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
3998                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
3999                 return -EINVAL;
4000         }
4001         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
4002                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
4003                 return -EINVAL;
4004         }
4005
4006         ret = txgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
4007         if (ret >= 0 && add) {
4008                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
4009                             filter->ether_type);
4010                 return -EEXIST;
4011         }
4012         if (ret < 0 && !add) {
4013                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
4014                             filter->ether_type);
4015                 return -ENOENT;
4016         }
4017
4018         if (add) {
4019                 etqf = TXGBE_ETFLT_ENA;
4020                 etqf |= TXGBE_ETFLT_ETID(filter->ether_type);
4021                 etqs |= TXGBE_ETCLS_QPID(filter->queue);
4022                 etqs |= TXGBE_ETCLS_QENA;
4023
4024                 ethertype_filter.ethertype = filter->ether_type;
4025                 ethertype_filter.etqf = etqf;
4026                 ethertype_filter.etqs = etqs;
4027                 ethertype_filter.conf = FALSE;
4028                 ret = txgbe_ethertype_filter_insert(filter_info,
4029                                                     &ethertype_filter);
4030                 if (ret < 0) {
4031                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
4032                         return -ENOSPC;
4033                 }
4034         } else {
4035                 ret = txgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
4036                 if (ret < 0)
4037                         return -ENOSYS;
4038         }
4039         wr32(hw, TXGBE_ETFLT(ret), etqf);
4040         wr32(hw, TXGBE_ETCLS(ret), etqs);
4041         txgbe_flush(hw);
4042
4043         return 0;
4044 }
4045
4046 static int
4047 txgbe_dev_filter_ctrl(__rte_unused struct rte_eth_dev *dev,
4048                      enum rte_filter_type filter_type,
4049                      enum rte_filter_op filter_op,
4050                      void *arg)
4051 {
4052         int ret = 0;
4053
4054         switch (filter_type) {
4055         case RTE_ETH_FILTER_GENERIC:
4056                 if (filter_op != RTE_ETH_FILTER_GET)
4057                         return -EINVAL;
4058                 *(const void **)arg = &txgbe_flow_ops;
4059                 break;
4060         default:
4061                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
4062                                                         filter_type);
4063                 ret = -EINVAL;
4064                 break;
4065         }
4066
4067         return ret;
4068 }
4069
4070 static u8 *
4071 txgbe_dev_addr_list_itr(__rte_unused struct txgbe_hw *hw,
4072                         u8 **mc_addr_ptr, u32 *vmdq)
4073 {
4074         u8 *mc_addr;
4075
4076         *vmdq = 0;
4077         mc_addr = *mc_addr_ptr;
4078         *mc_addr_ptr = (mc_addr + sizeof(struct rte_ether_addr));
4079         return mc_addr;
4080 }
4081
4082 int
4083 txgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
4084                           struct rte_ether_addr *mc_addr_set,
4085                           uint32_t nb_mc_addr)
4086 {
4087         struct txgbe_hw *hw;
4088         u8 *mc_addr_list;
4089
4090         hw = TXGBE_DEV_HW(dev);
4091         mc_addr_list = (u8 *)mc_addr_set;
4092         return txgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
4093                                          txgbe_dev_addr_list_itr, TRUE);
4094 }
4095
4096 static uint64_t
4097 txgbe_read_systime_cyclecounter(struct rte_eth_dev *dev)
4098 {
4099         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4100         uint64_t systime_cycles;
4101
4102         systime_cycles = (uint64_t)rd32(hw, TXGBE_TSTIMEL);
4103         systime_cycles |= (uint64_t)rd32(hw, TXGBE_TSTIMEH) << 32;
4104
4105         return systime_cycles;
4106 }
4107
4108 static uint64_t
4109 txgbe_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
4110 {
4111         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4112         uint64_t rx_tstamp_cycles;
4113
4114         /* TSRXSTMPL stores ns and TSRXSTMPH stores seconds. */
4115         rx_tstamp_cycles = (uint64_t)rd32(hw, TXGBE_TSRXSTMPL);
4116         rx_tstamp_cycles |= (uint64_t)rd32(hw, TXGBE_TSRXSTMPH) << 32;
4117
4118         return rx_tstamp_cycles;
4119 }
4120
4121 static uint64_t
4122 txgbe_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
4123 {
4124         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4125         uint64_t tx_tstamp_cycles;
4126
4127         /* TSTXSTMPL stores ns and TSTXSTMPH stores seconds. */
4128         tx_tstamp_cycles = (uint64_t)rd32(hw, TXGBE_TSTXSTMPL);
4129         tx_tstamp_cycles |= (uint64_t)rd32(hw, TXGBE_TSTXSTMPH) << 32;
4130
4131         return tx_tstamp_cycles;
4132 }
4133
4134 static void
4135 txgbe_start_timecounters(struct rte_eth_dev *dev)
4136 {
4137         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4138         struct txgbe_adapter *adapter = TXGBE_DEV_ADAPTER(dev);
4139         struct rte_eth_link link;
4140         uint32_t incval = 0;
4141         uint32_t shift = 0;
4142
4143         /* Get current link speed. */
4144         txgbe_dev_link_update(dev, 1);
4145         rte_eth_linkstatus_get(dev, &link);
4146
4147         switch (link.link_speed) {
4148         case ETH_SPEED_NUM_100M:
4149                 incval = TXGBE_INCVAL_100;
4150                 shift = TXGBE_INCVAL_SHIFT_100;
4151                 break;
4152         case ETH_SPEED_NUM_1G:
4153                 incval = TXGBE_INCVAL_1GB;
4154                 shift = TXGBE_INCVAL_SHIFT_1GB;
4155                 break;
4156         case ETH_SPEED_NUM_10G:
4157         default:
4158                 incval = TXGBE_INCVAL_10GB;
4159                 shift = TXGBE_INCVAL_SHIFT_10GB;
4160                 break;
4161         }
4162
4163         wr32(hw, TXGBE_TSTIMEINC, TXGBE_TSTIMEINC_VP(incval, 2));
4164
4165         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
4166         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
4167         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
4168
4169         adapter->systime_tc.cc_mask = TXGBE_CYCLECOUNTER_MASK;
4170         adapter->systime_tc.cc_shift = shift;
4171         adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
4172
4173         adapter->rx_tstamp_tc.cc_mask = TXGBE_CYCLECOUNTER_MASK;
4174         adapter->rx_tstamp_tc.cc_shift = shift;
4175         adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
4176
4177         adapter->tx_tstamp_tc.cc_mask = TXGBE_CYCLECOUNTER_MASK;
4178         adapter->tx_tstamp_tc.cc_shift = shift;
4179         adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
4180 }
4181
4182 static int
4183 txgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
4184 {
4185         struct txgbe_adapter *adapter = TXGBE_DEV_ADAPTER(dev);
4186
4187         adapter->systime_tc.nsec += delta;
4188         adapter->rx_tstamp_tc.nsec += delta;
4189         adapter->tx_tstamp_tc.nsec += delta;
4190
4191         return 0;
4192 }
4193
4194 static int
4195 txgbe_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
4196 {
4197         uint64_t ns;
4198         struct txgbe_adapter *adapter = TXGBE_DEV_ADAPTER(dev);
4199
4200         ns = rte_timespec_to_ns(ts);
4201         /* Set the timecounters to a new value. */
4202         adapter->systime_tc.nsec = ns;
4203         adapter->rx_tstamp_tc.nsec = ns;
4204         adapter->tx_tstamp_tc.nsec = ns;
4205
4206         return 0;
4207 }
4208
4209 static int
4210 txgbe_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
4211 {
4212         uint64_t ns, systime_cycles;
4213         struct txgbe_adapter *adapter = TXGBE_DEV_ADAPTER(dev);
4214
4215         systime_cycles = txgbe_read_systime_cyclecounter(dev);
4216         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
4217         *ts = rte_ns_to_timespec(ns);
4218
4219         return 0;
4220 }
4221
4222 static int
4223 txgbe_timesync_enable(struct rte_eth_dev *dev)
4224 {
4225         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4226         uint32_t tsync_ctl;
4227
4228         /* Stop the timesync system time. */
4229         wr32(hw, TXGBE_TSTIMEINC, 0x0);
4230         /* Reset the timesync system time value. */
4231         wr32(hw, TXGBE_TSTIMEL, 0x0);
4232         wr32(hw, TXGBE_TSTIMEH, 0x0);
4233
4234         txgbe_start_timecounters(dev);
4235
4236         /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
4237         wr32(hw, TXGBE_ETFLT(TXGBE_ETF_ID_1588),
4238                 RTE_ETHER_TYPE_1588 | TXGBE_ETFLT_ENA | TXGBE_ETFLT_1588);
4239
4240         /* Enable timestamping of received PTP packets. */
4241         tsync_ctl = rd32(hw, TXGBE_TSRXCTL);
4242         tsync_ctl |= TXGBE_TSRXCTL_ENA;
4243         wr32(hw, TXGBE_TSRXCTL, tsync_ctl);
4244
4245         /* Enable timestamping of transmitted PTP packets. */
4246         tsync_ctl = rd32(hw, TXGBE_TSTXCTL);
4247         tsync_ctl |= TXGBE_TSTXCTL_ENA;
4248         wr32(hw, TXGBE_TSTXCTL, tsync_ctl);
4249
4250         txgbe_flush(hw);
4251
4252         return 0;
4253 }
4254
4255 static int
4256 txgbe_timesync_disable(struct rte_eth_dev *dev)
4257 {
4258         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4259         uint32_t tsync_ctl;
4260
4261         /* Disable timestamping of transmitted PTP packets. */
4262         tsync_ctl = rd32(hw, TXGBE_TSTXCTL);
4263         tsync_ctl &= ~TXGBE_TSTXCTL_ENA;
4264         wr32(hw, TXGBE_TSTXCTL, tsync_ctl);
4265
4266         /* Disable timestamping of received PTP packets. */
4267         tsync_ctl = rd32(hw, TXGBE_TSRXCTL);
4268         tsync_ctl &= ~TXGBE_TSRXCTL_ENA;
4269         wr32(hw, TXGBE_TSRXCTL, tsync_ctl);
4270
4271         /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
4272         wr32(hw, TXGBE_ETFLT(TXGBE_ETF_ID_1588), 0);
4273
4274         /* Stop incrementating the System Time registers. */
4275         wr32(hw, TXGBE_TSTIMEINC, 0);
4276
4277         return 0;
4278 }
4279
4280 static int
4281 txgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
4282                                  struct timespec *timestamp,
4283                                  uint32_t flags __rte_unused)
4284 {
4285         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4286         struct txgbe_adapter *adapter = TXGBE_DEV_ADAPTER(dev);
4287         uint32_t tsync_rxctl;
4288         uint64_t rx_tstamp_cycles;
4289         uint64_t ns;
4290
4291         tsync_rxctl = rd32(hw, TXGBE_TSRXCTL);
4292         if ((tsync_rxctl & TXGBE_TSRXCTL_VLD) == 0)
4293                 return -EINVAL;
4294
4295         rx_tstamp_cycles = txgbe_read_rx_tstamp_cyclecounter(dev);
4296         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
4297         *timestamp = rte_ns_to_timespec(ns);
4298
4299         return  0;
4300 }
4301
4302 static int
4303 txgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
4304                                  struct timespec *timestamp)
4305 {
4306         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4307         struct txgbe_adapter *adapter = TXGBE_DEV_ADAPTER(dev);
4308         uint32_t tsync_txctl;
4309         uint64_t tx_tstamp_cycles;
4310         uint64_t ns;
4311
4312         tsync_txctl = rd32(hw, TXGBE_TSTXCTL);
4313         if ((tsync_txctl & TXGBE_TSTXCTL_VLD) == 0)
4314                 return -EINVAL;
4315
4316         tx_tstamp_cycles = txgbe_read_tx_tstamp_cyclecounter(dev);
4317         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
4318         *timestamp = rte_ns_to_timespec(ns);
4319
4320         return 0;
4321 }
4322
4323 static int
4324 txgbe_get_reg_length(struct rte_eth_dev *dev __rte_unused)
4325 {
4326         int count = 0;
4327         int g_ind = 0;
4328         const struct reg_info *reg_group;
4329         const struct reg_info **reg_set = txgbe_regs_others;
4330
4331         while ((reg_group = reg_set[g_ind++]))
4332                 count += txgbe_regs_group_count(reg_group);
4333
4334         return count;
4335 }
4336
4337 static int
4338 txgbe_get_regs(struct rte_eth_dev *dev,
4339               struct rte_dev_reg_info *regs)
4340 {
4341         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4342         uint32_t *data = regs->data;
4343         int g_ind = 0;
4344         int count = 0;
4345         const struct reg_info *reg_group;
4346         const struct reg_info **reg_set = txgbe_regs_others;
4347
4348         if (data == NULL) {
4349                 regs->length = txgbe_get_reg_length(dev);
4350                 regs->width = sizeof(uint32_t);
4351                 return 0;
4352         }
4353
4354         /* Support only full register dump */
4355         if (regs->length == 0 ||
4356             regs->length == (uint32_t)txgbe_get_reg_length(dev)) {
4357                 regs->version = hw->mac.type << 24 |
4358                                 hw->revision_id << 16 |
4359                                 hw->device_id;
4360                 while ((reg_group = reg_set[g_ind++]))
4361                         count += txgbe_read_regs_group(dev, &data[count],
4362                                                       reg_group);
4363                 return 0;
4364         }
4365
4366         return -ENOTSUP;
4367 }
4368
4369 static int
4370 txgbe_get_eeprom_length(struct rte_eth_dev *dev)
4371 {
4372         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4373
4374         /* Return unit is byte count */
4375         return hw->rom.word_size * 2;
4376 }
4377
4378 static int
4379 txgbe_get_eeprom(struct rte_eth_dev *dev,
4380                 struct rte_dev_eeprom_info *in_eeprom)
4381 {
4382         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4383         struct txgbe_rom_info *eeprom = &hw->rom;
4384         uint16_t *data = in_eeprom->data;
4385         int first, length;
4386
4387         first = in_eeprom->offset >> 1;
4388         length = in_eeprom->length >> 1;
4389         if (first > hw->rom.word_size ||
4390             ((first + length) > hw->rom.word_size))
4391                 return -EINVAL;
4392
4393         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
4394
4395         return eeprom->readw_buffer(hw, first, length, data);
4396 }
4397
4398 static int
4399 txgbe_set_eeprom(struct rte_eth_dev *dev,
4400                 struct rte_dev_eeprom_info *in_eeprom)
4401 {
4402         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4403         struct txgbe_rom_info *eeprom = &hw->rom;
4404         uint16_t *data = in_eeprom->data;
4405         int first, length;
4406
4407         first = in_eeprom->offset >> 1;
4408         length = in_eeprom->length >> 1;
4409         if (first > hw->rom.word_size ||
4410             ((first + length) > hw->rom.word_size))
4411                 return -EINVAL;
4412
4413         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
4414
4415         return eeprom->writew_buffer(hw,  first, length, data);
4416 }
4417
4418 static int
4419 txgbe_get_module_info(struct rte_eth_dev *dev,
4420                       struct rte_eth_dev_module_info *modinfo)
4421 {
4422         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4423         uint32_t status;
4424         uint8_t sff8472_rev, addr_mode;
4425         bool page_swap = false;
4426
4427         /* Check whether we support SFF-8472 or not */
4428         status = hw->phy.read_i2c_eeprom(hw,
4429                                              TXGBE_SFF_SFF_8472_COMP,
4430                                              &sff8472_rev);
4431         if (status != 0)
4432                 return -EIO;
4433
4434         /* addressing mode is not supported */
4435         status = hw->phy.read_i2c_eeprom(hw,
4436                                              TXGBE_SFF_SFF_8472_SWAP,
4437                                              &addr_mode);
4438         if (status != 0)
4439                 return -EIO;
4440
4441         if (addr_mode & TXGBE_SFF_ADDRESSING_MODE) {
4442                 PMD_DRV_LOG(ERR,
4443                             "Address change required to access page 0xA2, "
4444                             "but not supported. Please report the module "
4445                             "type to the driver maintainers.");
4446                 page_swap = true;
4447         }
4448
4449         if (sff8472_rev == TXGBE_SFF_SFF_8472_UNSUP || page_swap) {
4450                 /* We have a SFP, but it does not support SFF-8472 */
4451                 modinfo->type = RTE_ETH_MODULE_SFF_8079;
4452                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
4453         } else {
4454                 /* We have a SFP which supports a revision of SFF-8472. */
4455                 modinfo->type = RTE_ETH_MODULE_SFF_8472;
4456                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
4457         }
4458
4459         return 0;
4460 }
4461
4462 static int
4463 txgbe_get_module_eeprom(struct rte_eth_dev *dev,
4464                         struct rte_dev_eeprom_info *info)
4465 {
4466         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4467         uint32_t status = TXGBE_ERR_PHY_ADDR_INVALID;
4468         uint8_t databyte = 0xFF;
4469         uint8_t *data = info->data;
4470         uint32_t i = 0;
4471
4472         if (info->length == 0)
4473                 return -EINVAL;
4474
4475         for (i = info->offset; i < info->offset + info->length; i++) {
4476                 if (i < RTE_ETH_MODULE_SFF_8079_LEN)
4477                         status = hw->phy.read_i2c_eeprom(hw, i, &databyte);
4478                 else
4479                         status = hw->phy.read_i2c_sff8472(hw, i, &databyte);
4480
4481                 if (status != 0)
4482                         return -EIO;
4483
4484                 data[i - info->offset] = databyte;
4485         }
4486
4487         return 0;
4488 }
4489
4490 bool
4491 txgbe_rss_update_sp(enum txgbe_mac_type mac_type)
4492 {
4493         switch (mac_type) {
4494         case txgbe_mac_raptor:
4495                 return 1;
4496         default:
4497                 return 0;
4498         }
4499 }
4500
4501 static int
4502 txgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
4503                         struct rte_eth_dcb_info *dcb_info)
4504 {
4505         struct txgbe_dcb_config *dcb_config = TXGBE_DEV_DCB_CONFIG(dev);
4506         struct txgbe_dcb_tc_config *tc;
4507         struct rte_eth_dcb_tc_queue_mapping *tc_queue;
4508         uint8_t nb_tcs;
4509         uint8_t i, j;
4510
4511         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
4512                 dcb_info->nb_tcs = dcb_config->num_tcs.pg_tcs;
4513         else
4514                 dcb_info->nb_tcs = 1;
4515
4516         tc_queue = &dcb_info->tc_queue;
4517         nb_tcs = dcb_info->nb_tcs;
4518
4519         if (dcb_config->vt_mode) { /* vt is enabled */
4520                 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
4521                                 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
4522                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
4523                         dcb_info->prio_tc[i] = vmdq_rx_conf->dcb_tc[i];
4524                 if (RTE_ETH_DEV_SRIOV(dev).active > 0) {
4525                         for (j = 0; j < nb_tcs; j++) {
4526                                 tc_queue->tc_rxq[0][j].base = j;
4527                                 tc_queue->tc_rxq[0][j].nb_queue = 1;
4528                                 tc_queue->tc_txq[0][j].base = j;
4529                                 tc_queue->tc_txq[0][j].nb_queue = 1;
4530                         }
4531                 } else {
4532                         for (i = 0; i < vmdq_rx_conf->nb_queue_pools; i++) {
4533                                 for (j = 0; j < nb_tcs; j++) {
4534                                         tc_queue->tc_rxq[i][j].base =
4535                                                 i * nb_tcs + j;
4536                                         tc_queue->tc_rxq[i][j].nb_queue = 1;
4537                                         tc_queue->tc_txq[i][j].base =
4538                                                 i * nb_tcs + j;
4539                                         tc_queue->tc_txq[i][j].nb_queue = 1;
4540                                 }
4541                         }
4542                 }
4543         } else { /* vt is disabled */
4544                 struct rte_eth_dcb_rx_conf *rx_conf =
4545                                 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
4546                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
4547                         dcb_info->prio_tc[i] = rx_conf->dcb_tc[i];
4548                 if (dcb_info->nb_tcs == ETH_4_TCS) {
4549                         for (i = 0; i < dcb_info->nb_tcs; i++) {
4550                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 32;
4551                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
4552                         }
4553                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
4554                         dcb_info->tc_queue.tc_txq[0][1].base = 64;
4555                         dcb_info->tc_queue.tc_txq[0][2].base = 96;
4556                         dcb_info->tc_queue.tc_txq[0][3].base = 112;
4557                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 64;
4558                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
4559                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
4560                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
4561                 } else if (dcb_info->nb_tcs == ETH_8_TCS) {
4562                         for (i = 0; i < dcb_info->nb_tcs; i++) {
4563                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 16;
4564                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
4565                         }
4566                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
4567                         dcb_info->tc_queue.tc_txq[0][1].base = 32;
4568                         dcb_info->tc_queue.tc_txq[0][2].base = 64;
4569                         dcb_info->tc_queue.tc_txq[0][3].base = 80;
4570                         dcb_info->tc_queue.tc_txq[0][4].base = 96;
4571                         dcb_info->tc_queue.tc_txq[0][5].base = 104;
4572                         dcb_info->tc_queue.tc_txq[0][6].base = 112;
4573                         dcb_info->tc_queue.tc_txq[0][7].base = 120;
4574                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 32;
4575                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
4576                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
4577                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
4578                         dcb_info->tc_queue.tc_txq[0][4].nb_queue = 8;
4579                         dcb_info->tc_queue.tc_txq[0][5].nb_queue = 8;
4580                         dcb_info->tc_queue.tc_txq[0][6].nb_queue = 8;
4581                         dcb_info->tc_queue.tc_txq[0][7].nb_queue = 8;
4582                 }
4583         }
4584         for (i = 0; i < dcb_info->nb_tcs; i++) {
4585                 tc = &dcb_config->tc_config[i];
4586                 dcb_info->tc_bws[i] = tc->path[TXGBE_DCB_TX_CONFIG].bwg_percent;
4587         }
4588         return 0;
4589 }
4590
4591 /* Update e-tag ether type */
4592 static int
4593 txgbe_update_e_tag_eth_type(struct txgbe_hw *hw,
4594                             uint16_t ether_type)
4595 {
4596         uint32_t etag_etype;
4597
4598         etag_etype = rd32(hw, TXGBE_EXTAG);
4599         etag_etype &= ~TXGBE_EXTAG_ETAG_MASK;
4600         etag_etype |= ether_type;
4601         wr32(hw, TXGBE_EXTAG, etag_etype);
4602         txgbe_flush(hw);
4603
4604         return 0;
4605 }
4606
4607 /* Enable e-tag tunnel */
4608 static int
4609 txgbe_e_tag_enable(struct txgbe_hw *hw)
4610 {
4611         uint32_t etag_etype;
4612
4613         etag_etype = rd32(hw, TXGBE_PORTCTL);
4614         etag_etype |= TXGBE_PORTCTL_ETAG;
4615         wr32(hw, TXGBE_PORTCTL, etag_etype);
4616         txgbe_flush(hw);
4617
4618         return 0;
4619 }
4620
4621 static int
4622 txgbe_e_tag_filter_del(struct rte_eth_dev *dev,
4623                        struct txgbe_l2_tunnel_conf  *l2_tunnel)
4624 {
4625         int ret = 0;
4626         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4627         uint32_t i, rar_entries;
4628         uint32_t rar_low, rar_high;
4629
4630         rar_entries = hw->mac.num_rar_entries;
4631
4632         for (i = 1; i < rar_entries; i++) {
4633                 wr32(hw, TXGBE_ETHADDRIDX, i);
4634                 rar_high = rd32(hw, TXGBE_ETHADDRH);
4635                 rar_low  = rd32(hw, TXGBE_ETHADDRL);
4636                 if ((rar_high & TXGBE_ETHADDRH_VLD) &&
4637                     (rar_high & TXGBE_ETHADDRH_ETAG) &&
4638                     (TXGBE_ETHADDRL_ETAG(rar_low) ==
4639                      l2_tunnel->tunnel_id)) {
4640                         wr32(hw, TXGBE_ETHADDRL, 0);
4641                         wr32(hw, TXGBE_ETHADDRH, 0);
4642
4643                         txgbe_clear_vmdq(hw, i, BIT_MASK32);
4644
4645                         return ret;
4646                 }
4647         }
4648
4649         return ret;
4650 }
4651
4652 static int
4653 txgbe_e_tag_filter_add(struct rte_eth_dev *dev,
4654                        struct txgbe_l2_tunnel_conf *l2_tunnel)
4655 {
4656         int ret = 0;
4657         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4658         uint32_t i, rar_entries;
4659         uint32_t rar_low, rar_high;
4660
4661         /* One entry for one tunnel. Try to remove potential existing entry. */
4662         txgbe_e_tag_filter_del(dev, l2_tunnel);
4663
4664         rar_entries = hw->mac.num_rar_entries;
4665
4666         for (i = 1; i < rar_entries; i++) {
4667                 wr32(hw, TXGBE_ETHADDRIDX, i);
4668                 rar_high = rd32(hw, TXGBE_ETHADDRH);
4669                 if (rar_high & TXGBE_ETHADDRH_VLD) {
4670                         continue;
4671                 } else {
4672                         txgbe_set_vmdq(hw, i, l2_tunnel->pool);
4673                         rar_high = TXGBE_ETHADDRH_VLD | TXGBE_ETHADDRH_ETAG;
4674                         rar_low = l2_tunnel->tunnel_id;
4675
4676                         wr32(hw, TXGBE_ETHADDRL, rar_low);
4677                         wr32(hw, TXGBE_ETHADDRH, rar_high);
4678
4679                         return ret;
4680                 }
4681         }
4682
4683         PMD_INIT_LOG(NOTICE, "The table of E-tag forwarding rule is full."
4684                      " Please remove a rule before adding a new one.");
4685         return -EINVAL;
4686 }
4687
4688 static inline struct txgbe_l2_tn_filter *
4689 txgbe_l2_tn_filter_lookup(struct txgbe_l2_tn_info *l2_tn_info,
4690                           struct txgbe_l2_tn_key *key)
4691 {
4692         int ret;
4693
4694         ret = rte_hash_lookup(l2_tn_info->hash_handle, (const void *)key);
4695         if (ret < 0)
4696                 return NULL;
4697
4698         return l2_tn_info->hash_map[ret];
4699 }
4700
4701 static inline int
4702 txgbe_insert_l2_tn_filter(struct txgbe_l2_tn_info *l2_tn_info,
4703                           struct txgbe_l2_tn_filter *l2_tn_filter)
4704 {
4705         int ret;
4706
4707         ret = rte_hash_add_key(l2_tn_info->hash_handle,
4708                                &l2_tn_filter->key);
4709
4710         if (ret < 0) {
4711                 PMD_DRV_LOG(ERR,
4712                             "Failed to insert L2 tunnel filter"
4713                             " to hash table %d!",
4714                             ret);
4715                 return ret;
4716         }
4717
4718         l2_tn_info->hash_map[ret] = l2_tn_filter;
4719
4720         TAILQ_INSERT_TAIL(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
4721
4722         return 0;
4723 }
4724
4725 static inline int
4726 txgbe_remove_l2_tn_filter(struct txgbe_l2_tn_info *l2_tn_info,
4727                           struct txgbe_l2_tn_key *key)
4728 {
4729         int ret;
4730         struct txgbe_l2_tn_filter *l2_tn_filter;
4731
4732         ret = rte_hash_del_key(l2_tn_info->hash_handle, key);
4733
4734         if (ret < 0) {
4735                 PMD_DRV_LOG(ERR,
4736                             "No such L2 tunnel filter to delete %d!",
4737                             ret);
4738                 return ret;
4739         }
4740
4741         l2_tn_filter = l2_tn_info->hash_map[ret];
4742         l2_tn_info->hash_map[ret] = NULL;
4743
4744         TAILQ_REMOVE(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
4745         rte_free(l2_tn_filter);
4746
4747         return 0;
4748 }
4749
4750 /* Add l2 tunnel filter */
4751 int
4752 txgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev,
4753                                struct txgbe_l2_tunnel_conf *l2_tunnel,
4754                                bool restore)
4755 {
4756         int ret;
4757         struct txgbe_l2_tn_info *l2_tn_info = TXGBE_DEV_L2_TN(dev);
4758         struct txgbe_l2_tn_key key;
4759         struct txgbe_l2_tn_filter *node;
4760
4761         if (!restore) {
4762                 key.l2_tn_type = l2_tunnel->l2_tunnel_type;
4763                 key.tn_id = l2_tunnel->tunnel_id;
4764
4765                 node = txgbe_l2_tn_filter_lookup(l2_tn_info, &key);
4766
4767                 if (node) {
4768                         PMD_DRV_LOG(ERR,
4769                                     "The L2 tunnel filter already exists!");
4770                         return -EINVAL;
4771                 }
4772
4773                 node = rte_zmalloc("txgbe_l2_tn",
4774                                    sizeof(struct txgbe_l2_tn_filter),
4775                                    0);
4776                 if (!node)
4777                         return -ENOMEM;
4778
4779                 rte_memcpy(&node->key,
4780                                  &key,
4781                                  sizeof(struct txgbe_l2_tn_key));
4782                 node->pool = l2_tunnel->pool;
4783                 ret = txgbe_insert_l2_tn_filter(l2_tn_info, node);
4784                 if (ret < 0) {
4785                         rte_free(node);
4786                         return ret;
4787                 }
4788         }
4789
4790         switch (l2_tunnel->l2_tunnel_type) {
4791         case RTE_L2_TUNNEL_TYPE_E_TAG:
4792                 ret = txgbe_e_tag_filter_add(dev, l2_tunnel);
4793                 break;
4794         default:
4795                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
4796                 ret = -EINVAL;
4797                 break;
4798         }
4799
4800         if (!restore && ret < 0)
4801                 (void)txgbe_remove_l2_tn_filter(l2_tn_info, &key);
4802
4803         return ret;
4804 }
4805
4806 /* Delete l2 tunnel filter */
4807 int
4808 txgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev,
4809                                struct txgbe_l2_tunnel_conf *l2_tunnel)
4810 {
4811         int ret;
4812         struct txgbe_l2_tn_info *l2_tn_info = TXGBE_DEV_L2_TN(dev);
4813         struct txgbe_l2_tn_key key;
4814
4815         key.l2_tn_type = l2_tunnel->l2_tunnel_type;
4816         key.tn_id = l2_tunnel->tunnel_id;
4817         ret = txgbe_remove_l2_tn_filter(l2_tn_info, &key);
4818         if (ret < 0)
4819                 return ret;
4820
4821         switch (l2_tunnel->l2_tunnel_type) {
4822         case RTE_L2_TUNNEL_TYPE_E_TAG:
4823                 ret = txgbe_e_tag_filter_del(dev, l2_tunnel);
4824                 break;
4825         default:
4826                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
4827                 ret = -EINVAL;
4828                 break;
4829         }
4830
4831         return ret;
4832 }
4833
4834 static int
4835 txgbe_e_tag_forwarding_en_dis(struct rte_eth_dev *dev, bool en)
4836 {
4837         int ret = 0;
4838         uint32_t ctrl;
4839         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4840
4841         ctrl = rd32(hw, TXGBE_POOLCTL);
4842         ctrl &= ~TXGBE_POOLCTL_MODE_MASK;
4843         if (en)
4844                 ctrl |= TXGBE_PSRPOOL_MODE_ETAG;
4845         wr32(hw, TXGBE_POOLCTL, ctrl);
4846
4847         return ret;
4848 }
4849
4850 /* restore n-tuple filter */
4851 static inline void
4852 txgbe_ntuple_filter_restore(struct rte_eth_dev *dev)
4853 {
4854         struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(dev);
4855         struct txgbe_5tuple_filter *node;
4856
4857         TAILQ_FOREACH(node, &filter_info->fivetuple_list, entries) {
4858                 txgbe_inject_5tuple_filter(dev, node);
4859         }
4860 }
4861
4862 /* restore ethernet type filter */
4863 static inline void
4864 txgbe_ethertype_filter_restore(struct rte_eth_dev *dev)
4865 {
4866         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4867         struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(dev);
4868         int i;
4869
4870         for (i = 0; i < TXGBE_ETF_ID_MAX; i++) {
4871                 if (filter_info->ethertype_mask & (1 << i)) {
4872                         wr32(hw, TXGBE_ETFLT(i),
4873                                         filter_info->ethertype_filters[i].etqf);
4874                         wr32(hw, TXGBE_ETCLS(i),
4875                                         filter_info->ethertype_filters[i].etqs);
4876                         txgbe_flush(hw);
4877                 }
4878         }
4879 }
4880
4881 /* restore SYN filter */
4882 static inline void
4883 txgbe_syn_filter_restore(struct rte_eth_dev *dev)
4884 {
4885         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4886         struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(dev);
4887         uint32_t synqf;
4888
4889         synqf = filter_info->syn_info;
4890
4891         if (synqf & TXGBE_SYNCLS_ENA) {
4892                 wr32(hw, TXGBE_SYNCLS, synqf);
4893                 txgbe_flush(hw);
4894         }
4895 }
4896
4897 /* restore L2 tunnel filter */
4898 static inline void
4899 txgbe_l2_tn_filter_restore(struct rte_eth_dev *dev)
4900 {
4901         struct txgbe_l2_tn_info *l2_tn_info = TXGBE_DEV_L2_TN(dev);
4902         struct txgbe_l2_tn_filter *node;
4903         struct txgbe_l2_tunnel_conf l2_tn_conf;
4904
4905         TAILQ_FOREACH(node, &l2_tn_info->l2_tn_list, entries) {
4906                 l2_tn_conf.l2_tunnel_type = node->key.l2_tn_type;
4907                 l2_tn_conf.tunnel_id      = node->key.tn_id;
4908                 l2_tn_conf.pool           = node->pool;
4909                 (void)txgbe_dev_l2_tunnel_filter_add(dev, &l2_tn_conf, TRUE);
4910         }
4911 }
4912
4913 static int
4914 txgbe_filter_restore(struct rte_eth_dev *dev)
4915 {
4916         txgbe_ntuple_filter_restore(dev);
4917         txgbe_ethertype_filter_restore(dev);
4918         txgbe_syn_filter_restore(dev);
4919         txgbe_l2_tn_filter_restore(dev);
4920
4921         return 0;
4922 }
4923
4924 static void
4925 txgbe_l2_tunnel_conf(struct rte_eth_dev *dev)
4926 {
4927         struct txgbe_l2_tn_info *l2_tn_info = TXGBE_DEV_L2_TN(dev);
4928         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4929
4930         if (l2_tn_info->e_tag_en)
4931                 (void)txgbe_e_tag_enable(hw);
4932
4933         if (l2_tn_info->e_tag_fwd_en)
4934                 (void)txgbe_e_tag_forwarding_en_dis(dev, 1);
4935
4936         (void)txgbe_update_e_tag_eth_type(hw, l2_tn_info->e_tag_ether_type);
4937 }
4938
4939 static const struct eth_dev_ops txgbe_eth_dev_ops = {
4940         .dev_configure              = txgbe_dev_configure,
4941         .dev_infos_get              = txgbe_dev_info_get,
4942         .dev_start                  = txgbe_dev_start,
4943         .dev_stop                   = txgbe_dev_stop,
4944         .dev_set_link_up            = txgbe_dev_set_link_up,
4945         .dev_set_link_down          = txgbe_dev_set_link_down,
4946         .dev_close                  = txgbe_dev_close,
4947         .dev_reset                  = txgbe_dev_reset,
4948         .promiscuous_enable         = txgbe_dev_promiscuous_enable,
4949         .promiscuous_disable        = txgbe_dev_promiscuous_disable,
4950         .allmulticast_enable        = txgbe_dev_allmulticast_enable,
4951         .allmulticast_disable       = txgbe_dev_allmulticast_disable,
4952         .link_update                = txgbe_dev_link_update,
4953         .stats_get                  = txgbe_dev_stats_get,
4954         .xstats_get                 = txgbe_dev_xstats_get,
4955         .xstats_get_by_id           = txgbe_dev_xstats_get_by_id,
4956         .stats_reset                = txgbe_dev_stats_reset,
4957         .xstats_reset               = txgbe_dev_xstats_reset,
4958         .xstats_get_names           = txgbe_dev_xstats_get_names,
4959         .xstats_get_names_by_id     = txgbe_dev_xstats_get_names_by_id,
4960         .queue_stats_mapping_set    = txgbe_dev_queue_stats_mapping_set,
4961         .fw_version_get             = txgbe_fw_version_get,
4962         .dev_supported_ptypes_get   = txgbe_dev_supported_ptypes_get,
4963         .mtu_set                    = txgbe_dev_mtu_set,
4964         .vlan_filter_set            = txgbe_vlan_filter_set,
4965         .vlan_tpid_set              = txgbe_vlan_tpid_set,
4966         .vlan_offload_set           = txgbe_vlan_offload_set,
4967         .vlan_strip_queue_set       = txgbe_vlan_strip_queue_set,
4968         .rx_queue_start             = txgbe_dev_rx_queue_start,
4969         .rx_queue_stop              = txgbe_dev_rx_queue_stop,
4970         .tx_queue_start             = txgbe_dev_tx_queue_start,
4971         .tx_queue_stop              = txgbe_dev_tx_queue_stop,
4972         .rx_queue_setup             = txgbe_dev_rx_queue_setup,
4973         .rx_queue_intr_enable       = txgbe_dev_rx_queue_intr_enable,
4974         .rx_queue_intr_disable      = txgbe_dev_rx_queue_intr_disable,
4975         .rx_queue_release           = txgbe_dev_rx_queue_release,
4976         .tx_queue_setup             = txgbe_dev_tx_queue_setup,
4977         .tx_queue_release           = txgbe_dev_tx_queue_release,
4978         .dev_led_on                 = txgbe_dev_led_on,
4979         .dev_led_off                = txgbe_dev_led_off,
4980         .flow_ctrl_get              = txgbe_flow_ctrl_get,
4981         .flow_ctrl_set              = txgbe_flow_ctrl_set,
4982         .priority_flow_ctrl_set     = txgbe_priority_flow_ctrl_set,
4983         .mac_addr_add               = txgbe_add_rar,
4984         .mac_addr_remove            = txgbe_remove_rar,
4985         .mac_addr_set               = txgbe_set_default_mac_addr,
4986         .uc_hash_table_set          = txgbe_uc_hash_table_set,
4987         .uc_all_hash_table_set      = txgbe_uc_all_hash_table_set,
4988         .set_queue_rate_limit       = txgbe_set_queue_rate_limit,
4989         .reta_update                = txgbe_dev_rss_reta_update,
4990         .reta_query                 = txgbe_dev_rss_reta_query,
4991         .rss_hash_update            = txgbe_dev_rss_hash_update,
4992         .rss_hash_conf_get          = txgbe_dev_rss_hash_conf_get,
4993         .filter_ctrl                = txgbe_dev_filter_ctrl,
4994         .set_mc_addr_list           = txgbe_dev_set_mc_addr_list,
4995         .rxq_info_get               = txgbe_rxq_info_get,
4996         .txq_info_get               = txgbe_txq_info_get,
4997         .timesync_enable            = txgbe_timesync_enable,
4998         .timesync_disable           = txgbe_timesync_disable,
4999         .timesync_read_rx_timestamp = txgbe_timesync_read_rx_timestamp,
5000         .timesync_read_tx_timestamp = txgbe_timesync_read_tx_timestamp,
5001         .get_reg                    = txgbe_get_regs,
5002         .get_eeprom_length          = txgbe_get_eeprom_length,
5003         .get_eeprom                 = txgbe_get_eeprom,
5004         .set_eeprom                 = txgbe_set_eeprom,
5005         .get_module_info            = txgbe_get_module_info,
5006         .get_module_eeprom          = txgbe_get_module_eeprom,
5007         .get_dcb_info               = txgbe_dev_get_dcb_info,
5008         .timesync_adjust_time       = txgbe_timesync_adjust_time,
5009         .timesync_read_time         = txgbe_timesync_read_time,
5010         .timesync_write_time        = txgbe_timesync_write_time,
5011         .tx_done_cleanup            = txgbe_dev_tx_done_cleanup,
5012 };
5013
5014 RTE_PMD_REGISTER_PCI(net_txgbe, rte_txgbe_pmd);
5015 RTE_PMD_REGISTER_PCI_TABLE(net_txgbe, pci_id_txgbe_map);
5016 RTE_PMD_REGISTER_KMOD_DEP(net_txgbe, "* igb_uio | uio_pci_generic | vfio-pci");
5017
5018 RTE_LOG_REGISTER(txgbe_logtype_init, pmd.net.txgbe.init, NOTICE);
5019 RTE_LOG_REGISTER(txgbe_logtype_driver, pmd.net.txgbe.driver, NOTICE);
5020
5021 #ifdef RTE_LIBRTE_TXGBE_DEBUG_RX
5022         RTE_LOG_REGISTER(txgbe_logtype_rx, pmd.net.txgbe.rx, DEBUG);
5023 #endif
5024 #ifdef RTE_LIBRTE_TXGBE_DEBUG_TX
5025         RTE_LOG_REGISTER(txgbe_logtype_tx, pmd.net.txgbe.tx, DEBUG);
5026 #endif
5027
5028 #ifdef RTE_LIBRTE_TXGBE_DEBUG_TX_FREE
5029         RTE_LOG_REGISTER(txgbe_logtype_tx_free, pmd.net.txgbe.tx_free, DEBUG);
5030 #endif