1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2015-2020
5 #ifndef _TXGBE_ETHDEV_H_
6 #define _TXGBE_ETHDEV_H_
10 #include "base/txgbe.h"
11 #include "txgbe_ptypes.h"
13 #include <rte_flow_driver.h>
15 #include <rte_ethdev.h>
16 #include <rte_ethdev_core.h>
18 #include <rte_hash_crc.h>
19 #include <rte_tm_driver.h>
21 /* need update link, bit flag */
22 #define TXGBE_FLAG_NEED_LINK_UPDATE (uint32_t)(1 << 0)
23 #define TXGBE_FLAG_MAILBOX (uint32_t)(1 << 1)
24 #define TXGBE_FLAG_PHY_INTERRUPT (uint32_t)(1 << 2)
25 #define TXGBE_FLAG_MACSEC (uint32_t)(1 << 3)
26 #define TXGBE_FLAG_NEED_LINK_CONFIG (uint32_t)(1 << 4)
29 * Defines that were not part of txgbe_type.h as they are not used by the
32 #define TXGBE_VFTA_SIZE 128
33 #define TXGBE_VLAN_TAG_SIZE 4
34 #define TXGBE_HKEY_MAX_INDEX 10
35 /*Default value of Max Rx Queue*/
36 #define TXGBE_MAX_RX_QUEUE_NUM 128
37 #define TXGBE_VMDQ_DCB_NB_QUEUES TXGBE_MAX_RX_QUEUE_NUM
40 #define NBBY 8 /* number of bits in a byte */
42 #define TXGBE_HWSTRIP_BITMAP_SIZE \
43 (TXGBE_MAX_RX_QUEUE_NUM / (sizeof(uint32_t) * NBBY))
45 #define TXGBE_QUEUE_ITR_INTERVAL_DEFAULT 500 /* 500us */
47 #define TXGBE_MAX_QUEUE_NUM_PER_VF 8
49 #define TXGBE_5TUPLE_MAX_PRI 7
50 #define TXGBE_5TUPLE_MIN_PRI 1
52 #define TXGBE_RSS_OFFLOAD_ALL ( \
54 ETH_RSS_NONFRAG_IPV4_TCP | \
55 ETH_RSS_NONFRAG_IPV4_UDP | \
57 ETH_RSS_NONFRAG_IPV6_TCP | \
58 ETH_RSS_NONFRAG_IPV6_UDP | \
60 ETH_RSS_IPV6_TCP_EX | \
63 #define TXGBE_MISC_VEC_ID RTE_INTR_VEC_ZERO_OFFSET
64 #define TXGBE_RX_VEC_START RTE_INTR_VEC_RXTX_OFFSET
66 #define TXGBE_MAX_FDIR_FILTER_NUM (1024 * 32)
67 #define TXGBE_MAX_L2_TN_FILTER_NUM 128
70 * Information about the fdir mode.
72 struct txgbe_hw_fdir_mask {
73 uint16_t vlan_tci_mask;
74 uint32_t src_ipv4_mask;
75 uint32_t dst_ipv4_mask;
76 uint16_t src_ipv6_mask;
77 uint16_t dst_ipv6_mask;
78 uint16_t src_port_mask;
79 uint16_t dst_port_mask;
80 uint16_t flex_bytes_mask;
81 uint8_t mac_addr_byte_mask;
82 uint32_t tunnel_id_mask;
83 uint8_t tunnel_type_mask;
86 struct txgbe_fdir_filter {
87 TAILQ_ENTRY(txgbe_fdir_filter) entries;
88 struct txgbe_atr_input input; /* key of fdir filter*/
89 uint32_t fdirflags; /* drop or forward */
90 uint32_t fdirhash; /* hash value for fdir */
91 uint8_t queue; /* assigned rx queue */
94 /* list of fdir filters */
95 TAILQ_HEAD(txgbe_fdir_filter_list, txgbe_fdir_filter);
97 struct txgbe_fdir_rule {
98 struct txgbe_hw_fdir_mask mask;
99 struct txgbe_atr_input input; /* key of fdir filter */
100 bool b_spec; /* If TRUE, input, fdirflags, queue have meaning. */
101 bool b_mask; /* If TRUE, mask has meaning. */
102 enum rte_fdir_mode mode; /* IP, MAC VLAN, Tunnel */
103 uint32_t fdirflags; /* drop or forward */
104 uint32_t soft_id; /* an unique value for this rule */
105 uint8_t queue; /* assigned rx queue */
106 uint8_t flex_bytes_offset;
109 struct txgbe_hw_fdir_info {
110 struct txgbe_hw_fdir_mask mask;
111 uint8_t flex_bytes_offset;
120 struct txgbe_fdir_filter_list fdir_list; /* filter list*/
121 /* store the pointers of the filters, index is the hash value. */
122 struct txgbe_fdir_filter **hash_map;
123 struct rte_hash *hash_handle; /* cuckoo hash handler */
124 bool mask_added; /* If already got mask from consistent filter */
127 struct txgbe_rte_flow_rss_conf {
128 struct rte_flow_action_rss conf; /**< RSS parameters. */
129 uint8_t key[TXGBE_HKEY_MAX_INDEX * sizeof(uint32_t)]; /* Hash key. */
130 uint16_t queue[TXGBE_MAX_RX_QUEUE_NUM]; /**< Queues indices to use. */
133 /* structure for interrupt relative data */
134 struct txgbe_interrupt {
137 /* to save original mask during delayed handler */
138 uint32_t mask_misc_orig;
142 #define TXGBE_NB_STAT_MAPPING 32
143 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
144 #define NB_QMAP_FIELDS_PER_QSM_REG 4
145 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
146 struct txgbe_stat_mappings {
147 uint32_t tqsm[TXGBE_NB_STAT_MAPPING];
148 uint32_t rqsm[TXGBE_NB_STAT_MAPPING];
152 uint32_t vfta[TXGBE_VFTA_SIZE];
155 struct txgbe_hwstrip {
156 uint32_t bitmap[TXGBE_HWSTRIP_BITMAP_SIZE];
160 * VF data which used by PF host only
162 #define TXGBE_MAX_VF_MC_ENTRIES 30
164 struct txgbe_uta_info {
165 uint8_t uc_filter_type;
167 uint32_t uta_shadow[TXGBE_MAX_UTA];
170 #define TXGBE_MAX_MIRROR_RULES 4 /* Maximum nb. of mirror rules. */
172 struct txgbe_mirror_info {
173 struct rte_eth_mirror_conf mr_conf[TXGBE_MAX_MIRROR_RULES];
174 /* store PF mirror rules configuration */
177 struct txgbe_vf_info {
178 uint8_t vf_mac_addresses[RTE_ETHER_ADDR_LEN];
179 uint16_t vf_mc_hashes[TXGBE_MAX_VF_MC_ENTRIES];
180 uint16_t num_vf_mc_hashes;
182 uint16_t tx_rate[TXGBE_MAX_QUEUE_NUM_PER_VF];
185 uint16_t switch_domain_id;
190 TAILQ_HEAD(txgbe_5tuple_filter_list, txgbe_5tuple_filter);
192 struct txgbe_5tuple_filter_info {
197 enum txgbe_5tuple_protocol proto; /* l4 protocol. */
198 uint8_t priority; /* seven levels (001b-111b), 111b is highest,
199 * used when more than one filter matches.
201 uint8_t dst_ip_mask:1, /* if mask is 1b, do not compare dst ip. */
202 src_ip_mask:1, /* if mask is 1b, do not compare src ip. */
203 dst_port_mask:1, /* if mask is 1b, do not compare dst port. */
204 src_port_mask:1, /* if mask is 1b, do not compare src port. */
205 proto_mask:1; /* if mask is 1b, do not compare protocol. */
208 /* 5tuple filter structure */
209 struct txgbe_5tuple_filter {
210 TAILQ_ENTRY(txgbe_5tuple_filter) entries;
211 uint16_t index; /* the index of 5tuple filter */
212 struct txgbe_5tuple_filter_info filter_info;
213 uint16_t queue; /* rx queue assigned to */
216 #define TXGBE_5TUPLE_ARRAY_SIZE \
217 (RTE_ALIGN(TXGBE_MAX_FTQF_FILTERS, (sizeof(uint32_t) * NBBY)) / \
218 (sizeof(uint32_t) * NBBY))
220 struct txgbe_ethertype_filter {
225 * If this filter is added by configuration,
226 * it should not be removed.
232 * Structure to store filters' info.
234 struct txgbe_filter_info {
235 uint8_t ethertype_mask; /* Bit mask for every used ethertype filter */
236 /* store used ethertype filters*/
237 struct txgbe_ethertype_filter ethertype_filters[TXGBE_ETF_ID_MAX];
238 /* Bit mask for every used 5tuple filter */
239 uint32_t fivetuple_mask[TXGBE_5TUPLE_ARRAY_SIZE];
240 struct txgbe_5tuple_filter_list fivetuple_list;
241 /* store the SYN filter info */
243 /* store the rss filter info */
244 struct txgbe_rte_flow_rss_conf rss_info;
247 struct txgbe_l2_tn_key {
248 enum rte_eth_tunnel_type l2_tn_type;
252 struct txgbe_l2_tn_filter {
253 TAILQ_ENTRY(txgbe_l2_tn_filter) entries;
254 struct txgbe_l2_tn_key key;
258 TAILQ_HEAD(txgbe_l2_tn_filter_list, txgbe_l2_tn_filter);
260 struct txgbe_l2_tn_info {
261 struct txgbe_l2_tn_filter_list l2_tn_list;
262 struct txgbe_l2_tn_filter **hash_map;
263 struct rte_hash *hash_handle;
264 bool e_tag_en; /* e-tag enabled */
265 bool e_tag_fwd_en; /* e-tag based forwarding enabled */
266 uint16_t e_tag_ether_type; /* ether type for e-tag */
270 enum rte_filter_type filter_type;
274 /* The configuration of bandwidth */
275 struct txgbe_bw_conf {
276 uint8_t tc_num; /* Number of TCs. */
279 /* Struct to store Traffic Manager shaper profile. */
280 struct txgbe_tm_shaper_profile {
281 TAILQ_ENTRY(txgbe_tm_shaper_profile) node;
282 uint32_t shaper_profile_id;
283 uint32_t reference_count;
284 struct rte_tm_shaper_params profile;
287 TAILQ_HEAD(txgbe_shaper_profile_list, txgbe_tm_shaper_profile);
289 /* node type of Traffic Manager */
290 enum txgbe_tm_node_type {
291 TXGBE_TM_NODE_TYPE_PORT,
292 TXGBE_TM_NODE_TYPE_TC,
293 TXGBE_TM_NODE_TYPE_QUEUE,
294 TXGBE_TM_NODE_TYPE_MAX,
297 /* Struct to store Traffic Manager node configuration. */
298 struct txgbe_tm_node {
299 TAILQ_ENTRY(txgbe_tm_node) node;
303 uint32_t reference_count;
305 struct txgbe_tm_node *parent;
306 struct txgbe_tm_shaper_profile *shaper_profile;
307 struct rte_tm_node_params params;
310 TAILQ_HEAD(txgbe_tm_node_list, txgbe_tm_node);
312 /* The configuration of Traffic Manager */
313 struct txgbe_tm_conf {
314 struct txgbe_shaper_profile_list shaper_profile_list;
315 struct txgbe_tm_node *root; /* root node - port */
316 struct txgbe_tm_node_list tc_list; /* node list for all the TCs */
317 struct txgbe_tm_node_list queue_list; /* node list for all the queues */
319 * The number of added TC nodes.
320 * It should be no more than the TC number of this port.
324 * The number of added queue nodes.
325 * It should be no more than the queue number of this port.
327 uint32_t nb_queue_node;
329 * This flag is used to check if APP can change the TM node
331 * When it's true, means the configuration is applied to HW,
332 * APP should not change the configuration.
333 * As we don't support on-the-fly configuration, when starting
334 * the port, APP should call the hierarchy_commit API to set this
335 * flag to true. When stopping the port, this flag should be set
342 * Structure to store private data for each driver instance (for each port).
344 struct txgbe_adapter {
346 struct txgbe_hw_stats stats;
347 struct txgbe_hw_fdir_info fdir;
348 struct txgbe_interrupt intr;
349 struct txgbe_stat_mappings stat_mappings;
350 struct txgbe_vfta shadow_vfta;
351 struct txgbe_hwstrip hwstrip;
352 struct txgbe_dcb_config dcb_config;
353 struct txgbe_mirror_info mr_data;
354 struct txgbe_vf_info *vfdata;
355 struct txgbe_uta_info uta_info;
356 struct txgbe_filter_info filter;
357 struct txgbe_l2_tn_info l2_tn;
358 struct txgbe_bw_conf bw_conf;
359 bool rx_bulk_alloc_allowed;
360 struct rte_timecounter systime_tc;
361 struct rte_timecounter rx_tstamp_tc;
362 struct rte_timecounter tx_tstamp_tc;
363 struct txgbe_tm_conf tm_conf;
365 /* For RSS reta table update */
366 uint8_t rss_reta_updated;
369 #define TXGBE_DEV_ADAPTER(dev) \
370 ((struct txgbe_adapter *)(dev)->data->dev_private)
372 #define TXGBE_DEV_HW(dev) \
373 (&((struct txgbe_adapter *)(dev)->data->dev_private)->hw)
375 #define TXGBE_DEV_STATS(dev) \
376 (&((struct txgbe_adapter *)(dev)->data->dev_private)->stats)
378 #define TXGBE_DEV_INTR(dev) \
379 (&((struct txgbe_adapter *)(dev)->data->dev_private)->intr)
381 #define TXGBE_DEV_FDIR(dev) \
382 (&((struct txgbe_adapter *)(dev)->data->dev_private)->fdir)
384 #define TXGBE_DEV_STAT_MAPPINGS(dev) \
385 (&((struct txgbe_adapter *)(dev)->data->dev_private)->stat_mappings)
387 #define TXGBE_DEV_VFTA(dev) \
388 (&((struct txgbe_adapter *)(dev)->data->dev_private)->shadow_vfta)
390 #define TXGBE_DEV_HWSTRIP(dev) \
391 (&((struct txgbe_adapter *)(dev)->data->dev_private)->hwstrip)
393 #define TXGBE_DEV_DCB_CONFIG(dev) \
394 (&((struct txgbe_adapter *)(dev)->data->dev_private)->dcb_config)
396 #define TXGBE_DEV_VFDATA(dev) \
397 (&((struct txgbe_adapter *)(dev)->data->dev_private)->vfdata)
399 #define TXGBE_DEV_MR_INFO(dev) \
400 (&((struct txgbe_adapter *)(dev)->data->dev_private)->mr_data)
402 #define TXGBE_DEV_UTA_INFO(dev) \
403 (&((struct txgbe_adapter *)(dev)->data->dev_private)->uta_info)
405 #define TXGBE_DEV_FILTER(dev) \
406 (&((struct txgbe_adapter *)(dev)->data->dev_private)->filter)
408 #define TXGBE_DEV_L2_TN(dev) \
409 (&((struct txgbe_adapter *)(dev)->data->dev_private)->l2_tn)
411 #define TXGBE_DEV_BW_CONF(dev) \
412 (&((struct txgbe_adapter *)(dev)->data->dev_private)->bw_conf)
414 #define TXGBE_DEV_TM_CONF(dev) \
415 (&((struct txgbe_adapter *)(dev)->data->dev_private)->tm_conf)
418 * RX/TX function prototypes
420 void txgbe_dev_clear_queues(struct rte_eth_dev *dev);
422 void txgbe_dev_free_queues(struct rte_eth_dev *dev);
424 void txgbe_dev_rx_queue_release(void *rxq);
426 void txgbe_dev_tx_queue_release(void *txq);
428 int txgbe_dev_rx_queue_setup(struct rte_eth_dev *dev, uint16_t rx_queue_id,
429 uint16_t nb_rx_desc, unsigned int socket_id,
430 const struct rte_eth_rxconf *rx_conf,
431 struct rte_mempool *mb_pool);
433 int txgbe_dev_tx_queue_setup(struct rte_eth_dev *dev, uint16_t tx_queue_id,
434 uint16_t nb_tx_desc, unsigned int socket_id,
435 const struct rte_eth_txconf *tx_conf);
437 uint32_t txgbe_dev_rx_queue_count(struct rte_eth_dev *dev,
438 uint16_t rx_queue_id);
440 int txgbe_dev_rx_descriptor_status(void *rx_queue, uint16_t offset);
441 int txgbe_dev_tx_descriptor_status(void *tx_queue, uint16_t offset);
443 int txgbe_dev_rx_init(struct rte_eth_dev *dev);
445 void txgbe_dev_tx_init(struct rte_eth_dev *dev);
447 int txgbe_dev_rxtx_start(struct rte_eth_dev *dev);
449 void txgbe_dev_save_rx_queue(struct txgbe_hw *hw, uint16_t rx_queue_id);
450 void txgbe_dev_store_rx_queue(struct txgbe_hw *hw, uint16_t rx_queue_id);
451 void txgbe_dev_save_tx_queue(struct txgbe_hw *hw, uint16_t tx_queue_id);
452 void txgbe_dev_store_tx_queue(struct txgbe_hw *hw, uint16_t tx_queue_id);
454 int txgbe_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id);
456 int txgbe_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id);
458 int txgbe_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id);
460 int txgbe_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id);
462 void txgbe_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
463 struct rte_eth_rxq_info *qinfo);
465 void txgbe_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
466 struct rte_eth_txq_info *qinfo);
468 uint16_t txgbe_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
471 uint16_t txgbe_recv_pkts_bulk_alloc(void *rx_queue, struct rte_mbuf **rx_pkts,
474 uint16_t txgbe_recv_pkts_lro_single_alloc(void *rx_queue,
475 struct rte_mbuf **rx_pkts, uint16_t nb_pkts);
476 uint16_t txgbe_recv_pkts_lro_bulk_alloc(void *rx_queue,
477 struct rte_mbuf **rx_pkts, uint16_t nb_pkts);
479 uint16_t txgbe_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
482 uint16_t txgbe_xmit_pkts_simple(void *tx_queue, struct rte_mbuf **tx_pkts,
485 uint16_t txgbe_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
488 int txgbe_dev_rss_hash_update(struct rte_eth_dev *dev,
489 struct rte_eth_rss_conf *rss_conf);
491 int txgbe_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
492 struct rte_eth_rss_conf *rss_conf);
494 bool txgbe_rss_update_sp(enum txgbe_mac_type mac_type);
496 int txgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
497 struct rte_eth_ntuple_filter *filter,
499 int txgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
500 struct rte_eth_ethertype_filter *filter,
502 int txgbe_syn_filter_set(struct rte_eth_dev *dev,
503 struct rte_eth_syn_filter *filter,
507 * l2 tunnel configuration.
509 struct txgbe_l2_tunnel_conf {
510 enum rte_eth_tunnel_type l2_tunnel_type;
511 uint16_t ether_type; /* ether type in l2 header */
512 uint32_t tunnel_id; /* port tag id for e-tag */
513 uint16_t vf_id; /* VF id for tag insertion */
514 uint32_t pool; /* destination pool for tag based forwarding */
518 txgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev,
519 struct txgbe_l2_tunnel_conf *l2_tunnel,
522 txgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev,
523 struct txgbe_l2_tunnel_conf *l2_tunnel);
524 void txgbe_filterlist_init(void);
525 void txgbe_filterlist_flush(void);
527 void txgbe_set_ivar_map(struct txgbe_hw *hw, int8_t direction,
528 uint8_t queue, uint8_t msix_vector);
531 * Flow director function prototypes
533 int txgbe_fdir_configure(struct rte_eth_dev *dev);
534 int txgbe_fdir_set_input_mask(struct rte_eth_dev *dev);
535 int txgbe_fdir_set_flexbytes_offset(struct rte_eth_dev *dev,
537 int txgbe_fdir_filter_program(struct rte_eth_dev *dev,
538 struct txgbe_fdir_rule *rule,
539 bool del, bool update);
541 void txgbe_configure_pb(struct rte_eth_dev *dev);
542 void txgbe_configure_port(struct rte_eth_dev *dev);
543 void txgbe_configure_dcb(struct rte_eth_dev *dev);
546 txgbe_dev_link_update_share(struct rte_eth_dev *dev,
547 int wait_to_complete);
548 int txgbe_pf_host_init(struct rte_eth_dev *eth_dev);
550 void txgbe_pf_host_uninit(struct rte_eth_dev *eth_dev);
552 void txgbe_pf_mbx_process(struct rte_eth_dev *eth_dev);
554 int txgbe_pf_host_configure(struct rte_eth_dev *eth_dev);
556 uint32_t txgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val);
558 void txgbe_fdir_filter_restore(struct rte_eth_dev *dev);
559 int txgbe_clear_all_fdir_filter(struct rte_eth_dev *dev);
561 extern const struct rte_flow_ops txgbe_flow_ops;
563 void txgbe_clear_all_ethertype_filter(struct rte_eth_dev *dev);
564 void txgbe_clear_all_ntuple_filter(struct rte_eth_dev *dev);
565 void txgbe_clear_syn_filter(struct rte_eth_dev *dev);
566 int txgbe_clear_all_l2_tn_filter(struct rte_eth_dev *dev);
568 int txgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
569 uint16_t tx_rate, uint64_t q_msk);
570 int txgbe_tm_ops_get(struct rte_eth_dev *dev, void *ops);
571 void txgbe_tm_conf_init(struct rte_eth_dev *dev);
572 void txgbe_tm_conf_uninit(struct rte_eth_dev *dev);
573 int txgbe_set_queue_rate_limit(struct rte_eth_dev *dev, uint16_t queue_idx,
575 int txgbe_rss_conf_init(struct txgbe_rte_flow_rss_conf *out,
576 const struct rte_flow_action_rss *in);
577 int txgbe_action_rss_same(const struct rte_flow_action_rss *comp,
578 const struct rte_flow_action_rss *with);
579 int txgbe_config_rss_filter(struct rte_eth_dev *dev,
580 struct txgbe_rte_flow_rss_conf *conf, bool add);
583 txgbe_ethertype_filter_lookup(struct txgbe_filter_info *filter_info,
588 for (i = 0; i < TXGBE_ETF_ID_MAX; i++) {
589 if (filter_info->ethertype_filters[i].ethertype == ethertype &&
590 (filter_info->ethertype_mask & (1 << i)))
597 txgbe_ethertype_filter_insert(struct txgbe_filter_info *filter_info,
598 struct txgbe_ethertype_filter *ethertype_filter)
602 for (i = 0; i < TXGBE_ETF_ID_MAX; i++) {
603 if (filter_info->ethertype_mask & (1 << i))
606 filter_info->ethertype_mask |= 1 << i;
607 filter_info->ethertype_filters[i].ethertype =
608 ethertype_filter->ethertype;
609 filter_info->ethertype_filters[i].etqf =
610 ethertype_filter->etqf;
611 filter_info->ethertype_filters[i].etqs =
612 ethertype_filter->etqs;
613 filter_info->ethertype_filters[i].conf =
614 ethertype_filter->conf;
617 return (i < TXGBE_ETF_ID_MAX ? i : -1);
621 txgbe_ethertype_filter_remove(struct txgbe_filter_info *filter_info,
624 if (idx >= TXGBE_ETF_ID_MAX)
626 filter_info->ethertype_mask &= ~(1 << idx);
627 filter_info->ethertype_filters[idx].ethertype = 0;
628 filter_info->ethertype_filters[idx].etqf = 0;
629 filter_info->ethertype_filters[idx].etqs = 0;
630 filter_info->ethertype_filters[idx].etqs = FALSE;
634 /* High threshold controlling when to start sending XOFF frames. */
635 #define TXGBE_FC_XOFF_HITH 128 /*KB*/
636 /* Low threshold controlling when to start sending XON frames. */
637 #define TXGBE_FC_XON_LOTH 64 /*KB*/
639 /* Timer value included in XOFF frames. */
640 #define TXGBE_FC_PAUSE_TIME 0x680
642 #define TXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
643 #define TXGBE_LINK_UP_CHECK_TIMEOUT 1000 /* ms */
644 #define TXGBE_VMDQ_NUM_UC_MAC 4096 /* Maximum nb. of UC MAC addr. */
647 * Default values for RX/TX configuration
649 #define TXGBE_DEFAULT_RX_FREE_THRESH 32
650 #define TXGBE_DEFAULT_RX_PTHRESH 8
651 #define TXGBE_DEFAULT_RX_HTHRESH 8
652 #define TXGBE_DEFAULT_RX_WTHRESH 0
654 #define TXGBE_DEFAULT_TX_FREE_THRESH 32
655 #define TXGBE_DEFAULT_TX_PTHRESH 32
656 #define TXGBE_DEFAULT_TX_HTHRESH 0
657 #define TXGBE_DEFAULT_TX_WTHRESH 0
659 /* Additional timesync values. */
660 #define NSEC_PER_SEC 1000000000L
661 #define TXGBE_INCVAL_10GB 0xCCCCCC
662 #define TXGBE_INCVAL_1GB 0x800000
663 #define TXGBE_INCVAL_100 0xA00000
664 #define TXGBE_INCVAL_10 0xC7F380
665 #define TXGBE_INCVAL_FPGA 0x800000
666 #define TXGBE_INCVAL_SHIFT_10GB 20
667 #define TXGBE_INCVAL_SHIFT_1GB 18
668 #define TXGBE_INCVAL_SHIFT_100 15
669 #define TXGBE_INCVAL_SHIFT_10 12
670 #define TXGBE_INCVAL_SHIFT_FPGA 17
672 #define TXGBE_CYCLECOUNTER_MASK 0xffffffffffffffffULL
674 /* store statistics names and its offset in stats structure */
675 struct rte_txgbe_xstats_name_off {
676 char name[RTE_ETH_XSTATS_NAME_SIZE];
680 const uint32_t *txgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev);
681 int txgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
682 struct rte_ether_addr *mc_addr_set,
683 uint32_t nb_mc_addr);
684 int txgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
685 struct rte_eth_rss_reta_entry64 *reta_conf,
687 int txgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
688 struct rte_eth_rss_reta_entry64 *reta_conf,
690 void txgbe_dev_setup_link_alarm_handler(void *param);
691 void txgbe_read_stats_registers(struct txgbe_hw *hw,
692 struct txgbe_hw_stats *hw_stats);
694 void txgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev);
695 void txgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev);
696 void txgbe_vlan_hw_strip_config(struct rte_eth_dev *dev);
697 void txgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
698 uint16_t queue, bool on);
699 void txgbe_config_vlan_strip_on_all_queues(struct rte_eth_dev *dev,
702 #endif /* _TXGBE_ETHDEV_H_ */