1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2015-2020 Beijing WangXun Technology Co., Ltd.
3 * Copyright(c) 2010-2017 Intel Corporation
6 #ifndef _TXGBE_ETHDEV_H_
7 #define _TXGBE_ETHDEV_H_
11 #include "base/txgbe.h"
12 #include "txgbe_ptypes.h"
13 #ifdef RTE_LIB_SECURITY
14 #include "txgbe_ipsec.h"
17 #include <rte_flow_driver.h>
19 #include <rte_ethdev.h>
20 #include <rte_ethdev_core.h>
22 #include <rte_hash_crc.h>
23 #include <rte_bus_pci.h>
24 #include <rte_tm_driver.h>
26 /* need update link, bit flag */
27 #define TXGBE_FLAG_NEED_LINK_UPDATE (uint32_t)(1 << 0)
28 #define TXGBE_FLAG_MAILBOX (uint32_t)(1 << 1)
29 #define TXGBE_FLAG_PHY_INTERRUPT (uint32_t)(1 << 2)
30 #define TXGBE_FLAG_MACSEC (uint32_t)(1 << 3)
31 #define TXGBE_FLAG_NEED_LINK_CONFIG (uint32_t)(1 << 4)
32 #define TXGBE_FLAG_NEED_AN_CONFIG (uint32_t)(1 << 5)
35 * Defines that were not part of txgbe_type.h as they are not used by the
38 #define TXGBE_VFTA_SIZE 128
39 #define TXGBE_VLAN_TAG_SIZE 4
40 #define TXGBE_HKEY_MAX_INDEX 10
41 /*Default value of Max Rx Queue*/
42 #define TXGBE_MAX_RX_QUEUE_NUM 128
43 #define TXGBE_VMDQ_DCB_NB_QUEUES TXGBE_MAX_RX_QUEUE_NUM
46 #define NBBY 8 /* number of bits in a byte */
48 #define TXGBE_HWSTRIP_BITMAP_SIZE \
49 (TXGBE_MAX_RX_QUEUE_NUM / (sizeof(uint32_t) * NBBY))
51 #define TXGBE_QUEUE_ITR_INTERVAL_DEFAULT 500 /* 500us */
53 #define TXGBE_MAX_QUEUE_NUM_PER_VF 8
55 #define TXGBE_5TUPLE_MAX_PRI 7
56 #define TXGBE_5TUPLE_MIN_PRI 1
58 #define TXGBE_RSS_OFFLOAD_ALL ( \
60 ETH_RSS_NONFRAG_IPV4_TCP | \
61 ETH_RSS_NONFRAG_IPV4_UDP | \
63 ETH_RSS_NONFRAG_IPV6_TCP | \
64 ETH_RSS_NONFRAG_IPV6_UDP | \
66 ETH_RSS_IPV6_TCP_EX | \
69 #define TXGBE_MISC_VEC_ID RTE_INTR_VEC_ZERO_OFFSET
70 #define TXGBE_RX_VEC_START RTE_INTR_VEC_RXTX_OFFSET
72 #define TXGBE_MAX_FDIR_FILTER_NUM (1024 * 32)
73 #define TXGBE_MAX_L2_TN_FILTER_NUM 128
76 * Information about the fdir mode.
78 struct txgbe_hw_fdir_mask {
79 uint16_t vlan_tci_mask;
80 uint32_t src_ipv4_mask;
81 uint32_t dst_ipv4_mask;
82 uint16_t src_ipv6_mask;
83 uint16_t dst_ipv6_mask;
84 uint16_t src_port_mask;
85 uint16_t dst_port_mask;
86 uint16_t flex_bytes_mask;
87 uint8_t mac_addr_byte_mask;
88 uint32_t tunnel_id_mask;
89 uint8_t tunnel_type_mask;
92 struct txgbe_fdir_filter {
93 TAILQ_ENTRY(txgbe_fdir_filter) entries;
94 struct txgbe_atr_input input; /* key of fdir filter*/
95 uint32_t fdirflags; /* drop or forward */
96 uint32_t fdirhash; /* hash value for fdir */
97 uint8_t queue; /* assigned rx queue */
100 /* list of fdir filters */
101 TAILQ_HEAD(txgbe_fdir_filter_list, txgbe_fdir_filter);
103 struct txgbe_fdir_rule {
104 struct txgbe_hw_fdir_mask mask;
105 struct txgbe_atr_input input; /* key of fdir filter */
106 bool b_spec; /* If TRUE, input, fdirflags, queue have meaning. */
107 bool b_mask; /* If TRUE, mask has meaning. */
108 enum rte_fdir_mode mode; /* IP, MAC VLAN, Tunnel */
109 uint32_t fdirflags; /* drop or forward */
110 uint32_t soft_id; /* an unique value for this rule */
111 uint8_t queue; /* assigned rx queue */
112 uint8_t flex_bytes_offset;
115 struct txgbe_hw_fdir_info {
116 struct txgbe_hw_fdir_mask mask;
117 uint8_t flex_bytes_offset;
126 struct txgbe_fdir_filter_list fdir_list; /* filter list*/
127 /* store the pointers of the filters, index is the hash value. */
128 struct txgbe_fdir_filter **hash_map;
129 struct rte_hash *hash_handle; /* cuckoo hash handler */
130 bool mask_added; /* If already got mask from consistent filter */
133 struct txgbe_rte_flow_rss_conf {
134 struct rte_flow_action_rss conf; /**< RSS parameters. */
135 uint8_t key[TXGBE_HKEY_MAX_INDEX * sizeof(uint32_t)]; /* Hash key. */
136 uint16_t queue[TXGBE_MAX_RX_QUEUE_NUM]; /**< Queues indices to use. */
139 /* structure for interrupt relative data */
140 struct txgbe_interrupt {
143 uint32_t mask_misc_orig; /* save mask during delayed handler */
145 uint64_t mask_orig; /* save mask during delayed handler */
148 #define TXGBE_NB_STAT_MAPPING 32
149 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
150 #define NB_QMAP_FIELDS_PER_QSM_REG 4
151 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
152 struct txgbe_stat_mappings {
153 uint32_t tqsm[TXGBE_NB_STAT_MAPPING];
154 uint32_t rqsm[TXGBE_NB_STAT_MAPPING];
158 uint32_t vfta[TXGBE_VFTA_SIZE];
161 struct txgbe_hwstrip {
162 uint32_t bitmap[TXGBE_HWSTRIP_BITMAP_SIZE];
166 * VF data which used by PF host only
168 #define TXGBE_MAX_VF_MC_ENTRIES 30
170 struct txgbe_uta_info {
171 uint8_t uc_filter_type;
173 uint32_t uta_shadow[TXGBE_MAX_UTA];
176 #define TXGBE_MAX_MIRROR_RULES 4 /* Maximum nb. of mirror rules. */
178 struct txgbe_mirror_info {
179 struct rte_eth_mirror_conf mr_conf[TXGBE_MAX_MIRROR_RULES];
180 /* store PF mirror rules configuration */
183 struct txgbe_vf_info {
184 uint8_t vf_mac_addresses[RTE_ETHER_ADDR_LEN];
185 uint16_t vf_mc_hashes[TXGBE_MAX_VF_MC_ENTRIES];
186 uint16_t num_vf_mc_hashes;
188 uint16_t tx_rate[TXGBE_MAX_QUEUE_NUM_PER_VF];
191 uint16_t switch_domain_id;
196 TAILQ_HEAD(txgbe_5tuple_filter_list, txgbe_5tuple_filter);
198 struct txgbe_5tuple_filter_info {
203 enum txgbe_5tuple_protocol proto; /* l4 protocol. */
204 uint8_t priority; /* seven levels (001b-111b), 111b is highest,
205 * used when more than one filter matches.
207 uint8_t dst_ip_mask:1, /* if mask is 1b, do not compare dst ip. */
208 src_ip_mask:1, /* if mask is 1b, do not compare src ip. */
209 dst_port_mask:1, /* if mask is 1b, do not compare dst port. */
210 src_port_mask:1, /* if mask is 1b, do not compare src port. */
211 proto_mask:1; /* if mask is 1b, do not compare protocol. */
214 /* 5tuple filter structure */
215 struct txgbe_5tuple_filter {
216 TAILQ_ENTRY(txgbe_5tuple_filter) entries;
217 uint16_t index; /* the index of 5tuple filter */
218 struct txgbe_5tuple_filter_info filter_info;
219 uint16_t queue; /* rx queue assigned to */
222 #define TXGBE_5TUPLE_ARRAY_SIZE \
223 (RTE_ALIGN(TXGBE_MAX_FTQF_FILTERS, (sizeof(uint32_t) * NBBY)) / \
224 (sizeof(uint32_t) * NBBY))
226 struct txgbe_ethertype_filter {
231 * If this filter is added by configuration,
232 * it should not be removed.
238 * Structure to store filters' info.
240 struct txgbe_filter_info {
241 uint8_t ethertype_mask; /* Bit mask for every used ethertype filter */
242 /* store used ethertype filters*/
243 struct txgbe_ethertype_filter ethertype_filters[TXGBE_ETF_ID_MAX];
244 /* Bit mask for every used 5tuple filter */
245 uint32_t fivetuple_mask[TXGBE_5TUPLE_ARRAY_SIZE];
246 struct txgbe_5tuple_filter_list fivetuple_list;
247 /* store the SYN filter info */
249 /* store the rss filter info */
250 struct txgbe_rte_flow_rss_conf rss_info;
253 struct txgbe_l2_tn_key {
254 enum rte_eth_tunnel_type l2_tn_type;
258 struct txgbe_l2_tn_filter {
259 TAILQ_ENTRY(txgbe_l2_tn_filter) entries;
260 struct txgbe_l2_tn_key key;
264 TAILQ_HEAD(txgbe_l2_tn_filter_list, txgbe_l2_tn_filter);
266 struct txgbe_l2_tn_info {
267 struct txgbe_l2_tn_filter_list l2_tn_list;
268 struct txgbe_l2_tn_filter **hash_map;
269 struct rte_hash *hash_handle;
270 bool e_tag_en; /* e-tag enabled */
271 bool e_tag_fwd_en; /* e-tag based forwarding enabled */
272 uint16_t e_tag_ether_type; /* ether type for e-tag */
276 enum rte_filter_type filter_type;
280 /* The configuration of bandwidth */
281 struct txgbe_bw_conf {
282 uint8_t tc_num; /* Number of TCs. */
285 /* Struct to store Traffic Manager shaper profile. */
286 struct txgbe_tm_shaper_profile {
287 TAILQ_ENTRY(txgbe_tm_shaper_profile) node;
288 uint32_t shaper_profile_id;
289 uint32_t reference_count;
290 struct rte_tm_shaper_params profile;
293 TAILQ_HEAD(txgbe_shaper_profile_list, txgbe_tm_shaper_profile);
295 /* node type of Traffic Manager */
296 enum txgbe_tm_node_type {
297 TXGBE_TM_NODE_TYPE_PORT,
298 TXGBE_TM_NODE_TYPE_TC,
299 TXGBE_TM_NODE_TYPE_QUEUE,
300 TXGBE_TM_NODE_TYPE_MAX,
303 /* Struct to store Traffic Manager node configuration. */
304 struct txgbe_tm_node {
305 TAILQ_ENTRY(txgbe_tm_node) node;
309 uint32_t reference_count;
311 struct txgbe_tm_node *parent;
312 struct txgbe_tm_shaper_profile *shaper_profile;
313 struct rte_tm_node_params params;
316 TAILQ_HEAD(txgbe_tm_node_list, txgbe_tm_node);
318 /* The configuration of Traffic Manager */
319 struct txgbe_tm_conf {
320 struct txgbe_shaper_profile_list shaper_profile_list;
321 struct txgbe_tm_node *root; /* root node - port */
322 struct txgbe_tm_node_list tc_list; /* node list for all the TCs */
323 struct txgbe_tm_node_list queue_list; /* node list for all the queues */
325 * The number of added TC nodes.
326 * It should be no more than the TC number of this port.
330 * The number of added queue nodes.
331 * It should be no more than the queue number of this port.
333 uint32_t nb_queue_node;
335 * This flag is used to check if APP can change the TM node
337 * When it's true, means the configuration is applied to HW,
338 * APP should not change the configuration.
339 * As we don't support on-the-fly configuration, when starting
340 * the port, APP should call the hierarchy_commit API to set this
341 * flag to true. When stopping the port, this flag should be set
348 * Structure to store private data for each driver instance (for each port).
350 struct txgbe_adapter {
352 struct txgbe_hw_stats stats;
353 struct txgbe_hw_fdir_info fdir;
354 struct txgbe_interrupt intr;
355 struct txgbe_stat_mappings stat_mappings;
356 struct txgbe_vfta shadow_vfta;
357 struct txgbe_hwstrip hwstrip;
358 struct txgbe_dcb_config dcb_config;
359 struct txgbe_mirror_info mr_data;
360 struct txgbe_vf_info *vfdata;
361 struct txgbe_uta_info uta_info;
362 struct txgbe_filter_info filter;
363 struct txgbe_l2_tn_info l2_tn;
364 struct txgbe_bw_conf bw_conf;
365 #ifdef RTE_LIB_SECURITY
366 struct txgbe_ipsec ipsec;
368 bool rx_bulk_alloc_allowed;
369 struct rte_timecounter systime_tc;
370 struct rte_timecounter rx_tstamp_tc;
371 struct rte_timecounter tx_tstamp_tc;
372 struct txgbe_tm_conf tm_conf;
374 /* For RSS reta table update */
375 uint8_t rss_reta_updated;
378 #define TXGBE_DEV_ADAPTER(dev) \
379 ((struct txgbe_adapter *)(dev)->data->dev_private)
381 #define TXGBE_DEV_HW(dev) \
382 (&((struct txgbe_adapter *)(dev)->data->dev_private)->hw)
384 #define TXGBE_DEV_STATS(dev) \
385 (&((struct txgbe_adapter *)(dev)->data->dev_private)->stats)
387 #define TXGBE_DEV_INTR(dev) \
388 (&((struct txgbe_adapter *)(dev)->data->dev_private)->intr)
390 #define TXGBE_DEV_FDIR(dev) \
391 (&((struct txgbe_adapter *)(dev)->data->dev_private)->fdir)
393 #define TXGBE_DEV_STAT_MAPPINGS(dev) \
394 (&((struct txgbe_adapter *)(dev)->data->dev_private)->stat_mappings)
396 #define TXGBE_DEV_VFTA(dev) \
397 (&((struct txgbe_adapter *)(dev)->data->dev_private)->shadow_vfta)
399 #define TXGBE_DEV_HWSTRIP(dev) \
400 (&((struct txgbe_adapter *)(dev)->data->dev_private)->hwstrip)
402 #define TXGBE_DEV_DCB_CONFIG(dev) \
403 (&((struct txgbe_adapter *)(dev)->data->dev_private)->dcb_config)
405 #define TXGBE_DEV_VFDATA(dev) \
406 (&((struct txgbe_adapter *)(dev)->data->dev_private)->vfdata)
408 #define TXGBE_DEV_MR_INFO(dev) \
409 (&((struct txgbe_adapter *)(dev)->data->dev_private)->mr_data)
411 #define TXGBE_DEV_UTA_INFO(dev) \
412 (&((struct txgbe_adapter *)(dev)->data->dev_private)->uta_info)
414 #define TXGBE_DEV_FILTER(dev) \
415 (&((struct txgbe_adapter *)(dev)->data->dev_private)->filter)
417 #define TXGBE_DEV_L2_TN(dev) \
418 (&((struct txgbe_adapter *)(dev)->data->dev_private)->l2_tn)
420 #define TXGBE_DEV_BW_CONF(dev) \
421 (&((struct txgbe_adapter *)(dev)->data->dev_private)->bw_conf)
423 #define TXGBE_DEV_TM_CONF(dev) \
424 (&((struct txgbe_adapter *)(dev)->data->dev_private)->tm_conf)
426 #define TXGBE_DEV_IPSEC(dev) \
427 (&((struct txgbe_adapter *)(dev)->data->dev_private)->ipsec)
430 * RX/TX function prototypes
432 void txgbe_dev_clear_queues(struct rte_eth_dev *dev);
434 void txgbe_dev_free_queues(struct rte_eth_dev *dev);
436 void txgbe_dev_rx_queue_release(void *rxq);
438 void txgbe_dev_tx_queue_release(void *txq);
440 int txgbe_dev_rx_queue_setup(struct rte_eth_dev *dev, uint16_t rx_queue_id,
441 uint16_t nb_rx_desc, unsigned int socket_id,
442 const struct rte_eth_rxconf *rx_conf,
443 struct rte_mempool *mb_pool);
445 int txgbe_dev_tx_queue_setup(struct rte_eth_dev *dev, uint16_t tx_queue_id,
446 uint16_t nb_tx_desc, unsigned int socket_id,
447 const struct rte_eth_txconf *tx_conf);
449 uint32_t txgbe_dev_rx_queue_count(struct rte_eth_dev *dev,
450 uint16_t rx_queue_id);
452 int txgbe_dev_rx_descriptor_status(void *rx_queue, uint16_t offset);
453 int txgbe_dev_tx_descriptor_status(void *tx_queue, uint16_t offset);
455 int txgbe_dev_rx_init(struct rte_eth_dev *dev);
457 void txgbe_dev_tx_init(struct rte_eth_dev *dev);
459 int txgbe_dev_rxtx_start(struct rte_eth_dev *dev);
461 void txgbe_dev_save_rx_queue(struct txgbe_hw *hw, uint16_t rx_queue_id);
462 void txgbe_dev_store_rx_queue(struct txgbe_hw *hw, uint16_t rx_queue_id);
463 void txgbe_dev_save_tx_queue(struct txgbe_hw *hw, uint16_t tx_queue_id);
464 void txgbe_dev_store_tx_queue(struct txgbe_hw *hw, uint16_t tx_queue_id);
466 int txgbe_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id);
468 int txgbe_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id);
470 int txgbe_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id);
472 int txgbe_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id);
474 void txgbe_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
475 struct rte_eth_rxq_info *qinfo);
477 void txgbe_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
478 struct rte_eth_txq_info *qinfo);
480 int txgbevf_dev_rx_init(struct rte_eth_dev *dev);
482 void txgbevf_dev_tx_init(struct rte_eth_dev *dev);
484 void txgbevf_dev_rxtx_start(struct rte_eth_dev *dev);
486 uint16_t txgbe_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
489 uint16_t txgbe_recv_pkts_bulk_alloc(void *rx_queue, struct rte_mbuf **rx_pkts,
492 uint16_t txgbe_recv_pkts_lro_single_alloc(void *rx_queue,
493 struct rte_mbuf **rx_pkts, uint16_t nb_pkts);
494 uint16_t txgbe_recv_pkts_lro_bulk_alloc(void *rx_queue,
495 struct rte_mbuf **rx_pkts, uint16_t nb_pkts);
497 uint16_t txgbe_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
500 uint16_t txgbe_xmit_pkts_simple(void *tx_queue, struct rte_mbuf **tx_pkts,
503 uint16_t txgbe_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
506 int txgbe_dev_rss_hash_update(struct rte_eth_dev *dev,
507 struct rte_eth_rss_conf *rss_conf);
509 int txgbe_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
510 struct rte_eth_rss_conf *rss_conf);
512 bool txgbe_rss_update_sp(enum txgbe_mac_type mac_type);
514 int txgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
515 struct rte_eth_ntuple_filter *filter,
517 int txgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
518 struct rte_eth_ethertype_filter *filter,
520 int txgbe_syn_filter_set(struct rte_eth_dev *dev,
521 struct rte_eth_syn_filter *filter,
525 * l2 tunnel configuration.
527 struct txgbe_l2_tunnel_conf {
528 enum rte_eth_tunnel_type l2_tunnel_type;
529 uint16_t ether_type; /* ether type in l2 header */
530 uint32_t tunnel_id; /* port tag id for e-tag */
531 uint16_t vf_id; /* VF id for tag insertion */
532 uint32_t pool; /* destination pool for tag based forwarding */
536 txgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev,
537 struct txgbe_l2_tunnel_conf *l2_tunnel,
540 txgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev,
541 struct txgbe_l2_tunnel_conf *l2_tunnel);
542 void txgbe_filterlist_init(void);
543 void txgbe_filterlist_flush(void);
545 void txgbe_set_ivar_map(struct txgbe_hw *hw, int8_t direction,
546 uint8_t queue, uint8_t msix_vector);
549 * Flow director function prototypes
551 int txgbe_fdir_configure(struct rte_eth_dev *dev);
552 int txgbe_fdir_set_input_mask(struct rte_eth_dev *dev);
553 int txgbe_fdir_set_flexbytes_offset(struct rte_eth_dev *dev,
555 int txgbe_fdir_filter_program(struct rte_eth_dev *dev,
556 struct txgbe_fdir_rule *rule,
557 bool del, bool update);
559 void txgbe_configure_pb(struct rte_eth_dev *dev);
560 void txgbe_configure_port(struct rte_eth_dev *dev);
561 void txgbe_configure_dcb(struct rte_eth_dev *dev);
564 txgbe_dev_link_update_share(struct rte_eth_dev *dev,
565 int wait_to_complete);
566 int txgbe_pf_host_init(struct rte_eth_dev *eth_dev);
568 void txgbe_pf_host_uninit(struct rte_eth_dev *eth_dev);
570 void txgbe_pf_mbx_process(struct rte_eth_dev *eth_dev);
572 int txgbe_pf_host_configure(struct rte_eth_dev *eth_dev);
574 uint32_t txgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val);
576 void txgbe_fdir_filter_restore(struct rte_eth_dev *dev);
577 int txgbe_clear_all_fdir_filter(struct rte_eth_dev *dev);
579 extern const struct rte_flow_ops txgbe_flow_ops;
581 void txgbe_clear_all_ethertype_filter(struct rte_eth_dev *dev);
582 void txgbe_clear_all_ntuple_filter(struct rte_eth_dev *dev);
583 void txgbe_clear_syn_filter(struct rte_eth_dev *dev);
584 int txgbe_clear_all_l2_tn_filter(struct rte_eth_dev *dev);
586 int txgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
587 uint16_t tx_rate, uint64_t q_msk);
588 int txgbe_tm_ops_get(struct rte_eth_dev *dev, void *ops);
589 void txgbe_tm_conf_init(struct rte_eth_dev *dev);
590 void txgbe_tm_conf_uninit(struct rte_eth_dev *dev);
591 int txgbe_set_queue_rate_limit(struct rte_eth_dev *dev, uint16_t queue_idx,
593 int txgbe_rss_conf_init(struct txgbe_rte_flow_rss_conf *out,
594 const struct rte_flow_action_rss *in);
595 int txgbe_action_rss_same(const struct rte_flow_action_rss *comp,
596 const struct rte_flow_action_rss *with);
597 int txgbe_config_rss_filter(struct rte_eth_dev *dev,
598 struct txgbe_rte_flow_rss_conf *conf, bool add);
601 txgbe_ethertype_filter_lookup(struct txgbe_filter_info *filter_info,
606 for (i = 0; i < TXGBE_ETF_ID_MAX; i++) {
607 if (filter_info->ethertype_filters[i].ethertype == ethertype &&
608 (filter_info->ethertype_mask & (1 << i)))
615 txgbe_ethertype_filter_insert(struct txgbe_filter_info *filter_info,
616 struct txgbe_ethertype_filter *ethertype_filter)
620 for (i = 0; i < TXGBE_ETF_ID_MAX; i++) {
621 if (filter_info->ethertype_mask & (1 << i))
624 filter_info->ethertype_mask |= 1 << i;
625 filter_info->ethertype_filters[i].ethertype =
626 ethertype_filter->ethertype;
627 filter_info->ethertype_filters[i].etqf =
628 ethertype_filter->etqf;
629 filter_info->ethertype_filters[i].etqs =
630 ethertype_filter->etqs;
631 filter_info->ethertype_filters[i].conf =
632 ethertype_filter->conf;
635 return (i < TXGBE_ETF_ID_MAX ? i : -1);
639 txgbe_ethertype_filter_remove(struct txgbe_filter_info *filter_info,
642 if (idx >= TXGBE_ETF_ID_MAX)
644 filter_info->ethertype_mask &= ~(1 << idx);
645 filter_info->ethertype_filters[idx].ethertype = 0;
646 filter_info->ethertype_filters[idx].etqf = 0;
647 filter_info->ethertype_filters[idx].etqs = 0;
648 filter_info->ethertype_filters[idx].etqs = FALSE;
652 #ifdef RTE_LIB_SECURITY
653 int txgbe_ipsec_ctx_create(struct rte_eth_dev *dev);
656 /* High threshold controlling when to start sending XOFF frames. */
657 #define TXGBE_FC_XOFF_HITH 128 /*KB*/
658 /* Low threshold controlling when to start sending XON frames. */
659 #define TXGBE_FC_XON_LOTH 64 /*KB*/
661 /* Timer value included in XOFF frames. */
662 #define TXGBE_FC_PAUSE_TIME 0x680
664 #define TXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
665 #define TXGBE_LINK_UP_CHECK_TIMEOUT 1000 /* ms */
666 #define TXGBE_VMDQ_NUM_UC_MAC 4096 /* Maximum nb. of UC MAC addr. */
669 * Default values for RX/TX configuration
671 #define TXGBE_DEFAULT_RX_FREE_THRESH 32
672 #define TXGBE_DEFAULT_RX_PTHRESH 8
673 #define TXGBE_DEFAULT_RX_HTHRESH 8
674 #define TXGBE_DEFAULT_RX_WTHRESH 0
676 #define TXGBE_DEFAULT_TX_FREE_THRESH 32
677 #define TXGBE_DEFAULT_TX_PTHRESH 32
678 #define TXGBE_DEFAULT_TX_HTHRESH 0
679 #define TXGBE_DEFAULT_TX_WTHRESH 0
681 /* Additional timesync values. */
682 #define NSEC_PER_SEC 1000000000L
683 #define TXGBE_INCVAL_10GB 0xCCCCCC
684 #define TXGBE_INCVAL_1GB 0x800000
685 #define TXGBE_INCVAL_100 0xA00000
686 #define TXGBE_INCVAL_10 0xC7F380
687 #define TXGBE_INCVAL_FPGA 0x800000
688 #define TXGBE_INCVAL_SHIFT_10GB 20
689 #define TXGBE_INCVAL_SHIFT_1GB 18
690 #define TXGBE_INCVAL_SHIFT_100 15
691 #define TXGBE_INCVAL_SHIFT_10 12
692 #define TXGBE_INCVAL_SHIFT_FPGA 17
694 #define TXGBE_CYCLECOUNTER_MASK 0xffffffffffffffffULL
696 /* store statistics names and its offset in stats structure */
697 struct rte_txgbe_xstats_name_off {
698 char name[RTE_ETH_XSTATS_NAME_SIZE];
702 const uint32_t *txgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev);
703 int txgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
704 struct rte_ether_addr *mc_addr_set,
705 uint32_t nb_mc_addr);
706 int txgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
707 struct rte_eth_rss_reta_entry64 *reta_conf,
709 int txgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
710 struct rte_eth_rss_reta_entry64 *reta_conf,
712 void txgbe_dev_setup_link_alarm_handler(void *param);
713 void txgbe_read_stats_registers(struct txgbe_hw *hw,
714 struct txgbe_hw_stats *hw_stats);
716 void txgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev);
717 void txgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev);
718 void txgbe_vlan_hw_strip_config(struct rte_eth_dev *dev);
719 void txgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
720 uint16_t queue, bool on);
721 void txgbe_config_vlan_strip_on_all_queues(struct rte_eth_dev *dev,
724 #endif /* _TXGBE_ETHDEV_H_ */