1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2015-2020
5 #ifndef _TXGBE_ETHDEV_H_
6 #define _TXGBE_ETHDEV_H_
10 #include "base/txgbe.h"
11 #include "txgbe_ptypes.h"
14 #include <rte_ethdev.h>
15 #include <rte_ethdev_core.h>
17 #include <rte_hash_crc.h>
19 /* need update link, bit flag */
20 #define TXGBE_FLAG_NEED_LINK_UPDATE (uint32_t)(1 << 0)
21 #define TXGBE_FLAG_MAILBOX (uint32_t)(1 << 1)
22 #define TXGBE_FLAG_PHY_INTERRUPT (uint32_t)(1 << 2)
23 #define TXGBE_FLAG_MACSEC (uint32_t)(1 << 3)
24 #define TXGBE_FLAG_NEED_LINK_CONFIG (uint32_t)(1 << 4)
27 * Defines that were not part of txgbe_type.h as they are not used by the
30 #define TXGBE_VFTA_SIZE 128
31 #define TXGBE_VLAN_TAG_SIZE 4
32 #define TXGBE_HKEY_MAX_INDEX 10
33 /*Default value of Max Rx Queue*/
34 #define TXGBE_MAX_RX_QUEUE_NUM 128
35 #define TXGBE_VMDQ_DCB_NB_QUEUES TXGBE_MAX_RX_QUEUE_NUM
38 #define NBBY 8 /* number of bits in a byte */
40 #define TXGBE_HWSTRIP_BITMAP_SIZE \
41 (TXGBE_MAX_RX_QUEUE_NUM / (sizeof(uint32_t) * NBBY))
43 #define TXGBE_QUEUE_ITR_INTERVAL_DEFAULT 500 /* 500us */
45 #define TXGBE_MAX_QUEUE_NUM_PER_VF 8
47 #define TXGBE_5TUPLE_MAX_PRI 7
48 #define TXGBE_5TUPLE_MIN_PRI 1
50 #define TXGBE_RSS_OFFLOAD_ALL ( \
52 ETH_RSS_NONFRAG_IPV4_TCP | \
53 ETH_RSS_NONFRAG_IPV4_UDP | \
55 ETH_RSS_NONFRAG_IPV6_TCP | \
56 ETH_RSS_NONFRAG_IPV6_UDP | \
58 ETH_RSS_IPV6_TCP_EX | \
61 #define TXGBE_MISC_VEC_ID RTE_INTR_VEC_ZERO_OFFSET
62 #define TXGBE_RX_VEC_START RTE_INTR_VEC_RXTX_OFFSET
64 #define TXGBE_MAX_L2_TN_FILTER_NUM 128
66 /* structure for interrupt relative data */
67 struct txgbe_interrupt {
70 /* to save original mask during delayed handler */
71 uint32_t mask_misc_orig;
75 #define TXGBE_NB_STAT_MAPPING 32
76 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
77 #define NB_QMAP_FIELDS_PER_QSM_REG 4
78 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
79 struct txgbe_stat_mappings {
80 uint32_t tqsm[TXGBE_NB_STAT_MAPPING];
81 uint32_t rqsm[TXGBE_NB_STAT_MAPPING];
85 uint32_t vfta[TXGBE_VFTA_SIZE];
88 struct txgbe_hwstrip {
89 uint32_t bitmap[TXGBE_HWSTRIP_BITMAP_SIZE];
93 * VF data which used by PF host only
95 #define TXGBE_MAX_VF_MC_ENTRIES 30
97 struct txgbe_uta_info {
98 uint8_t uc_filter_type;
100 uint32_t uta_shadow[TXGBE_MAX_UTA];
103 #define TXGBE_MAX_MIRROR_RULES 4 /* Maximum nb. of mirror rules. */
105 struct txgbe_mirror_info {
106 struct rte_eth_mirror_conf mr_conf[TXGBE_MAX_MIRROR_RULES];
107 /* store PF mirror rules configuration */
110 struct txgbe_vf_info {
111 uint8_t vf_mac_addresses[RTE_ETHER_ADDR_LEN];
112 uint16_t vf_mc_hashes[TXGBE_MAX_VF_MC_ENTRIES];
113 uint16_t num_vf_mc_hashes;
115 uint16_t tx_rate[TXGBE_MAX_QUEUE_NUM_PER_VF];
118 uint16_t switch_domain_id;
123 TAILQ_HEAD(txgbe_5tuple_filter_list, txgbe_5tuple_filter);
125 struct txgbe_5tuple_filter_info {
130 enum txgbe_5tuple_protocol proto; /* l4 protocol. */
131 uint8_t priority; /* seven levels (001b-111b), 111b is highest,
132 * used when more than one filter matches.
134 uint8_t dst_ip_mask:1, /* if mask is 1b, do not compare dst ip. */
135 src_ip_mask:1, /* if mask is 1b, do not compare src ip. */
136 dst_port_mask:1, /* if mask is 1b, do not compare dst port. */
137 src_port_mask:1, /* if mask is 1b, do not compare src port. */
138 proto_mask:1; /* if mask is 1b, do not compare protocol. */
141 /* 5tuple filter structure */
142 struct txgbe_5tuple_filter {
143 TAILQ_ENTRY(txgbe_5tuple_filter) entries;
144 uint16_t index; /* the index of 5tuple filter */
145 struct txgbe_5tuple_filter_info filter_info;
146 uint16_t queue; /* rx queue assigned to */
149 #define TXGBE_5TUPLE_ARRAY_SIZE \
150 (RTE_ALIGN(TXGBE_MAX_FTQF_FILTERS, (sizeof(uint32_t) * NBBY)) / \
151 (sizeof(uint32_t) * NBBY))
153 struct txgbe_ethertype_filter {
158 * If this filter is added by configuration,
159 * it should not be removed.
165 * Structure to store filters' info.
167 struct txgbe_filter_info {
168 uint8_t ethertype_mask; /* Bit mask for every used ethertype filter */
169 /* store used ethertype filters*/
170 struct txgbe_ethertype_filter ethertype_filters[TXGBE_ETF_ID_MAX];
171 /* Bit mask for every used 5tuple filter */
172 uint32_t fivetuple_mask[TXGBE_5TUPLE_ARRAY_SIZE];
173 struct txgbe_5tuple_filter_list fivetuple_list;
174 /* store the SYN filter info */
178 struct txgbe_l2_tn_key {
179 enum rte_eth_tunnel_type l2_tn_type;
183 struct txgbe_l2_tn_filter {
184 TAILQ_ENTRY(txgbe_l2_tn_filter) entries;
185 struct txgbe_l2_tn_key key;
189 TAILQ_HEAD(txgbe_l2_tn_filter_list, txgbe_l2_tn_filter);
191 struct txgbe_l2_tn_info {
192 struct txgbe_l2_tn_filter_list l2_tn_list;
193 struct txgbe_l2_tn_filter **hash_map;
194 struct rte_hash *hash_handle;
195 bool e_tag_en; /* e-tag enabled */
196 bool e_tag_fwd_en; /* e-tag based forwarding enabled */
197 uint16_t e_tag_ether_type; /* ether type for e-tag */
200 /* The configuration of bandwidth */
201 struct txgbe_bw_conf {
202 uint8_t tc_num; /* Number of TCs. */
206 * Structure to store private data for each driver instance (for each port).
208 struct txgbe_adapter {
210 struct txgbe_hw_stats stats;
211 struct txgbe_interrupt intr;
212 struct txgbe_stat_mappings stat_mappings;
213 struct txgbe_vfta shadow_vfta;
214 struct txgbe_hwstrip hwstrip;
215 struct txgbe_dcb_config dcb_config;
216 struct txgbe_mirror_info mr_data;
217 struct txgbe_vf_info *vfdata;
218 struct txgbe_uta_info uta_info;
219 struct txgbe_filter_info filter;
220 struct txgbe_l2_tn_info l2_tn;
221 struct txgbe_bw_conf bw_conf;
222 bool rx_bulk_alloc_allowed;
223 struct rte_timecounter systime_tc;
224 struct rte_timecounter rx_tstamp_tc;
225 struct rte_timecounter tx_tstamp_tc;
227 /* For RSS reta table update */
228 uint8_t rss_reta_updated;
231 #define TXGBE_DEV_ADAPTER(dev) \
232 ((struct txgbe_adapter *)(dev)->data->dev_private)
234 #define TXGBE_DEV_HW(dev) \
235 (&((struct txgbe_adapter *)(dev)->data->dev_private)->hw)
237 #define TXGBE_DEV_STATS(dev) \
238 (&((struct txgbe_adapter *)(dev)->data->dev_private)->stats)
240 #define TXGBE_DEV_INTR(dev) \
241 (&((struct txgbe_adapter *)(dev)->data->dev_private)->intr)
243 #define TXGBE_DEV_STAT_MAPPINGS(dev) \
244 (&((struct txgbe_adapter *)(dev)->data->dev_private)->stat_mappings)
246 #define TXGBE_DEV_VFTA(dev) \
247 (&((struct txgbe_adapter *)(dev)->data->dev_private)->shadow_vfta)
249 #define TXGBE_DEV_HWSTRIP(dev) \
250 (&((struct txgbe_adapter *)(dev)->data->dev_private)->hwstrip)
252 #define TXGBE_DEV_DCB_CONFIG(dev) \
253 (&((struct txgbe_adapter *)(dev)->data->dev_private)->dcb_config)
255 #define TXGBE_DEV_VFDATA(dev) \
256 (&((struct txgbe_adapter *)(dev)->data->dev_private)->vfdata)
258 #define TXGBE_DEV_MR_INFO(dev) \
259 (&((struct txgbe_adapter *)(dev)->data->dev_private)->mr_data)
261 #define TXGBE_DEV_UTA_INFO(dev) \
262 (&((struct txgbe_adapter *)(dev)->data->dev_private)->uta_info)
264 #define TXGBE_DEV_FILTER(dev) \
265 (&((struct txgbe_adapter *)(dev)->data->dev_private)->filter)
267 #define TXGBE_DEV_L2_TN(dev) \
268 (&((struct txgbe_adapter *)(dev)->data->dev_private)->l2_tn)
270 #define TXGBE_DEV_BW_CONF(dev) \
271 (&((struct txgbe_adapter *)(dev)->data->dev_private)->bw_conf)
275 * RX/TX function prototypes
277 void txgbe_dev_clear_queues(struct rte_eth_dev *dev);
279 void txgbe_dev_free_queues(struct rte_eth_dev *dev);
281 void txgbe_dev_rx_queue_release(void *rxq);
283 void txgbe_dev_tx_queue_release(void *txq);
285 int txgbe_dev_rx_queue_setup(struct rte_eth_dev *dev, uint16_t rx_queue_id,
286 uint16_t nb_rx_desc, unsigned int socket_id,
287 const struct rte_eth_rxconf *rx_conf,
288 struct rte_mempool *mb_pool);
290 int txgbe_dev_tx_queue_setup(struct rte_eth_dev *dev, uint16_t tx_queue_id,
291 uint16_t nb_tx_desc, unsigned int socket_id,
292 const struct rte_eth_txconf *tx_conf);
294 uint32_t txgbe_dev_rx_queue_count(struct rte_eth_dev *dev,
295 uint16_t rx_queue_id);
297 int txgbe_dev_rx_descriptor_status(void *rx_queue, uint16_t offset);
298 int txgbe_dev_tx_descriptor_status(void *tx_queue, uint16_t offset);
300 int txgbe_dev_rx_init(struct rte_eth_dev *dev);
302 void txgbe_dev_tx_init(struct rte_eth_dev *dev);
304 int txgbe_dev_rxtx_start(struct rte_eth_dev *dev);
306 void txgbe_dev_save_rx_queue(struct txgbe_hw *hw, uint16_t rx_queue_id);
307 void txgbe_dev_store_rx_queue(struct txgbe_hw *hw, uint16_t rx_queue_id);
308 void txgbe_dev_save_tx_queue(struct txgbe_hw *hw, uint16_t tx_queue_id);
309 void txgbe_dev_store_tx_queue(struct txgbe_hw *hw, uint16_t tx_queue_id);
311 int txgbe_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id);
313 int txgbe_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id);
315 int txgbe_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id);
317 int txgbe_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id);
319 void txgbe_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
320 struct rte_eth_rxq_info *qinfo);
322 void txgbe_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
323 struct rte_eth_txq_info *qinfo);
325 uint16_t txgbe_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
328 uint16_t txgbe_recv_pkts_bulk_alloc(void *rx_queue, struct rte_mbuf **rx_pkts,
331 uint16_t txgbe_recv_pkts_lro_single_alloc(void *rx_queue,
332 struct rte_mbuf **rx_pkts, uint16_t nb_pkts);
333 uint16_t txgbe_recv_pkts_lro_bulk_alloc(void *rx_queue,
334 struct rte_mbuf **rx_pkts, uint16_t nb_pkts);
336 uint16_t txgbe_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
339 uint16_t txgbe_xmit_pkts_simple(void *tx_queue, struct rte_mbuf **tx_pkts,
342 uint16_t txgbe_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
345 int txgbe_dev_rss_hash_update(struct rte_eth_dev *dev,
346 struct rte_eth_rss_conf *rss_conf);
348 int txgbe_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
349 struct rte_eth_rss_conf *rss_conf);
351 bool txgbe_rss_update_sp(enum txgbe_mac_type mac_type);
353 int txgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
354 struct rte_eth_ntuple_filter *filter,
356 int txgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
357 struct rte_eth_ethertype_filter *filter,
359 int txgbe_syn_filter_set(struct rte_eth_dev *dev,
360 struct rte_eth_syn_filter *filter,
363 void txgbe_set_ivar_map(struct txgbe_hw *hw, int8_t direction,
364 uint8_t queue, uint8_t msix_vector);
366 void txgbe_configure_pb(struct rte_eth_dev *dev);
367 void txgbe_configure_port(struct rte_eth_dev *dev);
368 void txgbe_configure_dcb(struct rte_eth_dev *dev);
371 txgbe_dev_link_update_share(struct rte_eth_dev *dev,
372 int wait_to_complete);
373 int txgbe_pf_host_init(struct rte_eth_dev *eth_dev);
375 void txgbe_pf_host_uninit(struct rte_eth_dev *eth_dev);
377 void txgbe_pf_mbx_process(struct rte_eth_dev *eth_dev);
379 int txgbe_pf_host_configure(struct rte_eth_dev *eth_dev);
381 uint32_t txgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val);
383 extern const struct rte_flow_ops txgbe_flow_ops;
385 int txgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
386 uint16_t tx_rate, uint64_t q_msk);
387 int txgbe_set_queue_rate_limit(struct rte_eth_dev *dev, uint16_t queue_idx,
390 txgbe_ethertype_filter_lookup(struct txgbe_filter_info *filter_info,
395 for (i = 0; i < TXGBE_ETF_ID_MAX; i++) {
396 if (filter_info->ethertype_filters[i].ethertype == ethertype &&
397 (filter_info->ethertype_mask & (1 << i)))
404 txgbe_ethertype_filter_insert(struct txgbe_filter_info *filter_info,
405 struct txgbe_ethertype_filter *ethertype_filter)
409 for (i = 0; i < TXGBE_ETF_ID_MAX; i++) {
410 if (filter_info->ethertype_mask & (1 << i))
413 filter_info->ethertype_mask |= 1 << i;
414 filter_info->ethertype_filters[i].ethertype =
415 ethertype_filter->ethertype;
416 filter_info->ethertype_filters[i].etqf =
417 ethertype_filter->etqf;
418 filter_info->ethertype_filters[i].etqs =
419 ethertype_filter->etqs;
420 filter_info->ethertype_filters[i].conf =
421 ethertype_filter->conf;
424 return (i < TXGBE_ETF_ID_MAX ? i : -1);
428 txgbe_ethertype_filter_remove(struct txgbe_filter_info *filter_info,
431 if (idx >= TXGBE_ETF_ID_MAX)
433 filter_info->ethertype_mask &= ~(1 << idx);
434 filter_info->ethertype_filters[idx].ethertype = 0;
435 filter_info->ethertype_filters[idx].etqf = 0;
436 filter_info->ethertype_filters[idx].etqs = 0;
437 filter_info->ethertype_filters[idx].etqs = FALSE;
441 /* High threshold controlling when to start sending XOFF frames. */
442 #define TXGBE_FC_XOFF_HITH 128 /*KB*/
443 /* Low threshold controlling when to start sending XON frames. */
444 #define TXGBE_FC_XON_LOTH 64 /*KB*/
446 /* Timer value included in XOFF frames. */
447 #define TXGBE_FC_PAUSE_TIME 0x680
449 #define TXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
450 #define TXGBE_LINK_UP_CHECK_TIMEOUT 1000 /* ms */
451 #define TXGBE_VMDQ_NUM_UC_MAC 4096 /* Maximum nb. of UC MAC addr. */
454 * Default values for RX/TX configuration
456 #define TXGBE_DEFAULT_RX_FREE_THRESH 32
457 #define TXGBE_DEFAULT_RX_PTHRESH 8
458 #define TXGBE_DEFAULT_RX_HTHRESH 8
459 #define TXGBE_DEFAULT_RX_WTHRESH 0
461 #define TXGBE_DEFAULT_TX_FREE_THRESH 32
462 #define TXGBE_DEFAULT_TX_PTHRESH 32
463 #define TXGBE_DEFAULT_TX_HTHRESH 0
464 #define TXGBE_DEFAULT_TX_WTHRESH 0
466 /* Additional timesync values. */
467 #define NSEC_PER_SEC 1000000000L
468 #define TXGBE_INCVAL_10GB 0xCCCCCC
469 #define TXGBE_INCVAL_1GB 0x800000
470 #define TXGBE_INCVAL_100 0xA00000
471 #define TXGBE_INCVAL_10 0xC7F380
472 #define TXGBE_INCVAL_FPGA 0x800000
473 #define TXGBE_INCVAL_SHIFT_10GB 20
474 #define TXGBE_INCVAL_SHIFT_1GB 18
475 #define TXGBE_INCVAL_SHIFT_100 15
476 #define TXGBE_INCVAL_SHIFT_10 12
477 #define TXGBE_INCVAL_SHIFT_FPGA 17
479 #define TXGBE_CYCLECOUNTER_MASK 0xffffffffffffffffULL
481 /* store statistics names and its offset in stats structure */
482 struct rte_txgbe_xstats_name_off {
483 char name[RTE_ETH_XSTATS_NAME_SIZE];
487 const uint32_t *txgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev);
488 int txgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
489 struct rte_ether_addr *mc_addr_set,
490 uint32_t nb_mc_addr);
491 int txgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
492 struct rte_eth_rss_reta_entry64 *reta_conf,
494 int txgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
495 struct rte_eth_rss_reta_entry64 *reta_conf,
497 void txgbe_dev_setup_link_alarm_handler(void *param);
498 void txgbe_read_stats_registers(struct txgbe_hw *hw,
499 struct txgbe_hw_stats *hw_stats);
501 void txgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev);
502 void txgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev);
503 void txgbe_vlan_hw_strip_config(struct rte_eth_dev *dev);
504 void txgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
505 uint16_t queue, bool on);
506 void txgbe_config_vlan_strip_on_all_queues(struct rte_eth_dev *dev,
509 #endif /* _TXGBE_ETHDEV_H_ */