1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2015-2020
5 #ifndef _TXGBE_ETHDEV_H_
6 #define _TXGBE_ETHDEV_H_
10 #include "base/txgbe.h"
11 #include "txgbe_ptypes.h"
14 #include <rte_ethdev.h>
15 #include <rte_ethdev_core.h>
17 /* need update link, bit flag */
18 #define TXGBE_FLAG_NEED_LINK_UPDATE (uint32_t)(1 << 0)
19 #define TXGBE_FLAG_MAILBOX (uint32_t)(1 << 1)
20 #define TXGBE_FLAG_PHY_INTERRUPT (uint32_t)(1 << 2)
21 #define TXGBE_FLAG_MACSEC (uint32_t)(1 << 3)
22 #define TXGBE_FLAG_NEED_LINK_CONFIG (uint32_t)(1 << 4)
25 * Defines that were not part of txgbe_type.h as they are not used by the
28 #define TXGBE_VFTA_SIZE 128
29 #define TXGBE_VLAN_TAG_SIZE 4
30 #define TXGBE_HKEY_MAX_INDEX 10
31 /*Default value of Max Rx Queue*/
32 #define TXGBE_MAX_RX_QUEUE_NUM 128
33 #define TXGBE_VMDQ_DCB_NB_QUEUES TXGBE_MAX_RX_QUEUE_NUM
36 #define NBBY 8 /* number of bits in a byte */
38 #define TXGBE_HWSTRIP_BITMAP_SIZE \
39 (TXGBE_MAX_RX_QUEUE_NUM / (sizeof(uint32_t) * NBBY))
41 #define TXGBE_QUEUE_ITR_INTERVAL_DEFAULT 500 /* 500us */
43 #define TXGBE_MAX_QUEUE_NUM_PER_VF 8
45 #define TXGBE_5TUPLE_MAX_PRI 7
46 #define TXGBE_5TUPLE_MIN_PRI 1
48 #define TXGBE_RSS_OFFLOAD_ALL ( \
50 ETH_RSS_NONFRAG_IPV4_TCP | \
51 ETH_RSS_NONFRAG_IPV4_UDP | \
53 ETH_RSS_NONFRAG_IPV6_TCP | \
54 ETH_RSS_NONFRAG_IPV6_UDP | \
56 ETH_RSS_IPV6_TCP_EX | \
59 #define TXGBE_MISC_VEC_ID RTE_INTR_VEC_ZERO_OFFSET
60 #define TXGBE_RX_VEC_START RTE_INTR_VEC_RXTX_OFFSET
62 /* structure for interrupt relative data */
63 struct txgbe_interrupt {
66 /* to save original mask during delayed handler */
67 uint32_t mask_misc_orig;
71 #define TXGBE_NB_STAT_MAPPING 32
72 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
73 #define NB_QMAP_FIELDS_PER_QSM_REG 4
74 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
75 struct txgbe_stat_mappings {
76 uint32_t tqsm[TXGBE_NB_STAT_MAPPING];
77 uint32_t rqsm[TXGBE_NB_STAT_MAPPING];
81 uint32_t vfta[TXGBE_VFTA_SIZE];
84 struct txgbe_hwstrip {
85 uint32_t bitmap[TXGBE_HWSTRIP_BITMAP_SIZE];
89 * VF data which used by PF host only
91 #define TXGBE_MAX_VF_MC_ENTRIES 30
93 struct txgbe_uta_info {
94 uint8_t uc_filter_type;
96 uint32_t uta_shadow[TXGBE_MAX_UTA];
99 #define TXGBE_MAX_MIRROR_RULES 4 /* Maximum nb. of mirror rules. */
101 struct txgbe_mirror_info {
102 struct rte_eth_mirror_conf mr_conf[TXGBE_MAX_MIRROR_RULES];
103 /* store PF mirror rules configuration */
106 struct txgbe_vf_info {
107 uint8_t vf_mac_addresses[RTE_ETHER_ADDR_LEN];
108 uint16_t vf_mc_hashes[TXGBE_MAX_VF_MC_ENTRIES];
109 uint16_t num_vf_mc_hashes;
111 uint16_t tx_rate[TXGBE_MAX_QUEUE_NUM_PER_VF];
114 uint16_t switch_domain_id;
119 TAILQ_HEAD(txgbe_5tuple_filter_list, txgbe_5tuple_filter);
121 struct txgbe_5tuple_filter_info {
126 enum txgbe_5tuple_protocol proto; /* l4 protocol. */
127 uint8_t priority; /* seven levels (001b-111b), 111b is highest,
128 * used when more than one filter matches.
130 uint8_t dst_ip_mask:1, /* if mask is 1b, do not compare dst ip. */
131 src_ip_mask:1, /* if mask is 1b, do not compare src ip. */
132 dst_port_mask:1, /* if mask is 1b, do not compare dst port. */
133 src_port_mask:1, /* if mask is 1b, do not compare src port. */
134 proto_mask:1; /* if mask is 1b, do not compare protocol. */
137 /* 5tuple filter structure */
138 struct txgbe_5tuple_filter {
139 TAILQ_ENTRY(txgbe_5tuple_filter) entries;
140 uint16_t index; /* the index of 5tuple filter */
141 struct txgbe_5tuple_filter_info filter_info;
142 uint16_t queue; /* rx queue assigned to */
145 #define TXGBE_5TUPLE_ARRAY_SIZE \
146 (RTE_ALIGN(TXGBE_MAX_FTQF_FILTERS, (sizeof(uint32_t) * NBBY)) / \
147 (sizeof(uint32_t) * NBBY))
149 struct txgbe_ethertype_filter {
154 * If this filter is added by configuration,
155 * it should not be removed.
161 * Structure to store filters' info.
163 struct txgbe_filter_info {
164 uint8_t ethertype_mask; /* Bit mask for every used ethertype filter */
165 /* store used ethertype filters*/
166 struct txgbe_ethertype_filter ethertype_filters[TXGBE_ETF_ID_MAX];
167 /* Bit mask for every used 5tuple filter */
168 uint32_t fivetuple_mask[TXGBE_5TUPLE_ARRAY_SIZE];
169 struct txgbe_5tuple_filter_list fivetuple_list;
172 /* The configuration of bandwidth */
173 struct txgbe_bw_conf {
174 uint8_t tc_num; /* Number of TCs. */
178 * Structure to store private data for each driver instance (for each port).
180 struct txgbe_adapter {
182 struct txgbe_hw_stats stats;
183 struct txgbe_interrupt intr;
184 struct txgbe_stat_mappings stat_mappings;
185 struct txgbe_vfta shadow_vfta;
186 struct txgbe_hwstrip hwstrip;
187 struct txgbe_dcb_config dcb_config;
188 struct txgbe_mirror_info mr_data;
189 struct txgbe_vf_info *vfdata;
190 struct txgbe_uta_info uta_info;
191 struct txgbe_filter_info filter;
192 struct txgbe_bw_conf bw_conf;
193 bool rx_bulk_alloc_allowed;
194 struct rte_timecounter systime_tc;
195 struct rte_timecounter rx_tstamp_tc;
196 struct rte_timecounter tx_tstamp_tc;
198 /* For RSS reta table update */
199 uint8_t rss_reta_updated;
202 #define TXGBE_DEV_ADAPTER(dev) \
203 ((struct txgbe_adapter *)(dev)->data->dev_private)
205 #define TXGBE_DEV_HW(dev) \
206 (&((struct txgbe_adapter *)(dev)->data->dev_private)->hw)
208 #define TXGBE_DEV_STATS(dev) \
209 (&((struct txgbe_adapter *)(dev)->data->dev_private)->stats)
211 #define TXGBE_DEV_INTR(dev) \
212 (&((struct txgbe_adapter *)(dev)->data->dev_private)->intr)
214 #define TXGBE_DEV_STAT_MAPPINGS(dev) \
215 (&((struct txgbe_adapter *)(dev)->data->dev_private)->stat_mappings)
217 #define TXGBE_DEV_VFTA(dev) \
218 (&((struct txgbe_adapter *)(dev)->data->dev_private)->shadow_vfta)
220 #define TXGBE_DEV_HWSTRIP(dev) \
221 (&((struct txgbe_adapter *)(dev)->data->dev_private)->hwstrip)
223 #define TXGBE_DEV_DCB_CONFIG(dev) \
224 (&((struct txgbe_adapter *)(dev)->data->dev_private)->dcb_config)
226 #define TXGBE_DEV_VFDATA(dev) \
227 (&((struct txgbe_adapter *)(dev)->data->dev_private)->vfdata)
229 #define TXGBE_DEV_MR_INFO(dev) \
230 (&((struct txgbe_adapter *)(dev)->data->dev_private)->mr_data)
232 #define TXGBE_DEV_UTA_INFO(dev) \
233 (&((struct txgbe_adapter *)(dev)->data->dev_private)->uta_info)
235 #define TXGBE_DEV_FILTER(dev) \
236 (&((struct txgbe_adapter *)(dev)->data->dev_private)->filter)
237 #define TXGBE_DEV_BW_CONF(dev) \
238 (&((struct txgbe_adapter *)(dev)->data->dev_private)->bw_conf)
242 * RX/TX function prototypes
244 void txgbe_dev_clear_queues(struct rte_eth_dev *dev);
246 void txgbe_dev_free_queues(struct rte_eth_dev *dev);
248 void txgbe_dev_rx_queue_release(void *rxq);
250 void txgbe_dev_tx_queue_release(void *txq);
252 int txgbe_dev_rx_queue_setup(struct rte_eth_dev *dev, uint16_t rx_queue_id,
253 uint16_t nb_rx_desc, unsigned int socket_id,
254 const struct rte_eth_rxconf *rx_conf,
255 struct rte_mempool *mb_pool);
257 int txgbe_dev_tx_queue_setup(struct rte_eth_dev *dev, uint16_t tx_queue_id,
258 uint16_t nb_tx_desc, unsigned int socket_id,
259 const struct rte_eth_txconf *tx_conf);
261 uint32_t txgbe_dev_rx_queue_count(struct rte_eth_dev *dev,
262 uint16_t rx_queue_id);
264 int txgbe_dev_rx_descriptor_status(void *rx_queue, uint16_t offset);
265 int txgbe_dev_tx_descriptor_status(void *tx_queue, uint16_t offset);
267 int txgbe_dev_rx_init(struct rte_eth_dev *dev);
269 void txgbe_dev_tx_init(struct rte_eth_dev *dev);
271 int txgbe_dev_rxtx_start(struct rte_eth_dev *dev);
273 void txgbe_dev_save_rx_queue(struct txgbe_hw *hw, uint16_t rx_queue_id);
274 void txgbe_dev_store_rx_queue(struct txgbe_hw *hw, uint16_t rx_queue_id);
275 void txgbe_dev_save_tx_queue(struct txgbe_hw *hw, uint16_t tx_queue_id);
276 void txgbe_dev_store_tx_queue(struct txgbe_hw *hw, uint16_t tx_queue_id);
278 int txgbe_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id);
280 int txgbe_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id);
282 int txgbe_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id);
284 int txgbe_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id);
286 void txgbe_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
287 struct rte_eth_rxq_info *qinfo);
289 void txgbe_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
290 struct rte_eth_txq_info *qinfo);
292 uint16_t txgbe_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
295 uint16_t txgbe_recv_pkts_bulk_alloc(void *rx_queue, struct rte_mbuf **rx_pkts,
298 uint16_t txgbe_recv_pkts_lro_single_alloc(void *rx_queue,
299 struct rte_mbuf **rx_pkts, uint16_t nb_pkts);
300 uint16_t txgbe_recv_pkts_lro_bulk_alloc(void *rx_queue,
301 struct rte_mbuf **rx_pkts, uint16_t nb_pkts);
303 uint16_t txgbe_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
306 uint16_t txgbe_xmit_pkts_simple(void *tx_queue, struct rte_mbuf **tx_pkts,
309 uint16_t txgbe_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
312 int txgbe_dev_rss_hash_update(struct rte_eth_dev *dev,
313 struct rte_eth_rss_conf *rss_conf);
315 int txgbe_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
316 struct rte_eth_rss_conf *rss_conf);
318 bool txgbe_rss_update_sp(enum txgbe_mac_type mac_type);
320 int txgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
321 struct rte_eth_ntuple_filter *filter,
323 void txgbe_set_ivar_map(struct txgbe_hw *hw, int8_t direction,
324 uint8_t queue, uint8_t msix_vector);
326 void txgbe_configure_pb(struct rte_eth_dev *dev);
327 void txgbe_configure_port(struct rte_eth_dev *dev);
328 void txgbe_configure_dcb(struct rte_eth_dev *dev);
331 txgbe_dev_link_update_share(struct rte_eth_dev *dev,
332 int wait_to_complete);
333 int txgbe_pf_host_init(struct rte_eth_dev *eth_dev);
335 void txgbe_pf_host_uninit(struct rte_eth_dev *eth_dev);
337 void txgbe_pf_mbx_process(struct rte_eth_dev *eth_dev);
339 int txgbe_pf_host_configure(struct rte_eth_dev *eth_dev);
341 uint32_t txgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val);
343 extern const struct rte_flow_ops txgbe_flow_ops;
345 int txgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
346 uint16_t tx_rate, uint64_t q_msk);
347 int txgbe_set_queue_rate_limit(struct rte_eth_dev *dev, uint16_t queue_idx,
350 txgbe_ethertype_filter_lookup(struct txgbe_filter_info *filter_info,
355 for (i = 0; i < TXGBE_ETF_ID_MAX; i++) {
356 if (filter_info->ethertype_filters[i].ethertype == ethertype &&
357 (filter_info->ethertype_mask & (1 << i)))
364 txgbe_ethertype_filter_insert(struct txgbe_filter_info *filter_info,
365 struct txgbe_ethertype_filter *ethertype_filter)
369 for (i = 0; i < TXGBE_ETF_ID_MAX; i++) {
370 if (filter_info->ethertype_mask & (1 << i))
373 filter_info->ethertype_mask |= 1 << i;
374 filter_info->ethertype_filters[i].ethertype =
375 ethertype_filter->ethertype;
376 filter_info->ethertype_filters[i].etqf =
377 ethertype_filter->etqf;
378 filter_info->ethertype_filters[i].etqs =
379 ethertype_filter->etqs;
380 filter_info->ethertype_filters[i].conf =
381 ethertype_filter->conf;
384 return (i < TXGBE_ETF_ID_MAX ? i : -1);
387 /* High threshold controlling when to start sending XOFF frames. */
388 #define TXGBE_FC_XOFF_HITH 128 /*KB*/
389 /* Low threshold controlling when to start sending XON frames. */
390 #define TXGBE_FC_XON_LOTH 64 /*KB*/
392 /* Timer value included in XOFF frames. */
393 #define TXGBE_FC_PAUSE_TIME 0x680
395 #define TXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
396 #define TXGBE_LINK_UP_CHECK_TIMEOUT 1000 /* ms */
397 #define TXGBE_VMDQ_NUM_UC_MAC 4096 /* Maximum nb. of UC MAC addr. */
400 * Default values for RX/TX configuration
402 #define TXGBE_DEFAULT_RX_FREE_THRESH 32
403 #define TXGBE_DEFAULT_RX_PTHRESH 8
404 #define TXGBE_DEFAULT_RX_HTHRESH 8
405 #define TXGBE_DEFAULT_RX_WTHRESH 0
407 #define TXGBE_DEFAULT_TX_FREE_THRESH 32
408 #define TXGBE_DEFAULT_TX_PTHRESH 32
409 #define TXGBE_DEFAULT_TX_HTHRESH 0
410 #define TXGBE_DEFAULT_TX_WTHRESH 0
412 /* Additional timesync values. */
413 #define NSEC_PER_SEC 1000000000L
414 #define TXGBE_INCVAL_10GB 0xCCCCCC
415 #define TXGBE_INCVAL_1GB 0x800000
416 #define TXGBE_INCVAL_100 0xA00000
417 #define TXGBE_INCVAL_10 0xC7F380
418 #define TXGBE_INCVAL_FPGA 0x800000
419 #define TXGBE_INCVAL_SHIFT_10GB 20
420 #define TXGBE_INCVAL_SHIFT_1GB 18
421 #define TXGBE_INCVAL_SHIFT_100 15
422 #define TXGBE_INCVAL_SHIFT_10 12
423 #define TXGBE_INCVAL_SHIFT_FPGA 17
425 #define TXGBE_CYCLECOUNTER_MASK 0xffffffffffffffffULL
427 /* store statistics names and its offset in stats structure */
428 struct rte_txgbe_xstats_name_off {
429 char name[RTE_ETH_XSTATS_NAME_SIZE];
433 const uint32_t *txgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev);
434 int txgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
435 struct rte_ether_addr *mc_addr_set,
436 uint32_t nb_mc_addr);
437 int txgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
438 struct rte_eth_rss_reta_entry64 *reta_conf,
440 int txgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
441 struct rte_eth_rss_reta_entry64 *reta_conf,
443 void txgbe_dev_setup_link_alarm_handler(void *param);
444 void txgbe_read_stats_registers(struct txgbe_hw *hw,
445 struct txgbe_hw_stats *hw_stats);
447 void txgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev);
448 void txgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev);
449 void txgbe_vlan_hw_strip_config(struct rte_eth_dev *dev);
450 void txgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
451 uint16_t queue, bool on);
452 void txgbe_config_vlan_strip_on_all_queues(struct rte_eth_dev *dev,
455 #endif /* _TXGBE_ETHDEV_H_ */