1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2015-2020
5 #ifndef _TXGBE_ETHDEV_H_
6 #define _TXGBE_ETHDEV_H_
10 #include "base/txgbe.h"
11 #include "txgbe_ptypes.h"
13 #include <rte_flow_driver.h>
15 #include <rte_ethdev.h>
16 #include <rte_ethdev_core.h>
18 #include <rte_hash_crc.h>
20 /* need update link, bit flag */
21 #define TXGBE_FLAG_NEED_LINK_UPDATE (uint32_t)(1 << 0)
22 #define TXGBE_FLAG_MAILBOX (uint32_t)(1 << 1)
23 #define TXGBE_FLAG_PHY_INTERRUPT (uint32_t)(1 << 2)
24 #define TXGBE_FLAG_MACSEC (uint32_t)(1 << 3)
25 #define TXGBE_FLAG_NEED_LINK_CONFIG (uint32_t)(1 << 4)
28 * Defines that were not part of txgbe_type.h as they are not used by the
31 #define TXGBE_VFTA_SIZE 128
32 #define TXGBE_VLAN_TAG_SIZE 4
33 #define TXGBE_HKEY_MAX_INDEX 10
34 /*Default value of Max Rx Queue*/
35 #define TXGBE_MAX_RX_QUEUE_NUM 128
36 #define TXGBE_VMDQ_DCB_NB_QUEUES TXGBE_MAX_RX_QUEUE_NUM
39 #define NBBY 8 /* number of bits in a byte */
41 #define TXGBE_HWSTRIP_BITMAP_SIZE \
42 (TXGBE_MAX_RX_QUEUE_NUM / (sizeof(uint32_t) * NBBY))
44 #define TXGBE_QUEUE_ITR_INTERVAL_DEFAULT 500 /* 500us */
46 #define TXGBE_MAX_QUEUE_NUM_PER_VF 8
48 #define TXGBE_5TUPLE_MAX_PRI 7
49 #define TXGBE_5TUPLE_MIN_PRI 1
51 #define TXGBE_RSS_OFFLOAD_ALL ( \
53 ETH_RSS_NONFRAG_IPV4_TCP | \
54 ETH_RSS_NONFRAG_IPV4_UDP | \
56 ETH_RSS_NONFRAG_IPV6_TCP | \
57 ETH_RSS_NONFRAG_IPV6_UDP | \
59 ETH_RSS_IPV6_TCP_EX | \
62 #define TXGBE_MISC_VEC_ID RTE_INTR_VEC_ZERO_OFFSET
63 #define TXGBE_RX_VEC_START RTE_INTR_VEC_RXTX_OFFSET
65 #define TXGBE_MAX_FDIR_FILTER_NUM (1024 * 32)
66 #define TXGBE_MAX_L2_TN_FILTER_NUM 128
69 * Information about the fdir mode.
71 struct txgbe_hw_fdir_mask {
72 uint16_t vlan_tci_mask;
73 uint32_t src_ipv4_mask;
74 uint32_t dst_ipv4_mask;
75 uint16_t src_ipv6_mask;
76 uint16_t dst_ipv6_mask;
77 uint16_t src_port_mask;
78 uint16_t dst_port_mask;
79 uint16_t flex_bytes_mask;
80 uint8_t mac_addr_byte_mask;
81 uint32_t tunnel_id_mask;
82 uint8_t tunnel_type_mask;
85 struct txgbe_fdir_filter {
86 TAILQ_ENTRY(txgbe_fdir_filter) entries;
87 struct txgbe_atr_input input; /* key of fdir filter*/
88 uint32_t fdirflags; /* drop or forward */
89 uint32_t fdirhash; /* hash value for fdir */
90 uint8_t queue; /* assigned rx queue */
93 /* list of fdir filters */
94 TAILQ_HEAD(txgbe_fdir_filter_list, txgbe_fdir_filter);
96 struct txgbe_fdir_rule {
97 struct txgbe_hw_fdir_mask mask;
98 struct txgbe_atr_input input; /* key of fdir filter */
99 bool b_spec; /* If TRUE, input, fdirflags, queue have meaning. */
100 bool b_mask; /* If TRUE, mask has meaning. */
101 enum rte_fdir_mode mode; /* IP, MAC VLAN, Tunnel */
102 uint32_t fdirflags; /* drop or forward */
103 uint32_t soft_id; /* an unique value for this rule */
104 uint8_t queue; /* assigned rx queue */
105 uint8_t flex_bytes_offset;
108 struct txgbe_hw_fdir_info {
109 struct txgbe_hw_fdir_mask mask;
110 uint8_t flex_bytes_offset;
119 struct txgbe_fdir_filter_list fdir_list; /* filter list*/
120 /* store the pointers of the filters, index is the hash value. */
121 struct txgbe_fdir_filter **hash_map;
122 struct rte_hash *hash_handle; /* cuckoo hash handler */
123 bool mask_added; /* If already got mask from consistent filter */
126 /* structure for interrupt relative data */
127 struct txgbe_interrupt {
130 /* to save original mask during delayed handler */
131 uint32_t mask_misc_orig;
135 #define TXGBE_NB_STAT_MAPPING 32
136 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
137 #define NB_QMAP_FIELDS_PER_QSM_REG 4
138 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
139 struct txgbe_stat_mappings {
140 uint32_t tqsm[TXGBE_NB_STAT_MAPPING];
141 uint32_t rqsm[TXGBE_NB_STAT_MAPPING];
145 uint32_t vfta[TXGBE_VFTA_SIZE];
148 struct txgbe_hwstrip {
149 uint32_t bitmap[TXGBE_HWSTRIP_BITMAP_SIZE];
153 * VF data which used by PF host only
155 #define TXGBE_MAX_VF_MC_ENTRIES 30
157 struct txgbe_uta_info {
158 uint8_t uc_filter_type;
160 uint32_t uta_shadow[TXGBE_MAX_UTA];
163 #define TXGBE_MAX_MIRROR_RULES 4 /* Maximum nb. of mirror rules. */
165 struct txgbe_mirror_info {
166 struct rte_eth_mirror_conf mr_conf[TXGBE_MAX_MIRROR_RULES];
167 /* store PF mirror rules configuration */
170 struct txgbe_vf_info {
171 uint8_t vf_mac_addresses[RTE_ETHER_ADDR_LEN];
172 uint16_t vf_mc_hashes[TXGBE_MAX_VF_MC_ENTRIES];
173 uint16_t num_vf_mc_hashes;
175 uint16_t tx_rate[TXGBE_MAX_QUEUE_NUM_PER_VF];
178 uint16_t switch_domain_id;
183 TAILQ_HEAD(txgbe_5tuple_filter_list, txgbe_5tuple_filter);
185 struct txgbe_5tuple_filter_info {
190 enum txgbe_5tuple_protocol proto; /* l4 protocol. */
191 uint8_t priority; /* seven levels (001b-111b), 111b is highest,
192 * used when more than one filter matches.
194 uint8_t dst_ip_mask:1, /* if mask is 1b, do not compare dst ip. */
195 src_ip_mask:1, /* if mask is 1b, do not compare src ip. */
196 dst_port_mask:1, /* if mask is 1b, do not compare dst port. */
197 src_port_mask:1, /* if mask is 1b, do not compare src port. */
198 proto_mask:1; /* if mask is 1b, do not compare protocol. */
201 /* 5tuple filter structure */
202 struct txgbe_5tuple_filter {
203 TAILQ_ENTRY(txgbe_5tuple_filter) entries;
204 uint16_t index; /* the index of 5tuple filter */
205 struct txgbe_5tuple_filter_info filter_info;
206 uint16_t queue; /* rx queue assigned to */
209 #define TXGBE_5TUPLE_ARRAY_SIZE \
210 (RTE_ALIGN(TXGBE_MAX_FTQF_FILTERS, (sizeof(uint32_t) * NBBY)) / \
211 (sizeof(uint32_t) * NBBY))
213 struct txgbe_ethertype_filter {
218 * If this filter is added by configuration,
219 * it should not be removed.
225 * Structure to store filters' info.
227 struct txgbe_filter_info {
228 uint8_t ethertype_mask; /* Bit mask for every used ethertype filter */
229 /* store used ethertype filters*/
230 struct txgbe_ethertype_filter ethertype_filters[TXGBE_ETF_ID_MAX];
231 /* Bit mask for every used 5tuple filter */
232 uint32_t fivetuple_mask[TXGBE_5TUPLE_ARRAY_SIZE];
233 struct txgbe_5tuple_filter_list fivetuple_list;
234 /* store the SYN filter info */
238 struct txgbe_l2_tn_key {
239 enum rte_eth_tunnel_type l2_tn_type;
243 struct txgbe_l2_tn_filter {
244 TAILQ_ENTRY(txgbe_l2_tn_filter) entries;
245 struct txgbe_l2_tn_key key;
249 TAILQ_HEAD(txgbe_l2_tn_filter_list, txgbe_l2_tn_filter);
251 struct txgbe_l2_tn_info {
252 struct txgbe_l2_tn_filter_list l2_tn_list;
253 struct txgbe_l2_tn_filter **hash_map;
254 struct rte_hash *hash_handle;
255 bool e_tag_en; /* e-tag enabled */
256 bool e_tag_fwd_en; /* e-tag based forwarding enabled */
257 uint16_t e_tag_ether_type; /* ether type for e-tag */
260 /* The configuration of bandwidth */
261 struct txgbe_bw_conf {
262 uint8_t tc_num; /* Number of TCs. */
266 * Structure to store private data for each driver instance (for each port).
268 struct txgbe_adapter {
270 struct txgbe_hw_stats stats;
271 struct txgbe_hw_fdir_info fdir;
272 struct txgbe_interrupt intr;
273 struct txgbe_stat_mappings stat_mappings;
274 struct txgbe_vfta shadow_vfta;
275 struct txgbe_hwstrip hwstrip;
276 struct txgbe_dcb_config dcb_config;
277 struct txgbe_mirror_info mr_data;
278 struct txgbe_vf_info *vfdata;
279 struct txgbe_uta_info uta_info;
280 struct txgbe_filter_info filter;
281 struct txgbe_l2_tn_info l2_tn;
282 struct txgbe_bw_conf bw_conf;
283 bool rx_bulk_alloc_allowed;
284 struct rte_timecounter systime_tc;
285 struct rte_timecounter rx_tstamp_tc;
286 struct rte_timecounter tx_tstamp_tc;
288 /* For RSS reta table update */
289 uint8_t rss_reta_updated;
292 #define TXGBE_DEV_ADAPTER(dev) \
293 ((struct txgbe_adapter *)(dev)->data->dev_private)
295 #define TXGBE_DEV_HW(dev) \
296 (&((struct txgbe_adapter *)(dev)->data->dev_private)->hw)
298 #define TXGBE_DEV_STATS(dev) \
299 (&((struct txgbe_adapter *)(dev)->data->dev_private)->stats)
301 #define TXGBE_DEV_INTR(dev) \
302 (&((struct txgbe_adapter *)(dev)->data->dev_private)->intr)
304 #define TXGBE_DEV_FDIR(dev) \
305 (&((struct txgbe_adapter *)(dev)->data->dev_private)->fdir)
307 #define TXGBE_DEV_STAT_MAPPINGS(dev) \
308 (&((struct txgbe_adapter *)(dev)->data->dev_private)->stat_mappings)
310 #define TXGBE_DEV_VFTA(dev) \
311 (&((struct txgbe_adapter *)(dev)->data->dev_private)->shadow_vfta)
313 #define TXGBE_DEV_HWSTRIP(dev) \
314 (&((struct txgbe_adapter *)(dev)->data->dev_private)->hwstrip)
316 #define TXGBE_DEV_DCB_CONFIG(dev) \
317 (&((struct txgbe_adapter *)(dev)->data->dev_private)->dcb_config)
319 #define TXGBE_DEV_VFDATA(dev) \
320 (&((struct txgbe_adapter *)(dev)->data->dev_private)->vfdata)
322 #define TXGBE_DEV_MR_INFO(dev) \
323 (&((struct txgbe_adapter *)(dev)->data->dev_private)->mr_data)
325 #define TXGBE_DEV_UTA_INFO(dev) \
326 (&((struct txgbe_adapter *)(dev)->data->dev_private)->uta_info)
328 #define TXGBE_DEV_FILTER(dev) \
329 (&((struct txgbe_adapter *)(dev)->data->dev_private)->filter)
331 #define TXGBE_DEV_L2_TN(dev) \
332 (&((struct txgbe_adapter *)(dev)->data->dev_private)->l2_tn)
334 #define TXGBE_DEV_BW_CONF(dev) \
335 (&((struct txgbe_adapter *)(dev)->data->dev_private)->bw_conf)
339 * RX/TX function prototypes
341 void txgbe_dev_clear_queues(struct rte_eth_dev *dev);
343 void txgbe_dev_free_queues(struct rte_eth_dev *dev);
345 void txgbe_dev_rx_queue_release(void *rxq);
347 void txgbe_dev_tx_queue_release(void *txq);
349 int txgbe_dev_rx_queue_setup(struct rte_eth_dev *dev, uint16_t rx_queue_id,
350 uint16_t nb_rx_desc, unsigned int socket_id,
351 const struct rte_eth_rxconf *rx_conf,
352 struct rte_mempool *mb_pool);
354 int txgbe_dev_tx_queue_setup(struct rte_eth_dev *dev, uint16_t tx_queue_id,
355 uint16_t nb_tx_desc, unsigned int socket_id,
356 const struct rte_eth_txconf *tx_conf);
358 uint32_t txgbe_dev_rx_queue_count(struct rte_eth_dev *dev,
359 uint16_t rx_queue_id);
361 int txgbe_dev_rx_descriptor_status(void *rx_queue, uint16_t offset);
362 int txgbe_dev_tx_descriptor_status(void *tx_queue, uint16_t offset);
364 int txgbe_dev_rx_init(struct rte_eth_dev *dev);
366 void txgbe_dev_tx_init(struct rte_eth_dev *dev);
368 int txgbe_dev_rxtx_start(struct rte_eth_dev *dev);
370 void txgbe_dev_save_rx_queue(struct txgbe_hw *hw, uint16_t rx_queue_id);
371 void txgbe_dev_store_rx_queue(struct txgbe_hw *hw, uint16_t rx_queue_id);
372 void txgbe_dev_save_tx_queue(struct txgbe_hw *hw, uint16_t tx_queue_id);
373 void txgbe_dev_store_tx_queue(struct txgbe_hw *hw, uint16_t tx_queue_id);
375 int txgbe_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id);
377 int txgbe_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id);
379 int txgbe_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id);
381 int txgbe_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id);
383 void txgbe_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
384 struct rte_eth_rxq_info *qinfo);
386 void txgbe_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
387 struct rte_eth_txq_info *qinfo);
389 uint16_t txgbe_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
392 uint16_t txgbe_recv_pkts_bulk_alloc(void *rx_queue, struct rte_mbuf **rx_pkts,
395 uint16_t txgbe_recv_pkts_lro_single_alloc(void *rx_queue,
396 struct rte_mbuf **rx_pkts, uint16_t nb_pkts);
397 uint16_t txgbe_recv_pkts_lro_bulk_alloc(void *rx_queue,
398 struct rte_mbuf **rx_pkts, uint16_t nb_pkts);
400 uint16_t txgbe_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
403 uint16_t txgbe_xmit_pkts_simple(void *tx_queue, struct rte_mbuf **tx_pkts,
406 uint16_t txgbe_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
409 int txgbe_dev_rss_hash_update(struct rte_eth_dev *dev,
410 struct rte_eth_rss_conf *rss_conf);
412 int txgbe_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
413 struct rte_eth_rss_conf *rss_conf);
415 bool txgbe_rss_update_sp(enum txgbe_mac_type mac_type);
417 int txgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
418 struct rte_eth_ntuple_filter *filter,
420 int txgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
421 struct rte_eth_ethertype_filter *filter,
423 int txgbe_syn_filter_set(struct rte_eth_dev *dev,
424 struct rte_eth_syn_filter *filter,
428 * l2 tunnel configuration.
430 struct txgbe_l2_tunnel_conf {
431 enum rte_eth_tunnel_type l2_tunnel_type;
432 uint16_t ether_type; /* ether type in l2 header */
433 uint32_t tunnel_id; /* port tag id for e-tag */
434 uint16_t vf_id; /* VF id for tag insertion */
435 uint32_t pool; /* destination pool for tag based forwarding */
439 txgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev,
440 struct txgbe_l2_tunnel_conf *l2_tunnel,
443 txgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev,
444 struct txgbe_l2_tunnel_conf *l2_tunnel);
445 void txgbe_set_ivar_map(struct txgbe_hw *hw, int8_t direction,
446 uint8_t queue, uint8_t msix_vector);
449 * Flow director function prototypes
451 int txgbe_fdir_configure(struct rte_eth_dev *dev);
452 int txgbe_fdir_set_input_mask(struct rte_eth_dev *dev);
453 int txgbe_fdir_set_flexbytes_offset(struct rte_eth_dev *dev,
455 int txgbe_fdir_filter_program(struct rte_eth_dev *dev,
456 struct txgbe_fdir_rule *rule,
457 bool del, bool update);
459 void txgbe_configure_pb(struct rte_eth_dev *dev);
460 void txgbe_configure_port(struct rte_eth_dev *dev);
461 void txgbe_configure_dcb(struct rte_eth_dev *dev);
464 txgbe_dev_link_update_share(struct rte_eth_dev *dev,
465 int wait_to_complete);
466 int txgbe_pf_host_init(struct rte_eth_dev *eth_dev);
468 void txgbe_pf_host_uninit(struct rte_eth_dev *eth_dev);
470 void txgbe_pf_mbx_process(struct rte_eth_dev *eth_dev);
472 int txgbe_pf_host_configure(struct rte_eth_dev *eth_dev);
474 uint32_t txgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val);
476 void txgbe_fdir_filter_restore(struct rte_eth_dev *dev);
478 extern const struct rte_flow_ops txgbe_flow_ops;
480 int txgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
481 uint16_t tx_rate, uint64_t q_msk);
482 int txgbe_set_queue_rate_limit(struct rte_eth_dev *dev, uint16_t queue_idx,
485 txgbe_ethertype_filter_lookup(struct txgbe_filter_info *filter_info,
490 for (i = 0; i < TXGBE_ETF_ID_MAX; i++) {
491 if (filter_info->ethertype_filters[i].ethertype == ethertype &&
492 (filter_info->ethertype_mask & (1 << i)))
499 txgbe_ethertype_filter_insert(struct txgbe_filter_info *filter_info,
500 struct txgbe_ethertype_filter *ethertype_filter)
504 for (i = 0; i < TXGBE_ETF_ID_MAX; i++) {
505 if (filter_info->ethertype_mask & (1 << i))
508 filter_info->ethertype_mask |= 1 << i;
509 filter_info->ethertype_filters[i].ethertype =
510 ethertype_filter->ethertype;
511 filter_info->ethertype_filters[i].etqf =
512 ethertype_filter->etqf;
513 filter_info->ethertype_filters[i].etqs =
514 ethertype_filter->etqs;
515 filter_info->ethertype_filters[i].conf =
516 ethertype_filter->conf;
519 return (i < TXGBE_ETF_ID_MAX ? i : -1);
523 txgbe_ethertype_filter_remove(struct txgbe_filter_info *filter_info,
526 if (idx >= TXGBE_ETF_ID_MAX)
528 filter_info->ethertype_mask &= ~(1 << idx);
529 filter_info->ethertype_filters[idx].ethertype = 0;
530 filter_info->ethertype_filters[idx].etqf = 0;
531 filter_info->ethertype_filters[idx].etqs = 0;
532 filter_info->ethertype_filters[idx].etqs = FALSE;
536 /* High threshold controlling when to start sending XOFF frames. */
537 #define TXGBE_FC_XOFF_HITH 128 /*KB*/
538 /* Low threshold controlling when to start sending XON frames. */
539 #define TXGBE_FC_XON_LOTH 64 /*KB*/
541 /* Timer value included in XOFF frames. */
542 #define TXGBE_FC_PAUSE_TIME 0x680
544 #define TXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
545 #define TXGBE_LINK_UP_CHECK_TIMEOUT 1000 /* ms */
546 #define TXGBE_VMDQ_NUM_UC_MAC 4096 /* Maximum nb. of UC MAC addr. */
549 * Default values for RX/TX configuration
551 #define TXGBE_DEFAULT_RX_FREE_THRESH 32
552 #define TXGBE_DEFAULT_RX_PTHRESH 8
553 #define TXGBE_DEFAULT_RX_HTHRESH 8
554 #define TXGBE_DEFAULT_RX_WTHRESH 0
556 #define TXGBE_DEFAULT_TX_FREE_THRESH 32
557 #define TXGBE_DEFAULT_TX_PTHRESH 32
558 #define TXGBE_DEFAULT_TX_HTHRESH 0
559 #define TXGBE_DEFAULT_TX_WTHRESH 0
561 /* Additional timesync values. */
562 #define NSEC_PER_SEC 1000000000L
563 #define TXGBE_INCVAL_10GB 0xCCCCCC
564 #define TXGBE_INCVAL_1GB 0x800000
565 #define TXGBE_INCVAL_100 0xA00000
566 #define TXGBE_INCVAL_10 0xC7F380
567 #define TXGBE_INCVAL_FPGA 0x800000
568 #define TXGBE_INCVAL_SHIFT_10GB 20
569 #define TXGBE_INCVAL_SHIFT_1GB 18
570 #define TXGBE_INCVAL_SHIFT_100 15
571 #define TXGBE_INCVAL_SHIFT_10 12
572 #define TXGBE_INCVAL_SHIFT_FPGA 17
574 #define TXGBE_CYCLECOUNTER_MASK 0xffffffffffffffffULL
576 /* store statistics names and its offset in stats structure */
577 struct rte_txgbe_xstats_name_off {
578 char name[RTE_ETH_XSTATS_NAME_SIZE];
582 const uint32_t *txgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev);
583 int txgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
584 struct rte_ether_addr *mc_addr_set,
585 uint32_t nb_mc_addr);
586 int txgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
587 struct rte_eth_rss_reta_entry64 *reta_conf,
589 int txgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
590 struct rte_eth_rss_reta_entry64 *reta_conf,
592 void txgbe_dev_setup_link_alarm_handler(void *param);
593 void txgbe_read_stats_registers(struct txgbe_hw *hw,
594 struct txgbe_hw_stats *hw_stats);
596 void txgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev);
597 void txgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev);
598 void txgbe_vlan_hw_strip_config(struct rte_eth_dev *dev);
599 void txgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
600 uint16_t queue, bool on);
601 void txgbe_config_vlan_strip_on_all_queues(struct rte_eth_dev *dev,
604 #endif /* _TXGBE_ETHDEV_H_ */