1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2015-2020 Beijing WangXun Technology Co., Ltd.
3 * Copyright(c) 2010-2017 Intel Corporation
6 #ifndef _TXGBE_ETHDEV_H_
7 #define _TXGBE_ETHDEV_H_
11 #include "base/txgbe.h"
12 #include "txgbe_ptypes.h"
13 #ifdef RTE_LIB_SECURITY
14 #include "txgbe_ipsec.h"
17 #include <rte_flow_driver.h>
19 #include <rte_ethdev.h>
20 #include <rte_ethdev_core.h>
22 #include <rte_hash_crc.h>
23 #include <rte_bus_pci.h>
24 #include <rte_tm_driver.h>
26 /* need update link, bit flag */
27 #define TXGBE_FLAG_NEED_LINK_UPDATE (uint32_t)(1 << 0)
28 #define TXGBE_FLAG_MAILBOX (uint32_t)(1 << 1)
29 #define TXGBE_FLAG_PHY_INTERRUPT (uint32_t)(1 << 2)
30 #define TXGBE_FLAG_MACSEC (uint32_t)(1 << 3)
31 #define TXGBE_FLAG_NEED_LINK_CONFIG (uint32_t)(1 << 4)
32 #define TXGBE_FLAG_NEED_AN_CONFIG (uint32_t)(1 << 5)
35 * Defines that were not part of txgbe_type.h as they are not used by the
38 #define TXGBE_VFTA_SIZE 128
39 #define TXGBE_VLAN_TAG_SIZE 4
40 #define TXGBE_HKEY_MAX_INDEX 10
41 /*Default value of Max Rx Queue*/
42 #define TXGBE_MAX_RX_QUEUE_NUM 128
43 #define TXGBE_VMDQ_DCB_NB_QUEUES TXGBE_MAX_RX_QUEUE_NUM
46 #define NBBY 8 /* number of bits in a byte */
48 #define TXGBE_HWSTRIP_BITMAP_SIZE \
49 (TXGBE_MAX_RX_QUEUE_NUM / (sizeof(uint32_t) * NBBY))
51 #define TXGBE_QUEUE_ITR_INTERVAL_DEFAULT 500 /* 500us */
53 #define TXGBE_MAX_QUEUE_NUM_PER_VF 8
55 #define TXGBE_5TUPLE_MAX_PRI 7
56 #define TXGBE_5TUPLE_MIN_PRI 1
59 /* The overhead from MTU to max frame size. */
60 #define TXGBE_ETH_OVERHEAD (RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN)
62 #define TXGBE_RSS_OFFLOAD_ALL ( \
64 RTE_ETH_RSS_NONFRAG_IPV4_TCP | \
65 RTE_ETH_RSS_NONFRAG_IPV4_UDP | \
67 RTE_ETH_RSS_NONFRAG_IPV6_TCP | \
68 RTE_ETH_RSS_NONFRAG_IPV6_UDP | \
69 RTE_ETH_RSS_IPV6_EX | \
70 RTE_ETH_RSS_IPV6_TCP_EX | \
71 RTE_ETH_RSS_IPV6_UDP_EX)
73 #define TXGBE_MISC_VEC_ID RTE_INTR_VEC_ZERO_OFFSET
74 #define TXGBE_RX_VEC_START RTE_INTR_VEC_RXTX_OFFSET
76 #define TXGBE_MAX_FDIR_FILTER_NUM (1024 * 32)
77 #define TXGBE_MAX_L2_TN_FILTER_NUM 128
80 * Information about the fdir mode.
82 struct txgbe_hw_fdir_mask {
83 uint16_t vlan_tci_mask;
84 uint32_t src_ipv4_mask;
85 uint32_t dst_ipv4_mask;
86 uint16_t src_ipv6_mask;
87 uint16_t dst_ipv6_mask;
88 uint16_t src_port_mask;
89 uint16_t dst_port_mask;
90 uint16_t flex_bytes_mask;
91 uint8_t mac_addr_byte_mask;
92 uint32_t tunnel_id_mask;
93 uint8_t tunnel_type_mask;
96 struct txgbe_fdir_filter {
97 TAILQ_ENTRY(txgbe_fdir_filter) entries;
98 struct txgbe_atr_input input; /* key of fdir filter*/
99 uint32_t fdirflags; /* drop or forward */
100 uint32_t fdirhash; /* hash value for fdir */
101 uint8_t queue; /* assigned rx queue */
104 /* list of fdir filters */
105 TAILQ_HEAD(txgbe_fdir_filter_list, txgbe_fdir_filter);
107 struct txgbe_fdir_rule {
108 struct txgbe_hw_fdir_mask mask;
109 struct txgbe_atr_input input; /* key of fdir filter */
110 bool b_spec; /* If TRUE, input, fdirflags, queue have meaning. */
111 bool b_mask; /* If TRUE, mask has meaning. */
112 enum rte_fdir_mode mode; /* IP, MAC VLAN, Tunnel */
113 uint32_t fdirflags; /* drop or forward */
114 uint32_t soft_id; /* an unique value for this rule */
115 uint8_t queue; /* assigned rx queue */
116 uint8_t flex_bytes_offset;
119 struct txgbe_hw_fdir_info {
120 struct txgbe_hw_fdir_mask mask;
121 uint8_t flex_bytes_offset;
130 struct txgbe_fdir_filter_list fdir_list; /* filter list*/
131 /* store the pointers of the filters, index is the hash value. */
132 struct txgbe_fdir_filter **hash_map;
133 struct rte_hash *hash_handle; /* cuckoo hash handler */
134 bool mask_added; /* If already got mask from consistent filter */
137 struct txgbe_rte_flow_rss_conf {
138 struct rte_flow_action_rss conf; /**< RSS parameters. */
139 uint8_t key[TXGBE_HKEY_MAX_INDEX * sizeof(uint32_t)]; /* Hash key. */
140 uint16_t queue[TXGBE_MAX_RX_QUEUE_NUM]; /**< Queues indices to use. */
143 /* structure for interrupt relative data */
144 struct txgbe_interrupt {
147 uint32_t mask_misc_orig; /* save mask during delayed handler */
149 uint64_t mask_orig; /* save mask during delayed handler */
152 #define TXGBE_NB_STAT_MAPPING 32
153 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
154 #define NB_QMAP_FIELDS_PER_QSM_REG 4
155 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
156 struct txgbe_stat_mappings {
157 uint32_t tqsm[TXGBE_NB_STAT_MAPPING];
158 uint32_t rqsm[TXGBE_NB_STAT_MAPPING];
162 uint32_t vfta[TXGBE_VFTA_SIZE];
165 struct txgbe_hwstrip {
166 uint32_t bitmap[TXGBE_HWSTRIP_BITMAP_SIZE];
170 * VF data which used by PF host only
172 #define TXGBE_MAX_VF_MC_ENTRIES 30
174 struct txgbe_uta_info {
175 uint8_t uc_filter_type;
177 uint32_t uta_shadow[TXGBE_MAX_UTA];
180 struct txgbe_vf_info {
181 uint8_t vf_mac_addresses[RTE_ETHER_ADDR_LEN];
182 uint16_t vf_mc_hashes[TXGBE_MAX_VF_MC_ENTRIES];
183 uint16_t num_vf_mc_hashes;
185 uint16_t tx_rate[TXGBE_MAX_QUEUE_NUM_PER_VF];
188 uint16_t switch_domain_id;
193 TAILQ_HEAD(txgbe_5tuple_filter_list, txgbe_5tuple_filter);
195 struct txgbe_5tuple_filter_info {
200 enum txgbe_5tuple_protocol proto; /* l4 protocol. */
201 uint8_t priority; /* seven levels (001b-111b), 111b is highest,
202 * used when more than one filter matches.
204 uint8_t dst_ip_mask:1, /* if mask is 1b, do not compare dst ip. */
205 src_ip_mask:1, /* if mask is 1b, do not compare src ip. */
206 dst_port_mask:1, /* if mask is 1b, do not compare dst port. */
207 src_port_mask:1, /* if mask is 1b, do not compare src port. */
208 proto_mask:1; /* if mask is 1b, do not compare protocol. */
211 /* 5tuple filter structure */
212 struct txgbe_5tuple_filter {
213 TAILQ_ENTRY(txgbe_5tuple_filter) entries;
214 uint16_t index; /* the index of 5tuple filter */
215 struct txgbe_5tuple_filter_info filter_info;
216 uint16_t queue; /* rx queue assigned to */
219 #define TXGBE_5TUPLE_ARRAY_SIZE \
220 (RTE_ALIGN(TXGBE_MAX_FTQF_FILTERS, (sizeof(uint32_t) * NBBY)) / \
221 (sizeof(uint32_t) * NBBY))
223 struct txgbe_ethertype_filter {
228 * If this filter is added by configuration,
229 * it should not be removed.
235 * Structure to store filters' info.
237 struct txgbe_filter_info {
238 uint8_t ethertype_mask; /* Bit mask for every used ethertype filter */
239 /* store used ethertype filters*/
240 struct txgbe_ethertype_filter ethertype_filters[TXGBE_ETF_ID_MAX];
241 /* Bit mask for every used 5tuple filter */
242 uint32_t fivetuple_mask[TXGBE_5TUPLE_ARRAY_SIZE];
243 struct txgbe_5tuple_filter_list fivetuple_list;
244 /* store the SYN filter info */
246 /* store the rss filter info */
247 struct txgbe_rte_flow_rss_conf rss_info;
250 struct txgbe_l2_tn_key {
251 enum rte_eth_tunnel_type l2_tn_type;
255 struct txgbe_l2_tn_filter {
256 TAILQ_ENTRY(txgbe_l2_tn_filter) entries;
257 struct txgbe_l2_tn_key key;
261 TAILQ_HEAD(txgbe_l2_tn_filter_list, txgbe_l2_tn_filter);
263 struct txgbe_l2_tn_info {
264 struct txgbe_l2_tn_filter_list l2_tn_list;
265 struct txgbe_l2_tn_filter **hash_map;
266 struct rte_hash *hash_handle;
267 bool e_tag_en; /* e-tag enabled */
268 bool e_tag_fwd_en; /* e-tag based forwarding enabled */
269 uint16_t e_tag_ether_type; /* ether type for e-tag */
273 enum rte_filter_type filter_type;
277 /* The configuration of bandwidth */
278 struct txgbe_bw_conf {
279 uint8_t tc_num; /* Number of TCs. */
282 /* Struct to store Traffic Manager shaper profile. */
283 struct txgbe_tm_shaper_profile {
284 TAILQ_ENTRY(txgbe_tm_shaper_profile) node;
285 uint32_t shaper_profile_id;
286 uint32_t reference_count;
287 struct rte_tm_shaper_params profile;
290 TAILQ_HEAD(txgbe_shaper_profile_list, txgbe_tm_shaper_profile);
292 /* node type of Traffic Manager */
293 enum txgbe_tm_node_type {
294 TXGBE_TM_NODE_TYPE_PORT,
295 TXGBE_TM_NODE_TYPE_TC,
296 TXGBE_TM_NODE_TYPE_QUEUE,
297 TXGBE_TM_NODE_TYPE_MAX,
300 /* Struct to store Traffic Manager node configuration. */
301 struct txgbe_tm_node {
302 TAILQ_ENTRY(txgbe_tm_node) node;
306 uint32_t reference_count;
308 struct txgbe_tm_node *parent;
309 struct txgbe_tm_shaper_profile *shaper_profile;
310 struct rte_tm_node_params params;
313 TAILQ_HEAD(txgbe_tm_node_list, txgbe_tm_node);
315 /* The configuration of Traffic Manager */
316 struct txgbe_tm_conf {
317 struct txgbe_shaper_profile_list shaper_profile_list;
318 struct txgbe_tm_node *root; /* root node - port */
319 struct txgbe_tm_node_list tc_list; /* node list for all the TCs */
320 struct txgbe_tm_node_list queue_list; /* node list for all the queues */
322 * The number of added TC nodes.
323 * It should be no more than the TC number of this port.
327 * The number of added queue nodes.
328 * It should be no more than the queue number of this port.
330 uint32_t nb_queue_node;
332 * This flag is used to check if APP can change the TM node
334 * When it's true, means the configuration is applied to HW,
335 * APP should not change the configuration.
336 * As we don't support on-the-fly configuration, when starting
337 * the port, APP should call the hierarchy_commit API to set this
338 * flag to true. When stopping the port, this flag should be set
345 * Structure to store private data for each driver instance (for each port).
347 struct txgbe_adapter {
349 struct txgbe_hw_stats stats;
350 struct txgbe_hw_fdir_info fdir;
351 struct txgbe_interrupt intr;
352 struct txgbe_stat_mappings stat_mappings;
353 struct txgbe_vfta shadow_vfta;
354 struct txgbe_hwstrip hwstrip;
355 struct txgbe_dcb_config dcb_config;
356 struct txgbe_vf_info *vfdata;
357 struct txgbe_uta_info uta_info;
358 struct txgbe_filter_info filter;
359 struct txgbe_l2_tn_info l2_tn;
360 struct txgbe_bw_conf bw_conf;
361 #ifdef RTE_LIB_SECURITY
362 struct txgbe_ipsec ipsec;
364 bool rx_bulk_alloc_allowed;
365 struct rte_timecounter systime_tc;
366 struct rte_timecounter rx_tstamp_tc;
367 struct rte_timecounter tx_tstamp_tc;
368 struct txgbe_tm_conf tm_conf;
370 /* For RSS reta table update */
371 uint8_t rss_reta_updated;
374 #define TXGBE_DEV_ADAPTER(dev) \
375 ((struct txgbe_adapter *)(dev)->data->dev_private)
377 #define TXGBE_DEV_HW(dev) \
378 (&((struct txgbe_adapter *)(dev)->data->dev_private)->hw)
380 #define TXGBE_DEV_STATS(dev) \
381 (&((struct txgbe_adapter *)(dev)->data->dev_private)->stats)
383 #define TXGBE_DEV_INTR(dev) \
384 (&((struct txgbe_adapter *)(dev)->data->dev_private)->intr)
386 #define TXGBE_DEV_FDIR(dev) \
387 (&((struct txgbe_adapter *)(dev)->data->dev_private)->fdir)
389 #define TXGBE_DEV_STAT_MAPPINGS(dev) \
390 (&((struct txgbe_adapter *)(dev)->data->dev_private)->stat_mappings)
392 #define TXGBE_DEV_VFTA(dev) \
393 (&((struct txgbe_adapter *)(dev)->data->dev_private)->shadow_vfta)
395 #define TXGBE_DEV_HWSTRIP(dev) \
396 (&((struct txgbe_adapter *)(dev)->data->dev_private)->hwstrip)
398 #define TXGBE_DEV_DCB_CONFIG(dev) \
399 (&((struct txgbe_adapter *)(dev)->data->dev_private)->dcb_config)
401 #define TXGBE_DEV_VFDATA(dev) \
402 (&((struct txgbe_adapter *)(dev)->data->dev_private)->vfdata)
404 #define TXGBE_DEV_MR_INFO(dev) \
405 (&((struct txgbe_adapter *)(dev)->data->dev_private)->mr_data)
407 #define TXGBE_DEV_UTA_INFO(dev) \
408 (&((struct txgbe_adapter *)(dev)->data->dev_private)->uta_info)
410 #define TXGBE_DEV_FILTER(dev) \
411 (&((struct txgbe_adapter *)(dev)->data->dev_private)->filter)
413 #define TXGBE_DEV_L2_TN(dev) \
414 (&((struct txgbe_adapter *)(dev)->data->dev_private)->l2_tn)
416 #define TXGBE_DEV_BW_CONF(dev) \
417 (&((struct txgbe_adapter *)(dev)->data->dev_private)->bw_conf)
419 #define TXGBE_DEV_TM_CONF(dev) \
420 (&((struct txgbe_adapter *)(dev)->data->dev_private)->tm_conf)
422 #define TXGBE_DEV_IPSEC(dev) \
423 (&((struct txgbe_adapter *)(dev)->data->dev_private)->ipsec)
426 * RX/TX function prototypes
428 void txgbe_dev_clear_queues(struct rte_eth_dev *dev);
430 void txgbe_dev_free_queues(struct rte_eth_dev *dev);
432 void txgbe_dev_rx_queue_release(struct rte_eth_dev *dev, uint16_t qid);
434 void txgbe_dev_tx_queue_release(struct rte_eth_dev *dev, uint16_t qid);
436 int txgbe_dev_rx_queue_setup(struct rte_eth_dev *dev, uint16_t rx_queue_id,
437 uint16_t nb_rx_desc, unsigned int socket_id,
438 const struct rte_eth_rxconf *rx_conf,
439 struct rte_mempool *mb_pool);
441 int txgbe_dev_tx_queue_setup(struct rte_eth_dev *dev, uint16_t tx_queue_id,
442 uint16_t nb_tx_desc, unsigned int socket_id,
443 const struct rte_eth_txconf *tx_conf);
445 uint32_t txgbe_dev_rx_queue_count(void *rx_queue);
447 int txgbe_dev_rx_descriptor_status(void *rx_queue, uint16_t offset);
448 int txgbe_dev_tx_descriptor_status(void *tx_queue, uint16_t offset);
450 int txgbe_dev_rx_init(struct rte_eth_dev *dev);
452 void txgbe_dev_tx_init(struct rte_eth_dev *dev);
454 int txgbe_dev_rxtx_start(struct rte_eth_dev *dev);
456 void txgbe_dev_save_rx_queue(struct txgbe_hw *hw, uint16_t rx_queue_id);
457 void txgbe_dev_store_rx_queue(struct txgbe_hw *hw, uint16_t rx_queue_id);
458 void txgbe_dev_save_tx_queue(struct txgbe_hw *hw, uint16_t tx_queue_id);
459 void txgbe_dev_store_tx_queue(struct txgbe_hw *hw, uint16_t tx_queue_id);
461 int txgbe_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id);
463 int txgbe_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id);
465 int txgbe_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id);
467 int txgbe_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id);
469 void txgbe_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
470 struct rte_eth_rxq_info *qinfo);
472 void txgbe_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
473 struct rte_eth_txq_info *qinfo);
475 int txgbevf_dev_rx_init(struct rte_eth_dev *dev);
477 void txgbevf_dev_tx_init(struct rte_eth_dev *dev);
479 void txgbevf_dev_rxtx_start(struct rte_eth_dev *dev);
481 uint16_t txgbe_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
484 uint16_t txgbe_recv_pkts_bulk_alloc(void *rx_queue, struct rte_mbuf **rx_pkts,
487 uint16_t txgbe_recv_pkts_lro_single_alloc(void *rx_queue,
488 struct rte_mbuf **rx_pkts, uint16_t nb_pkts);
489 uint16_t txgbe_recv_pkts_lro_bulk_alloc(void *rx_queue,
490 struct rte_mbuf **rx_pkts, uint16_t nb_pkts);
492 uint16_t txgbe_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
495 uint16_t txgbe_xmit_pkts_simple(void *tx_queue, struct rte_mbuf **tx_pkts,
498 uint16_t txgbe_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
501 int txgbe_dev_rss_hash_update(struct rte_eth_dev *dev,
502 struct rte_eth_rss_conf *rss_conf);
504 int txgbe_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
505 struct rte_eth_rss_conf *rss_conf);
507 bool txgbe_rss_update_sp(enum txgbe_mac_type mac_type);
509 int txgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
510 struct rte_eth_ntuple_filter *filter,
512 int txgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
513 struct rte_eth_ethertype_filter *filter,
515 int txgbe_syn_filter_set(struct rte_eth_dev *dev,
516 struct rte_eth_syn_filter *filter,
520 * l2 tunnel configuration.
522 struct txgbe_l2_tunnel_conf {
523 enum rte_eth_tunnel_type l2_tunnel_type;
524 uint16_t ether_type; /* ether type in l2 header */
525 uint32_t tunnel_id; /* port tag id for e-tag */
526 uint16_t vf_id; /* VF id for tag insertion */
527 uint32_t pool; /* destination pool for tag based forwarding */
531 txgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev,
532 struct txgbe_l2_tunnel_conf *l2_tunnel,
535 txgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev,
536 struct txgbe_l2_tunnel_conf *l2_tunnel);
537 void txgbe_filterlist_init(void);
538 void txgbe_filterlist_flush(void);
540 void txgbe_set_ivar_map(struct txgbe_hw *hw, int8_t direction,
541 uint8_t queue, uint8_t msix_vector);
544 * Flow director function prototypes
546 int txgbe_fdir_configure(struct rte_eth_dev *dev);
547 int txgbe_fdir_set_input_mask(struct rte_eth_dev *dev);
548 int txgbe_fdir_set_flexbytes_offset(struct rte_eth_dev *dev,
550 int txgbe_fdir_filter_program(struct rte_eth_dev *dev,
551 struct txgbe_fdir_rule *rule,
552 bool del, bool update);
554 void txgbe_configure_pb(struct rte_eth_dev *dev);
555 void txgbe_configure_port(struct rte_eth_dev *dev);
556 void txgbe_configure_dcb(struct rte_eth_dev *dev);
559 txgbe_dev_link_update_share(struct rte_eth_dev *dev,
560 int wait_to_complete);
561 int txgbe_pf_host_init(struct rte_eth_dev *eth_dev);
563 void txgbe_pf_host_uninit(struct rte_eth_dev *eth_dev);
565 void txgbe_pf_mbx_process(struct rte_eth_dev *eth_dev);
567 int txgbe_pf_host_configure(struct rte_eth_dev *eth_dev);
569 uint32_t txgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val);
571 void txgbe_fdir_filter_restore(struct rte_eth_dev *dev);
572 int txgbe_clear_all_fdir_filter(struct rte_eth_dev *dev);
574 extern const struct rte_flow_ops txgbe_flow_ops;
576 void txgbe_clear_all_ethertype_filter(struct rte_eth_dev *dev);
577 void txgbe_clear_all_ntuple_filter(struct rte_eth_dev *dev);
578 void txgbe_clear_syn_filter(struct rte_eth_dev *dev);
579 int txgbe_clear_all_l2_tn_filter(struct rte_eth_dev *dev);
581 int txgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
582 uint16_t tx_rate, uint64_t q_msk);
583 int txgbe_tm_ops_get(struct rte_eth_dev *dev, void *ops);
584 void txgbe_tm_conf_init(struct rte_eth_dev *dev);
585 void txgbe_tm_conf_uninit(struct rte_eth_dev *dev);
586 int txgbe_set_queue_rate_limit(struct rte_eth_dev *dev, uint16_t queue_idx,
588 int txgbe_rss_conf_init(struct txgbe_rte_flow_rss_conf *out,
589 const struct rte_flow_action_rss *in);
590 int txgbe_action_rss_same(const struct rte_flow_action_rss *comp,
591 const struct rte_flow_action_rss *with);
592 int txgbe_config_rss_filter(struct rte_eth_dev *dev,
593 struct txgbe_rte_flow_rss_conf *conf, bool add);
596 txgbe_ethertype_filter_lookup(struct txgbe_filter_info *filter_info,
601 for (i = 0; i < TXGBE_ETF_ID_MAX; i++) {
602 if (filter_info->ethertype_filters[i].ethertype == ethertype &&
603 (filter_info->ethertype_mask & (1 << i)))
610 txgbe_ethertype_filter_insert(struct txgbe_filter_info *filter_info,
611 struct txgbe_ethertype_filter *ethertype_filter)
615 for (i = 0; i < TXGBE_ETF_ID_MAX; i++) {
616 if (filter_info->ethertype_mask & (1 << i))
619 filter_info->ethertype_mask |= 1 << i;
620 filter_info->ethertype_filters[i].ethertype =
621 ethertype_filter->ethertype;
622 filter_info->ethertype_filters[i].etqf =
623 ethertype_filter->etqf;
624 filter_info->ethertype_filters[i].etqs =
625 ethertype_filter->etqs;
626 filter_info->ethertype_filters[i].conf =
627 ethertype_filter->conf;
630 return (i < TXGBE_ETF_ID_MAX ? i : -1);
634 txgbe_ethertype_filter_remove(struct txgbe_filter_info *filter_info,
637 if (idx >= TXGBE_ETF_ID_MAX)
639 filter_info->ethertype_mask &= ~(1 << idx);
640 filter_info->ethertype_filters[idx].ethertype = 0;
641 filter_info->ethertype_filters[idx].etqf = 0;
642 filter_info->ethertype_filters[idx].etqs = 0;
643 filter_info->ethertype_filters[idx].etqs = FALSE;
647 #ifdef RTE_LIB_SECURITY
648 int txgbe_ipsec_ctx_create(struct rte_eth_dev *dev);
651 /* High threshold controlling when to start sending XOFF frames. */
652 #define TXGBE_FC_XOFF_HITH 128 /*KB*/
653 /* Low threshold controlling when to start sending XON frames. */
654 #define TXGBE_FC_XON_LOTH 64 /*KB*/
656 /* Timer value included in XOFF frames. */
657 #define TXGBE_FC_PAUSE_TIME 0x680
659 #define TXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
660 #define TXGBE_LINK_UP_CHECK_TIMEOUT 1000 /* ms */
661 #define TXGBE_VMDQ_NUM_UC_MAC 4096 /* Maximum nb. of UC MAC addr. */
664 * Default values for RX/TX configuration
666 #define TXGBE_DEFAULT_RX_FREE_THRESH 32
667 #define TXGBE_DEFAULT_RX_PTHRESH 8
668 #define TXGBE_DEFAULT_RX_HTHRESH 8
669 #define TXGBE_DEFAULT_RX_WTHRESH 0
671 #define TXGBE_DEFAULT_TX_FREE_THRESH 32
672 #define TXGBE_DEFAULT_TX_PTHRESH 32
673 #define TXGBE_DEFAULT_TX_HTHRESH 0
674 #define TXGBE_DEFAULT_TX_WTHRESH 0
676 /* Additional timesync values. */
677 #define NSEC_PER_SEC 1000000000L
678 #define TXGBE_INCVAL_10GB 0xCCCCCC
679 #define TXGBE_INCVAL_1GB 0x800000
680 #define TXGBE_INCVAL_100 0xA00000
681 #define TXGBE_INCVAL_10 0xC7F380
682 #define TXGBE_INCVAL_FPGA 0x800000
683 #define TXGBE_INCVAL_SHIFT_10GB 20
684 #define TXGBE_INCVAL_SHIFT_1GB 18
685 #define TXGBE_INCVAL_SHIFT_100 15
686 #define TXGBE_INCVAL_SHIFT_10 12
687 #define TXGBE_INCVAL_SHIFT_FPGA 17
689 #define TXGBE_CYCLECOUNTER_MASK 0xffffffffffffffffULL
691 /* store statistics names and its offset in stats structure */
692 struct rte_txgbe_xstats_name_off {
693 char name[RTE_ETH_XSTATS_NAME_SIZE];
697 const uint32_t *txgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev);
698 int txgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
699 struct rte_ether_addr *mc_addr_set,
700 uint32_t nb_mc_addr);
701 int txgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
702 struct rte_eth_rss_reta_entry64 *reta_conf,
704 int txgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
705 struct rte_eth_rss_reta_entry64 *reta_conf,
707 void txgbe_dev_setup_link_alarm_handler(void *param);
708 void txgbe_read_stats_registers(struct txgbe_hw *hw,
709 struct txgbe_hw_stats *hw_stats);
711 void txgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev);
712 void txgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev);
713 void txgbe_vlan_hw_strip_config(struct rte_eth_dev *dev);
714 void txgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
715 uint16_t queue, bool on);
716 void txgbe_config_vlan_strip_on_all_queues(struct rte_eth_dev *dev,
719 #endif /* _TXGBE_ETHDEV_H_ */