1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2015-2020
5 #ifndef _TXGBE_ETHDEV_H_
6 #define _TXGBE_ETHDEV_H_
10 #include "base/txgbe.h"
11 #include "txgbe_ptypes.h"
14 /* need update link, bit flag */
15 #define TXGBE_FLAG_NEED_LINK_UPDATE (uint32_t)(1 << 0)
16 #define TXGBE_FLAG_MAILBOX (uint32_t)(1 << 1)
17 #define TXGBE_FLAG_PHY_INTERRUPT (uint32_t)(1 << 2)
18 #define TXGBE_FLAG_MACSEC (uint32_t)(1 << 3)
19 #define TXGBE_FLAG_NEED_LINK_CONFIG (uint32_t)(1 << 4)
22 * Defines that were not part of txgbe_type.h as they are not used by the
25 #define TXGBE_VFTA_SIZE 128
26 #define TXGBE_VLAN_TAG_SIZE 4
27 #define TXGBE_HKEY_MAX_INDEX 10
28 /*Default value of Max Rx Queue*/
29 #define TXGBE_MAX_RX_QUEUE_NUM 128
30 #define TXGBE_VMDQ_DCB_NB_QUEUES TXGBE_MAX_RX_QUEUE_NUM
33 #define NBBY 8 /* number of bits in a byte */
35 #define TXGBE_HWSTRIP_BITMAP_SIZE \
36 (TXGBE_MAX_RX_QUEUE_NUM / (sizeof(uint32_t) * NBBY))
38 #define TXGBE_QUEUE_ITR_INTERVAL_DEFAULT 500 /* 500us */
40 #define TXGBE_MAX_QUEUE_NUM_PER_VF 8
42 #define TXGBE_RSS_OFFLOAD_ALL ( \
44 ETH_RSS_NONFRAG_IPV4_TCP | \
45 ETH_RSS_NONFRAG_IPV4_UDP | \
47 ETH_RSS_NONFRAG_IPV6_TCP | \
48 ETH_RSS_NONFRAG_IPV6_UDP | \
50 ETH_RSS_IPV6_TCP_EX | \
53 #define TXGBE_MISC_VEC_ID RTE_INTR_VEC_ZERO_OFFSET
54 #define TXGBE_RX_VEC_START RTE_INTR_VEC_RXTX_OFFSET
56 /* structure for interrupt relative data */
57 struct txgbe_interrupt {
60 /* to save original mask during delayed handler */
61 uint32_t mask_misc_orig;
65 #define TXGBE_NB_STAT_MAPPING 32
66 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
67 #define NB_QMAP_FIELDS_PER_QSM_REG 4
68 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
69 struct txgbe_stat_mappings {
70 uint32_t tqsm[TXGBE_NB_STAT_MAPPING];
71 uint32_t rqsm[TXGBE_NB_STAT_MAPPING];
75 uint32_t vfta[TXGBE_VFTA_SIZE];
78 struct txgbe_hwstrip {
79 uint32_t bitmap[TXGBE_HWSTRIP_BITMAP_SIZE];
83 * VF data which used by PF host only
85 #define TXGBE_MAX_VF_MC_ENTRIES 30
87 struct txgbe_uta_info {
88 uint8_t uc_filter_type;
90 uint32_t uta_shadow[TXGBE_MAX_UTA];
93 #define TXGBE_MAX_MIRROR_RULES 4 /* Maximum nb. of mirror rules. */
95 struct txgbe_mirror_info {
96 struct rte_eth_mirror_conf mr_conf[TXGBE_MAX_MIRROR_RULES];
97 /* store PF mirror rules configuration */
100 struct txgbe_vf_info {
101 uint8_t vf_mac_addresses[RTE_ETHER_ADDR_LEN];
102 uint16_t vf_mc_hashes[TXGBE_MAX_VF_MC_ENTRIES];
103 uint16_t num_vf_mc_hashes;
105 uint16_t tx_rate[TXGBE_MAX_QUEUE_NUM_PER_VF];
108 uint16_t switch_domain_id;
113 struct txgbe_ethertype_filter {
118 * If this filter is added by configuration,
119 * it should not be removed.
125 * Structure to store filters' info.
127 struct txgbe_filter_info {
128 uint8_t ethertype_mask; /* Bit mask for every used ethertype filter */
129 /* store used ethertype filters*/
130 struct txgbe_ethertype_filter ethertype_filters[TXGBE_ETF_ID_MAX];
133 /* The configuration of bandwidth */
134 struct txgbe_bw_conf {
135 uint8_t tc_num; /* Number of TCs. */
139 * Structure to store private data for each driver instance (for each port).
141 struct txgbe_adapter {
143 struct txgbe_hw_stats stats;
144 struct txgbe_interrupt intr;
145 struct txgbe_stat_mappings stat_mappings;
146 struct txgbe_vfta shadow_vfta;
147 struct txgbe_hwstrip hwstrip;
148 struct txgbe_dcb_config dcb_config;
149 struct txgbe_mirror_info mr_data;
150 struct txgbe_vf_info *vfdata;
151 struct txgbe_uta_info uta_info;
152 struct txgbe_filter_info filter;
153 struct txgbe_bw_conf bw_conf;
154 bool rx_bulk_alloc_allowed;
155 struct rte_timecounter systime_tc;
156 struct rte_timecounter rx_tstamp_tc;
157 struct rte_timecounter tx_tstamp_tc;
159 /* For RSS reta table update */
160 uint8_t rss_reta_updated;
163 #define TXGBE_DEV_ADAPTER(dev) \
164 ((struct txgbe_adapter *)(dev)->data->dev_private)
166 #define TXGBE_DEV_HW(dev) \
167 (&((struct txgbe_adapter *)(dev)->data->dev_private)->hw)
169 #define TXGBE_DEV_STATS(dev) \
170 (&((struct txgbe_adapter *)(dev)->data->dev_private)->stats)
172 #define TXGBE_DEV_INTR(dev) \
173 (&((struct txgbe_adapter *)(dev)->data->dev_private)->intr)
175 #define TXGBE_DEV_STAT_MAPPINGS(dev) \
176 (&((struct txgbe_adapter *)(dev)->data->dev_private)->stat_mappings)
178 #define TXGBE_DEV_VFTA(dev) \
179 (&((struct txgbe_adapter *)(dev)->data->dev_private)->shadow_vfta)
181 #define TXGBE_DEV_HWSTRIP(dev) \
182 (&((struct txgbe_adapter *)(dev)->data->dev_private)->hwstrip)
184 #define TXGBE_DEV_DCB_CONFIG(dev) \
185 (&((struct txgbe_adapter *)(dev)->data->dev_private)->dcb_config)
187 #define TXGBE_DEV_VFDATA(dev) \
188 (&((struct txgbe_adapter *)(dev)->data->dev_private)->vfdata)
190 #define TXGBE_DEV_MR_INFO(dev) \
191 (&((struct txgbe_adapter *)(dev)->data->dev_private)->mr_data)
193 #define TXGBE_DEV_UTA_INFO(dev) \
194 (&((struct txgbe_adapter *)(dev)->data->dev_private)->uta_info)
196 #define TXGBE_DEV_FILTER(dev) \
197 (&((struct txgbe_adapter *)(dev)->data->dev_private)->filter)
198 #define TXGBE_DEV_BW_CONF(dev) \
199 (&((struct txgbe_adapter *)(dev)->data->dev_private)->bw_conf)
203 * RX/TX function prototypes
205 void txgbe_dev_clear_queues(struct rte_eth_dev *dev);
207 void txgbe_dev_free_queues(struct rte_eth_dev *dev);
209 void txgbe_dev_rx_queue_release(void *rxq);
211 void txgbe_dev_tx_queue_release(void *txq);
213 int txgbe_dev_rx_queue_setup(struct rte_eth_dev *dev, uint16_t rx_queue_id,
214 uint16_t nb_rx_desc, unsigned int socket_id,
215 const struct rte_eth_rxconf *rx_conf,
216 struct rte_mempool *mb_pool);
218 int txgbe_dev_tx_queue_setup(struct rte_eth_dev *dev, uint16_t tx_queue_id,
219 uint16_t nb_tx_desc, unsigned int socket_id,
220 const struct rte_eth_txconf *tx_conf);
222 int txgbe_dev_rx_init(struct rte_eth_dev *dev);
224 void txgbe_dev_tx_init(struct rte_eth_dev *dev);
226 int txgbe_dev_rxtx_start(struct rte_eth_dev *dev);
228 void txgbe_dev_save_rx_queue(struct txgbe_hw *hw, uint16_t rx_queue_id);
229 void txgbe_dev_store_rx_queue(struct txgbe_hw *hw, uint16_t rx_queue_id);
230 void txgbe_dev_save_tx_queue(struct txgbe_hw *hw, uint16_t tx_queue_id);
231 void txgbe_dev_store_tx_queue(struct txgbe_hw *hw, uint16_t tx_queue_id);
233 int txgbe_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id);
235 int txgbe_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id);
237 int txgbe_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id);
239 int txgbe_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id);
241 void txgbe_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
242 struct rte_eth_rxq_info *qinfo);
244 void txgbe_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
245 struct rte_eth_txq_info *qinfo);
247 uint16_t txgbe_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
250 uint16_t txgbe_recv_pkts_bulk_alloc(void *rx_queue, struct rte_mbuf **rx_pkts,
253 uint16_t txgbe_recv_pkts_lro_single_alloc(void *rx_queue,
254 struct rte_mbuf **rx_pkts, uint16_t nb_pkts);
255 uint16_t txgbe_recv_pkts_lro_bulk_alloc(void *rx_queue,
256 struct rte_mbuf **rx_pkts, uint16_t nb_pkts);
258 uint16_t txgbe_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
261 uint16_t txgbe_xmit_pkts_simple(void *tx_queue, struct rte_mbuf **tx_pkts,
264 uint16_t txgbe_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
267 int txgbe_dev_rss_hash_update(struct rte_eth_dev *dev,
268 struct rte_eth_rss_conf *rss_conf);
270 int txgbe_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
271 struct rte_eth_rss_conf *rss_conf);
273 bool txgbe_rss_update_sp(enum txgbe_mac_type mac_type);
275 void txgbe_set_ivar_map(struct txgbe_hw *hw, int8_t direction,
276 uint8_t queue, uint8_t msix_vector);
278 void txgbe_configure_pb(struct rte_eth_dev *dev);
279 void txgbe_configure_port(struct rte_eth_dev *dev);
280 void txgbe_configure_dcb(struct rte_eth_dev *dev);
283 txgbe_dev_link_update_share(struct rte_eth_dev *dev,
284 int wait_to_complete);
285 void txgbe_pf_host_init(struct rte_eth_dev *eth_dev);
287 void txgbe_pf_host_uninit(struct rte_eth_dev *eth_dev);
289 void txgbe_pf_mbx_process(struct rte_eth_dev *eth_dev);
291 int txgbe_pf_host_configure(struct rte_eth_dev *eth_dev);
293 uint32_t txgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val);
295 int txgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
296 uint16_t tx_rate, uint64_t q_msk);
297 int txgbe_set_queue_rate_limit(struct rte_eth_dev *dev, uint16_t queue_idx,
300 txgbe_ethertype_filter_lookup(struct txgbe_filter_info *filter_info,
305 for (i = 0; i < TXGBE_ETF_ID_MAX; i++) {
306 if (filter_info->ethertype_filters[i].ethertype == ethertype &&
307 (filter_info->ethertype_mask & (1 << i)))
314 txgbe_ethertype_filter_insert(struct txgbe_filter_info *filter_info,
315 struct txgbe_ethertype_filter *ethertype_filter)
319 for (i = 0; i < TXGBE_ETF_ID_MAX; i++) {
320 if (filter_info->ethertype_mask & (1 << i))
323 filter_info->ethertype_mask |= 1 << i;
324 filter_info->ethertype_filters[i].ethertype =
325 ethertype_filter->ethertype;
326 filter_info->ethertype_filters[i].etqf =
327 ethertype_filter->etqf;
328 filter_info->ethertype_filters[i].etqs =
329 ethertype_filter->etqs;
330 filter_info->ethertype_filters[i].conf =
331 ethertype_filter->conf;
334 return (i < TXGBE_ETF_ID_MAX ? i : -1);
337 /* High threshold controlling when to start sending XOFF frames. */
338 #define TXGBE_FC_XOFF_HITH 128 /*KB*/
339 /* Low threshold controlling when to start sending XON frames. */
340 #define TXGBE_FC_XON_LOTH 64 /*KB*/
342 /* Timer value included in XOFF frames. */
343 #define TXGBE_FC_PAUSE_TIME 0x680
345 #define TXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
346 #define TXGBE_LINK_UP_CHECK_TIMEOUT 1000 /* ms */
347 #define TXGBE_VMDQ_NUM_UC_MAC 4096 /* Maximum nb. of UC MAC addr. */
350 * Default values for RX/TX configuration
352 #define TXGBE_DEFAULT_RX_FREE_THRESH 32
353 #define TXGBE_DEFAULT_RX_PTHRESH 8
354 #define TXGBE_DEFAULT_RX_HTHRESH 8
355 #define TXGBE_DEFAULT_RX_WTHRESH 0
357 #define TXGBE_DEFAULT_TX_FREE_THRESH 32
358 #define TXGBE_DEFAULT_TX_PTHRESH 32
359 #define TXGBE_DEFAULT_TX_HTHRESH 0
360 #define TXGBE_DEFAULT_TX_WTHRESH 0
362 /* Additional timesync values. */
363 #define NSEC_PER_SEC 1000000000L
364 #define TXGBE_INCVAL_10GB 0xCCCCCC
365 #define TXGBE_INCVAL_1GB 0x800000
366 #define TXGBE_INCVAL_100 0xA00000
367 #define TXGBE_INCVAL_10 0xC7F380
368 #define TXGBE_INCVAL_FPGA 0x800000
369 #define TXGBE_INCVAL_SHIFT_10GB 20
370 #define TXGBE_INCVAL_SHIFT_1GB 18
371 #define TXGBE_INCVAL_SHIFT_100 15
372 #define TXGBE_INCVAL_SHIFT_10 12
373 #define TXGBE_INCVAL_SHIFT_FPGA 17
375 #define TXGBE_CYCLECOUNTER_MASK 0xffffffffffffffffULL
377 /* store statistics names and its offset in stats structure */
378 struct rte_txgbe_xstats_name_off {
379 char name[RTE_ETH_XSTATS_NAME_SIZE];
383 const uint32_t *txgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev);
384 int txgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
385 struct rte_ether_addr *mc_addr_set,
386 uint32_t nb_mc_addr);
387 int txgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
388 struct rte_eth_rss_reta_entry64 *reta_conf,
390 int txgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
391 struct rte_eth_rss_reta_entry64 *reta_conf,
393 void txgbe_dev_setup_link_alarm_handler(void *param);
394 void txgbe_read_stats_registers(struct txgbe_hw *hw,
395 struct txgbe_hw_stats *hw_stats);
397 void txgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev);
398 void txgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev);
399 void txgbe_vlan_hw_strip_config(struct rte_eth_dev *dev);
400 void txgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
401 uint16_t queue, bool on);
402 void txgbe_config_vlan_strip_on_all_queues(struct rte_eth_dev *dev,
405 #endif /* _TXGBE_ETHDEV_H_ */